system
stringclasses 7
values | input
stringlengths 10
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You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#define M 10
// RED = 0, BLACK = 1
enum nodeColor {
RED,
BLACK
};
enum result {
Failure,
Success,
FirstInsert
};
enum caseFlag {
NOOP,
DID_CASE1,
DID_CASE3
};
struct par_rbNode {
int key, color;
struct par_rbNode *left, *right, *parent;
};
// /*Function prototypes */
__device__ void createNIL();
__device__ struct par_rbNode * createNode(int);
__device__ void createTree();
__device__ struct par_rbNode * Traverse(int);
__device__ enum result PlaceNode(struct par_rbNode *, struct par_rbNode *);
__device__ void Insert_Rebalance(struct par_rbNode *);
__device__ bool Update_Rotation(struct par_rbNode *, enum caseFlag *);
__device__ void Left_Rotate(struct par_rbNode *);
__device__ void Right_Rotate(struct par_rbNode *);
__device__ struct par_rbNode *nodes;
__device__ struct par_rbNode *root;
__device__ struct par_rbNode *NIL;
__device__ struct par_rbNode *rtParent;
__device__ struct par_rbNode *rtSibling; // U might feel this is unncessary, but it will be used
__device__ int nodeIndex = 0;
__device__ void createNIL(){
NIL = &nodes[0];
NIL->color = BLACK;
NIL->key = -1;
NIL->left = NIL->right = NIL->parent = NIL;
printf("NIL created\n");
}
__device__ struct par_rbNode * createNode(int key){
atomicAdd(&nodeIndex,1);
nodes[nodeIndex].key = key;
nodes[nodeIndex].left = nodes[nodeIndex].right = nodes[nodeIndex].parent = NIL;
return &nodes[nodeIndex]; // Even if this thread pauses it will eventually return the correct pointer
}
__device__ void createTree(){
rtParent = createNode(-1);
rtSibling = createNode(-1);
root = NIL;
rtParent->parent = NIL;
rtSibling->parent = rtParent;
rtSibling->right = NIL;
rtSibling->left = NIL;
rtParent->left = root;
rtParent->right = rtSibling;
rtParent->color = BLACK;
rtSibling->color = BLACK;
NIL->parent = rtParent;
printf("Tree Created \n");
printf("\n");
}
__device__ struct par_rbNode * Traverse(int d){
struct par_rbNode *x;
x = root;
if(x == NIL){
printf("Empty Tree\n");
return NIL;
}
while(x != NIL){
if(x->key == d){
printf("Found it!\n");
return x;
}else if(x->key > d){
x = x->left;
}else{
x = x->right;
}
}
printf("Couldn't find %d in this tree\n",d);
return NIL;
}
__device__ void Left_Rotate(struct par_rbNode *lptr){
struct par_rbNode *y;
y = lptr->right;
lptr->right = y->left;
if(y->left != NIL)
y->left->parent = lptr;
if(y!=NIL)
y->parent = lptr->parent;
if(lptr->parent == NIL){
root = y;
}else if(lptr == lptr->parent->left)
lptr->parent->left = y;
else
lptr->parent->right = y;
y->left = lptr;
if(lptr != NIL)
lptr->parent = y;
}
__device__ void Right_Rotate(struct par_rbNode *rptr){
struct par_rbNode *y;
y = rptr->left;
rptr->left = y->right;
if(y->right != NIL)
y->right->parent = rptr;
if(y!=NIL)
y->parent = rptr->parent;
if(rptr->parent == NIL){
root = y;
}else if(rptr == rptr->parent->right)
rptr->parent->right = y;
else
rptr->parent->left = y;
y->right = rptr;
if(rptr != NIL)
rptr->parent = y;
}
__device__ void Insert_fixup(struct par_rbNode *x){
struct par_rbNode *u;
while(x->parent->color == RED){
if(x->parent == x->parent->parent->left){
u = x->parent->parent->right;
if(u->color == RED){//CASE 1
x->parent->color = BLACK;
u->color = BLACK;
x->parent->parent->color = RED;
x = x->parent->parent;
}else if(x == x->parent->right){//CASE 2
x = x->parent;
Left_Rotate(x);
x->parent->color = BLACK;
x->parent->parent->color = RED;
Right_Rotate(x->parent->parent);
}else if(x == x->parent->left){
x->parent->color = BLACK;
x->parent->parent->color = RED;
Right_Rotate(x->parent->parent);
} //CASE 3
}else{
u = x->parent->parent->left;
if(u->color == RED){//CASE 1
x->parent->color = BLACK;
u->color = BLACK;
x->parent->parent->color = RED;
x = x->parent->parent;
}else if(x == x->parent->left){//CASE 2
x = x->parent;
Right_Rotate(x);
x->parent->color = BLACK;
x->parent->parent->color = RED;
Left_Rotate(x->parent->parent);
}else if(x == x->parent->right){
x->parent->color = BLACK;
x->parent->parent->color = RED;
Left_Rotate(x->parent->parent);
} //CASE 3
}
}
root->color = BLACK;
}
__device__ void Insert(int d){
if(root == NIL){
root = createNode(d);
root->color = BLACK;
return;
}
struct par_rbNode *x,*z;
x = root;
while(x != NIL){
z = x;
if(d == x->key){ // Find if the node with this value is already there or not
printf("Duplicate Nodes are not allowed\n");
return;
}
if(d < x->key)
x = x->left;
else
x = x->right;
}//end while
x=createNode(d);
x->parent = z;
if(x->key < z->key) //Check if y is the left child of z or not
z->left = x;
else
z->right = x;
//NEW NODE IS INSERTED, NOW FIX THE RB TREE
Insert_fixup(x);
// printInorder(root);
}
//Functions for printing the tree
__device__ void printPreorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
/* then recur on left child */
printPreorder(node->left);
/* now recur on right child */
printPreorder(node->right);
}
__device__ void printInorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first recur on left child */
printInorder(node->left);
/* then print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
/* now recur on right child */
printInorder(node->right);
}
__device__ void printPostorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first recur on left child */
printPostorder(node->left);
/* then recur on right child */
printPostorder(node->right);
/* now print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
}
__global__ void RBT(struct par_rbNode *d_nodes) {
printf("Starting the Tree\n");
nodes = d_nodes; // Make it a global variable
createNIL();
createTree();
for(int i=0;i<7;i++){
Insert(i);
}
printf("PreOrder: ");
printPreorder(root);
printf("\n");
printf("\n");
printf("InOrder: ");
printInorder(root);
printf("\n");
printf("\n");
printf("PostOrder: ");
printPostorder(root);
printf("\n");
printf("\n");
printf("Done\n");
//return to main
}
int main() {
struct par_rbNode h_nodes[M];
struct par_rbNode *d_nodes;
float time;
// 1. Allocate device array.
cudaMalloc(&d_nodes, M * sizeof(struct par_rbNode));
for(int i=0;i<M;i++){
h_nodes[i].color = RED;
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// 2. Copy array contents from host to device.
cudaMemcpy(d_nodes, h_nodes, M * sizeof(struct par_rbNode), cudaMemcpyHostToDevice);
printf("Kernel Launched\n");
cudaEventRecord(start, 0);
RBT<<<1,1>>>(d_nodes);
cudaMemcpy(h_nodes, d_nodes, M * sizeof(struct par_rbNode), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
printf("Came back\n");
cudaEventElapsedTime(&time, start, stop);
printf ("Time for the kernel: %f ms\n", time);
return 0;
}
|
.file "tmpxft_0009ecb6_00000000-6_serial_rbt_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9createNILv
.type _Z9createNILv, @function
_Z9createNILv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9createNILv, .-_Z9createNILv
.globl _Z10createNodei
.type _Z10createNodei, @function
_Z10createNodei:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10createNodei, .-_Z10createNodei
.globl _Z10createTreev
.type _Z10createTreev, @function
_Z10createTreev:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10createTreev, .-_Z10createTreev
.globl _Z8Traversei
.type _Z8Traversei, @function
_Z8Traversei:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z8Traversei, .-_Z8Traversei
.globl _Z11Left_RotateP10par_rbNode
.type _Z11Left_RotateP10par_rbNode, @function
_Z11Left_RotateP10par_rbNode:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z11Left_RotateP10par_rbNode, .-_Z11Left_RotateP10par_rbNode
.globl _Z12Right_RotateP10par_rbNode
.type _Z12Right_RotateP10par_rbNode, @function
_Z12Right_RotateP10par_rbNode:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z12Right_RotateP10par_rbNode, .-_Z12Right_RotateP10par_rbNode
.globl _Z12Insert_fixupP10par_rbNode
.type _Z12Insert_fixupP10par_rbNode, @function
_Z12Insert_fixupP10par_rbNode:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z12Insert_fixupP10par_rbNode, .-_Z12Insert_fixupP10par_rbNode
.globl _Z6Inserti
.type _Z6Inserti, @function
_Z6Inserti:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z6Inserti, .-_Z6Inserti
.globl _Z13printPreorderP10par_rbNode
.type _Z13printPreorderP10par_rbNode, @function
_Z13printPreorderP10par_rbNode:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z13printPreorderP10par_rbNode, .-_Z13printPreorderP10par_rbNode
.globl _Z12printInorderP10par_rbNode
.type _Z12printInorderP10par_rbNode, @function
_Z12printInorderP10par_rbNode:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z12printInorderP10par_rbNode, .-_Z12printInorderP10par_rbNode
.globl _Z14printPostorderP10par_rbNode
.type _Z14printPostorderP10par_rbNode, @function
_Z14printPostorderP10par_rbNode:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z14printPostorderP10par_rbNode, .-_Z14printPostorderP10par_rbNode
.globl _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode
.type _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode, @function
_Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode:
.LFB2093:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3RBTP10par_rbNode(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode, .-_Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode
.globl _Z3RBTP10par_rbNode
.type _Z3RBTP10par_rbNode, @function
_Z3RBTP10par_rbNode:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z3RBTP10par_rbNode, .-_Z3RBTP10par_rbNode
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Kernel Launched\n"
.LC1:
.string "Came back\n"
.LC2:
.string "Time for the kernel: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2068:
.cfi_startproc
endbr64
subq $392, %rsp
.cfi_def_cfa_offset 400
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $320, %esi
call cudaMalloc@PLT
leaq 52(%rsp), %rax
leaq 372(%rsp), %rdx
.L34:
movl $0, (%rax)
addq $32, %rax
cmpq %rdx, %rax
jne .L34
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $320, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $320, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 36(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq (%rsp), %rdi
call _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3RBTP10par_rbNode"
.LC4:
.string "nodes"
.LC5:
.string "root"
.LC6:
.string "NIL"
.LC7:
.string "rtParent"
.LC8:
.string "rtSibling"
.LC9:
.string "nodeIndex"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3RBTP10par_rbNode(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5nodes(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4root(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3NIL(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8rtParent(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9rtSibling(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9nodeIndex(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL9nodeIndex
.comm _ZL9nodeIndex,4,4
.local _ZL9rtSibling
.comm _ZL9rtSibling,8,8
.local _ZL8rtParent
.comm _ZL8rtParent,8,8
.local _ZL3NIL
.comm _ZL3NIL,8,8
.local _ZL4root
.comm _ZL4root,8,8
.local _ZL5nodes
.comm _ZL5nodes,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#define M 10
// RED = 0, BLACK = 1
enum nodeColor {
RED,
BLACK
};
enum result {
Failure,
Success,
FirstInsert
};
enum caseFlag {
NOOP,
DID_CASE1,
DID_CASE3
};
struct par_rbNode {
int key, color;
struct par_rbNode *left, *right, *parent;
};
// /*Function prototypes */
__device__ void createNIL();
__device__ struct par_rbNode * createNode(int);
__device__ void createTree();
__device__ struct par_rbNode * Traverse(int);
__device__ enum result PlaceNode(struct par_rbNode *, struct par_rbNode *);
__device__ void Insert_Rebalance(struct par_rbNode *);
__device__ bool Update_Rotation(struct par_rbNode *, enum caseFlag *);
__device__ void Left_Rotate(struct par_rbNode *);
__device__ void Right_Rotate(struct par_rbNode *);
__device__ struct par_rbNode *nodes;
__device__ struct par_rbNode *root;
__device__ struct par_rbNode *NIL;
__device__ struct par_rbNode *rtParent;
__device__ struct par_rbNode *rtSibling; // U might feel this is unncessary, but it will be used
__device__ int nodeIndex = 0;
__device__ void createNIL(){
NIL = &nodes[0];
NIL->color = BLACK;
NIL->key = -1;
NIL->left = NIL->right = NIL->parent = NIL;
printf("NIL created\n");
}
__device__ struct par_rbNode * createNode(int key){
atomicAdd(&nodeIndex,1);
nodes[nodeIndex].key = key;
nodes[nodeIndex].left = nodes[nodeIndex].right = nodes[nodeIndex].parent = NIL;
return &nodes[nodeIndex]; // Even if this thread pauses it will eventually return the correct pointer
}
__device__ void createTree(){
rtParent = createNode(-1);
rtSibling = createNode(-1);
root = NIL;
rtParent->parent = NIL;
rtSibling->parent = rtParent;
rtSibling->right = NIL;
rtSibling->left = NIL;
rtParent->left = root;
rtParent->right = rtSibling;
rtParent->color = BLACK;
rtSibling->color = BLACK;
NIL->parent = rtParent;
printf("Tree Created \n");
printf("\n");
}
__device__ struct par_rbNode * Traverse(int d){
struct par_rbNode *x;
x = root;
if(x == NIL){
printf("Empty Tree\n");
return NIL;
}
while(x != NIL){
if(x->key == d){
printf("Found it!\n");
return x;
}else if(x->key > d){
x = x->left;
}else{
x = x->right;
}
}
printf("Couldn't find %d in this tree\n",d);
return NIL;
}
__device__ void Left_Rotate(struct par_rbNode *lptr){
struct par_rbNode *y;
y = lptr->right;
lptr->right = y->left;
if(y->left != NIL)
y->left->parent = lptr;
if(y!=NIL)
y->parent = lptr->parent;
if(lptr->parent == NIL){
root = y;
}else if(lptr == lptr->parent->left)
lptr->parent->left = y;
else
lptr->parent->right = y;
y->left = lptr;
if(lptr != NIL)
lptr->parent = y;
}
__device__ void Right_Rotate(struct par_rbNode *rptr){
struct par_rbNode *y;
y = rptr->left;
rptr->left = y->right;
if(y->right != NIL)
y->right->parent = rptr;
if(y!=NIL)
y->parent = rptr->parent;
if(rptr->parent == NIL){
root = y;
}else if(rptr == rptr->parent->right)
rptr->parent->right = y;
else
rptr->parent->left = y;
y->right = rptr;
if(rptr != NIL)
rptr->parent = y;
}
__device__ void Insert_fixup(struct par_rbNode *x){
struct par_rbNode *u;
while(x->parent->color == RED){
if(x->parent == x->parent->parent->left){
u = x->parent->parent->right;
if(u->color == RED){//CASE 1
x->parent->color = BLACK;
u->color = BLACK;
x->parent->parent->color = RED;
x = x->parent->parent;
}else if(x == x->parent->right){//CASE 2
x = x->parent;
Left_Rotate(x);
x->parent->color = BLACK;
x->parent->parent->color = RED;
Right_Rotate(x->parent->parent);
}else if(x == x->parent->left){
x->parent->color = BLACK;
x->parent->parent->color = RED;
Right_Rotate(x->parent->parent);
} //CASE 3
}else{
u = x->parent->parent->left;
if(u->color == RED){//CASE 1
x->parent->color = BLACK;
u->color = BLACK;
x->parent->parent->color = RED;
x = x->parent->parent;
}else if(x == x->parent->left){//CASE 2
x = x->parent;
Right_Rotate(x);
x->parent->color = BLACK;
x->parent->parent->color = RED;
Left_Rotate(x->parent->parent);
}else if(x == x->parent->right){
x->parent->color = BLACK;
x->parent->parent->color = RED;
Left_Rotate(x->parent->parent);
} //CASE 3
}
}
root->color = BLACK;
}
__device__ void Insert(int d){
if(root == NIL){
root = createNode(d);
root->color = BLACK;
return;
}
struct par_rbNode *x,*z;
x = root;
while(x != NIL){
z = x;
if(d == x->key){ // Find if the node with this value is already there or not
printf("Duplicate Nodes are not allowed\n");
return;
}
if(d < x->key)
x = x->left;
else
x = x->right;
}//end while
x=createNode(d);
x->parent = z;
if(x->key < z->key) //Check if y is the left child of z or not
z->left = x;
else
z->right = x;
//NEW NODE IS INSERTED, NOW FIX THE RB TREE
Insert_fixup(x);
// printInorder(root);
}
//Functions for printing the tree
__device__ void printPreorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
/* then recur on left child */
printPreorder(node->left);
/* now recur on right child */
printPreorder(node->right);
}
__device__ void printInorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first recur on left child */
printInorder(node->left);
/* then print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
/* now recur on right child */
printInorder(node->right);
}
__device__ void printPostorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first recur on left child */
printPostorder(node->left);
/* then recur on right child */
printPostorder(node->right);
/* now print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
}
__global__ void RBT(struct par_rbNode *d_nodes) {
printf("Starting the Tree\n");
nodes = d_nodes; // Make it a global variable
createNIL();
createTree();
for(int i=0;i<7;i++){
Insert(i);
}
printf("PreOrder: ");
printPreorder(root);
printf("\n");
printf("\n");
printf("InOrder: ");
printInorder(root);
printf("\n");
printf("\n");
printf("PostOrder: ");
printPostorder(root);
printf("\n");
printf("\n");
printf("Done\n");
//return to main
}
int main() {
struct par_rbNode h_nodes[M];
struct par_rbNode *d_nodes;
float time;
// 1. Allocate device array.
cudaMalloc(&d_nodes, M * sizeof(struct par_rbNode));
for(int i=0;i<M;i++){
h_nodes[i].color = RED;
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// 2. Copy array contents from host to device.
cudaMemcpy(d_nodes, h_nodes, M * sizeof(struct par_rbNode), cudaMemcpyHostToDevice);
printf("Kernel Launched\n");
cudaEventRecord(start, 0);
RBT<<<1,1>>>(d_nodes);
cudaMemcpy(h_nodes, d_nodes, M * sizeof(struct par_rbNode), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
printf("Came back\n");
cudaEventElapsedTime(&time, start, stop);
printf ("Time for the kernel: %f ms\n", time);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#define M 10
// RED = 0, BLACK = 1
enum nodeColor {
RED,
BLACK
};
enum result {
Failure,
Success,
FirstInsert
};
enum caseFlag {
NOOP,
DID_CASE1,
DID_CASE3
};
struct par_rbNode {
int key, color;
struct par_rbNode *left, *right, *parent;
};
// /*Function prototypes */
__device__ void createNIL();
__device__ struct par_rbNode * createNode(int);
__device__ void createTree();
__device__ struct par_rbNode * Traverse(int);
__device__ enum result PlaceNode(struct par_rbNode *, struct par_rbNode *);
__device__ void Insert_Rebalance(struct par_rbNode *);
__device__ bool Update_Rotation(struct par_rbNode *, enum caseFlag *);
__device__ void Left_Rotate(struct par_rbNode *);
__device__ void Right_Rotate(struct par_rbNode *);
__device__ struct par_rbNode *nodes;
__device__ struct par_rbNode *root;
__device__ struct par_rbNode *NIL;
__device__ struct par_rbNode *rtParent;
__device__ struct par_rbNode *rtSibling; // U might feel this is unncessary, but it will be used
__device__ int nodeIndex = 0;
__device__ void createNIL(){
NIL = &nodes[0];
NIL->color = BLACK;
NIL->key = -1;
NIL->left = NIL->right = NIL->parent = NIL;
printf("NIL created\n");
}
__device__ struct par_rbNode * createNode(int key){
atomicAdd(&nodeIndex,1);
nodes[nodeIndex].key = key;
nodes[nodeIndex].left = nodes[nodeIndex].right = nodes[nodeIndex].parent = NIL;
return &nodes[nodeIndex]; // Even if this thread pauses it will eventually return the correct pointer
}
__device__ void createTree(){
rtParent = createNode(-1);
rtSibling = createNode(-1);
root = NIL;
rtParent->parent = NIL;
rtSibling->parent = rtParent;
rtSibling->right = NIL;
rtSibling->left = NIL;
rtParent->left = root;
rtParent->right = rtSibling;
rtParent->color = BLACK;
rtSibling->color = BLACK;
NIL->parent = rtParent;
printf("Tree Created \n");
printf("\n");
}
__device__ struct par_rbNode * Traverse(int d){
struct par_rbNode *x;
x = root;
if(x == NIL){
printf("Empty Tree\n");
return NIL;
}
while(x != NIL){
if(x->key == d){
printf("Found it!\n");
return x;
}else if(x->key > d){
x = x->left;
}else{
x = x->right;
}
}
printf("Couldn't find %d in this tree\n",d);
return NIL;
}
__device__ void Left_Rotate(struct par_rbNode *lptr){
struct par_rbNode *y;
y = lptr->right;
lptr->right = y->left;
if(y->left != NIL)
y->left->parent = lptr;
if(y!=NIL)
y->parent = lptr->parent;
if(lptr->parent == NIL){
root = y;
}else if(lptr == lptr->parent->left)
lptr->parent->left = y;
else
lptr->parent->right = y;
y->left = lptr;
if(lptr != NIL)
lptr->parent = y;
}
__device__ void Right_Rotate(struct par_rbNode *rptr){
struct par_rbNode *y;
y = rptr->left;
rptr->left = y->right;
if(y->right != NIL)
y->right->parent = rptr;
if(y!=NIL)
y->parent = rptr->parent;
if(rptr->parent == NIL){
root = y;
}else if(rptr == rptr->parent->right)
rptr->parent->right = y;
else
rptr->parent->left = y;
y->right = rptr;
if(rptr != NIL)
rptr->parent = y;
}
__device__ void Insert_fixup(struct par_rbNode *x){
struct par_rbNode *u;
while(x->parent->color == RED){
if(x->parent == x->parent->parent->left){
u = x->parent->parent->right;
if(u->color == RED){//CASE 1
x->parent->color = BLACK;
u->color = BLACK;
x->parent->parent->color = RED;
x = x->parent->parent;
}else if(x == x->parent->right){//CASE 2
x = x->parent;
Left_Rotate(x);
x->parent->color = BLACK;
x->parent->parent->color = RED;
Right_Rotate(x->parent->parent);
}else if(x == x->parent->left){
x->parent->color = BLACK;
x->parent->parent->color = RED;
Right_Rotate(x->parent->parent);
} //CASE 3
}else{
u = x->parent->parent->left;
if(u->color == RED){//CASE 1
x->parent->color = BLACK;
u->color = BLACK;
x->parent->parent->color = RED;
x = x->parent->parent;
}else if(x == x->parent->left){//CASE 2
x = x->parent;
Right_Rotate(x);
x->parent->color = BLACK;
x->parent->parent->color = RED;
Left_Rotate(x->parent->parent);
}else if(x == x->parent->right){
x->parent->color = BLACK;
x->parent->parent->color = RED;
Left_Rotate(x->parent->parent);
} //CASE 3
}
}
root->color = BLACK;
}
__device__ void Insert(int d){
if(root == NIL){
root = createNode(d);
root->color = BLACK;
return;
}
struct par_rbNode *x,*z;
x = root;
while(x != NIL){
z = x;
if(d == x->key){ // Find if the node with this value is already there or not
printf("Duplicate Nodes are not allowed\n");
return;
}
if(d < x->key)
x = x->left;
else
x = x->right;
}//end while
x=createNode(d);
x->parent = z;
if(x->key < z->key) //Check if y is the left child of z or not
z->left = x;
else
z->right = x;
//NEW NODE IS INSERTED, NOW FIX THE RB TREE
Insert_fixup(x);
// printInorder(root);
}
//Functions for printing the tree
__device__ void printPreorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
/* then recur on left child */
printPreorder(node->left);
/* now recur on right child */
printPreorder(node->right);
}
__device__ void printInorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first recur on left child */
printInorder(node->left);
/* then print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
/* now recur on right child */
printInorder(node->right);
}
__device__ void printPostorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first recur on left child */
printPostorder(node->left);
/* then recur on right child */
printPostorder(node->right);
/* now print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
}
__global__ void RBT(struct par_rbNode *d_nodes) {
printf("Starting the Tree\n");
nodes = d_nodes; // Make it a global variable
createNIL();
createTree();
for(int i=0;i<7;i++){
Insert(i);
}
printf("PreOrder: ");
printPreorder(root);
printf("\n");
printf("\n");
printf("InOrder: ");
printInorder(root);
printf("\n");
printf("\n");
printf("PostOrder: ");
printPostorder(root);
printf("\n");
printf("\n");
printf("Done\n");
//return to main
}
int main() {
struct par_rbNode h_nodes[M];
struct par_rbNode *d_nodes;
float time;
// 1. Allocate device array.
hipMalloc(&d_nodes, M * sizeof(struct par_rbNode));
for(int i=0;i<M;i++){
h_nodes[i].color = RED;
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// 2. Copy array contents from host to device.
hipMemcpy(d_nodes, h_nodes, M * sizeof(struct par_rbNode), hipMemcpyHostToDevice);
printf("Kernel Launched\n");
hipEventRecord(start, 0);
RBT<<<1,1>>>(d_nodes);
hipMemcpy(h_nodes, d_nodes, M * sizeof(struct par_rbNode), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
printf("Came back\n");
hipEventElapsedTime(&time, start, stop);
printf ("Time for the kernel: %f ms\n", time);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#define M 10
// RED = 0, BLACK = 1
enum nodeColor {
RED,
BLACK
};
enum result {
Failure,
Success,
FirstInsert
};
enum caseFlag {
NOOP,
DID_CASE1,
DID_CASE3
};
struct par_rbNode {
int key, color;
struct par_rbNode *left, *right, *parent;
};
// /*Function prototypes */
__device__ void createNIL();
__device__ struct par_rbNode * createNode(int);
__device__ void createTree();
__device__ struct par_rbNode * Traverse(int);
__device__ enum result PlaceNode(struct par_rbNode *, struct par_rbNode *);
__device__ void Insert_Rebalance(struct par_rbNode *);
__device__ bool Update_Rotation(struct par_rbNode *, enum caseFlag *);
__device__ void Left_Rotate(struct par_rbNode *);
__device__ void Right_Rotate(struct par_rbNode *);
__device__ struct par_rbNode *nodes;
__device__ struct par_rbNode *root;
__device__ struct par_rbNode *NIL;
__device__ struct par_rbNode *rtParent;
__device__ struct par_rbNode *rtSibling; // U might feel this is unncessary, but it will be used
__device__ int nodeIndex = 0;
__device__ void createNIL(){
NIL = &nodes[0];
NIL->color = BLACK;
NIL->key = -1;
NIL->left = NIL->right = NIL->parent = NIL;
printf("NIL created\n");
}
__device__ struct par_rbNode * createNode(int key){
atomicAdd(&nodeIndex,1);
nodes[nodeIndex].key = key;
nodes[nodeIndex].left = nodes[nodeIndex].right = nodes[nodeIndex].parent = NIL;
return &nodes[nodeIndex]; // Even if this thread pauses it will eventually return the correct pointer
}
__device__ void createTree(){
rtParent = createNode(-1);
rtSibling = createNode(-1);
root = NIL;
rtParent->parent = NIL;
rtSibling->parent = rtParent;
rtSibling->right = NIL;
rtSibling->left = NIL;
rtParent->left = root;
rtParent->right = rtSibling;
rtParent->color = BLACK;
rtSibling->color = BLACK;
NIL->parent = rtParent;
printf("Tree Created \n");
printf("\n");
}
__device__ struct par_rbNode * Traverse(int d){
struct par_rbNode *x;
x = root;
if(x == NIL){
printf("Empty Tree\n");
return NIL;
}
while(x != NIL){
if(x->key == d){
printf("Found it!\n");
return x;
}else if(x->key > d){
x = x->left;
}else{
x = x->right;
}
}
printf("Couldn't find %d in this tree\n",d);
return NIL;
}
__device__ void Left_Rotate(struct par_rbNode *lptr){
struct par_rbNode *y;
y = lptr->right;
lptr->right = y->left;
if(y->left != NIL)
y->left->parent = lptr;
if(y!=NIL)
y->parent = lptr->parent;
if(lptr->parent == NIL){
root = y;
}else if(lptr == lptr->parent->left)
lptr->parent->left = y;
else
lptr->parent->right = y;
y->left = lptr;
if(lptr != NIL)
lptr->parent = y;
}
__device__ void Right_Rotate(struct par_rbNode *rptr){
struct par_rbNode *y;
y = rptr->left;
rptr->left = y->right;
if(y->right != NIL)
y->right->parent = rptr;
if(y!=NIL)
y->parent = rptr->parent;
if(rptr->parent == NIL){
root = y;
}else if(rptr == rptr->parent->right)
rptr->parent->right = y;
else
rptr->parent->left = y;
y->right = rptr;
if(rptr != NIL)
rptr->parent = y;
}
__device__ void Insert_fixup(struct par_rbNode *x){
struct par_rbNode *u;
while(x->parent->color == RED){
if(x->parent == x->parent->parent->left){
u = x->parent->parent->right;
if(u->color == RED){//CASE 1
x->parent->color = BLACK;
u->color = BLACK;
x->parent->parent->color = RED;
x = x->parent->parent;
}else if(x == x->parent->right){//CASE 2
x = x->parent;
Left_Rotate(x);
x->parent->color = BLACK;
x->parent->parent->color = RED;
Right_Rotate(x->parent->parent);
}else if(x == x->parent->left){
x->parent->color = BLACK;
x->parent->parent->color = RED;
Right_Rotate(x->parent->parent);
} //CASE 3
}else{
u = x->parent->parent->left;
if(u->color == RED){//CASE 1
x->parent->color = BLACK;
u->color = BLACK;
x->parent->parent->color = RED;
x = x->parent->parent;
}else if(x == x->parent->left){//CASE 2
x = x->parent;
Right_Rotate(x);
x->parent->color = BLACK;
x->parent->parent->color = RED;
Left_Rotate(x->parent->parent);
}else if(x == x->parent->right){
x->parent->color = BLACK;
x->parent->parent->color = RED;
Left_Rotate(x->parent->parent);
} //CASE 3
}
}
root->color = BLACK;
}
__device__ void Insert(int d){
if(root == NIL){
root = createNode(d);
root->color = BLACK;
return;
}
struct par_rbNode *x,*z;
x = root;
while(x != NIL){
z = x;
if(d == x->key){ // Find if the node with this value is already there or not
printf("Duplicate Nodes are not allowed\n");
return;
}
if(d < x->key)
x = x->left;
else
x = x->right;
}//end while
x=createNode(d);
x->parent = z;
if(x->key < z->key) //Check if y is the left child of z or not
z->left = x;
else
z->right = x;
//NEW NODE IS INSERTED, NOW FIX THE RB TREE
Insert_fixup(x);
// printInorder(root);
}
//Functions for printing the tree
__device__ void printPreorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
/* then recur on left child */
printPreorder(node->left);
/* now recur on right child */
printPreorder(node->right);
}
__device__ void printInorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first recur on left child */
printInorder(node->left);
/* then print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
/* now recur on right child */
printInorder(node->right);
}
__device__ void printPostorder(struct par_rbNode* node)
{
if (node == NIL)
return;
/* first recur on left child */
printPostorder(node->left);
/* then recur on right child */
printPostorder(node->right);
/* now print the data of node */
printf("%d-", node->key);
printf("%d", node->color);
printf(" ");
}
__global__ void RBT(struct par_rbNode *d_nodes) {
printf("Starting the Tree\n");
nodes = d_nodes; // Make it a global variable
createNIL();
createTree();
for(int i=0;i<7;i++){
Insert(i);
}
printf("PreOrder: ");
printPreorder(root);
printf("\n");
printf("\n");
printf("InOrder: ");
printInorder(root);
printf("\n");
printf("\n");
printf("PostOrder: ");
printPostorder(root);
printf("\n");
printf("\n");
printf("Done\n");
//return to main
}
int main() {
struct par_rbNode h_nodes[M];
struct par_rbNode *d_nodes;
float time;
// 1. Allocate device array.
hipMalloc(&d_nodes, M * sizeof(struct par_rbNode));
for(int i=0;i<M;i++){
h_nodes[i].color = RED;
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// 2. Copy array contents from host to device.
hipMemcpy(d_nodes, h_nodes, M * sizeof(struct par_rbNode), hipMemcpyHostToDevice);
printf("Kernel Launched\n");
hipEventRecord(start, 0);
RBT<<<1,1>>>(d_nodes);
hipMemcpy(h_nodes, d_nodes, M * sizeof(struct par_rbNode), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
printf("Came back\n");
hipEventElapsedTime(&time, start, stop);
printf ("Time for the kernel: %f ms\n", time);
return 0;
}
|
.text
.file "serial_rbt_gpu.hip"
.globl _Z18__device_stub__RBTP10par_rbNode # -- Begin function _Z18__device_stub__RBTP10par_rbNode
.p2align 4, 0x90
.type _Z18__device_stub__RBTP10par_rbNode,@function
_Z18__device_stub__RBTP10par_rbNode: # @_Z18__device_stub__RBTP10par_rbNode
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3RBTP10par_rbNode, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__RBTP10par_rbNode, .Lfunc_end0-_Z18__device_stub__RBTP10par_rbNode
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 432
leaq 16(%rsp), %rdi
movl $320, %esi # imm = 0x140
callq hipMalloc
movl $4, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $0, 96(%rsp,%rax)
addq $32, %rax
cmpq $324, %rax # imm = 0x144
jne .LBB1_1
# %bb.2:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $320, %edx # imm = 0x140
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 48(%rsp)
leaq 24(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3RBTP10par_rbNode, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $320, %edx # imm = 0x140
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3RBTP10par_rbNode, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $nodes, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $root, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $NIL, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $rtParent, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $rtSibling, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $nodeIndex, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type nodes,@object # @nodes
.local nodes
.comm nodes,8,8
.type root,@object # @root
.local root
.comm root,8,8
.type NIL,@object # @NIL
.local NIL
.comm NIL,8,8
.type rtParent,@object # @rtParent
.local rtParent
.comm rtParent,8,8
.type rtSibling,@object # @rtSibling
.local rtSibling
.comm rtSibling,8,8
.type nodeIndex,@object # @nodeIndex
.local nodeIndex
.comm nodeIndex,4,4
.type _Z3RBTP10par_rbNode,@object # @_Z3RBTP10par_rbNode
.section .rodata,"a",@progbits
.globl _Z3RBTP10par_rbNode
.p2align 3, 0x0
_Z3RBTP10par_rbNode:
.quad _Z18__device_stub__RBTP10par_rbNode
.size _Z3RBTP10par_rbNode, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Time for the kernel: %f ms\n"
.size .L.str.2, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3RBTP10par_rbNode"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "nodes"
.size .L__unnamed_2, 6
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "root"
.size .L__unnamed_3, 5
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "NIL"
.size .L__unnamed_4, 4
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "rtParent"
.size .L__unnamed_5, 9
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "rtSibling"
.size .L__unnamed_6, 10
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "nodeIndex"
.size .L__unnamed_7, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Kernel Launched"
.size .Lstr, 16
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Came back"
.size .Lstr.1, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__RBTP10par_rbNode
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nodes
.addrsig_sym root
.addrsig_sym NIL
.addrsig_sym rtParent
.addrsig_sym rtSibling
.addrsig_sym nodeIndex
.addrsig_sym _Z3RBTP10par_rbNode
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0009ecb6_00000000-6_serial_rbt_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9createNILv
.type _Z9createNILv, @function
_Z9createNILv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9createNILv, .-_Z9createNILv
.globl _Z10createNodei
.type _Z10createNodei, @function
_Z10createNodei:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10createNodei, .-_Z10createNodei
.globl _Z10createTreev
.type _Z10createTreev, @function
_Z10createTreev:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10createTreev, .-_Z10createTreev
.globl _Z8Traversei
.type _Z8Traversei, @function
_Z8Traversei:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z8Traversei, .-_Z8Traversei
.globl _Z11Left_RotateP10par_rbNode
.type _Z11Left_RotateP10par_rbNode, @function
_Z11Left_RotateP10par_rbNode:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z11Left_RotateP10par_rbNode, .-_Z11Left_RotateP10par_rbNode
.globl _Z12Right_RotateP10par_rbNode
.type _Z12Right_RotateP10par_rbNode, @function
_Z12Right_RotateP10par_rbNode:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z12Right_RotateP10par_rbNode, .-_Z12Right_RotateP10par_rbNode
.globl _Z12Insert_fixupP10par_rbNode
.type _Z12Insert_fixupP10par_rbNode, @function
_Z12Insert_fixupP10par_rbNode:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z12Insert_fixupP10par_rbNode, .-_Z12Insert_fixupP10par_rbNode
.globl _Z6Inserti
.type _Z6Inserti, @function
_Z6Inserti:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z6Inserti, .-_Z6Inserti
.globl _Z13printPreorderP10par_rbNode
.type _Z13printPreorderP10par_rbNode, @function
_Z13printPreorderP10par_rbNode:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z13printPreorderP10par_rbNode, .-_Z13printPreorderP10par_rbNode
.globl _Z12printInorderP10par_rbNode
.type _Z12printInorderP10par_rbNode, @function
_Z12printInorderP10par_rbNode:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z12printInorderP10par_rbNode, .-_Z12printInorderP10par_rbNode
.globl _Z14printPostorderP10par_rbNode
.type _Z14printPostorderP10par_rbNode, @function
_Z14printPostorderP10par_rbNode:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z14printPostorderP10par_rbNode, .-_Z14printPostorderP10par_rbNode
.globl _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode
.type _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode, @function
_Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode:
.LFB2093:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3RBTP10par_rbNode(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode, .-_Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode
.globl _Z3RBTP10par_rbNode
.type _Z3RBTP10par_rbNode, @function
_Z3RBTP10par_rbNode:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z3RBTP10par_rbNode, .-_Z3RBTP10par_rbNode
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Kernel Launched\n"
.LC1:
.string "Came back\n"
.LC2:
.string "Time for the kernel: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2068:
.cfi_startproc
endbr64
subq $392, %rsp
.cfi_def_cfa_offset 400
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $320, %esi
call cudaMalloc@PLT
leaq 52(%rsp), %rax
leaq 372(%rsp), %rdx
.L34:
movl $0, (%rax)
addq $32, %rax
cmpq %rdx, %rax
jne .L34
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $320, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $320, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 36(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq (%rsp), %rdi
call _Z33__device_stub__Z3RBTP10par_rbNodeP10par_rbNode
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3RBTP10par_rbNode"
.LC4:
.string "nodes"
.LC5:
.string "root"
.LC6:
.string "NIL"
.LC7:
.string "rtParent"
.LC8:
.string "rtSibling"
.LC9:
.string "nodeIndex"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3RBTP10par_rbNode(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5nodes(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4root(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3NIL(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8rtParent(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9rtSibling(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9nodeIndex(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL9nodeIndex
.comm _ZL9nodeIndex,4,4
.local _ZL9rtSibling
.comm _ZL9rtSibling,8,8
.local _ZL8rtParent
.comm _ZL8rtParent,8,8
.local _ZL3NIL
.comm _ZL3NIL,8,8
.local _ZL4root
.comm _ZL4root,8,8
.local _ZL5nodes
.comm _ZL5nodes,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "serial_rbt_gpu.hip"
.globl _Z18__device_stub__RBTP10par_rbNode # -- Begin function _Z18__device_stub__RBTP10par_rbNode
.p2align 4, 0x90
.type _Z18__device_stub__RBTP10par_rbNode,@function
_Z18__device_stub__RBTP10par_rbNode: # @_Z18__device_stub__RBTP10par_rbNode
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3RBTP10par_rbNode, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__RBTP10par_rbNode, .Lfunc_end0-_Z18__device_stub__RBTP10par_rbNode
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 432
leaq 16(%rsp), %rdi
movl $320, %esi # imm = 0x140
callq hipMalloc
movl $4, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $0, 96(%rsp,%rax)
addq $32, %rax
cmpq $324, %rax # imm = 0x144
jne .LBB1_1
# %bb.2:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $320, %edx # imm = 0x140
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 48(%rsp)
leaq 24(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3RBTP10par_rbNode, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $320, %edx # imm = 0x140
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3RBTP10par_rbNode, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $nodes, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $root, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $NIL, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $rtParent, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $rtSibling, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $nodeIndex, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type nodes,@object # @nodes
.local nodes
.comm nodes,8,8
.type root,@object # @root
.local root
.comm root,8,8
.type NIL,@object # @NIL
.local NIL
.comm NIL,8,8
.type rtParent,@object # @rtParent
.local rtParent
.comm rtParent,8,8
.type rtSibling,@object # @rtSibling
.local rtSibling
.comm rtSibling,8,8
.type nodeIndex,@object # @nodeIndex
.local nodeIndex
.comm nodeIndex,4,4
.type _Z3RBTP10par_rbNode,@object # @_Z3RBTP10par_rbNode
.section .rodata,"a",@progbits
.globl _Z3RBTP10par_rbNode
.p2align 3, 0x0
_Z3RBTP10par_rbNode:
.quad _Z18__device_stub__RBTP10par_rbNode
.size _Z3RBTP10par_rbNode, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Time for the kernel: %f ms\n"
.size .L.str.2, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3RBTP10par_rbNode"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "nodes"
.size .L__unnamed_2, 6
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "root"
.size .L__unnamed_3, 5
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "NIL"
.size .L__unnamed_4, 4
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "rtParent"
.size .L__unnamed_5, 9
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "rtSibling"
.size .L__unnamed_6, 10
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "nodeIndex"
.size .L__unnamed_7, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Kernel Launched"
.size .Lstr, 16
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Came back"
.size .Lstr.1, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__RBTP10par_rbNode
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nodes
.addrsig_sym root
.addrsig_sym NIL
.addrsig_sym rtParent
.addrsig_sym rtSibling
.addrsig_sym nodeIndex
.addrsig_sym _Z3RBTP10par_rbNode
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N (1024)
__global__ void mult(float *A, float *B, float *C) {
unsigned int idx_X = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idx_Y = threadIdx.y + blockIdx.y * blockDim.y;
float sum = 0.;
if ((idx_X < N) && (idx_Y < N)) {
for (int i = 0; i < N; i++) {
sum += A[idx_X*N + i] * B[idx_Y + i*N];
}
C[idx_X*N + idx_Y] = sum;
}
}
int main(void) {
cudaEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *hostA, *hostB;
float *hostC;
float *devA, *devB;
float *devC;
size_t mem_size = N*N*sizeof(float);
hostA = (float *)malloc(mem_size);
hostB = (float *)malloc(mem_size);
hostC = (float *)malloc(mem_size);
cudaMalloc((void**)&devA, mem_size);
cudaMalloc((void**)&devB, mem_size);
cudaMalloc((void**)&devC, mem_size);
for (int i = 0; i < N*N; i++) {
hostA[i] = sqrtf(i);
hostB[i] = sinf(i);
hostC[i] = 0.;
}
int N_Threads = 8;
int N_Blocks = 0;
if (((N) % N_Threads) == 0) {
N_Blocks = ((N) / N_Threads);
}
else {
N_Blocks = ((N) / N_Threads) + 1;
}
dim3 Threads(N_Threads,N_Threads);
dim3 Blocks(N_Blocks, N_Blocks);
cudaEventCreate(&GPUstart);
cudaEventCreate(&GPUstop);
cudaEventRecord(GPUstart, 0);
cudaMemcpy(devA, hostA, mem_size, cudaMemcpyHostToDevice);
cudaMemcpy(devB, hostB, mem_size, cudaMemcpyHostToDevice);
cudaMemset(devC, 0, mem_size);
mult <<< Blocks, Threads >>> (devA, devB, devC);
cudaMemcpy(hostC, devC, mem_size, cudaMemcpyDeviceToHost);
cudaEventRecord(GPUstop, 0);
cudaEventSynchronize(GPUstop);
cudaEventElapsedTime(&GPUtime, GPUstart, GPUstop);
printf("GPU time : %.3f ms\n", GPUtime);
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
free(hostA);
free(hostB);
free(hostC);
return 0;
}
|
code for sm_80
Function : _Z4multPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fc400078e0200 */
/*0060*/ IMAD R0, R2, c[0x0][0x4], R5 ; /* 0x0000010002007a24 */
/* 0x002fca00078e0205 */
/*0070*/ LOP3.LUT P0, RZ, R3, 0xfffffc00, R0, 0xc8, !PT ; /* 0xfffffc0003ff7812 */
/* 0x000fda000780c800 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00a0*/ SHF.L.U32 R3, R3, 0xa, RZ ; /* 0x0000000a03037819 */
/* 0x000fe200000006ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R5, R0, 0x3c00, RZ ; /* 0x00003c0000057810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ MOV R29, RZ ; /* 0x000000ff001d7202 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fc60000000f00 */
/*00f0*/ IMAD.WIDE.U32 R6, R3, R2, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0002 */
/*0100*/ IADD3 R12, P0, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x000fe20007f1e0ff */
/*0110*/ HFMA2.MMA R6, -RZ, RZ, 0, 0.0078125 ; /* 0x00002000ff067435 */
/* 0x000fc600000001ff */
/*0120*/ IADD3.X R13, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fc800007fe4ff */
/*0130*/ IADD3 R9, R5.reuse, -0x3c00, RZ ; /* 0xffffc40005097810 */
/* 0x040fe20007ffe0ff */
/*0140*/ LDG.E R28, [R12.64+-0x20] ; /* 0xffffe0040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R11, R5.reuse, -0x3800, RZ ; /* 0xffffc800050b7810 */
/* 0x040fe40007ffe0ff */
/*0160*/ IADD3 R19, R5, -0x3400, RZ ; /* 0xffffcc0005137810 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.WIDE.U32 R8, R9, R2.reuse, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x080fe200078e0002 */
/*0180*/ LDG.E R26, [R12.64+-0x1c] ; /* 0xffffe4040c1a7981 */
/* 0x000ee6000c1e1900 */
/*0190*/ IMAD.WIDE.U32 R10, R11, R2, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe200078e0002 */
/*01a0*/ LDG.E R27, [R8.64] ; /* 0x00000004081b7981 */
/* 0x0000a2000c1e1900 */
/*01b0*/ IADD3 R21, R4, 0xc00, RZ ; /* 0x00000c0004157810 */
/* 0x000fc40007ffe0ff */
/*01c0*/ IMAD.WIDE.U32 R18, R19, R2.reuse, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x080fe200078e0002 */
/*01d0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x0002e2000c1e1900 */
/*01e0*/ IADD3 R17, R4.reuse, 0x1000, RZ ; /* 0x0000100004117810 */
/* 0x040fe40007ffe0ff */
/*01f0*/ IMAD.WIDE.U32 R20, R21, R2.reuse, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x080fe200078e0002 */
/*0200*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000968000c1e1900 */
/*0210*/ LDG.E R15, [R12.64+-0x18] ; /* 0xffffe8040c0f7981 */
/* 0x000f62000c1e1900 */
/*0220*/ IADD3 R25, R4, 0x1400, RZ ; /* 0x0000140004197810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.WIDE.U32 R16, R17, R2, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fc400078e0002 */
/*0240*/ LDG.E R7, [R20.64] ; /* 0x0000000414077981 */
/* 0x000368000c1e1900 */
/*0250*/ LDG.E R8, [R12.64+-0x14] ; /* 0xffffec040c087981 */
/* 0x001f62000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R24, R25, R2, c[0x0][0x168] ; /* 0x00005a0019187625 */
/* 0x000fe200078e0002 */
/*0270*/ IADD3 R19, R4.reuse, 0x1800, RZ ; /* 0x0000180004137810 */
/* 0x050fe40007ffe0ff */
/*0280*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R10, [R12.64+-0x10] ; /* 0xfffff0040c0a7981 */
/* 0x002f22000c1e1900 */
/*02a0*/ IADD3 R21, R4, 0x1c00, RZ ; /* 0x00001c0004157810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000322000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R16, R19, R2, c[0x0][0x168] ; /* 0x00005a0013107625 */
/* 0x001fc600078e0002 */
/*02d0*/ LDG.E R18, [R12.64+-0xc] ; /* 0xfffff4040c127981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000122000c1e1900 */
/*02f0*/ IMAD.WIDE.U32 R20, R21, R2, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fc600078e0002 */
/*0300*/ LDG.E R22, [R12.64+-0x8] ; /* 0xfffff8040c167981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000128000c1e1900 */
/*0320*/ LDG.E R20, [R12.64+-0x4] ; /* 0xfffffc040c147981 */
/* 0x001f22000c1e1900 */
/*0330*/ IADD3 R25, R4, 0x2000, RZ ; /* 0x0000200004197810 */
/* 0x002fe20007ffe0ff */
/*0340*/ FFMA R27, R27, R28, R29 ; /* 0x0000001c1b1b7223 */
/* 0x004fc8000000001d */
/*0350*/ FFMA R23, R23, R26, R27 ; /* 0x0000001a17177223 */
/* 0x008fe2000000001b */
/*0360*/ IADD3 R27, R4, 0x2400, RZ ; /* 0x00002400041b7810 */
/* 0x000fc60007ffe0ff */
/*0370*/ FFMA R23, R14, R15, R23 ; /* 0x0000000f0e177223 */
/* 0x020fe40000000017 */
/*0380*/ IMAD.WIDE.U32 R14, R25, R2, c[0x0][0x168] ; /* 0x00005a00190e7625 */
/* 0x000fe200078e0002 */
/*0390*/ IADD3 R25, R4, 0x2800, RZ ; /* 0x0000280004197810 */
/* 0x000fc60007ffe0ff */
/*03a0*/ IMAD.WIDE.U32 R16, R27, R2, c[0x0][0x168] ; /* 0x00005a001b107625 */
/* 0x000fe200078e0002 */
/*03b0*/ IADD3 R27, R4, 0x2c00, RZ ; /* 0x00002c00041b7810 */
/* 0x000fe20007ffe0ff */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*03d0*/ FFMA R8, R7, R8, R23 ; /* 0x0000000807087223 */
/* 0x000fe40000000017 */
/*03e0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0002a2000c1e1900 */
/*03f0*/ IMAD.WIDE.U32 R24, R25, R2, c[0x0][0x168] ; /* 0x00005a0019187625 */
/* 0x000fe200078e0002 */
/*0400*/ IADD3 R29, R5, -0xc00, RZ ; /* 0xfffff400051d7810 */
/* 0x000fe40007ffe0ff */
/*0410*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000762000c1e1900 */
/*0420*/ FFMA R10, R9, R10, R8 ; /* 0x0000000a090a7223 */
/* 0x010fc60000000008 */
/*0430*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000362000c1e1900 */
/*0440*/ IMAD.WIDE.U32 R26, R27, R2, c[0x0][0x168] ; /* 0x00005a001b1a7625 */
/* 0x000fc600078e0002 */
/*0450*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000962000c1e1900 */
/*0460*/ FFMA R10, R11, R18, R10 ; /* 0x000000120b0a7223 */
/* 0x000fe2000000000a */
/*0470*/ IADD3 R11, R5, -0x800, RZ ; /* 0xfffff800050b7810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LDG.E R15, [R12.64+0x8] ; /* 0x000008040c0f7981 */
/* 0x001362000c1e1900 */
/*0490*/ IMAD.WIDE.U32 R8, R29, R2, c[0x0][0x168] ; /* 0x00005a001d087625 */
/* 0x000fe200078e0002 */
/*04a0*/ IADD3 R18, R5, -0x400, RZ ; /* 0xfffffc0005127810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R28, R19, R22, R10 ; /* 0x00000016131c7223 */
/* 0x000fc6000000000a */
/*04d0*/ LDG.E R29, [R12.64+0xc] ; /* 0x00000c040c1d7981 */
/* 0x000362000c1e1900 */
/*04e0*/ IMAD.WIDE.U32 R10, R11, R2, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc600078e0002 */
/*04f0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0080e2000c1e1900 */
/*0500*/ IMAD.WIDE.U32 R18, R18, R2, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fc600078e0002 */
/*0510*/ LDG.E R22, [R12.64+0x10] ; /* 0x000010040c167981 */
/* 0x0002e8000c1e1900 */
/*0520*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0530*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0540*/ LDG.E R25, [R12.64+0x14] ; /* 0x000014040c197981 */
/* 0x010322000c1e1900 */
/*0550*/ IMAD.WIDE.U32 R8, R5, R2, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x001fc600078e0002 */
/*0560*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1900 */
/*0570*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x000328000c1e1900 */
/*0580*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f28000c1e1900 */
/*0590*/ LDG.E R20, [R12.64+0x1c] ; /* 0x00001c040c147981 */
/* 0x000322000c1e1900 */
/*05a0*/ IADD3 R6, R6, 0x4000, RZ ; /* 0x0000400006067810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.NE.AND P0, PT, R6, 0x102000, PT ; /* 0x001020000600780c */
/* 0x000fe40003f05270 */
/*05c0*/ IADD3 R12, P1, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fe40007f3e0ff */
/*05d0*/ IADD3 R5, R5, 0x4000, RZ ; /* 0x0000400005057810 */
/* 0x000fe40007ffe0ff */
/*05e0*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe40000ffe4ff */
/*05f0*/ IADD3 R4, R4, 0x4000, RZ ; /* 0x0000400004047810 */
/* 0x000fe20007ffe0ff */
/*0600*/ FFMA R7, R14, R7, R28 ; /* 0x000000070e077223 */
/* 0x004fc8000000001c */
/*0610*/ FFMA R7, R16, R23, R7 ; /* 0x0000001710077223 */
/* 0x020fc80000000007 */
/*0620*/ FFMA R7, R24, R15, R7 ; /* 0x0000000f18077223 */
/* 0x000fc80000000007 */
/*0630*/ FFMA R7, R26, R29, R7 ; /* 0x0000001d1a077223 */
/* 0x000fc80000000007 */
/*0640*/ FFMA R7, R17, R22, R7 ; /* 0x0000001611077223 */
/* 0x008fc80000000007 */
/*0650*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x010fc80000000007 */
/*0660*/ FFMA R7, R18, R21, R7 ; /* 0x0000001512077223 */
/* 0x000fc80000000007 */
/*0670*/ FFMA R29, R9, R20, R7 ; /* 0x00000014091d7223 */
/* 0x000fe20000000007 */
/*0680*/ @P0 BRA 0x130 ; /* 0xfffffaa000000947 */
/* 0x000fea000383ffff */
/*0690*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fca0007ffe0ff */
/*06a0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0002 */
/*06b0*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x000fe2000c101904 */
/*06c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06d0*/ BRA 0x6d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N (1024)
__global__ void mult(float *A, float *B, float *C) {
unsigned int idx_X = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idx_Y = threadIdx.y + blockIdx.y * blockDim.y;
float sum = 0.;
if ((idx_X < N) && (idx_Y < N)) {
for (int i = 0; i < N; i++) {
sum += A[idx_X*N + i] * B[idx_Y + i*N];
}
C[idx_X*N + idx_Y] = sum;
}
}
int main(void) {
cudaEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *hostA, *hostB;
float *hostC;
float *devA, *devB;
float *devC;
size_t mem_size = N*N*sizeof(float);
hostA = (float *)malloc(mem_size);
hostB = (float *)malloc(mem_size);
hostC = (float *)malloc(mem_size);
cudaMalloc((void**)&devA, mem_size);
cudaMalloc((void**)&devB, mem_size);
cudaMalloc((void**)&devC, mem_size);
for (int i = 0; i < N*N; i++) {
hostA[i] = sqrtf(i);
hostB[i] = sinf(i);
hostC[i] = 0.;
}
int N_Threads = 8;
int N_Blocks = 0;
if (((N) % N_Threads) == 0) {
N_Blocks = ((N) / N_Threads);
}
else {
N_Blocks = ((N) / N_Threads) + 1;
}
dim3 Threads(N_Threads,N_Threads);
dim3 Blocks(N_Blocks, N_Blocks);
cudaEventCreate(&GPUstart);
cudaEventCreate(&GPUstop);
cudaEventRecord(GPUstart, 0);
cudaMemcpy(devA, hostA, mem_size, cudaMemcpyHostToDevice);
cudaMemcpy(devB, hostB, mem_size, cudaMemcpyHostToDevice);
cudaMemset(devC, 0, mem_size);
mult <<< Blocks, Threads >>> (devA, devB, devC);
cudaMemcpy(hostC, devC, mem_size, cudaMemcpyDeviceToHost);
cudaEventRecord(GPUstop, 0);
cudaEventSynchronize(GPUstop);
cudaEventElapsedTime(&GPUtime, GPUstart, GPUstop);
printf("GPU time : %.3f ms\n", GPUtime);
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
free(hostA);
free(hostB);
free(hostC);
return 0;
}
|
.file "tmpxft_00072109_00000000-6_Example3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4multPfS_S_PfS_S_
.type _Z27__device_stub__Z4multPfS_S_PfS_S_, @function
_Z27__device_stub__Z4multPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4multPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z4multPfS_S_PfS_S_, .-_Z27__device_stub__Z4multPfS_S_PfS_S_
.globl _Z4multPfS_S_
.type _Z4multPfS_S_, @function
_Z4multPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4multPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4multPfS_S_, .-_Z4multPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU time : %.3f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0x00000000, 20(%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %ebx
movl $0x00000000, %r14d
.L15:
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
movss %xmm1, 12(%rsp)
movd %r14d, %xmm2
ucomiss %xmm1, %xmm2
ja .L20
sqrtss %xmm1, %xmm1
movaps %xmm1, %xmm0
.L14:
movss %xmm0, 0(%r13,%rbx,4)
movss 12(%rsp), %xmm0
call sinf@PLT
movss %xmm0, (%r12,%rbx,4)
movl $0x00000000, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $1048576, %rbx
jne .L15
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $1, 72(%rsp)
movl $128, 76(%rsp)
movl $128, 80(%rsp)
movl $1, 84(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $4194304, %edx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movl $2, %ecx
movl $4194304, %edx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L14
.L22:
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z27__device_stub__Z4multPfS_S_PfS_S_
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4multPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4multPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N (1024)
__global__ void mult(float *A, float *B, float *C) {
unsigned int idx_X = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idx_Y = threadIdx.y + blockIdx.y * blockDim.y;
float sum = 0.;
if ((idx_X < N) && (idx_Y < N)) {
for (int i = 0; i < N; i++) {
sum += A[idx_X*N + i] * B[idx_Y + i*N];
}
C[idx_X*N + idx_Y] = sum;
}
}
int main(void) {
cudaEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *hostA, *hostB;
float *hostC;
float *devA, *devB;
float *devC;
size_t mem_size = N*N*sizeof(float);
hostA = (float *)malloc(mem_size);
hostB = (float *)malloc(mem_size);
hostC = (float *)malloc(mem_size);
cudaMalloc((void**)&devA, mem_size);
cudaMalloc((void**)&devB, mem_size);
cudaMalloc((void**)&devC, mem_size);
for (int i = 0; i < N*N; i++) {
hostA[i] = sqrtf(i);
hostB[i] = sinf(i);
hostC[i] = 0.;
}
int N_Threads = 8;
int N_Blocks = 0;
if (((N) % N_Threads) == 0) {
N_Blocks = ((N) / N_Threads);
}
else {
N_Blocks = ((N) / N_Threads) + 1;
}
dim3 Threads(N_Threads,N_Threads);
dim3 Blocks(N_Blocks, N_Blocks);
cudaEventCreate(&GPUstart);
cudaEventCreate(&GPUstop);
cudaEventRecord(GPUstart, 0);
cudaMemcpy(devA, hostA, mem_size, cudaMemcpyHostToDevice);
cudaMemcpy(devB, hostB, mem_size, cudaMemcpyHostToDevice);
cudaMemset(devC, 0, mem_size);
mult <<< Blocks, Threads >>> (devA, devB, devC);
cudaMemcpy(hostC, devC, mem_size, cudaMemcpyDeviceToHost);
cudaEventRecord(GPUstop, 0);
cudaEventSynchronize(GPUstop);
cudaEventElapsedTime(&GPUtime, GPUstart, GPUstop);
printf("GPU time : %.3f ms\n", GPUtime);
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
free(hostA);
free(hostB);
free(hostC);
return 0;
}
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N (1024)
__global__ void mult(float *A, float *B, float *C) {
unsigned int idx_X = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idx_Y = threadIdx.y + blockIdx.y * blockDim.y;
float sum = 0.;
if ((idx_X < N) && (idx_Y < N)) {
for (int i = 0; i < N; i++) {
sum += A[idx_X*N + i] * B[idx_Y + i*N];
}
C[idx_X*N + idx_Y] = sum;
}
}
int main(void) {
hipEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *hostA, *hostB;
float *hostC;
float *devA, *devB;
float *devC;
size_t mem_size = N*N*sizeof(float);
hostA = (float *)malloc(mem_size);
hostB = (float *)malloc(mem_size);
hostC = (float *)malloc(mem_size);
hipMalloc((void**)&devA, mem_size);
hipMalloc((void**)&devB, mem_size);
hipMalloc((void**)&devC, mem_size);
for (int i = 0; i < N*N; i++) {
hostA[i] = sqrtf(i);
hostB[i] = sinf(i);
hostC[i] = 0.;
}
int N_Threads = 8;
int N_Blocks = 0;
if (((N) % N_Threads) == 0) {
N_Blocks = ((N) / N_Threads);
}
else {
N_Blocks = ((N) / N_Threads) + 1;
}
dim3 Threads(N_Threads,N_Threads);
dim3 Blocks(N_Blocks, N_Blocks);
hipEventCreate(&GPUstart);
hipEventCreate(&GPUstop);
hipEventRecord(GPUstart, 0);
hipMemcpy(devA, hostA, mem_size, hipMemcpyHostToDevice);
hipMemcpy(devB, hostB, mem_size, hipMemcpyHostToDevice);
hipMemset(devC, 0, mem_size);
mult <<< Blocks, Threads >>> (devA, devB, devC);
hipMemcpy(hostC, devC, mem_size, hipMemcpyDeviceToHost);
hipEventRecord(GPUstop, 0);
hipEventSynchronize(GPUstop);
hipEventElapsedTime(&GPUtime, GPUstart, GPUstop);
printf("GPU time : %.3f ms\n", GPUtime);
hipFree(devA);
hipFree(devB);
hipFree(devC);
free(hostA);
free(hostB);
free(hostC);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N (1024)
__global__ void mult(float *A, float *B, float *C) {
unsigned int idx_X = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idx_Y = threadIdx.y + blockIdx.y * blockDim.y;
float sum = 0.;
if ((idx_X < N) && (idx_Y < N)) {
for (int i = 0; i < N; i++) {
sum += A[idx_X*N + i] * B[idx_Y + i*N];
}
C[idx_X*N + idx_Y] = sum;
}
}
int main(void) {
hipEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *hostA, *hostB;
float *hostC;
float *devA, *devB;
float *devC;
size_t mem_size = N*N*sizeof(float);
hostA = (float *)malloc(mem_size);
hostB = (float *)malloc(mem_size);
hostC = (float *)malloc(mem_size);
hipMalloc((void**)&devA, mem_size);
hipMalloc((void**)&devB, mem_size);
hipMalloc((void**)&devC, mem_size);
for (int i = 0; i < N*N; i++) {
hostA[i] = sqrtf(i);
hostB[i] = sinf(i);
hostC[i] = 0.;
}
int N_Threads = 8;
int N_Blocks = 0;
if (((N) % N_Threads) == 0) {
N_Blocks = ((N) / N_Threads);
}
else {
N_Blocks = ((N) / N_Threads) + 1;
}
dim3 Threads(N_Threads,N_Threads);
dim3 Blocks(N_Blocks, N_Blocks);
hipEventCreate(&GPUstart);
hipEventCreate(&GPUstop);
hipEventRecord(GPUstart, 0);
hipMemcpy(devA, hostA, mem_size, hipMemcpyHostToDevice);
hipMemcpy(devB, hostB, mem_size, hipMemcpyHostToDevice);
hipMemset(devC, 0, mem_size);
mult <<< Blocks, Threads >>> (devA, devB, devC);
hipMemcpy(hostC, devC, mem_size, hipMemcpyDeviceToHost);
hipEventRecord(GPUstop, 0);
hipEventSynchronize(GPUstop);
hipEventElapsedTime(&GPUtime, GPUstart, GPUstop);
printf("GPU time : %.3f ms\n", GPUtime);
hipFree(devA);
hipFree(devB);
hipFree(devC);
free(hostA);
free(hostB);
free(hostC);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4multPfS_S_
.globl _Z4multPfS_S_
.p2align 8
.type _Z4multPfS_S_,@function
_Z4multPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_or_b32_e32 v2, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x400, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 10, v0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v4, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, v5, s2
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v6, vcc_lo
v_add_nc_u32_e32 v2, 0x400, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
global_load_b32 v9, v[9:10], off
global_load_b32 v7, v[7:8], off
s_cmpk_eq_i32 s2, 0x1000
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v9, v7
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v0, 10, v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4multPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4multPfS_S_, .Lfunc_end0-_Z4multPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4multPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4multPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N (1024)
__global__ void mult(float *A, float *B, float *C) {
unsigned int idx_X = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idx_Y = threadIdx.y + blockIdx.y * blockDim.y;
float sum = 0.;
if ((idx_X < N) && (idx_Y < N)) {
for (int i = 0; i < N; i++) {
sum += A[idx_X*N + i] * B[idx_Y + i*N];
}
C[idx_X*N + idx_Y] = sum;
}
}
int main(void) {
hipEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *hostA, *hostB;
float *hostC;
float *devA, *devB;
float *devC;
size_t mem_size = N*N*sizeof(float);
hostA = (float *)malloc(mem_size);
hostB = (float *)malloc(mem_size);
hostC = (float *)malloc(mem_size);
hipMalloc((void**)&devA, mem_size);
hipMalloc((void**)&devB, mem_size);
hipMalloc((void**)&devC, mem_size);
for (int i = 0; i < N*N; i++) {
hostA[i] = sqrtf(i);
hostB[i] = sinf(i);
hostC[i] = 0.;
}
int N_Threads = 8;
int N_Blocks = 0;
if (((N) % N_Threads) == 0) {
N_Blocks = ((N) / N_Threads);
}
else {
N_Blocks = ((N) / N_Threads) + 1;
}
dim3 Threads(N_Threads,N_Threads);
dim3 Blocks(N_Blocks, N_Blocks);
hipEventCreate(&GPUstart);
hipEventCreate(&GPUstop);
hipEventRecord(GPUstart, 0);
hipMemcpy(devA, hostA, mem_size, hipMemcpyHostToDevice);
hipMemcpy(devB, hostB, mem_size, hipMemcpyHostToDevice);
hipMemset(devC, 0, mem_size);
mult <<< Blocks, Threads >>> (devA, devB, devC);
hipMemcpy(hostC, devC, mem_size, hipMemcpyDeviceToHost);
hipEventRecord(GPUstop, 0);
hipEventSynchronize(GPUstop);
hipEventElapsedTime(&GPUtime, GPUstart, GPUstop);
printf("GPU time : %.3f ms\n", GPUtime);
hipFree(devA);
hipFree(devB);
hipFree(devC);
free(hostA);
free(hostB);
free(hostC);
return 0;
}
|
.text
.file "Example3.hip"
.globl _Z19__device_stub__multPfS_S_ # -- Begin function _Z19__device_stub__multPfS_S_
.p2align 4, 0x90
.type _Z19__device_stub__multPfS_S_,@function
_Z19__device_stub__multPfS_S_: # @_Z19__device_stub__multPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4multPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__multPfS_S_, .Lfunc_end0-_Z19__device_stub__multPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 4(%rsp)
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %r12d, %r12d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # %call.sqrt
# in Loop: Header=BB1_1 Depth=1
movaps %xmm1, %xmm0
movss %xmm1, 44(%rsp) # 4-byte Spill
callq sqrtf
movss 44(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.LBB1_4: # %.split
# in Loop: Header=BB1_1 Depth=1
movss %xmm0, (%rbx,%r12,4)
movaps %xmm1, %xmm0
callq sinf
movss %xmm0, (%r14,%r12,4)
movl $0, (%r15,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
je .LBB1_5
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %r12d, %xmm1
ucomiss .LCPI1_0(%rip), %xmm1
jb .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
xorps %xmm0, %xmm0
sqrtss %xmm1, %xmm0
jmp .LBB1_4
.LBB1_5:
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4multPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4multPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4multPfS_S_,@object # @_Z4multPfS_S_
.section .rodata,"a",@progbits
.globl _Z4multPfS_S_
.p2align 3, 0x0
_Z4multPfS_S_:
.quad _Z19__device_stub__multPfS_S_
.size _Z4multPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU time : %.3f ms\n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4multPfS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__multPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4multPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4multPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fc400078e0200 */
/*0060*/ IMAD R0, R2, c[0x0][0x4], R5 ; /* 0x0000010002007a24 */
/* 0x002fca00078e0205 */
/*0070*/ LOP3.LUT P0, RZ, R3, 0xfffffc00, R0, 0xc8, !PT ; /* 0xfffffc0003ff7812 */
/* 0x000fda000780c800 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00a0*/ SHF.L.U32 R3, R3, 0xa, RZ ; /* 0x0000000a03037819 */
/* 0x000fe200000006ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R5, R0, 0x3c00, RZ ; /* 0x00003c0000057810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ MOV R29, RZ ; /* 0x000000ff001d7202 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fc60000000f00 */
/*00f0*/ IMAD.WIDE.U32 R6, R3, R2, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0002 */
/*0100*/ IADD3 R12, P0, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x000fe20007f1e0ff */
/*0110*/ HFMA2.MMA R6, -RZ, RZ, 0, 0.0078125 ; /* 0x00002000ff067435 */
/* 0x000fc600000001ff */
/*0120*/ IADD3.X R13, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fc800007fe4ff */
/*0130*/ IADD3 R9, R5.reuse, -0x3c00, RZ ; /* 0xffffc40005097810 */
/* 0x040fe20007ffe0ff */
/*0140*/ LDG.E R28, [R12.64+-0x20] ; /* 0xffffe0040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R11, R5.reuse, -0x3800, RZ ; /* 0xffffc800050b7810 */
/* 0x040fe40007ffe0ff */
/*0160*/ IADD3 R19, R5, -0x3400, RZ ; /* 0xffffcc0005137810 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.WIDE.U32 R8, R9, R2.reuse, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x080fe200078e0002 */
/*0180*/ LDG.E R26, [R12.64+-0x1c] ; /* 0xffffe4040c1a7981 */
/* 0x000ee6000c1e1900 */
/*0190*/ IMAD.WIDE.U32 R10, R11, R2, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe200078e0002 */
/*01a0*/ LDG.E R27, [R8.64] ; /* 0x00000004081b7981 */
/* 0x0000a2000c1e1900 */
/*01b0*/ IADD3 R21, R4, 0xc00, RZ ; /* 0x00000c0004157810 */
/* 0x000fc40007ffe0ff */
/*01c0*/ IMAD.WIDE.U32 R18, R19, R2.reuse, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x080fe200078e0002 */
/*01d0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x0002e2000c1e1900 */
/*01e0*/ IADD3 R17, R4.reuse, 0x1000, RZ ; /* 0x0000100004117810 */
/* 0x040fe40007ffe0ff */
/*01f0*/ IMAD.WIDE.U32 R20, R21, R2.reuse, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x080fe200078e0002 */
/*0200*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000968000c1e1900 */
/*0210*/ LDG.E R15, [R12.64+-0x18] ; /* 0xffffe8040c0f7981 */
/* 0x000f62000c1e1900 */
/*0220*/ IADD3 R25, R4, 0x1400, RZ ; /* 0x0000140004197810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.WIDE.U32 R16, R17, R2, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fc400078e0002 */
/*0240*/ LDG.E R7, [R20.64] ; /* 0x0000000414077981 */
/* 0x000368000c1e1900 */
/*0250*/ LDG.E R8, [R12.64+-0x14] ; /* 0xffffec040c087981 */
/* 0x001f62000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R24, R25, R2, c[0x0][0x168] ; /* 0x00005a0019187625 */
/* 0x000fe200078e0002 */
/*0270*/ IADD3 R19, R4.reuse, 0x1800, RZ ; /* 0x0000180004137810 */
/* 0x050fe40007ffe0ff */
/*0280*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R10, [R12.64+-0x10] ; /* 0xfffff0040c0a7981 */
/* 0x002f22000c1e1900 */
/*02a0*/ IADD3 R21, R4, 0x1c00, RZ ; /* 0x00001c0004157810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000322000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R16, R19, R2, c[0x0][0x168] ; /* 0x00005a0013107625 */
/* 0x001fc600078e0002 */
/*02d0*/ LDG.E R18, [R12.64+-0xc] ; /* 0xfffff4040c127981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000122000c1e1900 */
/*02f0*/ IMAD.WIDE.U32 R20, R21, R2, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fc600078e0002 */
/*0300*/ LDG.E R22, [R12.64+-0x8] ; /* 0xfffff8040c167981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000128000c1e1900 */
/*0320*/ LDG.E R20, [R12.64+-0x4] ; /* 0xfffffc040c147981 */
/* 0x001f22000c1e1900 */
/*0330*/ IADD3 R25, R4, 0x2000, RZ ; /* 0x0000200004197810 */
/* 0x002fe20007ffe0ff */
/*0340*/ FFMA R27, R27, R28, R29 ; /* 0x0000001c1b1b7223 */
/* 0x004fc8000000001d */
/*0350*/ FFMA R23, R23, R26, R27 ; /* 0x0000001a17177223 */
/* 0x008fe2000000001b */
/*0360*/ IADD3 R27, R4, 0x2400, RZ ; /* 0x00002400041b7810 */
/* 0x000fc60007ffe0ff */
/*0370*/ FFMA R23, R14, R15, R23 ; /* 0x0000000f0e177223 */
/* 0x020fe40000000017 */
/*0380*/ IMAD.WIDE.U32 R14, R25, R2, c[0x0][0x168] ; /* 0x00005a00190e7625 */
/* 0x000fe200078e0002 */
/*0390*/ IADD3 R25, R4, 0x2800, RZ ; /* 0x0000280004197810 */
/* 0x000fc60007ffe0ff */
/*03a0*/ IMAD.WIDE.U32 R16, R27, R2, c[0x0][0x168] ; /* 0x00005a001b107625 */
/* 0x000fe200078e0002 */
/*03b0*/ IADD3 R27, R4, 0x2c00, RZ ; /* 0x00002c00041b7810 */
/* 0x000fe20007ffe0ff */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*03d0*/ FFMA R8, R7, R8, R23 ; /* 0x0000000807087223 */
/* 0x000fe40000000017 */
/*03e0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0002a2000c1e1900 */
/*03f0*/ IMAD.WIDE.U32 R24, R25, R2, c[0x0][0x168] ; /* 0x00005a0019187625 */
/* 0x000fe200078e0002 */
/*0400*/ IADD3 R29, R5, -0xc00, RZ ; /* 0xfffff400051d7810 */
/* 0x000fe40007ffe0ff */
/*0410*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000762000c1e1900 */
/*0420*/ FFMA R10, R9, R10, R8 ; /* 0x0000000a090a7223 */
/* 0x010fc60000000008 */
/*0430*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000362000c1e1900 */
/*0440*/ IMAD.WIDE.U32 R26, R27, R2, c[0x0][0x168] ; /* 0x00005a001b1a7625 */
/* 0x000fc600078e0002 */
/*0450*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000962000c1e1900 */
/*0460*/ FFMA R10, R11, R18, R10 ; /* 0x000000120b0a7223 */
/* 0x000fe2000000000a */
/*0470*/ IADD3 R11, R5, -0x800, RZ ; /* 0xfffff800050b7810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LDG.E R15, [R12.64+0x8] ; /* 0x000008040c0f7981 */
/* 0x001362000c1e1900 */
/*0490*/ IMAD.WIDE.U32 R8, R29, R2, c[0x0][0x168] ; /* 0x00005a001d087625 */
/* 0x000fe200078e0002 */
/*04a0*/ IADD3 R18, R5, -0x400, RZ ; /* 0xfffffc0005127810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R28, R19, R22, R10 ; /* 0x00000016131c7223 */
/* 0x000fc6000000000a */
/*04d0*/ LDG.E R29, [R12.64+0xc] ; /* 0x00000c040c1d7981 */
/* 0x000362000c1e1900 */
/*04e0*/ IMAD.WIDE.U32 R10, R11, R2, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc600078e0002 */
/*04f0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0080e2000c1e1900 */
/*0500*/ IMAD.WIDE.U32 R18, R18, R2, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fc600078e0002 */
/*0510*/ LDG.E R22, [R12.64+0x10] ; /* 0x000010040c167981 */
/* 0x0002e8000c1e1900 */
/*0520*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0530*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0540*/ LDG.E R25, [R12.64+0x14] ; /* 0x000014040c197981 */
/* 0x010322000c1e1900 */
/*0550*/ IMAD.WIDE.U32 R8, R5, R2, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x001fc600078e0002 */
/*0560*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1900 */
/*0570*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x000328000c1e1900 */
/*0580*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f28000c1e1900 */
/*0590*/ LDG.E R20, [R12.64+0x1c] ; /* 0x00001c040c147981 */
/* 0x000322000c1e1900 */
/*05a0*/ IADD3 R6, R6, 0x4000, RZ ; /* 0x0000400006067810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.NE.AND P0, PT, R6, 0x102000, PT ; /* 0x001020000600780c */
/* 0x000fe40003f05270 */
/*05c0*/ IADD3 R12, P1, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fe40007f3e0ff */
/*05d0*/ IADD3 R5, R5, 0x4000, RZ ; /* 0x0000400005057810 */
/* 0x000fe40007ffe0ff */
/*05e0*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe40000ffe4ff */
/*05f0*/ IADD3 R4, R4, 0x4000, RZ ; /* 0x0000400004047810 */
/* 0x000fe20007ffe0ff */
/*0600*/ FFMA R7, R14, R7, R28 ; /* 0x000000070e077223 */
/* 0x004fc8000000001c */
/*0610*/ FFMA R7, R16, R23, R7 ; /* 0x0000001710077223 */
/* 0x020fc80000000007 */
/*0620*/ FFMA R7, R24, R15, R7 ; /* 0x0000000f18077223 */
/* 0x000fc80000000007 */
/*0630*/ FFMA R7, R26, R29, R7 ; /* 0x0000001d1a077223 */
/* 0x000fc80000000007 */
/*0640*/ FFMA R7, R17, R22, R7 ; /* 0x0000001611077223 */
/* 0x008fc80000000007 */
/*0650*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x010fc80000000007 */
/*0660*/ FFMA R7, R18, R21, R7 ; /* 0x0000001512077223 */
/* 0x000fc80000000007 */
/*0670*/ FFMA R29, R9, R20, R7 ; /* 0x00000014091d7223 */
/* 0x000fe20000000007 */
/*0680*/ @P0 BRA 0x130 ; /* 0xfffffaa000000947 */
/* 0x000fea000383ffff */
/*0690*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fca0007ffe0ff */
/*06a0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0002 */
/*06b0*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x000fe2000c101904 */
/*06c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06d0*/ BRA 0x6d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4multPfS_S_
.globl _Z4multPfS_S_
.p2align 8
.type _Z4multPfS_S_,@function
_Z4multPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_or_b32_e32 v2, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x400, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 10, v0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v4, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, v5, s2
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v6, vcc_lo
v_add_nc_u32_e32 v2, 0x400, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
global_load_b32 v9, v[9:10], off
global_load_b32 v7, v[7:8], off
s_cmpk_eq_i32 s2, 0x1000
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v9, v7
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v0, 10, v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4multPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4multPfS_S_, .Lfunc_end0-_Z4multPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4multPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4multPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00072109_00000000-6_Example3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4multPfS_S_PfS_S_
.type _Z27__device_stub__Z4multPfS_S_PfS_S_, @function
_Z27__device_stub__Z4multPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4multPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z4multPfS_S_PfS_S_, .-_Z27__device_stub__Z4multPfS_S_PfS_S_
.globl _Z4multPfS_S_
.type _Z4multPfS_S_, @function
_Z4multPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4multPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4multPfS_S_, .-_Z4multPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU time : %.3f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0x00000000, 20(%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %ebx
movl $0x00000000, %r14d
.L15:
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
movss %xmm1, 12(%rsp)
movd %r14d, %xmm2
ucomiss %xmm1, %xmm2
ja .L20
sqrtss %xmm1, %xmm1
movaps %xmm1, %xmm0
.L14:
movss %xmm0, 0(%r13,%rbx,4)
movss 12(%rsp), %xmm0
call sinf@PLT
movss %xmm0, (%r12,%rbx,4)
movl $0x00000000, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $1048576, %rbx
jne .L15
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $1, 72(%rsp)
movl $128, 76(%rsp)
movl $128, 80(%rsp)
movl $1, 84(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $4194304, %edx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movl $2, %ecx
movl $4194304, %edx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L14
.L22:
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z27__device_stub__Z4multPfS_S_PfS_S_
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4multPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4multPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "Example3.hip"
.globl _Z19__device_stub__multPfS_S_ # -- Begin function _Z19__device_stub__multPfS_S_
.p2align 4, 0x90
.type _Z19__device_stub__multPfS_S_,@function
_Z19__device_stub__multPfS_S_: # @_Z19__device_stub__multPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4multPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__multPfS_S_, .Lfunc_end0-_Z19__device_stub__multPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 4(%rsp)
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %r12d, %r12d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # %call.sqrt
# in Loop: Header=BB1_1 Depth=1
movaps %xmm1, %xmm0
movss %xmm1, 44(%rsp) # 4-byte Spill
callq sqrtf
movss 44(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.LBB1_4: # %.split
# in Loop: Header=BB1_1 Depth=1
movss %xmm0, (%rbx,%r12,4)
movaps %xmm1, %xmm0
callq sinf
movss %xmm0, (%r14,%r12,4)
movl $0, (%r15,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
je .LBB1_5
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %r12d, %xmm1
ucomiss .LCPI1_0(%rip), %xmm1
jb .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
xorps %xmm0, %xmm0
sqrtss %xmm1, %xmm0
jmp .LBB1_4
.LBB1_5:
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4multPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4multPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4multPfS_S_,@object # @_Z4multPfS_S_
.section .rodata,"a",@progbits
.globl _Z4multPfS_S_
.p2align 3, 0x0
_Z4multPfS_S_:
.quad _Z19__device_stub__multPfS_S_
.size _Z4multPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU time : %.3f ms\n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4multPfS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__multPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4multPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void plusMinus(int *size, const double *base, const float *deviation, double *a, float *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
a[ix] = base[ix] - deviation[ix];
b[ix] = base[ix] + deviation[ix];
}
}
|
code for sm_80
Function : _Z9plusMinusPiPKdPKfPdPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0070*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e240000002500 */
/*0080*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x0], R2 ; /* 0x0000000007027a25 */
/* 0x001fe200078e0002 */
/*0090*/ SHF.R.S32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x004fc80000011405 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fc80003f06070 */
/*00b0*/ ISETP.GE.AND.EX P0, PT, R3, R7, PT, P0 ; /* 0x000000070300720c */
/* 0x000fda0003f06300 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.SHL.U32 R14, R2.reuse, 0x4, RZ ; /* 0x00000004020e7824 */
/* 0x040fe200078e00ff */
/*00e0*/ SHF.L.U64.HI R15, R2, 0x2, R3 ; /* 0x00000002020f7819 */
/* 0x000fc80000010203 */
/*00f0*/ IADD3 R4, P0, R14, c[0x0][0x170], RZ ; /* 0x00005c000e047a10 */
/* 0x000fc80007f1e0ff */
/*0100*/ IADD3.X R5, R15, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000f057a10 */
/* 0x000fe200007fe4ff */
/*0110*/ IMAD.SHL.U32 R12, R2, 0x8, RZ ; /* 0x00000008020c7824 */
/* 0x000fc800078e00ff */
/*0120*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*0130*/ SHF.L.U64.HI R10, R2, 0x3, R3 ; /* 0x00000003020a7819 */
/* 0x000fe40000010203 */
/*0140*/ IADD3 R2, P0, R12, c[0x0][0x168], RZ ; /* 0x00005a000c027a10 */
/* 0x000fc80007f1e0ff */
/*0150*/ IADD3.X R3, R10, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000a037a10 */
/* 0x000fca00007fe4ff */
/*0160*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee2000c1e1b00 */
/*0170*/ IADD3 R12, P0, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0180*/ IADD3.X R13, R10, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a0d7a10 */
/* 0x000fe200007fe4ff */
/*0190*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x004ee40000201800 */
/*01a0*/ DADD R6, -R6, R8 ; /* 0x0000000006067229 */
/* 0x008e0e0000000108 */
/*01b0*/ STG.E.64 [R12.64], R6 ; /* 0x000000060c007986 */
/* 0x001fe8000c101b04 */
/*01c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee2000c1e1b00 */
/*01e0*/ F2F.F64.F32 R8, R4 ; /* 0x0000000400087310 */
/* 0x004ee40000201800 */
/*01f0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x008044000000000a */
/*0200*/ IADD3 R10, P0, R14, c[0x0][0x180], RZ ; /* 0x000060000e0a7a10 */
/* 0x001fc80007f1e0ff */
/*0210*/ IADD3.X R11, R15, c[0x0][0x184], RZ, P0, !PT ; /* 0x000061000f0b7a10 */
/* 0x000fc800007fe4ff */
/*0220*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x002e240000301000 */
/*0230*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x001fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void plusMinus(int *size, const double *base, const float *deviation, double *a, float *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
a[ix] = base[ix] - deviation[ix];
b[ix] = base[ix] + deviation[ix];
}
}
|
.file "tmpxft_0018d32a_00000000-6_plusMinus.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf
.type _Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf, @function
_Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9plusMinusPiPKdPKfPdPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf, .-_Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf
.globl _Z9plusMinusPiPKdPKfPdPf
.type _Z9plusMinusPiPKdPKfPdPf, @function
_Z9plusMinusPiPKdPKfPdPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9plusMinusPiPKdPKfPdPf, .-_Z9plusMinusPiPKdPKfPdPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9plusMinusPiPKdPKfPdPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9plusMinusPiPKdPKfPdPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void plusMinus(int *size, const double *base, const float *deviation, double *a, float *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
a[ix] = base[ix] - deviation[ix];
b[ix] = base[ix] + deviation[ix];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void plusMinus(int *size, const double *base, const float *deviation, double *a, float *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
a[ix] = base[ix] - deviation[ix];
b[ix] = base[ix] + deviation[ix];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void plusMinus(int *size, const double *base, const float *deviation, double *a, float *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
a[ix] = base[ix] - deviation[ix];
b[ix] = base[ix] + deviation[ix];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9plusMinusPiPKdPKfPdPf
.globl _Z9plusMinusPiPKdPKfPdPf
.p2align 8
.type _Z9plusMinusPiPKdPKfPdPf,@function
_Z9plusMinusPiPKdPKfPdPf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x34
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s15, v[0:1]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_b32 v8, v[4:5], off
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[6:7], v[4:5], off
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[8:9], v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[8:9]
global_store_b64 v[2:3], v[6:7], off
global_load_b64 v[2:3], v[4:5], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9plusMinusPiPKdPKfPdPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9plusMinusPiPKdPKfPdPf, .Lfunc_end0-_Z9plusMinusPiPKdPKfPdPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9plusMinusPiPKdPKfPdPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9plusMinusPiPKdPKfPdPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void plusMinus(int *size, const double *base, const float *deviation, double *a, float *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
a[ix] = base[ix] - deviation[ix];
b[ix] = base[ix] + deviation[ix];
}
}
|
.text
.file "plusMinus.hip"
.globl _Z24__device_stub__plusMinusPiPKdPKfPdPf # -- Begin function _Z24__device_stub__plusMinusPiPKdPKfPdPf
.p2align 4, 0x90
.type _Z24__device_stub__plusMinusPiPKdPKfPdPf,@function
_Z24__device_stub__plusMinusPiPKdPKfPdPf: # @_Z24__device_stub__plusMinusPiPKdPKfPdPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9plusMinusPiPKdPKfPdPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__plusMinusPiPKdPKfPdPf, .Lfunc_end0-_Z24__device_stub__plusMinusPiPKdPKfPdPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9plusMinusPiPKdPKfPdPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9plusMinusPiPKdPKfPdPf,@object # @_Z9plusMinusPiPKdPKfPdPf
.section .rodata,"a",@progbits
.globl _Z9plusMinusPiPKdPKfPdPf
.p2align 3, 0x0
_Z9plusMinusPiPKdPKfPdPf:
.quad _Z24__device_stub__plusMinusPiPKdPKfPdPf
.size _Z9plusMinusPiPKdPKfPdPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9plusMinusPiPKdPKfPdPf"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__plusMinusPiPKdPKfPdPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9plusMinusPiPKdPKfPdPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z9plusMinusPiPKdPKfPdPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0070*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e240000002500 */
/*0080*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x0], R2 ; /* 0x0000000007027a25 */
/* 0x001fe200078e0002 */
/*0090*/ SHF.R.S32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x004fc80000011405 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fc80003f06070 */
/*00b0*/ ISETP.GE.AND.EX P0, PT, R3, R7, PT, P0 ; /* 0x000000070300720c */
/* 0x000fda0003f06300 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.SHL.U32 R14, R2.reuse, 0x4, RZ ; /* 0x00000004020e7824 */
/* 0x040fe200078e00ff */
/*00e0*/ SHF.L.U64.HI R15, R2, 0x2, R3 ; /* 0x00000002020f7819 */
/* 0x000fc80000010203 */
/*00f0*/ IADD3 R4, P0, R14, c[0x0][0x170], RZ ; /* 0x00005c000e047a10 */
/* 0x000fc80007f1e0ff */
/*0100*/ IADD3.X R5, R15, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000f057a10 */
/* 0x000fe200007fe4ff */
/*0110*/ IMAD.SHL.U32 R12, R2, 0x8, RZ ; /* 0x00000008020c7824 */
/* 0x000fc800078e00ff */
/*0120*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*0130*/ SHF.L.U64.HI R10, R2, 0x3, R3 ; /* 0x00000003020a7819 */
/* 0x000fe40000010203 */
/*0140*/ IADD3 R2, P0, R12, c[0x0][0x168], RZ ; /* 0x00005a000c027a10 */
/* 0x000fc80007f1e0ff */
/*0150*/ IADD3.X R3, R10, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000a037a10 */
/* 0x000fca00007fe4ff */
/*0160*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee2000c1e1b00 */
/*0170*/ IADD3 R12, P0, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0180*/ IADD3.X R13, R10, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a0d7a10 */
/* 0x000fe200007fe4ff */
/*0190*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x004ee40000201800 */
/*01a0*/ DADD R6, -R6, R8 ; /* 0x0000000006067229 */
/* 0x008e0e0000000108 */
/*01b0*/ STG.E.64 [R12.64], R6 ; /* 0x000000060c007986 */
/* 0x001fe8000c101b04 */
/*01c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee2000c1e1b00 */
/*01e0*/ F2F.F64.F32 R8, R4 ; /* 0x0000000400087310 */
/* 0x004ee40000201800 */
/*01f0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x008044000000000a */
/*0200*/ IADD3 R10, P0, R14, c[0x0][0x180], RZ ; /* 0x000060000e0a7a10 */
/* 0x001fc80007f1e0ff */
/*0210*/ IADD3.X R11, R15, c[0x0][0x184], RZ, P0, !PT ; /* 0x000061000f0b7a10 */
/* 0x000fc800007fe4ff */
/*0220*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x002e240000301000 */
/*0230*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x001fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9plusMinusPiPKdPKfPdPf
.globl _Z9plusMinusPiPKdPKfPdPf
.p2align 8
.type _Z9plusMinusPiPKdPKfPdPf,@function
_Z9plusMinusPiPKdPKfPdPf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x34
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s15, v[0:1]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_b32 v8, v[4:5], off
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[6:7], v[4:5], off
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[8:9], v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[8:9]
global_store_b64 v[2:3], v[6:7], off
global_load_b64 v[2:3], v[4:5], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[8:9]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9plusMinusPiPKdPKfPdPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9plusMinusPiPKdPKfPdPf, .Lfunc_end0-_Z9plusMinusPiPKdPKfPdPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9plusMinusPiPKdPKfPdPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9plusMinusPiPKdPKfPdPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0018d32a_00000000-6_plusMinus.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf
.type _Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf, @function
_Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9plusMinusPiPKdPKfPdPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf, .-_Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf
.globl _Z9plusMinusPiPKdPKfPdPf
.type _Z9plusMinusPiPKdPKfPdPf, @function
_Z9plusMinusPiPKdPKfPdPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9plusMinusPiPKdPKfPdPfPiPKdPKfPdPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9plusMinusPiPKdPKfPdPf, .-_Z9plusMinusPiPKdPKfPdPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9plusMinusPiPKdPKfPdPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9plusMinusPiPKdPKfPdPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "plusMinus.hip"
.globl _Z24__device_stub__plusMinusPiPKdPKfPdPf # -- Begin function _Z24__device_stub__plusMinusPiPKdPKfPdPf
.p2align 4, 0x90
.type _Z24__device_stub__plusMinusPiPKdPKfPdPf,@function
_Z24__device_stub__plusMinusPiPKdPKfPdPf: # @_Z24__device_stub__plusMinusPiPKdPKfPdPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9plusMinusPiPKdPKfPdPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__plusMinusPiPKdPKfPdPf, .Lfunc_end0-_Z24__device_stub__plusMinusPiPKdPKfPdPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9plusMinusPiPKdPKfPdPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9plusMinusPiPKdPKfPdPf,@object # @_Z9plusMinusPiPKdPKfPdPf
.section .rodata,"a",@progbits
.globl _Z9plusMinusPiPKdPKfPdPf
.p2align 3, 0x0
_Z9plusMinusPiPKdPKfPdPf:
.quad _Z24__device_stub__plusMinusPiPKdPKfPdPf
.size _Z9plusMinusPiPKdPKfPdPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9plusMinusPiPKdPKfPdPf"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__plusMinusPiPKdPKfPdPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9plusMinusPiPKdPKfPdPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
__global__ void PDH_kernel3(unsigned long long* d_histogram,
double* d_atom_x_list, double* d_atom_y_list, double * d_atom_z_list,
long long acnt, double res)//,
//int numBlocks, int blockSize)
{
extern __shared__ double R[];
//the size of this should be 3*BLOCK_SIZE*sizeof(double), to house the three arrays in shared memory
//where t is a specific index into the 'atom' array
//
//the rth x array should be accessed by R[t + 3*BLOCK_SIZE]
//the rth y array should be accessed by R[t + BLOCK_SIZE + 3*BLOCK_SIZE]
//the rth z array should be accessed by R[t + BLOCK_SIZE*2 + 3*BLOCK_SIZE]
int cur_id = blockIdx.x * blockDim.x + threadIdx.x;
int i, j, h_pos;
//int i_id, j_id;
// int cur_id;
double Lx, Ly, Lz, Rt;//, Rx, Ry, Rz;
double dist;
if(cur_id < acnt)
{
Lx = d_atom_x_list[cur_id];
Ly = d_atom_y_list[cur_id];
Lz = d_atom_z_list[cur_id];
for(i = blockIdx.x +1; i < gridDim.x; i++)
{
cur_id = i * blockDim.x + threadIdx.x; //only valid threads may load into shared memory for block i
if(cur_id < acnt)
{
R[threadIdx.x] = d_atom_x_list[cur_id];
R[threadIdx.x + blockDim.x] = d_atom_y_list[cur_id];
R[threadIdx.x + blockDim.x*2] = d_atom_z_list[cur_id];
}
__syncthreads();
for(j = 0; j < blockDim.x; j++)
{
cur_id = i * blockDim.x + j; //now this prevents us from writing junk data for thread j
if(cur_id < acnt)
{
// Rx = R[j];
// Ry = R[j + blockDim.x];
// Rz = R[j + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[j];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[j + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[j + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
__syncthreads();
}
//now load the L values into R
R[threadIdx.x] = Lx;
R[threadIdx.x + blockDim.x] = Ly;
R[threadIdx.x + blockDim.x*2] = Lz;
__syncthreads();
for(i = threadIdx.x+ 1; i < blockDim.x; i++)
{
cur_id = blockIdx.x * blockDim.x + i; //we only proceed with valid threads for each thread i
if(cur_id < acnt)
{
// Rx = R[i];
// Ry = R[i + blockDim.x];
// Rz = R[i + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[i];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[i + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[i + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
}
}
|
.file "tmpxft_000bbdfa_00000000-6_kernel_3A.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd
.type _Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd, @function
_Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11PDH_kernel3PyPdS0_S0_xd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd, .-_Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd
.globl _Z11PDH_kernel3PyPdS0_S0_xd
.type _Z11PDH_kernel3PyPdS0_S0_xd, @function
_Z11PDH_kernel3PyPdS0_S0_xd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11PDH_kernel3PyPdS0_S0_xd, .-_Z11PDH_kernel3PyPdS0_S0_xd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11PDH_kernel3PyPdS0_S0_xd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11PDH_kernel3PyPdS0_S0_xd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
__global__ void PDH_kernel3(unsigned long long* d_histogram,
double* d_atom_x_list, double* d_atom_y_list, double * d_atom_z_list,
long long acnt, double res)//,
//int numBlocks, int blockSize)
{
extern __shared__ double R[];
//the size of this should be 3*BLOCK_SIZE*sizeof(double), to house the three arrays in shared memory
//where t is a specific index into the 'atom' array
//
//the rth x array should be accessed by R[t + 3*BLOCK_SIZE]
//the rth y array should be accessed by R[t + BLOCK_SIZE + 3*BLOCK_SIZE]
//the rth z array should be accessed by R[t + BLOCK_SIZE*2 + 3*BLOCK_SIZE]
int cur_id = blockIdx.x * blockDim.x + threadIdx.x;
int i, j, h_pos;
//int i_id, j_id;
// int cur_id;
double Lx, Ly, Lz, Rt;//, Rx, Ry, Rz;
double dist;
if(cur_id < acnt)
{
Lx = d_atom_x_list[cur_id];
Ly = d_atom_y_list[cur_id];
Lz = d_atom_z_list[cur_id];
for(i = blockIdx.x +1; i < gridDim.x; i++)
{
cur_id = i * blockDim.x + threadIdx.x; //only valid threads may load into shared memory for block i
if(cur_id < acnt)
{
R[threadIdx.x] = d_atom_x_list[cur_id];
R[threadIdx.x + blockDim.x] = d_atom_y_list[cur_id];
R[threadIdx.x + blockDim.x*2] = d_atom_z_list[cur_id];
}
__syncthreads();
for(j = 0; j < blockDim.x; j++)
{
cur_id = i * blockDim.x + j; //now this prevents us from writing junk data for thread j
if(cur_id < acnt)
{
// Rx = R[j];
// Ry = R[j + blockDim.x];
// Rz = R[j + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[j];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[j + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[j + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
__syncthreads();
}
//now load the L values into R
R[threadIdx.x] = Lx;
R[threadIdx.x + blockDim.x] = Ly;
R[threadIdx.x + blockDim.x*2] = Lz;
__syncthreads();
for(i = threadIdx.x+ 1; i < blockDim.x; i++)
{
cur_id = blockIdx.x * blockDim.x + i; //we only proceed with valid threads for each thread i
if(cur_id < acnt)
{
// Rx = R[i];
// Ry = R[i + blockDim.x];
// Rz = R[i + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[i];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[i + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[i + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
}
}
|
#include <hip/hip_runtime.h>
__global__ void PDH_kernel3(unsigned long long* d_histogram,
double* d_atom_x_list, double* d_atom_y_list, double * d_atom_z_list,
long long acnt, double res)//,
//int numBlocks, int blockSize)
{
extern __shared__ double R[];
//the size of this should be 3*BLOCK_SIZE*sizeof(double), to house the three arrays in shared memory
//where t is a specific index into the 'atom' array
//
//the rth x array should be accessed by R[t + 3*BLOCK_SIZE]
//the rth y array should be accessed by R[t + BLOCK_SIZE + 3*BLOCK_SIZE]
//the rth z array should be accessed by R[t + BLOCK_SIZE*2 + 3*BLOCK_SIZE]
int cur_id = blockIdx.x * blockDim.x + threadIdx.x;
int i, j, h_pos;
//int i_id, j_id;
// int cur_id;
double Lx, Ly, Lz, Rt;//, Rx, Ry, Rz;
double dist;
if(cur_id < acnt)
{
Lx = d_atom_x_list[cur_id];
Ly = d_atom_y_list[cur_id];
Lz = d_atom_z_list[cur_id];
for(i = blockIdx.x +1; i < gridDim.x; i++)
{
cur_id = i * blockDim.x + threadIdx.x; //only valid threads may load into shared memory for block i
if(cur_id < acnt)
{
R[threadIdx.x] = d_atom_x_list[cur_id];
R[threadIdx.x + blockDim.x] = d_atom_y_list[cur_id];
R[threadIdx.x + blockDim.x*2] = d_atom_z_list[cur_id];
}
__syncthreads();
for(j = 0; j < blockDim.x; j++)
{
cur_id = i * blockDim.x + j; //now this prevents us from writing junk data for thread j
if(cur_id < acnt)
{
// Rx = R[j];
// Ry = R[j + blockDim.x];
// Rz = R[j + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[j];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[j + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[j + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
__syncthreads();
}
//now load the L values into R
R[threadIdx.x] = Lx;
R[threadIdx.x + blockDim.x] = Ly;
R[threadIdx.x + blockDim.x*2] = Lz;
__syncthreads();
for(i = threadIdx.x+ 1; i < blockDim.x; i++)
{
cur_id = blockIdx.x * blockDim.x + i; //we only proceed with valid threads for each thread i
if(cur_id < acnt)
{
// Rx = R[i];
// Ry = R[i + blockDim.x];
// Rz = R[i + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[i];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[i + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[i + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
__global__ void PDH_kernel3(unsigned long long* d_histogram,
double* d_atom_x_list, double* d_atom_y_list, double * d_atom_z_list,
long long acnt, double res)//,
//int numBlocks, int blockSize)
{
extern __shared__ double R[];
//the size of this should be 3*BLOCK_SIZE*sizeof(double), to house the three arrays in shared memory
//where t is a specific index into the 'atom' array
//
//the rth x array should be accessed by R[t + 3*BLOCK_SIZE]
//the rth y array should be accessed by R[t + BLOCK_SIZE + 3*BLOCK_SIZE]
//the rth z array should be accessed by R[t + BLOCK_SIZE*2 + 3*BLOCK_SIZE]
int cur_id = blockIdx.x * blockDim.x + threadIdx.x;
int i, j, h_pos;
//int i_id, j_id;
// int cur_id;
double Lx, Ly, Lz, Rt;//, Rx, Ry, Rz;
double dist;
if(cur_id < acnt)
{
Lx = d_atom_x_list[cur_id];
Ly = d_atom_y_list[cur_id];
Lz = d_atom_z_list[cur_id];
for(i = blockIdx.x +1; i < gridDim.x; i++)
{
cur_id = i * blockDim.x + threadIdx.x; //only valid threads may load into shared memory for block i
if(cur_id < acnt)
{
R[threadIdx.x] = d_atom_x_list[cur_id];
R[threadIdx.x + blockDim.x] = d_atom_y_list[cur_id];
R[threadIdx.x + blockDim.x*2] = d_atom_z_list[cur_id];
}
__syncthreads();
for(j = 0; j < blockDim.x; j++)
{
cur_id = i * blockDim.x + j; //now this prevents us from writing junk data for thread j
if(cur_id < acnt)
{
// Rx = R[j];
// Ry = R[j + blockDim.x];
// Rz = R[j + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[j];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[j + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[j + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
__syncthreads();
}
//now load the L values into R
R[threadIdx.x] = Lx;
R[threadIdx.x + blockDim.x] = Ly;
R[threadIdx.x + blockDim.x*2] = Lz;
__syncthreads();
for(i = threadIdx.x+ 1; i < blockDim.x; i++)
{
cur_id = blockIdx.x * blockDim.x + i; //we only proceed with valid threads for each thread i
if(cur_id < acnt)
{
// Rx = R[i];
// Ry = R[i + blockDim.x];
// Rz = R[i + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[i];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[i + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[i + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11PDH_kernel3PyPdS0_S0_xd
.globl _Z11PDH_kernel3PyPdS0_S0_xd
.p2align 8
.type _Z11PDH_kernel3PyPdS0_S0_xd,@function
_Z11PDH_kernel3PyPdS0_S0_xd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x20
s_add_u32 s12, s0, 48
s_addc_u32 s13, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s4, 0xffff
s_mov_b32 s4, exec_lo
s_mul_i32 s16, s15, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s16, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_16
s_load_b256 s[4:11], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_nc_u32_e32 v9, s14, v0
s_add_i32 s15, s15, 1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v2, vcc_lo
global_load_b64 v[1:2], v[3:4], off
global_load_b64 v[3:4], v[5:6], off
global_load_b64 v[5:6], v[7:8], off
s_load_b32 s17, s[12:13], 0x0
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s17
s_cbranch_scc1 .LBB0_11
v_lshl_add_u32 v7, s14, 1, v0
s_cmp_lg_u32 s14, 0
v_lshl_add_u32 v10, v0, 3, 0
v_lshl_add_u32 v11, v9, 3, 0
s_cselect_b32 s18, -1, 0
v_lshl_add_u32 v12, v7, 3, 0
s_lshl_b32 s19, s14, 3
s_lshl_b32 s12, s14, 4
s_add_i32 s21, s19, 0
s_add_i32 s20, s12, 0
s_mul_i32 s22, s15, s14
s_branch .LBB0_4
.LBB0_3:
s_add_i32 s15, s15, 1
s_add_i32 s22, s22, s14
s_cmp_lt_u32 s15, s17
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_11
.LBB0_4:
s_waitcnt vmcnt(2)
v_mad_u64_u32 v[7:8], null, s15, s14, v[0:1]
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_cmpx_gt_i64_e64 s[2:3], v[7:8]
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v15, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
global_load_b64 v[13:14], v[13:14], off
global_load_b64 v[15:16], v[15:16], off
global_load_b64 v[7:8], v[7:8], off
s_waitcnt vmcnt(2)
ds_store_b64 v10, v[13:14]
s_waitcnt vmcnt(1)
ds_store_b64 v11, v[15:16]
s_waitcnt vmcnt(0)
ds_store_b64 v12, v[7:8]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s18
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_3
s_mov_b32 s23, 0
s_mov_b32 s12, s22
s_branch .LBB0_9
.LBB0_8:
s_add_i32 s23, s23, 8
s_add_i32 s12, s12, 1
s_cmp_lg_u32 s19, s23
s_cbranch_scc0 .LBB0_3
.LBB0_9:
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i64_e64 s13, s[12:13], s[2:3]
s_and_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_8
s_add_i32 s13, s21, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v7, s13
s_add_i32 s13, s20, s23
v_mov_b32_e32 v13, s13
s_add_i32 s13, s23, 0
ds_load_b64 v[7:8], v7
v_mov_b32_e32 v15, s13
ds_load_b64 v[13:14], v13
ds_load_b64 v[15:16], v15
s_waitcnt lgkmcnt(2)
v_add_f64 v[7:8], v[3:4], -v[7:8]
s_waitcnt lgkmcnt(1)
v_add_f64 v[13:14], v[5:6], -v[13:14]
s_waitcnt lgkmcnt(0)
v_add_f64 v[15:16], v[1:2], -v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[7:8], v[7:8]
v_fma_f64 v[7:8], v[15:16], v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[13:14], v[13:14], v[7:8]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[7:8]
v_cndmask_b32_e64 v13, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v13, 8, v13
v_ldexp_f64 v[7:8], v[7:8], v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[13:14], v[7:8]
s_waitcnt_depctr 0xfff
v_mul_f64 v[15:16], v[7:8], v[13:14]
v_mul_f64 v[13:14], v[13:14], 0.5
v_fma_f64 v[17:18], -v[13:14], v[15:16], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
v_fma_f64 v[17:18], -v[15:16], v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[17:18], v[13:14], v[15:16]
v_fma_f64 v[17:18], -v[15:16], v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[13:14], v[17:18], v[13:14], v[15:16]
v_cndmask_b32_e64 v15, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[7:8], 0x260
v_ldexp_f64 v[13:14], v[13:14], v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v8, v14, v8 :: v_dual_cndmask_b32 v7, v13, v7
v_div_scale_f64 v[13:14], null, s[0:1], s[0:1], v[7:8]
v_div_scale_f64 v[19:20], vcc_lo, v[7:8], s[0:1], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[15:16], v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[19:20], v[15:16]
v_fma_f64 v[13:14], -v[13:14], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[17:18]
v_div_fixup_f64 v[7:8], v[13:14], s[0:1], v[7:8]
v_mov_b32_e32 v13, 1
v_mov_b32_e32 v14, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v7, v[7:8]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_atomic_add_u64 v[7:8], v[13:14], off
s_branch .LBB0_8
.LBB0_11:
v_lshl_add_u32 v8, s14, 1, v0
v_add_nc_u32_e32 v7, 1, v0
v_lshl_add_u32 v10, v0, 3, 0
v_lshl_add_u32 v9, v9, 3, 0
s_mov_b32 s6, 0
v_lshl_add_u32 v8, v8, 3, 0
v_cmp_gt_u32_e32 vcc_lo, s14, v7
s_waitcnt vmcnt(2)
ds_store_b64 v10, v[1:2]
s_waitcnt vmcnt(1)
ds_store_b64 v9, v[3:4]
s_waitcnt vmcnt(0)
ds_store_b64 v8, v[5:6]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_16
v_add_lshl_u32 v8, v0, s14, 3
v_lshlrev_b32_e32 v9, 3, v0
s_lshl_b32 s7, s14, 4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v0, v8, 0, 8
v_add3_u32 v8, v9, 0, 8
s_branch .LBB0_14
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v7, 1, v7
v_add_nc_u32_e32 v0, 8, v0
v_add_nc_u32_e32 v8, 8, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s14, v7
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_16
.LBB0_14:
v_add_nc_u32_e32 v9, s16, v7
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_cmpx_gt_i64_e64 s[2:3], v[9:10]
s_cbranch_execz .LBB0_13
ds_load_b64 v[9:10], v0
ds_load_b64 v[11:12], v8
v_add_nc_u32_e32 v13, s7, v8
ds_load_b64 v[13:14], v13
s_waitcnt lgkmcnt(2)
v_add_f64 v[9:10], v[3:4], -v[9:10]
s_waitcnt lgkmcnt(1)
v_add_f64 v[11:12], v[1:2], -v[11:12]
s_waitcnt lgkmcnt(0)
v_add_f64 v[13:14], v[5:6], -v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[9:10], v[9:10]
v_fma_f64 v[9:10], v[11:12], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[13:14], v[13:14], v[9:10]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[9:10]
v_cndmask_b32_e64 v11, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v11, 8, v11
v_ldexp_f64 v[9:10], v[9:10], v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_mul_f64 v[13:14], v[9:10], v[11:12]
v_mul_f64 v[11:12], v[11:12], 0.5
v_fma_f64 v[15:16], -v[11:12], v[13:14], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
v_fma_f64 v[15:16], -v[13:14], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[15:16], v[11:12], v[13:14]
v_fma_f64 v[15:16], -v[13:14], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[11:12], v[15:16], v[11:12], v[13:14]
v_cndmask_b32_e64 v13, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[9:10], 0x260
v_ldexp_f64 v[11:12], v[11:12], v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v10, v12, v10 :: v_dual_cndmask_b32 v9, v11, v9
v_div_scale_f64 v[11:12], null, s[0:1], s[0:1], v[9:10]
v_div_scale_f64 v[17:18], vcc_lo, v[9:10], s[0:1], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[17:18], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
v_div_fixup_f64 v[9:10], v[11:12], s[0:1], v[9:10]
v_mov_b32_e32 v11, 1
v_mov_b32_e32 v12, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v9, v[9:10]
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_atomic_add_u64 v[9:10], v[11:12], off
s_branch .LBB0_13
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11PDH_kernel3PyPdS0_S0_xd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11PDH_kernel3PyPdS0_S0_xd, .Lfunc_end0-_Z11PDH_kernel3PyPdS0_S0_xd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
- .offset: 168
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11PDH_kernel3PyPdS0_S0_xd
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z11PDH_kernel3PyPdS0_S0_xd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
__global__ void PDH_kernel3(unsigned long long* d_histogram,
double* d_atom_x_list, double* d_atom_y_list, double * d_atom_z_list,
long long acnt, double res)//,
//int numBlocks, int blockSize)
{
extern __shared__ double R[];
//the size of this should be 3*BLOCK_SIZE*sizeof(double), to house the three arrays in shared memory
//where t is a specific index into the 'atom' array
//
//the rth x array should be accessed by R[t + 3*BLOCK_SIZE]
//the rth y array should be accessed by R[t + BLOCK_SIZE + 3*BLOCK_SIZE]
//the rth z array should be accessed by R[t + BLOCK_SIZE*2 + 3*BLOCK_SIZE]
int cur_id = blockIdx.x * blockDim.x + threadIdx.x;
int i, j, h_pos;
//int i_id, j_id;
// int cur_id;
double Lx, Ly, Lz, Rt;//, Rx, Ry, Rz;
double dist;
if(cur_id < acnt)
{
Lx = d_atom_x_list[cur_id];
Ly = d_atom_y_list[cur_id];
Lz = d_atom_z_list[cur_id];
for(i = blockIdx.x +1; i < gridDim.x; i++)
{
cur_id = i * blockDim.x + threadIdx.x; //only valid threads may load into shared memory for block i
if(cur_id < acnt)
{
R[threadIdx.x] = d_atom_x_list[cur_id];
R[threadIdx.x + blockDim.x] = d_atom_y_list[cur_id];
R[threadIdx.x + blockDim.x*2] = d_atom_z_list[cur_id];
}
__syncthreads();
for(j = 0; j < blockDim.x; j++)
{
cur_id = i * blockDim.x + j; //now this prevents us from writing junk data for thread j
if(cur_id < acnt)
{
// Rx = R[j];
// Ry = R[j + blockDim.x];
// Rz = R[j + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[j];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[j + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[j + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
__syncthreads();
}
//now load the L values into R
R[threadIdx.x] = Lx;
R[threadIdx.x + blockDim.x] = Ly;
R[threadIdx.x + blockDim.x*2] = Lz;
__syncthreads();
for(i = threadIdx.x+ 1; i < blockDim.x; i++)
{
cur_id = blockIdx.x * blockDim.x + i; //we only proceed with valid threads for each thread i
if(cur_id < acnt)
{
// Rx = R[i];
// Ry = R[i + blockDim.x];
// Rz = R[i + blockDim.x*2];
// dist = sqrt((Lx - Rx)*(Lx-Rx) + (Ly - Ry)*(Ly - Ry) + (Lz - Rz)*(Lz - Rz));
dist = 0.0;
//Rx
Rt = Lx - R[i];
Rt *= Rt;
dist += Rt;
//Ry
Rt = Ly - R[i + blockDim.x];
Rt *= Rt;
dist += Rt;
//Rz
Rt = Lz - R[i + blockDim.x*2];
Rt *= Rt;
dist += Rt;
dist = sqrt(dist);
h_pos = (int)(dist/res);
atomicAdd(&d_histogram[h_pos], 1);
}
}
}
}
|
.text
.file "kernel_3A.hip"
.globl _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd # -- Begin function _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.p2align 4, 0x90
.type _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd,@function
_Z26__device_stub__PDH_kernel3PyPdS0_S0_xd: # @_Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11PDH_kernel3PyPdS0_S0_xd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd, .Lfunc_end0-_Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11PDH_kernel3PyPdS0_S0_xd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11PDH_kernel3PyPdS0_S0_xd,@object # @_Z11PDH_kernel3PyPdS0_S0_xd
.section .rodata,"a",@progbits
.globl _Z11PDH_kernel3PyPdS0_S0_xd
.p2align 3, 0x0
_Z11PDH_kernel3PyPdS0_S0_xd:
.quad _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.size _Z11PDH_kernel3PyPdS0_S0_xd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11PDH_kernel3PyPdS0_S0_xd"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11PDH_kernel3PyPdS0_S0_xd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000bbdfa_00000000-6_kernel_3A.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd
.type _Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd, @function
_Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11PDH_kernel3PyPdS0_S0_xd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd, .-_Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd
.globl _Z11PDH_kernel3PyPdS0_S0_xd
.type _Z11PDH_kernel3PyPdS0_S0_xd, @function
_Z11PDH_kernel3PyPdS0_S0_xd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11PDH_kernel3PyPdS0_S0_xdPyPdS0_S0_xd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11PDH_kernel3PyPdS0_S0_xd, .-_Z11PDH_kernel3PyPdS0_S0_xd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11PDH_kernel3PyPdS0_S0_xd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11PDH_kernel3PyPdS0_S0_xd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel_3A.hip"
.globl _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd # -- Begin function _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.p2align 4, 0x90
.type _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd,@function
_Z26__device_stub__PDH_kernel3PyPdS0_S0_xd: # @_Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11PDH_kernel3PyPdS0_S0_xd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd, .Lfunc_end0-_Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11PDH_kernel3PyPdS0_S0_xd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11PDH_kernel3PyPdS0_S0_xd,@object # @_Z11PDH_kernel3PyPdS0_S0_xd
.section .rodata,"a",@progbits
.globl _Z11PDH_kernel3PyPdS0_S0_xd
.p2align 3, 0x0
_Z11PDH_kernel3PyPdS0_S0_xd:
.quad _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.size _Z11PDH_kernel3PyPdS0_S0_xd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11PDH_kernel3PyPdS0_S0_xd"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__PDH_kernel3PyPdS0_S0_xd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11PDH_kernel3PyPdS0_S0_xd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// #include "vec.cuh"
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::WC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::BC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// #include "vec.cuh"
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::WC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::BC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
|
.file "tmpxft_000d9ca5_00000000-6_vec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// #include "vec.cuh"
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::WC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::BC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
|
#include <hip/hip_runtime.h>
// #include "vec.cuh"
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::WC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::BC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
// #include "vec.cuh"
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::WC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::BC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
// #include "vec.cuh"
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::WC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
// template <>
// template <> __device__ void Vector_gmem<char>::CleanData<ExecutionPolicy::BC>() {
// for (size_t i = LTID; i < *size; i += blockDim.x) {
// data[i] = 0;
// }
// }
|
.text
.file "vec.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000d9ca5_00000000-6_vec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "vec.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <assert.h>
#include <curand.h>
#include <curand_kernel.h>
#include <time.h>
#include <sys/time.h>
// Placeholder for longer list of primes
struct list_node{
unsigned long long value;
list_node* next;
};
list_node* prime_list;
// List of primes less than 100 to be checked for divisibility
__device__ const unsigned long long small_primes[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97};
__device__ const int small_primes_size = 25;
// Function prototypes
__device__ bool basic_test(unsigned long long);
__device__ bool exact_test(unsigned long long);
__device__ bool fermat_test(unsigned long long, curandState state);
__device__ bool miller_rabin_test(unsigned long long);
///////////////////////////////////////////////////////////////////////////////
// Kernel functions
///////////////////////////////////////////////////////////////////////////////
// Generate an initial list of numbers to test for primality
// start must be a multiple of 6 for this to be correct
__global__ void primeCandidates(int count, unsigned long long start, unsigned long long* list)
{
for(int i = count/2*threadIdx.x; i < count/2*(threadIdx.x+1); i++){
list[2*i] = start + 6*i - 1;
list[(2*i)+1] = start + 6*i + 1;
}
}
// Perform basic filters to eliminate obvious composite numbers.
__global__ void filterCandidates(int count, unsigned long long* list){
for(int i = count*threadIdx.x; i < count*(threadIdx.x+1); i++){
if (!(basic_test(list[i]))){
list[i] = 0;
}
}
}
// Perform more rigorous tests to confirm a number is prime
__global__ void testCandidates(int count, unsigned long long* list){
int idx = threadIdx.x;
curandState state;
curand_init(idx, idx, 0, &state);
for(int i = threadIdx.x * count; i < (threadIdx.x + 1)*count; i++){
// int exact = 1;
if (list[i] == 0) continue;
// if (!exact_test(list[i])) exact = 0;
if (!fermat_test(list[i], state)){
// if(exact) printf(" %d\n",list[i]);
list[i] = 0;
}
else{
// if(!exact) printf(" %d\n",list[i]);
}
}
}
///////////////////////////////////////////////////////////////////////////////
// Device helper functions
///////////////////////////////////////////////////////////////////////////////
// Tests for divisibility against the list of small primes
__device__ bool basic_test(unsigned long long n){
for(int i = 0; i < small_primes_size; i++){
if (!(n % small_primes[i])) return false;
}
return true;
}
// Exhaustively search possible divisors to confirm a number is prime.
__device__ bool exact_test(unsigned long long n){
for(unsigned long long i = 101; i * i <= n; i += 2){
if (!(n % i)) return false;
}
return true;
}
// Perform Fermat's primality test for a given number
__device__ bool fermat_test(unsigned long long n, curandState state){
int k = 10;
for(int i = 0; i < k; i++){
double x = curand_uniform_double(&state);
unsigned long long a = x * (n-4) + 2;
unsigned long long b = 1;
unsigned long long e = n-1;
while(e > 0){
if (e & 1) b = (b * a) % n;
e >>= 1;
a = (a * a) % n;
}
if (b != 1) return false;
}
return true;
}
// Perform the Miller-Rabin primality test for a given number
__device__ bool miller_rabin_test(unsigned long long n){
return false;
}
///////////////////////////////////////////////////////////////////////////////
// Host helpers
///////////////////////////////////////////////////////////////////////////////
// Placeholder for building linked list of primes
void build_primes(unsigned long long start){
list_node* node;
cudaMalloc((void**)&node, sizeof(list_node));
node->value = 2;
node->next = NULL;
prime_list = node;
for(int i = 3; i * i < start; i+= 2){
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
// Initialization
const int count = 3200;
// Ints to process per thread. Must be even
const int num_threads = 32; // Threads to launch in a single 1-D block
const int list_size = count * num_threads;
const unsigned long long start = 6;
unsigned long long* list; // Device pointer to potential primes
cudaMalloc((void**)&list, list_size * sizeof(unsigned long long));
dim3 gridSize(1,1,1);
dim3 blockSize(num_threads, 1, 1);
struct timeval tv;
struct timezone tz;
clock_t startTime, endTime, elapsedTime;
double timeInSeconds;
long GTODStartTime, GTODEndTime;
startTime = clock();
gettimeofday(&tv, &tz);
GTODStartTime = tv.tv_sec * 1000 + tv.tv_usec / 1000;
// First, generate a list of prime candidates
primeCandidates<<<gridSize, blockSize>>>(count, start, list);
// Second, filter the candidates to quickly eliminate composites
filterCandidates<<<gridSize, blockSize>>>(count, list);
// Third, confirm if candidates are actually prime
testCandidates<<<gridSize, blockSize>>>(count, list);
gettimeofday(&tv, &tz);
GTODEndTime = tv.tv_sec * 1000 + tv.tv_usec / 1000;
endTime = clock();
elapsedTime = endTime - startTime;
timeInSeconds = (elapsedTime / (double)CLOCKS_PER_SEC);
printf(" GetTimeOfDay Time= %g\n", (double)(GTODEndTime - GTODStartTime) / 1000.0);
printf(" Clock Time = %g\n", timeInSeconds);
// Copy list back and display (for debugging)
unsigned long long h_list[list_size];
cudaMemcpy(h_list, list, list_size * sizeof(unsigned long long), cudaMemcpyDeviceToHost);
int nprimes = 0;
for(int i = 0; i < list_size; i++){
if (h_list[i] != 0) {
// printf("%llu\n",h_list[i]);
nprimes++;
}
}
printf("Number of primes: %d\n",nprimes);
return 0;
}
|
.file "tmpxft_00194c83_00000000-6_primes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2279:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2279:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10basic_testy
.type _Z10basic_testy, @function
_Z10basic_testy:
.LFB2271:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2271:
.size _Z10basic_testy, .-_Z10basic_testy
.globl _Z10exact_testy
.type _Z10exact_testy, @function
_Z10exact_testy:
.LFB2272:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2272:
.size _Z10exact_testy, .-_Z10exact_testy
.globl _Z11fermat_testy17curandStateXORWOW
.type _Z11fermat_testy17curandStateXORWOW, @function
_Z11fermat_testy17curandStateXORWOW:
.LFB2273:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2273:
.size _Z11fermat_testy17curandStateXORWOW, .-_Z11fermat_testy17curandStateXORWOW
.globl _Z17miller_rabin_testy
.type _Z17miller_rabin_testy, @function
_Z17miller_rabin_testy:
.LFB2274:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2274:
.size _Z17miller_rabin_testy, .-_Z17miller_rabin_testy
.globl _Z12build_primesy
.type _Z12build_primesy, @function
_Z12build_primesy:
.LFB2275:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
movq (%rsp), %rax
movq $2, (%rax)
movq (%rsp), %rax
movq $0, 8(%rax)
movq %rax, prime_list(%rip)
cmpq $9, %rbx
jbe .L11
movl $3, %eax
.L13:
addl $2, %eax
movl %eax, %edx
imull %eax, %edx
movslq %edx, %rdx
cmpq %rbx, %rdx
jb .L13
.L11:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2275:
.size _Z12build_primesy, .-_Z12build_primesy
.globl _Z37__device_stub__Z15primeCandidatesiyPyiyPy
.type _Z37__device_stub__Z15primeCandidatesiyPyiyPy, @function
_Z37__device_stub__Z15primeCandidatesiyPyiyPy:
.LFB2301:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15primeCandidatesiyPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2301:
.size _Z37__device_stub__Z15primeCandidatesiyPyiyPy, .-_Z37__device_stub__Z15primeCandidatesiyPyiyPy
.globl _Z15primeCandidatesiyPy
.type _Z15primeCandidatesiyPy, @function
_Z15primeCandidatesiyPy:
.LFB2302:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15primeCandidatesiyPyiyPy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _Z15primeCandidatesiyPy, .-_Z15primeCandidatesiyPy
.globl _Z37__device_stub__Z16filterCandidatesiPyiPy
.type _Z37__device_stub__Z16filterCandidatesiPyiPy, @function
_Z37__device_stub__Z16filterCandidatesiPyiPy:
.LFB2303:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16filterCandidatesiPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2303:
.size _Z37__device_stub__Z16filterCandidatesiPyiPy, .-_Z37__device_stub__Z16filterCandidatesiPyiPy
.globl _Z16filterCandidatesiPy
.type _Z16filterCandidatesiPy, @function
_Z16filterCandidatesiPy:
.LFB2304:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16filterCandidatesiPyiPy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2304:
.size _Z16filterCandidatesiPy, .-_Z16filterCandidatesiPy
.globl _Z35__device_stub__Z14testCandidatesiPyiPy
.type _Z35__device_stub__Z14testCandidatesiPyiPy, @function
_Z35__device_stub__Z14testCandidatesiPyiPy:
.LFB2305:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14testCandidatesiPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2305:
.size _Z35__device_stub__Z14testCandidatesiPyiPy, .-_Z35__device_stub__Z14testCandidatesiPyiPy
.globl _Z14testCandidatesiPy
.type _Z14testCandidatesiPy, @function
_Z14testCandidatesiPy:
.LFB2306:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14testCandidatesiPyiPy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2306:
.size _Z14testCandidatesiPy, .-_Z14testCandidatesiPy
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string " GetTimeOfDay Time= %g\n"
.align 8
.LC3:
.string " Clock Time = %g\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Number of primes: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2276:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -819200(%rsp), %r11
.cfi_def_cfa 11, 819232
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $80, %rsp
.cfi_def_cfa_offset 819312
movq %fs:40, %rax
movq %rax, 819272(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $819200, %esi
call cudaMalloc@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
call clock@PLT
movq %rax, %rbx
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
imulq $1000, 48(%rsp), %rbp
movq 56(%rsp), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
addq %rdx, %rbp
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L43:
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L44:
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L45:
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
imulq $1000, 48(%rsp), %r12
movq 56(%rsp), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
addq %rdx, %r12
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
subq %rbp, %r12
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $819200, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 819264(%rsp), %rcx
movl $0, %edx
.L47:
cmpq $1, (%rax)
sbbl $-1, %edx
addq $8, %rax
cmpq %rcx, %rax
jne .L47
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 819272(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $819280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $6, %esi
movl $3200, %edi
call _Z37__device_stub__Z15primeCandidatesiyPyiyPy
jmp .L43
.L52:
movq 8(%rsp), %rsi
movl $3200, %edi
call _Z37__device_stub__Z16filterCandidatesiPyiPy
jmp .L44
.L53:
movq 8(%rsp), %rsi
movl $3200, %edi
call _Z35__device_stub__Z14testCandidatesiPyiPy
jmp .L45
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2276:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z14testCandidatesiPy"
.LC6:
.string "_Z16filterCandidatesiPy"
.LC7:
.string "_Z15primeCandidatesiyPy"
.LC8:
.string "precalc_xorwow_matrix"
.LC9:
.string "precalc_xorwow_offset_matrix"
.LC10:
.string "mrg32k3aM1"
.LC11:
.string "mrg32k3aM2"
.LC12:
.string "mrg32k3aM1SubSeq"
.LC13:
.string "mrg32k3aM2SubSeq"
.LC14:
.string "mrg32k3aM1Seq"
.LC15:
.string "mrg32k3aM2Seq"
.LC16:
.string "__cr_lgamma_table"
.LC17:
.string "small_primes"
.LC18:
.string "small_primes_size"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2308:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14testCandidatesiPy(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16filterCandidatesiPy(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15primeCandidatesiyPy(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $200, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12small_primes(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17small_primes_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2308:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 4
.type _ZL17small_primes_size, @object
.size _ZL17small_primes_size, 4
_ZL17small_primes_size:
.long 25
.align 32
.type _ZL12small_primes, @object
.size _ZL12small_primes, 200
_ZL12small_primes:
.quad 2
.quad 3
.quad 5
.quad 7
.quad 11
.quad 13
.quad 17
.quad 19
.quad 23
.quad 29
.quad 31
.quad 37
.quad 41
.quad 43
.quad 47
.quad 53
.quad 59
.quad 61
.quad 67
.quad 71
.quad 73
.quad 79
.quad 83
.quad 89
.quad 97
.globl prime_list
.bss
.align 8
.type prime_list, @object
.size prime_list, 8
prime_list:
.zero 8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC1:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <assert.h>
#include <curand.h>
#include <curand_kernel.h>
#include <time.h>
#include <sys/time.h>
// Placeholder for longer list of primes
struct list_node{
unsigned long long value;
list_node* next;
};
list_node* prime_list;
// List of primes less than 100 to be checked for divisibility
__device__ const unsigned long long small_primes[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97};
__device__ const int small_primes_size = 25;
// Function prototypes
__device__ bool basic_test(unsigned long long);
__device__ bool exact_test(unsigned long long);
__device__ bool fermat_test(unsigned long long, curandState state);
__device__ bool miller_rabin_test(unsigned long long);
///////////////////////////////////////////////////////////////////////////////
// Kernel functions
///////////////////////////////////////////////////////////////////////////////
// Generate an initial list of numbers to test for primality
// start must be a multiple of 6 for this to be correct
__global__ void primeCandidates(int count, unsigned long long start, unsigned long long* list)
{
for(int i = count/2*threadIdx.x; i < count/2*(threadIdx.x+1); i++){
list[2*i] = start + 6*i - 1;
list[(2*i)+1] = start + 6*i + 1;
}
}
// Perform basic filters to eliminate obvious composite numbers.
__global__ void filterCandidates(int count, unsigned long long* list){
for(int i = count*threadIdx.x; i < count*(threadIdx.x+1); i++){
if (!(basic_test(list[i]))){
list[i] = 0;
}
}
}
// Perform more rigorous tests to confirm a number is prime
__global__ void testCandidates(int count, unsigned long long* list){
int idx = threadIdx.x;
curandState state;
curand_init(idx, idx, 0, &state);
for(int i = threadIdx.x * count; i < (threadIdx.x + 1)*count; i++){
// int exact = 1;
if (list[i] == 0) continue;
// if (!exact_test(list[i])) exact = 0;
if (!fermat_test(list[i], state)){
// if(exact) printf(" %d\n",list[i]);
list[i] = 0;
}
else{
// if(!exact) printf(" %d\n",list[i]);
}
}
}
///////////////////////////////////////////////////////////////////////////////
// Device helper functions
///////////////////////////////////////////////////////////////////////////////
// Tests for divisibility against the list of small primes
__device__ bool basic_test(unsigned long long n){
for(int i = 0; i < small_primes_size; i++){
if (!(n % small_primes[i])) return false;
}
return true;
}
// Exhaustively search possible divisors to confirm a number is prime.
__device__ bool exact_test(unsigned long long n){
for(unsigned long long i = 101; i * i <= n; i += 2){
if (!(n % i)) return false;
}
return true;
}
// Perform Fermat's primality test for a given number
__device__ bool fermat_test(unsigned long long n, curandState state){
int k = 10;
for(int i = 0; i < k; i++){
double x = curand_uniform_double(&state);
unsigned long long a = x * (n-4) + 2;
unsigned long long b = 1;
unsigned long long e = n-1;
while(e > 0){
if (e & 1) b = (b * a) % n;
e >>= 1;
a = (a * a) % n;
}
if (b != 1) return false;
}
return true;
}
// Perform the Miller-Rabin primality test for a given number
__device__ bool miller_rabin_test(unsigned long long n){
return false;
}
///////////////////////////////////////////////////////////////////////////////
// Host helpers
///////////////////////////////////////////////////////////////////////////////
// Placeholder for building linked list of primes
void build_primes(unsigned long long start){
list_node* node;
cudaMalloc((void**)&node, sizeof(list_node));
node->value = 2;
node->next = NULL;
prime_list = node;
for(int i = 3; i * i < start; i+= 2){
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
// Initialization
const int count = 3200;
// Ints to process per thread. Must be even
const int num_threads = 32; // Threads to launch in a single 1-D block
const int list_size = count * num_threads;
const unsigned long long start = 6;
unsigned long long* list; // Device pointer to potential primes
cudaMalloc((void**)&list, list_size * sizeof(unsigned long long));
dim3 gridSize(1,1,1);
dim3 blockSize(num_threads, 1, 1);
struct timeval tv;
struct timezone tz;
clock_t startTime, endTime, elapsedTime;
double timeInSeconds;
long GTODStartTime, GTODEndTime;
startTime = clock();
gettimeofday(&tv, &tz);
GTODStartTime = tv.tv_sec * 1000 + tv.tv_usec / 1000;
// First, generate a list of prime candidates
primeCandidates<<<gridSize, blockSize>>>(count, start, list);
// Second, filter the candidates to quickly eliminate composites
filterCandidates<<<gridSize, blockSize>>>(count, list);
// Third, confirm if candidates are actually prime
testCandidates<<<gridSize, blockSize>>>(count, list);
gettimeofday(&tv, &tz);
GTODEndTime = tv.tv_sec * 1000 + tv.tv_usec / 1000;
endTime = clock();
elapsedTime = endTime - startTime;
timeInSeconds = (elapsedTime / (double)CLOCKS_PER_SEC);
printf(" GetTimeOfDay Time= %g\n", (double)(GTODEndTime - GTODStartTime) / 1000.0);
printf(" Clock Time = %g\n", timeInSeconds);
// Copy list back and display (for debugging)
unsigned long long h_list[list_size];
cudaMemcpy(h_list, list, list_size * sizeof(unsigned long long), cudaMemcpyDeviceToHost);
int nprimes = 0;
for(int i = 0; i < list_size; i++){
if (h_list[i] != 0) {
// printf("%llu\n",h_list[i]);
nprimes++;
}
}
printf("Number of primes: %d\n",nprimes);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <time.h>
#include <sys/time.h>
// Placeholder for longer list of primes
struct list_node{
unsigned long long value;
list_node* next;
};
list_node* prime_list;
// List of primes less than 100 to be checked for divisibility
__device__ const unsigned long long small_primes[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97};
__device__ const int small_primes_size = 25;
// Function prototypes
__device__ bool basic_test(unsigned long long);
__device__ bool exact_test(unsigned long long);
__device__ bool fermat_test(unsigned long long, hiprandState state);
__device__ bool miller_rabin_test(unsigned long long);
///////////////////////////////////////////////////////////////////////////////
// Kernel functions
///////////////////////////////////////////////////////////////////////////////
// Generate an initial list of numbers to test for primality
// start must be a multiple of 6 for this to be correct
__global__ void primeCandidates(int count, unsigned long long start, unsigned long long* list)
{
for(int i = count/2*threadIdx.x; i < count/2*(threadIdx.x+1); i++){
list[2*i] = start + 6*i - 1;
list[(2*i)+1] = start + 6*i + 1;
}
}
// Perform basic filters to eliminate obvious composite numbers.
__global__ void filterCandidates(int count, unsigned long long* list){
for(int i = count*threadIdx.x; i < count*(threadIdx.x+1); i++){
if (!(basic_test(list[i]))){
list[i] = 0;
}
}
}
// Perform more rigorous tests to confirm a number is prime
__global__ void testCandidates(int count, unsigned long long* list){
int idx = threadIdx.x;
hiprandState state;
hiprand_init(idx, idx, 0, &state);
for(int i = threadIdx.x * count; i < (threadIdx.x + 1)*count; i++){
// int exact = 1;
if (list[i] == 0) continue;
// if (!exact_test(list[i])) exact = 0;
if (!fermat_test(list[i], state)){
// if(exact) printf(" %d\n",list[i]);
list[i] = 0;
}
else{
// if(!exact) printf(" %d\n",list[i]);
}
}
}
///////////////////////////////////////////////////////////////////////////////
// Device helper functions
///////////////////////////////////////////////////////////////////////////////
// Tests for divisibility against the list of small primes
__device__ bool basic_test(unsigned long long n){
for(int i = 0; i < small_primes_size; i++){
if (!(n % small_primes[i])) return false;
}
return true;
}
// Exhaustively search possible divisors to confirm a number is prime.
__device__ bool exact_test(unsigned long long n){
for(unsigned long long i = 101; i * i <= n; i += 2){
if (!(n % i)) return false;
}
return true;
}
// Perform Fermat's primality test for a given number
__device__ bool fermat_test(unsigned long long n, hiprandState state){
int k = 10;
for(int i = 0; i < k; i++){
double x = hiprand_uniform_double(&state);
unsigned long long a = x * (n-4) + 2;
unsigned long long b = 1;
unsigned long long e = n-1;
while(e > 0){
if (e & 1) b = (b * a) % n;
e >>= 1;
a = (a * a) % n;
}
if (b != 1) return false;
}
return true;
}
// Perform the Miller-Rabin primality test for a given number
__device__ bool miller_rabin_test(unsigned long long n){
return false;
}
///////////////////////////////////////////////////////////////////////////////
// Host helpers
///////////////////////////////////////////////////////////////////////////////
// Placeholder for building linked list of primes
void build_primes(unsigned long long start){
list_node* node;
hipMalloc((void**)&node, sizeof(list_node));
node->value = 2;
node->next = NULL;
prime_list = node;
for(int i = 3; i * i < start; i+= 2){
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
// Initialization
const int count = 3200;
// Ints to process per thread. Must be even
const int num_threads = 32; // Threads to launch in a single 1-D block
const int list_size = count * num_threads;
const unsigned long long start = 6;
unsigned long long* list; // Device pointer to potential primes
hipMalloc((void**)&list, list_size * sizeof(unsigned long long));
dim3 gridSize(1,1,1);
dim3 blockSize(num_threads, 1, 1);
struct timeval tv;
struct timezone tz;
clock_t startTime, endTime, elapsedTime;
double timeInSeconds;
long GTODStartTime, GTODEndTime;
startTime = clock();
gettimeofday(&tv, &tz);
GTODStartTime = tv.tv_sec * 1000 + tv.tv_usec / 1000;
// First, generate a list of prime candidates
primeCandidates<<<gridSize, blockSize>>>(count, start, list);
// Second, filter the candidates to quickly eliminate composites
filterCandidates<<<gridSize, blockSize>>>(count, list);
// Third, confirm if candidates are actually prime
testCandidates<<<gridSize, blockSize>>>(count, list);
gettimeofday(&tv, &tz);
GTODEndTime = tv.tv_sec * 1000 + tv.tv_usec / 1000;
endTime = clock();
elapsedTime = endTime - startTime;
timeInSeconds = (elapsedTime / (double)CLOCKS_PER_SEC);
printf(" GetTimeOfDay Time= %g\n", (double)(GTODEndTime - GTODStartTime) / 1000.0);
printf(" Clock Time = %g\n", timeInSeconds);
// Copy list back and display (for debugging)
unsigned long long h_list[list_size];
hipMemcpy(h_list, list, list_size * sizeof(unsigned long long), hipMemcpyDeviceToHost);
int nprimes = 0;
for(int i = 0; i < list_size; i++){
if (h_list[i] != 0) {
// printf("%llu\n",h_list[i]);
nprimes++;
}
}
printf("Number of primes: %d\n",nprimes);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <time.h>
#include <sys/time.h>
// Placeholder for longer list of primes
struct list_node{
unsigned long long value;
list_node* next;
};
list_node* prime_list;
// List of primes less than 100 to be checked for divisibility
__device__ const unsigned long long small_primes[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97};
__device__ const int small_primes_size = 25;
// Function prototypes
__device__ bool basic_test(unsigned long long);
__device__ bool exact_test(unsigned long long);
__device__ bool fermat_test(unsigned long long, hiprandState state);
__device__ bool miller_rabin_test(unsigned long long);
///////////////////////////////////////////////////////////////////////////////
// Kernel functions
///////////////////////////////////////////////////////////////////////////////
// Generate an initial list of numbers to test for primality
// start must be a multiple of 6 for this to be correct
__global__ void primeCandidates(int count, unsigned long long start, unsigned long long* list)
{
for(int i = count/2*threadIdx.x; i < count/2*(threadIdx.x+1); i++){
list[2*i] = start + 6*i - 1;
list[(2*i)+1] = start + 6*i + 1;
}
}
// Perform basic filters to eliminate obvious composite numbers.
__global__ void filterCandidates(int count, unsigned long long* list){
for(int i = count*threadIdx.x; i < count*(threadIdx.x+1); i++){
if (!(basic_test(list[i]))){
list[i] = 0;
}
}
}
// Perform more rigorous tests to confirm a number is prime
__global__ void testCandidates(int count, unsigned long long* list){
int idx = threadIdx.x;
hiprandState state;
hiprand_init(idx, idx, 0, &state);
for(int i = threadIdx.x * count; i < (threadIdx.x + 1)*count; i++){
// int exact = 1;
if (list[i] == 0) continue;
// if (!exact_test(list[i])) exact = 0;
if (!fermat_test(list[i], state)){
// if(exact) printf(" %d\n",list[i]);
list[i] = 0;
}
else{
// if(!exact) printf(" %d\n",list[i]);
}
}
}
///////////////////////////////////////////////////////////////////////////////
// Device helper functions
///////////////////////////////////////////////////////////////////////////////
// Tests for divisibility against the list of small primes
__device__ bool basic_test(unsigned long long n){
for(int i = 0; i < small_primes_size; i++){
if (!(n % small_primes[i])) return false;
}
return true;
}
// Exhaustively search possible divisors to confirm a number is prime.
__device__ bool exact_test(unsigned long long n){
for(unsigned long long i = 101; i * i <= n; i += 2){
if (!(n % i)) return false;
}
return true;
}
// Perform Fermat's primality test for a given number
__device__ bool fermat_test(unsigned long long n, hiprandState state){
int k = 10;
for(int i = 0; i < k; i++){
double x = hiprand_uniform_double(&state);
unsigned long long a = x * (n-4) + 2;
unsigned long long b = 1;
unsigned long long e = n-1;
while(e > 0){
if (e & 1) b = (b * a) % n;
e >>= 1;
a = (a * a) % n;
}
if (b != 1) return false;
}
return true;
}
// Perform the Miller-Rabin primality test for a given number
__device__ bool miller_rabin_test(unsigned long long n){
return false;
}
///////////////////////////////////////////////////////////////////////////////
// Host helpers
///////////////////////////////////////////////////////////////////////////////
// Placeholder for building linked list of primes
void build_primes(unsigned long long start){
list_node* node;
hipMalloc((void**)&node, sizeof(list_node));
node->value = 2;
node->next = NULL;
prime_list = node;
for(int i = 3; i * i < start; i+= 2){
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
// Initialization
const int count = 3200;
// Ints to process per thread. Must be even
const int num_threads = 32; // Threads to launch in a single 1-D block
const int list_size = count * num_threads;
const unsigned long long start = 6;
unsigned long long* list; // Device pointer to potential primes
hipMalloc((void**)&list, list_size * sizeof(unsigned long long));
dim3 gridSize(1,1,1);
dim3 blockSize(num_threads, 1, 1);
struct timeval tv;
struct timezone tz;
clock_t startTime, endTime, elapsedTime;
double timeInSeconds;
long GTODStartTime, GTODEndTime;
startTime = clock();
gettimeofday(&tv, &tz);
GTODStartTime = tv.tv_sec * 1000 + tv.tv_usec / 1000;
// First, generate a list of prime candidates
primeCandidates<<<gridSize, blockSize>>>(count, start, list);
// Second, filter the candidates to quickly eliminate composites
filterCandidates<<<gridSize, blockSize>>>(count, list);
// Third, confirm if candidates are actually prime
testCandidates<<<gridSize, blockSize>>>(count, list);
gettimeofday(&tv, &tz);
GTODEndTime = tv.tv_sec * 1000 + tv.tv_usec / 1000;
endTime = clock();
elapsedTime = endTime - startTime;
timeInSeconds = (elapsedTime / (double)CLOCKS_PER_SEC);
printf(" GetTimeOfDay Time= %g\n", (double)(GTODEndTime - GTODStartTime) / 1000.0);
printf(" Clock Time = %g\n", timeInSeconds);
// Copy list back and display (for debugging)
unsigned long long h_list[list_size];
hipMemcpy(h_list, list, list_size * sizeof(unsigned long long), hipMemcpyDeviceToHost);
int nprimes = 0;
for(int i = 0; i < list_size; i++){
if (h_list[i] != 0) {
// printf("%llu\n",h_list[i]);
nprimes++;
}
}
printf("Number of primes: %d\n",nprimes);
return 0;
}
|
.text
.file "primes.hip"
.globl _Z30__device_stub__primeCandidatesiyPy # -- Begin function _Z30__device_stub__primeCandidatesiyPy
.p2align 4, 0x90
.type _Z30__device_stub__primeCandidatesiyPy,@function
_Z30__device_stub__primeCandidatesiyPy: # @_Z30__device_stub__primeCandidatesiyPy
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15primeCandidatesiyPy, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__primeCandidatesiyPy, .Lfunc_end0-_Z30__device_stub__primeCandidatesiyPy
.cfi_endproc
# -- End function
.globl _Z31__device_stub__filterCandidatesiPy # -- Begin function _Z31__device_stub__filterCandidatesiPy
.p2align 4, 0x90
.type _Z31__device_stub__filterCandidatesiPy,@function
_Z31__device_stub__filterCandidatesiPy: # @_Z31__device_stub__filterCandidatesiPy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16filterCandidatesiPy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__filterCandidatesiPy, .Lfunc_end1-_Z31__device_stub__filterCandidatesiPy
.cfi_endproc
# -- End function
.globl _Z29__device_stub__testCandidatesiPy # -- Begin function _Z29__device_stub__testCandidatesiPy
.p2align 4, 0x90
.type _Z29__device_stub__testCandidatesiPy,@function
_Z29__device_stub__testCandidatesiPy: # @_Z29__device_stub__testCandidatesiPy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14testCandidatesiPy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z29__device_stub__testCandidatesiPy, .Lfunc_end2-_Z29__device_stub__testCandidatesiPy
.cfi_endproc
# -- End function
.globl _Z12build_primesy # -- Begin function _Z12build_primesy
.p2align 4, 0x90
.type _Z12build_primesy,@function
_Z12build_primesy: # @_Z12build_primesy
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movq (%rsp), %rax
movq $2, (%rax)
movq $0, 8(%rax)
movq %rax, prime_list(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12build_primesy, .Lfunc_end3-_Z12build_primesy
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $819320, %rsp # imm = 0xC8078
.cfi_def_cfa_offset 819376
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r15 # imm = 0x100000001
leaq 64(%rsp), %rdi
movl $819200, %esi # imm = 0xC8000
callq hipMalloc
callq clock
movq %rax, %rbx
leaq 80(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movabsq $-2361183241434822607, %rax # imm = 0xDF3B645A1CAC0831
imulq 88(%rsp)
movq %rdx, %r14
movq 80(%rsp), %rbp
leaq 31(%r15), %r13
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 64(%rsp), %rax
movl $3200, 76(%rsp) # imm = 0xC80
movq $6, 56(%rsp)
movq %rax, 16(%rsp)
leaq 76(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15primeCandidatesiyPy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq %r14, %r12
shrq $63, %r12
sarq $7, %r14
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 64(%rsp), %rax
movl $3200, (%rsp) # imm = 0xC80
movq %rax, 56(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16filterCandidatesiPy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
addq %r12, %r14
xorl %r12d, %r12d
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 64(%rsp), %rax
movl $3200, (%rsp) # imm = 0xC80
movq %rax, 56(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14testCandidatesiPy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
leaq 80(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movabsq $2361183241434822607, %rax # imm = 0x20C49BA5E353F7CF
imulq 88(%rsp)
movq %rdx, %r15
movq 80(%rsp), %r13
subq %rbp, %r13
movq %rdx, %rax
shrq $63, %rax
sarq $7, %r15
addq %rax, %r15
addq %r14, %r15
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 96(%rsp) # 8-byte Spill
imulq $1000, %r13, %rax # imm = 0x3E8
addq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_1(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 64(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $819200, %edx # imm = 0xC8000
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_7: # =>This Inner Loop Header: Depth=1
cmpq $1, 112(%rsp,%rax,8)
sbbl $-1, %r12d
incq %rax
cmpq $102400, %rax # imm = 0x19000
jne .LBB4_7
# %bb.8:
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $819320, %rsp # imm = 0xC8078
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15primeCandidatesiyPy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16filterCandidatesiPy, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14testCandidatesiPy, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type prime_list,@object # @prime_list
.bss
.globl prime_list
.p2align 3, 0x0
prime_list:
.quad 0
.size prime_list, 8
.type _Z15primeCandidatesiyPy,@object # @_Z15primeCandidatesiyPy
.section .rodata,"a",@progbits
.globl _Z15primeCandidatesiyPy
.p2align 3, 0x0
_Z15primeCandidatesiyPy:
.quad _Z30__device_stub__primeCandidatesiyPy
.size _Z15primeCandidatesiyPy, 8
.type _Z16filterCandidatesiPy,@object # @_Z16filterCandidatesiPy
.globl _Z16filterCandidatesiPy
.p2align 3, 0x0
_Z16filterCandidatesiPy:
.quad _Z31__device_stub__filterCandidatesiPy
.size _Z16filterCandidatesiPy, 8
.type _Z14testCandidatesiPy,@object # @_Z14testCandidatesiPy
.globl _Z14testCandidatesiPy
.p2align 3, 0x0
_Z14testCandidatesiPy:
.quad _Z29__device_stub__testCandidatesiPy
.size _Z14testCandidatesiPy, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " GetTimeOfDay Time= %g\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Clock Time = %g\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of primes: %d\n"
.size .L.str.2, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15primeCandidatesiyPy"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16filterCandidatesiPy"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14testCandidatesiPy"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__primeCandidatesiyPy
.addrsig_sym _Z31__device_stub__filterCandidatesiPy
.addrsig_sym _Z29__device_stub__testCandidatesiPy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15primeCandidatesiyPy
.addrsig_sym _Z16filterCandidatesiPy
.addrsig_sym _Z14testCandidatesiPy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00194c83_00000000-6_primes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2279:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2279:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10basic_testy
.type _Z10basic_testy, @function
_Z10basic_testy:
.LFB2271:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2271:
.size _Z10basic_testy, .-_Z10basic_testy
.globl _Z10exact_testy
.type _Z10exact_testy, @function
_Z10exact_testy:
.LFB2272:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2272:
.size _Z10exact_testy, .-_Z10exact_testy
.globl _Z11fermat_testy17curandStateXORWOW
.type _Z11fermat_testy17curandStateXORWOW, @function
_Z11fermat_testy17curandStateXORWOW:
.LFB2273:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2273:
.size _Z11fermat_testy17curandStateXORWOW, .-_Z11fermat_testy17curandStateXORWOW
.globl _Z17miller_rabin_testy
.type _Z17miller_rabin_testy, @function
_Z17miller_rabin_testy:
.LFB2274:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2274:
.size _Z17miller_rabin_testy, .-_Z17miller_rabin_testy
.globl _Z12build_primesy
.type _Z12build_primesy, @function
_Z12build_primesy:
.LFB2275:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
movq (%rsp), %rax
movq $2, (%rax)
movq (%rsp), %rax
movq $0, 8(%rax)
movq %rax, prime_list(%rip)
cmpq $9, %rbx
jbe .L11
movl $3, %eax
.L13:
addl $2, %eax
movl %eax, %edx
imull %eax, %edx
movslq %edx, %rdx
cmpq %rbx, %rdx
jb .L13
.L11:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2275:
.size _Z12build_primesy, .-_Z12build_primesy
.globl _Z37__device_stub__Z15primeCandidatesiyPyiyPy
.type _Z37__device_stub__Z15primeCandidatesiyPyiyPy, @function
_Z37__device_stub__Z15primeCandidatesiyPyiyPy:
.LFB2301:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15primeCandidatesiyPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2301:
.size _Z37__device_stub__Z15primeCandidatesiyPyiyPy, .-_Z37__device_stub__Z15primeCandidatesiyPyiyPy
.globl _Z15primeCandidatesiyPy
.type _Z15primeCandidatesiyPy, @function
_Z15primeCandidatesiyPy:
.LFB2302:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15primeCandidatesiyPyiyPy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _Z15primeCandidatesiyPy, .-_Z15primeCandidatesiyPy
.globl _Z37__device_stub__Z16filterCandidatesiPyiPy
.type _Z37__device_stub__Z16filterCandidatesiPyiPy, @function
_Z37__device_stub__Z16filterCandidatesiPyiPy:
.LFB2303:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16filterCandidatesiPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2303:
.size _Z37__device_stub__Z16filterCandidatesiPyiPy, .-_Z37__device_stub__Z16filterCandidatesiPyiPy
.globl _Z16filterCandidatesiPy
.type _Z16filterCandidatesiPy, @function
_Z16filterCandidatesiPy:
.LFB2304:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16filterCandidatesiPyiPy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2304:
.size _Z16filterCandidatesiPy, .-_Z16filterCandidatesiPy
.globl _Z35__device_stub__Z14testCandidatesiPyiPy
.type _Z35__device_stub__Z14testCandidatesiPyiPy, @function
_Z35__device_stub__Z14testCandidatesiPyiPy:
.LFB2305:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14testCandidatesiPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2305:
.size _Z35__device_stub__Z14testCandidatesiPyiPy, .-_Z35__device_stub__Z14testCandidatesiPyiPy
.globl _Z14testCandidatesiPy
.type _Z14testCandidatesiPy, @function
_Z14testCandidatesiPy:
.LFB2306:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14testCandidatesiPyiPy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2306:
.size _Z14testCandidatesiPy, .-_Z14testCandidatesiPy
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string " GetTimeOfDay Time= %g\n"
.align 8
.LC3:
.string " Clock Time = %g\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Number of primes: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2276:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -819200(%rsp), %r11
.cfi_def_cfa 11, 819232
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $80, %rsp
.cfi_def_cfa_offset 819312
movq %fs:40, %rax
movq %rax, 819272(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $819200, %esi
call cudaMalloc@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
call clock@PLT
movq %rax, %rbx
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
imulq $1000, 48(%rsp), %rbp
movq 56(%rsp), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
addq %rdx, %rbp
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L43:
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L44:
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L45:
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
imulq $1000, 48(%rsp), %r12
movq 56(%rsp), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
addq %rdx, %r12
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
subq %rbp, %r12
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $819200, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 819264(%rsp), %rcx
movl $0, %edx
.L47:
cmpq $1, (%rax)
sbbl $-1, %edx
addq $8, %rax
cmpq %rcx, %rax
jne .L47
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 819272(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $819280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $6, %esi
movl $3200, %edi
call _Z37__device_stub__Z15primeCandidatesiyPyiyPy
jmp .L43
.L52:
movq 8(%rsp), %rsi
movl $3200, %edi
call _Z37__device_stub__Z16filterCandidatesiPyiPy
jmp .L44
.L53:
movq 8(%rsp), %rsi
movl $3200, %edi
call _Z35__device_stub__Z14testCandidatesiPyiPy
jmp .L45
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2276:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z14testCandidatesiPy"
.LC6:
.string "_Z16filterCandidatesiPy"
.LC7:
.string "_Z15primeCandidatesiyPy"
.LC8:
.string "precalc_xorwow_matrix"
.LC9:
.string "precalc_xorwow_offset_matrix"
.LC10:
.string "mrg32k3aM1"
.LC11:
.string "mrg32k3aM2"
.LC12:
.string "mrg32k3aM1SubSeq"
.LC13:
.string "mrg32k3aM2SubSeq"
.LC14:
.string "mrg32k3aM1Seq"
.LC15:
.string "mrg32k3aM2Seq"
.LC16:
.string "__cr_lgamma_table"
.LC17:
.string "small_primes"
.LC18:
.string "small_primes_size"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2308:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14testCandidatesiPy(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16filterCandidatesiPy(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15primeCandidatesiyPy(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $200, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12small_primes(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17small_primes_size(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2308:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 4
.type _ZL17small_primes_size, @object
.size _ZL17small_primes_size, 4
_ZL17small_primes_size:
.long 25
.align 32
.type _ZL12small_primes, @object
.size _ZL12small_primes, 200
_ZL12small_primes:
.quad 2
.quad 3
.quad 5
.quad 7
.quad 11
.quad 13
.quad 17
.quad 19
.quad 23
.quad 29
.quad 31
.quad 37
.quad 41
.quad 43
.quad 47
.quad 53
.quad 59
.quad 61
.quad 67
.quad 71
.quad 73
.quad 79
.quad 83
.quad 89
.quad 97
.globl prime_list
.bss
.align 8
.type prime_list, @object
.size prime_list, 8
prime_list:
.zero 8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC1:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "primes.hip"
.globl _Z30__device_stub__primeCandidatesiyPy # -- Begin function _Z30__device_stub__primeCandidatesiyPy
.p2align 4, 0x90
.type _Z30__device_stub__primeCandidatesiyPy,@function
_Z30__device_stub__primeCandidatesiyPy: # @_Z30__device_stub__primeCandidatesiyPy
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15primeCandidatesiyPy, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__primeCandidatesiyPy, .Lfunc_end0-_Z30__device_stub__primeCandidatesiyPy
.cfi_endproc
# -- End function
.globl _Z31__device_stub__filterCandidatesiPy # -- Begin function _Z31__device_stub__filterCandidatesiPy
.p2align 4, 0x90
.type _Z31__device_stub__filterCandidatesiPy,@function
_Z31__device_stub__filterCandidatesiPy: # @_Z31__device_stub__filterCandidatesiPy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16filterCandidatesiPy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__filterCandidatesiPy, .Lfunc_end1-_Z31__device_stub__filterCandidatesiPy
.cfi_endproc
# -- End function
.globl _Z29__device_stub__testCandidatesiPy # -- Begin function _Z29__device_stub__testCandidatesiPy
.p2align 4, 0x90
.type _Z29__device_stub__testCandidatesiPy,@function
_Z29__device_stub__testCandidatesiPy: # @_Z29__device_stub__testCandidatesiPy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14testCandidatesiPy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z29__device_stub__testCandidatesiPy, .Lfunc_end2-_Z29__device_stub__testCandidatesiPy
.cfi_endproc
# -- End function
.globl _Z12build_primesy # -- Begin function _Z12build_primesy
.p2align 4, 0x90
.type _Z12build_primesy,@function
_Z12build_primesy: # @_Z12build_primesy
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movq (%rsp), %rax
movq $2, (%rax)
movq $0, 8(%rax)
movq %rax, prime_list(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12build_primesy, .Lfunc_end3-_Z12build_primesy
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI4_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $819320, %rsp # imm = 0xC8078
.cfi_def_cfa_offset 819376
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r15 # imm = 0x100000001
leaq 64(%rsp), %rdi
movl $819200, %esi # imm = 0xC8000
callq hipMalloc
callq clock
movq %rax, %rbx
leaq 80(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movabsq $-2361183241434822607, %rax # imm = 0xDF3B645A1CAC0831
imulq 88(%rsp)
movq %rdx, %r14
movq 80(%rsp), %rbp
leaq 31(%r15), %r13
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 64(%rsp), %rax
movl $3200, 76(%rsp) # imm = 0xC80
movq $6, 56(%rsp)
movq %rax, 16(%rsp)
leaq 76(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15primeCandidatesiyPy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq %r14, %r12
shrq $63, %r12
sarq $7, %r14
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 64(%rsp), %rax
movl $3200, (%rsp) # imm = 0xC80
movq %rax, 56(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16filterCandidatesiPy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
addq %r12, %r14
xorl %r12d, %r12d
movq %r15, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 64(%rsp), %rax
movl $3200, (%rsp) # imm = 0xC80
movq %rax, 56(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14testCandidatesiPy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
leaq 80(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movabsq $2361183241434822607, %rax # imm = 0x20C49BA5E353F7CF
imulq 88(%rsp)
movq %rdx, %r15
movq 80(%rsp), %r13
subq %rbp, %r13
movq %rdx, %rax
shrq $63, %rax
sarq $7, %r15
addq %rax, %r15
addq %r14, %r15
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 96(%rsp) # 8-byte Spill
imulq $1000, %r13, %rax # imm = 0x3E8
addq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_1(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 64(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $819200, %edx # imm = 0xC8000
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_7: # =>This Inner Loop Header: Depth=1
cmpq $1, 112(%rsp,%rax,8)
sbbl $-1, %r12d
incq %rax
cmpq $102400, %rax # imm = 0x19000
jne .LBB4_7
# %bb.8:
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $819320, %rsp # imm = 0xC8078
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15primeCandidatesiyPy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16filterCandidatesiPy, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14testCandidatesiPy, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type prime_list,@object # @prime_list
.bss
.globl prime_list
.p2align 3, 0x0
prime_list:
.quad 0
.size prime_list, 8
.type _Z15primeCandidatesiyPy,@object # @_Z15primeCandidatesiyPy
.section .rodata,"a",@progbits
.globl _Z15primeCandidatesiyPy
.p2align 3, 0x0
_Z15primeCandidatesiyPy:
.quad _Z30__device_stub__primeCandidatesiyPy
.size _Z15primeCandidatesiyPy, 8
.type _Z16filterCandidatesiPy,@object # @_Z16filterCandidatesiPy
.globl _Z16filterCandidatesiPy
.p2align 3, 0x0
_Z16filterCandidatesiPy:
.quad _Z31__device_stub__filterCandidatesiPy
.size _Z16filterCandidatesiPy, 8
.type _Z14testCandidatesiPy,@object # @_Z14testCandidatesiPy
.globl _Z14testCandidatesiPy
.p2align 3, 0x0
_Z14testCandidatesiPy:
.quad _Z29__device_stub__testCandidatesiPy
.size _Z14testCandidatesiPy, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " GetTimeOfDay Time= %g\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Clock Time = %g\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of primes: %d\n"
.size .L.str.2, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15primeCandidatesiyPy"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16filterCandidatesiPy"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14testCandidatesiPy"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__primeCandidatesiyPy
.addrsig_sym _Z31__device_stub__filterCandidatesiPy
.addrsig_sym _Z29__device_stub__testCandidatesiPy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15primeCandidatesiyPy
.addrsig_sym _Z16filterCandidatesiPy
.addrsig_sym _Z14testCandidatesiPy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void STREAM_Add(float *a, float *b, float *c, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
c[idx] = a[idx]+b[idx];
idx += blockDim.x * gridDim.x;
}
}
|
code for sm_80
Function : _Z10STREAM_AddPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x041fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R7, R0, 0x2, R11 ; /* 0x0000000200077819 */
/* 0x000fc8000001020b */
/*00c0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f3e0ff */
/*00d0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f1e0ff */
/*00e0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */
/* 0x040fe40000ffe4ff */
/*00f0*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */
/* 0x000fc800007fe4ff */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe20007f1e0ff */
/*0130*/ IMAD R13, R8, c[0x0][0xc], RZ ; /* 0x00000300080d7a24 */
/* 0x000fc600078e02ff */
/*0140*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe400007fe4ff */
/*0150*/ IADD3 R0, P0, R13, R0, RZ ; /* 0x000000000d007210 */
/* 0x000fca0007f1e0ff */
/*0160*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e060b */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0180*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */
/* 0x000fe20003f06100 */
/*0190*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*01b0*/ @!P0 BRA 0xa0 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void STREAM_Add(float *a, float *b, float *c, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
c[idx] = a[idx]+b[idx];
idx += blockDim.x * gridDim.x;
}
}
|
.file "tmpxft_00096e9e_00000000-6_STREAM_Add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m
.type _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m, @function
_Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10STREAM_AddPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m, .-_Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m
.globl _Z10STREAM_AddPfS_S_m
.type _Z10STREAM_AddPfS_S_m, @function
_Z10STREAM_AddPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10STREAM_AddPfS_S_m, .-_Z10STREAM_AddPfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10STREAM_AddPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10STREAM_AddPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void STREAM_Add(float *a, float *b, float *c, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
c[idx] = a[idx]+b[idx];
idx += blockDim.x * gridDim.x;
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void STREAM_Add(float *a, float *b, float *c, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
c[idx] = a[idx]+b[idx];
idx += blockDim.x * gridDim.x;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void STREAM_Add(float *a, float *b, float *c, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
c[idx] = a[idx]+b[idx];
idx += blockDim.x * gridDim.x;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10STREAM_AddPfS_S_m
.globl _Z10STREAM_AddPfS_S_m
.p2align 8
.type _Z10STREAM_AddPfS_S_m,@function
_Z10STREAM_AddPfS_S_m:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s11
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s12, s10
s_lshl_b64 s[12:13], s[10:11], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
global_load_b32 v0, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10STREAM_AddPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10STREAM_AddPfS_S_m, .Lfunc_end0-_Z10STREAM_AddPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10STREAM_AddPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10STREAM_AddPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void STREAM_Add(float *a, float *b, float *c, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
c[idx] = a[idx]+b[idx];
idx += blockDim.x * gridDim.x;
}
}
|
.text
.file "STREAM_Add.hip"
.globl _Z25__device_stub__STREAM_AddPfS_S_m # -- Begin function _Z25__device_stub__STREAM_AddPfS_S_m
.p2align 4, 0x90
.type _Z25__device_stub__STREAM_AddPfS_S_m,@function
_Z25__device_stub__STREAM_AddPfS_S_m: # @_Z25__device_stub__STREAM_AddPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10STREAM_AddPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__STREAM_AddPfS_S_m, .Lfunc_end0-_Z25__device_stub__STREAM_AddPfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10STREAM_AddPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10STREAM_AddPfS_S_m,@object # @_Z10STREAM_AddPfS_S_m
.section .rodata,"a",@progbits
.globl _Z10STREAM_AddPfS_S_m
.p2align 3, 0x0
_Z10STREAM_AddPfS_S_m:
.quad _Z25__device_stub__STREAM_AddPfS_S_m
.size _Z10STREAM_AddPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10STREAM_AddPfS_S_m"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__STREAM_AddPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10STREAM_AddPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z10STREAM_AddPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x041fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R7, R0, 0x2, R11 ; /* 0x0000000200077819 */
/* 0x000fc8000001020b */
/*00c0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f3e0ff */
/*00d0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f1e0ff */
/*00e0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */
/* 0x040fe40000ffe4ff */
/*00f0*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */
/* 0x000fc800007fe4ff */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe20007f1e0ff */
/*0130*/ IMAD R13, R8, c[0x0][0xc], RZ ; /* 0x00000300080d7a24 */
/* 0x000fc600078e02ff */
/*0140*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe400007fe4ff */
/*0150*/ IADD3 R0, P0, R13, R0, RZ ; /* 0x000000000d007210 */
/* 0x000fca0007f1e0ff */
/*0160*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e060b */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0180*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */
/* 0x000fe20003f06100 */
/*0190*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*01b0*/ @!P0 BRA 0xa0 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10STREAM_AddPfS_S_m
.globl _Z10STREAM_AddPfS_S_m
.p2align 8
.type _Z10STREAM_AddPfS_S_m,@function
_Z10STREAM_AddPfS_S_m:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s11
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s12, s10
s_lshl_b64 s[12:13], s[10:11], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
global_load_b32 v0, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10STREAM_AddPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10STREAM_AddPfS_S_m, .Lfunc_end0-_Z10STREAM_AddPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10STREAM_AddPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10STREAM_AddPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00096e9e_00000000-6_STREAM_Add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m
.type _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m, @function
_Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10STREAM_AddPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m, .-_Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m
.globl _Z10STREAM_AddPfS_S_m
.type _Z10STREAM_AddPfS_S_m, @function
_Z10STREAM_AddPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10STREAM_AddPfS_S_m, .-_Z10STREAM_AddPfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10STREAM_AddPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10STREAM_AddPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "STREAM_Add.hip"
.globl _Z25__device_stub__STREAM_AddPfS_S_m # -- Begin function _Z25__device_stub__STREAM_AddPfS_S_m
.p2align 4, 0x90
.type _Z25__device_stub__STREAM_AddPfS_S_m,@function
_Z25__device_stub__STREAM_AddPfS_S_m: # @_Z25__device_stub__STREAM_AddPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10STREAM_AddPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__STREAM_AddPfS_S_m, .Lfunc_end0-_Z25__device_stub__STREAM_AddPfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10STREAM_AddPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10STREAM_AddPfS_S_m,@object # @_Z10STREAM_AddPfS_S_m
.section .rodata,"a",@progbits
.globl _Z10STREAM_AddPfS_S_m
.p2align 3, 0x0
_Z10STREAM_AddPfS_S_m:
.quad _Z25__device_stub__STREAM_AddPfS_S_m
.size _Z10STREAM_AddPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10STREAM_AddPfS_S_m"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__STREAM_AddPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10STREAM_AddPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <cstdlib>
#include <cstdio>
#include <curand_kernel.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/execution_policy.h>
#include <thrust/extrema.h>
#include <thrust/device_ptr.h>
#define N 10
using namespace std;
struct node{
int base;
int data;
node *next;
};
__device__ node *head[N];
__global__ void print_kernel()
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i >= N){
return;
}
node *temp = head[i];
while (temp){
printf("%d and %d from %d\n", temp->base, temp->data, i);
temp = temp->next;
}
}
__global__ void setup_kernel()
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i >= N){
return;
}
head[i]=NULL;
node *end = head[i];
for (int j=i; j<i+5; j++){
node *temp = new node();
temp->base = j;
temp->data = j;
temp->next = NULL;
if (end){
end->next = temp;
end = end->next;
}
else{
head[i]=temp;
end = head[i];
}
}
}
int main(int argc, char const *argv[])
{
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock -1)/threadsPerBlock;
setup_kernel<<<blocksPerGrid, threadsPerBlock>>>();
print_kernel<<<blocksPerGrid, threadsPerBlock>>>();
cudaDeviceReset();
return 0;
}
|
code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12setup_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x9, PT ; /* 0x000000090200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; /* 0x00000008ff177424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R16, 0x1b0 ; /* 0x000001b000107802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; /* 0x00000010ff047424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.WIDE R22, R2, R23, c[0x4][0x40] ; /* 0x0100100002167625 */
/* 0x000fe200078e0217 */
/*00b0*/ LDC.64 R6, c[0x4][R16] ; /* 0x0100000010067b82 */
/* 0x0000660000000a00 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00d0*/ STG.E.64 [R22.64], RZ ; /* 0x000000ff16007986 */
/* 0x0001e8000c101b24 */
/*00e0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*00f0*/ MOV R3, 0x160 ; /* 0x0000016000037802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R20, 0xe0 ; /* 0x000000e000147802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0130*/ IADD3 R20, P0, P1, -R20, R3, R8 ; /* 0x0000000314147210 */
/* 0x000fc8000791e108 */
/*0140*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0150*/ CALL.ABS.NOINC R6 ; /* 0x0000000006007343 */
/* 0x003fea0003c00000 */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0002 */
/*0170*/ LDC.64 R16, c[0x4][R16] ; /* 0x0100000010107b82 */
/* 0x000e220000000a00 */
/*0180*/ IMAD.MOV.U32 R18, RZ, RZ, R4 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0004 */
/*0190*/ IMAD.MOV.U32 R19, RZ, RZ, R5 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0005 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; /* 0x00000010ff047424 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*01c0*/ ST.E.64 [R18.64], R2 ; /* 0x0000000212007985 */
/* 0x0003e8000c101b24 */
/*01d0*/ ST.E.64 [R18.64+0x8], RZ ; /* 0x000008ff12007985 */
/* 0x0003e8000c101b24 */
/*01e0*/ STG.E.64 [R22.64], R18 ; /* 0x0000001216007986 */
/* 0x0003e4000c101b24 */
/*01f0*/ LEPC R6 ; /* 0x000000000006734e */
/* 0x000fe20000000000 */
/*0200*/ MOV R3, 0x270 ; /* 0x0000027000037802 */
/* 0x002fc40000000f00 */
/*0210*/ MOV R20, 0x1f0 ; /* 0x000001f000147802 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0230*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0240*/ IADD3 R20, P0, P1, -R20, R3, R6 ; /* 0x0000000314147210 */
/* 0x000fc8000791e106 */
/*0250*/ IADD3.X R21, ~R0, R21, R7, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2507 */
/*0260*/ CALL.ABS.NOINC R16 ; /* 0x0000000010007343 */
/* 0x001fea0003c00000 */
/*0270*/ ISETP.NE.U32.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f05070 */
/*0280*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0004 */
/*0290*/ IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0005 */
/*02b0*/ ISETP.NE.AND.EX P0, PT, R19, RZ, PT, P0 ; /* 0x000000ff1300720c */
/* 0x000fe20003f05300 */
/*02c0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; /* 0x00000010ff047424 */
/* 0x000fe200078e00ff */
/*02d0*/ MOV R0, 0x1b0 ; /* 0x000001b000007802 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0006 */
/*02f0*/ ST.E.64 [R16.64+0x8], RZ ; /* 0x000008ff10007985 */
/* 0x0001e2000c101b24 */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0310*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000640000000a00 */
/*0320*/ ST.E.64 [R16.64], R6 ; /* 0x0000000610007985 */
/* 0x0001ea000c101b24 */
/*0330*/ @P0 ST.E.64 [R18.64+0x8], R16 ; /* 0x0000081012000985 */
/* 0x0001e8000c101b24 */
/*0340*/ @!P0 STG.E.64 [R22.64], R16 ; /* 0x0000001016008986 */
/* 0x0001e4000c101b24 */
/*0350*/ LEPC R6 ; /* 0x000000000006734e */
/* 0x001fe20000000000 */
/*0360*/ MOV R3, 0x3d0 ; /* 0x000003d000037802 */
/* 0x000fc40000000f00 */
/*0370*/ MOV R20, 0x350 ; /* 0x0000035000147802 */
/* 0x000fe40000000f00 */
/*0380*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0390*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*03a0*/ IADD3 R20, P0, P1, -R20, R3, R6 ; /* 0x0000000314147210 */
/* 0x000fc8000791e106 */
/*03b0*/ IADD3.X R21, ~R0, R21, R7, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2507 */
/*03c0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*03d0*/ ISETP.NE.U32.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05070 */
/*03e0*/ IMAD.MOV.U32 R18, RZ, RZ, R4 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0004 */
/*03f0*/ IADD3 R6, R2, 0x2, RZ ; /* 0x0000000202067810 */
/* 0x000fe20007ffe0ff */
/*0400*/ IMAD.MOV.U32 R19, RZ, RZ, R5 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0005 */
/*0410*/ ISETP.NE.AND.EX P0, PT, R17, RZ, PT, P0 ; /* 0x000000ff1100720c */
/* 0x000fe20003f05300 */
/*0420*/ IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; /* 0x00000010ff047424 */
/* 0x000fe200078e00ff */
/*0430*/ MOV R0, 0x1b0 ; /* 0x000001b000007802 */
/* 0x000fe20000000f00 */
/*0440*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0006 */
/*0450*/ ST.E.64 [R18.64+0x8], RZ ; /* 0x000008ff12007985 */
/* 0x0001e2000c101b24 */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0470*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000640000000a00 */
/*0480*/ ST.E.64 [R18.64], R6 ; /* 0x0000000612007985 */
/* 0x0001ea000c101b24 */
/*0490*/ @P0 ST.E.64 [R16.64+0x8], R18 ; /* 0x0000081210000985 */
/* 0x0001e8000c101b24 */
/*04a0*/ @!P0 STG.E.64 [R22.64], R18 ; /* 0x0000001216008986 */
/* 0x0001e4000c101b24 */
/*04b0*/ LEPC R6 ; /* 0x000000000006734e */
/* 0x001fe20000000000 */
/*04c0*/ MOV R3, 0x530 ; /* 0x0000053000037802 */
/* 0x000fc40000000f00 */
/*04d0*/ MOV R20, 0x4b0 ; /* 0x000004b000147802 */
/* 0x000fe40000000f00 */
/*04e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*04f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0500*/ IADD3 R20, P0, P1, -R20, R3, R6 ; /* 0x0000000314147210 */
/* 0x000fc8000791e106 */
/*0510*/ IADD3.X R21, ~R0, R21, R7, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2507 */
/*0520*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0530*/ ISETP.NE.U32.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f05070 */
/*0540*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0004 */
/*0550*/ IADD3 R6, R2, 0x3, RZ ; /* 0x0000000302067810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0005 */
/*0570*/ ISETP.NE.AND.EX P0, PT, R19, RZ, PT, P0 ; /* 0x000000ff1300720c */
/* 0x000fe20003f05300 */
/*0580*/ IMAD.MOV.U32 R4, RZ, RZ, 0x10 ; /* 0x00000010ff047424 */
/* 0x000fe200078e00ff */
/*0590*/ MOV R0, 0x1b0 ; /* 0x000001b000007802 */
/* 0x000fe20000000f00 */
/*05a0*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0006 */
/*05b0*/ ST.E.64 [R16.64+0x8], RZ ; /* 0x000008ff10007985 */
/* 0x0001e2000c101b24 */
/*05c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*05d0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000640000000a00 */
/*05e0*/ ST.E.64 [R16.64], R6 ; /* 0x0000000610007985 */
/* 0x0001ea000c101b24 */
/*05f0*/ @P0 ST.E.64 [R18.64+0x8], R16 ; /* 0x0000081012000985 */
/* 0x0001e8000c101b24 */
/*0600*/ @!P0 STG.E.64 [R22.64], R16 ; /* 0x0000001016008986 */
/* 0x0001e4000c101b24 */
/*0610*/ LEPC R6 ; /* 0x000000000006734e */
/* 0x001fe20000000000 */
/*0620*/ MOV R3, 0x690 ; /* 0x0000069000037802 */
/* 0x000fc40000000f00 */
/*0630*/ MOV R20, 0x610 ; /* 0x0000061000147802 */
/* 0x000fe40000000f00 */
/*0640*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0650*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0660*/ IADD3 R20, P0, P1, -R20, R3, R6 ; /* 0x0000000314147210 */
/* 0x000fc8000791e106 */
/*0670*/ IADD3.X R21, ~R0, R21, R7, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2507 */
/*0680*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0690*/ ISETP.NE.U32.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05070 */
/*06a0*/ ST.E.64 [R4.64+0x8], RZ ; /* 0x000008ff04007985 */
/* 0x0001e2000c101b24 */
/*06b0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ ISETP.NE.AND.EX P0, PT, R17, RZ, PT, P0 ; /* 0x000000ff1100720c */
/* 0x000fc60003f05300 */
/*06d0*/ IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0002 */
/*06e0*/ ST.E.64 [R4.64], R2 ; /* 0x0000000204007985 */
/* 0x0001ea000c101b24 */
/*06f0*/ @P0 ST.E.64 [R16.64+0x8], R4 ; /* 0x0000080410000985 */
/* 0x0001e2000c101b24 */
/*0700*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0710*/ STG.E.64 [R22.64], R4 ; /* 0x0000000416007986 */
/* 0x000fe2000c101b24 */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ BRA 0x730; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12print_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GT.AND P0, PT, R2, 0x9, PT ; /* 0x000000090200780c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R4, R2, R5, c[0x4][0x40] ; /* 0x0100100002047625 */
/* 0x000fca00078e0205 */
/*00a0*/ LDG.E.64 R16, [R4.64] ; /* 0x0000002404107981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IADD3 R18, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001127a10 */
/* 0x000fca0007f3e0ff */
/*00c0*/ IMAD.X R19, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff137624 */
/* 0x000fe200008e06ff */
/*00d0*/ ISETP.NE.U32.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x004fc80003f05070 */
/*00e0*/ ISETP.NE.AND.EX P0, PT, R17, RZ, PT, P0 ; /* 0x000000ff1100720c */
/* 0x000fda0003f05300 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ LD.E.64 R10, [R16.64] ; /* 0x00000024100a7980 */
/* 0x000ea2000c101b00 */
/*0110*/ MOV R8, 0x1b8 ; /* 0x000001b800087802 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x1a8] ; /* 0x01006a00ff047624 */
/* 0x000fe400078e00ff */
/*0130*/ STL [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001e20000100800 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1ac] ; /* 0x01006b00ff057624 */
/* 0x000fe400078e00ff */
/*0150*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*0180*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*0190*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe20000000000 */
/*01a0*/ MOV R3, 0x210 ; /* 0x0000021000037802 */
/* 0x000fc40000000f00 */
/*01b0*/ MOV R20, 0x190 ; /* 0x0000019000147802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01e0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*01f0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0200*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0210*/ LD.E.64 R16, [R16.64+0x8] ; /* 0x0000082410107980 */
/* 0x000ea4000c101b00 */
/*0220*/ ISETP.NE.U32.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x004fc80003f05070 */
/*0230*/ ISETP.NE.AND.EX P0, PT, R17, RZ, PT, P0 ; /* 0x000000ff1100720c */
/* 0x000fda0003f05300 */
/*0240*/ @P0 BRA 0x100 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <cstdlib>
#include <cstdio>
#include <curand_kernel.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/execution_policy.h>
#include <thrust/extrema.h>
#include <thrust/device_ptr.h>
#define N 10
using namespace std;
struct node{
int base;
int data;
node *next;
};
__device__ node *head[N];
__global__ void print_kernel()
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i >= N){
return;
}
node *temp = head[i];
while (temp){
printf("%d and %d from %d\n", temp->base, temp->data, i);
temp = temp->next;
}
}
__global__ void setup_kernel()
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i >= N){
return;
}
head[i]=NULL;
node *end = head[i];
for (int j=i; j<i+5; j++){
node *temp = new node();
temp->base = j;
temp->data = j;
temp->next = NULL;
if (end){
end->next = temp;
end = end->next;
}
else{
head[i]=temp;
end = head[i];
}
}
}
int main(int argc, char const *argv[])
{
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock -1)/threadsPerBlock;
setup_kernel<<<blocksPerGrid, threadsPerBlock>>>();
print_kernel<<<blocksPerGrid, threadsPerBlock>>>();
cudaDeviceReset();
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cstdio>
#include <hiprand/hiprand_kernel.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/execution_policy.h>
#include <thrust/extrema.h>
#include <thrust/device_ptr.h>
#define N 10
using namespace std;
struct node{
int base;
int data;
node *next;
};
__device__ node *head[N];
__global__ void print_kernel()
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i >= N){
return;
}
node *temp = head[i];
while (temp){
printf("%d and %d from %d\n", temp->base, temp->data, i);
temp = temp->next;
}
}
__global__ void setup_kernel()
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i >= N){
return;
}
head[i]=NULL;
node *end = head[i];
for (int j=i; j<i+5; j++){
node *temp = new node();
temp->base = j;
temp->data = j;
temp->next = NULL;
if (end){
end->next = temp;
end = end->next;
}
else{
head[i]=temp;
end = head[i];
}
}
}
int main(int argc, char const *argv[])
{
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock -1)/threadsPerBlock;
setup_kernel<<<blocksPerGrid, threadsPerBlock>>>();
print_kernel<<<blocksPerGrid, threadsPerBlock>>>();
hipDeviceReset();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cstdio>
#include <hiprand/hiprand_kernel.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/execution_policy.h>
#include <thrust/extrema.h>
#include <thrust/device_ptr.h>
#define N 10
using namespace std;
struct node{
int base;
int data;
node *next;
};
__device__ node *head[N];
__global__ void print_kernel()
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i >= N){
return;
}
node *temp = head[i];
while (temp){
printf("%d and %d from %d\n", temp->base, temp->data, i);
temp = temp->next;
}
}
__global__ void setup_kernel()
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i >= N){
return;
}
head[i]=NULL;
node *end = head[i];
for (int j=i; j<i+5; j++){
node *temp = new node();
temp->base = j;
temp->data = j;
temp->next = NULL;
if (end){
end->next = temp;
end = end->next;
}
else{
head[i]=temp;
end = head[i];
}
}
}
int main(int argc, char const *argv[])
{
int threadsPerBlock = 256;
int blocksPerGrid = (N + threadsPerBlock -1)/threadsPerBlock;
setup_kernel<<<blocksPerGrid, threadsPerBlock>>>();
print_kernel<<<blocksPerGrid, threadsPerBlock>>>();
hipDeviceReset();
return 0;
}
|
.text
.file "linkedListTrial.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__print_kernelv # -- Begin function _Z27__device_stub__print_kernelv
.p2align 4, 0x90
.type _Z27__device_stub__print_kernelv,@function
_Z27__device_stub__print_kernelv: # @_Z27__device_stub__print_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12print_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__print_kernelv, .Lfunc_end0-_Z27__device_stub__print_kernelv
.cfi_endproc
# -- End function
.globl _Z27__device_stub__setup_kernelv # -- Begin function _Z27__device_stub__setup_kernelv
.p2align 4, 0x90
.type _Z27__device_stub__setup_kernelv,@function
_Z27__device_stub__setup_kernelv: # @_Z27__device_stub__setup_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12setup_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z27__device_stub__setup_kernelv, .Lfunc_end1-_Z27__device_stub__setup_kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 255(%r14), %rbx
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12setup_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12print_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12print_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12setup_kernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $head, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $80, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type head,@object # @head
.local head
.comm head,80,16
.type _Z12print_kernelv,@object # @_Z12print_kernelv
.section .rodata,"a",@progbits
.globl _Z12print_kernelv
.p2align 3, 0x0
_Z12print_kernelv:
.quad _Z27__device_stub__print_kernelv
.size _Z12print_kernelv, 8
.type _Z12setup_kernelv,@object # @_Z12setup_kernelv
.globl _Z12setup_kernelv
.p2align 3, 0x0
_Z12setup_kernelv:
.quad _Z27__device_stub__setup_kernelv
.size _Z12setup_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12print_kernelv"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12setup_kernelv"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "head"
.size .L__unnamed_3, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__print_kernelv
.addrsig_sym _Z27__device_stub__setup_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym head
.addrsig_sym _Z12print_kernelv
.addrsig_sym _Z12setup_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <sys/utsname.h>
// Includes, system
#include <stdio.h>
#include <cassert>
// Includes CUDA
#include <cuda_runtime.h>
const char *sampleName = "simpleAssert";
////////////////////////////////////////////////////////////////////////////////
// Auto-Verification Code
bool testResult = true;
////////////////////////////////////////////////////////////////////////////////
// Kernels
////////////////////////////////////////////////////////////////////////////////
//! Tests assert function.
//! Thread whose id > N will print assertion failed error message.
////////////////////////////////////////////////////////////////////////////////
__global__ void testKernel(int N)
{
int gtid = blockIdx.x*blockDim.x + threadIdx.x ;
assert(gtid < N) ;
}
void simpleAssert( void )
{
int Nblocks = 2;
int Nthreads = 32;
cudaError_t error ;
// Kernel configuration, where a one-dimensional
// grid and one-dimensional blocks are configured.
dim3 dimGrid(Nblocks);
dim3 dimBlock(Nthreads);
printf("Launch kernel to generate assertion failures\n");
testKernel<<<dimGrid, dimBlock>>>(60);
//Synchronize (flushes assert output).
printf("\n-- Begin assert output\n\n");
error = cudaDeviceSynchronize();
printf("\n-- End assert output\n\n");
//Check for errors and failed asserts in asynchronous kernel launch.
if (error == cudaErrorAssert)
{
printf("Device assert failed as expected, "
"CUDA error message is: %s\n\n",
cudaGetErrorString(error));
}
testResult = error == cudaErrorAssert;
}
|
code for sm_80
Function : _Z10testKerneli
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <sys/utsname.h>
// Includes, system
#include <stdio.h>
#include <cassert>
// Includes CUDA
#include <cuda_runtime.h>
const char *sampleName = "simpleAssert";
////////////////////////////////////////////////////////////////////////////////
// Auto-Verification Code
bool testResult = true;
////////////////////////////////////////////////////////////////////////////////
// Kernels
////////////////////////////////////////////////////////////////////////////////
//! Tests assert function.
//! Thread whose id > N will print assertion failed error message.
////////////////////////////////////////////////////////////////////////////////
__global__ void testKernel(int N)
{
int gtid = blockIdx.x*blockDim.x + threadIdx.x ;
assert(gtid < N) ;
}
void simpleAssert( void )
{
int Nblocks = 2;
int Nthreads = 32;
cudaError_t error ;
// Kernel configuration, where a one-dimensional
// grid and one-dimensional blocks are configured.
dim3 dimGrid(Nblocks);
dim3 dimBlock(Nthreads);
printf("Launch kernel to generate assertion failures\n");
testKernel<<<dimGrid, dimBlock>>>(60);
//Synchronize (flushes assert output).
printf("\n-- Begin assert output\n\n");
error = cudaDeviceSynchronize();
printf("\n-- End assert output\n\n");
//Check for errors and failed asserts in asynchronous kernel launch.
if (error == cudaErrorAssert)
{
printf("Device assert failed as expected, "
"CUDA error message is: %s\n\n",
cudaGetErrorString(error));
}
testResult = error == cudaErrorAssert;
}
|
.file "tmpxft_00021949_00000000-6_simpleAssert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10testKernelii
.type _Z29__device_stub__Z10testKernelii, @function
_Z29__device_stub__Z10testKernelii:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10testKerneli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10testKernelii, .-_Z29__device_stub__Z10testKernelii
.globl _Z10testKerneli
.type _Z10testKerneli, @function
_Z10testKerneli:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10testKernelii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10testKerneli, .-_Z10testKerneli
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Launch kernel to generate assertion failures\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n-- Begin assert output\n\n"
.LC2:
.string "\n-- End assert output\n\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Device assert failed as expected, CUDA error message is: %s\n\n"
.text
.globl _Z12simpleAssertv
.type _Z12simpleAssertv, @function
_Z12simpleAssertv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $710, %ebx
je .L16
.L13:
cmpl $710, %ebx
sete testResult(%rip)
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $60, %edi
call _Z29__device_stub__Z10testKernelii
jmp .L12
.L16:
movl $710, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.cfi_endproc
.LFE2057:
.size _Z12simpleAssertv, .-_Z12simpleAssertv
.section .rodata.str1.1
.LC4:
.string "_Z10testKerneli"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testKerneli(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl testResult
.data
.type testResult, @object
.size testResult, 1
testResult:
.byte 1
.globl sampleName
.section .rodata.str1.1
.LC5:
.string "simpleAssert"
.section .data.rel.local,"aw"
.align 8
.type sampleName, @object
.size sampleName, 8
sampleName:
.quad .LC5
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <sys/utsname.h>
// Includes, system
#include <stdio.h>
#include <cassert>
// Includes CUDA
#include <cuda_runtime.h>
const char *sampleName = "simpleAssert";
////////////////////////////////////////////////////////////////////////////////
// Auto-Verification Code
bool testResult = true;
////////////////////////////////////////////////////////////////////////////////
// Kernels
////////////////////////////////////////////////////////////////////////////////
//! Tests assert function.
//! Thread whose id > N will print assertion failed error message.
////////////////////////////////////////////////////////////////////////////////
__global__ void testKernel(int N)
{
int gtid = blockIdx.x*blockDim.x + threadIdx.x ;
assert(gtid < N) ;
}
void simpleAssert( void )
{
int Nblocks = 2;
int Nthreads = 32;
cudaError_t error ;
// Kernel configuration, where a one-dimensional
// grid and one-dimensional blocks are configured.
dim3 dimGrid(Nblocks);
dim3 dimBlock(Nthreads);
printf("Launch kernel to generate assertion failures\n");
testKernel<<<dimGrid, dimBlock>>>(60);
//Synchronize (flushes assert output).
printf("\n-- Begin assert output\n\n");
error = cudaDeviceSynchronize();
printf("\n-- End assert output\n\n");
//Check for errors and failed asserts in asynchronous kernel launch.
if (error == cudaErrorAssert)
{
printf("Device assert failed as expected, "
"CUDA error message is: %s\n\n",
cudaGetErrorString(error));
}
testResult = error == cudaErrorAssert;
}
|
#include <sys/utsname.h>
// Includes, system
#include <stdio.h>
#include <cassert>
// Includes CUDA
#include <hip/hip_runtime.h>
const char *sampleName = "simpleAssert";
////////////////////////////////////////////////////////////////////////////////
// Auto-Verification Code
bool testResult = true;
////////////////////////////////////////////////////////////////////////////////
// Kernels
////////////////////////////////////////////////////////////////////////////////
//! Tests assert function.
//! Thread whose id > N will print assertion failed error message.
////////////////////////////////////////////////////////////////////////////////
__global__ void testKernel(int N)
{
int gtid = blockIdx.x*blockDim.x + threadIdx.x ;
assert(gtid < N) ;
}
void simpleAssert( void )
{
int Nblocks = 2;
int Nthreads = 32;
hipError_t error ;
// Kernel configuration, where a one-dimensional
// grid and one-dimensional blocks are configured.
dim3 dimGrid(Nblocks);
dim3 dimBlock(Nthreads);
printf("Launch kernel to generate assertion failures\n");
testKernel<<<dimGrid, dimBlock>>>(60);
//Synchronize (flushes assert output).
printf("\n-- Begin assert output\n\n");
error = hipDeviceSynchronize();
printf("\n-- End assert output\n\n");
//Check for errors and failed asserts in asynchronous kernel launch.
if (error == hipErrorAssert)
{
printf("Device assert failed as expected, "
"CUDA error message is: %s\n\n",
hipGetErrorString(error));
}
testResult = error == hipErrorAssert;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <sys/utsname.h>
// Includes, system
#include <stdio.h>
#include <cassert>
// Includes CUDA
#include <hip/hip_runtime.h>
const char *sampleName = "simpleAssert";
////////////////////////////////////////////////////////////////////////////////
// Auto-Verification Code
bool testResult = true;
////////////////////////////////////////////////////////////////////////////////
// Kernels
////////////////////////////////////////////////////////////////////////////////
//! Tests assert function.
//! Thread whose id > N will print assertion failed error message.
////////////////////////////////////////////////////////////////////////////////
__global__ void testKernel(int N)
{
int gtid = blockIdx.x*blockDim.x + threadIdx.x ;
assert(gtid < N) ;
}
void simpleAssert( void )
{
int Nblocks = 2;
int Nthreads = 32;
hipError_t error ;
// Kernel configuration, where a one-dimensional
// grid and one-dimensional blocks are configured.
dim3 dimGrid(Nblocks);
dim3 dimBlock(Nthreads);
printf("Launch kernel to generate assertion failures\n");
testKernel<<<dimGrid, dimBlock>>>(60);
//Synchronize (flushes assert output).
printf("\n-- Begin assert output\n\n");
error = hipDeviceSynchronize();
printf("\n-- End assert output\n\n");
//Check for errors and failed asserts in asynchronous kernel launch.
if (error == hipErrorAssert)
{
printf("Device assert failed as expected, "
"CUDA error message is: %s\n\n",
hipGetErrorString(error));
}
testResult = error == hipErrorAssert;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10testKerneli
.globl _Z10testKerneli
.p2align 8
.type _Z10testKerneli,@function
_Z10testKerneli:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testKerneli
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10testKerneli, .Lfunc_end0-_Z10testKerneli
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testKerneli
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10testKerneli.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <sys/utsname.h>
// Includes, system
#include <stdio.h>
#include <cassert>
// Includes CUDA
#include <hip/hip_runtime.h>
const char *sampleName = "simpleAssert";
////////////////////////////////////////////////////////////////////////////////
// Auto-Verification Code
bool testResult = true;
////////////////////////////////////////////////////////////////////////////////
// Kernels
////////////////////////////////////////////////////////////////////////////////
//! Tests assert function.
//! Thread whose id > N will print assertion failed error message.
////////////////////////////////////////////////////////////////////////////////
__global__ void testKernel(int N)
{
int gtid = blockIdx.x*blockDim.x + threadIdx.x ;
assert(gtid < N) ;
}
void simpleAssert( void )
{
int Nblocks = 2;
int Nthreads = 32;
hipError_t error ;
// Kernel configuration, where a one-dimensional
// grid and one-dimensional blocks are configured.
dim3 dimGrid(Nblocks);
dim3 dimBlock(Nthreads);
printf("Launch kernel to generate assertion failures\n");
testKernel<<<dimGrid, dimBlock>>>(60);
//Synchronize (flushes assert output).
printf("\n-- Begin assert output\n\n");
error = hipDeviceSynchronize();
printf("\n-- End assert output\n\n");
//Check for errors and failed asserts in asynchronous kernel launch.
if (error == hipErrorAssert)
{
printf("Device assert failed as expected, "
"CUDA error message is: %s\n\n",
hipGetErrorString(error));
}
testResult = error == hipErrorAssert;
}
|
.text
.file "simpleAssert.hip"
.globl _Z25__device_stub__testKerneli # -- Begin function _Z25__device_stub__testKerneli
.p2align 4, 0x90
.type _Z25__device_stub__testKerneli,@function
_Z25__device_stub__testKerneli: # @_Z25__device_stub__testKerneli
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10testKerneli, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__testKerneli, .Lfunc_end0-_Z25__device_stub__testKerneli
.cfi_endproc
# -- End function
.globl _Z12simpleAssertv # -- Begin function _Z12simpleAssertv
.p2align 4, 0x90
.type _Z12simpleAssertv,@function
_Z12simpleAssertv: # @_Z12simpleAssertv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $60, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10testKerneli, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr.1, %edi
callq puts@PLT
callq hipDeviceSynchronize
movl %eax, %ebx
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $710, %ebx # imm = 0x2C6
jne .LBB1_4
# %bb.3:
movl $710, %edi # imm = 0x2C6
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_4:
cmpl $710, %ebx # imm = 0x2C6
sete testResult(%rip)
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12simpleAssertv, .Lfunc_end1-_Z12simpleAssertv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testKerneli, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "simpleAssert"
.size .L.str, 13
.type sampleName,@object # @sampleName
.data
.globl sampleName
.p2align 3, 0x0
sampleName:
.quad .L.str
.size sampleName, 8
.type testResult,@object # @testResult
.globl testResult
testResult:
.byte 1 # 0x1
.size testResult, 1
.type _Z10testKerneli,@object # @_Z10testKerneli
.section .rodata,"a",@progbits
.globl _Z10testKerneli
.p2align 3, 0x0
_Z10testKerneli:
.quad _Z25__device_stub__testKerneli
.size _Z10testKerneli, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Device assert failed as expected, CUDA error message is: %s\n\n"
.size .L.str.4, 62
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10testKerneli"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Launch kernel to generate assertion failures"
.size .Lstr, 45
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n-- Begin assert output\n"
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n-- End assert output\n"
.size .Lstr.2, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testKerneli
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testKerneli
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z10testKerneli
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10testKerneli
.globl _Z10testKerneli
.p2align 8
.type _Z10testKerneli,@function
_Z10testKerneli:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testKerneli
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10testKerneli, .Lfunc_end0-_Z10testKerneli
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testKerneli
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10testKerneli.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00021949_00000000-6_simpleAssert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10testKernelii
.type _Z29__device_stub__Z10testKernelii, @function
_Z29__device_stub__Z10testKernelii:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10testKerneli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10testKernelii, .-_Z29__device_stub__Z10testKernelii
.globl _Z10testKerneli
.type _Z10testKerneli, @function
_Z10testKerneli:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10testKernelii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10testKerneli, .-_Z10testKerneli
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Launch kernel to generate assertion failures\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n-- Begin assert output\n\n"
.LC2:
.string "\n-- End assert output\n\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Device assert failed as expected, CUDA error message is: %s\n\n"
.text
.globl _Z12simpleAssertv
.type _Z12simpleAssertv, @function
_Z12simpleAssertv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $710, %ebx
je .L16
.L13:
cmpl $710, %ebx
sete testResult(%rip)
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $60, %edi
call _Z29__device_stub__Z10testKernelii
jmp .L12
.L16:
movl $710, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.cfi_endproc
.LFE2057:
.size _Z12simpleAssertv, .-_Z12simpleAssertv
.section .rodata.str1.1
.LC4:
.string "_Z10testKerneli"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testKerneli(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl testResult
.data
.type testResult, @object
.size testResult, 1
testResult:
.byte 1
.globl sampleName
.section .rodata.str1.1
.LC5:
.string "simpleAssert"
.section .data.rel.local,"aw"
.align 8
.type sampleName, @object
.size sampleName, 8
sampleName:
.quad .LC5
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "simpleAssert.hip"
.globl _Z25__device_stub__testKerneli # -- Begin function _Z25__device_stub__testKerneli
.p2align 4, 0x90
.type _Z25__device_stub__testKerneli,@function
_Z25__device_stub__testKerneli: # @_Z25__device_stub__testKerneli
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10testKerneli, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__testKerneli, .Lfunc_end0-_Z25__device_stub__testKerneli
.cfi_endproc
# -- End function
.globl _Z12simpleAssertv # -- Begin function _Z12simpleAssertv
.p2align 4, 0x90
.type _Z12simpleAssertv,@function
_Z12simpleAssertv: # @_Z12simpleAssertv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $60, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10testKerneli, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr.1, %edi
callq puts@PLT
callq hipDeviceSynchronize
movl %eax, %ebx
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $710, %ebx # imm = 0x2C6
jne .LBB1_4
# %bb.3:
movl $710, %edi # imm = 0x2C6
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_4:
cmpl $710, %ebx # imm = 0x2C6
sete testResult(%rip)
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12simpleAssertv, .Lfunc_end1-_Z12simpleAssertv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testKerneli, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "simpleAssert"
.size .L.str, 13
.type sampleName,@object # @sampleName
.data
.globl sampleName
.p2align 3, 0x0
sampleName:
.quad .L.str
.size sampleName, 8
.type testResult,@object # @testResult
.globl testResult
testResult:
.byte 1 # 0x1
.size testResult, 1
.type _Z10testKerneli,@object # @_Z10testKerneli
.section .rodata,"a",@progbits
.globl _Z10testKerneli
.p2align 3, 0x0
_Z10testKerneli:
.quad _Z25__device_stub__testKerneli
.size _Z10testKerneli, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Device assert failed as expected, CUDA error message is: %s\n\n"
.size .L.str.4, 62
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10testKerneli"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Launch kernel to generate assertion failures"
.size .Lstr, 45
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n-- Begin assert output\n"
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n-- End assert output\n"
.size .Lstr.2, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testKerneli
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testKerneli
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
extern "C"
__global__ void add(int n, float *a, float *b, float *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
while(i < n) {
sum[i] = a[i] + b[i];
i = i + blockDim.x * gridDim.x;
}
}
|
code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
extern "C"
__global__ void add(int n, float *a, float *b, float *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
while(i < n) {
sum[i] = a[i] + b[i];
i = i + blockDim.x * gridDim.x;
}
}
|
.file "tmpxft_000f84b0_00000000-6_JCudaVectorAddKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addiPfS_S_iPfS_S_
.type _Z27__device_stub__Z3addiPfS_S_iPfS_S_, @function
_Z27__device_stub__Z3addiPfS_S_iPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addiPfS_S_iPfS_S_, .-_Z27__device_stub__Z3addiPfS_S_iPfS_S_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
extern "C"
__global__ void add(int n, float *a, float *b, float *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
while(i < n) {
sum[i] = a[i] + b[i];
i = i + blockDim.x * gridDim.x;
}
}
|
#include <hip/hip_runtime.h>
extern "C"
__global__ void add(int n, float *a, float *b, float *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
while(i < n) {
sum[i] = a[i] + b[i];
i = i + blockDim.x * gridDim.x;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
extern "C"
__global__ void add(int n, float *a, float *b, float *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
while(i < n) {
sum[i] = a[i] + b[i];
i = i + blockDim.x * gridDim.x;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
extern "C"
__global__ void add(int n, float *a, float *b, float *sum)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
while(i < n) {
sum[i] = a[i] + b[i];
i = i + blockDim.x * gridDim.x;
}
}
|
.text
.file "JCudaVectorAddKernel.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000f84b0_00000000-6_JCudaVectorAddKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addiPfS_S_iPfS_S_
.type _Z27__device_stub__Z3addiPfS_S_iPfS_S_, @function
_Z27__device_stub__Z3addiPfS_S_iPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addiPfS_S_iPfS_S_, .-_Z27__device_stub__Z3addiPfS_S_iPfS_S_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "JCudaVectorAddKernel.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <math.h>
#include <stdio.h>
__global__
void add(double *a,double*b,double* c,int n) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id>0)
c[id] = a[id] + b[id];
}
int main()
{
int n = 100;
// Device input vectors
double *d_a;
double *d_b;
//Device output vector
double *d_c;
int i=0;
cudaMallocManaged(&d_a,n*sizeof(double));
cudaMallocManaged(&d_b,n*sizeof(double));
cudaMallocManaged(&d_c,n*sizeof(double));
for ( i = 0; i < n; i++) {
d_a[i] = i;
d_b[i] = i;
}
int blockSize = 512;
// Number of thread blocks in grid
int gridSize = (int)ceil((float)n/blockSize);
add <<< gridSize,blockSize >>>(d_a,d_b,d_c,n);
cudaDeviceSynchronize();
printf("%d %d\n",gridSize,blockSize );
for(i=0;i<n;i++)
{
printf("%f + %f = %f\n",d_a[i],d_b[i],d_c[i]);
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
/*float maxError = 0.0f;
for (int i = 0; i < n; i++)
maxError = fmax(maxError, fabs(d_c[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;*/
}
|
code for sm_80
Function : _Z3addPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <math.h>
#include <stdio.h>
__global__
void add(double *a,double*b,double* c,int n) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id>0)
c[id] = a[id] + b[id];
}
int main()
{
int n = 100;
// Device input vectors
double *d_a;
double *d_b;
//Device output vector
double *d_c;
int i=0;
cudaMallocManaged(&d_a,n*sizeof(double));
cudaMallocManaged(&d_b,n*sizeof(double));
cudaMallocManaged(&d_c,n*sizeof(double));
for ( i = 0; i < n; i++) {
d_a[i] = i;
d_b[i] = i;
}
int blockSize = 512;
// Number of thread blocks in grid
int gridSize = (int)ceil((float)n/blockSize);
add <<< gridSize,blockSize >>>(d_a,d_b,d_c,n);
cudaDeviceSynchronize();
printf("%d %d\n",gridSize,blockSize );
for(i=0;i<n;i++)
{
printf("%f + %f = %f\n",d_a[i],d_b[i],d_c[i]);
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
/*float maxError = 0.0f;
for (int i = 0; i < n; i++)
maxError = fmax(maxError, fabs(d_c[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;*/
}
|
.file "tmpxft_0014fc9c_00000000-6_q2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPdS_S_iPdS_S_i
.type _Z27__device_stub__Z3addPdS_S_iPdS_S_i, @function
_Z27__device_stub__Z3addPdS_S_iPdS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addPdS_S_iPdS_S_i, .-_Z27__device_stub__Z3addPdS_S_iPdS_S_i
.globl _Z3addPdS_S_i
.type _Z3addPdS_S_i, @function
_Z3addPdS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPdS_S_i, .-_Z3addPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %d\n"
.LC1:
.string "%f + %f = %f\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $800, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $800, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $800, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movq 8(%rsp), %rdx
movsd %xmm0, (%rdx,%rax,8)
movq 16(%rsp), %rdx
movsd %xmm0, (%rdx,%rax,8)
addq $1, %rax
cmpq $100, %rax
jne .L12
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $512, %ecx
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L14:
movq 8(%rsp), %rax
movsd (%rax,%rbx), %xmm0
movq 24(%rsp), %rax
movsd (%rax,%rbx), %xmm2
movq 16(%rsp), %rax
movsd (%rax,%rbx), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq $800, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $100, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPdS_S_iPdS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <math.h>
#include <stdio.h>
__global__
void add(double *a,double*b,double* c,int n) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id>0)
c[id] = a[id] + b[id];
}
int main()
{
int n = 100;
// Device input vectors
double *d_a;
double *d_b;
//Device output vector
double *d_c;
int i=0;
cudaMallocManaged(&d_a,n*sizeof(double));
cudaMallocManaged(&d_b,n*sizeof(double));
cudaMallocManaged(&d_c,n*sizeof(double));
for ( i = 0; i < n; i++) {
d_a[i] = i;
d_b[i] = i;
}
int blockSize = 512;
// Number of thread blocks in grid
int gridSize = (int)ceil((float)n/blockSize);
add <<< gridSize,blockSize >>>(d_a,d_b,d_c,n);
cudaDeviceSynchronize();
printf("%d %d\n",gridSize,blockSize );
for(i=0;i<n;i++)
{
printf("%f + %f = %f\n",d_a[i],d_b[i],d_c[i]);
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
/*float maxError = 0.0f;
for (int i = 0; i < n; i++)
maxError = fmax(maxError, fabs(d_c[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;*/
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <stdio.h>
__global__
void add(double *a,double*b,double* c,int n) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id>0)
c[id] = a[id] + b[id];
}
int main()
{
int n = 100;
// Device input vectors
double *d_a;
double *d_b;
//Device output vector
double *d_c;
int i=0;
hipMallocManaged(&d_a,n*sizeof(double));
hipMallocManaged(&d_b,n*sizeof(double));
hipMallocManaged(&d_c,n*sizeof(double));
for ( i = 0; i < n; i++) {
d_a[i] = i;
d_b[i] = i;
}
int blockSize = 512;
// Number of thread blocks in grid
int gridSize = (int)ceil((float)n/blockSize);
add <<< gridSize,blockSize >>>(d_a,d_b,d_c,n);
hipDeviceSynchronize();
printf("%d %d\n",gridSize,blockSize );
for(i=0;i<n;i++)
{
printf("%f + %f = %f\n",d_a[i],d_b[i],d_c[i]);
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
/*float maxError = 0.0f;
for (int i = 0; i < n; i++)
maxError = fmax(maxError, fabs(d_c[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;*/
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <stdio.h>
__global__
void add(double *a,double*b,double* c,int n) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id>0)
c[id] = a[id] + b[id];
}
int main()
{
int n = 100;
// Device input vectors
double *d_a;
double *d_b;
//Device output vector
double *d_c;
int i=0;
hipMallocManaged(&d_a,n*sizeof(double));
hipMallocManaged(&d_b,n*sizeof(double));
hipMallocManaged(&d_c,n*sizeof(double));
for ( i = 0; i < n; i++) {
d_a[i] = i;
d_b[i] = i;
}
int blockSize = 512;
// Number of thread blocks in grid
int gridSize = (int)ceil((float)n/blockSize);
add <<< gridSize,blockSize >>>(d_a,d_b,d_c,n);
hipDeviceSynchronize();
printf("%d %d\n",gridSize,blockSize );
for(i=0;i<n;i++)
{
printf("%f + %f = %f\n",d_a[i],d_b[i],d_c[i]);
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
/*float maxError = 0.0f;
for (int i = 0; i < n; i++)
maxError = fmax(maxError, fabs(d_c[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;*/
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdS_S_i
.globl _Z3addPdS_S_i
.p2align 8
.type _Z3addPdS_S_i,@function
_Z3addPdS_S_i:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdS_S_i, .Lfunc_end0-_Z3addPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <stdio.h>
__global__
void add(double *a,double*b,double* c,int n) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if(id>0)
c[id] = a[id] + b[id];
}
int main()
{
int n = 100;
// Device input vectors
double *d_a;
double *d_b;
//Device output vector
double *d_c;
int i=0;
hipMallocManaged(&d_a,n*sizeof(double));
hipMallocManaged(&d_b,n*sizeof(double));
hipMallocManaged(&d_c,n*sizeof(double));
for ( i = 0; i < n; i++) {
d_a[i] = i;
d_b[i] = i;
}
int blockSize = 512;
// Number of thread blocks in grid
int gridSize = (int)ceil((float)n/blockSize);
add <<< gridSize,blockSize >>>(d_a,d_b,d_c,n);
hipDeviceSynchronize();
printf("%d %d\n",gridSize,blockSize );
for(i=0;i<n;i++)
{
printf("%f + %f = %f\n",d_a[i],d_b[i],d_c[i]);
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
/*float maxError = 0.0f;
for (int i = 0; i < n; i++)
maxError = fmax(maxError, fabs(d_c[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;*/
}
|
.text
.file "q2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPdS_S_i # -- Begin function _Z18__device_stub__addPdS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPdS_S_i,@function
_Z18__device_stub__addPdS_S_i: # @_Z18__device_stub__addPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdS_S_i, .Lfunc_end0-_Z18__device_stub__addPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $800, %esi # imm = 0x320
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $800, %esi # imm = 0x320
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%rax,%rcx,8)
movsd %xmm0, (%rdx,%rcx,8)
incq %rcx
cmpq $100, %rcx
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
movl $.L.str, %edi
movl $1, %esi
movl $512, %edx # imm = 0x200
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movsd (%rax,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movq 8(%rsp), %rax
movsd (%rax,%rbx,8), %xmm1 # xmm1 = mem[0],zero
movq 24(%rsp), %rax
movsd (%rax,%rbx,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.1, %edi
movb $3, %al
callq printf
incq %rbx
cmpq $100, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdS_S_i,@object # @_Z3addPdS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPdS_S_i
.p2align 3, 0x0
_Z3addPdS_S_i:
.quad _Z18__device_stub__addPdS_S_i
.size _Z3addPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d\n"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f + %f = %f\n"
.size .L.str.1, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPdS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3addPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdS_S_i
.globl _Z3addPdS_S_i
.p2align 8
.type _Z3addPdS_S_i,@function
_Z3addPdS_S_i:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdS_S_i, .Lfunc_end0-_Z3addPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0014fc9c_00000000-6_q2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPdS_S_iPdS_S_i
.type _Z27__device_stub__Z3addPdS_S_iPdS_S_i, @function
_Z27__device_stub__Z3addPdS_S_iPdS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addPdS_S_iPdS_S_i, .-_Z27__device_stub__Z3addPdS_S_iPdS_S_i
.globl _Z3addPdS_S_i
.type _Z3addPdS_S_i, @function
_Z3addPdS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPdS_S_i, .-_Z3addPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %d\n"
.LC1:
.string "%f + %f = %f\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $800, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $800, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $800, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movq 8(%rsp), %rdx
movsd %xmm0, (%rdx,%rax,8)
movq 16(%rsp), %rdx
movsd %xmm0, (%rdx,%rax,8)
addq $1, %rax
cmpq $100, %rax
jne .L12
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $512, %ecx
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L14:
movq 8(%rsp), %rax
movsd (%rax,%rbx), %xmm0
movq 24(%rsp), %rax
movsd (%rax,%rbx), %xmm2
movq 16(%rsp), %rax
movsd (%rax,%rbx), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq $800, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $100, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPdS_S_iPdS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "q2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPdS_S_i # -- Begin function _Z18__device_stub__addPdS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPdS_S_i,@function
_Z18__device_stub__addPdS_S_i: # @_Z18__device_stub__addPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdS_S_i, .Lfunc_end0-_Z18__device_stub__addPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $800, %esi # imm = 0x320
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $800, %esi # imm = 0x320
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%rax,%rcx,8)
movsd %xmm0, (%rdx,%rcx,8)
incq %rcx
cmpq $100, %rcx
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
movl $.L.str, %edi
movl $1, %esi
movl $512, %edx # imm = 0x200
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movsd (%rax,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movq 8(%rsp), %rax
movsd (%rax,%rbx,8), %xmm1 # xmm1 = mem[0],zero
movq 24(%rsp), %rax
movsd (%rax,%rbx,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.1, %edi
movb $3, %al
callq printf
incq %rbx
cmpq $100, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdS_S_i,@object # @_Z3addPdS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPdS_S_i
.p2align 3, 0x0
_Z3addPdS_S_i:
.quad _Z18__device_stub__addPdS_S_i
.size _Z3addPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d\n"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f + %f = %f\n"
.size .L.str.1, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPdS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void kSelectRows(float* source, float* target, float* indices, int nRowIs, int nCols, int nSourceRows){
__shared__ int sourceRowIndices[32];
const int startTargetRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startTargetRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
sourceRowIndices[tid] = int(indices[startTargetRowI + tid]);
if (sourceRowIndices[tid]<0)
sourceRowIndices[tid] += nSourceRows;
if (sourceRowIndices[tid]<0 || sourceRowIndices[tid]>=nSourceRows)
sourceRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int targetRowI = startTargetRowI + i, sourceRowI = sourceRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = sourceRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
}
|
code for sm_80
Function : _Z11kSelectRowsPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, -0x20 ; /* 0xffffffe0ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x170 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R2, R5, c[0x0][0x178] ; /* 0x00005e0002007624 */
/* 0x001fca00078e0205 */
/*0070*/ IMNMX R4, R0.reuse, 0x20, PT ; /* 0x0000002000047817 */
/* 0x040fe40003800200 */
/*0080*/ ISETP.GE.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f26270 */
/*0090*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x002fda0003f06270 */
/*00a0*/ @P0 BRA 0x160 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R6, R2, 0x20, R3 ; /* 0x0000002002067824 */
/* 0x000fe400078e0203 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ F2I.TRUNC.NTZ R0, R6 ; /* 0x0000000600007305 */
/* 0x004e24000020f100 */
/*0100*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f06270 */
/*0110*/ @!P0 IADD3 R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000008a10 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f06270 */
/*0130*/ ISETP.GT.AND P0, PT, R0, -0x1, !P0 ; /* 0xffffffff0000780c */
/* 0x000fc80004704270 */
/*0140*/ SEL R0, R0, 0xffffffff, P0 ; /* 0xffffffff00007807 */
/* 0x000fca0000000000 */
/*0150*/ STS [R3.X4], R0 ; /* 0x0000000003007388 */
/* 0x0001e80000004800 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0190*/ LOP3.LUT R5, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff057212 */
/* 0x000fe200078e33ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01b0*/ IADD3 R6, R3, 0x20, RZ ; /* 0x0000002003067810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ IADD3 R5, R5, c[0x0][0x17c], RZ ; /* 0x00005f0005057a10 */
/* 0x000fc40007ffe0ff */
/*01d0*/ IADD3 R7, R3, 0x40, RZ ; /* 0x0000004003077810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ LEA.HI R9, R5, 0x1, RZ, 0x1b ; /* 0x0000000105097811 */
/* 0x000fe400078fd8ff */
/*01f0*/ IADD3 R8, R3, 0x60, RZ ; /* 0x0000006003087810 */
/* 0x000fe40007ffe0ff */
/*0200*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe400078ec0ff */
/*0210*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0220*/ BSSY B0, 0x940 ; /* 0x0000071000007945 */
/* 0x000fd80003800000 */
/*0230*/ @P0 BRA 0x930 ; /* 0x000006f000000947 */
/* 0x003fea0003800000 */
/*0240*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fe2000800063f */
/*0250*/ LEA R20, R2, UR4, 0x5 ; /* 0x0000000402147c11 */
/* 0x000fe2000f8e28ff */
/*0260*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD R16, R20, c[0x0][0x17c], R3 ; /* 0x00005f0014107a24 */
/* 0x000fc600078e0203 */
/*0280*/ LDS R0, [UR5] ; /* 0x00000005ff007984 */
/* 0x001e220008000800 */
/*0290*/ IMAD.WIDE R16, R16, R19, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fe200078e0213 */
/*02a0*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x001fda0003f05270 */
/*02b0*/ @!P0 BRA 0x600 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*02d0*/ BSSY B1, 0x400 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*02e0*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x000fd60000000f00 */
/*02f0*/ @!P0 BRA 0x3f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD R10, R0, c[0x0][0x17c], R3 ; /* 0x00005f00000a7a24 */
/* 0x000fc800078e0203 */
/*0310*/ IMAD.WIDE R10, R10, R19, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e0213 */
/*0320*/ LDG.E R13, [R10.64] ; /* 0x000000060a0d7981 */
/* 0x000ea2000c1e1900 */
/*0330*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f05270 */
/*0340*/ IMAD.MOV.U32 R15, RZ, RZ, R6 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0006 */
/*0350*/ STG.E [R16.64], R13 ; /* 0x0000000d10007986 */
/* 0x0041f4000c101906 */
/*0360*/ @!P0 BRA 0x3f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R13, [R10.64+0x80] ; /* 0x000080060a0d7981 */
/* 0x001ea2000c1e1900 */
/*0380*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f05270 */
/*0390*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fc400078e0007 */
/*03a0*/ STG.E [R16.64+0x80], R13 ; /* 0x0000800d10007986 */
/* 0x0041f4000c101906 */
/*03b0*/ @!P0 BRA 0x3f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R11, [R10.64+0x100] ; /* 0x000100060a0b7981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IMAD.MOV.U32 R15, RZ, RZ, R8 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e0008 */
/*03e0*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0043e8000c101906 */
/*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.GE.U32.AND P0, PT, R5, 0x60, PT ; /* 0x000000600500780c */
/* 0x000fe20003f06070 */
/*0410*/ BSSY B1, 0x5f0 ; /* 0x000001d000017945 */
/* 0x000fd80003800000 */
/*0420*/ @!P0 BRA 0x5e0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0430*/ IMAD R10, R0, c[0x0][0x17c], R15.reuse ; /* 0x00005f00000a7a24 */
/* 0x100fe400078e020f */
/*0440*/ IMAD R27, R20, c[0x0][0x17c], R15 ; /* 0x00005f00141b7a24 */
/* 0x000fe400078e020f */
/*0450*/ IMAD.WIDE R10, R10, R19, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x002fc800078e0213 */
/*0460*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000a */
/*0470*/ MOV R17, R11 ; /* 0x0000000b00117202 */
/* 0x001fe20000000f00 */
/*0480*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.MOV.U32 R25, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff197624 */
/* 0x000fe400078e00ff */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*04b0*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e0011 */
/*04c0*/ LDG.E R17, [R10.64] ; /* 0x000000060a117981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ MOV R12, R0 ; /* 0x00000000000c7202 */
/* 0x002fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R13, RZ, RZ, R25 ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e0019 */
/*04f0*/ IMAD.WIDE R12, R27, 0x4, R12 ; /* 0x000000041b0c7825 */
/* 0x000fca00078e020c */
/*0500*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0041e8000c101906 */
/*0510*/ LDG.E R19, [R10.64+0x80] ; /* 0x000080060a137981 */
/* 0x000ea8000c1e1900 */
/*0520*/ STG.E [R12.64+0x80], R19 ; /* 0x000080130c007986 */
/* 0x0043e8000c101906 */
/*0530*/ LDG.E R21, [R10.64+0x100] ; /* 0x000100060a157981 */
/* 0x000ea8000c1e1900 */
/*0540*/ STG.E [R12.64+0x100], R21 ; /* 0x000100150c007986 */
/* 0x0043e8000c101906 */
/*0550*/ LDG.E R23, [R10.64+0x180] ; /* 0x000180060a177981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IADD3 R15, R15, 0x80, RZ ; /* 0x000000800f0f7810 */
/* 0x000fc40007ffe0ff */
/*0570*/ IADD3 R0, P1, R0, 0x200, RZ ; /* 0x0000020000007810 */
/* 0x000fe40007f3e0ff */
/*0580*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fe40003f06270 */
/*0590*/ IADD3 R14, P2, R10, 0x200, RZ ; /* 0x000002000a0e7810 */
/* 0x000fe20007f5e0ff */
/*05a0*/ IMAD.X R25, RZ, RZ, R25, P1 ; /* 0x000000ffff197224 */
/* 0x000fc800008e0619 */
/*05b0*/ IMAD.X R17, RZ, RZ, R11, P2 ; /* 0x000000ffff117224 */
/* 0x001fe200010e060b */
/*05c0*/ STG.E [R12.64+0x180], R23 ; /* 0x000180170c007986 */
/* 0x0043ea000c101906 */
/*05d0*/ @!P0 BRA 0x4a0 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*05e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x930 ; /* 0x0000033000007947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0610*/ BSSY B1, 0x7f0 ; /* 0x000001d000017945 */
/* 0x000fe20003800000 */
/*0620*/ IMAD.MOV.U32 R21, RZ, RZ, R3 ; /* 0x000000ffff157224 */
/* 0x000fd600078e0003 */
/*0630*/ @!P0 BRA 0x7e0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0640*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0650*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f05270 */
/*0660*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe200078e00ff */
/*0670*/ MOV R0, 0x690 ; /* 0x0000069000007802 */
/* 0x000fcc0000000f00 */
/*0680*/ CALL.REL.NOINC 0x980 ; /* 0x000002f000007944 */
/* 0x000fea0003c00000 */
/*0690*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe400078e000c */
/*06a0*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000d */
/*06b0*/ IMAD.MOV.U32 R21, RZ, RZ, R6 ; /* 0x000000ffff157224 */
/* 0x000fc800078e0006 */
/*06c0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e14000000080a */
/*06d0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*06e0*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0011e2000c101906 */
/*06f0*/ @!P0 BRA 0x7e0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0700*/ STG.E [R16.64+0x80], R11 ; /* 0x0000800b10007986 */
/* 0x0003e2000c101906 */
/*0710*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe40003f05270 */
/*0720*/ MOV R21, R7 ; /* 0x0000000700157202 */
/* 0x000fd60000000f00 */
/*0730*/ @!P0 BRA 0x7e0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0740*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e00ff */
/*0750*/ MOV R0, 0x780 ; /* 0x0000078000007802 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe400078e00ff */
/*0770*/ CALL.REL.NOINC 0x980 ; /* 0x0000020000007944 */
/* 0x001fea0003c00000 */
/*0780*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e000c */
/*0790*/ MOV R21, R8 ; /* 0x0000000800157202 */
/* 0x000fe20000000f00 */
/*07a0*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e000d */
/*07b0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e14000000080a */
/*07c0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*07d0*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0011e4000c101906 */
/*07e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R5, 0x60, PT ; /* 0x000000600500780c */
/* 0x000fda0003f06070 */
/*0800*/ @!P0 BRA 0x930 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x001fe200078e00ff */
/*0820*/ MOV R0, 0x880 ; /* 0x0000088000007802 */
/* 0x000fe20000000f00 */
/*0830*/ IMAD R16, R20, c[0x0][0x17c], R21 ; /* 0x00005f0014107a24 */
/* 0x000fe400078e0215 */
/*0840*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0850*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe400078e00ff */
/*0860*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fc800078e0211 */
/*0870*/ CALL.REL.NOINC 0x980 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0880*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e000c */
/*0890*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe40000000f00 */
/*08a0*/ IADD3 R21, R21, 0x80, RZ ; /* 0x0000008015157810 */
/* 0x000fc80007ffe0ff */
/*08b0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e22000000080a */
/*08c0*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x17c], PT ; /* 0x00005f0015007a0c */
/* 0x000fd20003f06270 */
/*08d0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*08e0*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0011e8000c101906 */
/*08f0*/ STG.E [R16.64+0x80], R11 ; /* 0x0000800b10007986 */
/* 0x0001e8000c101906 */
/*0900*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0001e8000c101906 */
/*0910*/ STG.E [R16.64+0x180], R11 ; /* 0x0001800b10007986 */
/* 0x0001e2000c101906 */
/*0920*/ @!P0 BRA 0x810 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0930*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0940*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0950*/ ISETP.LE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf03270 */
/*0960*/ @!P0 BRA 0x210 ; /* 0xfffff8a000008947 */
/* 0x000fea000383ffff */
/*0970*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0980*/ IMAD.MOV.U32 R11, RZ, RZ, R10 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e000a */
/*0990*/ DSETP.GTU.AND P1, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f2c200 */
/*09a0*/ @P1 BRA 0xbb0 ; /* 0x0000020000001947 */
/* 0x001fea0003800000 */
/*09b0*/ LOP3.LUT R14, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0a0e7812 */
/* 0x000fc800078ec0ff */
/*09c0*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ ISETP.GE.U32.AND P1, PT, R12, 0x7fefffff, PT ; /* 0x7fefffff0c00780c */
/* 0x000fda0003f26070 */
/*09e0*/ @P1 LOP3.LUT R13, R11, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff000000b0d1812 */
/* 0x000fe200078e3cff */
/*09f0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e00ff */
/*0a00*/ @P1 BRA 0xbd0 ; /* 0x000001c000001947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.U32.AND P1, PT, R14, 0x1000001, PT ; /* 0x010000010e00780c */
/* 0x000fda0003f26070 */
/*0a20*/ @!P1 BRA 0xb10 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0a30*/ IADD3 R13, R11, -0x3fe00000, RZ ; /* 0xc02000000b0d7810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*0a50*/ IMAD.MOV.U32 R14, RZ, RZ, R19 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0013 */
/*0a60*/ MUFU.RCP64H R15, R13 ; /* 0x0000000d000f7308 */
/* 0x000e2a0000001800 */
/*0a70*/ DFMA R18, -R12, R14, 1 ; /* 0x3ff000000c12742b */
/* 0x001e0c000000010e */
/*0a80*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0a90*/ DFMA R18, R14, R18, R14 ; /* 0x000000120e12722b */
/* 0x001e0c000000000e */
/*0aa0*/ DFMA R14, -R12, R18, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000112 */
/*0ab0*/ DFMA R14, R18, R14, R18 ; /* 0x0000000e120e722b */
/* 0x001e0c0000000012 */
/*0ac0*/ DMUL R14, R14, 2.2250738585072013831e-308 ; /* 0x001000000e0e7828 */
/* 0x001e0c0000000000 */
/*0ad0*/ DFMA R10, -R10, R14, 1 ; /* 0x3ff000000a0a742b */
/* 0x001e0c000000010e */
/*0ae0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0af0*/ DFMA R12, R14, R10, R14 ; /* 0x0000000a0e0c722b */
/* 0x001062000000000e */
/*0b00*/ BRA 0xbd0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0b10*/ DMUL R14, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0e7828 */
/* 0x0000640000000000 */
/*0b20*/ MOV R10, R19 ; /* 0x00000013000a7202 */
/* 0x001fc80000000f00 */
/*0b30*/ MUFU.RCP64H R11, R15 ; /* 0x0000000f000b7308 */
/* 0x002e240000001800 */
/*0b40*/ DFMA R12, -R14, R10, 1 ; /* 0x3ff000000e0c742b */
/* 0x001e0c000000010a */
/*0b50*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0b60*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0b70*/ DFMA R10, -R14, R12, 1 ; /* 0x3ff000000e0a742b */
/* 0x001e0c000000010c */
/*0b80*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*0b90*/ DMUL R12, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0c7828 */
/* 0x0010620000000000 */
/*0ba0*/ BRA 0xbd0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0d7812 */
/* 0x000fe200078efcff */
/*0bc0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*0bd0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0000 */
/*0be0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*0bf0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff4000a007950 */
/* 0x000fea0003c3ffff */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void kSelectRows(float* source, float* target, float* indices, int nRowIs, int nCols, int nSourceRows){
__shared__ int sourceRowIndices[32];
const int startTargetRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startTargetRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
sourceRowIndices[tid] = int(indices[startTargetRowI + tid]);
if (sourceRowIndices[tid]<0)
sourceRowIndices[tid] += nSourceRows;
if (sourceRowIndices[tid]<0 || sourceRowIndices[tid]>=nSourceRows)
sourceRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int targetRowI = startTargetRowI + i, sourceRowI = sourceRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = sourceRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
}
|
.file "tmpxft_00072e3e_00000000-6_kSelectRows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii
.type _Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii, @function
_Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11kSelectRowsPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii, .-_Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii
.globl _Z11kSelectRowsPfS_S_iii
.type _Z11kSelectRowsPfS_S_iii, @function
_Z11kSelectRowsPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kSelectRowsPfS_S_iii, .-_Z11kSelectRowsPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kSelectRowsPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kSelectRowsPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void kSelectRows(float* source, float* target, float* indices, int nRowIs, int nCols, int nSourceRows){
__shared__ int sourceRowIndices[32];
const int startTargetRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startTargetRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
sourceRowIndices[tid] = int(indices[startTargetRowI + tid]);
if (sourceRowIndices[tid]<0)
sourceRowIndices[tid] += nSourceRows;
if (sourceRowIndices[tid]<0 || sourceRowIndices[tid]>=nSourceRows)
sourceRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int targetRowI = startTargetRowI + i, sourceRowI = sourceRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = sourceRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kSelectRows(float* source, float* target, float* indices, int nRowIs, int nCols, int nSourceRows){
__shared__ int sourceRowIndices[32];
const int startTargetRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startTargetRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
sourceRowIndices[tid] = int(indices[startTargetRowI + tid]);
if (sourceRowIndices[tid]<0)
sourceRowIndices[tid] += nSourceRows;
if (sourceRowIndices[tid]<0 || sourceRowIndices[tid]>=nSourceRows)
sourceRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int targetRowI = startTargetRowI + i, sourceRowI = sourceRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = sourceRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kSelectRows(float* source, float* target, float* indices, int nRowIs, int nCols, int nSourceRows){
__shared__ int sourceRowIndices[32];
const int startTargetRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startTargetRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
sourceRowIndices[tid] = int(indices[startTargetRowI + tid]);
if (sourceRowIndices[tid]<0)
sourceRowIndices[tid] += nSourceRows;
if (sourceRowIndices[tid]<0 || sourceRowIndices[tid]>=nSourceRows)
sourceRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int targetRowI = startTargetRowI + i, sourceRowI = sourceRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = sourceRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kSelectRowsPfS_S_iii
.globl _Z11kSelectRowsPfS_S_iii
.p2align 8
.type _Z11kSelectRowsPfS_S_iii,@function
_Z11kSelectRowsPfS_S_iii:
s_load_b32 s2, s[0:1], 0x18
s_lshl_b32 s5, s15, 5
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s2, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_i32 s2, s3, 32
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x10
v_add_nc_u32_e32 v1, s5, v0
s_load_b32 s5, s[0:1], 0x20
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_and_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v2, v1
v_max_i32_e32 v2, -1, v1
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, -1, v2, vcc_lo
ds_store_b32 v3, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_i32 s3, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_12
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_max_i32 s8, s2, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s3, v0
s_mul_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s9, s15, 5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_10
s_lshl_b32 s1, s10, 2
s_mov_b32 s12, 0
v_mov_b32_e32 v1, s1
ds_load_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v2, s3
v_cmp_ne_u32_e64 s1, -1, v2
v_mov_b32_e32 v2, v0
s_branch .LBB0_8
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v1, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
.LBB0_7:
v_add_nc_u32_e32 v4, s9, v2
v_add_nc_u32_e32 v2, 32, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_cmp_le_i32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_or_b32 s12, vcc_lo, s12
v_add_co_u32 v4, s2, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s7, v5, s2
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v3, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_10
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccz .LBB0_6
v_mov_b32_e32 v3, 0x7fc00000
s_branch .LBB0_7
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_add_i32 s9, s9, s3
s_cmp_eq_u32 s10, s8
s_cbranch_scc0 .LBB0_4
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kSelectRowsPfS_S_iii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kSelectRowsPfS_S_iii, .Lfunc_end0-_Z11kSelectRowsPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kSelectRowsPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kSelectRowsPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kSelectRows(float* source, float* target, float* indices, int nRowIs, int nCols, int nSourceRows){
__shared__ int sourceRowIndices[32];
const int startTargetRowI = blockIdx.x * 32;
const int tid = threadIdx.x;
const int localNRowIs = min(32, nRowIs-startTargetRowI);
// cooperatively load 32 row indices
if (tid < localNRowIs){
sourceRowIndices[tid] = int(indices[startTargetRowI + tid]);
if (sourceRowIndices[tid]<0)
sourceRowIndices[tid] += nSourceRows;
if (sourceRowIndices[tid]<0 || sourceRowIndices[tid]>=nSourceRows)
sourceRowIndices[tid] = -1;
}
__syncthreads();
// copy 32 rows
for (int i=0; i<localNRowIs; i++){
const int targetRowI = startTargetRowI + i, sourceRowI = sourceRowIndices[i];
for (int colI=tid; colI<nCols; colI+=32)
target[targetRowI * nCols + colI] = sourceRowI==-1 ? (1.0/0.0 -1.0/0.0) : source[sourceRowI * nCols + colI];
}
}
|
.text
.file "kSelectRows.hip"
.globl _Z26__device_stub__kSelectRowsPfS_S_iii # -- Begin function _Z26__device_stub__kSelectRowsPfS_S_iii
.p2align 4, 0x90
.type _Z26__device_stub__kSelectRowsPfS_S_iii,@function
_Z26__device_stub__kSelectRowsPfS_S_iii: # @_Z26__device_stub__kSelectRowsPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11kSelectRowsPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__kSelectRowsPfS_S_iii, .Lfunc_end0-_Z26__device_stub__kSelectRowsPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kSelectRowsPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kSelectRowsPfS_S_iii,@object # @_Z11kSelectRowsPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z11kSelectRowsPfS_S_iii
.p2align 3, 0x0
_Z11kSelectRowsPfS_S_iii:
.quad _Z26__device_stub__kSelectRowsPfS_S_iii
.size _Z11kSelectRowsPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kSelectRowsPfS_S_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kSelectRowsPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kSelectRowsPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z11kSelectRowsPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, -0x20 ; /* 0xffffffe0ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x170 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R2, R5, c[0x0][0x178] ; /* 0x00005e0002007624 */
/* 0x001fca00078e0205 */
/*0070*/ IMNMX R4, R0.reuse, 0x20, PT ; /* 0x0000002000047817 */
/* 0x040fe40003800200 */
/*0080*/ ISETP.GE.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f26270 */
/*0090*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x002fda0003f06270 */
/*00a0*/ @P0 BRA 0x160 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R6, R2, 0x20, R3 ; /* 0x0000002002067824 */
/* 0x000fe400078e0203 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ F2I.TRUNC.NTZ R0, R6 ; /* 0x0000000600007305 */
/* 0x004e24000020f100 */
/*0100*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f06270 */
/*0110*/ @!P0 IADD3 R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000008a10 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f06270 */
/*0130*/ ISETP.GT.AND P0, PT, R0, -0x1, !P0 ; /* 0xffffffff0000780c */
/* 0x000fc80004704270 */
/*0140*/ SEL R0, R0, 0xffffffff, P0 ; /* 0xffffffff00007807 */
/* 0x000fca0000000000 */
/*0150*/ STS [R3.X4], R0 ; /* 0x0000000003007388 */
/* 0x0001e80000004800 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0190*/ LOP3.LUT R5, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff057212 */
/* 0x000fe200078e33ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01b0*/ IADD3 R6, R3, 0x20, RZ ; /* 0x0000002003067810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ IADD3 R5, R5, c[0x0][0x17c], RZ ; /* 0x00005f0005057a10 */
/* 0x000fc40007ffe0ff */
/*01d0*/ IADD3 R7, R3, 0x40, RZ ; /* 0x0000004003077810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ LEA.HI R9, R5, 0x1, RZ, 0x1b ; /* 0x0000000105097811 */
/* 0x000fe400078fd8ff */
/*01f0*/ IADD3 R8, R3, 0x60, RZ ; /* 0x0000006003087810 */
/* 0x000fe40007ffe0ff */
/*0200*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe400078ec0ff */
/*0210*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0220*/ BSSY B0, 0x940 ; /* 0x0000071000007945 */
/* 0x000fd80003800000 */
/*0230*/ @P0 BRA 0x930 ; /* 0x000006f000000947 */
/* 0x003fea0003800000 */
/*0240*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fe2000800063f */
/*0250*/ LEA R20, R2, UR4, 0x5 ; /* 0x0000000402147c11 */
/* 0x000fe2000f8e28ff */
/*0260*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD R16, R20, c[0x0][0x17c], R3 ; /* 0x00005f0014107a24 */
/* 0x000fc600078e0203 */
/*0280*/ LDS R0, [UR5] ; /* 0x00000005ff007984 */
/* 0x001e220008000800 */
/*0290*/ IMAD.WIDE R16, R16, R19, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fe200078e0213 */
/*02a0*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x001fda0003f05270 */
/*02b0*/ @!P0 BRA 0x600 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*02d0*/ BSSY B1, 0x400 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*02e0*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x000fd60000000f00 */
/*02f0*/ @!P0 BRA 0x3f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD R10, R0, c[0x0][0x17c], R3 ; /* 0x00005f00000a7a24 */
/* 0x000fc800078e0203 */
/*0310*/ IMAD.WIDE R10, R10, R19, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e0213 */
/*0320*/ LDG.E R13, [R10.64] ; /* 0x000000060a0d7981 */
/* 0x000ea2000c1e1900 */
/*0330*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f05270 */
/*0340*/ IMAD.MOV.U32 R15, RZ, RZ, R6 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0006 */
/*0350*/ STG.E [R16.64], R13 ; /* 0x0000000d10007986 */
/* 0x0041f4000c101906 */
/*0360*/ @!P0 BRA 0x3f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R13, [R10.64+0x80] ; /* 0x000080060a0d7981 */
/* 0x001ea2000c1e1900 */
/*0380*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe20003f05270 */
/*0390*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fc400078e0007 */
/*03a0*/ STG.E [R16.64+0x80], R13 ; /* 0x0000800d10007986 */
/* 0x0041f4000c101906 */
/*03b0*/ @!P0 BRA 0x3f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R11, [R10.64+0x100] ; /* 0x000100060a0b7981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IMAD.MOV.U32 R15, RZ, RZ, R8 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e0008 */
/*03e0*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0043e8000c101906 */
/*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.GE.U32.AND P0, PT, R5, 0x60, PT ; /* 0x000000600500780c */
/* 0x000fe20003f06070 */
/*0410*/ BSSY B1, 0x5f0 ; /* 0x000001d000017945 */
/* 0x000fd80003800000 */
/*0420*/ @!P0 BRA 0x5e0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0430*/ IMAD R10, R0, c[0x0][0x17c], R15.reuse ; /* 0x00005f00000a7a24 */
/* 0x100fe400078e020f */
/*0440*/ IMAD R27, R20, c[0x0][0x17c], R15 ; /* 0x00005f00141b7a24 */
/* 0x000fe400078e020f */
/*0450*/ IMAD.WIDE R10, R10, R19, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x002fc800078e0213 */
/*0460*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000a */
/*0470*/ MOV R17, R11 ; /* 0x0000000b00117202 */
/* 0x001fe20000000f00 */
/*0480*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.MOV.U32 R25, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff197624 */
/* 0x000fe400078e00ff */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*04b0*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e0011 */
/*04c0*/ LDG.E R17, [R10.64] ; /* 0x000000060a117981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ MOV R12, R0 ; /* 0x00000000000c7202 */
/* 0x002fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R13, RZ, RZ, R25 ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e0019 */
/*04f0*/ IMAD.WIDE R12, R27, 0x4, R12 ; /* 0x000000041b0c7825 */
/* 0x000fca00078e020c */
/*0500*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0041e8000c101906 */
/*0510*/ LDG.E R19, [R10.64+0x80] ; /* 0x000080060a137981 */
/* 0x000ea8000c1e1900 */
/*0520*/ STG.E [R12.64+0x80], R19 ; /* 0x000080130c007986 */
/* 0x0043e8000c101906 */
/*0530*/ LDG.E R21, [R10.64+0x100] ; /* 0x000100060a157981 */
/* 0x000ea8000c1e1900 */
/*0540*/ STG.E [R12.64+0x100], R21 ; /* 0x000100150c007986 */
/* 0x0043e8000c101906 */
/*0550*/ LDG.E R23, [R10.64+0x180] ; /* 0x000180060a177981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IADD3 R15, R15, 0x80, RZ ; /* 0x000000800f0f7810 */
/* 0x000fc40007ffe0ff */
/*0570*/ IADD3 R0, P1, R0, 0x200, RZ ; /* 0x0000020000007810 */
/* 0x000fe40007f3e0ff */
/*0580*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fe40003f06270 */
/*0590*/ IADD3 R14, P2, R10, 0x200, RZ ; /* 0x000002000a0e7810 */
/* 0x000fe20007f5e0ff */
/*05a0*/ IMAD.X R25, RZ, RZ, R25, P1 ; /* 0x000000ffff197224 */
/* 0x000fc800008e0619 */
/*05b0*/ IMAD.X R17, RZ, RZ, R11, P2 ; /* 0x000000ffff117224 */
/* 0x001fe200010e060b */
/*05c0*/ STG.E [R12.64+0x180], R23 ; /* 0x000180170c007986 */
/* 0x0043ea000c101906 */
/*05d0*/ @!P0 BRA 0x4a0 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*05e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x930 ; /* 0x0000033000007947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0610*/ BSSY B1, 0x7f0 ; /* 0x000001d000017945 */
/* 0x000fe20003800000 */
/*0620*/ IMAD.MOV.U32 R21, RZ, RZ, R3 ; /* 0x000000ffff157224 */
/* 0x000fd600078e0003 */
/*0630*/ @!P0 BRA 0x7e0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0640*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0650*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f05270 */
/*0660*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe200078e00ff */
/*0670*/ MOV R0, 0x690 ; /* 0x0000069000007802 */
/* 0x000fcc0000000f00 */
/*0680*/ CALL.REL.NOINC 0x980 ; /* 0x000002f000007944 */
/* 0x000fea0003c00000 */
/*0690*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe400078e000c */
/*06a0*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000d */
/*06b0*/ IMAD.MOV.U32 R21, RZ, RZ, R6 ; /* 0x000000ffff157224 */
/* 0x000fc800078e0006 */
/*06c0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e14000000080a */
/*06d0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*06e0*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0011e2000c101906 */
/*06f0*/ @!P0 BRA 0x7e0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0700*/ STG.E [R16.64+0x80], R11 ; /* 0x0000800b10007986 */
/* 0x0003e2000c101906 */
/*0710*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fe40003f05270 */
/*0720*/ MOV R21, R7 ; /* 0x0000000700157202 */
/* 0x000fd60000000f00 */
/*0730*/ @!P0 BRA 0x7e0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0740*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e00ff */
/*0750*/ MOV R0, 0x780 ; /* 0x0000078000007802 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe400078e00ff */
/*0770*/ CALL.REL.NOINC 0x980 ; /* 0x0000020000007944 */
/* 0x001fea0003c00000 */
/*0780*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e000c */
/*0790*/ MOV R21, R8 ; /* 0x0000000800157202 */
/* 0x000fe20000000f00 */
/*07a0*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e000d */
/*07b0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e14000000080a */
/*07c0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*07d0*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0011e4000c101906 */
/*07e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R5, 0x60, PT ; /* 0x000000600500780c */
/* 0x000fda0003f06070 */
/*0800*/ @!P0 BRA 0x930 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x001fe200078e00ff */
/*0820*/ MOV R0, 0x880 ; /* 0x0000088000007802 */
/* 0x000fe20000000f00 */
/*0830*/ IMAD R16, R20, c[0x0][0x17c], R21 ; /* 0x00005f0014107a24 */
/* 0x000fe400078e0215 */
/*0840*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0850*/ IMAD.MOV.U32 R19, RZ, RZ, -0x100000 ; /* 0xfff00000ff137424 */
/* 0x000fe400078e00ff */
/*0860*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fc800078e0211 */
/*0870*/ CALL.REL.NOINC 0x980 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0880*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e000c */
/*0890*/ MOV R11, R13 ; /* 0x0000000d000b7202 */
/* 0x000fe40000000f00 */
/*08a0*/ IADD3 R21, R21, 0x80, RZ ; /* 0x0000008015157810 */
/* 0x000fc80007ffe0ff */
/*08b0*/ DADD R10, R10, -R10 ; /* 0x000000000a0a7229 */
/* 0x000e22000000080a */
/*08c0*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x17c], PT ; /* 0x00005f0015007a0c */
/* 0x000fd20003f06270 */
/*08d0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*08e0*/ STG.E [R16.64], R11 ; /* 0x0000000b10007986 */
/* 0x0011e8000c101906 */
/*08f0*/ STG.E [R16.64+0x80], R11 ; /* 0x0000800b10007986 */
/* 0x0001e8000c101906 */
/*0900*/ STG.E [R16.64+0x100], R11 ; /* 0x0001000b10007986 */
/* 0x0001e8000c101906 */
/*0910*/ STG.E [R16.64+0x180], R11 ; /* 0x0001800b10007986 */
/* 0x0001e2000c101906 */
/*0920*/ @!P0 BRA 0x810 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0930*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0940*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0950*/ ISETP.LE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf03270 */
/*0960*/ @!P0 BRA 0x210 ; /* 0xfffff8a000008947 */
/* 0x000fea000383ffff */
/*0970*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0980*/ IMAD.MOV.U32 R11, RZ, RZ, R10 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e000a */
/*0990*/ DSETP.GTU.AND P1, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f2c200 */
/*09a0*/ @P1 BRA 0xbb0 ; /* 0x0000020000001947 */
/* 0x001fea0003800000 */
/*09b0*/ LOP3.LUT R14, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0a0e7812 */
/* 0x000fc800078ec0ff */
/*09c0*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ ISETP.GE.U32.AND P1, PT, R12, 0x7fefffff, PT ; /* 0x7fefffff0c00780c */
/* 0x000fda0003f26070 */
/*09e0*/ @P1 LOP3.LUT R13, R11, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff000000b0d1812 */
/* 0x000fe200078e3cff */
/*09f0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e00ff */
/*0a00*/ @P1 BRA 0xbd0 ; /* 0x000001c000001947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.U32.AND P1, PT, R14, 0x1000001, PT ; /* 0x010000010e00780c */
/* 0x000fda0003f26070 */
/*0a20*/ @!P1 BRA 0xb10 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0a30*/ IADD3 R13, R11, -0x3fe00000, RZ ; /* 0xc02000000b0d7810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*0a50*/ IMAD.MOV.U32 R14, RZ, RZ, R19 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0013 */
/*0a60*/ MUFU.RCP64H R15, R13 ; /* 0x0000000d000f7308 */
/* 0x000e2a0000001800 */
/*0a70*/ DFMA R18, -R12, R14, 1 ; /* 0x3ff000000c12742b */
/* 0x001e0c000000010e */
/*0a80*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0a90*/ DFMA R18, R14, R18, R14 ; /* 0x000000120e12722b */
/* 0x001e0c000000000e */
/*0aa0*/ DFMA R14, -R12, R18, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000112 */
/*0ab0*/ DFMA R14, R18, R14, R18 ; /* 0x0000000e120e722b */
/* 0x001e0c0000000012 */
/*0ac0*/ DMUL R14, R14, 2.2250738585072013831e-308 ; /* 0x001000000e0e7828 */
/* 0x001e0c0000000000 */
/*0ad0*/ DFMA R10, -R10, R14, 1 ; /* 0x3ff000000a0a742b */
/* 0x001e0c000000010e */
/*0ae0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0af0*/ DFMA R12, R14, R10, R14 ; /* 0x0000000a0e0c722b */
/* 0x001062000000000e */
/*0b00*/ BRA 0xbd0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0b10*/ DMUL R14, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0e7828 */
/* 0x0000640000000000 */
/*0b20*/ MOV R10, R19 ; /* 0x00000013000a7202 */
/* 0x001fc80000000f00 */
/*0b30*/ MUFU.RCP64H R11, R15 ; /* 0x0000000f000b7308 */
/* 0x002e240000001800 */
/*0b40*/ DFMA R12, -R14, R10, 1 ; /* 0x3ff000000e0c742b */
/* 0x001e0c000000010a */
/*0b50*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0b60*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0b70*/ DFMA R10, -R14, R12, 1 ; /* 0x3ff000000e0a742b */
/* 0x001e0c000000010c */
/*0b80*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*0b90*/ DMUL R12, R10, 8.11296384146066816958e+31 ; /* 0x469000000a0c7828 */
/* 0x0010620000000000 */
/*0ba0*/ BRA 0xbd0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0d7812 */
/* 0x000fe200078efcff */
/*0bc0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*0bd0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0000 */
/*0be0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*0bf0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff4000a007950 */
/* 0x000fea0003c3ffff */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kSelectRowsPfS_S_iii
.globl _Z11kSelectRowsPfS_S_iii
.p2align 8
.type _Z11kSelectRowsPfS_S_iii,@function
_Z11kSelectRowsPfS_S_iii:
s_load_b32 s2, s[0:1], 0x18
s_lshl_b32 s5, s15, 5
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s2, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_i32 s2, s3, 32
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x10
v_add_nc_u32_e32 v1, s5, v0
s_load_b32 s5, s[0:1], 0x20
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_and_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v2, v1
v_max_i32_e32 v2, -1, v1
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, -1, v2, vcc_lo
ds_store_b32 v3, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_i32 s3, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_12
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_max_i32 s8, s2, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s3, v0
s_mul_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s9, s15, 5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_10
s_lshl_b32 s1, s10, 2
s_mov_b32 s12, 0
v_mov_b32_e32 v1, s1
ds_load_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v2, s3
v_cmp_ne_u32_e64 s1, -1, v2
v_mov_b32_e32 v2, v0
s_branch .LBB0_8
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v1, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
.LBB0_7:
v_add_nc_u32_e32 v4, s9, v2
v_add_nc_u32_e32 v2, 32, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_cmp_le_i32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_or_b32 s12, vcc_lo, s12
v_add_co_u32 v4, s2, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s7, v5, s2
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v3, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_10
.LBB0_8:
s_delay_alu instid0(VALU_DEP_2)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccz .LBB0_6
v_mov_b32_e32 v3, 0x7fc00000
s_branch .LBB0_7
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_add_i32 s9, s9, s3
s_cmp_eq_u32 s10, s8
s_cbranch_scc0 .LBB0_4
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kSelectRowsPfS_S_iii
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kSelectRowsPfS_S_iii, .Lfunc_end0-_Z11kSelectRowsPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kSelectRowsPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kSelectRowsPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00072e3e_00000000-6_kSelectRows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii
.type _Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii, @function
_Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11kSelectRowsPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii, .-_Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii
.globl _Z11kSelectRowsPfS_S_iii
.type _Z11kSelectRowsPfS_S_iii, @function
_Z11kSelectRowsPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11kSelectRowsPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kSelectRowsPfS_S_iii, .-_Z11kSelectRowsPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kSelectRowsPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kSelectRowsPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kSelectRows.hip"
.globl _Z26__device_stub__kSelectRowsPfS_S_iii # -- Begin function _Z26__device_stub__kSelectRowsPfS_S_iii
.p2align 4, 0x90
.type _Z26__device_stub__kSelectRowsPfS_S_iii,@function
_Z26__device_stub__kSelectRowsPfS_S_iii: # @_Z26__device_stub__kSelectRowsPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11kSelectRowsPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__kSelectRowsPfS_S_iii, .Lfunc_end0-_Z26__device_stub__kSelectRowsPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kSelectRowsPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kSelectRowsPfS_S_iii,@object # @_Z11kSelectRowsPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z11kSelectRowsPfS_S_iii
.p2align 3, 0x0
_Z11kSelectRowsPfS_S_iii:
.quad _Z26__device_stub__kSelectRowsPfS_S_iii
.size _Z11kSelectRowsPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kSelectRowsPfS_S_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kSelectRowsPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kSelectRowsPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <stdlib.h>
#include <cstdio>
__host__ __device__ inline double dg4(const double v1, const double v2, const double v3, const double v4, const double v5, const double v6, const double v7)
{
return (1./576.)*(v1+v7) + (-54./576.)*(v2+v6) + (783./576.)*(v3+v5) + (-1460./576.)*v4;
}
/*
4th order diffusion (3D), quite similar to CPU implementation MicroHH
*/
void diff_cpu_3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells)
{
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj1 = 1*icells;
const int jj2 = 2*icells;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const double visc = 0.1;
for (int k=kstart; k<kend; ++k)
for (int j=jstart; j<jend; ++j)
#pragma ivdep
for (int i=istart; i<iend; ++i)
{
const int ijk = i + j*icells + k*ijcells;
at[ijk] += visc * dg4(a[ijk-ii3], a[ijk-ii2], a[ijk-ii1], a[ijk], a[ijk+ii1], a[ijk+ii2], a[ijk+ii3])*dxidxi
+ visc * dg4(a[ijk-jj3], a[ijk-jj2], a[ijk-jj1], a[ijk], a[ijk+jj1], a[ijk+jj2], a[ijk+jj3])*dyidyi
+ visc * dg4(a[ijk-kk3], a[ijk-kk2], a[ijk-kk1], a[ijk], a[ijk+kk1], a[ijk+kk2], a[ijk+kk3])*dzidzi;
}
}
/*
4th order diffusion (3D), no shared memory use, quite similar to GPU implementation MicroHH
*/
__global__ void diff_gpu_3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int k = blockIdx.z + kstart;
const double visc = 0.1;
if(i < iend && j < jend && k < kend)
{
const int ijk = i + j*icells + k*ijcells;
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj1 = 1*icells;
const int jj2 = 2*icells;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
at[ijk] += visc * dg4(a[ijk-ii3], a[ijk-ii2], a[ijk-ii1], a[ijk], a[ijk+ii1], a[ijk+ii2], a[ijk+ii3])*dxidxi
+ visc * dg4(a[ijk-jj3], a[ijk-jj2], a[ijk-jj1], a[ijk], a[ijk+jj1], a[ijk+jj2], a[ijk+jj3])*dyidyi
+ visc * dg4(a[ijk-kk3], a[ijk-kk2], a[ijk-kk1], a[ijk], a[ijk+kk1], a[ijk+kk2], a[ijk+kk3])*dzidzi;
}
}
/*
4th order diffusion, shared memory for horizontal (i,j) stencil, global memory for vertical (k) stencil
*/
__global__ void diff_gpu_3d_s2d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells, const int ngc)
{
extern __shared__ double as[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int k = blockIdx.z + kstart;
const int blockxpad = blockDim.x+2*ngc;
const double visc = 0.1;
if(i < iend && j < jend && k < kend)
{
const int ijk = i + j*icells + k*ijcells; // index in global memory
const int ijks = (tx+ngc) + (ty+ngc)*blockxpad; // Same location in 2d shared mem
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const int jjs1 = 1*blockxpad;
const int jjs2 = 2*blockxpad;
const int jjs3 = 3*blockxpad;
as[ijks] = a[ijk];
if(ty < ngc)
as[ijks-jjs3] = a[ijk-jj3];
if(ty >= blockDim.y-ngc)
as[ijks+jjs3] = a[ijk+jj3];
if(tx < ngc)
as[ijks-ii3] = a[ijk-ii3];
if(tx >= blockDim.x-ngc)
as[ijks+ii3] = a[ijk+ii3];
__syncthreads();
at[ijk] += visc * dg4(as[ijks-ii3 ], as[ijks-ii2 ], as[ijks-ii1 ], as[ijks], as[ijks+ii1 ], as[ijks+ii2 ], as[ijks+ii3 ])*dxidxi
+ visc * dg4(as[ijks-jjs3], as[ijks-jjs2], as[ijks-jjs1], as[ijks], as[ijks+jjs1], as[ijks+jjs2], as[ijks+jjs3])*dyidyi
+ visc * dg4(a [ijk-kk3 ], a [ijk-kk2 ], a [ijk-kk1 ], as[ijks], a [ijk+kk1 ], a [ijk+kk2 ], a [ijk+kk3 ])*dzidzi;
}
}
/*
4th order diffusion, shared memory for horizontal (i,j) stencil, vertical stencil in local variables, vertical loop on GPU
*/
__global__ void diff_gpu_3d_s3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells, const int ngc)
{
extern __shared__ double as[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int blockxpad = blockDim.x+2*ngc;
const double visc = 0.1;
if(i < iend && j < jend)
{
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const int kk4 = 4*ijcells;
const int jjs1 = 1*blockxpad;
const int jjs2 = 2*blockxpad;
const int jjs3 = 3*blockxpad;
int ijk = i +j*icells + kstart*ijcells;
double akm3, akm2, akm1, aijk, akp1, akp2, akp3;
// Read vertical stencil into variables
akm3 = a[ijk-kk3];
akm2 = a[ijk-kk2];
akm1 = a[ijk-kk1];
aijk = a[ijk ];
akp1 = a[ijk+kk1];
akp2 = a[ijk+kk2];
akp3 = a[ijk+kk3];
for (int k=kstart; k<kend; ++k)
{
const int ijk = i + j*icells + k*ijcells; // index in global memory
const int ijks = (tx+ngc) + (ty+ngc)*blockxpad; // Same location in 2d shared mem
__syncthreads();
as[ijks] = aijk;
if(ty < ngc)
as[ijks-jjs3] = a[ijk-jj3];
if(ty >= blockDim.y-ngc)
as[ijks+jjs3] = a[ijk+jj3];
if(tx < ngc)
as[ijks-ii3] = a[ijk-ii3];
if(tx >= blockDim.x-ngc)
as[ijks+ii3] = a[ijk+ii3];
__syncthreads();
at[ijk] += visc * dg4(as[ijks-ii3 ], as[ijks-ii2 ], as[ijks-ii1 ], as[ijks], as[ijks+ii1 ], as[ijks+ii2 ], as[ijks+ii3 ])*dxidxi
+ visc * dg4(as[ijks-jjs3], as[ijks-jjs2], as[ijks-jjs1], as[ijks], as[ijks+jjs1], as[ijks+jjs2], as[ijks+jjs3])*dyidyi
+ visc * dg4(akm3, akm2, akm1, aijk, akp1, akp2, akp3 )*dzidzi;
// Shift vertical stencil
akm3 = akm2;
akm2 = akm1;
akm1 = aijk;
aijk = akp1;
akp1 = akp2;
akp2 = akp3;
if(k < kend-1)
akp3 = a[ijk+kk4];
}
}
}
/*
Get max difference between two fields
*/
double maxdiff(const double * const __restrict__ a, const double * const __restrict__ b, const int n)
{
double maxdiff=0;
double diff=0;
for(int i=0; i<n; ++i)
{
diff = std::abs(a[i]-b[i]);
if(diff > maxdiff)
maxdiff = diff;
}
return maxdiff;
}
int main()
{
//
// Grid
//
const double dxi = 0.1;
const double dyi = 0.1;
const double dzi = 0.1;
const int itot = 256;
const int jtot = 256;
const int ktot = 256;
const int gc = 3;
const int iter = 50;
//
// Calculate the required variables.
//
const int ncells = (itot+2*gc)*(jtot+2*gc)*(ktot+2*gc);
const int istart = gc;
const int jstart = gc;
const int kstart = gc;
const int iend = itot+gc;
const int jend = jtot+gc;
const int kend = ktot+gc;
const int icells = itot+2*gc;
const int ijcells = (itot+2*gc)*(jtot+2*gc);
//
// Prepare fields on HOST
//
double *a = new double[ncells];
double *at = new double[ncells];
double *tmp1 = new double[ncells];
for (int n=0; n<ncells; ++n)
{
a [n] = 0.001 * (std::rand() % 1000) - 0.5;
at[n] = 0.;
tmp1[n] = 0.;
}
//
// Prepare fields on DEVICE
//
double *ad, *atd;
cudaMalloc((void **)&ad, ncells*sizeof(double));
cudaMalloc((void **)&atd, ncells*sizeof(double));
cudaMemcpy(ad, a, ncells*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(atd, at, ncells*sizeof(double), cudaMemcpyHostToDevice);
//
// CUDA thread blocks
//
const int blocki = 32;
const int blockj = 8;
const int gridi = itot/blocki + (itot%blocki > 0);
const int gridj = jtot/blockj + (jtot%blockj > 0);
dim3 gridGPU (gridi, gridj, ktot);
dim3 gridGPU2d(gridi, gridj, 1);
dim3 blockGPU(blocki, blockj, 1);
//
// Timer stuff
//
cudaEvent_t startEvent, stopEvent;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
float dt1, dt2;
//
// Execute kernels
//
//////////////////// CPU //////////////////////////
cudaEventRecord(startEvent, 0);
for(int n=0; n<iter; ++n)
{
diff_cpu_3d(at, a, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells);
}
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&dt1, startEvent, stopEvent);
printf("CPU; elapsed=%f [ms]\n",dt1);
//////////////////// GPU //////////////////////////
cudaDeviceSetSharedMemConfig(cudaSharedMemBankSizeEightByte);
cudaEventRecord(startEvent, 0);
for(int n=0; n<iter; ++n)
{
diff_gpu_3d<<<gridGPU, blockGPU>>>
(atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells);
//diff_gpu_3d_s2d<<<gridGPU, blockGPU, (blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>>
// (atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells, gc);
//diff_gpu_3d_s3d<<<gridGPU2d, blockGPU, (blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>>
// (atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells, gc);
}
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&dt2, startEvent, stopEvent);
//
// Copy device field to tmp1
//
cudaMemcpy(tmp1, atd, ncells*sizeof(double), cudaMemcpyDeviceToHost);
printf("GPU; elapsed=%f [ms], speedup=%f, maxdiff=%e \n",dt2,dt1/dt2,maxdiff(at,tmp1,ncells));
return 0;
}
|
.file "tmpxft_000e6334_00000000-6_diff4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11diff_cpu_3dPdPKddddiiiiiiii
.type _Z11diff_cpu_3dPdPKddddiiiiiiii, @function
_Z11diff_cpu_3dPdPKddddiiiiiiii:
.LFB3950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -32(%rsp)
movq %rsi, -80(%rsp)
movl %edx, -60(%rsp)
movl %ecx, -24(%rsp)
movl %r8d, -16(%rsp)
movl %r9d, -64(%rsp)
movl 56(%rsp), %ecx
movl 80(%rsp), %r12d
cmpl 64(%rsp), %ecx
jge .L3
movapd %xmm0, %xmm7
movapd %xmm1, %xmm8
movapd %xmm2, %xmm9
movl %ecx, %ebx
imull %r12d, %ebx
movl %ebx, -92(%rsp)
imull 72(%rsp), %r8d
movl %r8d, -12(%rsp)
movslq 72(%rsp), %rdi
leaq (%rdi,%rdi,2), %r10
salq $3, %r10
movq %rdi, %rbp
salq $4, %rbp
movq %rdi, %rsi
negq %rsi
leaq 0(,%rsi,8), %rbx
movq %rbx, -88(%rsp)
movq %rsi, %r14
salq $4, %r14
leaq 0(,%rdi,4), %rdx
movq %rdi, %rsi
subq %rdx, %rsi
leaq 0(,%rsi,8), %rdx
movslq %r12d, %rsi
leaq (%rsi,%rsi,2), %r9
salq $3, %r9
movq %rsi, %rbx
salq $4, %rbx
movq %rsi, %r8
negq %r8
salq $3, %r8
movq %rsi, %r15
negq %r15
salq $4, %r15
leaq 0(,%rsi,4), %r11
movq %rsi, %r13
subq %r11, %r13
leaq 0(,%r13,8), %r11
movl -60(%rsp), %eax
movslq %eax, %r13
movq %r13, -40(%rsp)
movl -24(%rsp), %r13d
subl %eax, %r13d
movq %r13, %rax
movq -40(%rsp), %r13
addq %r13, %rax
movsd .LC0(%rip), %xmm10
movsd .LC1(%rip), %xmm6
movsd .LC2(%rip), %xmm5
movq -88(%rsp), %r13
movq %rdx, -72(%rsp)
movq %rax, -8(%rsp)
movl -92(%rsp), %eax
jmp .L5
.L8:
movslq -88(%rsp), %r12
movq -40(%rsp), %rax
movq -56(%rsp), %rcx
addq %rax, %rcx
addq %r12, %rcx
salq $3, %rcx
movq -80(%rsp), %rax
addq %rcx, %rax
movq %rax, -72(%rsp)
movq -32(%rsp), %rax
addq %rax, %rcx
movq -48(%rsp), %rax
addq %rax, %r12
movq -80(%rsp), %rax
leaq (%rax,%r12,8), %r12
movsd .LC4(%rip), %xmm3
movq -72(%rsp), %rax
.L6:
movapd %xmm10, %xmm11
mulsd (%rax), %xmm11
movsd 24(%rax), %xmm0
addsd -24(%rax), %xmm0
mulsd %xmm6, %xmm0
movsd 16(%rax), %xmm1
addsd -16(%rax), %xmm1
mulsd %xmm5, %xmm1
addsd %xmm1, %xmm0
movsd 8(%rax), %xmm1
addsd -8(%rax), %xmm1
mulsd %xmm4, %xmm1
addsd %xmm1, %xmm0
addsd %xmm11, %xmm0
mulsd %xmm3, %xmm0
mulsd %xmm7, %xmm0
movsd (%rax,%r10), %xmm1
addsd (%rax,%rdx), %xmm1
mulsd %xmm6, %xmm1
movsd (%rax,%rbp), %xmm2
addsd (%rax,%r14), %xmm2
mulsd %xmm5, %xmm2
addsd %xmm2, %xmm1
movsd (%rax,%rdi,8), %xmm2
addsd (%rax,%r13), %xmm2
mulsd %xmm4, %xmm2
addsd %xmm2, %xmm1
addsd %xmm11, %xmm1
mulsd %xmm3, %xmm1
mulsd %xmm8, %xmm1
addsd %xmm1, %xmm0
movsd (%rax,%r9), %xmm2
addsd (%rax,%r11), %xmm2
mulsd %xmm6, %xmm2
movsd (%rax,%rbx), %xmm1
addsd (%rax,%r15), %xmm1
mulsd %xmm5, %xmm1
addsd %xmm1, %xmm2
movsd (%rax,%rsi,8), %xmm1
addsd (%rax,%r8), %xmm1
mulsd %xmm4, %xmm1
addsd %xmm2, %xmm1
addsd %xmm11, %xmm1
mulsd %xmm3, %xmm1
mulsd %xmm9, %xmm1
addsd %xmm1, %xmm0
addsd (%rcx), %xmm0
movsd %xmm0, (%rcx)
addq $8, %rax
addq $8, %rcx
cmpq %r12, %rax
jne .L6
.L9:
addl $1, -92(%rsp)
movl -92(%rsp), %eax
movl 72(%rsp), %r12d
addl %r12d, -88(%rsp)
cmpl %eax, -64(%rsp)
je .L12
.L10:
movl -24(%rsp), %ecx
cmpl %ecx, -60(%rsp)
jl .L8
jmp .L9
.L12:
movl -20(%rsp), %eax
movl 56(%rsp), %ecx
movq %rdx, -72(%rsp)
.L7:
addl $1, %ecx
addl 80(%rsp), %eax
cmpl %ecx, 64(%rsp)
je .L3
.L5:
movl -16(%rsp), %r12d
movl -64(%rsp), %edx
cmpl %edx, %r12d
jge .L7
movl -12(%rsp), %edx
movl %edx, -88(%rsp)
movl %r12d, -92(%rsp)
movslq %eax, %r12
movq %r12, -56(%rsp)
movq -8(%rsp), %rdx
addq %r12, %rdx
movq %rdx, -48(%rsp)
movsd .LC3(%rip), %xmm4
movl %eax, -20(%rsp)
movl %ecx, 56(%rsp)
movq -72(%rsp), %rdx
jmp .L10
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _Z11diff_cpu_3dPdPKddddiiiiiiii, .-_Z11diff_cpu_3dPdPKddddiiiiiiii
.globl _Z7maxdiffPKdS0_i
.type _Z7maxdiffPKdS0_i, @function
_Z7maxdiffPKdS0_i:
.LFB3951:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L18
movslq %edx, %rdx
salq $3, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
movq .LC6(%rip), %xmm2
.L17:
movsd (%rdi,%rax), %xmm0
subsd (%rsi,%rax), %xmm0
andpd %xmm2, %xmm0
maxsd %xmm1, %xmm0
movapd %xmm0, %xmm1
addq $8, %rax
cmpq %rax, %rdx
jne .L17
.L14:
movapd %xmm1, %xmm0
ret
.L18:
pxor %xmm1, %xmm1
jmp .L14
.cfi_endproc
.LFE3951:
.size _Z7maxdiffPKdS0_i, .-_Z7maxdiffPKdS0_i
.globl _Z45__device_stub__Z11diff_gpu_3dPdPKddddiiiiiiiiPdPKddddiiiiiiii
.type _Z45__device_stub__Z11diff_gpu_3dPdPKddddiiiiiiiiPdPKddddiiiiiiii, @function
_Z45__device_stub__Z11diff_gpu_3dPdPKddddiiiiiiiiPdPKddddiiiiiiii:
.LFB3977:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movsd %xmm0, 40(%rsp)
movsd %xmm1, 32(%rsp)
movsd %xmm2, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
movq %rdi, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
leaq 280(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11diff_gpu_3dPdPKddddiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z45__device_stub__Z11diff_gpu_3dPdPKddddiiiiiiiiPdPKddddiiiiiiii, .-_Z45__device_stub__Z11diff_gpu_3dPdPKddddiiiiiiiiPdPKddddiiiiiiii
.globl _Z11diff_gpu_3dPdPKddddiiiiiiii
.type _Z11diff_gpu_3dPdPKddddiiiiiiii, @function
_Z11diff_gpu_3dPdPKddddiiiiiiii:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z45__device_stub__Z11diff_gpu_3dPdPKddddiiiiiiiiPdPKddddiiiiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z11diff_gpu_3dPdPKddddiiiiiiii, .-_Z11diff_gpu_3dPdPKddddiiiiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "CPU; elapsed=%f [ms]\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "GPU; elapsed=%f [ms], speedup=%f, maxdiff=%e \n"
.text
.globl main
.type main, @function
main:
.LFB3952:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $143877824, %edi
call _Znam@PLT
movq %rax, %r12
movl $143877824, %edi
call _Znam@PLT
movq %rax, %rbp
movl $143877824, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %ebx
.L30:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC7(%rip), %xmm0
subsd .LC8(%rip), %xmm0
movsd %xmm0, (%r12,%rbx)
movq $0x000000000, 0(%rbp,%rbx)
movq $0x000000000, 0(%r13,%rbx)
addq $8, %rbx
cmpq $143877824, %rbx
jne .L30
leaq 16(%rsp), %rdi
movl $143877824, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $143877824, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $143877824, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $143877824, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 48(%rsp)
movl $32, 52(%rsp)
movl $256, 56(%rsp)
movl $32, 60(%rsp)
movl $8, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $50, %ebx
.L31:
pushq $68644
.cfi_def_cfa_offset 136
pushq $262
.cfi_def_cfa_offset 144
pushq $259
.cfi_def_cfa_offset 152
pushq $3
.cfi_def_cfa_offset 160
movl $259, %r9d
movl $3, %r8d
movl $259, %ecx
movl $3, %edx
movsd .LC4(%rip), %xmm2
movapd %xmm2, %xmm1
movapd %xmm2, %xmm0
movq %r12, %rsi
movq %rbp, %rdi
call _Z11diff_cpu_3dPdPKddddiiiiiiii
addq $32, %rsp
.cfi_def_cfa_offset 128
subl $1, %ebx
jne .L31
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %edi
call cudaDeviceSetSharedMemConfig@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $50, %ebx
jmp .L33
.L32:
subl $1, %ebx
je .L39
.L33:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
pushq $68644
.cfi_def_cfa_offset 136
pushq $262
.cfi_def_cfa_offset 144
pushq $259
.cfi_def_cfa_offset 152
pushq $3
.cfi_def_cfa_offset 160
movl $259, %r9d
movl $3, %r8d
movl $259, %ecx
movl $3, %edx
movsd .LC4(%rip), %xmm2
movapd %xmm2, %xmm1
movapd %xmm2, %xmm0
movq 48(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z45__device_stub__Z11diff_gpu_3dPdPKddddiiiiiiiiPdPKddddiiiiiiii
addq $32, %rsp
.cfi_def_cfa_offset 128
jmp .L32
.L39:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $143877824, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $17984728, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z7maxdiffPKdS0_i
movapd %xmm0, %xmm2
movss 12(%rsp), %xmm3
movss 8(%rsp), %xmm1
divss %xmm3, %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3952:
.size main, .-main
.globl _Z50__device_stub__Z15diff_gpu_3d_s2dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii
.type _Z50__device_stub__Z15diff_gpu_3d_s2dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii, @function
_Z50__device_stub__Z15diff_gpu_3d_s2dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii:
.LFB3979:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movsd %xmm0, 40(%rsp)
movsd %xmm1, 32(%rsp)
movsd %xmm2, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movq %rdi, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
leaq 304(%rsp), %rax
movq %rax, 232(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3979:
.size _Z50__device_stub__Z15diff_gpu_3d_s2dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii, .-_Z50__device_stub__Z15diff_gpu_3d_s2dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii
.globl _Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii
.type _Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii, @function
_Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii:
.LFB3980:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z50__device_stub__Z15diff_gpu_3d_s2dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii, .-_Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii
.globl _Z50__device_stub__Z15diff_gpu_3d_s3dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii
.type _Z50__device_stub__Z15diff_gpu_3d_s3dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii, @function
_Z50__device_stub__Z15diff_gpu_3d_s3dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii:
.LFB3981:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movsd %xmm0, 40(%rsp)
movsd %xmm1, 32(%rsp)
movsd %xmm2, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movq %rdi, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
leaq 304(%rsp), %rax
movq %rax, 232(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3981:
.size _Z50__device_stub__Z15diff_gpu_3d_s3dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii, .-_Z50__device_stub__Z15diff_gpu_3d_s3dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii
.globl _Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii
.type _Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii, @function
_Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii:
.LFB3982:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z50__device_stub__Z15diff_gpu_3d_s3dPdPKddddiiiiiiiiiPdPKddddiiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii, .-_Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii"
.align 8
.LC12:
.string "_Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii"
.align 8
.LC13:
.string "_Z11diff_gpu_3dPdPKddddiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3984:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11diff_gpu_3dPdPKddddiiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3984:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1908874354
.long -1073461476
.align 8
.LC1:
.long 477218588
.long 1063023047
.align 8
.LC2:
.long 0
.long -1078460416
.align 8
.LC3:
.long 0
.long 1073070080
.align 8
.LC4:
.long -1717986918
.long 1069128089
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC7:
.long -755914244
.long 1062232653
.align 8
.LC8:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <stdlib.h>
#include <cstdio>
__host__ __device__ inline double dg4(const double v1, const double v2, const double v3, const double v4, const double v5, const double v6, const double v7)
{
return (1./576.)*(v1+v7) + (-54./576.)*(v2+v6) + (783./576.)*(v3+v5) + (-1460./576.)*v4;
}
/*
4th order diffusion (3D), quite similar to CPU implementation MicroHH
*/
void diff_cpu_3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells)
{
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj1 = 1*icells;
const int jj2 = 2*icells;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const double visc = 0.1;
for (int k=kstart; k<kend; ++k)
for (int j=jstart; j<jend; ++j)
#pragma ivdep
for (int i=istart; i<iend; ++i)
{
const int ijk = i + j*icells + k*ijcells;
at[ijk] += visc * dg4(a[ijk-ii3], a[ijk-ii2], a[ijk-ii1], a[ijk], a[ijk+ii1], a[ijk+ii2], a[ijk+ii3])*dxidxi
+ visc * dg4(a[ijk-jj3], a[ijk-jj2], a[ijk-jj1], a[ijk], a[ijk+jj1], a[ijk+jj2], a[ijk+jj3])*dyidyi
+ visc * dg4(a[ijk-kk3], a[ijk-kk2], a[ijk-kk1], a[ijk], a[ijk+kk1], a[ijk+kk2], a[ijk+kk3])*dzidzi;
}
}
/*
4th order diffusion (3D), no shared memory use, quite similar to GPU implementation MicroHH
*/
__global__ void diff_gpu_3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int k = blockIdx.z + kstart;
const double visc = 0.1;
if(i < iend && j < jend && k < kend)
{
const int ijk = i + j*icells + k*ijcells;
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj1 = 1*icells;
const int jj2 = 2*icells;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
at[ijk] += visc * dg4(a[ijk-ii3], a[ijk-ii2], a[ijk-ii1], a[ijk], a[ijk+ii1], a[ijk+ii2], a[ijk+ii3])*dxidxi
+ visc * dg4(a[ijk-jj3], a[ijk-jj2], a[ijk-jj1], a[ijk], a[ijk+jj1], a[ijk+jj2], a[ijk+jj3])*dyidyi
+ visc * dg4(a[ijk-kk3], a[ijk-kk2], a[ijk-kk1], a[ijk], a[ijk+kk1], a[ijk+kk2], a[ijk+kk3])*dzidzi;
}
}
/*
4th order diffusion, shared memory for horizontal (i,j) stencil, global memory for vertical (k) stencil
*/
__global__ void diff_gpu_3d_s2d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells, const int ngc)
{
extern __shared__ double as[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int k = blockIdx.z + kstart;
const int blockxpad = blockDim.x+2*ngc;
const double visc = 0.1;
if(i < iend && j < jend && k < kend)
{
const int ijk = i + j*icells + k*ijcells; // index in global memory
const int ijks = (tx+ngc) + (ty+ngc)*blockxpad; // Same location in 2d shared mem
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const int jjs1 = 1*blockxpad;
const int jjs2 = 2*blockxpad;
const int jjs3 = 3*blockxpad;
as[ijks] = a[ijk];
if(ty < ngc)
as[ijks-jjs3] = a[ijk-jj3];
if(ty >= blockDim.y-ngc)
as[ijks+jjs3] = a[ijk+jj3];
if(tx < ngc)
as[ijks-ii3] = a[ijk-ii3];
if(tx >= blockDim.x-ngc)
as[ijks+ii3] = a[ijk+ii3];
__syncthreads();
at[ijk] += visc * dg4(as[ijks-ii3 ], as[ijks-ii2 ], as[ijks-ii1 ], as[ijks], as[ijks+ii1 ], as[ijks+ii2 ], as[ijks+ii3 ])*dxidxi
+ visc * dg4(as[ijks-jjs3], as[ijks-jjs2], as[ijks-jjs1], as[ijks], as[ijks+jjs1], as[ijks+jjs2], as[ijks+jjs3])*dyidyi
+ visc * dg4(a [ijk-kk3 ], a [ijk-kk2 ], a [ijk-kk1 ], as[ijks], a [ijk+kk1 ], a [ijk+kk2 ], a [ijk+kk3 ])*dzidzi;
}
}
/*
4th order diffusion, shared memory for horizontal (i,j) stencil, vertical stencil in local variables, vertical loop on GPU
*/
__global__ void diff_gpu_3d_s3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells, const int ngc)
{
extern __shared__ double as[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int blockxpad = blockDim.x+2*ngc;
const double visc = 0.1;
if(i < iend && j < jend)
{
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const int kk4 = 4*ijcells;
const int jjs1 = 1*blockxpad;
const int jjs2 = 2*blockxpad;
const int jjs3 = 3*blockxpad;
int ijk = i +j*icells + kstart*ijcells;
double akm3, akm2, akm1, aijk, akp1, akp2, akp3;
// Read vertical stencil into variables
akm3 = a[ijk-kk3];
akm2 = a[ijk-kk2];
akm1 = a[ijk-kk1];
aijk = a[ijk ];
akp1 = a[ijk+kk1];
akp2 = a[ijk+kk2];
akp3 = a[ijk+kk3];
for (int k=kstart; k<kend; ++k)
{
const int ijk = i + j*icells + k*ijcells; // index in global memory
const int ijks = (tx+ngc) + (ty+ngc)*blockxpad; // Same location in 2d shared mem
__syncthreads();
as[ijks] = aijk;
if(ty < ngc)
as[ijks-jjs3] = a[ijk-jj3];
if(ty >= blockDim.y-ngc)
as[ijks+jjs3] = a[ijk+jj3];
if(tx < ngc)
as[ijks-ii3] = a[ijk-ii3];
if(tx >= blockDim.x-ngc)
as[ijks+ii3] = a[ijk+ii3];
__syncthreads();
at[ijk] += visc * dg4(as[ijks-ii3 ], as[ijks-ii2 ], as[ijks-ii1 ], as[ijks], as[ijks+ii1 ], as[ijks+ii2 ], as[ijks+ii3 ])*dxidxi
+ visc * dg4(as[ijks-jjs3], as[ijks-jjs2], as[ijks-jjs1], as[ijks], as[ijks+jjs1], as[ijks+jjs2], as[ijks+jjs3])*dyidyi
+ visc * dg4(akm3, akm2, akm1, aijk, akp1, akp2, akp3 )*dzidzi;
// Shift vertical stencil
akm3 = akm2;
akm2 = akm1;
akm1 = aijk;
aijk = akp1;
akp1 = akp2;
akp2 = akp3;
if(k < kend-1)
akp3 = a[ijk+kk4];
}
}
}
/*
Get max difference between two fields
*/
double maxdiff(const double * const __restrict__ a, const double * const __restrict__ b, const int n)
{
double maxdiff=0;
double diff=0;
for(int i=0; i<n; ++i)
{
diff = std::abs(a[i]-b[i]);
if(diff > maxdiff)
maxdiff = diff;
}
return maxdiff;
}
int main()
{
//
// Grid
//
const double dxi = 0.1;
const double dyi = 0.1;
const double dzi = 0.1;
const int itot = 256;
const int jtot = 256;
const int ktot = 256;
const int gc = 3;
const int iter = 50;
//
// Calculate the required variables.
//
const int ncells = (itot+2*gc)*(jtot+2*gc)*(ktot+2*gc);
const int istart = gc;
const int jstart = gc;
const int kstart = gc;
const int iend = itot+gc;
const int jend = jtot+gc;
const int kend = ktot+gc;
const int icells = itot+2*gc;
const int ijcells = (itot+2*gc)*(jtot+2*gc);
//
// Prepare fields on HOST
//
double *a = new double[ncells];
double *at = new double[ncells];
double *tmp1 = new double[ncells];
for (int n=0; n<ncells; ++n)
{
a [n] = 0.001 * (std::rand() % 1000) - 0.5;
at[n] = 0.;
tmp1[n] = 0.;
}
//
// Prepare fields on DEVICE
//
double *ad, *atd;
cudaMalloc((void **)&ad, ncells*sizeof(double));
cudaMalloc((void **)&atd, ncells*sizeof(double));
cudaMemcpy(ad, a, ncells*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(atd, at, ncells*sizeof(double), cudaMemcpyHostToDevice);
//
// CUDA thread blocks
//
const int blocki = 32;
const int blockj = 8;
const int gridi = itot/blocki + (itot%blocki > 0);
const int gridj = jtot/blockj + (jtot%blockj > 0);
dim3 gridGPU (gridi, gridj, ktot);
dim3 gridGPU2d(gridi, gridj, 1);
dim3 blockGPU(blocki, blockj, 1);
//
// Timer stuff
//
cudaEvent_t startEvent, stopEvent;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
float dt1, dt2;
//
// Execute kernels
//
//////////////////// CPU //////////////////////////
cudaEventRecord(startEvent, 0);
for(int n=0; n<iter; ++n)
{
diff_cpu_3d(at, a, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells);
}
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&dt1, startEvent, stopEvent);
printf("CPU; elapsed=%f [ms]\n",dt1);
//////////////////// GPU //////////////////////////
cudaDeviceSetSharedMemConfig(cudaSharedMemBankSizeEightByte);
cudaEventRecord(startEvent, 0);
for(int n=0; n<iter; ++n)
{
diff_gpu_3d<<<gridGPU, blockGPU>>>
(atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells);
//diff_gpu_3d_s2d<<<gridGPU, blockGPU, (blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>>
// (atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells, gc);
//diff_gpu_3d_s3d<<<gridGPU2d, blockGPU, (blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>>
// (atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells, gc);
}
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&dt2, startEvent, stopEvent);
//
// Copy device field to tmp1
//
cudaMemcpy(tmp1, atd, ncells*sizeof(double), cudaMemcpyDeviceToHost);
printf("GPU; elapsed=%f [ms], speedup=%f, maxdiff=%e \n",dt2,dt1/dt2,maxdiff(at,tmp1,ncells));
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <stdlib.h>
#include <cstdio>
__host__ __device__ inline double dg4(const double v1, const double v2, const double v3, const double v4, const double v5, const double v6, const double v7)
{
return (1./576.)*(v1+v7) + (-54./576.)*(v2+v6) + (783./576.)*(v3+v5) + (-1460./576.)*v4;
}
/*
4th order diffusion (3D), quite similar to CPU implementation MicroHH
*/
void diff_cpu_3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells)
{
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj1 = 1*icells;
const int jj2 = 2*icells;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const double visc = 0.1;
for (int k=kstart; k<kend; ++k)
for (int j=jstart; j<jend; ++j)
#pragma ivdep
for (int i=istart; i<iend; ++i)
{
const int ijk = i + j*icells + k*ijcells;
at[ijk] += visc * dg4(a[ijk-ii3], a[ijk-ii2], a[ijk-ii1], a[ijk], a[ijk+ii1], a[ijk+ii2], a[ijk+ii3])*dxidxi
+ visc * dg4(a[ijk-jj3], a[ijk-jj2], a[ijk-jj1], a[ijk], a[ijk+jj1], a[ijk+jj2], a[ijk+jj3])*dyidyi
+ visc * dg4(a[ijk-kk3], a[ijk-kk2], a[ijk-kk1], a[ijk], a[ijk+kk1], a[ijk+kk2], a[ijk+kk3])*dzidzi;
}
}
/*
4th order diffusion (3D), no shared memory use, quite similar to GPU implementation MicroHH
*/
__global__ void diff_gpu_3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int k = blockIdx.z + kstart;
const double visc = 0.1;
if(i < iend && j < jend && k < kend)
{
const int ijk = i + j*icells + k*ijcells;
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj1 = 1*icells;
const int jj2 = 2*icells;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
at[ijk] += visc * dg4(a[ijk-ii3], a[ijk-ii2], a[ijk-ii1], a[ijk], a[ijk+ii1], a[ijk+ii2], a[ijk+ii3])*dxidxi
+ visc * dg4(a[ijk-jj3], a[ijk-jj2], a[ijk-jj1], a[ijk], a[ijk+jj1], a[ijk+jj2], a[ijk+jj3])*dyidyi
+ visc * dg4(a[ijk-kk3], a[ijk-kk2], a[ijk-kk1], a[ijk], a[ijk+kk1], a[ijk+kk2], a[ijk+kk3])*dzidzi;
}
}
/*
4th order diffusion, shared memory for horizontal (i,j) stencil, global memory for vertical (k) stencil
*/
__global__ void diff_gpu_3d_s2d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells, const int ngc)
{
extern __shared__ double as[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int k = blockIdx.z + kstart;
const int blockxpad = blockDim.x+2*ngc;
const double visc = 0.1;
if(i < iend && j < jend && k < kend)
{
const int ijk = i + j*icells + k*ijcells; // index in global memory
const int ijks = (tx+ngc) + (ty+ngc)*blockxpad; // Same location in 2d shared mem
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const int jjs1 = 1*blockxpad;
const int jjs2 = 2*blockxpad;
const int jjs3 = 3*blockxpad;
as[ijks] = a[ijk];
if(ty < ngc)
as[ijks-jjs3] = a[ijk-jj3];
if(ty >= blockDim.y-ngc)
as[ijks+jjs3] = a[ijk+jj3];
if(tx < ngc)
as[ijks-ii3] = a[ijk-ii3];
if(tx >= blockDim.x-ngc)
as[ijks+ii3] = a[ijk+ii3];
__syncthreads();
at[ijk] += visc * dg4(as[ijks-ii3 ], as[ijks-ii2 ], as[ijks-ii1 ], as[ijks], as[ijks+ii1 ], as[ijks+ii2 ], as[ijks+ii3 ])*dxidxi
+ visc * dg4(as[ijks-jjs3], as[ijks-jjs2], as[ijks-jjs1], as[ijks], as[ijks+jjs1], as[ijks+jjs2], as[ijks+jjs3])*dyidyi
+ visc * dg4(a [ijk-kk3 ], a [ijk-kk2 ], a [ijk-kk1 ], as[ijks], a [ijk+kk1 ], a [ijk+kk2 ], a [ijk+kk3 ])*dzidzi;
}
}
/*
4th order diffusion, shared memory for horizontal (i,j) stencil, vertical stencil in local variables, vertical loop on GPU
*/
__global__ void diff_gpu_3d_s3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells, const int ngc)
{
extern __shared__ double as[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int blockxpad = blockDim.x+2*ngc;
const double visc = 0.1;
if(i < iend && j < jend)
{
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const int kk4 = 4*ijcells;
const int jjs1 = 1*blockxpad;
const int jjs2 = 2*blockxpad;
const int jjs3 = 3*blockxpad;
int ijk = i +j*icells + kstart*ijcells;
double akm3, akm2, akm1, aijk, akp1, akp2, akp3;
// Read vertical stencil into variables
akm3 = a[ijk-kk3];
akm2 = a[ijk-kk2];
akm1 = a[ijk-kk1];
aijk = a[ijk ];
akp1 = a[ijk+kk1];
akp2 = a[ijk+kk2];
akp3 = a[ijk+kk3];
for (int k=kstart; k<kend; ++k)
{
const int ijk = i + j*icells + k*ijcells; // index in global memory
const int ijks = (tx+ngc) + (ty+ngc)*blockxpad; // Same location in 2d shared mem
__syncthreads();
as[ijks] = aijk;
if(ty < ngc)
as[ijks-jjs3] = a[ijk-jj3];
if(ty >= blockDim.y-ngc)
as[ijks+jjs3] = a[ijk+jj3];
if(tx < ngc)
as[ijks-ii3] = a[ijk-ii3];
if(tx >= blockDim.x-ngc)
as[ijks+ii3] = a[ijk+ii3];
__syncthreads();
at[ijk] += visc * dg4(as[ijks-ii3 ], as[ijks-ii2 ], as[ijks-ii1 ], as[ijks], as[ijks+ii1 ], as[ijks+ii2 ], as[ijks+ii3 ])*dxidxi
+ visc * dg4(as[ijks-jjs3], as[ijks-jjs2], as[ijks-jjs1], as[ijks], as[ijks+jjs1], as[ijks+jjs2], as[ijks+jjs3])*dyidyi
+ visc * dg4(akm3, akm2, akm1, aijk, akp1, akp2, akp3 )*dzidzi;
// Shift vertical stencil
akm3 = akm2;
akm2 = akm1;
akm1 = aijk;
aijk = akp1;
akp1 = akp2;
akp2 = akp3;
if(k < kend-1)
akp3 = a[ijk+kk4];
}
}
}
/*
Get max difference between two fields
*/
double maxdiff(const double * const __restrict__ a, const double * const __restrict__ b, const int n)
{
double maxdiff=0;
double diff=0;
for(int i=0; i<n; ++i)
{
diff = std::abs(a[i]-b[i]);
if(diff > maxdiff)
maxdiff = diff;
}
return maxdiff;
}
int main()
{
//
// Grid
//
const double dxi = 0.1;
const double dyi = 0.1;
const double dzi = 0.1;
const int itot = 256;
const int jtot = 256;
const int ktot = 256;
const int gc = 3;
const int iter = 50;
//
// Calculate the required variables.
//
const int ncells = (itot+2*gc)*(jtot+2*gc)*(ktot+2*gc);
const int istart = gc;
const int jstart = gc;
const int kstart = gc;
const int iend = itot+gc;
const int jend = jtot+gc;
const int kend = ktot+gc;
const int icells = itot+2*gc;
const int ijcells = (itot+2*gc)*(jtot+2*gc);
//
// Prepare fields on HOST
//
double *a = new double[ncells];
double *at = new double[ncells];
double *tmp1 = new double[ncells];
for (int n=0; n<ncells; ++n)
{
a [n] = 0.001 * (std::rand() % 1000) - 0.5;
at[n] = 0.;
tmp1[n] = 0.;
}
//
// Prepare fields on DEVICE
//
double *ad, *atd;
hipMalloc((void **)&ad, ncells*sizeof(double));
hipMalloc((void **)&atd, ncells*sizeof(double));
hipMemcpy(ad, a, ncells*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(atd, at, ncells*sizeof(double), hipMemcpyHostToDevice);
//
// CUDA thread blocks
//
const int blocki = 32;
const int blockj = 8;
const int gridi = itot/blocki + (itot%blocki > 0);
const int gridj = jtot/blockj + (jtot%blockj > 0);
dim3 gridGPU (gridi, gridj, ktot);
dim3 gridGPU2d(gridi, gridj, 1);
dim3 blockGPU(blocki, blockj, 1);
//
// Timer stuff
//
hipEvent_t startEvent, stopEvent;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
float dt1, dt2;
//
// Execute kernels
//
//////////////////// CPU //////////////////////////
hipEventRecord(startEvent, 0);
for(int n=0; n<iter; ++n)
{
diff_cpu_3d(at, a, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells);
}
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&dt1, startEvent, stopEvent);
printf("CPU; elapsed=%f [ms]\n",dt1);
//////////////////// GPU //////////////////////////
hipDeviceSetSharedMemConfig(hipSharedMemBankSizeEightByte);
hipEventRecord(startEvent, 0);
for(int n=0; n<iter; ++n)
{
diff_gpu_3d<<<gridGPU, blockGPU>>>
(atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells);
//diff_gpu_3d_s2d<<<gridGPU, blockGPU, (blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>>
// (atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells, gc);
//diff_gpu_3d_s3d<<<gridGPU2d, blockGPU, (blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>>
// (atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells, gc);
}
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&dt2, startEvent, stopEvent);
//
// Copy device field to tmp1
//
hipMemcpy(tmp1, atd, ncells*sizeof(double), hipMemcpyDeviceToHost);
printf("GPU; elapsed=%f [ms], speedup=%f, maxdiff=%e \n",dt2,dt1/dt2,maxdiff(at,tmp1,ncells));
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <stdlib.h>
#include <cstdio>
__host__ __device__ inline double dg4(const double v1, const double v2, const double v3, const double v4, const double v5, const double v6, const double v7)
{
return (1./576.)*(v1+v7) + (-54./576.)*(v2+v6) + (783./576.)*(v3+v5) + (-1460./576.)*v4;
}
/*
4th order diffusion (3D), quite similar to CPU implementation MicroHH
*/
void diff_cpu_3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells)
{
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj1 = 1*icells;
const int jj2 = 2*icells;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const double visc = 0.1;
for (int k=kstart; k<kend; ++k)
for (int j=jstart; j<jend; ++j)
#pragma ivdep
for (int i=istart; i<iend; ++i)
{
const int ijk = i + j*icells + k*ijcells;
at[ijk] += visc * dg4(a[ijk-ii3], a[ijk-ii2], a[ijk-ii1], a[ijk], a[ijk+ii1], a[ijk+ii2], a[ijk+ii3])*dxidxi
+ visc * dg4(a[ijk-jj3], a[ijk-jj2], a[ijk-jj1], a[ijk], a[ijk+jj1], a[ijk+jj2], a[ijk+jj3])*dyidyi
+ visc * dg4(a[ijk-kk3], a[ijk-kk2], a[ijk-kk1], a[ijk], a[ijk+kk1], a[ijk+kk2], a[ijk+kk3])*dzidzi;
}
}
/*
4th order diffusion (3D), no shared memory use, quite similar to GPU implementation MicroHH
*/
__global__ void diff_gpu_3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells)
{
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int k = blockIdx.z + kstart;
const double visc = 0.1;
if(i < iend && j < jend && k < kend)
{
const int ijk = i + j*icells + k*ijcells;
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj1 = 1*icells;
const int jj2 = 2*icells;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
at[ijk] += visc * dg4(a[ijk-ii3], a[ijk-ii2], a[ijk-ii1], a[ijk], a[ijk+ii1], a[ijk+ii2], a[ijk+ii3])*dxidxi
+ visc * dg4(a[ijk-jj3], a[ijk-jj2], a[ijk-jj1], a[ijk], a[ijk+jj1], a[ijk+jj2], a[ijk+jj3])*dyidyi
+ visc * dg4(a[ijk-kk3], a[ijk-kk2], a[ijk-kk1], a[ijk], a[ijk+kk1], a[ijk+kk2], a[ijk+kk3])*dzidzi;
}
}
/*
4th order diffusion, shared memory for horizontal (i,j) stencil, global memory for vertical (k) stencil
*/
__global__ void diff_gpu_3d_s2d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells, const int ngc)
{
extern __shared__ double as[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int k = blockIdx.z + kstart;
const int blockxpad = blockDim.x+2*ngc;
const double visc = 0.1;
if(i < iend && j < jend && k < kend)
{
const int ijk = i + j*icells + k*ijcells; // index in global memory
const int ijks = (tx+ngc) + (ty+ngc)*blockxpad; // Same location in 2d shared mem
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const int jjs1 = 1*blockxpad;
const int jjs2 = 2*blockxpad;
const int jjs3 = 3*blockxpad;
as[ijks] = a[ijk];
if(ty < ngc)
as[ijks-jjs3] = a[ijk-jj3];
if(ty >= blockDim.y-ngc)
as[ijks+jjs3] = a[ijk+jj3];
if(tx < ngc)
as[ijks-ii3] = a[ijk-ii3];
if(tx >= blockDim.x-ngc)
as[ijks+ii3] = a[ijk+ii3];
__syncthreads();
at[ijk] += visc * dg4(as[ijks-ii3 ], as[ijks-ii2 ], as[ijks-ii1 ], as[ijks], as[ijks+ii1 ], as[ijks+ii2 ], as[ijks+ii3 ])*dxidxi
+ visc * dg4(as[ijks-jjs3], as[ijks-jjs2], as[ijks-jjs1], as[ijks], as[ijks+jjs1], as[ijks+jjs2], as[ijks+jjs3])*dyidyi
+ visc * dg4(a [ijk-kk3 ], a [ijk-kk2 ], a [ijk-kk1 ], as[ijks], a [ijk+kk1 ], a [ijk+kk2 ], a [ijk+kk3 ])*dzidzi;
}
}
/*
4th order diffusion, shared memory for horizontal (i,j) stencil, vertical stencil in local variables, vertical loop on GPU
*/
__global__ void diff_gpu_3d_s3d(double * const __restrict__ at, const double * const __restrict__ a,
const double dxidxi, const double dyidyi, const double dzidzi,
const int istart, const int iend,
const int jstart, const int jend,
const int kstart, const int kend,
const int icells, const int ijcells, const int ngc)
{
extern __shared__ double as[];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int i = blockIdx.x*blockDim.x + threadIdx.x + istart;
const int j = blockIdx.y*blockDim.y + threadIdx.y + jstart;
const int blockxpad = blockDim.x+2*ngc;
const double visc = 0.1;
if(i < iend && j < jend)
{
const int ii1 = 1;
const int ii2 = 2;
const int ii3 = 3;
const int jj3 = 3*icells;
const int kk1 = 1*ijcells;
const int kk2 = 2*ijcells;
const int kk3 = 3*ijcells;
const int kk4 = 4*ijcells;
const int jjs1 = 1*blockxpad;
const int jjs2 = 2*blockxpad;
const int jjs3 = 3*blockxpad;
int ijk = i +j*icells + kstart*ijcells;
double akm3, akm2, akm1, aijk, akp1, akp2, akp3;
// Read vertical stencil into variables
akm3 = a[ijk-kk3];
akm2 = a[ijk-kk2];
akm1 = a[ijk-kk1];
aijk = a[ijk ];
akp1 = a[ijk+kk1];
akp2 = a[ijk+kk2];
akp3 = a[ijk+kk3];
for (int k=kstart; k<kend; ++k)
{
const int ijk = i + j*icells + k*ijcells; // index in global memory
const int ijks = (tx+ngc) + (ty+ngc)*blockxpad; // Same location in 2d shared mem
__syncthreads();
as[ijks] = aijk;
if(ty < ngc)
as[ijks-jjs3] = a[ijk-jj3];
if(ty >= blockDim.y-ngc)
as[ijks+jjs3] = a[ijk+jj3];
if(tx < ngc)
as[ijks-ii3] = a[ijk-ii3];
if(tx >= blockDim.x-ngc)
as[ijks+ii3] = a[ijk+ii3];
__syncthreads();
at[ijk] += visc * dg4(as[ijks-ii3 ], as[ijks-ii2 ], as[ijks-ii1 ], as[ijks], as[ijks+ii1 ], as[ijks+ii2 ], as[ijks+ii3 ])*dxidxi
+ visc * dg4(as[ijks-jjs3], as[ijks-jjs2], as[ijks-jjs1], as[ijks], as[ijks+jjs1], as[ijks+jjs2], as[ijks+jjs3])*dyidyi
+ visc * dg4(akm3, akm2, akm1, aijk, akp1, akp2, akp3 )*dzidzi;
// Shift vertical stencil
akm3 = akm2;
akm2 = akm1;
akm1 = aijk;
aijk = akp1;
akp1 = akp2;
akp2 = akp3;
if(k < kend-1)
akp3 = a[ijk+kk4];
}
}
}
/*
Get max difference between two fields
*/
double maxdiff(const double * const __restrict__ a, const double * const __restrict__ b, const int n)
{
double maxdiff=0;
double diff=0;
for(int i=0; i<n; ++i)
{
diff = std::abs(a[i]-b[i]);
if(diff > maxdiff)
maxdiff = diff;
}
return maxdiff;
}
int main()
{
//
// Grid
//
const double dxi = 0.1;
const double dyi = 0.1;
const double dzi = 0.1;
const int itot = 256;
const int jtot = 256;
const int ktot = 256;
const int gc = 3;
const int iter = 50;
//
// Calculate the required variables.
//
const int ncells = (itot+2*gc)*(jtot+2*gc)*(ktot+2*gc);
const int istart = gc;
const int jstart = gc;
const int kstart = gc;
const int iend = itot+gc;
const int jend = jtot+gc;
const int kend = ktot+gc;
const int icells = itot+2*gc;
const int ijcells = (itot+2*gc)*(jtot+2*gc);
//
// Prepare fields on HOST
//
double *a = new double[ncells];
double *at = new double[ncells];
double *tmp1 = new double[ncells];
for (int n=0; n<ncells; ++n)
{
a [n] = 0.001 * (std::rand() % 1000) - 0.5;
at[n] = 0.;
tmp1[n] = 0.;
}
//
// Prepare fields on DEVICE
//
double *ad, *atd;
hipMalloc((void **)&ad, ncells*sizeof(double));
hipMalloc((void **)&atd, ncells*sizeof(double));
hipMemcpy(ad, a, ncells*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(atd, at, ncells*sizeof(double), hipMemcpyHostToDevice);
//
// CUDA thread blocks
//
const int blocki = 32;
const int blockj = 8;
const int gridi = itot/blocki + (itot%blocki > 0);
const int gridj = jtot/blockj + (jtot%blockj > 0);
dim3 gridGPU (gridi, gridj, ktot);
dim3 gridGPU2d(gridi, gridj, 1);
dim3 blockGPU(blocki, blockj, 1);
//
// Timer stuff
//
hipEvent_t startEvent, stopEvent;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
float dt1, dt2;
//
// Execute kernels
//
//////////////////// CPU //////////////////////////
hipEventRecord(startEvent, 0);
for(int n=0; n<iter; ++n)
{
diff_cpu_3d(at, a, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells);
}
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&dt1, startEvent, stopEvent);
printf("CPU; elapsed=%f [ms]\n",dt1);
//////////////////// GPU //////////////////////////
hipDeviceSetSharedMemConfig(hipSharedMemBankSizeEightByte);
hipEventRecord(startEvent, 0);
for(int n=0; n<iter; ++n)
{
diff_gpu_3d<<<gridGPU, blockGPU>>>
(atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells);
//diff_gpu_3d_s2d<<<gridGPU, blockGPU, (blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>>
// (atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells, gc);
//diff_gpu_3d_s3d<<<gridGPU2d, blockGPU, (blocki+2*gc)*(blockj+2*gc)*sizeof(double)>>>
// (atd, ad, dxi, dyi, dzi, istart, iend, jstart, jend, kstart, kend, icells, ijcells, gc);
}
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&dt2, startEvent, stopEvent);
//
// Copy device field to tmp1
//
hipMemcpy(tmp1, atd, ncells*sizeof(double), hipMemcpyDeviceToHost);
printf("GPU; elapsed=%f [ms], speedup=%f, maxdiff=%e \n",dt2,dt1/dt2,maxdiff(at,tmp1,ncells));
return 0;
}
|
.text
.file "diff4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11diff_cpu_3dPdPKddddiiiiiiii
.LCPI0_0:
.quad 0x3f5c71c71c71c71c # double 0.001736111111111111
.LCPI0_1:
.quad 0x3fb8000000000000 # double 0.09375
.LCPI0_2:
.quad 0x3ff5c00000000000 # double 1.359375
.LCPI0_3:
.quad 0x4004471c71c71c72 # double 2.5347222222222223
.LCPI0_4:
.quad 0x3fb999999999999a # double 0.10000000000000001
.text
.globl _Z11diff_cpu_3dPdPKddddiiiiiiii
.p2align 4, 0x90
.type _Z11diff_cpu_3dPdPKddddiiiiiiii,@function
_Z11diff_cpu_3dPdPKddddiiiiiiii: # @_Z11diff_cpu_3dPdPKddddiiiiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $96, %rsp
.cfi_def_cfa_offset 152
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, -120(%rsp) # 4-byte Spill
# kill: def $r8d killed $r8d def $r8
movq %r8, -80(%rsp) # 8-byte Spill
movl %ecx, -124(%rsp) # 4-byte Spill
movl %edx, -128(%rsp) # 4-byte Spill
movl 152(%rsp), %r12d
cmpl 160(%rsp), %r12d
jge .LBB0_8
# %bb.1: # %.preheader83.lr.ph
movl 176(%rsp), %ecx
movl 168(%rsp), %r15d
movl -128(%rsp), %r8d # 4-byte Reload
movslq %r8d, %rdx
movl %r8d, %r9d
movslq -124(%rsp), %r8 # 4-byte Folded Reload
subq %rdx, %r8
movq %r8, 80(%rsp) # 8-byte Spill
leal -3(%r12), %edx
imull %ecx, %edx
movq %rdx, -88(%rsp) # 8-byte Spill
leal -2(%r12), %edx
imull %ecx, %edx
movq %rdx, -96(%rsp) # 8-byte Spill
leal -1(%r12), %ebx
imull %ecx, %ebx
leal 1(%r12), %r14d
imull %ecx, %r14d
leal 2(%r12), %r13d
imull %ecx, %r13d
leal 3(%r12), %ebp
imull %ecx, %ebp
movl %ecx, %edx
imull %r12d, %edx
addl %r9d, %edx
movq -80(%rsp), %r8 # 8-byte Reload
leal -3(%r8), %ecx
imull %r15d, %ecx
movq %rcx, -112(%rsp) # 8-byte Spill
leal -2(%r8), %eax
imull %r15d, %eax
leal -1(%r8), %ecx
imull %r15d, %ecx
movq %rcx, -104(%rsp) # 8-byte Spill
leal 1(%r8), %r9d
imull %r15d, %r9d
leal 2(%r8), %ecx
imull %r15d, %ecx
leal 3(%r8), %r11d
imull %r15d, %r11d
movq %rdi, %r10
movl %r15d, %edi
imull %r8d, %edi
movq -112(%rsp), %r8 # 8-byte Reload
addl %edx, %r8d
movq %r8, -112(%rsp) # 8-byte Spill
addl %edx, %eax
movq -104(%rsp), %r8 # 8-byte Reload
addl %edx, %r8d
addl %edx, %r9d
addl %edx, %ecx
addl %edx, %r11d
addl %edi, %edx
movq %rdx, -72(%rsp) # 8-byte Spill
movq %r8, %rdx
movq %rcx, %r8
movq -88(%rsp), %rcx # 8-byte Reload
addl -128(%rsp), %edi # 4-byte Folded Reload
addl %edi, %ecx
movq -96(%rsp), %r15 # 8-byte Reload
addl %edi, %r15d
addl %edi, %ebx
addl %edi, %r14d
addl %edi, %r13d
addl %edi, %ebp
movq %r15, %rdi
movl 176(%rsp), %r15d
movq %r15, -8(%rsp) # 8-byte Spill
movl 168(%rsp), %r15d
movq %r15, 72(%rsp) # 8-byte Spill
movsd .LCPI0_0(%rip), %xmm15 # xmm15 = mem[0],zero
movsd .LCPI0_1(%rip), %xmm4 # xmm4 = mem[0],zero
movsd .LCPI0_2(%rip), %xmm7 # xmm7 = mem[0],zero
movsd .LCPI0_3(%rip), %xmm9 # xmm9 = mem[0],zero
movsd .LCPI0_4(%rip), %xmm3 # xmm3 = mem[0],zero
movsd %xmm2, 88(%rsp) # 8-byte Spill
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_7: # %._crit_edge86
# in Loop: Header=BB0_2 Depth=1
movq 64(%rsp), %r12 # 8-byte Reload
incl %r12d
movq -8(%rsp), %r15 # 8-byte Reload
addq %r15, -72(%rsp) # 8-byte Folded Spill
addq %r15, -112(%rsp) # 8-byte Folded Spill
movq 24(%rsp), %rax # 8-byte Reload
addq %r15, %rax
movq -104(%rsp), %rdx # 8-byte Reload
addq %r15, %rdx
movq 16(%rsp), %r9 # 8-byte Reload
addq %r15, %r9
movq 8(%rsp), %r8 # 8-byte Reload
addq %r15, %r8
movq (%rsp), %r11 # 8-byte Reload
addq %r15, %r11
movq -88(%rsp), %rcx # 8-byte Reload
addq %r15, %rcx
movq -96(%rsp), %rdi # 8-byte Reload
addq %r15, %rdi
movq 56(%rsp), %rbx # 8-byte Reload
addq %r15, %rbx
movq 48(%rsp), %r14 # 8-byte Reload
addq %r15, %r14
movq 40(%rsp), %r13 # 8-byte Reload
addq %r15, %r13
movq 32(%rsp), %rbp # 8-byte Reload
addq %r15, %rbp
cmpl 160(%rsp), %r12d
je .LBB0_8
.LBB0_2: # %.preheader83
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_5 Depth 3
movq %r12, 64(%rsp) # 8-byte Spill
movq %rbp, 32(%rsp) # 8-byte Spill
movq %r13, 40(%rsp) # 8-byte Spill
movq %r13, -32(%rsp) # 8-byte Spill
movq %r14, 48(%rsp) # 8-byte Spill
movq %r14, -40(%rsp) # 8-byte Spill
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rbx, %r12
movq %rdi, -96(%rsp) # 8-byte Spill
movq %rdi, %r13
movq %rcx, -88(%rsp) # 8-byte Spill
movq %r11, (%rsp) # 8-byte Spill
movq %r11, -48(%rsp) # 8-byte Spill
movq %r8, 8(%rsp) # 8-byte Spill
movq %r9, 16(%rsp) # 8-byte Spill
movq %r9, -56(%rsp) # 8-byte Spill
movq %rdx, -104(%rsp) # 8-byte Spill
movq %rdx, %r9
movq %rax, 24(%rsp) # 8-byte Spill
movq %rax, %r11
movq -112(%rsp), %rbx # 8-byte Reload
movq -72(%rsp), %rax # 8-byte Reload
movq %rax, -64(%rsp) # 8-byte Spill
movq -80(%rsp), %rax # 8-byte Reload
movl %eax, %edx
movl %eax, -116(%rsp) # 4-byte Spill
cmpl -120(%rsp), %eax # 4-byte Folded Reload
jl .LBB0_3
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_6: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
movl -116(%rsp), %edi # 4-byte Reload
incl %edi
movq 72(%rsp), %rax # 8-byte Reload
addq %rax, %rbx
movq %rbx, -64(%rsp) # 8-byte Spill
addq %rax, %rbp
movq %rbp, %rbx
addq %rax, %r11
addq %rax, %r9
addq %rax, %r8
movq %r8, -56(%rsp) # 8-byte Spill
movq -16(%rsp), %r8 # 8-byte Reload
addq %rax, %r8
addq %rax, %rdx
movq %rdx, -48(%rsp) # 8-byte Spill
addq %rax, %rcx
addq %rax, %r13
addq %rax, %r12
addq %rax, %r15
movq %r15, -40(%rsp) # 8-byte Spill
addq %rax, -32(%rsp) # 8-byte Folded Spill
movq -24(%rsp), %rbp # 8-byte Reload
addq %rax, %rbp
movl %edi, -116(%rsp) # 4-byte Spill
cmpl -120(%rsp), %edi # 4-byte Folded Reload
je .LBB0_7
.LBB0_3: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_5 Depth 3
movq %rbp, -24(%rsp) # 8-byte Spill
movq %r8, -16(%rsp) # 8-byte Spill
movl -128(%rsp), %eax # 4-byte Reload
cmpl -124(%rsp), %eax # 4-byte Folded Reload
movq 80(%rsp), %r14 # 8-byte Reload
movq -40(%rsp), %r15 # 8-byte Reload
movq -48(%rsp), %rdx # 8-byte Reload
movq -56(%rsp), %r8 # 8-byte Reload
movq %rbx, %rbp
movq -64(%rsp), %rbx # 8-byte Reload
jge .LBB0_6
# %bb.4: # %.lr.ph
# in Loop: Header=BB0_3 Depth=2
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_5: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
leal (%rax,%rbp), %edi
movslq %edi, %rdi
movapd %xmm1, %xmm2
movapd %xmm9, %xmm1
movsd (%rsi,%rdi,8), %xmm9 # xmm9 = mem[0],zero
leal (%r11,%rax), %edi
movslq %edi, %rdi
movsd (%rsi,%rdi,8), %xmm10 # xmm10 = mem[0],zero
leal (%r9,%rax), %edi
movslq %edi, %rdi
movsd (%rsi,%rdi,8), %xmm8 # xmm8 = mem[0],zero
leal (%rcx,%rax), %edi
movslq %edi, %rdi
movsd (%rsi,%rdi,8), %xmm11 # xmm11 = mem[0],zero
leal (%r13,%rax), %edi
movslq %edi, %rdi
movsd (%rsi,%rdi,8), %xmm13 # xmm13 = mem[0],zero
leal (%rdx,%rax), %edi
movslq %edi, %rdi
addsd (%rsi,%rdi,8), %xmm9
movq -16(%rsp), %rdi # 8-byte Reload
leal (%rdi,%rax), %edi
movslq %edi, %rdi
addsd (%rsi,%rdi,8), %xmm10
leal (%r8,%rax), %edi
movslq %edi, %rdi
addsd (%rsi,%rdi,8), %xmm8
leal (%r12,%rax), %edi
movslq %edi, %rdi
movsd (%rsi,%rdi,8), %xmm12 # xmm12 = mem[0],zero
movq -24(%rsp), %rdi # 8-byte Reload
leal (%rdi,%rax), %edi
movslq %edi, %rdi
addsd (%rsi,%rdi,8), %xmm11
movq -32(%rsp), %rdi # 8-byte Reload
leal (%rdi,%rax), %edi
movslq %edi, %rdi
addsd (%rsi,%rdi,8), %xmm13
leal (%r15,%rax), %edi
movslq %edi, %rdi
addsd (%rsi,%rdi,8), %xmm12
leal (%rbx,%rax), %edi
movslq %edi, %rdi
movsd -24(%rsi,%rdi,8), %xmm14 # xmm14 = mem[0],zero
addsd 24(%rsi,%rdi,8), %xmm14
movapd %xmm4, %xmm5
movapd %xmm15, %xmm4
movsd -16(%rsi,%rdi,8), %xmm15 # xmm15 = mem[0],zero
addsd 16(%rsi,%rdi,8), %xmm15
movsd -8(%rsi,%rdi,8), %xmm6 # xmm6 = mem[0],zero
mulsd %xmm4, %xmm14
addsd 8(%rsi,%rdi,8), %xmm6
mulsd %xmm5, %xmm15
subsd %xmm15, %xmm14
movapd %xmm4, %xmm15
movapd %xmm5, %xmm4
mulsd %xmm15, %xmm9
mulsd %xmm5, %xmm10
subsd %xmm10, %xmm9
mulsd %xmm7, %xmm6
mulsd %xmm15, %xmm11
mulsd %xmm5, %xmm13
addsd %xmm14, %xmm6
subsd %xmm13, %xmm11
movsd (%rsi,%rdi,8), %xmm10 # xmm10 = mem[0],zero
mulsd %xmm7, %xmm8
addsd %xmm9, %xmm8
movapd %xmm1, %xmm9
movapd %xmm2, %xmm1
movsd 88(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd %xmm9, %xmm10
subsd %xmm10, %xmm6
mulsd %xmm3, %xmm6
mulsd %xmm0, %xmm6
subsd %xmm10, %xmm8
mulsd %xmm3, %xmm8
mulsd %xmm7, %xmm12
mulsd %xmm1, %xmm8
addsd %xmm11, %xmm12
subsd %xmm10, %xmm12
mulsd %xmm3, %xmm12
addsd %xmm6, %xmm8
mulsd %xmm2, %xmm12
addsd %xmm8, %xmm12
addsd (%r10,%rdi,8), %xmm12
movsd %xmm12, (%r10,%rdi,8)
incq %rax
cmpq %rax, %r14
jne .LBB0_5
jmp .LBB0_6
.LBB0_8: # %._crit_edge88
addq $96, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11diff_cpu_3dPdPKddddiiiiiiii, .Lfunc_end0-_Z11diff_cpu_3dPdPKddddiiiiiiii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__diff_gpu_3dPdPKddddiiiiiiii # -- Begin function _Z26__device_stub__diff_gpu_3dPdPKddddiiiiiiii
.p2align 4, 0x90
.type _Z26__device_stub__diff_gpu_3dPdPKddddiiiiiiii,@function
_Z26__device_stub__diff_gpu_3dPdPKddddiiiiiiii: # @_Z26__device_stub__diff_gpu_3dPdPKddddiiiiiiii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movsd %xmm2, 72(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 224(%rsp), %rax
movq %rax, 184(%rsp)
leaq 232(%rsp), %rax
movq %rax, 192(%rsp)
leaq 240(%rsp), %rax
movq %rax, 200(%rsp)
leaq 248(%rsp), %rax
movq %rax, 208(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11diff_gpu_3dPdPKddddiiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end1:
.size _Z26__device_stub__diff_gpu_3dPdPKddddiiiiiiii, .Lfunc_end1-_Z26__device_stub__diff_gpu_3dPdPKddddiiiiiiii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__diff_gpu_3d_s2dPdPKddddiiiiiiiii # -- Begin function _Z30__device_stub__diff_gpu_3d_s2dPdPKddddiiiiiiiii
.p2align 4, 0x90
.type _Z30__device_stub__diff_gpu_3d_s2dPdPKddddiiiiiiiii,@function
_Z30__device_stub__diff_gpu_3d_s2dPdPKddddiiiiiiiii: # @_Z30__device_stub__diff_gpu_3d_s2dPdPKddddiiiiiiiii
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movsd %xmm2, 72(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end2:
.size _Z30__device_stub__diff_gpu_3d_s2dPdPKddddiiiiiiiii, .Lfunc_end2-_Z30__device_stub__diff_gpu_3d_s2dPdPKddddiiiiiiiii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__diff_gpu_3d_s3dPdPKddddiiiiiiiii # -- Begin function _Z30__device_stub__diff_gpu_3d_s3dPdPKddddiiiiiiiii
.p2align 4, 0x90
.type _Z30__device_stub__diff_gpu_3d_s3dPdPKddddiiiiiiiii,@function
_Z30__device_stub__diff_gpu_3d_s3dPdPKddddiiiiiiiii: # @_Z30__device_stub__diff_gpu_3d_s3dPdPKddddiiiiiiiii
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movsd %xmm2, 72(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end3:
.size _Z30__device_stub__diff_gpu_3d_s3dPdPKddddiiiiiiiii, .Lfunc_end3-_Z30__device_stub__diff_gpu_3d_s3dPdPKddddiiiiiiiii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z7maxdiffPKdS0_i
.LCPI4_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z7maxdiffPKdS0_i
.p2align 4, 0x90
.type _Z7maxdiffPKdS0_i,@function
_Z7maxdiffPKdS0_i: # @_Z7maxdiffPKdS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_1
# %bb.3: # %.lr.ph.preheader
movl %edx, %eax
xorpd %xmm2, %xmm2
xorl %ecx, %ecx
movapd .LCPI4_0(%rip), %xmm1 # xmm1 = [NaN,NaN]
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
subsd (%rsi,%rcx,8), %xmm0
andpd %xmm1, %xmm0
maxsd %xmm2, %xmm0
incq %rcx
movapd %xmm0, %xmm2
cmpq %rcx, %rax
jne .LBB4_4
# %bb.2: # %._crit_edge
retq
.LBB4_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end4:
.size _Z7maxdiffPKdS0_i, .Lfunc_end4-_Z7maxdiffPKdS0_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI5_1:
.quad 0xbfe0000000000000 # double -0.5
.LCPI5_2:
.quad 0x3fb999999999999a # double 0.10000000000000001
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI5_3:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $143877824, %edi # imm = 0x89366C0
callq _Znam
movq %rax, %r15
movl $143877824, %edi # imm = 0x89366C0
callq _Znam
movq %rax, %rbx
movl $143877824, %edi # imm = 0x89366C0
callq _Znam
movq %rax, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI5_0(%rip), %xmm0
addsd .LCPI5_1(%rip), %xmm0
movsd %xmm0, (%r15,%r12,8)
movq $0, (%rbx,%r12,8)
movq $0, (%r14,%r12,8)
incq %r12
cmpq $17984728, %r12 # imm = 0x1126CD8
jne .LBB5_1
# %bb.2:
leaq 64(%rsp), %rdi
movl $143877824, %esi # imm = 0x89366C0
callq hipMalloc
leaq 24(%rsp), %rdi
movl $143877824, %esi # imm = 0x89366C0
callq hipMalloc
movq 64(%rsp), %rdi
movl $143877824, %edx # imm = 0x89366C0
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $143877824, %edx # imm = 0x89366C0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $50, %ebp
.p2align 4, 0x90
.LBB5_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movq %r15, %rsi
movsd .LCPI5_2(%rip), %xmm0 # xmm0 = mem[0],zero
movapd %xmm0, %xmm1
movapd %xmm0, %xmm2
movl $3, %edx
movl $259, %ecx # imm = 0x103
movl $3, %r8d
movl $259, %r9d # imm = 0x103
pushq $68644 # imm = 0x10C24
.cfi_adjust_cfa_offset 8
pushq $262 # imm = 0x106
.cfi_adjust_cfa_offset 8
pushq $259 # imm = 0x103
.cfi_adjust_cfa_offset 8
pushq $3
.cfi_adjust_cfa_offset 8
callq _Z11diff_cpu_3dPdPKddddiiiiiiii
addq $32, %rsp
.cfi_adjust_cfa_offset -32
decl %ebp
jne .LBB5_3
# %bb.4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $2, %edi
callq hipDeviceSetSharedMemConfig
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $50, %ebp
movabsq $137438953480, %r15 # imm = 0x2000000008
movabsq $34359738400, %r12 # imm = 0x800000020
movabsq $4591870180066957722, %r13 # imm = 0x3FB999999999999A
jmp .LBB5_5
.p2align 4, 0x90
.LBB5_7: # in Loop: Header=BB5_5 Depth=1
decl %ebp
je .LBB5_8
.LBB5_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $256, %esi # imm = 0x100
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6: # in Loop: Header=BB5_5 Depth=1
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 64(%rsp), %rax
movq %rax, 144(%rsp)
movq %r13, 136(%rsp)
movq %r13, 128(%rsp)
movq %r13, 120(%rsp)
movl $3, 60(%rsp)
movl $259, 56(%rsp) # imm = 0x103
movl $3, 52(%rsp)
movl $259, 48(%rsp) # imm = 0x103
movl $3, 44(%rsp)
movl $259, 40(%rsp) # imm = 0x103
movl $262, 36(%rsp) # imm = 0x106
movl $68644, 32(%rsp) # imm = 0x10C24
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 52(%rsp), %rax
movq %rax, 216(%rsp)
leaq 48(%rsp), %rax
movq %rax, 224(%rsp)
leaq 44(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 36(%rsp), %rax
movq %rax, 248(%rsp)
leaq 32(%rsp), %rax
movq %rax, 256(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z11diff_gpu_3dPdPKddddiiiiiiii, %edi
leaq 160(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_7
.LBB5_8:
movq (%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rsi
movl $143877824, %edx # imm = 0x89366C0
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorpd %xmm2, %xmm2
movapd .LCPI5_3(%rip), %xmm3 # xmm3 = [NaN,NaN]
.p2align 4, 0x90
.LBB5_9: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movapd %xmm2, %xmm4
movsd (%rbx,%r15,8), %xmm2 # xmm2 = mem[0],zero
subsd (%r14,%r15,8), %xmm2
andpd %xmm3, %xmm2
maxsd %xmm4, %xmm2
incq %r15
cmpq $17984728, %r15 # imm = 0x1126CD8
jne .LBB5_9
# %bb.10: # %_Z7maxdiffPKdS0_i.exit
divss %xmm0, %xmm1
cvtss2sd %xmm1, %xmm1
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $3, %al
callq printf
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11diff_gpu_3dPdPKddddiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11diff_gpu_3dPdPKddddiiiiiiii,@object # @_Z11diff_gpu_3dPdPKddddiiiiiiii
.section .rodata,"a",@progbits
.globl _Z11diff_gpu_3dPdPKddddiiiiiiii
.p2align 3, 0x0
_Z11diff_gpu_3dPdPKddddiiiiiiii:
.quad _Z26__device_stub__diff_gpu_3dPdPKddddiiiiiiii
.size _Z11diff_gpu_3dPdPKddddiiiiiiii, 8
.type _Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii,@object # @_Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii
.globl _Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii
.p2align 3, 0x0
_Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii:
.quad _Z30__device_stub__diff_gpu_3d_s2dPdPKddddiiiiiiiii
.size _Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii, 8
.type _Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii,@object # @_Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii
.globl _Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii
.p2align 3, 0x0
_Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii:
.quad _Z30__device_stub__diff_gpu_3d_s3dPdPKddddiiiiiiiii
.size _Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU
.size .L.str.1, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11diff_gpu_3dPdPKddddiiiiiiii"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii"
.size .L__unnamed_2, 37
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii"
.size .L__unnamed_3, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__diff_gpu_3dPdPKddddiiiiiiii
.addrsig_sym _Z30__device_stub__diff_gpu_3d_s2dPdPKddddiiiiiiiii
.addrsig_sym _Z30__device_stub__diff_gpu_3d_s3dPdPKddddiiiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11diff_gpu_3dPdPKddddiiiiiiii
.addrsig_sym _Z15diff_gpu_3d_s2dPdPKddddiiiiiiiii
.addrsig_sym _Z15diff_gpu_3d_s3dPdPKddddiiiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#define SIZE 10
__global__ void demo(int * p){
int tx=threadIdx.x;
// Trying to access variables allocated on main memory in a kernel function is illegal.
p[tx]=tx+p[tx];
}
int main(int argc , char **argv){
int * p;
p=(int *)malloc(10*sizeof(int));
int i;
for(i=0;i<SIZE;i++){
p[i]=1;
}
dim3 dimGrid(1,1);
dim3 dimBlock(SIZE,1);
demo<<<dimGrid,dimBlock>>>(p);
for(i=0;i<SIZE;i++){
printf("p[%d]=%d\n",i,p[i]);
}
free(p);
return 0;
}
|
code for sm_80
Function : _Z4demoPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#define SIZE 10
__global__ void demo(int * p){
int tx=threadIdx.x;
// Trying to access variables allocated on main memory in a kernel function is illegal.
p[tx]=tx+p[tx];
}
int main(int argc , char **argv){
int * p;
p=(int *)malloc(10*sizeof(int));
int i;
for(i=0;i<SIZE;i++){
p[i]=1;
}
dim3 dimGrid(1,1);
dim3 dimBlock(SIZE,1);
demo<<<dimGrid,dimBlock>>>(p);
for(i=0;i<SIZE;i++){
printf("p[%d]=%d\n",i,p[i]);
}
free(p);
return 0;
}
|
.file "tmpxft_001099a2_00000000-6_m1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4demoPiPi
.type _Z23__device_stub__Z4demoPiPi, @function
_Z23__device_stub__Z4demoPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4demoPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4demoPiPi, .-_Z23__device_stub__Z4demoPiPi
.globl _Z4demoPi
.type _Z4demoPi, @function
_Z4demoPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4demoPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4demoPi, .-_Z4demoPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "p[%d]=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rax), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L13:
movl $0, %ebx
leaq .LC0(%rip), %r12
.L14:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq %rbp, %rdi
call _Z23__device_stub__Z4demoPiPi
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4demoPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4demoPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#define SIZE 10
__global__ void demo(int * p){
int tx=threadIdx.x;
// Trying to access variables allocated on main memory in a kernel function is illegal.
p[tx]=tx+p[tx];
}
int main(int argc , char **argv){
int * p;
p=(int *)malloc(10*sizeof(int));
int i;
for(i=0;i<SIZE;i++){
p[i]=1;
}
dim3 dimGrid(1,1);
dim3 dimBlock(SIZE,1);
demo<<<dimGrid,dimBlock>>>(p);
for(i=0;i<SIZE;i++){
printf("p[%d]=%d\n",i,p[i]);
}
free(p);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SIZE 10
__global__ void demo(int * p){
int tx=threadIdx.x;
// Trying to access variables allocated on main memory in a kernel function is illegal.
p[tx]=tx+p[tx];
}
int main(int argc , char **argv){
int * p;
p=(int *)malloc(10*sizeof(int));
int i;
for(i=0;i<SIZE;i++){
p[i]=1;
}
dim3 dimGrid(1,1);
dim3 dimBlock(SIZE,1);
demo<<<dimGrid,dimBlock>>>(p);
for(i=0;i<SIZE;i++){
printf("p[%d]=%d\n",i,p[i]);
}
free(p);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SIZE 10
__global__ void demo(int * p){
int tx=threadIdx.x;
// Trying to access variables allocated on main memory in a kernel function is illegal.
p[tx]=tx+p[tx];
}
int main(int argc , char **argv){
int * p;
p=(int *)malloc(10*sizeof(int));
int i;
for(i=0;i<SIZE;i++){
p[i]=1;
}
dim3 dimGrid(1,1);
dim3 dimBlock(SIZE,1);
demo<<<dimGrid,dimBlock>>>(p);
for(i=0;i<SIZE;i++){
printf("p[%d]=%d\n",i,p[i]);
}
free(p);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4demoPi
.globl _Z4demoPi
.p2align 8
.type _Z4demoPi,@function
_Z4demoPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4demoPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4demoPi, .Lfunc_end0-_Z4demoPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4demoPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z4demoPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SIZE 10
__global__ void demo(int * p){
int tx=threadIdx.x;
// Trying to access variables allocated on main memory in a kernel function is illegal.
p[tx]=tx+p[tx];
}
int main(int argc , char **argv){
int * p;
p=(int *)malloc(10*sizeof(int));
int i;
for(i=0;i<SIZE;i++){
p[i]=1;
}
dim3 dimGrid(1,1);
dim3 dimBlock(SIZE,1);
demo<<<dimGrid,dimBlock>>>(p);
for(i=0;i<SIZE;i++){
printf("p[%d]=%d\n",i,p[i]);
}
free(p);
return 0;
}
|
.text
.file "m1.hip"
.globl _Z19__device_stub__demoPi # -- Begin function _Z19__device_stub__demoPi
.p2align 4, 0x90
.type _Z19__device_stub__demoPi,@function
_Z19__device_stub__demoPi: # @_Z19__device_stub__demoPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4demoPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__demoPi, .Lfunc_end0-_Z19__device_stub__demoPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq %rbx, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4demoPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4: # %.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4demoPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4demoPi,@object # @_Z4demoPi
.section .rodata,"a",@progbits
.globl _Z4demoPi
.p2align 3, 0x0
_Z4demoPi:
.quad _Z19__device_stub__demoPi
.size _Z4demoPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "p[%d]=%d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4demoPi"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__demoPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4demoPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4demoPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4demoPi
.globl _Z4demoPi
.p2align 8
.type _Z4demoPi,@function
_Z4demoPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4demoPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4demoPi, .Lfunc_end0-_Z4demoPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4demoPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z4demoPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001099a2_00000000-6_m1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4demoPiPi
.type _Z23__device_stub__Z4demoPiPi, @function
_Z23__device_stub__Z4demoPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4demoPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4demoPiPi, .-_Z23__device_stub__Z4demoPiPi
.globl _Z4demoPi
.type _Z4demoPi, @function
_Z4demoPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4demoPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4demoPi, .-_Z4demoPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "p[%d]=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rax), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L13:
movl $0, %ebx
leaq .LC0(%rip), %r12
.L14:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq %rbp, %rdi
call _Z23__device_stub__Z4demoPiPi
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4demoPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4demoPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "m1.hip"
.globl _Z19__device_stub__demoPi # -- Begin function _Z19__device_stub__demoPi
.p2align 4, 0x90
.type _Z19__device_stub__demoPi,@function
_Z19__device_stub__demoPi: # @_Z19__device_stub__demoPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4demoPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__demoPi, .Lfunc_end0-_Z19__device_stub__demoPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq %rbx, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4demoPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4: # %.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4demoPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4demoPi,@object # @_Z4demoPi
.section .rodata,"a",@progbits
.globl _Z4demoPi
.p2align 3, 0x0
_Z4demoPi:
.quad _Z19__device_stub__demoPi
.size _Z4demoPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "p[%d]=%d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4demoPi"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__demoPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4demoPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#define N 4000
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
#include <stdio.h>
__global__ void matrixMult (float *a, float *b, float *c, int width) {
int k = 0;
float sum = 0.0;
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < width && row < width) {
for (k = 0; k < width; k++)
sum += a[row * width + k] * b[k * width + col];
c[row * width + col] = sum;
}
}
int main() {
//float a[N][N], b[N][N], c[N][N];
float *dev_a, *dev_b, *dev_c;
float *a,*b,*c;
a = (float*) malloc(N*N*sizeof(float));
b = (float*) malloc(N*N*sizeof(float));
c = (float*) malloc(N*N*sizeof(float));
// initialize matrices a and b with appropriate values
for (int i = 0; i< N ; i++)
for (int j=0 ; j<N ; j++)
{
a[i*N+j] = 1;
b[i*N+j] = 1;
}
int size = N * N * sizeof(float);
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
int NumThreads = 32;
dim3 dimGrid(DIV_UP(N,NumThreads), DIV_UP(N,NumThreads));
dim3 dimBlock(NumThreads, NumThreads);
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
//measure performance
cudaError_t error;
cudaDeviceSynchronize();
cudaEvent_t start;
error = cudaEventCreate(&start);
if (error != cudaSuccess)
fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
cudaEvent_t stop;
error = cudaEventCreate(&stop);
if (error != cudaSuccess)
fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
error = cudaEventRecord(start, NULL);
if (error != cudaSuccess)
fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
int nIter = 10;
for (int j = 0; j < nIter; j++)
{
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
}
// Record the stop event
error = cudaEventRecord(stop, NULL);
if (error != cudaSuccess)
fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
// Wait for the stop event to complete
error = cudaEventSynchronize(stop);
if (error != cudaSuccess)
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
float msecTotal = 0.0f;
error = cudaEventElapsedTime(&msecTotal, start, stop);
if (error != cudaSuccess)
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
// Compute and print the performance
float msecPerMatrixMul = msecTotal / nIter;
printf ("msec %f\n",msecPerMatrixMul);
//end measure performance
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
/*
for (int i = 0; i< N ; i++){
for (int j=0 ; j<N ; j++)
{
printf("%f , ", c[i][j]);
}
printf ("\n");
}
*/
printf("%f, %f \n",c[0],c[N*N-1] );
cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c);
}
|
code for sm_80
Function : _Z10matrixMultPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#define N 4000
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
#include <stdio.h>
__global__ void matrixMult (float *a, float *b, float *c, int width) {
int k = 0;
float sum = 0.0;
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < width && row < width) {
for (k = 0; k < width; k++)
sum += a[row * width + k] * b[k * width + col];
c[row * width + col] = sum;
}
}
int main() {
//float a[N][N], b[N][N], c[N][N];
float *dev_a, *dev_b, *dev_c;
float *a,*b,*c;
a = (float*) malloc(N*N*sizeof(float));
b = (float*) malloc(N*N*sizeof(float));
c = (float*) malloc(N*N*sizeof(float));
// initialize matrices a and b with appropriate values
for (int i = 0; i< N ; i++)
for (int j=0 ; j<N ; j++)
{
a[i*N+j] = 1;
b[i*N+j] = 1;
}
int size = N * N * sizeof(float);
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
int NumThreads = 32;
dim3 dimGrid(DIV_UP(N,NumThreads), DIV_UP(N,NumThreads));
dim3 dimBlock(NumThreads, NumThreads);
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
//measure performance
cudaError_t error;
cudaDeviceSynchronize();
cudaEvent_t start;
error = cudaEventCreate(&start);
if (error != cudaSuccess)
fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
cudaEvent_t stop;
error = cudaEventCreate(&stop);
if (error != cudaSuccess)
fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
error = cudaEventRecord(start, NULL);
if (error != cudaSuccess)
fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
int nIter = 10;
for (int j = 0; j < nIter; j++)
{
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
}
// Record the stop event
error = cudaEventRecord(stop, NULL);
if (error != cudaSuccess)
fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
// Wait for the stop event to complete
error = cudaEventSynchronize(stop);
if (error != cudaSuccess)
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
float msecTotal = 0.0f;
error = cudaEventElapsedTime(&msecTotal, start, stop);
if (error != cudaSuccess)
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
// Compute and print the performance
float msecPerMatrixMul = msecTotal / nIter;
printf ("msec %f\n",msecPerMatrixMul);
//end measure performance
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
/*
for (int i = 0; i< N ; i++){
for (int j=0 ; j<N ; j++)
{
printf("%f , ", c[i][j]);
}
printf ("\n");
}
*/
printf("%f, %f \n",c[0],c[N*N-1] );
cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c);
}
|
.file "tmpxft_000c3ef9_00000000-6_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
.globl _Z10matrixMultPfS_S_i
.type _Z10matrixMultPfS_S_i, @function
_Z10matrixMultPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10matrixMultPfS_S_i, .-_Z10matrixMultPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to create start event (error code %s)!\n"
.align 8
.LC2:
.string "Failed to create stop event (error code %s)!\n"
.align 8
.LC3:
.string "Failed to record start event (error code %s)!\n"
.align 8
.LC4:
.string "Failed to record stop event (error code %s)!\n"
.align 8
.LC5:
.string "Failed to synchronize on the stop event (error code %s)!\n"
.align 8
.LC7:
.string "Failed to get time elapsed between events (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "msec %f\n"
.LC10:
.string "%f, %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $64000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $64000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $64000000, %edi
call malloc@PLT
movq %rax, %r12
movl $16000, %edx
movss .LC0(%rip), %xmm0
.L12:
leaq -16000(%rdx), %rax
.L13:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addq $16000, %rdx
cmpq $64016000, %rdx
jne .L12
leaq 8(%rsp), %rdi
movl $64000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64000000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $125, 48(%rsp)
movl $125, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L15:
call cudaDeviceSynchronize@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
jne .L29
.L16:
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
jne .L30
.L17:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
jne .L31
.L18:
movl $10, %ebx
jmp .L20
.L28:
movl $4000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
jmp .L15
.L29:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L16
.L30:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L17
.L31:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L19:
subl $1, %ebx
je .L32
.L20:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
movl $4000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
jmp .L19
.L32:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
jne .L33
.L21:
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
jne .L34
.L22:
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
testl %eax, %eax
jne .L35
.L23:
movss 4(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $64000000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 63999996(%r12), %xmm1
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L21
.L34:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L22
.L35:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L23
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z10matrixMultPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC8:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#define N 4000
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
#include <stdio.h>
__global__ void matrixMult (float *a, float *b, float *c, int width) {
int k = 0;
float sum = 0.0;
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < width && row < width) {
for (k = 0; k < width; k++)
sum += a[row * width + k] * b[k * width + col];
c[row * width + col] = sum;
}
}
int main() {
//float a[N][N], b[N][N], c[N][N];
float *dev_a, *dev_b, *dev_c;
float *a,*b,*c;
a = (float*) malloc(N*N*sizeof(float));
b = (float*) malloc(N*N*sizeof(float));
c = (float*) malloc(N*N*sizeof(float));
// initialize matrices a and b with appropriate values
for (int i = 0; i< N ; i++)
for (int j=0 ; j<N ; j++)
{
a[i*N+j] = 1;
b[i*N+j] = 1;
}
int size = N * N * sizeof(float);
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
int NumThreads = 32;
dim3 dimGrid(DIV_UP(N,NumThreads), DIV_UP(N,NumThreads));
dim3 dimBlock(NumThreads, NumThreads);
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
//measure performance
cudaError_t error;
cudaDeviceSynchronize();
cudaEvent_t start;
error = cudaEventCreate(&start);
if (error != cudaSuccess)
fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
cudaEvent_t stop;
error = cudaEventCreate(&stop);
if (error != cudaSuccess)
fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
error = cudaEventRecord(start, NULL);
if (error != cudaSuccess)
fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
int nIter = 10;
for (int j = 0; j < nIter; j++)
{
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
}
// Record the stop event
error = cudaEventRecord(stop, NULL);
if (error != cudaSuccess)
fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
// Wait for the stop event to complete
error = cudaEventSynchronize(stop);
if (error != cudaSuccess)
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
float msecTotal = 0.0f;
error = cudaEventElapsedTime(&msecTotal, start, stop);
if (error != cudaSuccess)
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
// Compute and print the performance
float msecPerMatrixMul = msecTotal / nIter;
printf ("msec %f\n",msecPerMatrixMul);
//end measure performance
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
/*
for (int i = 0; i< N ; i++){
for (int j=0 ; j<N ; j++)
{
printf("%f , ", c[i][j]);
}
printf ("\n");
}
*/
printf("%f, %f \n",c[0],c[N*N-1] );
cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c);
}
|
#define N 4000
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matrixMult (float *a, float *b, float *c, int width) {
int k = 0;
float sum = 0.0;
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < width && row < width) {
for (k = 0; k < width; k++)
sum += a[row * width + k] * b[k * width + col];
c[row * width + col] = sum;
}
}
int main() {
//float a[N][N], b[N][N], c[N][N];
float *dev_a, *dev_b, *dev_c;
float *a,*b,*c;
a = (float*) malloc(N*N*sizeof(float));
b = (float*) malloc(N*N*sizeof(float));
c = (float*) malloc(N*N*sizeof(float));
// initialize matrices a and b with appropriate values
for (int i = 0; i< N ; i++)
for (int j=0 ; j<N ; j++)
{
a[i*N+j] = 1;
b[i*N+j] = 1;
}
int size = N * N * sizeof(float);
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
int NumThreads = 32;
dim3 dimGrid(DIV_UP(N,NumThreads), DIV_UP(N,NumThreads));
dim3 dimBlock(NumThreads, NumThreads);
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
//measure performance
hipError_t error;
hipDeviceSynchronize();
hipEvent_t start;
error = hipEventCreate(&start);
if (error != hipSuccess)
fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
hipEvent_t stop;
error = hipEventCreate(&stop);
if (error != hipSuccess)
fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
error = hipEventRecord(start, NULL);
if (error != hipSuccess)
fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
int nIter = 10;
for (int j = 0; j < nIter; j++)
{
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
}
// Record the stop event
error = hipEventRecord(stop, NULL);
if (error != hipSuccess)
fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
// Wait for the stop event to complete
error = hipEventSynchronize(stop);
if (error != hipSuccess)
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
float msecTotal = 0.0f;
error = hipEventElapsedTime(&msecTotal, start, stop);
if (error != hipSuccess)
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
// Compute and print the performance
float msecPerMatrixMul = msecTotal / nIter;
printf ("msec %f\n",msecPerMatrixMul);
//end measure performance
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
/*
for (int i = 0; i< N ; i++){
for (int j=0 ; j<N ; j++)
{
printf("%f , ", c[i][j]);
}
printf ("\n");
}
*/
printf("%f, %f \n",c[0],c[N*N-1] );
hipFree(dev_a); hipFree(dev_b); hipFree(dev_c);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#define N 4000
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matrixMult (float *a, float *b, float *c, int width) {
int k = 0;
float sum = 0.0;
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < width && row < width) {
for (k = 0; k < width; k++)
sum += a[row * width + k] * b[k * width + col];
c[row * width + col] = sum;
}
}
int main() {
//float a[N][N], b[N][N], c[N][N];
float *dev_a, *dev_b, *dev_c;
float *a,*b,*c;
a = (float*) malloc(N*N*sizeof(float));
b = (float*) malloc(N*N*sizeof(float));
c = (float*) malloc(N*N*sizeof(float));
// initialize matrices a and b with appropriate values
for (int i = 0; i< N ; i++)
for (int j=0 ; j<N ; j++)
{
a[i*N+j] = 1;
b[i*N+j] = 1;
}
int size = N * N * sizeof(float);
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
int NumThreads = 32;
dim3 dimGrid(DIV_UP(N,NumThreads), DIV_UP(N,NumThreads));
dim3 dimBlock(NumThreads, NumThreads);
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
//measure performance
hipError_t error;
hipDeviceSynchronize();
hipEvent_t start;
error = hipEventCreate(&start);
if (error != hipSuccess)
fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
hipEvent_t stop;
error = hipEventCreate(&stop);
if (error != hipSuccess)
fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
error = hipEventRecord(start, NULL);
if (error != hipSuccess)
fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
int nIter = 10;
for (int j = 0; j < nIter; j++)
{
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
}
// Record the stop event
error = hipEventRecord(stop, NULL);
if (error != hipSuccess)
fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
// Wait for the stop event to complete
error = hipEventSynchronize(stop);
if (error != hipSuccess)
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
float msecTotal = 0.0f;
error = hipEventElapsedTime(&msecTotal, start, stop);
if (error != hipSuccess)
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
// Compute and print the performance
float msecPerMatrixMul = msecTotal / nIter;
printf ("msec %f\n",msecPerMatrixMul);
//end measure performance
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
/*
for (int i = 0; i< N ; i++){
for (int j=0 ; j<N ; j++)
{
printf("%f , ", c[i][j]);
}
printf ("\n");
}
*/
printf("%f, %f \n",c[0],c[N*N-1] );
hipFree(dev_a); hipFree(dev_b); hipFree(dev_c);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPfS_S_i
.globl _Z10matrixMultPfS_S_i
.p2align 8
.type _Z10matrixMultPfS_S_i,@function
_Z10matrixMultPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPfS_S_i, .Lfunc_end0-_Z10matrixMultPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#define N 4000
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matrixMult (float *a, float *b, float *c, int width) {
int k = 0;
float sum = 0.0;
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < width && row < width) {
for (k = 0; k < width; k++)
sum += a[row * width + k] * b[k * width + col];
c[row * width + col] = sum;
}
}
int main() {
//float a[N][N], b[N][N], c[N][N];
float *dev_a, *dev_b, *dev_c;
float *a,*b,*c;
a = (float*) malloc(N*N*sizeof(float));
b = (float*) malloc(N*N*sizeof(float));
c = (float*) malloc(N*N*sizeof(float));
// initialize matrices a and b with appropriate values
for (int i = 0; i< N ; i++)
for (int j=0 ; j<N ; j++)
{
a[i*N+j] = 1;
b[i*N+j] = 1;
}
int size = N * N * sizeof(float);
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
int NumThreads = 32;
dim3 dimGrid(DIV_UP(N,NumThreads), DIV_UP(N,NumThreads));
dim3 dimBlock(NumThreads, NumThreads);
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
//measure performance
hipError_t error;
hipDeviceSynchronize();
hipEvent_t start;
error = hipEventCreate(&start);
if (error != hipSuccess)
fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
hipEvent_t stop;
error = hipEventCreate(&stop);
if (error != hipSuccess)
fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
error = hipEventRecord(start, NULL);
if (error != hipSuccess)
fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
int nIter = 10;
for (int j = 0; j < nIter; j++)
{
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
}
// Record the stop event
error = hipEventRecord(stop, NULL);
if (error != hipSuccess)
fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
// Wait for the stop event to complete
error = hipEventSynchronize(stop);
if (error != hipSuccess)
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
float msecTotal = 0.0f;
error = hipEventElapsedTime(&msecTotal, start, stop);
if (error != hipSuccess)
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
// Compute and print the performance
float msecPerMatrixMul = msecTotal / nIter;
printf ("msec %f\n",msecPerMatrixMul);
//end measure performance
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
/*
for (int i = 0; i< N ; i++){
for (int j=0 ; j<N ; j++)
{
printf("%f , ", c[i][j]);
}
printf ("\n");
}
*/
printf("%f, %f \n",c[0],c[N*N-1] );
hipFree(dev_a); hipFree(dev_b); hipFree(dev_c);
}
|
.text
.file "matmul.hip"
.globl _Z25__device_stub__matrixMultPfS_S_i # -- Begin function _Z25__device_stub__matrixMultPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPfS_S_i,@function
_Z25__device_stub__matrixMultPfS_S_i: # @_Z25__device_stub__matrixMultPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPfS_S_i, .Lfunc_end0-_Z25__device_stub__matrixMultPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $64000000, %edi # imm = 0x3D09000
callq malloc
movq %rax, %r13
movl $64000000, %edi # imm = 0x3D09000
callq malloc
movq %rax, %r12
movl $64000000, %edi # imm = 0x3D09000
callq malloc
movq %rax, 160(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %r13, %rcx
movq %r12, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rcx,%rsi,4) # imm = 0x3F800000
movl $1065353216, (%rdx,%rsi,4) # imm = 0x3F800000
incq %rsi
cmpq $4000, %rsi # imm = 0xFA0
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $16000, %rdx # imm = 0x3E80
addq $16000, %rcx # imm = 0x3E80
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_1
# %bb.4:
movabsq $536870912125, %rbx # imm = 0x7D0000007D
movabsq $137438953504, %r14 # imm = 0x2000000020
leaq 32(%rsp), %rdi
movl $64000000, %esi # imm = 0x3D09000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $64000000, %esi # imm = 0x3D09000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $64000000, %esi # imm = 0x3D09000
callq hipMalloc
movq 32(%rsp), %rdi
movl $64000000, %edx # imm = 0x3D09000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $64000000, %edx # imm = 0x3D09000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
movl $4000, 8(%rsp) # imm = 0xFA0
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10matrixMultPfS_S_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_7
.LBB1_8:
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_9
.LBB1_10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_11
.LBB1_12:
movl $10, %r15d
leaq 80(%rsp), %r12
leaq 64(%rsp), %r13
leaq 56(%rsp), %rbp
leaq 48(%rsp), %rbx
leaq 128(%rsp), %r14
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_13 Depth=1
decl %r15d
je .LBB1_16
.LBB1_13: # =>This Inner Loop Header: Depth=1
movabsq $536870912125, %rdi # imm = 0x7D0000007D
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
movl $4000, 124(%rsp) # imm = 0xFA0
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
movq %r12, %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z10matrixMultPfS_S_i, %edi
movq %r14, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_15
.LBB1_16:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_17
.LBB1_18:
movq 40(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_19
.LBB1_20:
movl $0, 128(%rsp)
movq 8(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_21
.LBB1_22:
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movl $64000000, %edx # imm = 0x3D09000
movq 160(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 63999996(%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.7, %edi
movb $2, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_8
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_12
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_18
.LBB1_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_20
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_22
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPfS_S_i,@object # @_Z10matrixMultPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPfS_S_i
.p2align 3, 0x0
_Z10matrixMultPfS_S_i:
.quad _Z25__device_stub__matrixMultPfS_S_i
.size _Z10matrixMultPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to create start event (error code %s)!\n"
.size .L.str, 47
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to create stop event (error code %s)!\n"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to record start event (error code %s)!\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to record stop event (error code %s)!\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to synchronize on the stop event (error code %s)!\n"
.size .L.str.4, 58
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to get time elapsed between events (error code %s)!\n"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "msec %f\n"
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%f, %f \n"
.size .L.str.7, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixMultPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z10matrixMultPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPfS_S_i
.globl _Z10matrixMultPfS_S_i
.p2align 8
.type _Z10matrixMultPfS_S_i,@function
_Z10matrixMultPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPfS_S_i, .Lfunc_end0-_Z10matrixMultPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000c3ef9_00000000-6_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
.globl _Z10matrixMultPfS_S_i
.type _Z10matrixMultPfS_S_i, @function
_Z10matrixMultPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10matrixMultPfS_S_i, .-_Z10matrixMultPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to create start event (error code %s)!\n"
.align 8
.LC2:
.string "Failed to create stop event (error code %s)!\n"
.align 8
.LC3:
.string "Failed to record start event (error code %s)!\n"
.align 8
.LC4:
.string "Failed to record stop event (error code %s)!\n"
.align 8
.LC5:
.string "Failed to synchronize on the stop event (error code %s)!\n"
.align 8
.LC7:
.string "Failed to get time elapsed between events (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "msec %f\n"
.LC10:
.string "%f, %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $64000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $64000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $64000000, %edi
call malloc@PLT
movq %rax, %r12
movl $16000, %edx
movss .LC0(%rip), %xmm0
.L12:
leaq -16000(%rdx), %rax
.L13:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addq $16000, %rdx
cmpq $64016000, %rdx
jne .L12
leaq 8(%rsp), %rdi
movl $64000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64000000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $125, 48(%rsp)
movl $125, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L15:
call cudaDeviceSynchronize@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
jne .L29
.L16:
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
testl %eax, %eax
jne .L30
.L17:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
jne .L31
.L18:
movl $10, %ebx
jmp .L20
.L28:
movl $4000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
jmp .L15
.L29:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L16
.L30:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L17
.L31:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L19:
subl $1, %ebx
je .L32
.L20:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
movl $4000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPfS_S_iPfS_S_i
jmp .L19
.L32:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
testl %eax, %eax
jne .L33
.L21:
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
testl %eax, %eax
jne .L34
.L22:
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
testl %eax, %eax
jne .L35
.L23:
movss 4(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $64000000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 63999996(%r12), %xmm1
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L21
.L34:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L22
.L35:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L23
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z10matrixMultPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC8:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matmul.hip"
.globl _Z25__device_stub__matrixMultPfS_S_i # -- Begin function _Z25__device_stub__matrixMultPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPfS_S_i,@function
_Z25__device_stub__matrixMultPfS_S_i: # @_Z25__device_stub__matrixMultPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPfS_S_i, .Lfunc_end0-_Z25__device_stub__matrixMultPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $64000000, %edi # imm = 0x3D09000
callq malloc
movq %rax, %r13
movl $64000000, %edi # imm = 0x3D09000
callq malloc
movq %rax, %r12
movl $64000000, %edi # imm = 0x3D09000
callq malloc
movq %rax, 160(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %r13, %rcx
movq %r12, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rcx,%rsi,4) # imm = 0x3F800000
movl $1065353216, (%rdx,%rsi,4) # imm = 0x3F800000
incq %rsi
cmpq $4000, %rsi # imm = 0xFA0
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $16000, %rdx # imm = 0x3E80
addq $16000, %rcx # imm = 0x3E80
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_1
# %bb.4:
movabsq $536870912125, %rbx # imm = 0x7D0000007D
movabsq $137438953504, %r14 # imm = 0x2000000020
leaq 32(%rsp), %rdi
movl $64000000, %esi # imm = 0x3D09000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $64000000, %esi # imm = 0x3D09000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $64000000, %esi # imm = 0x3D09000
callq hipMalloc
movq 32(%rsp), %rdi
movl $64000000, %edx # imm = 0x3D09000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $64000000, %edx # imm = 0x3D09000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
movl $4000, 8(%rsp) # imm = 0xFA0
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10matrixMultPfS_S_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_7
.LBB1_8:
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_9
.LBB1_10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_11
.LBB1_12:
movl $10, %r15d
leaq 80(%rsp), %r12
leaq 64(%rsp), %r13
leaq 56(%rsp), %rbp
leaq 48(%rsp), %rbx
leaq 128(%rsp), %r14
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_13 Depth=1
decl %r15d
je .LBB1_16
.LBB1_13: # =>This Inner Loop Header: Depth=1
movabsq $536870912125, %rdi # imm = 0x7D0000007D
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
movl $4000, 124(%rsp) # imm = 0xFA0
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
movq %r12, %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z10matrixMultPfS_S_i, %edi
movq %r14, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_15
.LBB1_16:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_17
.LBB1_18:
movq 40(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_19
.LBB1_20:
movl $0, 128(%rsp)
movq 8(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_21
.LBB1_22:
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movl $64000000, %edx # imm = 0x3D09000
movq 160(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 63999996(%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.7, %edi
movb $2, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_8
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_12
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_18
.LBB1_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_20
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_22
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPfS_S_i,@object # @_Z10matrixMultPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPfS_S_i
.p2align 3, 0x0
_Z10matrixMultPfS_S_i:
.quad _Z25__device_stub__matrixMultPfS_S_i
.size _Z10matrixMultPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to create start event (error code %s)!\n"
.size .L.str, 47
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to create stop event (error code %s)!\n"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to record start event (error code %s)!\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to record stop event (error code %s)!\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to synchronize on the stop event (error code %s)!\n"
.size .L.str.4, 58
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to get time elapsed between events (error code %s)!\n"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "msec %f\n"
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%f, %f \n"
.size .L.str.7, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixMultPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
// MASK SIZE
#define MASK_WIDTH 5
// MASK RADIO
#define MASK_R (MASK_WIDTH-1)/2
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
// SIZE OF TILE
#define TILE_WIDTH 32
// SIZE OF SHARE MATRIX
#define SHARED_SIZE (MASK_WIDTH-1 + TILE_WIDTH)
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
__global__ void smoothing_kernel(PPMImage *d_image, PPMImage *d_image_copy) {
// Creating variables
int i, j, row, col;
int total_red = 0, total_blue = 0, total_green = 0;
int index_dst_y, index_dst_x, index_src_y, index_src_x;
// Get Row and COl
row = blockIdx.y * TILE_WIDTH + threadIdx.y;
col = blockIdx.x * TILE_WIDTH + threadIdx.x;
// Create Shared block of data
__shared__ PPMPixel shared_image_data[SHARED_SIZE*SHARED_SIZE];
// Filling the shared variable with a two-step for.
// first step fill the data with index inside the blocks dim
// -----------------
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// | | | | | | | | |
// -----------------
// Second step fill the data with index outside the blocks dim
// -----------------
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// |x|x|x|x|x|x|x|x|
// -----------------
for (i = 0; i <= TILE_WIDTH * TILE_WIDTH; i = i + TILE_WIDTH * TILE_WIDTH)
{
// Get indexs of dst matrix
index_dst_y = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) / SHARED_SIZE;
index_dst_x = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) % SHARED_SIZE;
// Get indexs of destination matrix
index_src_y = (blockIdx.y * TILE_WIDTH) + index_dst_y - MASK_R;
index_src_x = (blockIdx.x * TILE_WIDTH) + index_dst_x - MASK_R;
//Work only if dst geral index stay into shared matrix size
if (index_dst_y * SHARED_SIZE + index_dst_x < (SHARED_SIZE*SHARED_SIZE)) {
// if src index stay into image save images values else save 0
if (index_src_y >= 0 && index_src_y < d_image->y && index_src_x >= 0 && index_src_x < d_image->x){
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].red;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].blue;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].green;
}
else{
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = 0;
}
}
}
// sync threads
__syncthreads();
// if row and col stay into image proceed with convolution
if (row < d_image->y && col < d_image->x){
for (i = 0; i < MASK_WIDTH; i++){
for (j = 0; j < MASK_WIDTH; j++) {
total_red += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].red;
total_blue += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].blue;
total_green += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].green;
}
}
// Save data of convolution into devise image
d_image->data[(row * d_image->x) + col].red = total_red / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
void smoothing_GPU(PPMImage *image, PPMImage *image_copy) {
unsigned int rows, cols, img_size;
PPMImage *d_image, *d_image_copy;
PPMPixel *d_pixels, *d_pixels_copy, *new_pixels;
// Get data
cols = image->x;
rows = image->y;
img_size = cols * rows;
// Alloc structure to devise
cudaMalloc((void **)&d_image, sizeof(PPMImage));
cudaMalloc((void **)&d_image_copy, sizeof(PPMImage));
// Alloc image to devise
cudaMalloc((void **)&d_pixels, sizeof(PPMPixel) * img_size);
cudaMalloc((void **)&d_pixels_copy, sizeof(PPMPixel) * img_size);
// cpy stucture to devise
cudaMemcpy(d_image, image, sizeof(PPMImage), cudaMemcpyHostToDevice);
cudaMemcpy(d_pixels, image->data, sizeof(PPMPixel) * img_size, cudaMemcpyHostToDevice);
cudaMemcpy(&(d_image->data), &d_pixels, sizeof(PPMPixel *), cudaMemcpyHostToDevice);
cudaMemcpy(d_image_copy, image, sizeof(PPMImage), cudaMemcpyHostToDevice);
cudaMemcpy(d_pixels_copy, image->data, sizeof(PPMPixel) * img_size, cudaMemcpyHostToDevice);
cudaMemcpy(&(d_image_copy->data), &d_pixels_copy, sizeof(PPMPixel *), cudaMemcpyHostToDevice);
dim3 dimGrid(ceil((float)cols / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
// Call function
smoothing_kernel<<<dimGrid, dimBlock>>>(d_image, d_image_copy);
new_pixels = (PPMPixel *) malloc(img_size * sizeof(PPMPixel));
// Copy result to local array
cudaMemcpy(image, d_image, sizeof(PPMImage), cudaMemcpyDeviceToHost);
cudaMemcpy(new_pixels, d_pixels, sizeof(PPMPixel) * img_size, cudaMemcpyDeviceToHost);
image->data = new_pixels;
//Free memory
cudaFree(d_image);
cudaFree(d_image_copy);
cudaFree(d_pixels);
cudaFree(d_pixels_copy);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
//int i;
char *filename = argv[1]; //Recebendo o arquivo!;
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
smoothing_GPU(image_output, image);
//t_end = rtclock();
writePPM(image_output);
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
}
|
code for sm_80
Function : _Z16smoothing_kernelP8PPMImageS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x3b0 ; /* 0x0000037000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0050*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0060*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002500 */
/*0070*/ IMAD R3, R9, 0x20, R6 ; /* 0x0000002009037824 */
/* 0x001fc800078e0206 */
/*0080*/ IMAD.WIDE.U32 R4, R3, 0x38e38e39, RZ ; /* 0x38e38e3903047825 */
/* 0x000fca00078e00ff */
/*0090*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*00a0*/ IMAD R8, R5.reuse, -0x24, R3 ; /* 0xffffffdc05087824 */
/* 0x040fe400078e0203 */
/*00b0*/ IMAD R4, R0, 0x20, R5 ; /* 0x0000002000047824 */
/* 0x002fe400078e0205 */
/*00c0*/ IMAD R2, R5, 0x24, R8 ; /* 0x0000002405027824 */
/* 0x000fca00078e0208 */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R2.reuse, 0x50f, PT ; /* 0x0000050f0200780c */
/* 0x040fe20003f04070 */
/*00e0*/ IMAD R2, R2, 0x3, RZ ; /* 0x0000000302027824 */
/* 0x000fd800078e02ff */
/*00f0*/ @P0 BRA 0x3a0 ; /* 0x000002a000000947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R12, R4, -0x2, RZ ; /* 0xfffffffe040c7810 */
/* 0x004fe20007ffe0ff */
/*0110*/ UMOV UR6, 0x1 ; /* 0x0000000100067882 */
/* 0x000fe20000000000 */
/*0120*/ IMAD R8, R7, 0x20, R8 ; /* 0x0000002007087824 */
/* 0x000fe200078e0208 */
/*0130*/ ULDC.64 UR4, c[0x2][0x0] ; /* 0x0080000000047ab9 */
/* 0x000fe20000000a00 */
/*0140*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f26270 */
/*0150*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe20000000a00 */
/*0160*/ BSSY B1, 0x230 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*0170*/ UIMAD.WIDE.U32 UR4, UR6, UR8, UR4 ; /* 0x00000008060472a5 */
/* 0x000fe2000f8e0004 */
/*0180*/ IADD3 R8, R8, -0x2, RZ ; /* 0xfffffffe08087810 */
/* 0x000fe20007ffe0ff */
/*0190*/ UIMAD UR6, UR6, UR9, URZ ; /* 0x00000009060672a4 */
/* 0x000fe2000f8e023f */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*01b0*/ UIADD3 UR6, UR5, UR6, URZ ; /* 0x0000000605067290 */
/* 0x000fe2000fffe03f */
/*01c0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe4000f8e00ff */
/*01d0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fc6000f8e00ff */
/*01e0*/ IMAD.U32 R5, RZ, RZ, UR6 ; /* 0x00000006ff057e24 */
/* 0x000fe2000f8e00ff */
/*01f0*/ @!P1 BRA 0x220 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0200*/ LDG.E R11, [R4.64] ; /* 0x0000000a040b7981 */
/* 0x000ea4000c1e1900 */
/*0210*/ ISETP.LT.AND P0, PT, R12, R11, PT ; /* 0x0000000b0c00720c */
/* 0x004fd00003f01270 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.LT.OR P0, PT, R8, RZ, !P0 ; /* 0x000000ff0800720c */
/* 0x000fe20004701670 */
/*0240*/ BSSY B1, 0x2b0 ; /* 0x0000006000017945 */
/* 0x000fd80003800000 */
/*0250*/ @P0 BRA 0x2a0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0260*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc0a040d7981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x004fda0003f06270 */
/*0280*/ @!P0 BREAK B1 ; /* 0x0000000000018942 */
/* 0x000fe20003800000 */
/*0290*/ @!P0 BRA 0x2f0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02b0*/ STS.U8 [R2], RZ ; /* 0x000000ff02007388 */
/* 0x0001e80000000000 */
/*02c0*/ STS.U8 [R2+0x2], RZ ; /* 0x000002ff02007388 */
/* 0x0001e80000000000 */
/*02d0*/ STS.U8 [R2+0x1], RZ ; /* 0x000001ff02007388 */
/* 0x0001e20000000000 */
/*02e0*/ BRA 0x3a0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe400078e00ff */
/*0300*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fca00078e00ff */
/*0310*/ LDG.E.64 R4, [R10.64+0x8] ; /* 0x0000080a0a047981 */
/* 0x000ea2000c1e1b00 */
/*0320*/ IMAD R13, R12, R13, R8 ; /* 0x0000000d0c0d7224 */
/* 0x000fc800078e0208 */
/*0330*/ IMAD.WIDE R4, R13, 0x3, R4 ; /* 0x000000030d047825 */
/* 0x004fca00078e0204 */
/*0340*/ LDG.E.U8 R13, [R4.64] ; /* 0x0000000a040d7981 */
/* 0x000ea8000c1e1100 */
/*0350*/ LDG.E.U8 R15, [R4.64+0x2] ; /* 0x0000020a040f7981 */
/* 0x000ee8000c1e1100 */
/*0360*/ LDG.E.U8 R17, [R4.64+0x1] ; /* 0x0000010a04117981 */
/* 0x000f28000c1e1100 */
/*0370*/ STS.U8 [R2], R13 ; /* 0x0000000d02007388 */
/* 0x0041e80000000000 */
/*0380*/ STS.U8 [R2+0x2], R15 ; /* 0x0000020f02007388 */
/* 0x0081e80000000000 */
/*0390*/ STS.U8 [R2+0x1], R17 ; /* 0x0000011102007388 */
/* 0x0101e40000000000 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*03b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*03c0*/ IADD3 R3, R3, 0x400, RZ ; /* 0x0000040003037810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ BSSY B0, 0x700 ; /* 0x0000032000007945 */
/* 0x000fe80003800000 */
/*03e0*/ IMAD.WIDE.U32 R4, R3, 0x38e38e39, RZ ; /* 0x38e38e3903047825 */
/* 0x000fca00078e00ff */
/*03f0*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*0400*/ IMAD R4, R5, -0x24, R3 ; /* 0xffffffdc05047824 */
/* 0x000fc800078e0203 */
/*0410*/ IMAD R3, R5, 0x24, R4.reuse ; /* 0x0000002405037824 */
/* 0x100fe400078e0204 */
/*0420*/ IMAD R8, R7, 0x20, R4 ; /* 0x0000002007087824 */
/* 0x000fc600078e0204 */
/*0430*/ ISETP.GT.U32.AND P0, PT, R3, 0x50f, PT ; /* 0x0000050f0300780c */
/* 0x000fe20003f04070 */
/*0440*/ IMAD R3, R0, 0x20, R5 ; /* 0x0000002000037824 */
/* 0x000fd800078e0205 */
/*0450*/ @P0 BRA 0x6f0 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R3, R3, -0x2, RZ ; /* 0xfffffffe03037810 */
/* 0x000fe20007ffe0ff */
/*0470*/ UMOV UR8, 0x1 ; /* 0x0000000100087882 */
/* 0x000fe20000000000 */
/*0480*/ BSSY B1, 0x580 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0490*/ ULDC.64 UR4, c[0x2][0x0] ; /* 0x0080000000047ab9 */
/* 0x000fe20000000a00 */
/*04a0*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f26270 */
/*04b0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*04c0*/ IADD3 R8, R8, -0x2, RZ ; /* 0xfffffffe08087810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ UIMAD.WIDE.U32 UR4, UR8, UR6, UR4 ; /* 0x00000006080472a5 */
/* 0x000fe2000f8e0004 */
/*04e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*04f0*/ UIMAD UR7, UR8, UR7, URZ ; /* 0x00000007080772a4 */
/* 0x000fc8000f8e023f */
/*0500*/ UIADD3 UR7, UR5, UR7, URZ ; /* 0x0000000705077290 */
/* 0x000fe2000fffe03f */
/*0510*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe4000f8e00ff */
/*0520*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fc6000f8e00ff */
/*0530*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*0540*/ @!P1 BRA 0x570 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E R10, [R4.64] ; /* 0x0000000a040a7981 */
/* 0x000ea4000c1e1900 */
/*0560*/ ISETP.LT.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x004fd00003f01270 */
/*0570*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.LT.OR P0, PT, R8, RZ, !P0 ; /* 0x000000ff0800720c */
/* 0x000fe20004701670 */
/*0590*/ BSSY B1, 0x600 ; /* 0x0000006000017945 */
/* 0x000fd80003800000 */
/*05a0*/ @P0 BRA 0x5f0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*05b0*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc0a040d7981 */
/* 0x001ea4000c1e1900 */
/*05c0*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x004fda0003f06270 */
/*05d0*/ @!P0 BREAK B1 ; /* 0x0000000000018942 */
/* 0x000fe20003800000 */
/*05e0*/ @!P0 BRA 0x640 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*05f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0600*/ STS.U8 [R2+0xc00], RZ ; /* 0x000c00ff02007388 */
/* 0x0003e80000000000 */
/*0610*/ STS.U8 [R2+0xc02], RZ ; /* 0x000c02ff02007388 */
/* 0x0003e80000000000 */
/*0620*/ STS.U8 [R2+0xc01], RZ ; /* 0x000c01ff02007388 */
/* 0x0003e20000000000 */
/*0630*/ BRA 0x6f0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe400078e00ff */
/*0650*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fca00078e00ff */
/*0660*/ LDG.E.64 R4, [R10.64+0x8] ; /* 0x0000080a0a047981 */
/* 0x000ea2000c1e1b00 */
/*0670*/ IMAD R3, R13, R3, R8 ; /* 0x000000030d037224 */
/* 0x000fc800078e0208 */
/*0680*/ IMAD.WIDE R4, R3, 0x3, R4 ; /* 0x0000000303047825 */
/* 0x004fca00078e0204 */
/*0690*/ LDG.E.U8 R3, [R4.64] ; /* 0x0000000a04037981 */
/* 0x000ea8000c1e1100 */
/*06a0*/ LDG.E.U8 R13, [R4.64+0x2] ; /* 0x0000020a040d7981 */
/* 0x000ee8000c1e1100 */
/*06b0*/ LDG.E.U8 R15, [R4.64+0x1] ; /* 0x0000010a040f7981 */
/* 0x000f28000c1e1100 */
/*06c0*/ STS.U8 [R2+0xc00], R3 ; /* 0x000c000302007388 */
/* 0x0041e80000000000 */
/*06d0*/ STS.U8 [R2+0xc02], R13 ; /* 0x000c020d02007388 */
/* 0x0081e80000000000 */
/*06e0*/ STS.U8 [R2+0xc01], R15 ; /* 0x000c010f02007388 */
/* 0x0101e40000000000 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0720*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fc400078e00ff */
/*0730*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fc600078e00ff */
/*0740*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0750*/ LDG.E R5, [R4.64+0x4] ; /* 0x0000040a04057981 */
/* 0x000ea2000c1e1900 */
/*0760*/ IMAD R0, R0, 0x20, R9 ; /* 0x0000002000007824 */
/* 0x000fe200078e0209 */
/*0770*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0780*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0790*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x003fc8000f8e00ff */
/*07a0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*07b0*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f06270 */
/*07c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*07d0*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0a02087981 */
/* 0x000ea2000c1e1900 */
/*07e0*/ IMAD R7, R7, 0x20, R6 ; /* 0x0000002007077824 */
/* 0x000fca00078e0206 */
/*07f0*/ ISETP.GE.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x004fda0003f06270 */
/*0800*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0810*/ LDG.E.64 R4, [R2.64+0x4] ; /* 0x0000040a02047981 */
/* 0x000ea2000c1e1b00 */
/*0820*/ IMAD R6, R9, 0x24, R6 ; /* 0x0000002409067824 */
/* 0x000fc800078e0206 */
/*0830*/ IMAD R6, R6, 0x3, RZ ; /* 0x0000000306067824 */
/* 0x000fca00078e02ff */
/*0840*/ LDS.U8 R19, [R6] ; /* 0x0000000006137984 */
/* 0x000fe80000000000 */
/*0850*/ LDS.U8 R20, [R6+0x6c] ; /* 0x00006c0006147984 */
/* 0x000fe80000000000 */
/*0860*/ LDS.U8 R23, [R6+0xd8] ; /* 0x0000d80006177984 */
/* 0x000e280000000000 */
/*0870*/ LDS.U8 R24, [R6+0x144] ; /* 0x0001440006187984 */
/* 0x000fe80000000000 */
/*0880*/ LDS.U8 R25, [R6+0x1b0] ; /* 0x0001b00006197984 */
/* 0x000e680000000000 */
/*0890*/ LDS.U8 R21, [R6+0x3] ; /* 0x0000030006157984 */
/* 0x000fe80000000000 */
/*08a0*/ LDS.U8 R22, [R6+0x6f] ; /* 0x00006f0006167984 */
/* 0x000ee80000000000 */
/*08b0*/ LDS.U8 R17, [R6+0xdb] ; /* 0x0000db0006117984 */
/* 0x000fe80000000000 */
/*08c0*/ LDS.U8 R18, [R6+0x147] ; /* 0x0001470006127984 */
/* 0x000f280000000000 */
/*08d0*/ LDS.U8 R9, [R6+0x1b3] ; /* 0x0001b30006097984 */
/* 0x000fe80000000000 */
/*08e0*/ LDS.U8 R10, [R6+0x6] ; /* 0x00000600060a7984 */
/* 0x000f680000000000 */
/*08f0*/ LDS.U8 R11, [R6+0x72] ; /* 0x00007200060b7984 */
/* 0x000fe80000000000 */
/*0900*/ LDS.U8 R12, [R6+0xde] ; /* 0x0000de00060c7984 */
/* 0x000f620000000000 */
/*0910*/ IADD3 R23, R23, R19, R20 ; /* 0x0000001317177210 */
/* 0x001fc60007ffe014 */
/*0920*/ LDS.U8 R13, [R6+0x14a] ; /* 0x00014a00060d7984 */
/* 0x000fe80000000000 */
/*0930*/ LDS.U8 R14, [R6+0x1b6] ; /* 0x0001b600060e7984 */
/* 0x000e220000000000 */
/*0940*/ IADD3 R25, R25, R23, R24 ; /* 0x0000001719197210 */
/* 0x002fc60007ffe018 */
/*0950*/ LDS.U8 R15, [R6+0x9] ; /* 0x00000900060f7984 */
/* 0x000fe80000000000 */
/*0960*/ LDS.U8 R16, [R6+0x75] ; /* 0x0000750006107984 */
/* 0x000e620000000000 */
/*0970*/ IADD3 R25, R22, R25, R21 ; /* 0x0000001916197210 */
/* 0x008fc60007ffe015 */
/*0980*/ LDS.U8 R19, [R6+0xe1] ; /* 0x0000e10006137984 */
/* 0x000fe80000000000 */
/*0990*/ LDS.U8 R20, [R6+0x14d] ; /* 0x00014d0006147984 */
/* 0x000ee20000000000 */
/*09a0*/ IADD3 R25, R18, R25, R17 ; /* 0x0000001912197210 */
/* 0x010fc60007ffe011 */
/*09b0*/ LDS.U8 R24, [R6+0x1b9] ; /* 0x0001b90006187984 */
/* 0x000fe80000000000 */
/*09c0*/ LDS.U8 R23, [R6+0xc] ; /* 0x00000c0006177984 */
/* 0x000f220000000000 */
/*09d0*/ IADD3 R9, R10, R25, R9 ; /* 0x000000190a097210 */
/* 0x020fc60007ffe009 */
/*09e0*/ LDS.U8 R22, [R6+0x78] ; /* 0x0000780006167984 */
/* 0x000fe80000000000 */
/*09f0*/ LDS.U8 R21, [R6+0xe4] ; /* 0x0000e40006157984 */
/* 0x000f620000000000 */
/*0a00*/ IADD3 R9, R12, R9, R11 ; /* 0x000000090c097210 */
/* 0x000fe20007ffe00b */
/*0a10*/ IMAD R11, R0, R8, R7 ; /* 0x00000008000b7224 */
/* 0x000fe400078e0207 */
/*0a20*/ LDS.U8 R18, [R6+0x150] ; /* 0x0001500006127984 */
/* 0x000fe80000000000 */
/*0a30*/ LDS.U8 R17, [R6+0x1bc] ; /* 0x0001bc0006117984 */
/* 0x000f620000000000 */
/*0a40*/ IADD3 R9, R14, R9, R13 ; /* 0x000000090e097210 */
/* 0x001fc60007ffe00d */
/*0a50*/ LDS.U8 R25, [R6+0x1b2] ; /* 0x0001b20006197984 */
/* 0x000fe20000000000 */
/*0a60*/ IADD3 R9, R16, R9, R15 ; /* 0x0000000910097210 */
/* 0x002fc60007ffe00f */
/*0a70*/ LDS.U8 R12, [R6+0xe0] ; /* 0x0000e000060c7984 */
/* 0x000fe80000000000 */
/*0a80*/ LDS.U8 R13, [R6+0x14c] ; /* 0x00014c00060d7984 */
/* 0x000fe20000000000 */
/*0a90*/ IADD3 R9, R20, R9, R19 ; /* 0x0000000914097210 */
/* 0x008fc60007ffe013 */
/*0aa0*/ LDS.U8 R14, [R6+0x1b8] ; /* 0x0001b800060e7984 */
/* 0x000fe80000000000 */
/*0ab0*/ LDS.U8 R19, [R6+0x2] ; /* 0x0000020006137984 */
/* 0x000fe20000000000 */
/*0ac0*/ IADD3 R9, R23, R9, R24 ; /* 0x0000000917097210 */
/* 0x010fc60007ffe018 */
/*0ad0*/ LDS.U8 R20, [R6+0x6e] ; /* 0x00006e0006147984 */
/* 0x000fe80000000000 */
/*0ae0*/ LDS.U8 R23, [R6+0xda] ; /* 0x0000da0006177984 */
/* 0x000e220000000000 */
/*0af0*/ IADD3 R9, R21, R9, R22 ; /* 0x0000000915097210 */
/* 0x020fc60007ffe016 */
/*0b00*/ LDS.U8 R24, [R6+0x146] ; /* 0x0001460006187984 */
/* 0x000e680000000000 */
/*0b10*/ LDS.U8 R21, [R6+0x5] ; /* 0x0000050006157984 */
/* 0x000fe20000000000 */
/*0b20*/ IADD3 R9, R17, R9, R18 ; /* 0x0000000911097210 */
/* 0x000fc60007ffe012 */
/*0b30*/ LDS.U8 R22, [R6+0x71] ; /* 0x0000710006167984 */
/* 0x000ee40000000000 */
/*0b40*/ IMAD.HI R9, R9, 0x51eb851f, RZ ; /* 0x51eb851f09097827 */
/* 0x000fe400078e02ff */
/*0b50*/ LDS.U8 R17, [R6+0xdd] ; /* 0x0000dd0006117984 */
/* 0x000fe60000000000 */
/*0b60*/ SHF.R.U32.HI R8, RZ, 0x1f, R9 ; /* 0x0000001fff087819 */
/* 0x000fe20000011609 */
/*0b70*/ LDS.U8 R18, [R6+0x149] ; /* 0x0001490006127984 */
/* 0x000f260000000000 */
/*0b80*/ LEA.HI R9, R9, R8, RZ, 0x1d ; /* 0x0000000809097211 */
/* 0x000fe200078fe8ff */
/*0b90*/ LDS.U8 R15, [R6+0xb] ; /* 0x00000b00060f7984 */
/* 0x000fe80000000000 */
/*0ba0*/ LDS.U8 R16, [R6+0x77] ; /* 0x0000770006107984 */
/* 0x000fe20000000000 */
/*0bb0*/ IMAD.WIDE R10, R11, 0x3, R4 ; /* 0x000000030b0a7825 */
/* 0x004fca00078e0204 */
/*0bc0*/ STG.E.U8 [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x000fe8000c10110a */
/*0bd0*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0a02087981 */
/* 0x000ea8000c1e1900 */
/*0be0*/ LDG.E.64 R4, [R2.64+0x4] ; /* 0x0000040a02047981 */
/* 0x000f62000c1e1b00 */
/*0bf0*/ IADD3 R23, R23, R19, R20 ; /* 0x0000001317177210 */
/* 0x001fc60007ffe014 */
/*0c00*/ LDS.U8 R9, [R6+0x1b5] ; /* 0x0001b50006097984 */
/* 0x000fe20000000000 */
/*0c10*/ IADD3 R25, R25, R23, R24 ; /* 0x0000001719197210 */
/* 0x002fc60007ffe018 */
/*0c20*/ LDS.U8 R10, [R6+0x8] ; /* 0x00000800060a7984 */
/* 0x000e220000000000 */
/*0c30*/ IADD3 R25, R22, R25, R21 ; /* 0x0000001916197210 */
/* 0x008fc60007ffe015 */
/*0c40*/ LDS.U8 R11, [R6+0x74] ; /* 0x00007400060b7984 */
/* 0x000e620000000000 */
/*0c50*/ IADD3 R25, R18, R25, R17 ; /* 0x0000001912197210 */
/* 0x010fc60007ffe011 */
/*0c60*/ LDS.U8 R19, [R6+0xe3] ; /* 0x0000e30006137984 */
/* 0x000fe80000000000 */
/*0c70*/ LDS.U8 R20, [R6+0x14f] ; /* 0x00014f0006147984 */
/* 0x000ee80000000000 */
/*0c80*/ LDS.U8 R24, [R6+0x1bb] ; /* 0x0001bb0006187984 */
/* 0x000fe80000000000 */
/*0c90*/ LDS.U8 R23, [R6+0xe] ; /* 0x00000e0006177984 */
/* 0x000f280000000000 */
/*0ca0*/ LDS.U8 R22, [R6+0x7a] ; /* 0x00007a0006167984 */
/* 0x000fe80000000000 */
/*0cb0*/ LDS.U8 R21, [R6+0xe6] ; /* 0x0000e60006157984 */
/* 0x000f280000000000 */
/*0cc0*/ LDS.U8 R18, [R6+0x152] ; /* 0x0001520006127984 */
/* 0x000fe80000000000 */
/*0cd0*/ LDS.U8 R17, [R6+0x1be] ; /* 0x0001be0006117984 */
/* 0x000f220000000000 */
/*0ce0*/ IADD3 R9, R10, R25, R9 ; /* 0x000000190a097210 */
/* 0x001fc80007ffe009 */
/*0cf0*/ IADD3 R9, R12, R9, R11 ; /* 0x000000090c097210 */
/* 0x002fe40007ffe00b */
/*0d00*/ LDS.U8 R12, [R6+0x1b7] ; /* 0x0001b700060c7984 */
/* 0x000fe40000000000 */
/*0d10*/ IADD3 R9, R14, R9, R13 ; /* 0x000000090e097210 */
/* 0x000fe40007ffe00d */
/*0d20*/ LDS.U8 R13, [R6+0xdc] ; /* 0x0000dc00060d7984 */
/* 0x000fe40000000000 */
/*0d30*/ IADD3 R9, R16, R9, R15 ; /* 0x0000000910097210 */
/* 0x000fe40007ffe00f */
/*0d40*/ LDS.U8 R15, [R6+0x1] ; /* 0x00000100060f7984 */
/* 0x000fe40000000000 */
/*0d50*/ IADD3 R9, R20, R9, R19 ; /* 0x0000000914097210 */
/* 0x008fc40007ffe013 */
/*0d60*/ LDS.U8 R16, [R6+0x6d] ; /* 0x00006d0006107984 */
/* 0x000fe40000000000 */
/*0d70*/ IADD3 R9, R23, R9, R24 ; /* 0x0000000917097210 */
/* 0x010fe40007ffe018 */
/*0d80*/ LDS.U8 R19, [R6+0x1b1] ; /* 0x0001b10006137984 */
/* 0x000fe80000000000 */
/*0d90*/ LDS.U8 R20, [R6+0x4] ; /* 0x0000040006147984 */
/* 0x000fe20000000000 */
/*0da0*/ IADD3 R9, R21, R9, R22 ; /* 0x0000000915097210 */
/* 0x000fc60007ffe016 */
/*0db0*/ LDS.U8 R21, [R6+0x70] ; /* 0x0000700006157984 */
/* 0x000fe80000000000 */
/*0dc0*/ LDS.U8 R14, [R6+0x148] ; /* 0x00014800060e7984 */
/* 0x000fe20000000000 */
/*0dd0*/ IADD3 R9, R17, R9, R18 ; /* 0x0000000911097210 */
/* 0x000fc60007ffe012 */
/*0de0*/ LDS.U8 R17, [R6+0xd9] ; /* 0x0000d90006117984 */
/* 0x000e240000000000 */
/*0df0*/ IMAD.HI R9, R9, 0x51eb851f, RZ ; /* 0x51eb851f09097827 */
/* 0x000fe400078e02ff */
/*0e00*/ LDS.U8 R18, [R6+0x145] ; /* 0x0001450006127984 */
/* 0x000e660000000000 */
/*0e10*/ SHF.R.U32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fe20000011609 */
/*0e20*/ LDS.U8 R22, [R6+0xe5] ; /* 0x0000e50006167984 */
/* 0x000fe60000000000 */
/*0e30*/ LEA.HI R9, R9, R10, RZ, 0x1d ; /* 0x0000000a09097211 */
/* 0x000fe200078fe8ff */
/*0e40*/ LDS.U8 R23, [R6+0x1bd] ; /* 0x0001bd0006177984 */
/* 0x000fe20000000000 */
/*0e50*/ IMAD R11, R0, R8, R7 ; /* 0x00000008000b7224 */
/* 0x004fc800078e0207 */
/*0e60*/ IMAD.WIDE R10, R11, 0x3, R4 ; /* 0x000000030b0a7825 */
/* 0x020fca00078e0204 */
/*0e70*/ STG.E.U8 [R10.64+0x2], R9 ; /* 0x000002090a007986 */
/* 0x000fe8000c10110a */
/*0e80*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0a02087981 */
/* 0x0004e8000c1e1900 */
/*0e90*/ LDG.E.64 R4, [R2.64+0x4] ; /* 0x0000040a02047981 */
/* 0x000522000c1e1b00 */
/*0ea0*/ IADD3 R17, R17, R15, R16 ; /* 0x0000000f11117210 */
/* 0x001fc60007ffe010 */
/*0eb0*/ LDS.U8 R9, [R6+0x1b4] ; /* 0x0001b40006097984 */
/* 0x000fe20000000000 */
/*0ec0*/ IADD3 R19, R19, R17, R18 ; /* 0x0000001113137210 */
/* 0x002fc60007ffe012 */
/*0ed0*/ LDS.U8 R10, [R6+0xdf] ; /* 0x0000df00060a7984 */
/* 0x000fe20000000000 */
/*0ee0*/ IADD3 R21, R21, R19, R20 ; /* 0x0000001315157210 */
/* 0x000fc60007ffe014 */
/*0ef0*/ LDS.U8 R2, [R6+0x7] ; /* 0x0000070006027984 */
/* 0x004e220000000000 */
/*0f00*/ IADD3 R14, R14, R21, R13 ; /* 0x000000150e0e7210 */
/* 0x000fc60007ffe00d */
/*0f10*/ LDS.U8 R3, [R6+0x73] ; /* 0x0000730006037984 */
/* 0x000e680000000000 */
/*0f20*/ LDS.U8 R11, [R6+0x14b] ; /* 0x00014b00060b7984 */
/* 0x000ea80000000000 */
/*0f30*/ LDS.U8 R16, [R6+0xa] ; /* 0x00000a0006107984 */
/* 0x000fe80000000000 */
/*0f40*/ LDS.U8 R15, [R6+0x76] ; /* 0x00007600060f7984 */
/* 0x000f680000000000 */
/*0f50*/ LDS.U8 R18, [R6+0xe2] ; /* 0x0000e20006127984 */
/* 0x000fe80000000000 */
/*0f60*/ LDS.U8 R17, [R6+0x14e] ; /* 0x00014e0006117984 */
/* 0x000f680000000000 */
/*0f70*/ LDS.U8 R20, [R6+0x1ba] ; /* 0x0001ba0006147984 */
/* 0x000fe80000000000 */
/*0f80*/ LDS.U8 R19, [R6+0xd] ; /* 0x00000d0006137984 */
/* 0x000f680000000000 */
/*0f90*/ LDS.U8 R21, [R6+0x79] ; /* 0x0000790006157984 */
/* 0x000f680000000000 */
/*0fa0*/ LDS.U8 R13, [R6+0x151] ; /* 0x00015100060d7984 */
/* 0x000f620000000000 */
/*0fb0*/ IADD3 R2, R2, R14, R9 ; /* 0x0000000e02027210 */
/* 0x001fc80007ffe009 */
/*0fc0*/ IADD3 R2, R10, R2, R3 ; /* 0x000000020a027210 */
/* 0x002fc80007ffe003 */
/*0fd0*/ IADD3 R2, R12, R2, R11 ; /* 0x000000020c027210 */
/* 0x004fc80007ffe00b */
/*0fe0*/ IADD3 R2, R15, R2, R16 ; /* 0x000000020f027210 */
/* 0x020fc80007ffe010 */
/*0ff0*/ IADD3 R2, R17, R2, R18 ; /* 0x0000000211027210 */
/* 0x000fc80007ffe012 */
/*1000*/ IADD3 R2, R19, R2, R20 ; /* 0x0000000213027210 */
/* 0x000fc80007ffe014 */
/*1010*/ IADD3 R2, R22, R2, R21 ; /* 0x0000000216027210 */
/* 0x000fc80007ffe015 */
/*1020*/ IADD3 R2, R23, R2, R13 ; /* 0x0000000217027210 */
/* 0x000fca0007ffe00d */
/*1030*/ IMAD.HI R2, R2, 0x51eb851f, RZ ; /* 0x51eb851f02027827 */
/* 0x000fca00078e02ff */
/*1040*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*1050*/ LEA.HI R3, R2, R3, RZ, 0x1d ; /* 0x0000000302037211 */
/* 0x000fe200078fe8ff */
/*1060*/ IMAD R7, R0, R8, R7 ; /* 0x0000000800077224 */
/* 0x008fc800078e0207 */
/*1070*/ IMAD.WIDE R4, R7, 0x3, R4 ; /* 0x0000000307047825 */
/* 0x010fca00078e0204 */
/*1080*/ STG.E.U8 [R4.64+0x1], R3 ; /* 0x0000010304007986 */
/* 0x000fe2000c10110a */
/*1090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10a0*/ BRA 0x10a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
// MASK SIZE
#define MASK_WIDTH 5
// MASK RADIO
#define MASK_R (MASK_WIDTH-1)/2
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
// SIZE OF TILE
#define TILE_WIDTH 32
// SIZE OF SHARE MATRIX
#define SHARED_SIZE (MASK_WIDTH-1 + TILE_WIDTH)
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
__global__ void smoothing_kernel(PPMImage *d_image, PPMImage *d_image_copy) {
// Creating variables
int i, j, row, col;
int total_red = 0, total_blue = 0, total_green = 0;
int index_dst_y, index_dst_x, index_src_y, index_src_x;
// Get Row and COl
row = blockIdx.y * TILE_WIDTH + threadIdx.y;
col = blockIdx.x * TILE_WIDTH + threadIdx.x;
// Create Shared block of data
__shared__ PPMPixel shared_image_data[SHARED_SIZE*SHARED_SIZE];
// Filling the shared variable with a two-step for.
// first step fill the data with index inside the blocks dim
// -----------------
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// | | | | | | | | |
// -----------------
// Second step fill the data with index outside the blocks dim
// -----------------
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// |x|x|x|x|x|x|x|x|
// -----------------
for (i = 0; i <= TILE_WIDTH * TILE_WIDTH; i = i + TILE_WIDTH * TILE_WIDTH)
{
// Get indexs of dst matrix
index_dst_y = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) / SHARED_SIZE;
index_dst_x = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) % SHARED_SIZE;
// Get indexs of destination matrix
index_src_y = (blockIdx.y * TILE_WIDTH) + index_dst_y - MASK_R;
index_src_x = (blockIdx.x * TILE_WIDTH) + index_dst_x - MASK_R;
//Work only if dst geral index stay into shared matrix size
if (index_dst_y * SHARED_SIZE + index_dst_x < (SHARED_SIZE*SHARED_SIZE)) {
// if src index stay into image save images values else save 0
if (index_src_y >= 0 && index_src_y < d_image->y && index_src_x >= 0 && index_src_x < d_image->x){
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].red;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].blue;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].green;
}
else{
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = 0;
}
}
}
// sync threads
__syncthreads();
// if row and col stay into image proceed with convolution
if (row < d_image->y && col < d_image->x){
for (i = 0; i < MASK_WIDTH; i++){
for (j = 0; j < MASK_WIDTH; j++) {
total_red += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].red;
total_blue += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].blue;
total_green += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].green;
}
}
// Save data of convolution into devise image
d_image->data[(row * d_image->x) + col].red = total_red / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
void smoothing_GPU(PPMImage *image, PPMImage *image_copy) {
unsigned int rows, cols, img_size;
PPMImage *d_image, *d_image_copy;
PPMPixel *d_pixels, *d_pixels_copy, *new_pixels;
// Get data
cols = image->x;
rows = image->y;
img_size = cols * rows;
// Alloc structure to devise
cudaMalloc((void **)&d_image, sizeof(PPMImage));
cudaMalloc((void **)&d_image_copy, sizeof(PPMImage));
// Alloc image to devise
cudaMalloc((void **)&d_pixels, sizeof(PPMPixel) * img_size);
cudaMalloc((void **)&d_pixels_copy, sizeof(PPMPixel) * img_size);
// cpy stucture to devise
cudaMemcpy(d_image, image, sizeof(PPMImage), cudaMemcpyHostToDevice);
cudaMemcpy(d_pixels, image->data, sizeof(PPMPixel) * img_size, cudaMemcpyHostToDevice);
cudaMemcpy(&(d_image->data), &d_pixels, sizeof(PPMPixel *), cudaMemcpyHostToDevice);
cudaMemcpy(d_image_copy, image, sizeof(PPMImage), cudaMemcpyHostToDevice);
cudaMemcpy(d_pixels_copy, image->data, sizeof(PPMPixel) * img_size, cudaMemcpyHostToDevice);
cudaMemcpy(&(d_image_copy->data), &d_pixels_copy, sizeof(PPMPixel *), cudaMemcpyHostToDevice);
dim3 dimGrid(ceil((float)cols / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
// Call function
smoothing_kernel<<<dimGrid, dimBlock>>>(d_image, d_image_copy);
new_pixels = (PPMPixel *) malloc(img_size * sizeof(PPMPixel));
// Copy result to local array
cudaMemcpy(image, d_image, sizeof(PPMImage), cudaMemcpyDeviceToHost);
cudaMemcpy(new_pixels, d_pixels, sizeof(PPMPixel) * img_size, cudaMemcpyDeviceToHost);
image->data = new_pixels;
//Free memory
cudaFree(d_image);
cudaFree(d_image_copy);
cudaFree(d_pixels);
cudaFree(d_pixels_copy);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
//int i;
char *filename = argv[1]; //Recebendo o arquivo!;
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
smoothing_GPU(image_output, image);
//t_end = rtclock();
writePPM(image_output);
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
}
|
.file "tmpxft_0007f4e4_00000000-6_smooth_gpu.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "Unable to open file '%s'\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Invalid image format (must be 'P6')\n"
.section .rodata.str1.1
.LC3:
.string "Unable to allocate memory\n"
.LC4:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC5:
.string "Invalid image size (error loading '%s')\n"
.section .rodata.str1.1
.LC6:
.string "%d"
.section .rodata.str1.8
.align 8
.LC7:
.string "Invalid rgb component (error loading '%s')\n"
.align 8
.LC8:
.string "'%s' does not have 8-bits components\n"
.section .rodata.str1.1
.LC9:
.string "Error loading image '%s'\n"
#NO_APP
.text
.type _ZL7readPPMPKc, @function
_ZL7readPPMPKc:
.LFB2058:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L20
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %rax, %rcx
movl $16, %edx
movl $16, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L21
cmpb $80, 16(%rsp)
jne .L4
cmpb $54, 17(%rsp)
jne .L4
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L22
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
jne .L7
.L8:
movq %rbx, %rdi
call getc@PLT
cmpl $10, %eax
jne .L8
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
je .L8
.L7:
movq %rbx, %rsi
movl %eax, %edi
call ungetc@PLT
leaq 4(%rbp), %rcx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L23
leaq 12(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L24
cmpl $255, 12(%rsp)
jne .L25
.L12:
movq %rbx, %rdi
call fgetc@PLT
cmpl $10, %eax
jne .L12
movl 0(%rbp), %r14d
movl 4(%rbp), %r13d
movl %r14d, %eax
imull %r13d, %eax
cltq
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%rbp)
movslq %r13d, %rcx
leal (%r14,%r14,2), %edx
movslq %edx, %rdx
movq %rbx, %r8
movq %r15, %rsi
call __fread_chk@PLT
movslq 4(%rbp), %rdx
cmpq %rax, %rdx
jne .L26
movq %rbx, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movq %rbp, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq %r12, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L21:
movq %r12, %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L4:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movq %r12, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq %r12, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movq %r12, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movq %r12, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZL7readPPMPKc, .-_ZL7readPPMPKc
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8
.align 8
.LC10:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L34
.L31:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC11(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.section .rodata.str1.1
.LC12:
.string "P6\n"
.LC13:
.string "Histogram_GPU"
.LC14:
.string "# %s\n"
.LC15:
.string "%d %d\n"
.LC16:
.string "%d\n"
.text
.globl _Z8writePPMP8PPMImage
.type _Z8writePPMP8PPMImage, @function
_Z8writePPMP8PPMImage:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl (%rbx), %ecx
movl 4(%rbx), %r8d
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $255, %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq 4(%rbx), %rdx
movl (%rbx), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
movq 8(%rbx), %rdi
movq stdout(%rip), %rcx
call fwrite@PLT
movq stdout(%rip), %rdi
call fclose@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8writePPMP8PPMImage, .-_Z8writePPMP8PPMImage
.globl _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_
.type _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_, @function
_Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16smoothing_kernelP8PPMImageS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_, .-_Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_
.globl _Z16smoothing_kernelP8PPMImageS0_
.type _Z16smoothing_kernelP8PPMImageS0_, @function
_Z16smoothing_kernelP8PPMImageS0_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z16smoothing_kernelP8PPMImageS0_, .-_Z16smoothing_kernelP8PPMImageS0_
.globl _Z13smoothing_GPUP8PPMImageS0_
.type _Z13smoothing_GPUP8PPMImageS0_, @function
_Z13smoothing_GPUP8PPMImageS0_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl (%rdi), %r12d
movl 4(%rdi), %r13d
movl %r12d, %ebp
imull %r13d, %ebp
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl %ebp, %eax
leaq (%rax,%rax,2), %rbp
leaq 16(%rsp), %r15
movq %rbp, %rsi
movq %r15, %rdi
call cudaMalloc@PLT
leaq 24(%rsp), %r14
movq %rbp, %rsi
movq %r14, %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $16, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rbx), %rsi
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %ecx
movl $8, %edx
movq %r15, %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rbx), %rsi
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %ecx
movl $8, %edx
movq %r14, %rsi
call cudaMemcpy@PLT
movl %r13d, %r13d
pxor %xmm0, %xmm0
cvtsi2ssq %r13, %xmm0
mulss .LC17(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC21(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC18(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L49
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC20(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L49:
movl %r12d, %r12d
pxor %xmm0, %xmm0
cvtsi2ssq %r12, %xmm0
mulss .LC17(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC21(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC18(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L52
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC20(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L52:
cvttss2siq %xmm4, %rax
movl %eax, 32(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L53:
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movl $16, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, 8(%rbx)
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_
jmp .L53
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z13smoothing_GPUP8PPMImageS0_, .-_Z13smoothing_GPUP8PPMImageS0_
.section .rodata.str1.8
.align 8
.LC22:
.string "Too many or no one arguments supplied.\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
cmpl $2, %edi
jne .L61
.L59:
movq 8(%rbx), %rbx
movq %rbx, %rdi
call _ZL7readPPMPKc
movq %rax, %rbp
movq %rbx, %rdi
call _ZL7readPPMPKc
movq %rax, %rbx
movq %rbp, %rsi
movq %rax, %rdi
call _Z13smoothing_GPUP8PPMImageS0_
movq %rbx, %rdi
call _Z8writePPMP8PPMImage
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L59
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC23:
.string "_Z16smoothing_kernelP8PPMImageS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z16smoothing_kernelP8PPMImageS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long 1023410176
.align 4
.LC18:
.long 1258291200
.align 4
.LC20:
.long 1065353216
.align 4
.LC21:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
// MASK SIZE
#define MASK_WIDTH 5
// MASK RADIO
#define MASK_R (MASK_WIDTH-1)/2
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
// SIZE OF TILE
#define TILE_WIDTH 32
// SIZE OF SHARE MATRIX
#define SHARED_SIZE (MASK_WIDTH-1 + TILE_WIDTH)
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
__global__ void smoothing_kernel(PPMImage *d_image, PPMImage *d_image_copy) {
// Creating variables
int i, j, row, col;
int total_red = 0, total_blue = 0, total_green = 0;
int index_dst_y, index_dst_x, index_src_y, index_src_x;
// Get Row and COl
row = blockIdx.y * TILE_WIDTH + threadIdx.y;
col = blockIdx.x * TILE_WIDTH + threadIdx.x;
// Create Shared block of data
__shared__ PPMPixel shared_image_data[SHARED_SIZE*SHARED_SIZE];
// Filling the shared variable with a two-step for.
// first step fill the data with index inside the blocks dim
// -----------------
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// | | | | | | | | |
// -----------------
// Second step fill the data with index outside the blocks dim
// -----------------
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// |x|x|x|x|x|x|x|x|
// -----------------
for (i = 0; i <= TILE_WIDTH * TILE_WIDTH; i = i + TILE_WIDTH * TILE_WIDTH)
{
// Get indexs of dst matrix
index_dst_y = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) / SHARED_SIZE;
index_dst_x = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) % SHARED_SIZE;
// Get indexs of destination matrix
index_src_y = (blockIdx.y * TILE_WIDTH) + index_dst_y - MASK_R;
index_src_x = (blockIdx.x * TILE_WIDTH) + index_dst_x - MASK_R;
//Work only if dst geral index stay into shared matrix size
if (index_dst_y * SHARED_SIZE + index_dst_x < (SHARED_SIZE*SHARED_SIZE)) {
// if src index stay into image save images values else save 0
if (index_src_y >= 0 && index_src_y < d_image->y && index_src_x >= 0 && index_src_x < d_image->x){
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].red;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].blue;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].green;
}
else{
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = 0;
}
}
}
// sync threads
__syncthreads();
// if row and col stay into image proceed with convolution
if (row < d_image->y && col < d_image->x){
for (i = 0; i < MASK_WIDTH; i++){
for (j = 0; j < MASK_WIDTH; j++) {
total_red += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].red;
total_blue += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].blue;
total_green += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].green;
}
}
// Save data of convolution into devise image
d_image->data[(row * d_image->x) + col].red = total_red / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
void smoothing_GPU(PPMImage *image, PPMImage *image_copy) {
unsigned int rows, cols, img_size;
PPMImage *d_image, *d_image_copy;
PPMPixel *d_pixels, *d_pixels_copy, *new_pixels;
// Get data
cols = image->x;
rows = image->y;
img_size = cols * rows;
// Alloc structure to devise
cudaMalloc((void **)&d_image, sizeof(PPMImage));
cudaMalloc((void **)&d_image_copy, sizeof(PPMImage));
// Alloc image to devise
cudaMalloc((void **)&d_pixels, sizeof(PPMPixel) * img_size);
cudaMalloc((void **)&d_pixels_copy, sizeof(PPMPixel) * img_size);
// cpy stucture to devise
cudaMemcpy(d_image, image, sizeof(PPMImage), cudaMemcpyHostToDevice);
cudaMemcpy(d_pixels, image->data, sizeof(PPMPixel) * img_size, cudaMemcpyHostToDevice);
cudaMemcpy(&(d_image->data), &d_pixels, sizeof(PPMPixel *), cudaMemcpyHostToDevice);
cudaMemcpy(d_image_copy, image, sizeof(PPMImage), cudaMemcpyHostToDevice);
cudaMemcpy(d_pixels_copy, image->data, sizeof(PPMPixel) * img_size, cudaMemcpyHostToDevice);
cudaMemcpy(&(d_image_copy->data), &d_pixels_copy, sizeof(PPMPixel *), cudaMemcpyHostToDevice);
dim3 dimGrid(ceil((float)cols / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
// Call function
smoothing_kernel<<<dimGrid, dimBlock>>>(d_image, d_image_copy);
new_pixels = (PPMPixel *) malloc(img_size * sizeof(PPMPixel));
// Copy result to local array
cudaMemcpy(image, d_image, sizeof(PPMImage), cudaMemcpyDeviceToHost);
cudaMemcpy(new_pixels, d_pixels, sizeof(PPMPixel) * img_size, cudaMemcpyDeviceToHost);
image->data = new_pixels;
//Free memory
cudaFree(d_image);
cudaFree(d_image_copy);
cudaFree(d_pixels);
cudaFree(d_pixels_copy);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
//int i;
char *filename = argv[1]; //Recebendo o arquivo!;
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
smoothing_GPU(image_output, image);
//t_end = rtclock();
writePPM(image_output);
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
// MASK SIZE
#define MASK_WIDTH 5
// MASK RADIO
#define MASK_R (MASK_WIDTH-1)/2
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
// SIZE OF TILE
#define TILE_WIDTH 32
// SIZE OF SHARE MATRIX
#define SHARED_SIZE (MASK_WIDTH-1 + TILE_WIDTH)
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
__global__ void smoothing_kernel(PPMImage *d_image, PPMImage *d_image_copy) {
// Creating variables
int i, j, row, col;
int total_red = 0, total_blue = 0, total_green = 0;
int index_dst_y, index_dst_x, index_src_y, index_src_x;
// Get Row and COl
row = blockIdx.y * TILE_WIDTH + threadIdx.y;
col = blockIdx.x * TILE_WIDTH + threadIdx.x;
// Create Shared block of data
__shared__ PPMPixel shared_image_data[SHARED_SIZE*SHARED_SIZE];
// Filling the shared variable with a two-step for.
// first step fill the data with index inside the blocks dim
// -----------------
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// | | | | | | | | |
// -----------------
// Second step fill the data with index outside the blocks dim
// -----------------
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// |x|x|x|x|x|x|x|x|
// -----------------
for (i = 0; i <= TILE_WIDTH * TILE_WIDTH; i = i + TILE_WIDTH * TILE_WIDTH)
{
// Get indexs of dst matrix
index_dst_y = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) / SHARED_SIZE;
index_dst_x = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) % SHARED_SIZE;
// Get indexs of destination matrix
index_src_y = (blockIdx.y * TILE_WIDTH) + index_dst_y - MASK_R;
index_src_x = (blockIdx.x * TILE_WIDTH) + index_dst_x - MASK_R;
//Work only if dst geral index stay into shared matrix size
if (index_dst_y * SHARED_SIZE + index_dst_x < (SHARED_SIZE*SHARED_SIZE)) {
// if src index stay into image save images values else save 0
if (index_src_y >= 0 && index_src_y < d_image->y && index_src_x >= 0 && index_src_x < d_image->x){
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].red;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].blue;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].green;
}
else{
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = 0;
}
}
}
// sync threads
__syncthreads();
// if row and col stay into image proceed with convolution
if (row < d_image->y && col < d_image->x){
for (i = 0; i < MASK_WIDTH; i++){
for (j = 0; j < MASK_WIDTH; j++) {
total_red += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].red;
total_blue += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].blue;
total_green += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].green;
}
}
// Save data of convolution into devise image
d_image->data[(row * d_image->x) + col].red = total_red / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
void smoothing_GPU(PPMImage *image, PPMImage *image_copy) {
unsigned int rows, cols, img_size;
PPMImage *d_image, *d_image_copy;
PPMPixel *d_pixels, *d_pixels_copy, *new_pixels;
// Get data
cols = image->x;
rows = image->y;
img_size = cols * rows;
// Alloc structure to devise
hipMalloc((void **)&d_image, sizeof(PPMImage));
hipMalloc((void **)&d_image_copy, sizeof(PPMImage));
// Alloc image to devise
hipMalloc((void **)&d_pixels, sizeof(PPMPixel) * img_size);
hipMalloc((void **)&d_pixels_copy, sizeof(PPMPixel) * img_size);
// cpy stucture to devise
hipMemcpy(d_image, image, sizeof(PPMImage), hipMemcpyHostToDevice);
hipMemcpy(d_pixels, image->data, sizeof(PPMPixel) * img_size, hipMemcpyHostToDevice);
hipMemcpy(&(d_image->data), &d_pixels, sizeof(PPMPixel *), hipMemcpyHostToDevice);
hipMemcpy(d_image_copy, image, sizeof(PPMImage), hipMemcpyHostToDevice);
hipMemcpy(d_pixels_copy, image->data, sizeof(PPMPixel) * img_size, hipMemcpyHostToDevice);
hipMemcpy(&(d_image_copy->data), &d_pixels_copy, sizeof(PPMPixel *), hipMemcpyHostToDevice);
dim3 dimGrid(ceil((float)cols / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
// Call function
smoothing_kernel<<<dimGrid, dimBlock>>>(d_image, d_image_copy);
new_pixels = (PPMPixel *) malloc(img_size * sizeof(PPMPixel));
// Copy result to local array
hipMemcpy(image, d_image, sizeof(PPMImage), hipMemcpyDeviceToHost);
hipMemcpy(new_pixels, d_pixels, sizeof(PPMPixel) * img_size, hipMemcpyDeviceToHost);
image->data = new_pixels;
//Free memory
hipFree(d_image);
hipFree(d_image_copy);
hipFree(d_pixels);
hipFree(d_pixels_copy);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
//int i;
char *filename = argv[1]; //Recebendo o arquivo!;
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
smoothing_GPU(image_output, image);
//t_end = rtclock();
writePPM(image_output);
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
// MASK SIZE
#define MASK_WIDTH 5
// MASK RADIO
#define MASK_R (MASK_WIDTH-1)/2
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
// SIZE OF TILE
#define TILE_WIDTH 32
// SIZE OF SHARE MATRIX
#define SHARED_SIZE (MASK_WIDTH-1 + TILE_WIDTH)
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
__global__ void smoothing_kernel(PPMImage *d_image, PPMImage *d_image_copy) {
// Creating variables
int i, j, row, col;
int total_red = 0, total_blue = 0, total_green = 0;
int index_dst_y, index_dst_x, index_src_y, index_src_x;
// Get Row and COl
row = blockIdx.y * TILE_WIDTH + threadIdx.y;
col = blockIdx.x * TILE_WIDTH + threadIdx.x;
// Create Shared block of data
__shared__ PPMPixel shared_image_data[SHARED_SIZE*SHARED_SIZE];
// Filling the shared variable with a two-step for.
// first step fill the data with index inside the blocks dim
// -----------------
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// | | | | | | | | |
// -----------------
// Second step fill the data with index outside the blocks dim
// -----------------
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// |x|x|x|x|x|x|x|x|
// -----------------
for (i = 0; i <= TILE_WIDTH * TILE_WIDTH; i = i + TILE_WIDTH * TILE_WIDTH)
{
// Get indexs of dst matrix
index_dst_y = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) / SHARED_SIZE;
index_dst_x = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) % SHARED_SIZE;
// Get indexs of destination matrix
index_src_y = (blockIdx.y * TILE_WIDTH) + index_dst_y - MASK_R;
index_src_x = (blockIdx.x * TILE_WIDTH) + index_dst_x - MASK_R;
//Work only if dst geral index stay into shared matrix size
if (index_dst_y * SHARED_SIZE + index_dst_x < (SHARED_SIZE*SHARED_SIZE)) {
// if src index stay into image save images values else save 0
if (index_src_y >= 0 && index_src_y < d_image->y && index_src_x >= 0 && index_src_x < d_image->x){
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].red;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].blue;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].green;
}
else{
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = 0;
}
}
}
// sync threads
__syncthreads();
// if row and col stay into image proceed with convolution
if (row < d_image->y && col < d_image->x){
for (i = 0; i < MASK_WIDTH; i++){
for (j = 0; j < MASK_WIDTH; j++) {
total_red += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].red;
total_blue += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].blue;
total_green += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].green;
}
}
// Save data of convolution into devise image
d_image->data[(row * d_image->x) + col].red = total_red / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
void smoothing_GPU(PPMImage *image, PPMImage *image_copy) {
unsigned int rows, cols, img_size;
PPMImage *d_image, *d_image_copy;
PPMPixel *d_pixels, *d_pixels_copy, *new_pixels;
// Get data
cols = image->x;
rows = image->y;
img_size = cols * rows;
// Alloc structure to devise
hipMalloc((void **)&d_image, sizeof(PPMImage));
hipMalloc((void **)&d_image_copy, sizeof(PPMImage));
// Alloc image to devise
hipMalloc((void **)&d_pixels, sizeof(PPMPixel) * img_size);
hipMalloc((void **)&d_pixels_copy, sizeof(PPMPixel) * img_size);
// cpy stucture to devise
hipMemcpy(d_image, image, sizeof(PPMImage), hipMemcpyHostToDevice);
hipMemcpy(d_pixels, image->data, sizeof(PPMPixel) * img_size, hipMemcpyHostToDevice);
hipMemcpy(&(d_image->data), &d_pixels, sizeof(PPMPixel *), hipMemcpyHostToDevice);
hipMemcpy(d_image_copy, image, sizeof(PPMImage), hipMemcpyHostToDevice);
hipMemcpy(d_pixels_copy, image->data, sizeof(PPMPixel) * img_size, hipMemcpyHostToDevice);
hipMemcpy(&(d_image_copy->data), &d_pixels_copy, sizeof(PPMPixel *), hipMemcpyHostToDevice);
dim3 dimGrid(ceil((float)cols / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
// Call function
smoothing_kernel<<<dimGrid, dimBlock>>>(d_image, d_image_copy);
new_pixels = (PPMPixel *) malloc(img_size * sizeof(PPMPixel));
// Copy result to local array
hipMemcpy(image, d_image, sizeof(PPMImage), hipMemcpyDeviceToHost);
hipMemcpy(new_pixels, d_pixels, sizeof(PPMPixel) * img_size, hipMemcpyDeviceToHost);
image->data = new_pixels;
//Free memory
hipFree(d_image);
hipFree(d_image_copy);
hipFree(d_pixels);
hipFree(d_pixels_copy);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
//int i;
char *filename = argv[1]; //Recebendo o arquivo!;
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
smoothing_GPU(image_output, image);
//t_end = rtclock();
writePPM(image_output);
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16smoothing_kernelP8PPMImageS0_
.globl _Z16smoothing_kernelP8PPMImageS0_
.p2align 8
.type _Z16smoothing_kernelP8PPMImageS0_,@function
_Z16smoothing_kernelP8PPMImageS0_:
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_lshl_b32 s2, s15, 5
s_lshl_b32 s1, s14, 5
s_add_i32 s3, s2, -2
s_add_i32 s8, s1, -2
v_lshl_add_u32 v3, v1, 5, v2
s_mov_b32 s9, 0
s_branch .LBB0_3
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt vmcnt(0) lgkmcnt(0)
ds_store_b8 v6, v7 offset:1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
s_addk_i32 s9, 0x400
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s9, 0x400
s_cbranch_scc0 .LBB0_12
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s9, v3
s_mov_b32 s10, exec_lo
v_cmpx_gt_u32_e32 0x510, v6
s_cbranch_execz .LBB0_2
v_mul_hi_u32 v5, v6, 0x38e38e39
s_mov_b32 s0, 0
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v7, 3, v5
v_add_nc_u32_e32 v5, s3, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e64 s11, 0, v5
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB0_8
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[4:5], 0x4
v_mul_lo_u32 v0, v7, 36
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v6, v0
v_add_nc_u32_e32 v0, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s0, v5
s_and_b32 s15, vcc_lo, s0
s_mov_b32 s0, 0
s_xor_b32 s13, s15, -1
s_and_saveexec_b32 s14, s15
s_cbranch_execz .LBB0_7
s_load_b32 s15, s[4:5], 0x0
s_and_not1_b32 s13, s13, exec_lo
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s15, v0
v_mov_b32_e32 v4, s15
s_and_b32 s15, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s13, s13, s15
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s11, s11, exec_lo
s_and_b32 s13, s13, exec_lo
s_and_b32 s0, s0, exec_lo
s_or_b32 s11, s11, s13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s12
v_lshl_add_u32 v6, v6, 1, v6
s_and_saveexec_b32 s13, s11
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v7, 0
s_mov_b32 s12, 0
s_and_not1_b32 s0, s0, exec_lo
ds_store_b8 v6, v7
ds_store_b8 v6, v7 offset:2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v7, s12
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_1
s_waitcnt lgkmcnt(0)
s_load_b64 s[12:13], s[6:7], 0x8
v_mad_u64_u32 v[7:8], null, v4, v5, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_i64_i32 v[8:9], null, v7, 3, s[12:13]
s_clause 0x2
flat_load_u8 v5, v[8:9]
flat_load_u8 v10, v[8:9] offset:2
flat_load_u8 v7, v[8:9] offset:1
s_waitcnt vmcnt(2) lgkmcnt(2)
ds_store_b8 v6, v5
s_waitcnt vmcnt(1) lgkmcnt(2)
ds_store_b8 v6, v10 offset:2
s_branch .LBB0_1
.LBB0_12:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s0, s[4:5], 0x4
v_add_nc_u32_e32 v3, s2, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v3
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b32 s0, s[4:5], 0x0
v_add_nc_u32_e32 v0, s1, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
v_mul_u32_u24_e32 v5, 3, v2
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v2, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3)
v_mad_u32_u24 v5, v1, 0x6c, v5
v_mov_b32_e32 v1, 0
.p2align 6
.LBB0_15:
s_mov_b32 s2, 0
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v6, s2, v5
s_addk_i32 s2, 0x6c
ds_load_u8 v7, v6
ds_load_u8 v8, v6 offset:2
ds_load_u8 v6, v6 offset:1
s_cmpk_lg_i32 s2, 0x21c
s_waitcnt lgkmcnt(2)
v_add_nc_u32_e32 v4, v4, v7
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v2, v2, v8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v6
s_cbranch_scc1 .LBB0_16
v_add_nc_u32_e32 v5, 3, v5
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 5
s_cbranch_scc1 .LBB0_15
s_load_b64 s[2:3], s[4:5], 0x8
v_mul_hi_i32 v4, v4, 0x51eb851f
v_mul_hi_i32 v5, v2, 0x51eb851f
v_mul_hi_i32 v6, v1, 0x51eb851f
v_mad_u64_u32 v[1:2], null, s0, v3, v[0:1]
s_delay_alu instid0(VALU_DEP_4)
v_lshrrev_b32_e32 v0, 31, v4
v_lshrrev_b32_e32 v4, 3, v4
v_lshrrev_b32_e32 v7, 31, v5
v_lshrrev_b32_e32 v5, 3, v5
v_lshrrev_b32_e32 v8, 31, v6
v_lshrrev_b32_e32 v6, 3, v6
v_add_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v4, v6, v8
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 3, s[2:3]
v_add_nc_u32_e32 v1, v5, v7
s_clause 0x2
flat_store_b8 v[2:3], v0
flat_store_b8 v[2:3], v1 offset:2
flat_store_b8 v[2:3], v4 offset:1
.LBB0_19:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16smoothing_kernelP8PPMImageS0_
.amdhsa_group_segment_fixed_size 3888
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16smoothing_kernelP8PPMImageS0_, .Lfunc_end0-_Z16smoothing_kernelP8PPMImageS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 3888
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16smoothing_kernelP8PPMImageS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16smoothing_kernelP8PPMImageS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
// MASK SIZE
#define MASK_WIDTH 5
// MASK RADIO
#define MASK_R (MASK_WIDTH-1)/2
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
// SIZE OF TILE
#define TILE_WIDTH 32
// SIZE OF SHARE MATRIX
#define SHARED_SIZE (MASK_WIDTH-1 + TILE_WIDTH)
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
void writePPM(PPMImage *img) {
fprintf(stdout, "P6\n");
fprintf(stdout, "# %s\n", COMMENT);
fprintf(stdout, "%d %d\n", img->x, img->y);
fprintf(stdout, "%d\n", RGB_COMPONENT_COLOR);
fwrite(img->data, 3 * img->x, img->y, stdout);
fclose(stdout);
}
__global__ void smoothing_kernel(PPMImage *d_image, PPMImage *d_image_copy) {
// Creating variables
int i, j, row, col;
int total_red = 0, total_blue = 0, total_green = 0;
int index_dst_y, index_dst_x, index_src_y, index_src_x;
// Get Row and COl
row = blockIdx.y * TILE_WIDTH + threadIdx.y;
col = blockIdx.x * TILE_WIDTH + threadIdx.x;
// Create Shared block of data
__shared__ PPMPixel shared_image_data[SHARED_SIZE*SHARED_SIZE];
// Filling the shared variable with a two-step for.
// first step fill the data with index inside the blocks dim
// -----------------
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// |x|x|x|x|x|x|x| |
// | | | | | | | | |
// -----------------
// Second step fill the data with index outside the blocks dim
// -----------------
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// | | | | | | | |x|
// |x|x|x|x|x|x|x|x|
// -----------------
for (i = 0; i <= TILE_WIDTH * TILE_WIDTH; i = i + TILE_WIDTH * TILE_WIDTH)
{
// Get indexs of dst matrix
index_dst_y = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) / SHARED_SIZE;
index_dst_x = (threadIdx.y * TILE_WIDTH + threadIdx.x + i) % SHARED_SIZE;
// Get indexs of destination matrix
index_src_y = (blockIdx.y * TILE_WIDTH) + index_dst_y - MASK_R;
index_src_x = (blockIdx.x * TILE_WIDTH) + index_dst_x - MASK_R;
//Work only if dst geral index stay into shared matrix size
if (index_dst_y * SHARED_SIZE + index_dst_x < (SHARED_SIZE*SHARED_SIZE)) {
// if src index stay into image save images values else save 0
if (index_src_y >= 0 && index_src_y < d_image->y && index_src_x >= 0 && index_src_x < d_image->x){
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].red;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].blue;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = d_image_copy->data[(index_src_y * d_image->x) + index_src_x].green;
}
else{
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].red = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].blue = 0;
shared_image_data[index_dst_y * SHARED_SIZE + index_dst_x].green = 0;
}
}
}
// sync threads
__syncthreads();
// if row and col stay into image proceed with convolution
if (row < d_image->y && col < d_image->x){
for (i = 0; i < MASK_WIDTH; i++){
for (j = 0; j < MASK_WIDTH; j++) {
total_red += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].red;
total_blue += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].blue;
total_green += shared_image_data[((threadIdx.y + j) * SHARED_SIZE) + (threadIdx.x + i)].green;
}
}
// Save data of convolution into devise image
d_image->data[(row * d_image->x) + col].red = total_red / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].blue = total_blue / (MASK_WIDTH*MASK_WIDTH);
d_image->data[(row * d_image->x) + col].green = total_green / (MASK_WIDTH*MASK_WIDTH);
}
}
void smoothing_GPU(PPMImage *image, PPMImage *image_copy) {
unsigned int rows, cols, img_size;
PPMImage *d_image, *d_image_copy;
PPMPixel *d_pixels, *d_pixels_copy, *new_pixels;
// Get data
cols = image->x;
rows = image->y;
img_size = cols * rows;
// Alloc structure to devise
hipMalloc((void **)&d_image, sizeof(PPMImage));
hipMalloc((void **)&d_image_copy, sizeof(PPMImage));
// Alloc image to devise
hipMalloc((void **)&d_pixels, sizeof(PPMPixel) * img_size);
hipMalloc((void **)&d_pixels_copy, sizeof(PPMPixel) * img_size);
// cpy stucture to devise
hipMemcpy(d_image, image, sizeof(PPMImage), hipMemcpyHostToDevice);
hipMemcpy(d_pixels, image->data, sizeof(PPMPixel) * img_size, hipMemcpyHostToDevice);
hipMemcpy(&(d_image->data), &d_pixels, sizeof(PPMPixel *), hipMemcpyHostToDevice);
hipMemcpy(d_image_copy, image, sizeof(PPMImage), hipMemcpyHostToDevice);
hipMemcpy(d_pixels_copy, image->data, sizeof(PPMPixel) * img_size, hipMemcpyHostToDevice);
hipMemcpy(&(d_image_copy->data), &d_pixels_copy, sizeof(PPMPixel *), hipMemcpyHostToDevice);
dim3 dimGrid(ceil((float)cols / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
// Call function
smoothing_kernel<<<dimGrid, dimBlock>>>(d_image, d_image_copy);
new_pixels = (PPMPixel *) malloc(img_size * sizeof(PPMPixel));
// Copy result to local array
hipMemcpy(image, d_image, sizeof(PPMImage), hipMemcpyDeviceToHost);
hipMemcpy(new_pixels, d_pixels, sizeof(PPMPixel) * img_size, hipMemcpyDeviceToHost);
image->data = new_pixels;
//Free memory
hipFree(d_image);
hipFree(d_image_copy);
hipFree(d_pixels);
hipFree(d_pixels_copy);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
//int i;
char *filename = argv[1]; //Recebendo o arquivo!;
PPMImage *image = readPPM(filename);
PPMImage *image_output = readPPM(filename);
//t_start = rtclock();
smoothing_GPU(image_output, image);
//t_end = rtclock();
writePPM(image_output);
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(image);
free(image_output);
}
|
.text
.file "smooth_gpu.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z8writePPMP8PPMImage # -- Begin function _Z8writePPMP8PPMImage
.p2align 4, 0x90
.type _Z8writePPMP8PPMImage,@function
_Z8writePPMP8PPMImage: # @_Z8writePPMP8PPMImage
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
callq fwrite
movq stdout(%rip), %rdi
movl $.L.str.2, %esi
movl $.L.str.3, %edx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl (%rbx), %edx
movl 4(%rbx), %ecx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl $.L.str.5, %esi
movl $255, %edx
xorl %eax, %eax
callq fprintf
movq 8(%rbx), %rdi
movslq (%rbx), %rax
leaq (%rax,%rax,2), %rsi
movslq 4(%rbx), %rdx
movq stdout(%rip), %rcx
callq fwrite
movq stdout(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z8writePPMP8PPMImage, .Lfunc_end1-_Z8writePPMP8PPMImage
.cfi_endproc
# -- End function
.globl _Z31__device_stub__smoothing_kernelP8PPMImageS0_ # -- Begin function _Z31__device_stub__smoothing_kernelP8PPMImageS0_
.p2align 4, 0x90
.type _Z31__device_stub__smoothing_kernelP8PPMImageS0_,@function
_Z31__device_stub__smoothing_kernelP8PPMImageS0_: # @_Z31__device_stub__smoothing_kernelP8PPMImageS0_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16smoothing_kernelP8PPMImageS0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z31__device_stub__smoothing_kernelP8PPMImageS0_, .Lfunc_end2-_Z31__device_stub__smoothing_kernelP8PPMImageS0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13smoothing_GPUP8PPMImageS0_
.LCPI3_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z13smoothing_GPUP8PPMImageS0_
.p2align 4, 0x90
.type _Z13smoothing_GPUP8PPMImageS0_,@function
_Z13smoothing_GPUP8PPMImageS0_: # @_Z13smoothing_GPUP8PPMImageS0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl (%rdi), %ebp
movl 4(%rdi), %r13d
movl %r13d, %r14d
imull %ebp, %r14d
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq (%r14,%r14,2), %r14
leaq 16(%rsp), %r12
movq %r12, %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %r15
movq %r15, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 8(%rbx), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
addq $8, %rdi
movl $8, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 8(%rbx), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
addq $8, %rdi
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %rbp, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r15
xorps %xmm0, %xmm0
cvtsi2ss %r13, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %r15d, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16smoothing_kernelP8PPMImageS0_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq (%rsp), %rsi
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r15, 8(%rbx)
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z13smoothing_GPUP8PPMImageS0_, .Lfunc_end3-_Z13smoothing_GPUP8PPMImageS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
cmpl $2, %edi
je .LBB4_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB4_2:
movq 8(%rbx), %r14
movq %r14, %rdi
callq _ZL7readPPMPKc
movq %rax, %rbx
movq %r14, %rdi
callq _ZL7readPPMPKc
movq %rax, %r14
movq %rax, %rdi
callq _Z13smoothing_GPUP8PPMImageS0_
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
callq fwrite
movq stdout(%rip), %rdi
movl $.L.str.2, %esi
movl $.L.str.3, %edx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl (%r14), %edx
movl 4(%r14), %ecx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl $.L.str.5, %esi
movl $255, %edx
xorl %eax, %eax
callq fprintf
movq 8(%r14), %rdi
movslq (%r14), %rax
leaq (%rax,%rax,2), %rsi
movslq 4(%r14), %rdx
movq stdout(%rip), %rcx
callq fwrite
movq stdout(%rip), %rdi
callq fclose
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL7readPPMPKc
.type _ZL7readPPMPKc,@function
_ZL7readPPMPKc: # @_ZL7readPPMPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.7, %esi
callq fopen
testq %rax, %rax
je .LBB5_1
# %bb.3:
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $16, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB5_23
# %bb.4:
cmpb $80, 16(%rsp)
jne .LBB5_6
# %bb.5:
cmpb $54, 17(%rsp)
jne .LBB5_6
# %bb.8:
movl $16, %edi
callq malloc
testq %rax, %rax
je .LBB5_9
# %bb.10:
movq %rax, %r15
.p2align 4, 0x90
.LBB5_11: # =>This Loop Header: Depth=1
# Child Loop BB5_12 Depth 2
movq %r14, %rdi
callq getc
cmpl $35, %eax
jne .LBB5_13
.LBB5_12: # %.preheader44
# Parent Loop BB5_11 Depth=1
# => This Inner Loop Header: Depth=2
movq %r14, %rdi
callq getc
cmpl $10, %eax
jne .LBB5_12
jmp .LBB5_11
.LBB5_13: # %._crit_edge
movl %eax, %edi
movq %r14, %rsi
callq ungetc
movq %r15, %rcx
addq $4, %rcx
movl $.L.str.11, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB5_14
# %bb.15:
leaq 12(%rsp), %rdx
movl $.L.str.13, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB5_16
# %bb.17:
cmpl $255, 12(%rsp)
jne .LBB5_18
.p2align 4, 0x90
.LBB5_19: # %.preheader
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq fgetc
cmpl $10, %eax
jne .LBB5_19
# %bb.20:
movslq (%r15), %rax
movslq 4(%r15), %r12
leaq (%rax,%rax,2), %r13
movq %r13, %rdi
imulq %r12, %rdi
callq malloc
movq %rax, 8(%r15)
movq %rax, %rdi
movq %r13, %rsi
movq %r12, %rdx
movq %r14, %rcx
callq fread
movslq 4(%r15), %rcx
cmpq %rcx, %rax
jne .LBB5_21
# %bb.22:
movq %r14, %rdi
callq fclose
movq %r15, %rax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_1:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
jmp .LBB5_2
.LBB5_23:
movq %rbx, %rdi
callq perror
movl $1, %edi
callq exit
.LBB5_6:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $36, %esi
jmp .LBB5_7
.LBB5_9:
movq stderr(%rip), %rcx
movl $.L.str.10, %edi
movl $26, %esi
.LBB5_7:
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.LBB5_14:
movq stderr(%rip), %rdi
movl $.L.str.12, %esi
jmp .LBB5_2
.LBB5_16:
movq stderr(%rip), %rdi
movl $.L.str.14, %esi
jmp .LBB5_2
.LBB5_18:
movq stderr(%rip), %rdi
movl $.L.str.15, %esi
jmp .LBB5_2
.LBB5_21:
movq stderr(%rip), %rdi
movl $.L.str.16, %esi
.LBB5_2:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end5:
.size _ZL7readPPMPKc, .Lfunc_end5-_ZL7readPPMPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16smoothing_kernelP8PPMImageS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "P6\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "# %s\n"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Histogram_GPU"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %d\n"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type _Z16smoothing_kernelP8PPMImageS0_,@object # @_Z16smoothing_kernelP8PPMImageS0_
.section .rodata,"a",@progbits
.globl _Z16smoothing_kernelP8PPMImageS0_
.p2align 3, 0x0
_Z16smoothing_kernelP8PPMImageS0_:
.quad _Z31__device_stub__smoothing_kernelP8PPMImageS0_
.size _Z16smoothing_kernelP8PPMImageS0_, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "rb"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Unable to open file '%s'\n"
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Invalid image format (must be 'P6')\n"
.size .L.str.9, 37
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Unable to allocate memory\n"
.size .L.str.10, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%d %d"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Invalid image size (error loading '%s')\n"
.size .L.str.12, 41
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%d"
.size .L.str.13, 3
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Invalid rgb component (error loading '%s')\n"
.size .L.str.14, 44
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "'%s' does not have 8-bits components\n"
.size .L.str.15, 38
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Error loading image '%s'\n"
.size .L.str.16, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16smoothing_kernelP8PPMImageS0_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too many or no one arguments supplied."
.size .Lstr, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__smoothing_kernelP8PPMImageS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16smoothing_kernelP8PPMImageS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z16smoothing_kernelP8PPMImageS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x3b0 ; /* 0x0000037000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0050*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0060*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002500 */
/*0070*/ IMAD R3, R9, 0x20, R6 ; /* 0x0000002009037824 */
/* 0x001fc800078e0206 */
/*0080*/ IMAD.WIDE.U32 R4, R3, 0x38e38e39, RZ ; /* 0x38e38e3903047825 */
/* 0x000fca00078e00ff */
/*0090*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*00a0*/ IMAD R8, R5.reuse, -0x24, R3 ; /* 0xffffffdc05087824 */
/* 0x040fe400078e0203 */
/*00b0*/ IMAD R4, R0, 0x20, R5 ; /* 0x0000002000047824 */
/* 0x002fe400078e0205 */
/*00c0*/ IMAD R2, R5, 0x24, R8 ; /* 0x0000002405027824 */
/* 0x000fca00078e0208 */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R2.reuse, 0x50f, PT ; /* 0x0000050f0200780c */
/* 0x040fe20003f04070 */
/*00e0*/ IMAD R2, R2, 0x3, RZ ; /* 0x0000000302027824 */
/* 0x000fd800078e02ff */
/*00f0*/ @P0 BRA 0x3a0 ; /* 0x000002a000000947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R12, R4, -0x2, RZ ; /* 0xfffffffe040c7810 */
/* 0x004fe20007ffe0ff */
/*0110*/ UMOV UR6, 0x1 ; /* 0x0000000100067882 */
/* 0x000fe20000000000 */
/*0120*/ IMAD R8, R7, 0x20, R8 ; /* 0x0000002007087824 */
/* 0x000fe200078e0208 */
/*0130*/ ULDC.64 UR4, c[0x2][0x0] ; /* 0x0080000000047ab9 */
/* 0x000fe20000000a00 */
/*0140*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f26270 */
/*0150*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe20000000a00 */
/*0160*/ BSSY B1, 0x230 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*0170*/ UIMAD.WIDE.U32 UR4, UR6, UR8, UR4 ; /* 0x00000008060472a5 */
/* 0x000fe2000f8e0004 */
/*0180*/ IADD3 R8, R8, -0x2, RZ ; /* 0xfffffffe08087810 */
/* 0x000fe20007ffe0ff */
/*0190*/ UIMAD UR6, UR6, UR9, URZ ; /* 0x00000009060672a4 */
/* 0x000fe2000f8e023f */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*01b0*/ UIADD3 UR6, UR5, UR6, URZ ; /* 0x0000000605067290 */
/* 0x000fe2000fffe03f */
/*01c0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe4000f8e00ff */
/*01d0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fc6000f8e00ff */
/*01e0*/ IMAD.U32 R5, RZ, RZ, UR6 ; /* 0x00000006ff057e24 */
/* 0x000fe2000f8e00ff */
/*01f0*/ @!P1 BRA 0x220 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0200*/ LDG.E R11, [R4.64] ; /* 0x0000000a040b7981 */
/* 0x000ea4000c1e1900 */
/*0210*/ ISETP.LT.AND P0, PT, R12, R11, PT ; /* 0x0000000b0c00720c */
/* 0x004fd00003f01270 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.LT.OR P0, PT, R8, RZ, !P0 ; /* 0x000000ff0800720c */
/* 0x000fe20004701670 */
/*0240*/ BSSY B1, 0x2b0 ; /* 0x0000006000017945 */
/* 0x000fd80003800000 */
/*0250*/ @P0 BRA 0x2a0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0260*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc0a040d7981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x004fda0003f06270 */
/*0280*/ @!P0 BREAK B1 ; /* 0x0000000000018942 */
/* 0x000fe20003800000 */
/*0290*/ @!P0 BRA 0x2f0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02b0*/ STS.U8 [R2], RZ ; /* 0x000000ff02007388 */
/* 0x0001e80000000000 */
/*02c0*/ STS.U8 [R2+0x2], RZ ; /* 0x000002ff02007388 */
/* 0x0001e80000000000 */
/*02d0*/ STS.U8 [R2+0x1], RZ ; /* 0x000001ff02007388 */
/* 0x0001e20000000000 */
/*02e0*/ BRA 0x3a0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe400078e00ff */
/*0300*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fca00078e00ff */
/*0310*/ LDG.E.64 R4, [R10.64+0x8] ; /* 0x0000080a0a047981 */
/* 0x000ea2000c1e1b00 */
/*0320*/ IMAD R13, R12, R13, R8 ; /* 0x0000000d0c0d7224 */
/* 0x000fc800078e0208 */
/*0330*/ IMAD.WIDE R4, R13, 0x3, R4 ; /* 0x000000030d047825 */
/* 0x004fca00078e0204 */
/*0340*/ LDG.E.U8 R13, [R4.64] ; /* 0x0000000a040d7981 */
/* 0x000ea8000c1e1100 */
/*0350*/ LDG.E.U8 R15, [R4.64+0x2] ; /* 0x0000020a040f7981 */
/* 0x000ee8000c1e1100 */
/*0360*/ LDG.E.U8 R17, [R4.64+0x1] ; /* 0x0000010a04117981 */
/* 0x000f28000c1e1100 */
/*0370*/ STS.U8 [R2], R13 ; /* 0x0000000d02007388 */
/* 0x0041e80000000000 */
/*0380*/ STS.U8 [R2+0x2], R15 ; /* 0x0000020f02007388 */
/* 0x0081e80000000000 */
/*0390*/ STS.U8 [R2+0x1], R17 ; /* 0x0000011102007388 */
/* 0x0101e40000000000 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*03b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*03c0*/ IADD3 R3, R3, 0x400, RZ ; /* 0x0000040003037810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ BSSY B0, 0x700 ; /* 0x0000032000007945 */
/* 0x000fe80003800000 */
/*03e0*/ IMAD.WIDE.U32 R4, R3, 0x38e38e39, RZ ; /* 0x38e38e3903047825 */
/* 0x000fca00078e00ff */
/*03f0*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*0400*/ IMAD R4, R5, -0x24, R3 ; /* 0xffffffdc05047824 */
/* 0x000fc800078e0203 */
/*0410*/ IMAD R3, R5, 0x24, R4.reuse ; /* 0x0000002405037824 */
/* 0x100fe400078e0204 */
/*0420*/ IMAD R8, R7, 0x20, R4 ; /* 0x0000002007087824 */
/* 0x000fc600078e0204 */
/*0430*/ ISETP.GT.U32.AND P0, PT, R3, 0x50f, PT ; /* 0x0000050f0300780c */
/* 0x000fe20003f04070 */
/*0440*/ IMAD R3, R0, 0x20, R5 ; /* 0x0000002000037824 */
/* 0x000fd800078e0205 */
/*0450*/ @P0 BRA 0x6f0 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R3, R3, -0x2, RZ ; /* 0xfffffffe03037810 */
/* 0x000fe20007ffe0ff */
/*0470*/ UMOV UR8, 0x1 ; /* 0x0000000100087882 */
/* 0x000fe20000000000 */
/*0480*/ BSSY B1, 0x580 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0490*/ ULDC.64 UR4, c[0x2][0x0] ; /* 0x0080000000047ab9 */
/* 0x000fe20000000a00 */
/*04a0*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f26270 */
/*04b0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*04c0*/ IADD3 R8, R8, -0x2, RZ ; /* 0xfffffffe08087810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ UIMAD.WIDE.U32 UR4, UR8, UR6, UR4 ; /* 0x00000006080472a5 */
/* 0x000fe2000f8e0004 */
/*04e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*04f0*/ UIMAD UR7, UR8, UR7, URZ ; /* 0x00000007080772a4 */
/* 0x000fc8000f8e023f */
/*0500*/ UIADD3 UR7, UR5, UR7, URZ ; /* 0x0000000705077290 */
/* 0x000fe2000fffe03f */
/*0510*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe4000f8e00ff */
/*0520*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fc6000f8e00ff */
/*0530*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*0540*/ @!P1 BRA 0x570 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E R10, [R4.64] ; /* 0x0000000a040a7981 */
/* 0x000ea4000c1e1900 */
/*0560*/ ISETP.LT.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x004fd00003f01270 */
/*0570*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.LT.OR P0, PT, R8, RZ, !P0 ; /* 0x000000ff0800720c */
/* 0x000fe20004701670 */
/*0590*/ BSSY B1, 0x600 ; /* 0x0000006000017945 */
/* 0x000fd80003800000 */
/*05a0*/ @P0 BRA 0x5f0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*05b0*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc0a040d7981 */
/* 0x001ea4000c1e1900 */
/*05c0*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x004fda0003f06270 */
/*05d0*/ @!P0 BREAK B1 ; /* 0x0000000000018942 */
/* 0x000fe20003800000 */
/*05e0*/ @!P0 BRA 0x640 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*05f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0600*/ STS.U8 [R2+0xc00], RZ ; /* 0x000c00ff02007388 */
/* 0x0003e80000000000 */
/*0610*/ STS.U8 [R2+0xc02], RZ ; /* 0x000c02ff02007388 */
/* 0x0003e80000000000 */
/*0620*/ STS.U8 [R2+0xc01], RZ ; /* 0x000c01ff02007388 */
/* 0x0003e20000000000 */
/*0630*/ BRA 0x6f0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe400078e00ff */
/*0650*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fca00078e00ff */
/*0660*/ LDG.E.64 R4, [R10.64+0x8] ; /* 0x0000080a0a047981 */
/* 0x000ea2000c1e1b00 */
/*0670*/ IMAD R3, R13, R3, R8 ; /* 0x000000030d037224 */
/* 0x000fc800078e0208 */
/*0680*/ IMAD.WIDE R4, R3, 0x3, R4 ; /* 0x0000000303047825 */
/* 0x004fca00078e0204 */
/*0690*/ LDG.E.U8 R3, [R4.64] ; /* 0x0000000a04037981 */
/* 0x000ea8000c1e1100 */
/*06a0*/ LDG.E.U8 R13, [R4.64+0x2] ; /* 0x0000020a040d7981 */
/* 0x000ee8000c1e1100 */
/*06b0*/ LDG.E.U8 R15, [R4.64+0x1] ; /* 0x0000010a040f7981 */
/* 0x000f28000c1e1100 */
/*06c0*/ STS.U8 [R2+0xc00], R3 ; /* 0x000c000302007388 */
/* 0x0041e80000000000 */
/*06d0*/ STS.U8 [R2+0xc02], R13 ; /* 0x000c020d02007388 */
/* 0x0081e80000000000 */
/*06e0*/ STS.U8 [R2+0xc01], R15 ; /* 0x000c010f02007388 */
/* 0x0101e40000000000 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0720*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fc400078e00ff */
/*0730*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fc600078e00ff */
/*0740*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0750*/ LDG.E R5, [R4.64+0x4] ; /* 0x0000040a04057981 */
/* 0x000ea2000c1e1900 */
/*0760*/ IMAD R0, R0, 0x20, R9 ; /* 0x0000002000007824 */
/* 0x000fe200078e0209 */
/*0770*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0780*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0790*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x003fc8000f8e00ff */
/*07a0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*07b0*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f06270 */
/*07c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*07d0*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0a02087981 */
/* 0x000ea2000c1e1900 */
/*07e0*/ IMAD R7, R7, 0x20, R6 ; /* 0x0000002007077824 */
/* 0x000fca00078e0206 */
/*07f0*/ ISETP.GE.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x004fda0003f06270 */
/*0800*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0810*/ LDG.E.64 R4, [R2.64+0x4] ; /* 0x0000040a02047981 */
/* 0x000ea2000c1e1b00 */
/*0820*/ IMAD R6, R9, 0x24, R6 ; /* 0x0000002409067824 */
/* 0x000fc800078e0206 */
/*0830*/ IMAD R6, R6, 0x3, RZ ; /* 0x0000000306067824 */
/* 0x000fca00078e02ff */
/*0840*/ LDS.U8 R19, [R6] ; /* 0x0000000006137984 */
/* 0x000fe80000000000 */
/*0850*/ LDS.U8 R20, [R6+0x6c] ; /* 0x00006c0006147984 */
/* 0x000fe80000000000 */
/*0860*/ LDS.U8 R23, [R6+0xd8] ; /* 0x0000d80006177984 */
/* 0x000e280000000000 */
/*0870*/ LDS.U8 R24, [R6+0x144] ; /* 0x0001440006187984 */
/* 0x000fe80000000000 */
/*0880*/ LDS.U8 R25, [R6+0x1b0] ; /* 0x0001b00006197984 */
/* 0x000e680000000000 */
/*0890*/ LDS.U8 R21, [R6+0x3] ; /* 0x0000030006157984 */
/* 0x000fe80000000000 */
/*08a0*/ LDS.U8 R22, [R6+0x6f] ; /* 0x00006f0006167984 */
/* 0x000ee80000000000 */
/*08b0*/ LDS.U8 R17, [R6+0xdb] ; /* 0x0000db0006117984 */
/* 0x000fe80000000000 */
/*08c0*/ LDS.U8 R18, [R6+0x147] ; /* 0x0001470006127984 */
/* 0x000f280000000000 */
/*08d0*/ LDS.U8 R9, [R6+0x1b3] ; /* 0x0001b30006097984 */
/* 0x000fe80000000000 */
/*08e0*/ LDS.U8 R10, [R6+0x6] ; /* 0x00000600060a7984 */
/* 0x000f680000000000 */
/*08f0*/ LDS.U8 R11, [R6+0x72] ; /* 0x00007200060b7984 */
/* 0x000fe80000000000 */
/*0900*/ LDS.U8 R12, [R6+0xde] ; /* 0x0000de00060c7984 */
/* 0x000f620000000000 */
/*0910*/ IADD3 R23, R23, R19, R20 ; /* 0x0000001317177210 */
/* 0x001fc60007ffe014 */
/*0920*/ LDS.U8 R13, [R6+0x14a] ; /* 0x00014a00060d7984 */
/* 0x000fe80000000000 */
/*0930*/ LDS.U8 R14, [R6+0x1b6] ; /* 0x0001b600060e7984 */
/* 0x000e220000000000 */
/*0940*/ IADD3 R25, R25, R23, R24 ; /* 0x0000001719197210 */
/* 0x002fc60007ffe018 */
/*0950*/ LDS.U8 R15, [R6+0x9] ; /* 0x00000900060f7984 */
/* 0x000fe80000000000 */
/*0960*/ LDS.U8 R16, [R6+0x75] ; /* 0x0000750006107984 */
/* 0x000e620000000000 */
/*0970*/ IADD3 R25, R22, R25, R21 ; /* 0x0000001916197210 */
/* 0x008fc60007ffe015 */
/*0980*/ LDS.U8 R19, [R6+0xe1] ; /* 0x0000e10006137984 */
/* 0x000fe80000000000 */
/*0990*/ LDS.U8 R20, [R6+0x14d] ; /* 0x00014d0006147984 */
/* 0x000ee20000000000 */
/*09a0*/ IADD3 R25, R18, R25, R17 ; /* 0x0000001912197210 */
/* 0x010fc60007ffe011 */
/*09b0*/ LDS.U8 R24, [R6+0x1b9] ; /* 0x0001b90006187984 */
/* 0x000fe80000000000 */
/*09c0*/ LDS.U8 R23, [R6+0xc] ; /* 0x00000c0006177984 */
/* 0x000f220000000000 */
/*09d0*/ IADD3 R9, R10, R25, R9 ; /* 0x000000190a097210 */
/* 0x020fc60007ffe009 */
/*09e0*/ LDS.U8 R22, [R6+0x78] ; /* 0x0000780006167984 */
/* 0x000fe80000000000 */
/*09f0*/ LDS.U8 R21, [R6+0xe4] ; /* 0x0000e40006157984 */
/* 0x000f620000000000 */
/*0a00*/ IADD3 R9, R12, R9, R11 ; /* 0x000000090c097210 */
/* 0x000fe20007ffe00b */
/*0a10*/ IMAD R11, R0, R8, R7 ; /* 0x00000008000b7224 */
/* 0x000fe400078e0207 */
/*0a20*/ LDS.U8 R18, [R6+0x150] ; /* 0x0001500006127984 */
/* 0x000fe80000000000 */
/*0a30*/ LDS.U8 R17, [R6+0x1bc] ; /* 0x0001bc0006117984 */
/* 0x000f620000000000 */
/*0a40*/ IADD3 R9, R14, R9, R13 ; /* 0x000000090e097210 */
/* 0x001fc60007ffe00d */
/*0a50*/ LDS.U8 R25, [R6+0x1b2] ; /* 0x0001b20006197984 */
/* 0x000fe20000000000 */
/*0a60*/ IADD3 R9, R16, R9, R15 ; /* 0x0000000910097210 */
/* 0x002fc60007ffe00f */
/*0a70*/ LDS.U8 R12, [R6+0xe0] ; /* 0x0000e000060c7984 */
/* 0x000fe80000000000 */
/*0a80*/ LDS.U8 R13, [R6+0x14c] ; /* 0x00014c00060d7984 */
/* 0x000fe20000000000 */
/*0a90*/ IADD3 R9, R20, R9, R19 ; /* 0x0000000914097210 */
/* 0x008fc60007ffe013 */
/*0aa0*/ LDS.U8 R14, [R6+0x1b8] ; /* 0x0001b800060e7984 */
/* 0x000fe80000000000 */
/*0ab0*/ LDS.U8 R19, [R6+0x2] ; /* 0x0000020006137984 */
/* 0x000fe20000000000 */
/*0ac0*/ IADD3 R9, R23, R9, R24 ; /* 0x0000000917097210 */
/* 0x010fc60007ffe018 */
/*0ad0*/ LDS.U8 R20, [R6+0x6e] ; /* 0x00006e0006147984 */
/* 0x000fe80000000000 */
/*0ae0*/ LDS.U8 R23, [R6+0xda] ; /* 0x0000da0006177984 */
/* 0x000e220000000000 */
/*0af0*/ IADD3 R9, R21, R9, R22 ; /* 0x0000000915097210 */
/* 0x020fc60007ffe016 */
/*0b00*/ LDS.U8 R24, [R6+0x146] ; /* 0x0001460006187984 */
/* 0x000e680000000000 */
/*0b10*/ LDS.U8 R21, [R6+0x5] ; /* 0x0000050006157984 */
/* 0x000fe20000000000 */
/*0b20*/ IADD3 R9, R17, R9, R18 ; /* 0x0000000911097210 */
/* 0x000fc60007ffe012 */
/*0b30*/ LDS.U8 R22, [R6+0x71] ; /* 0x0000710006167984 */
/* 0x000ee40000000000 */
/*0b40*/ IMAD.HI R9, R9, 0x51eb851f, RZ ; /* 0x51eb851f09097827 */
/* 0x000fe400078e02ff */
/*0b50*/ LDS.U8 R17, [R6+0xdd] ; /* 0x0000dd0006117984 */
/* 0x000fe60000000000 */
/*0b60*/ SHF.R.U32.HI R8, RZ, 0x1f, R9 ; /* 0x0000001fff087819 */
/* 0x000fe20000011609 */
/*0b70*/ LDS.U8 R18, [R6+0x149] ; /* 0x0001490006127984 */
/* 0x000f260000000000 */
/*0b80*/ LEA.HI R9, R9, R8, RZ, 0x1d ; /* 0x0000000809097211 */
/* 0x000fe200078fe8ff */
/*0b90*/ LDS.U8 R15, [R6+0xb] ; /* 0x00000b00060f7984 */
/* 0x000fe80000000000 */
/*0ba0*/ LDS.U8 R16, [R6+0x77] ; /* 0x0000770006107984 */
/* 0x000fe20000000000 */
/*0bb0*/ IMAD.WIDE R10, R11, 0x3, R4 ; /* 0x000000030b0a7825 */
/* 0x004fca00078e0204 */
/*0bc0*/ STG.E.U8 [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x000fe8000c10110a */
/*0bd0*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0a02087981 */
/* 0x000ea8000c1e1900 */
/*0be0*/ LDG.E.64 R4, [R2.64+0x4] ; /* 0x0000040a02047981 */
/* 0x000f62000c1e1b00 */
/*0bf0*/ IADD3 R23, R23, R19, R20 ; /* 0x0000001317177210 */
/* 0x001fc60007ffe014 */
/*0c00*/ LDS.U8 R9, [R6+0x1b5] ; /* 0x0001b50006097984 */
/* 0x000fe20000000000 */
/*0c10*/ IADD3 R25, R25, R23, R24 ; /* 0x0000001719197210 */
/* 0x002fc60007ffe018 */
/*0c20*/ LDS.U8 R10, [R6+0x8] ; /* 0x00000800060a7984 */
/* 0x000e220000000000 */
/*0c30*/ IADD3 R25, R22, R25, R21 ; /* 0x0000001916197210 */
/* 0x008fc60007ffe015 */
/*0c40*/ LDS.U8 R11, [R6+0x74] ; /* 0x00007400060b7984 */
/* 0x000e620000000000 */
/*0c50*/ IADD3 R25, R18, R25, R17 ; /* 0x0000001912197210 */
/* 0x010fc60007ffe011 */
/*0c60*/ LDS.U8 R19, [R6+0xe3] ; /* 0x0000e30006137984 */
/* 0x000fe80000000000 */
/*0c70*/ LDS.U8 R20, [R6+0x14f] ; /* 0x00014f0006147984 */
/* 0x000ee80000000000 */
/*0c80*/ LDS.U8 R24, [R6+0x1bb] ; /* 0x0001bb0006187984 */
/* 0x000fe80000000000 */
/*0c90*/ LDS.U8 R23, [R6+0xe] ; /* 0x00000e0006177984 */
/* 0x000f280000000000 */
/*0ca0*/ LDS.U8 R22, [R6+0x7a] ; /* 0x00007a0006167984 */
/* 0x000fe80000000000 */
/*0cb0*/ LDS.U8 R21, [R6+0xe6] ; /* 0x0000e60006157984 */
/* 0x000f280000000000 */
/*0cc0*/ LDS.U8 R18, [R6+0x152] ; /* 0x0001520006127984 */
/* 0x000fe80000000000 */
/*0cd0*/ LDS.U8 R17, [R6+0x1be] ; /* 0x0001be0006117984 */
/* 0x000f220000000000 */
/*0ce0*/ IADD3 R9, R10, R25, R9 ; /* 0x000000190a097210 */
/* 0x001fc80007ffe009 */
/*0cf0*/ IADD3 R9, R12, R9, R11 ; /* 0x000000090c097210 */
/* 0x002fe40007ffe00b */
/*0d00*/ LDS.U8 R12, [R6+0x1b7] ; /* 0x0001b700060c7984 */
/* 0x000fe40000000000 */
/*0d10*/ IADD3 R9, R14, R9, R13 ; /* 0x000000090e097210 */
/* 0x000fe40007ffe00d */
/*0d20*/ LDS.U8 R13, [R6+0xdc] ; /* 0x0000dc00060d7984 */
/* 0x000fe40000000000 */
/*0d30*/ IADD3 R9, R16, R9, R15 ; /* 0x0000000910097210 */
/* 0x000fe40007ffe00f */
/*0d40*/ LDS.U8 R15, [R6+0x1] ; /* 0x00000100060f7984 */
/* 0x000fe40000000000 */
/*0d50*/ IADD3 R9, R20, R9, R19 ; /* 0x0000000914097210 */
/* 0x008fc40007ffe013 */
/*0d60*/ LDS.U8 R16, [R6+0x6d] ; /* 0x00006d0006107984 */
/* 0x000fe40000000000 */
/*0d70*/ IADD3 R9, R23, R9, R24 ; /* 0x0000000917097210 */
/* 0x010fe40007ffe018 */
/*0d80*/ LDS.U8 R19, [R6+0x1b1] ; /* 0x0001b10006137984 */
/* 0x000fe80000000000 */
/*0d90*/ LDS.U8 R20, [R6+0x4] ; /* 0x0000040006147984 */
/* 0x000fe20000000000 */
/*0da0*/ IADD3 R9, R21, R9, R22 ; /* 0x0000000915097210 */
/* 0x000fc60007ffe016 */
/*0db0*/ LDS.U8 R21, [R6+0x70] ; /* 0x0000700006157984 */
/* 0x000fe80000000000 */
/*0dc0*/ LDS.U8 R14, [R6+0x148] ; /* 0x00014800060e7984 */
/* 0x000fe20000000000 */
/*0dd0*/ IADD3 R9, R17, R9, R18 ; /* 0x0000000911097210 */
/* 0x000fc60007ffe012 */
/*0de0*/ LDS.U8 R17, [R6+0xd9] ; /* 0x0000d90006117984 */
/* 0x000e240000000000 */
/*0df0*/ IMAD.HI R9, R9, 0x51eb851f, RZ ; /* 0x51eb851f09097827 */
/* 0x000fe400078e02ff */
/*0e00*/ LDS.U8 R18, [R6+0x145] ; /* 0x0001450006127984 */
/* 0x000e660000000000 */
/*0e10*/ SHF.R.U32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fe20000011609 */
/*0e20*/ LDS.U8 R22, [R6+0xe5] ; /* 0x0000e50006167984 */
/* 0x000fe60000000000 */
/*0e30*/ LEA.HI R9, R9, R10, RZ, 0x1d ; /* 0x0000000a09097211 */
/* 0x000fe200078fe8ff */
/*0e40*/ LDS.U8 R23, [R6+0x1bd] ; /* 0x0001bd0006177984 */
/* 0x000fe20000000000 */
/*0e50*/ IMAD R11, R0, R8, R7 ; /* 0x00000008000b7224 */
/* 0x004fc800078e0207 */
/*0e60*/ IMAD.WIDE R10, R11, 0x3, R4 ; /* 0x000000030b0a7825 */
/* 0x020fca00078e0204 */
/*0e70*/ STG.E.U8 [R10.64+0x2], R9 ; /* 0x000002090a007986 */
/* 0x000fe8000c10110a */
/*0e80*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0a02087981 */
/* 0x0004e8000c1e1900 */
/*0e90*/ LDG.E.64 R4, [R2.64+0x4] ; /* 0x0000040a02047981 */
/* 0x000522000c1e1b00 */
/*0ea0*/ IADD3 R17, R17, R15, R16 ; /* 0x0000000f11117210 */
/* 0x001fc60007ffe010 */
/*0eb0*/ LDS.U8 R9, [R6+0x1b4] ; /* 0x0001b40006097984 */
/* 0x000fe20000000000 */
/*0ec0*/ IADD3 R19, R19, R17, R18 ; /* 0x0000001113137210 */
/* 0x002fc60007ffe012 */
/*0ed0*/ LDS.U8 R10, [R6+0xdf] ; /* 0x0000df00060a7984 */
/* 0x000fe20000000000 */
/*0ee0*/ IADD3 R21, R21, R19, R20 ; /* 0x0000001315157210 */
/* 0x000fc60007ffe014 */
/*0ef0*/ LDS.U8 R2, [R6+0x7] ; /* 0x0000070006027984 */
/* 0x004e220000000000 */
/*0f00*/ IADD3 R14, R14, R21, R13 ; /* 0x000000150e0e7210 */
/* 0x000fc60007ffe00d */
/*0f10*/ LDS.U8 R3, [R6+0x73] ; /* 0x0000730006037984 */
/* 0x000e680000000000 */
/*0f20*/ LDS.U8 R11, [R6+0x14b] ; /* 0x00014b00060b7984 */
/* 0x000ea80000000000 */
/*0f30*/ LDS.U8 R16, [R6+0xa] ; /* 0x00000a0006107984 */
/* 0x000fe80000000000 */
/*0f40*/ LDS.U8 R15, [R6+0x76] ; /* 0x00007600060f7984 */
/* 0x000f680000000000 */
/*0f50*/ LDS.U8 R18, [R6+0xe2] ; /* 0x0000e20006127984 */
/* 0x000fe80000000000 */
/*0f60*/ LDS.U8 R17, [R6+0x14e] ; /* 0x00014e0006117984 */
/* 0x000f680000000000 */
/*0f70*/ LDS.U8 R20, [R6+0x1ba] ; /* 0x0001ba0006147984 */
/* 0x000fe80000000000 */
/*0f80*/ LDS.U8 R19, [R6+0xd] ; /* 0x00000d0006137984 */
/* 0x000f680000000000 */
/*0f90*/ LDS.U8 R21, [R6+0x79] ; /* 0x0000790006157984 */
/* 0x000f680000000000 */
/*0fa0*/ LDS.U8 R13, [R6+0x151] ; /* 0x00015100060d7984 */
/* 0x000f620000000000 */
/*0fb0*/ IADD3 R2, R2, R14, R9 ; /* 0x0000000e02027210 */
/* 0x001fc80007ffe009 */
/*0fc0*/ IADD3 R2, R10, R2, R3 ; /* 0x000000020a027210 */
/* 0x002fc80007ffe003 */
/*0fd0*/ IADD3 R2, R12, R2, R11 ; /* 0x000000020c027210 */
/* 0x004fc80007ffe00b */
/*0fe0*/ IADD3 R2, R15, R2, R16 ; /* 0x000000020f027210 */
/* 0x020fc80007ffe010 */
/*0ff0*/ IADD3 R2, R17, R2, R18 ; /* 0x0000000211027210 */
/* 0x000fc80007ffe012 */
/*1000*/ IADD3 R2, R19, R2, R20 ; /* 0x0000000213027210 */
/* 0x000fc80007ffe014 */
/*1010*/ IADD3 R2, R22, R2, R21 ; /* 0x0000000216027210 */
/* 0x000fc80007ffe015 */
/*1020*/ IADD3 R2, R23, R2, R13 ; /* 0x0000000217027210 */
/* 0x000fca0007ffe00d */
/*1030*/ IMAD.HI R2, R2, 0x51eb851f, RZ ; /* 0x51eb851f02027827 */
/* 0x000fca00078e02ff */
/*1040*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*1050*/ LEA.HI R3, R2, R3, RZ, 0x1d ; /* 0x0000000302037211 */
/* 0x000fe200078fe8ff */
/*1060*/ IMAD R7, R0, R8, R7 ; /* 0x0000000800077224 */
/* 0x008fc800078e0207 */
/*1070*/ IMAD.WIDE R4, R7, 0x3, R4 ; /* 0x0000000307047825 */
/* 0x010fca00078e0204 */
/*1080*/ STG.E.U8 [R4.64+0x1], R3 ; /* 0x0000010304007986 */
/* 0x000fe2000c10110a */
/*1090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10a0*/ BRA 0x10a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16smoothing_kernelP8PPMImageS0_
.globl _Z16smoothing_kernelP8PPMImageS0_
.p2align 8
.type _Z16smoothing_kernelP8PPMImageS0_,@function
_Z16smoothing_kernelP8PPMImageS0_:
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_lshl_b32 s2, s15, 5
s_lshl_b32 s1, s14, 5
s_add_i32 s3, s2, -2
s_add_i32 s8, s1, -2
v_lshl_add_u32 v3, v1, 5, v2
s_mov_b32 s9, 0
s_branch .LBB0_3
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt vmcnt(0) lgkmcnt(0)
ds_store_b8 v6, v7 offset:1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
s_addk_i32 s9, 0x400
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s9, 0x400
s_cbranch_scc0 .LBB0_12
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s9, v3
s_mov_b32 s10, exec_lo
v_cmpx_gt_u32_e32 0x510, v6
s_cbranch_execz .LBB0_2
v_mul_hi_u32 v5, v6, 0x38e38e39
s_mov_b32 s0, 0
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v7, 3, v5
v_add_nc_u32_e32 v5, s3, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e64 s11, 0, v5
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB0_8
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[4:5], 0x4
v_mul_lo_u32 v0, v7, 36
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v6, v0
v_add_nc_u32_e32 v0, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s0, v5
s_and_b32 s15, vcc_lo, s0
s_mov_b32 s0, 0
s_xor_b32 s13, s15, -1
s_and_saveexec_b32 s14, s15
s_cbranch_execz .LBB0_7
s_load_b32 s15, s[4:5], 0x0
s_and_not1_b32 s13, s13, exec_lo
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s15, v0
v_mov_b32_e32 v4, s15
s_and_b32 s15, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s13, s13, s15
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s11, s11, exec_lo
s_and_b32 s13, s13, exec_lo
s_and_b32 s0, s0, exec_lo
s_or_b32 s11, s11, s13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s12
v_lshl_add_u32 v6, v6, 1, v6
s_and_saveexec_b32 s13, s11
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v7, 0
s_mov_b32 s12, 0
s_and_not1_b32 s0, s0, exec_lo
ds_store_b8 v6, v7
ds_store_b8 v6, v7 offset:2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v7, s12
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_1
s_waitcnt lgkmcnt(0)
s_load_b64 s[12:13], s[6:7], 0x8
v_mad_u64_u32 v[7:8], null, v4, v5, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_i64_i32 v[8:9], null, v7, 3, s[12:13]
s_clause 0x2
flat_load_u8 v5, v[8:9]
flat_load_u8 v10, v[8:9] offset:2
flat_load_u8 v7, v[8:9] offset:1
s_waitcnt vmcnt(2) lgkmcnt(2)
ds_store_b8 v6, v5
s_waitcnt vmcnt(1) lgkmcnt(2)
ds_store_b8 v6, v10 offset:2
s_branch .LBB0_1
.LBB0_12:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s0, s[4:5], 0x4
v_add_nc_u32_e32 v3, s2, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v3
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b32 s0, s[4:5], 0x0
v_add_nc_u32_e32 v0, s1, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
v_mul_u32_u24_e32 v5, 3, v2
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v2, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3)
v_mad_u32_u24 v5, v1, 0x6c, v5
v_mov_b32_e32 v1, 0
.p2align 6
.LBB0_15:
s_mov_b32 s2, 0
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v6, s2, v5
s_addk_i32 s2, 0x6c
ds_load_u8 v7, v6
ds_load_u8 v8, v6 offset:2
ds_load_u8 v6, v6 offset:1
s_cmpk_lg_i32 s2, 0x21c
s_waitcnt lgkmcnt(2)
v_add_nc_u32_e32 v4, v4, v7
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v2, v2, v8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v6
s_cbranch_scc1 .LBB0_16
v_add_nc_u32_e32 v5, 3, v5
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 5
s_cbranch_scc1 .LBB0_15
s_load_b64 s[2:3], s[4:5], 0x8
v_mul_hi_i32 v4, v4, 0x51eb851f
v_mul_hi_i32 v5, v2, 0x51eb851f
v_mul_hi_i32 v6, v1, 0x51eb851f
v_mad_u64_u32 v[1:2], null, s0, v3, v[0:1]
s_delay_alu instid0(VALU_DEP_4)
v_lshrrev_b32_e32 v0, 31, v4
v_lshrrev_b32_e32 v4, 3, v4
v_lshrrev_b32_e32 v7, 31, v5
v_lshrrev_b32_e32 v5, 3, v5
v_lshrrev_b32_e32 v8, 31, v6
v_lshrrev_b32_e32 v6, 3, v6
v_add_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v4, v6, v8
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 3, s[2:3]
v_add_nc_u32_e32 v1, v5, v7
s_clause 0x2
flat_store_b8 v[2:3], v0
flat_store_b8 v[2:3], v1 offset:2
flat_store_b8 v[2:3], v4 offset:1
.LBB0_19:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16smoothing_kernelP8PPMImageS0_
.amdhsa_group_segment_fixed_size 3888
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16smoothing_kernelP8PPMImageS0_, .Lfunc_end0-_Z16smoothing_kernelP8PPMImageS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 3888
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16smoothing_kernelP8PPMImageS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16smoothing_kernelP8PPMImageS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0007f4e4_00000000-6_smooth_gpu.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "Unable to open file '%s'\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Invalid image format (must be 'P6')\n"
.section .rodata.str1.1
.LC3:
.string "Unable to allocate memory\n"
.LC4:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC5:
.string "Invalid image size (error loading '%s')\n"
.section .rodata.str1.1
.LC6:
.string "%d"
.section .rodata.str1.8
.align 8
.LC7:
.string "Invalid rgb component (error loading '%s')\n"
.align 8
.LC8:
.string "'%s' does not have 8-bits components\n"
.section .rodata.str1.1
.LC9:
.string "Error loading image '%s'\n"
#NO_APP
.text
.type _ZL7readPPMPKc, @function
_ZL7readPPMPKc:
.LFB2058:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L20
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %rax, %rcx
movl $16, %edx
movl $16, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L21
cmpb $80, 16(%rsp)
jne .L4
cmpb $54, 17(%rsp)
jne .L4
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L22
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
jne .L7
.L8:
movq %rbx, %rdi
call getc@PLT
cmpl $10, %eax
jne .L8
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
je .L8
.L7:
movq %rbx, %rsi
movl %eax, %edi
call ungetc@PLT
leaq 4(%rbp), %rcx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L23
leaq 12(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L24
cmpl $255, 12(%rsp)
jne .L25
.L12:
movq %rbx, %rdi
call fgetc@PLT
cmpl $10, %eax
jne .L12
movl 0(%rbp), %r14d
movl 4(%rbp), %r13d
movl %r14d, %eax
imull %r13d, %eax
cltq
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%rbp)
movslq %r13d, %rcx
leal (%r14,%r14,2), %edx
movslq %edx, %rdx
movq %rbx, %r8
movq %r15, %rsi
call __fread_chk@PLT
movslq 4(%rbp), %rdx
cmpq %rax, %rdx
jne .L26
movq %rbx, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movq %rbp, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq %r12, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L21:
movq %r12, %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L4:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L23:
movq %r12, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq %r12, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movq %r12, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movq %r12, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZL7readPPMPKc, .-_ZL7readPPMPKc
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8
.align 8
.LC10:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L34
.L31:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC11(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.section .rodata.str1.1
.LC12:
.string "P6\n"
.LC13:
.string "Histogram_GPU"
.LC14:
.string "# %s\n"
.LC15:
.string "%d %d\n"
.LC16:
.string "%d\n"
.text
.globl _Z8writePPMP8PPMImage
.type _Z8writePPMP8PPMImage, @function
_Z8writePPMP8PPMImage:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl (%rbx), %ecx
movl 4(%rbx), %r8d
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $255, %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq 4(%rbx), %rdx
movl (%rbx), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
movq 8(%rbx), %rdi
movq stdout(%rip), %rcx
call fwrite@PLT
movq stdout(%rip), %rdi
call fclose@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8writePPMP8PPMImage, .-_Z8writePPMP8PPMImage
.globl _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_
.type _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_, @function
_Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16smoothing_kernelP8PPMImageS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_, .-_Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_
.globl _Z16smoothing_kernelP8PPMImageS0_
.type _Z16smoothing_kernelP8PPMImageS0_, @function
_Z16smoothing_kernelP8PPMImageS0_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z16smoothing_kernelP8PPMImageS0_, .-_Z16smoothing_kernelP8PPMImageS0_
.globl _Z13smoothing_GPUP8PPMImageS0_
.type _Z13smoothing_GPUP8PPMImageS0_, @function
_Z13smoothing_GPUP8PPMImageS0_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl (%rdi), %r12d
movl 4(%rdi), %r13d
movl %r12d, %ebp
imull %r13d, %ebp
movq %rsp, %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl %ebp, %eax
leaq (%rax,%rax,2), %rbp
leaq 16(%rsp), %r15
movq %rbp, %rsi
movq %r15, %rdi
call cudaMalloc@PLT
leaq 24(%rsp), %r14
movq %rbp, %rsi
movq %r14, %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $16, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rbx), %rsi
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %ecx
movl $8, %edx
movq %r15, %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rbx), %rsi
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %ecx
movl $8, %edx
movq %r14, %rsi
call cudaMemcpy@PLT
movl %r13d, %r13d
pxor %xmm0, %xmm0
cvtsi2ssq %r13, %xmm0
mulss .LC17(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC21(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC18(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L49
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC20(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L49:
movl %r12d, %r12d
pxor %xmm0, %xmm0
cvtsi2ssq %r12, %xmm0
mulss .LC17(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC21(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC18(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L52
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC20(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L52:
cvttss2siq %xmm4, %rax
movl %eax, 32(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L53:
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movl $16, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, 8(%rbx)
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z47__device_stub__Z16smoothing_kernelP8PPMImageS0_P8PPMImageS0_
jmp .L53
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z13smoothing_GPUP8PPMImageS0_, .-_Z13smoothing_GPUP8PPMImageS0_
.section .rodata.str1.8
.align 8
.LC22:
.string "Too many or no one arguments supplied.\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
cmpl $2, %edi
jne .L61
.L59:
movq 8(%rbx), %rbx
movq %rbx, %rdi
call _ZL7readPPMPKc
movq %rax, %rbp
movq %rbx, %rdi
call _ZL7readPPMPKc
movq %rax, %rbx
movq %rbp, %rsi
movq %rax, %rdi
call _Z13smoothing_GPUP8PPMImageS0_
movq %rbx, %rdi
call _Z8writePPMP8PPMImage
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L59
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC23:
.string "_Z16smoothing_kernelP8PPMImageS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z16smoothing_kernelP8PPMImageS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long 1023410176
.align 4
.LC18:
.long 1258291200
.align 4
.LC20:
.long 1065353216
.align 4
.LC21:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "smooth_gpu.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z8writePPMP8PPMImage # -- Begin function _Z8writePPMP8PPMImage
.p2align 4, 0x90
.type _Z8writePPMP8PPMImage,@function
_Z8writePPMP8PPMImage: # @_Z8writePPMP8PPMImage
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
callq fwrite
movq stdout(%rip), %rdi
movl $.L.str.2, %esi
movl $.L.str.3, %edx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl (%rbx), %edx
movl 4(%rbx), %ecx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl $.L.str.5, %esi
movl $255, %edx
xorl %eax, %eax
callq fprintf
movq 8(%rbx), %rdi
movslq (%rbx), %rax
leaq (%rax,%rax,2), %rsi
movslq 4(%rbx), %rdx
movq stdout(%rip), %rcx
callq fwrite
movq stdout(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z8writePPMP8PPMImage, .Lfunc_end1-_Z8writePPMP8PPMImage
.cfi_endproc
# -- End function
.globl _Z31__device_stub__smoothing_kernelP8PPMImageS0_ # -- Begin function _Z31__device_stub__smoothing_kernelP8PPMImageS0_
.p2align 4, 0x90
.type _Z31__device_stub__smoothing_kernelP8PPMImageS0_,@function
_Z31__device_stub__smoothing_kernelP8PPMImageS0_: # @_Z31__device_stub__smoothing_kernelP8PPMImageS0_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16smoothing_kernelP8PPMImageS0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z31__device_stub__smoothing_kernelP8PPMImageS0_, .Lfunc_end2-_Z31__device_stub__smoothing_kernelP8PPMImageS0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13smoothing_GPUP8PPMImageS0_
.LCPI3_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z13smoothing_GPUP8PPMImageS0_
.p2align 4, 0x90
.type _Z13smoothing_GPUP8PPMImageS0_,@function
_Z13smoothing_GPUP8PPMImageS0_: # @_Z13smoothing_GPUP8PPMImageS0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl (%rdi), %ebp
movl 4(%rdi), %r13d
movl %r13d, %r14d
imull %ebp, %r14d
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq (%r14,%r14,2), %r14
leaq 16(%rsp), %r12
movq %r12, %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %r15
movq %r15, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 8(%rbx), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
addq $8, %rdi
movl $8, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 8(%rbx), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
addq $8, %rdi
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %rbp, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r15
xorps %xmm0, %xmm0
cvtsi2ss %r13, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %r15d, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16smoothing_kernelP8PPMImageS0_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq (%rsp), %rsi
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r15, 8(%rbx)
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z13smoothing_GPUP8PPMImageS0_, .Lfunc_end3-_Z13smoothing_GPUP8PPMImageS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
cmpl $2, %edi
je .LBB4_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB4_2:
movq 8(%rbx), %r14
movq %r14, %rdi
callq _ZL7readPPMPKc
movq %rax, %rbx
movq %r14, %rdi
callq _ZL7readPPMPKc
movq %rax, %r14
movq %rax, %rdi
callq _Z13smoothing_GPUP8PPMImageS0_
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
callq fwrite
movq stdout(%rip), %rdi
movl $.L.str.2, %esi
movl $.L.str.3, %edx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl (%r14), %edx
movl 4(%r14), %ecx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl $.L.str.5, %esi
movl $255, %edx
xorl %eax, %eax
callq fprintf
movq 8(%r14), %rdi
movslq (%r14), %rax
leaq (%rax,%rax,2), %rsi
movslq 4(%r14), %rdx
movq stdout(%rip), %rcx
callq fwrite
movq stdout(%rip), %rdi
callq fclose
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL7readPPMPKc
.type _ZL7readPPMPKc,@function
_ZL7readPPMPKc: # @_ZL7readPPMPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.7, %esi
callq fopen
testq %rax, %rax
je .LBB5_1
# %bb.3:
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $16, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB5_23
# %bb.4:
cmpb $80, 16(%rsp)
jne .LBB5_6
# %bb.5:
cmpb $54, 17(%rsp)
jne .LBB5_6
# %bb.8:
movl $16, %edi
callq malloc
testq %rax, %rax
je .LBB5_9
# %bb.10:
movq %rax, %r15
.p2align 4, 0x90
.LBB5_11: # =>This Loop Header: Depth=1
# Child Loop BB5_12 Depth 2
movq %r14, %rdi
callq getc
cmpl $35, %eax
jne .LBB5_13
.LBB5_12: # %.preheader44
# Parent Loop BB5_11 Depth=1
# => This Inner Loop Header: Depth=2
movq %r14, %rdi
callq getc
cmpl $10, %eax
jne .LBB5_12
jmp .LBB5_11
.LBB5_13: # %._crit_edge
movl %eax, %edi
movq %r14, %rsi
callq ungetc
movq %r15, %rcx
addq $4, %rcx
movl $.L.str.11, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB5_14
# %bb.15:
leaq 12(%rsp), %rdx
movl $.L.str.13, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB5_16
# %bb.17:
cmpl $255, 12(%rsp)
jne .LBB5_18
.p2align 4, 0x90
.LBB5_19: # %.preheader
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq fgetc
cmpl $10, %eax
jne .LBB5_19
# %bb.20:
movslq (%r15), %rax
movslq 4(%r15), %r12
leaq (%rax,%rax,2), %r13
movq %r13, %rdi
imulq %r12, %rdi
callq malloc
movq %rax, 8(%r15)
movq %rax, %rdi
movq %r13, %rsi
movq %r12, %rdx
movq %r14, %rcx
callq fread
movslq 4(%r15), %rcx
cmpq %rcx, %rax
jne .LBB5_21
# %bb.22:
movq %r14, %rdi
callq fclose
movq %r15, %rax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_1:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
jmp .LBB5_2
.LBB5_23:
movq %rbx, %rdi
callq perror
movl $1, %edi
callq exit
.LBB5_6:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $36, %esi
jmp .LBB5_7
.LBB5_9:
movq stderr(%rip), %rcx
movl $.L.str.10, %edi
movl $26, %esi
.LBB5_7:
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.LBB5_14:
movq stderr(%rip), %rdi
movl $.L.str.12, %esi
jmp .LBB5_2
.LBB5_16:
movq stderr(%rip), %rdi
movl $.L.str.14, %esi
jmp .LBB5_2
.LBB5_18:
movq stderr(%rip), %rdi
movl $.L.str.15, %esi
jmp .LBB5_2
.LBB5_21:
movq stderr(%rip), %rdi
movl $.L.str.16, %esi
.LBB5_2:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end5:
.size _ZL7readPPMPKc, .Lfunc_end5-_ZL7readPPMPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16smoothing_kernelP8PPMImageS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "P6\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "# %s\n"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Histogram_GPU"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %d\n"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type _Z16smoothing_kernelP8PPMImageS0_,@object # @_Z16smoothing_kernelP8PPMImageS0_
.section .rodata,"a",@progbits
.globl _Z16smoothing_kernelP8PPMImageS0_
.p2align 3, 0x0
_Z16smoothing_kernelP8PPMImageS0_:
.quad _Z31__device_stub__smoothing_kernelP8PPMImageS0_
.size _Z16smoothing_kernelP8PPMImageS0_, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "rb"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Unable to open file '%s'\n"
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Invalid image format (must be 'P6')\n"
.size .L.str.9, 37
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Unable to allocate memory\n"
.size .L.str.10, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%d %d"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Invalid image size (error loading '%s')\n"
.size .L.str.12, 41
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%d"
.size .L.str.13, 3
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Invalid rgb component (error loading '%s')\n"
.size .L.str.14, 44
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "'%s' does not have 8-bits components\n"
.size .L.str.15, 38
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Error loading image '%s'\n"
.size .L.str.16, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16smoothing_kernelP8PPMImageS0_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too many or no one arguments supplied."
.size .Lstr, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__smoothing_kernelP8PPMImageS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16smoothing_kernelP8PPMImageS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 10;
// Device input vectors
double *d_a;
// Size, in bytes, of each vector
size_t bytes = n*sizeof(double);
// Allocate memory for each vector on GPU
cudaMalloc(&d_a, bytes);
// Free memory
cudaFree(d_a);
return 0;
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 10;
// Device input vectors
double *d_a;
// Size, in bytes, of each vector
size_t bytes = n*sizeof(double);
// Allocate memory for each vector on GPU
cudaMalloc(&d_a, bytes);
// Free memory
cudaFree(d_a);
return 0;
}
|
.file "tmpxft_00169a73_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $80, %esi
call cudaMalloc@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 10;
// Device input vectors
double *d_a;
// Size, in bytes, of each vector
size_t bytes = n*sizeof(double);
// Allocate memory for each vector on GPU
cudaMalloc(&d_a, bytes);
// Free memory
cudaFree(d_a);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 10;
// Device input vectors
double *d_a;
// Size, in bytes, of each vector
size_t bytes = n*sizeof(double);
// Allocate memory for each vector on GPU
hipMalloc(&d_a, bytes);
// Free memory
hipFree(d_a);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 10;
// Device input vectors
double *d_a;
// Size, in bytes, of each vector
size_t bytes = n*sizeof(double);
// Allocate memory for each vector on GPU
hipMalloc(&d_a, bytes);
// Free memory
hipFree(d_a);
return 0;
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
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