system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/**
* Given a input tensor x with shape (N, C, D), compute x.mean(2).mean(0)
* This function is useful in batch normalization.
* Refer to https://people.maths.ox.ac.uk/gilesm/cuda/prac4/reduction.pdf.
* But the unrolling warps seems to be not working correctly for now.
*/
const int N = 256;
const int C = 1024;
const int D = 28*28;
__global__ void reduce0(const float* in, float* out) {
__shared__ float buffer[CUDA_NUM_THREADS];
const unsigned int tid = threadIdx.x;
const unsigned int c = blockIdx.x;
// load and accumulate data to buffer
buffer[tid] = 0;
for (int i = tid; i < N * D; i += blockDim.x) {
const unsigned int n = i / D;
const unsigned int d = i % D;
const unsigned int index = n * C * D + c * D + d;
buffer[tid] += in[index];
}
__syncthreads();
// do tree reduction in buffer
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) { // <-- bad: divergent branching
buffer[tid] += buffer[tid + s];
}
__syncthreads();
}
if (tid == 0) out[c] = buffer[0] / (N * D);
} | .file "tmpxft_00185182_00000000-6_reduce0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7reduce0PKfPfPKfPf
.type _Z29__device_stub__Z7reduce0PKfPfPKfPf, @function
_Z29__device_stub__Z7reduce0PKfPfPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce0PKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z7reduce0PKfPfPKfPf, .-_Z29__device_stub__Z7reduce0PKfPfPKfPf
.globl _Z7reduce0PKfPf
.type _Z7reduce0PKfPf, @function
_Z7reduce0PKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7reduce0PKfPfPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7reduce0PKfPf, .-_Z7reduce0PKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7reduce0PKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce0PKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/**
* Given a input tensor x with shape (N, C, D), compute x.mean(2).mean(0)
* This function is useful in batch normalization.
* Refer to https://people.maths.ox.ac.uk/gilesm/cuda/prac4/reduction.pdf.
* But the unrolling warps seems to be not working correctly for now.
*/
const int N = 256;
const int C = 1024;
const int D = 28*28;
__global__ void reduce0(const float* in, float* out) {
__shared__ float buffer[CUDA_NUM_THREADS];
const unsigned int tid = threadIdx.x;
const unsigned int c = blockIdx.x;
// load and accumulate data to buffer
buffer[tid] = 0;
for (int i = tid; i < N * D; i += blockDim.x) {
const unsigned int n = i / D;
const unsigned int d = i % D;
const unsigned int index = n * C * D + c * D + d;
buffer[tid] += in[index];
}
__syncthreads();
// do tree reduction in buffer
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) { // <-- bad: divergent branching
buffer[tid] += buffer[tid + s];
}
__syncthreads();
}
if (tid == 0) out[c] = buffer[0] / (N * D);
} | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Given a input tensor x with shape (N, C, D), compute x.mean(2).mean(0)
* This function is useful in batch normalization.
* Refer to https://people.maths.ox.ac.uk/gilesm/cuda/prac4/reduction.pdf.
* But the unrolling warps seems to be not working correctly for now.
*/
const int N = 256;
const int C = 1024;
const int D = 28*28;
__global__ void reduce0(const float* in, float* out) {
__shared__ float buffer[CUDA_NUM_THREADS];
const unsigned int tid = threadIdx.x;
const unsigned int c = blockIdx.x;
// load and accumulate data to buffer
buffer[tid] = 0;
for (int i = tid; i < N * D; i += blockDim.x) {
const unsigned int n = i / D;
const unsigned int d = i % D;
const unsigned int index = n * C * D + c * D + d;
buffer[tid] += in[index];
}
__syncthreads();
// do tree reduction in buffer
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) { // <-- bad: divergent branching
buffer[tid] += buffer[tid + s];
}
__syncthreads();
}
if (tid == 0) out[c] = buffer[0] / (N * D);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Given a input tensor x with shape (N, C, D), compute x.mean(2).mean(0)
* This function is useful in batch normalization.
* Refer to https://people.maths.ox.ac.uk/gilesm/cuda/prac4/reduction.pdf.
* But the unrolling warps seems to be not working correctly for now.
*/
const int N = 256;
const int C = 1024;
const int D = 28*28;
__global__ void reduce0(const float* in, float* out) {
__shared__ float buffer[CUDA_NUM_THREADS];
const unsigned int tid = threadIdx.x;
const unsigned int c = blockIdx.x;
// load and accumulate data to buffer
buffer[tid] = 0;
for (int i = tid; i < N * D; i += blockDim.x) {
const unsigned int n = i / D;
const unsigned int d = i % D;
const unsigned int index = n * C * D + c * D + d;
buffer[tid] += in[index];
}
__syncthreads();
// do tree reduction in buffer
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) { // <-- bad: divergent branching
buffer[tid] += buffer[tid + s];
}
__syncthreads();
}
if (tid == 0) out[c] = buffer[0] / (N * D);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce0PKfPf
.globl _Z7reduce0PKfPf
.p2align 8
.type _Z7reduce0PKfPf,@function
_Z7reduce0PKfPf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, v0
s_mov_b32 s2, s15
s_mul_i32 s3, s15, 0x310
ds_store_b32 v3, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, 0
.p2align 6
.LBB0_1:
v_mul_hi_u32 v1, v5, 0x5397829d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, 8, v1
v_mul_u32_u24_e32 v6, 0x310, v1
v_mul_u32_u24_e32 v1, 0xc4000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v6
v_add3_u32 v1, s3, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v4, v1, v4 :: v_dual_add_nc_u32 v5, s7, v5
v_cmp_lt_u32_e32 vcc_lo, 0x30fff, v5
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s6
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s4, s3, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_7
s_and_b32 s3, 0xffff, s3
s_mov_b32 s5, 1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v1, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v1, s5, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_div_scale_f32 v2, null, 0x48440000, 0x48440000, v1
v_div_scale_f32 v5, vcc_lo, v1, 0x48440000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v5, v3
v_fma_f32 v6, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v3
v_fma_f32 v2, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v4
v_div_fixup_f32 v1, v2, 0x48440000, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce0PKfPf
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce0PKfPf, .Lfunc_end0-_Z7reduce0PKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce0PKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce0PKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Given a input tensor x with shape (N, C, D), compute x.mean(2).mean(0)
* This function is useful in batch normalization.
* Refer to https://people.maths.ox.ac.uk/gilesm/cuda/prac4/reduction.pdf.
* But the unrolling warps seems to be not working correctly for now.
*/
const int N = 256;
const int C = 1024;
const int D = 28*28;
__global__ void reduce0(const float* in, float* out) {
__shared__ float buffer[CUDA_NUM_THREADS];
const unsigned int tid = threadIdx.x;
const unsigned int c = blockIdx.x;
// load and accumulate data to buffer
buffer[tid] = 0;
for (int i = tid; i < N * D; i += blockDim.x) {
const unsigned int n = i / D;
const unsigned int d = i % D;
const unsigned int index = n * C * D + c * D + d;
buffer[tid] += in[index];
}
__syncthreads();
// do tree reduction in buffer
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) { // <-- bad: divergent branching
buffer[tid] += buffer[tid + s];
}
__syncthreads();
}
if (tid == 0) out[c] = buffer[0] / (N * D);
} | .text
.file "reduce0.hip"
.globl _Z22__device_stub__reduce0PKfPf # -- Begin function _Z22__device_stub__reduce0PKfPf
.p2align 4, 0x90
.type _Z22__device_stub__reduce0PKfPf,@function
_Z22__device_stub__reduce0PKfPf: # @_Z22__device_stub__reduce0PKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce0PKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce0PKfPf, .Lfunc_end0-_Z22__device_stub__reduce0PKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce0PKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce0PKfPf,@object # @_Z7reduce0PKfPf
.section .rodata,"a",@progbits
.globl _Z7reduce0PKfPf
.p2align 3, 0x0
_Z7reduce0PKfPf:
.quad _Z22__device_stub__reduce0PKfPf
.size _Z7reduce0PKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7reduce0PKfPf"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce0PKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce0PKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7reduce0PKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1c0 ; /* 0x0000018000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0011e20000004800 */
/*0060*/ ISETP.GE.AND P0, PT, R2.reuse, 0x31000, PT ; /* 0x000310000200780c */
/* 0x040fe20003f06270 */
/*0070*/ IMAD.SHL.U32 R3, R2, 0x4, RZ ; /* 0x0000000402037824 */
/* 0x000fd800078e00ff */
/*0080*/ @P0 BRA 0x1b0 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0090*/ BSSY B1, 0x1a0 ; /* 0x0000010000017945 */
/* 0x003fe20003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0002 */
/*00c0*/ IMAD.HI R4, R6, 0x5397829d, RZ ; /* 0x5397829d06047827 */
/* 0x000fca00078e02ff */
/*00d0*/ SHF.R.U32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011604 */
/*00e0*/ LEA.HI.SX32 R5, R4, R5, 0x18 ; /* 0x0000000504057211 */
/* 0x000fca00078fc2ff */
/*00f0*/ IMAD R9, R5, -0x310, R6 ; /* 0xfffffcf005097824 */
/* 0x000fc800078e0206 */
/*0100*/ IMAD R4, R0, 0x310, R9 ; /* 0x0000031000047824 */
/* 0x000fe400078e0209 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD R4, R5, 0xc4000, R4 ; /* 0x000c400005047824 */
/* 0x000fc800078e0204 */
/*0130*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0009 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R6, R6, c[0x0][0x0], RZ ; /* 0x0000000006067a10 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.AND P0, PT, R6, 0x31000, PT ; /* 0x000310000600780c */
/* 0x000fe20003f06270 */
/*0170*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x004fd80000000000 */
/*0180*/ @!P0 BRA 0xc0 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01a0*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e40000004800 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe200078e00ff */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f05270 */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fda0003f26070 */
/*0200*/ @!P1 BRA 0x3e0 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.SHL.U32 R8, R6, 0x2, RZ ; /* 0x0000000206087824 */
/* 0x000fc800078e00ff */
/*0230*/ I2F.U32.RP R7, R8 ; /* 0x0000000800077306 */
/* 0x000e220000209000 */
/*0240*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a08 */
/*0250*/ ISETP.NE.U32.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fcc0003f45070 */
/*0260*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0270*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fcc0007ffe0ff */
/*0280*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*02a0*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*02b0*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*02c0*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*02e0*/ IMAD R5, R8, R5, R2 ; /* 0x0000000508057224 */
/* 0x000fca00078e0202 */
/*02f0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*0300*/ @P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105051824 */
/* 0x000fca00078e0a08 */
/*0310*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*0320*/ @P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105051824 */
/* 0x000fe200078e0a08 */
/*0330*/ @!P2 LOP3.LUT R5, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff05a212 */
/* 0x000fc800078e33ff */
/*0340*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0350*/ @!P1 IMAD R4, R6, 0x4, R3 ; /* 0x0000000406049824 */
/* 0x000fe200078e0203 */
/*0360*/ @!P1 LDS R5, [R2.X4] ; /* 0x0000000002059984 */
/* 0x000fe20000004800 */
/*0370*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fc80000000f00 */
/*0380*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*0390*/ @!P1 FADD R5, R5, R4 ; /* 0x0000000405059221 */
/* 0x001fca0000000000 */
/*03a0*/ @!P1 STS [R2.X4], R5 ; /* 0x0000000502009388 */
/* 0x0001e80000004800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fda0003f26070 */
/*03d0*/ @!P1 BRA 0x220 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*03e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03f0*/ LDS R3, [RZ] ; /* 0x00000000ff037984 */
/* 0x000e220000000800 */
/*0400*/ IMAD.MOV.U32 R5, RZ, RZ, 0x36a72f05 ; /* 0x36a72f05ff057424 */
/* 0x000fe400078e00ff */
/*0410*/ IMAD.MOV.U32 R2, RZ, RZ, 0x48440000 ; /* 0x48440000ff027424 */
/* 0x000fc800078e00ff */
/*0420*/ FFMA R2, R5, -R2, 1 ; /* 0x3f80000005027423 */
/* 0x000fc80000000802 */
/*0430*/ FFMA R2, R2, R5, 4.9824616326077375561e-06 ; /* 0x36a72f0502027423 */
/* 0x000fe20000000005 */
/*0440*/ FCHK P0, R3, 200704 ; /* 0x4844000003007902 */
/* 0x001e260000000000 */
/*0450*/ FFMA R4, R3, R2, RZ ; /* 0x0000000203047223 */
/* 0x000fc800000000ff */
/*0460*/ FFMA R5, R4, -200704, R3 ; /* 0xc844000004057823 */
/* 0x000fc80000000003 */
/*0470*/ FFMA R5, R2, R5, R4 ; /* 0x0000000502057223 */
/* 0x000fe20000000004 */
/*0480*/ @!P0 BRA 0x4b0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0490*/ MOV R2, 0x4b0 ; /* 0x000004b000027802 */
/* 0x000fe40000000f00 */
/*04a0*/ CALL.REL.NOINC 0x4f0 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*04b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*04c0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*04d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ SHF.R.U32.HI R4, RZ, 0x17, R3.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011603 */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0003 */
/*0510*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fc800078ec0ff */
/*0520*/ IADD3 R7, R4, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x000fc80007ffe0ff */
/*0530*/ ISETP.GT.U32.OR P0, PT, R7, 0xfd, !PT ; /* 0x000000fd0700780c */
/* 0x000fda0007f04470 */
/*0540*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0550*/ @!P0 BRA 0x650 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0560*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0570*/ @P0 BRA 0xa20 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*0580*/ IMAD.MOV.U32 R6, RZ, RZ, 0x48440000 ; /* 0x48440000ff067424 */
/* 0x000fca00078e00ff */
/*0590*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*05a0*/ @!P0 BRA 0xa00 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*05b0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*05c0*/ @!P0 BRA 0x9e0 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*05d0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1d200 */
/*05e0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*05f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0600*/ @P0 BRA 0x9b0 ; /* 0x000003a000000947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*0620*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe200078e00ff */
/*0630*/ @!P0 MOV R6, 0xffffffc0 ; /* 0xffffffc000068802 */
/* 0x000fe20000000f00 */
/*0640*/ @!P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003058823 */
/* 0x000fe400000000ff */
/*0650*/ UMOV UR4, 0x48440000 ; /* 0x4844000000047882 */
/* 0x000fe20000000000 */
/*0660*/ IADD3 R4, R4, -0x7f, RZ ; /* 0xffffff8104047810 */
/* 0x000fe20007ffe0ff */
/*0670*/ UIADD3 UR4, UR4, -0x8800000, URZ ; /* 0xf780000004047890 */
/* 0x000fc6000fffe03f */
/*0680*/ IADD3 R6, R6, -0x11, R4 ; /* 0xffffffef06067810 */
/* 0x000fe20007ffe004 */
/*0690*/ IMAD R5, R4, -0x800000, R5 ; /* 0xff80000004057824 */
/* 0x000fe400078e0205 */
/*06a0*/ FADD.FTZ R8, -RZ, -UR4 ; /* 0x80000004ff087e21 */
/* 0x000fc60008010100 */
/*06b0*/ MUFU.RCP R3, UR4 ; /* 0x0000000400037d08 */
/* 0x000e240008001000 */
/*06c0*/ FFMA R10, R3, R8, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000008 */
/*06d0*/ FFMA R10, R3, R10, R3 ; /* 0x0000000a030a7223 */
/* 0x000fc80000000003 */
/*06e0*/ FFMA R3, R5, R10, RZ ; /* 0x0000000a05037223 */
/* 0x000fc800000000ff */
/*06f0*/ FFMA R7, R8, R3, R5 ; /* 0x0000000308077223 */
/* 0x000fc80000000005 */
/*0700*/ FFMA R7, R10, R7, R3 ; /* 0x000000070a077223 */
/* 0x000fc80000000003 */
/*0710*/ FFMA R8, R8, R7, R5 ; /* 0x0000000708087223 */
/* 0x000fc80000000005 */
/*0720*/ FFMA R5, R10, R8, R7 ; /* 0x000000080a057223 */
/* 0x000fca0000000007 */
/*0730*/ SHF.R.U32.HI R3, RZ, 0x17, R5 ; /* 0x00000017ff037819 */
/* 0x000fc80000011605 */
/*0740*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*0750*/ IMAD.IADD R9, R3, 0x1, R6 ; /* 0x0000000103097824 */
/* 0x000fca00078e0206 */
/*0760*/ IADD3 R3, R9, -0x1, RZ ; /* 0xffffffff09037810 */
/* 0x000fc80007ffe0ff */
/*0770*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*0780*/ @!P0 BRA 0x990 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0790*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*07a0*/ @P0 BRA 0x960 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*07b0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*07c0*/ @P0 BRA 0xa30 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*07d0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*07e0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*07f0*/ @!P0 BRA 0xa30 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0800*/ FFMA.RZ R3, R10.reuse, R8.reuse, R7 ; /* 0x000000080a037223 */
/* 0x0c0fe2000000c007 */
/*0810*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0820*/ IMAD.MOV R6, RZ, RZ, -R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a09 */
/*0830*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0840*/ LOP3.LUT R4, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03047812 */
/* 0x000fe200078ec0ff */
/*0850*/ FFMA.RP R3, R10.reuse, R8.reuse, R7.reuse ; /* 0x000000080a037223 */
/* 0x1c0fe40000008007 */
/*0860*/ FFMA.RM R10, R10, R8, R7 ; /* 0x000000080a0a7223 */
/* 0x000fe20000004007 */
/*0870*/ IADD3 R7, R9, 0x20, RZ ; /* 0x0000002009077810 */
/* 0x000fe40007ffe0ff */
/*0880*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fc400078efcff */
/*0890*/ FSETP.NEU.FTZ.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720b */
/* 0x000fe40003f1d000 */
/*08a0*/ SHF.L.U32 R7, R4, R7, RZ ; /* 0x0000000704077219 */
/* 0x000fe400000006ff */
/*08b0*/ SEL R3, R6, RZ, P2 ; /* 0x000000ff06037207 */
/* 0x000fe40001000000 */
/*08c0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*08d0*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fe40000011604 */
/*08e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*08f0*/ SHF.R.U32.HI R7, RZ, 0x1, R3 ; /* 0x00000001ff077819 */
/* 0x000fe40000011603 */
/*0900*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0910*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0920*/ LOP3.LUT R4, R4, R3, RZ, 0xc0, !PT ; /* 0x0000000304047212 */
/* 0x000fca00078ec0ff */
/*0930*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0940*/ LOP3.LUT R5, R4, R5, RZ, 0xfc, !PT ; /* 0x0000000504057212 */
/* 0x000fe200078efcff */
/*0950*/ BRA 0xa30 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0960*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0970*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0980*/ BRA 0xa30 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0990*/ IMAD R5, R6, 0x800000, R5 ; /* 0x0080000006057824 */
/* 0x000fe200078e0205 */
/*09a0*/ BRA 0xa30 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*09b0*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fc800078e4805 */
/*09c0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*09d0*/ BRA 0xa30 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078e4805 */
/*09f0*/ BRA 0xa30 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a00*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0a10*/ BRA 0xa30 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a20*/ FADD.FTZ R5, R3, 200704 ; /* 0x4844000003057421 */
/* 0x000fe40000010000 */
/*0a30*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0a40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff5b002007950 */
/* 0x000fea0003c3ffff */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce0PKfPf
.globl _Z7reduce0PKfPf
.p2align 8
.type _Z7reduce0PKfPf,@function
_Z7reduce0PKfPf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, v0
s_mov_b32 s2, s15
s_mul_i32 s3, s15, 0x310
ds_store_b32 v3, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, 0
.p2align 6
.LBB0_1:
v_mul_hi_u32 v1, v5, 0x5397829d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, 8, v1
v_mul_u32_u24_e32 v6, 0x310, v1
v_mul_u32_u24_e32 v1, 0xc4000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v6
v_add3_u32 v1, s3, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v4, v1, v4 :: v_dual_add_nc_u32 v5, s7, v5
v_cmp_lt_u32_e32 vcc_lo, 0x30fff, v5
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s6
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s4, s3, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_7
s_and_b32 s3, 0xffff, s3
s_mov_b32 s5, 1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v1, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v1, s5, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_div_scale_f32 v2, null, 0x48440000, 0x48440000, v1
v_div_scale_f32 v5, vcc_lo, v1, 0x48440000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v5, v3
v_fma_f32 v6, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v3
v_fma_f32 v2, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v4
v_div_fixup_f32 v1, v2, 0x48440000, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce0PKfPf
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce0PKfPf, .Lfunc_end0-_Z7reduce0PKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce0PKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce0PKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00185182_00000000-6_reduce0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7reduce0PKfPfPKfPf
.type _Z29__device_stub__Z7reduce0PKfPfPKfPf, @function
_Z29__device_stub__Z7reduce0PKfPfPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce0PKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z7reduce0PKfPfPKfPf, .-_Z29__device_stub__Z7reduce0PKfPfPKfPf
.globl _Z7reduce0PKfPf
.type _Z7reduce0PKfPf, @function
_Z7reduce0PKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7reduce0PKfPfPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7reduce0PKfPf, .-_Z7reduce0PKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7reduce0PKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce0PKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce0.hip"
.globl _Z22__device_stub__reduce0PKfPf # -- Begin function _Z22__device_stub__reduce0PKfPf
.p2align 4, 0x90
.type _Z22__device_stub__reduce0PKfPf,@function
_Z22__device_stub__reduce0PKfPf: # @_Z22__device_stub__reduce0PKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce0PKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce0PKfPf, .Lfunc_end0-_Z22__device_stub__reduce0PKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce0PKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce0PKfPf,@object # @_Z7reduce0PKfPf
.section .rodata,"a",@progbits
.globl _Z7reduce0PKfPf
.p2align 3, 0x0
_Z7reduce0PKfPf:
.quad _Z22__device_stub__reduce0PKfPf
.size _Z7reduce0PKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7reduce0PKfPf"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce0PKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce0PKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
Problem 1: initialize array of size 32 to 0
Problem 2: change array size to 1024
Problem 3: create another kernel that adds i to array[ i ]
Problem 4: change array size 8000 (check answer to Problem 3 still works)
*/
//initialize array to 0
//add i to array[ i ]
__global__ void kernel2( int N, int *d_array ){
for( int i = 0; i < N; i++ ){
d_array[ i ] = i;
}
} | code for sm_80
Function : _Z7kernel2iPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0x640 ; /* 0x000005a000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, -R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*00d0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fd800078e00ff */
/*00f0*/ @!P0 BRA 0x550 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0110*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0120*/ @!P1 BRA 0x3b0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0140*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0150*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0160*/ IADD3 R7, R5.reuse, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x040fe40007ffe0ff */
/*0170*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0180*/ IADD3 R9, R5.reuse, 0x2, RZ ; /* 0x0000000205097810 */
/* 0x040fe20007ffe0ff */
/*0190*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c101904 */
/*01a0*/ IADD3 R11, R5.reuse, 0x3, RZ ; /* 0x00000003050b7810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ IADD3 R13, R5.reuse, 0x4, RZ ; /* 0x00000004050d7810 */
/* 0x040fe20007ffe0ff */
/*01c0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x0003e2000c101904 */
/*01d0*/ IADD3 R15, R5, 0x5, RZ ; /* 0x00000005050f7810 */
/* 0x000fc40007ffe0ff */
/*01e0*/ IADD3 R17, R5.reuse, 0x6, RZ ; /* 0x0000000605117810 */
/* 0x040fe20007ffe0ff */
/*01f0*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x0005e2000c101904 */
/*0200*/ IADD3 R6, P2, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fe40007f5e0ff */
/*0210*/ IADD3 R19, R5.reuse, 0x7, RZ ; /* 0x0000000705137810 */
/* 0x040fe20007ffe0ff */
/*0220*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x0007e2000c101904 */
/*0230*/ IADD3 R21, R5.reuse, 0x8, RZ ; /* 0x0000000805157810 */
/* 0x040fe40007ffe0ff */
/*0240*/ IADD3 R23, R5.reuse, 0x9, RZ ; /* 0x0000000905177810 */
/* 0x040fe20007ffe0ff */
/*0250*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x0009e2000c101904 */
/*0260*/ IADD3 R25, R5, 0xa, RZ ; /* 0x0000000a05197810 */
/* 0x000fc40007ffe0ff */
/*0270*/ IADD3 R7, R5.reuse, 0xb, RZ ; /* 0x0000000b05077810 */
/* 0x041fe20007ffe0ff */
/*0280*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x0001e2000c101904 */
/*0290*/ IADD3 R9, R5.reuse, 0xc, RZ ; /* 0x0000000c05097810 */
/* 0x042fe40007ffe0ff */
/*02a0*/ IADD3 R11, R5.reuse, 0xd, RZ ; /* 0x0000000d050b7810 */
/* 0x044fe20007ffe0ff */
/*02b0*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x000fe2000c101904 */
/*02c0*/ IADD3 R13, R5.reuse, 0xe, RZ ; /* 0x0000000e050d7810 */
/* 0x048fe40007ffe0ff */
/*02d0*/ IADD3 R15, R5.reuse, 0xf, RZ ; /* 0x0000000f050f7810 */
/* 0x050fe20007ffe0ff */
/*02e0*/ STG.E [R2.64+0x20], R21 ; /* 0x0000201502007986 */
/* 0x000fe2000c101904 */
/*02f0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD.X R17, RZ, RZ, R3, P2 ; /* 0x000000ffff117224 */
/* 0x001fc400010e0603 */
/*0310*/ STG.E [R2.64+0x24], R23 ; /* 0x0000241702007986 */
/* 0x000fe8000c101904 */
/*0320*/ STG.E [R2.64+0x28], R25 ; /* 0x0000281902007986 */
/* 0x000fe8000c101904 */
/*0330*/ STG.E [R2.64+0x2c], R7 ; /* 0x00002c0702007986 */
/* 0x000fe8000c101904 */
/*0340*/ STG.E [R2.64+0x30], R9 ; /* 0x0000300902007986 */
/* 0x000fe8000c101904 */
/*0350*/ STG.E [R2.64+0x34], R11 ; /* 0x0000340b02007986 */
/* 0x000fe8000c101904 */
/*0360*/ STG.E [R2.64+0x38], R13 ; /* 0x0000380d02007986 */
/* 0x000fe8000c101904 */
/*0370*/ STG.E [R2.64+0x3c], R15 ; /* 0x00003c0f02007986 */
/* 0x0001e4000c101904 */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, R17 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0011 */
/*03a0*/ @P1 BRA 0x140 ; /* 0xfffffd9000001947 */
/* 0x000fea000383ffff */
/*03b0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*03c0*/ @!P1 BRA 0x530 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*03d0*/ IADD3 R7, R5.reuse, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x040fe20007ffe0ff */
/*03e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*03f0*/ IADD3 R6, P1, R2, 0x20, RZ ; /* 0x0000002002067810 */
/* 0x000fe40007f3e0ff */
/*0400*/ IADD3 R9, R5.reuse, 0x2, RZ ; /* 0x0000000205097810 */
/* 0x040fe20007ffe0ff */
/*0410*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c101904 */
/*0420*/ IADD3 R11, R5.reuse, 0x3, RZ ; /* 0x00000003050b7810 */
/* 0x040fe40007ffe0ff */
/*0430*/ IADD3 R13, R5.reuse, 0x4, RZ ; /* 0x00000004050d7810 */
/* 0x040fe20007ffe0ff */
/*0440*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe2000c101904 */
/*0450*/ IADD3 R15, R5, 0x5, RZ ; /* 0x00000005050f7810 */
/* 0x000fc40007ffe0ff */
/*0460*/ IADD3 R17, R5.reuse, 0x6, RZ ; /* 0x0000000605117810 */
/* 0x040fe20007ffe0ff */
/*0470*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x000fe2000c101904 */
/*0480*/ IADD3 R19, R5.reuse, 0x7, RZ ; /* 0x0000000705137810 */
/* 0x040fe40007ffe0ff */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*04a0*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x001fe200008e0603 */
/*04b0*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe2000c101904 */
/*04c0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x000fe8000c101904 */
/*04f0*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x000fe8000c101904 */
/*0500*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x0001e4000c101904 */
/*0510*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0520*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0530*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0540*/ @!P0 BRA 0x640 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0560*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*0570*/ IADD3 R6, P1, R2, 0x10, RZ ; /* 0x0000001002067810 */
/* 0x000fe40007f3e0ff */
/*0580*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0590*/ IADD3 R9, R5.reuse, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x040fe20007ffe0ff */
/*05a0*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0603 */
/*05b0*/ IADD3 R11, R5.reuse, 0x2, RZ ; /* 0x00000002050b7810 */
/* 0x040fe40007ffe0ff */
/*05c0*/ IADD3 R13, R5.reuse, 0x3, RZ ; /* 0x00000003050d7810 */
/* 0x040fe20007ffe0ff */
/*05d0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe2000c101904 */
/*05e0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x001fc60007ffe0ff */
/*05f0*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x000fe8000c101904 */
/*0600*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0001e4000c101904 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0006 */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*0630*/ @P0 BRA 0x550 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0650*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0670*/ IMAD.WIDE R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0202 */
/*0680*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0690*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e6000c101904 */
/*06a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*06b0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f3e0ff */
/*06c0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc60007ffe0ff */
/*06d0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*06e0*/ @P0 BRA 0x680 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*06f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0700*/ BRA 0x700; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
Problem 1: initialize array of size 32 to 0
Problem 2: change array size to 1024
Problem 3: create another kernel that adds i to array[ i ]
Problem 4: change array size 8000 (check answer to Problem 3 still works)
*/
//initialize array to 0
//add i to array[ i ]
__global__ void kernel2( int N, int *d_array ){
for( int i = 0; i < N; i++ ){
d_array[ i ] = i;
}
} | .file "tmpxft_00133a23_00000000-6_kernel2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7kernel2iPiiPi
.type _Z27__device_stub__Z7kernel2iPiiPi, @function
_Z27__device_stub__Z7kernel2iPiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel2iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7kernel2iPiiPi, .-_Z27__device_stub__Z7kernel2iPiiPi
.globl _Z7kernel2iPi
.type _Z7kernel2iPi, @function
_Z7kernel2iPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel2iPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7kernel2iPi, .-_Z7kernel2iPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kernel2iPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2iPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
Problem 1: initialize array of size 32 to 0
Problem 2: change array size to 1024
Problem 3: create another kernel that adds i to array[ i ]
Problem 4: change array size 8000 (check answer to Problem 3 still works)
*/
//initialize array to 0
//add i to array[ i ]
__global__ void kernel2( int N, int *d_array ){
for( int i = 0; i < N; i++ ){
d_array[ i ] = i;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
Problem 1: initialize array of size 32 to 0
Problem 2: change array size to 1024
Problem 3: create another kernel that adds i to array[ i ]
Problem 4: change array size 8000 (check answer to Problem 3 still works)
*/
//initialize array to 0
//add i to array[ i ]
__global__ void kernel2( int N, int *d_array ){
for( int i = 0; i < N; i++ ){
d_array[ i ] = i;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
Problem 1: initialize array of size 32 to 0
Problem 2: change array size to 1024
Problem 3: create another kernel that adds i to array[ i ]
Problem 4: change array size 8000 (check answer to Problem 3 still works)
*/
//initialize array to 0
//add i to array[ i ]
__global__ void kernel2( int N, int *d_array ){
for( int i = 0; i < N; i++ ){
d_array[ i ] = i;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel2iPi
.globl _Z7kernel2iPi
.p2align 8
.type _Z7kernel2iPi,@function
_Z7kernel2iPi:
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s3
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2iPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel2iPi, .Lfunc_end0-_Z7kernel2iPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2iPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z7kernel2iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
Problem 1: initialize array of size 32 to 0
Problem 2: change array size to 1024
Problem 3: create another kernel that adds i to array[ i ]
Problem 4: change array size 8000 (check answer to Problem 3 still works)
*/
//initialize array to 0
//add i to array[ i ]
__global__ void kernel2( int N, int *d_array ){
for( int i = 0; i < N; i++ ){
d_array[ i ] = i;
}
} | .text
.file "kernel2.hip"
.globl _Z22__device_stub__kernel2iPi # -- Begin function _Z22__device_stub__kernel2iPi
.p2align 4, 0x90
.type _Z22__device_stub__kernel2iPi,@function
_Z22__device_stub__kernel2iPi: # @_Z22__device_stub__kernel2iPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel2iPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel2iPi, .Lfunc_end0-_Z22__device_stub__kernel2iPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2iPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel2iPi,@object # @_Z7kernel2iPi
.section .rodata,"a",@progbits
.globl _Z7kernel2iPi
.p2align 3, 0x0
_Z7kernel2iPi:
.quad _Z22__device_stub__kernel2iPi
.size _Z7kernel2iPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernel2iPi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel2iPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel2iPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernel2iPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0x640 ; /* 0x000005a000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, -R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*00d0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fd800078e00ff */
/*00f0*/ @!P0 BRA 0x550 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0110*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0120*/ @!P1 BRA 0x3b0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0140*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0150*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0160*/ IADD3 R7, R5.reuse, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x040fe40007ffe0ff */
/*0170*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0180*/ IADD3 R9, R5.reuse, 0x2, RZ ; /* 0x0000000205097810 */
/* 0x040fe20007ffe0ff */
/*0190*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c101904 */
/*01a0*/ IADD3 R11, R5.reuse, 0x3, RZ ; /* 0x00000003050b7810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ IADD3 R13, R5.reuse, 0x4, RZ ; /* 0x00000004050d7810 */
/* 0x040fe20007ffe0ff */
/*01c0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x0003e2000c101904 */
/*01d0*/ IADD3 R15, R5, 0x5, RZ ; /* 0x00000005050f7810 */
/* 0x000fc40007ffe0ff */
/*01e0*/ IADD3 R17, R5.reuse, 0x6, RZ ; /* 0x0000000605117810 */
/* 0x040fe20007ffe0ff */
/*01f0*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x0005e2000c101904 */
/*0200*/ IADD3 R6, P2, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fe40007f5e0ff */
/*0210*/ IADD3 R19, R5.reuse, 0x7, RZ ; /* 0x0000000705137810 */
/* 0x040fe20007ffe0ff */
/*0220*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x0007e2000c101904 */
/*0230*/ IADD3 R21, R5.reuse, 0x8, RZ ; /* 0x0000000805157810 */
/* 0x040fe40007ffe0ff */
/*0240*/ IADD3 R23, R5.reuse, 0x9, RZ ; /* 0x0000000905177810 */
/* 0x040fe20007ffe0ff */
/*0250*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x0009e2000c101904 */
/*0260*/ IADD3 R25, R5, 0xa, RZ ; /* 0x0000000a05197810 */
/* 0x000fc40007ffe0ff */
/*0270*/ IADD3 R7, R5.reuse, 0xb, RZ ; /* 0x0000000b05077810 */
/* 0x041fe20007ffe0ff */
/*0280*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x0001e2000c101904 */
/*0290*/ IADD3 R9, R5.reuse, 0xc, RZ ; /* 0x0000000c05097810 */
/* 0x042fe40007ffe0ff */
/*02a0*/ IADD3 R11, R5.reuse, 0xd, RZ ; /* 0x0000000d050b7810 */
/* 0x044fe20007ffe0ff */
/*02b0*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x000fe2000c101904 */
/*02c0*/ IADD3 R13, R5.reuse, 0xe, RZ ; /* 0x0000000e050d7810 */
/* 0x048fe40007ffe0ff */
/*02d0*/ IADD3 R15, R5.reuse, 0xf, RZ ; /* 0x0000000f050f7810 */
/* 0x050fe20007ffe0ff */
/*02e0*/ STG.E [R2.64+0x20], R21 ; /* 0x0000201502007986 */
/* 0x000fe2000c101904 */
/*02f0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD.X R17, RZ, RZ, R3, P2 ; /* 0x000000ffff117224 */
/* 0x001fc400010e0603 */
/*0310*/ STG.E [R2.64+0x24], R23 ; /* 0x0000241702007986 */
/* 0x000fe8000c101904 */
/*0320*/ STG.E [R2.64+0x28], R25 ; /* 0x0000281902007986 */
/* 0x000fe8000c101904 */
/*0330*/ STG.E [R2.64+0x2c], R7 ; /* 0x00002c0702007986 */
/* 0x000fe8000c101904 */
/*0340*/ STG.E [R2.64+0x30], R9 ; /* 0x0000300902007986 */
/* 0x000fe8000c101904 */
/*0350*/ STG.E [R2.64+0x34], R11 ; /* 0x0000340b02007986 */
/* 0x000fe8000c101904 */
/*0360*/ STG.E [R2.64+0x38], R13 ; /* 0x0000380d02007986 */
/* 0x000fe8000c101904 */
/*0370*/ STG.E [R2.64+0x3c], R15 ; /* 0x00003c0f02007986 */
/* 0x0001e4000c101904 */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, R17 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0011 */
/*03a0*/ @P1 BRA 0x140 ; /* 0xfffffd9000001947 */
/* 0x000fea000383ffff */
/*03b0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*03c0*/ @!P1 BRA 0x530 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*03d0*/ IADD3 R7, R5.reuse, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x040fe20007ffe0ff */
/*03e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*03f0*/ IADD3 R6, P1, R2, 0x20, RZ ; /* 0x0000002002067810 */
/* 0x000fe40007f3e0ff */
/*0400*/ IADD3 R9, R5.reuse, 0x2, RZ ; /* 0x0000000205097810 */
/* 0x040fe20007ffe0ff */
/*0410*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c101904 */
/*0420*/ IADD3 R11, R5.reuse, 0x3, RZ ; /* 0x00000003050b7810 */
/* 0x040fe40007ffe0ff */
/*0430*/ IADD3 R13, R5.reuse, 0x4, RZ ; /* 0x00000004050d7810 */
/* 0x040fe20007ffe0ff */
/*0440*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe2000c101904 */
/*0450*/ IADD3 R15, R5, 0x5, RZ ; /* 0x00000005050f7810 */
/* 0x000fc40007ffe0ff */
/*0460*/ IADD3 R17, R5.reuse, 0x6, RZ ; /* 0x0000000605117810 */
/* 0x040fe20007ffe0ff */
/*0470*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x000fe2000c101904 */
/*0480*/ IADD3 R19, R5.reuse, 0x7, RZ ; /* 0x0000000705137810 */
/* 0x040fe40007ffe0ff */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*04a0*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x001fe200008e0603 */
/*04b0*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe2000c101904 */
/*04c0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x000fe8000c101904 */
/*04f0*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x000fe8000c101904 */
/*0500*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x0001e4000c101904 */
/*0510*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0520*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0530*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0540*/ @!P0 BRA 0x640 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0560*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*0570*/ IADD3 R6, P1, R2, 0x10, RZ ; /* 0x0000001002067810 */
/* 0x000fe40007f3e0ff */
/*0580*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0590*/ IADD3 R9, R5.reuse, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x040fe20007ffe0ff */
/*05a0*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0603 */
/*05b0*/ IADD3 R11, R5.reuse, 0x2, RZ ; /* 0x00000002050b7810 */
/* 0x040fe40007ffe0ff */
/*05c0*/ IADD3 R13, R5.reuse, 0x3, RZ ; /* 0x00000003050d7810 */
/* 0x040fe20007ffe0ff */
/*05d0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe2000c101904 */
/*05e0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x001fc60007ffe0ff */
/*05f0*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x000fe8000c101904 */
/*0600*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0001e4000c101904 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0006 */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*0630*/ @P0 BRA 0x550 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0650*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0660*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0670*/ IMAD.WIDE R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0202 */
/*0680*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0690*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e6000c101904 */
/*06a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*06b0*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f3e0ff */
/*06c0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc60007ffe0ff */
/*06d0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*06e0*/ @P0 BRA 0x680 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*06f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0700*/ BRA 0x700; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel2iPi
.globl _Z7kernel2iPi
.p2align 8
.type _Z7kernel2iPi,@function
_Z7kernel2iPi:
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s3
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2iPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel2iPi, .Lfunc_end0-_Z7kernel2iPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2iPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z7kernel2iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00133a23_00000000-6_kernel2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7kernel2iPiiPi
.type _Z27__device_stub__Z7kernel2iPiiPi, @function
_Z27__device_stub__Z7kernel2iPiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7kernel2iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7kernel2iPiiPi, .-_Z27__device_stub__Z7kernel2iPiiPi
.globl _Z7kernel2iPi
.type _Z7kernel2iPi, @function
_Z7kernel2iPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7kernel2iPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7kernel2iPi, .-_Z7kernel2iPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kernel2iPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2iPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel2.hip"
.globl _Z22__device_stub__kernel2iPi # -- Begin function _Z22__device_stub__kernel2iPi
.p2align 4, 0x90
.type _Z22__device_stub__kernel2iPi,@function
_Z22__device_stub__kernel2iPi: # @_Z22__device_stub__kernel2iPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7kernel2iPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel2iPi, .Lfunc_end0-_Z22__device_stub__kernel2iPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2iPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel2iPi,@object # @_Z7kernel2iPi
.section .rodata,"a",@progbits
.globl _Z7kernel2iPi
.p2align 3, 0x0
_Z7kernel2iPi:
.quad _Z22__device_stub__kernel2iPi
.size _Z7kernel2iPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernel2iPi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel2iPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel2iPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#define DEBUG false
// Simple SAXPY operation.
__global__ void cuda_saxpy_mat_1(int N, float a, float *x, float *y)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < N*N)
{
y[index] = a * x[index] + y[index];
}
}
void wait()
{
puts("Press any key to continue...");
getchar();
}
// Heavy lifting
double run_computation(bool on_gpu, int N)
{
#if(DEBUG)
printf("N = %d\n\n", N);
#endif
float a = 6.0f;
float *host_x, *host_y, *device_x, *device_y;
host_x = (float*)malloc(N*N*sizeof(float));
host_y = (float*)malloc(N*N*sizeof(float));
if (on_gpu)
{
cudaMalloc(&device_x, N*N*sizeof(float));
cudaMalloc(&device_y, N*N*sizeof(float));
}
dim3 blocks_per_grid((N*N+255)/256, 1, 1);
dim3 threads_per_block(256, 1, 1);
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_x + i*N + j) = 1.0f;
*(host_y + i*N + j) = 3.0f;
}
}
#if (DEBUG)
printf("Initializing...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + (N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
#endif
if (on_gpu)
{
cudaMemcpy(device_x, host_x, N*N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(device_y, host_y, N*N*sizeof(float), cudaMemcpyHostToDevice);
}
#if (DEBUG)
printf("Computing y[i][j] = 6*x[i][j] + y[i][j]\n\n");
#endif
clock_t start, end;
double time_used;
if (on_gpu)
{
// Runs on the GPU.
start = clock();
cuda_saxpy_mat_1<<<blocks_per_grid,threads_per_block>>>(N, a, device_x, device_y);
// This is only a fair comparison if the device synchronization is invoked, since it awaits the end of the computation.
cudaDeviceSynchronize();
end = clock();
}
else
{
// Runs on the CPU.
start = clock();
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_y + i*N + j) = a * *(host_x + i*N + j) + *(host_y + i*N + j);
}
}
end = clock();
}
time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
if (on_gpu)
{
cudaMemcpy(host_y, device_y, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
}
#if (DEBUG)
printf("Outputting...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + 0*(N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
printf("Elapsed time: %f ms\n\n", 1e3*time_used);
#endif
if (on_gpu)
{
cudaFree(device_x);
cudaFree(device_y);
}
#if (DEBUG)
if (on_gpu)
{
printf("Look how fast that was!\n\n\n");
}
else
{
printf("Look how fast that wasn't!\n\n\n");
}
#endif
if (*(host_y + (N-1)*N + (N-1)) < 5.0f)
{
printf("Error detected. Stop.\n\n");
exit(1);
}
free(host_x);
free(host_y);
return 1e3*time_used;
}
int main()
{
// Benchmarks a SAXPY matrix operation on CPU vs GPU
// Define the dimensions of the matrix. GPU performance overtakes CPU performance around N = 2^11 - 2^12 (64 MB).
// Program crashes for N = 2^15 (4 GB).
int N = 1<<14;
int N2 = N*N;
// Output
printf("Runtimes for N*N = %d (%f MB):\n\n", N2, sizeof(float)*N2/(1024.0f*1024.0f));
clock_t start, end;
double time_used_total_cpu, time_used_total_gpu;
// Run on GPU first
start = clock();
double gpu_time = run_computation(true, N);
end = clock();
time_used_total_gpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Run on CPU
start = clock();
double cpu_time = run_computation(false, N);
end = clock();
time_used_total_cpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Output
printf(" CPU computation: %f ms\n", cpu_time);
printf(" CPU total: %f ms\n\n", time_used_total_cpu);
printf(" GPU computation: %f ms\n", gpu_time);
printf(" GPU total: %f ms\n\n", time_used_total_gpu);
return 0;
} | code for sm_80
Function : _Z16cuda_saxpy_mat_1ifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#define DEBUG false
// Simple SAXPY operation.
__global__ void cuda_saxpy_mat_1(int N, float a, float *x, float *y)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < N*N)
{
y[index] = a * x[index] + y[index];
}
}
void wait()
{
puts("Press any key to continue...");
getchar();
}
// Heavy lifting
double run_computation(bool on_gpu, int N)
{
#if(DEBUG)
printf("N = %d\n\n", N);
#endif
float a = 6.0f;
float *host_x, *host_y, *device_x, *device_y;
host_x = (float*)malloc(N*N*sizeof(float));
host_y = (float*)malloc(N*N*sizeof(float));
if (on_gpu)
{
cudaMalloc(&device_x, N*N*sizeof(float));
cudaMalloc(&device_y, N*N*sizeof(float));
}
dim3 blocks_per_grid((N*N+255)/256, 1, 1);
dim3 threads_per_block(256, 1, 1);
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_x + i*N + j) = 1.0f;
*(host_y + i*N + j) = 3.0f;
}
}
#if (DEBUG)
printf("Initializing...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + (N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
#endif
if (on_gpu)
{
cudaMemcpy(device_x, host_x, N*N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(device_y, host_y, N*N*sizeof(float), cudaMemcpyHostToDevice);
}
#if (DEBUG)
printf("Computing y[i][j] = 6*x[i][j] + y[i][j]\n\n");
#endif
clock_t start, end;
double time_used;
if (on_gpu)
{
// Runs on the GPU.
start = clock();
cuda_saxpy_mat_1<<<blocks_per_grid,threads_per_block>>>(N, a, device_x, device_y);
// This is only a fair comparison if the device synchronization is invoked, since it awaits the end of the computation.
cudaDeviceSynchronize();
end = clock();
}
else
{
// Runs on the CPU.
start = clock();
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_y + i*N + j) = a * *(host_x + i*N + j) + *(host_y + i*N + j);
}
}
end = clock();
}
time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
if (on_gpu)
{
cudaMemcpy(host_y, device_y, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
}
#if (DEBUG)
printf("Outputting...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + 0*(N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
printf("Elapsed time: %f ms\n\n", 1e3*time_used);
#endif
if (on_gpu)
{
cudaFree(device_x);
cudaFree(device_y);
}
#if (DEBUG)
if (on_gpu)
{
printf("Look how fast that was!\n\n\n");
}
else
{
printf("Look how fast that wasn't!\n\n\n");
}
#endif
if (*(host_y + (N-1)*N + (N-1)) < 5.0f)
{
printf("Error detected. Stop.\n\n");
exit(1);
}
free(host_x);
free(host_y);
return 1e3*time_used;
}
int main()
{
// Benchmarks a SAXPY matrix operation on CPU vs GPU
// Define the dimensions of the matrix. GPU performance overtakes CPU performance around N = 2^11 - 2^12 (64 MB).
// Program crashes for N = 2^15 (4 GB).
int N = 1<<14;
int N2 = N*N;
// Output
printf("Runtimes for N*N = %d (%f MB):\n\n", N2, sizeof(float)*N2/(1024.0f*1024.0f));
clock_t start, end;
double time_used_total_cpu, time_used_total_gpu;
// Run on GPU first
start = clock();
double gpu_time = run_computation(true, N);
end = clock();
time_used_total_gpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Run on CPU
start = clock();
double cpu_time = run_computation(false, N);
end = clock();
time_used_total_cpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Output
printf(" CPU computation: %f ms\n", cpu_time);
printf(" CPU total: %f ms\n\n", time_used_total_cpu);
printf(" GPU computation: %f ms\n", gpu_time);
printf(" GPU total: %f ms\n\n", time_used_total_gpu);
return 0;
} | .file "tmpxft_0001c560_00000000-6_benchmarking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Press any key to continue..."
.text
.globl _Z4waitv
.type _Z4waitv, @function
_Z4waitv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdi
call puts@PLT
movq stdin(%rip), %rdi
call getc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4waitv, .-_Z4waitv
.globl _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_
.type _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_, @function
_Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16cuda_saxpy_mat_1ifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_, .-_Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_
.globl _Z16cuda_saxpy_mat_1ifPfS_
.type _Z16cuda_saxpy_mat_1ifPfS_, @function
_Z16cuda_saxpy_mat_1ifPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16cuda_saxpy_mat_1ifPfS_, .-_Z16cuda_saxpy_mat_1ifPfS_
.section .rodata.str1.1
.LC6:
.string "Error detected. Stop.\n\n"
.text
.globl _Z15run_computationbi
.type _Z15run_computationbi, @function
_Z15run_computationbi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r13d
movl %edi, 12(%rsp)
movl %esi, %r15d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %esi, %ebx
imull %esi, %ebx
movslq %ebx, %rax
leaq 0(,%rax,4), %r14
movq %r14, (%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
testb %r13b, %r13b
jne .L36
leal 510(%rbx), %eax
addl $255, %ebx
cmovns %ebx, %eax
sarl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
testl %r15d, %r15d
jle .L37
.L26:
movslq %r15d, %rcx
leaq 0(,%rcx,4), %r13
movl $0, %edx
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L16:
leaq 0(,%rdx,4), %rax
movl $0, %ebx
.L17:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
movl %ebx, %r14d
addl $1, %ebx
addq %r13, %rax
cmpl %ebx, %r15d
jne .L17
addq $1, %rdx
cmpq %rcx, %rdx
jne .L16
cmpb $0, 12(%rsp)
jne .L15
call clock@PLT
movq %rax, (%rsp)
movslq %ebx, %rbx
movl $0, %esi
movss .LC3(%rip), %xmm1
.L19:
leaq 0(,%rsi,4), %rax
movl $0, %edx
.L22:
movaps %xmm1, %xmm0
mulss (%r12,%rax), %xmm0
addss 0(%rbp,%rax), %xmm0
movss %xmm0, 0(%rbp,%rax)
movl %edx, %ecx
addl $1, %edx
addq %r13, %rax
cmpl %ecx, %r14d
jne .L22
addq $1, %rsi
cmpq %rsi, %rbx
jne .L19
.L23:
call clock@PLT
movq (%rsp), %rdi
subq %rdi, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq %xmm0, %rbx
jmp .L21
.L36:
leaq 16(%rsp), %rdi
movq (%rsp), %r14
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leal 510(%rbx), %eax
addl $255, %ebx
cmovns %ebx, %eax
sarl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
testl %r15d, %r15d
jg .L26
.L15:
movl $1, %ecx
movq (%rsp), %rbx
movq %rbx, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %rbx
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L20:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq %xmm0, %rbx
movl $2, %ecx
movq (%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
.L21:
leal -1(%r15), %eax
imull %r15d, %eax
cltq
movslq %r15d, %r15
addq %r15, %rax
movss .LC5(%rip), %xmm0
comiss -4(%rbp,%rax,4), %xmm0
ja .L39
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %xmm0
mulsd .LC7(%rip), %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movss .LC3(%rip), %xmm0
movl %r15d, %edi
call _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_
jmp .L20
.L39:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
call clock@PLT
movq %rax, (%rsp)
jmp .L23
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z15run_computationbi, .-_Z15run_computationbi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "Runtimes for N*N = %d (%f MB):\n\n"
.section .rodata.str1.1
.LC10:
.string " CPU computation: %f ms\n"
.LC11:
.string " CPU total: %f ms\n\n"
.LC12:
.string " GPU computation: %f ms\n"
.LC13:
.string " GPU total: %f ms\n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movsd .LC8(%rip), %xmm0
movl $268435456, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $16384, %esi
movl $1, %edi
call _Z15run_computationbi
movsd %xmm0, (%rsp)
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC7(%rip), %xmm0
movapd %xmm0, %xmm1
divsd .LC4(%rip), %xmm1
movsd %xmm1, 8(%rsp)
call clock@PLT
movq %rax, %rbx
movl $16384, %esi
movl $0, %edi
call _Z15run_computationbi
movsd %xmm0, 16(%rsp)
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC7(%rip), %xmm0
movapd %xmm0, %xmm2
divsd .LC4(%rip), %xmm2
movsd %xmm2, 24(%rsp)
movsd 16(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z16cuda_saxpy_mat_1ifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z16cuda_saxpy_mat_1ifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1077936128
.align 4
.LC3:
.long 1086324736
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.section .rodata.cst4
.align 4
.LC5:
.long 1084227584
.section .rodata.cst8
.align 8
.LC7:
.long 0
.long 1083129856
.align 8
.LC8:
.long 0
.long 1083179008
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#define DEBUG false
// Simple SAXPY operation.
__global__ void cuda_saxpy_mat_1(int N, float a, float *x, float *y)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < N*N)
{
y[index] = a * x[index] + y[index];
}
}
void wait()
{
puts("Press any key to continue...");
getchar();
}
// Heavy lifting
double run_computation(bool on_gpu, int N)
{
#if(DEBUG)
printf("N = %d\n\n", N);
#endif
float a = 6.0f;
float *host_x, *host_y, *device_x, *device_y;
host_x = (float*)malloc(N*N*sizeof(float));
host_y = (float*)malloc(N*N*sizeof(float));
if (on_gpu)
{
cudaMalloc(&device_x, N*N*sizeof(float));
cudaMalloc(&device_y, N*N*sizeof(float));
}
dim3 blocks_per_grid((N*N+255)/256, 1, 1);
dim3 threads_per_block(256, 1, 1);
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_x + i*N + j) = 1.0f;
*(host_y + i*N + j) = 3.0f;
}
}
#if (DEBUG)
printf("Initializing...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + (N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
#endif
if (on_gpu)
{
cudaMemcpy(device_x, host_x, N*N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(device_y, host_y, N*N*sizeof(float), cudaMemcpyHostToDevice);
}
#if (DEBUG)
printf("Computing y[i][j] = 6*x[i][j] + y[i][j]\n\n");
#endif
clock_t start, end;
double time_used;
if (on_gpu)
{
// Runs on the GPU.
start = clock();
cuda_saxpy_mat_1<<<blocks_per_grid,threads_per_block>>>(N, a, device_x, device_y);
// This is only a fair comparison if the device synchronization is invoked, since it awaits the end of the computation.
cudaDeviceSynchronize();
end = clock();
}
else
{
// Runs on the CPU.
start = clock();
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_y + i*N + j) = a * *(host_x + i*N + j) + *(host_y + i*N + j);
}
}
end = clock();
}
time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
if (on_gpu)
{
cudaMemcpy(host_y, device_y, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
}
#if (DEBUG)
printf("Outputting...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + 0*(N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
printf("Elapsed time: %f ms\n\n", 1e3*time_used);
#endif
if (on_gpu)
{
cudaFree(device_x);
cudaFree(device_y);
}
#if (DEBUG)
if (on_gpu)
{
printf("Look how fast that was!\n\n\n");
}
else
{
printf("Look how fast that wasn't!\n\n\n");
}
#endif
if (*(host_y + (N-1)*N + (N-1)) < 5.0f)
{
printf("Error detected. Stop.\n\n");
exit(1);
}
free(host_x);
free(host_y);
return 1e3*time_used;
}
int main()
{
// Benchmarks a SAXPY matrix operation on CPU vs GPU
// Define the dimensions of the matrix. GPU performance overtakes CPU performance around N = 2^11 - 2^12 (64 MB).
// Program crashes for N = 2^15 (4 GB).
int N = 1<<14;
int N2 = N*N;
// Output
printf("Runtimes for N*N = %d (%f MB):\n\n", N2, sizeof(float)*N2/(1024.0f*1024.0f));
clock_t start, end;
double time_used_total_cpu, time_used_total_gpu;
// Run on GPU first
start = clock();
double gpu_time = run_computation(true, N);
end = clock();
time_used_total_gpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Run on CPU
start = clock();
double cpu_time = run_computation(false, N);
end = clock();
time_used_total_cpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Output
printf(" CPU computation: %f ms\n", cpu_time);
printf(" CPU total: %f ms\n\n", time_used_total_cpu);
printf(" GPU computation: %f ms\n", gpu_time);
printf(" GPU total: %f ms\n\n", time_used_total_gpu);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define DEBUG false
// Simple SAXPY operation.
__global__ void cuda_saxpy_mat_1(int N, float a, float *x, float *y)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < N*N)
{
y[index] = a * x[index] + y[index];
}
}
void wait()
{
puts("Press any key to continue...");
getchar();
}
// Heavy lifting
double run_computation(bool on_gpu, int N)
{
#if(DEBUG)
printf("N = %d\n\n", N);
#endif
float a = 6.0f;
float *host_x, *host_y, *device_x, *device_y;
host_x = (float*)malloc(N*N*sizeof(float));
host_y = (float*)malloc(N*N*sizeof(float));
if (on_gpu)
{
hipMalloc(&device_x, N*N*sizeof(float));
hipMalloc(&device_y, N*N*sizeof(float));
}
dim3 blocks_per_grid((N*N+255)/256, 1, 1);
dim3 threads_per_block(256, 1, 1);
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_x + i*N + j) = 1.0f;
*(host_y + i*N + j) = 3.0f;
}
}
#if (DEBUG)
printf("Initializing...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + (N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
#endif
if (on_gpu)
{
hipMemcpy(device_x, host_x, N*N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(device_y, host_y, N*N*sizeof(float), hipMemcpyHostToDevice);
}
#if (DEBUG)
printf("Computing y[i][j] = 6*x[i][j] + y[i][j]\n\n");
#endif
clock_t start, end;
double time_used;
if (on_gpu)
{
// Runs on the GPU.
start = clock();
cuda_saxpy_mat_1<<<blocks_per_grid,threads_per_block>>>(N, a, device_x, device_y);
// This is only a fair comparison if the device synchronization is invoked, since it awaits the end of the computation.
hipDeviceSynchronize();
end = clock();
}
else
{
// Runs on the CPU.
start = clock();
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_y + i*N + j) = a * *(host_x + i*N + j) + *(host_y + i*N + j);
}
}
end = clock();
}
time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
if (on_gpu)
{
hipMemcpy(host_y, device_y, N*N*sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
}
#if (DEBUG)
printf("Outputting...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + 0*(N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
printf("Elapsed time: %f ms\n\n", 1e3*time_used);
#endif
if (on_gpu)
{
hipFree(device_x);
hipFree(device_y);
}
#if (DEBUG)
if (on_gpu)
{
printf("Look how fast that was!\n\n\n");
}
else
{
printf("Look how fast that wasn't!\n\n\n");
}
#endif
if (*(host_y + (N-1)*N + (N-1)) < 5.0f)
{
printf("Error detected. Stop.\n\n");
exit(1);
}
free(host_x);
free(host_y);
return 1e3*time_used;
}
int main()
{
// Benchmarks a SAXPY matrix operation on CPU vs GPU
// Define the dimensions of the matrix. GPU performance overtakes CPU performance around N = 2^11 - 2^12 (64 MB).
// Program crashes for N = 2^15 (4 GB).
int N = 1<<14;
int N2 = N*N;
// Output
printf("Runtimes for N*N = %d (%f MB):\n\n", N2, sizeof(float)*N2/(1024.0f*1024.0f));
clock_t start, end;
double time_used_total_cpu, time_used_total_gpu;
// Run on GPU first
start = clock();
double gpu_time = run_computation(true, N);
end = clock();
time_used_total_gpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Run on CPU
start = clock();
double cpu_time = run_computation(false, N);
end = clock();
time_used_total_cpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Output
printf(" CPU computation: %f ms\n", cpu_time);
printf(" CPU total: %f ms\n\n", time_used_total_cpu);
printf(" GPU computation: %f ms\n", gpu_time);
printf(" GPU total: %f ms\n\n", time_used_total_gpu);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define DEBUG false
// Simple SAXPY operation.
__global__ void cuda_saxpy_mat_1(int N, float a, float *x, float *y)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < N*N)
{
y[index] = a * x[index] + y[index];
}
}
void wait()
{
puts("Press any key to continue...");
getchar();
}
// Heavy lifting
double run_computation(bool on_gpu, int N)
{
#if(DEBUG)
printf("N = %d\n\n", N);
#endif
float a = 6.0f;
float *host_x, *host_y, *device_x, *device_y;
host_x = (float*)malloc(N*N*sizeof(float));
host_y = (float*)malloc(N*N*sizeof(float));
if (on_gpu)
{
hipMalloc(&device_x, N*N*sizeof(float));
hipMalloc(&device_y, N*N*sizeof(float));
}
dim3 blocks_per_grid((N*N+255)/256, 1, 1);
dim3 threads_per_block(256, 1, 1);
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_x + i*N + j) = 1.0f;
*(host_y + i*N + j) = 3.0f;
}
}
#if (DEBUG)
printf("Initializing...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + (N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
#endif
if (on_gpu)
{
hipMemcpy(device_x, host_x, N*N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(device_y, host_y, N*N*sizeof(float), hipMemcpyHostToDevice);
}
#if (DEBUG)
printf("Computing y[i][j] = 6*x[i][j] + y[i][j]\n\n");
#endif
clock_t start, end;
double time_used;
if (on_gpu)
{
// Runs on the GPU.
start = clock();
cuda_saxpy_mat_1<<<blocks_per_grid,threads_per_block>>>(N, a, device_x, device_y);
// This is only a fair comparison if the device synchronization is invoked, since it awaits the end of the computation.
hipDeviceSynchronize();
end = clock();
}
else
{
// Runs on the CPU.
start = clock();
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_y + i*N + j) = a * *(host_x + i*N + j) + *(host_y + i*N + j);
}
}
end = clock();
}
time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
if (on_gpu)
{
hipMemcpy(host_y, device_y, N*N*sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
}
#if (DEBUG)
printf("Outputting...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + 0*(N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
printf("Elapsed time: %f ms\n\n", 1e3*time_used);
#endif
if (on_gpu)
{
hipFree(device_x);
hipFree(device_y);
}
#if (DEBUG)
if (on_gpu)
{
printf("Look how fast that was!\n\n\n");
}
else
{
printf("Look how fast that wasn't!\n\n\n");
}
#endif
if (*(host_y + (N-1)*N + (N-1)) < 5.0f)
{
printf("Error detected. Stop.\n\n");
exit(1);
}
free(host_x);
free(host_y);
return 1e3*time_used;
}
int main()
{
// Benchmarks a SAXPY matrix operation on CPU vs GPU
// Define the dimensions of the matrix. GPU performance overtakes CPU performance around N = 2^11 - 2^12 (64 MB).
// Program crashes for N = 2^15 (4 GB).
int N = 1<<14;
int N2 = N*N;
// Output
printf("Runtimes for N*N = %d (%f MB):\n\n", N2, sizeof(float)*N2/(1024.0f*1024.0f));
clock_t start, end;
double time_used_total_cpu, time_used_total_gpu;
// Run on GPU first
start = clock();
double gpu_time = run_computation(true, N);
end = clock();
time_used_total_gpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Run on CPU
start = clock();
double cpu_time = run_computation(false, N);
end = clock();
time_used_total_cpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Output
printf(" CPU computation: %f ms\n", cpu_time);
printf(" CPU total: %f ms\n\n", time_used_total_cpu);
printf(" GPU computation: %f ms\n", gpu_time);
printf(" GPU total: %f ms\n\n", time_used_total_gpu);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16cuda_saxpy_mat_1ifPfS_
.globl _Z16cuda_saxpy_mat_1ifPfS_
.p2align 8
.type _Z16cuda_saxpy_mat_1ifPfS_,@function
_Z16cuda_saxpy_mat_1ifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s3, s3, s3
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16cuda_saxpy_mat_1ifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16cuda_saxpy_mat_1ifPfS_, .Lfunc_end0-_Z16cuda_saxpy_mat_1ifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16cuda_saxpy_mat_1ifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16cuda_saxpy_mat_1ifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define DEBUG false
// Simple SAXPY operation.
__global__ void cuda_saxpy_mat_1(int N, float a, float *x, float *y)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if (index < N*N)
{
y[index] = a * x[index] + y[index];
}
}
void wait()
{
puts("Press any key to continue...");
getchar();
}
// Heavy lifting
double run_computation(bool on_gpu, int N)
{
#if(DEBUG)
printf("N = %d\n\n", N);
#endif
float a = 6.0f;
float *host_x, *host_y, *device_x, *device_y;
host_x = (float*)malloc(N*N*sizeof(float));
host_y = (float*)malloc(N*N*sizeof(float));
if (on_gpu)
{
hipMalloc(&device_x, N*N*sizeof(float));
hipMalloc(&device_y, N*N*sizeof(float));
}
dim3 blocks_per_grid((N*N+255)/256, 1, 1);
dim3 threads_per_block(256, 1, 1);
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_x + i*N + j) = 1.0f;
*(host_y + i*N + j) = 3.0f;
}
}
#if (DEBUG)
printf("Initializing...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + (N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
#endif
if (on_gpu)
{
hipMemcpy(device_x, host_x, N*N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(device_y, host_y, N*N*sizeof(float), hipMemcpyHostToDevice);
}
#if (DEBUG)
printf("Computing y[i][j] = 6*x[i][j] + y[i][j]\n\n");
#endif
clock_t start, end;
double time_used;
if (on_gpu)
{
// Runs on the GPU.
start = clock();
cuda_saxpy_mat_1<<<blocks_per_grid,threads_per_block>>>(N, a, device_x, device_y);
// This is only a fair comparison if the device synchronization is invoked, since it awaits the end of the computation.
hipDeviceSynchronize();
end = clock();
}
else
{
// Runs on the CPU.
start = clock();
for (int j = 0; j < N; j++)
{
for (int i = 0; i < N; i++)
{
*(host_y + i*N + j) = a * *(host_x + i*N + j) + *(host_y + i*N + j);
}
}
end = clock();
}
time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
if (on_gpu)
{
hipMemcpy(host_y, device_y, N*N*sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
}
#if (DEBUG)
printf("Outputting...\n");
printf("x[0][0] = %f\n", *(host_x + 0*N + 0));
printf("...\n");
printf("x[N-1][N-1] = %f\n\n", *(host_x + (N-1)*N + 0*(N-1)));
printf("y[0][0] = %f\n", *(host_y + 0*N + 0));
printf("...\n");
printf("y[N-1][N-1] = %f\n\n", *(host_y + (N-1)*N + (N-1)));
printf("Elapsed time: %f ms\n\n", 1e3*time_used);
#endif
if (on_gpu)
{
hipFree(device_x);
hipFree(device_y);
}
#if (DEBUG)
if (on_gpu)
{
printf("Look how fast that was!\n\n\n");
}
else
{
printf("Look how fast that wasn't!\n\n\n");
}
#endif
if (*(host_y + (N-1)*N + (N-1)) < 5.0f)
{
printf("Error detected. Stop.\n\n");
exit(1);
}
free(host_x);
free(host_y);
return 1e3*time_used;
}
int main()
{
// Benchmarks a SAXPY matrix operation on CPU vs GPU
// Define the dimensions of the matrix. GPU performance overtakes CPU performance around N = 2^11 - 2^12 (64 MB).
// Program crashes for N = 2^15 (4 GB).
int N = 1<<14;
int N2 = N*N;
// Output
printf("Runtimes for N*N = %d (%f MB):\n\n", N2, sizeof(float)*N2/(1024.0f*1024.0f));
clock_t start, end;
double time_used_total_cpu, time_used_total_gpu;
// Run on GPU first
start = clock();
double gpu_time = run_computation(true, N);
end = clock();
time_used_total_gpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Run on CPU
start = clock();
double cpu_time = run_computation(false, N);
end = clock();
time_used_total_cpu = 1e3*((double) (end - start)) / CLOCKS_PER_SEC;
// Output
printf(" CPU computation: %f ms\n", cpu_time);
printf(" CPU total: %f ms\n\n", time_used_total_cpu);
printf(" GPU computation: %f ms\n", gpu_time);
printf(" GPU total: %f ms\n\n", time_used_total_gpu);
return 0;
} | .text
.file "benchmarking.hip"
.globl _Z31__device_stub__cuda_saxpy_mat_1ifPfS_ # -- Begin function _Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.p2align 4, 0x90
.type _Z31__device_stub__cuda_saxpy_mat_1ifPfS_,@function
_Z31__device_stub__cuda_saxpy_mat_1ifPfS_: # @_Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16cuda_saxpy_mat_1ifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__cuda_saxpy_mat_1ifPfS_, .Lfunc_end0-_Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.cfi_endproc
# -- End function
.globl _Z4waitv # -- Begin function _Z4waitv
.p2align 4, 0x90
.type _Z4waitv,@function
_Z4waitv: # @_Z4waitv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
callq puts
movq stdin(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp getc # TAILCALL
.Lfunc_end1:
.size _Z4waitv, .Lfunc_end1-_Z4waitv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15run_computationbi
.LCPI2_0:
.long 0x40c00000 # float 6
.LCPI2_1:
.long 0x40a00000 # float 5
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_3:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z15run_computationbi
.p2align 4, 0x90
.type _Z15run_computationbi,@function
_Z15run_computationbi: # @_Z15run_computationbi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r13d
movl %edi, %ebp
movl %esi, %r15d
imull %r15d, %r15d
leaq (,%r15,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
testl %ebp, %ebp
je .LBB2_2
# %bb.1:
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.LBB2_2:
testl %r13d, %r13d
jle .LBB2_7
# %bb.3: # %.preheader83.lr.ph
movl %r13d, %eax
leaq (,%rax,4), %rcx
xorl %edx, %edx
movq %rbx, %rsi
movq %r14, %rdi
.p2align 4, 0x90
.LBB2_4: # %.preheader83
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
movq %rax, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rsi,%r9) # imm = 0x3F800000
movl $1077936128, (%rdi,%r9) # imm = 0x40400000
addq %rcx, %r9
decq %r8
jne .LBB2_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB2_4 Depth=1
incq %rdx
addq $4, %rdi
addq $4, %rsi
cmpq %rax, %rdx
jne .LBB2_4
.LBB2_7: # %._crit_edge88
testb %bpl, %bpl
je .LBB2_11
# %bb.8:
addl $255, %r15d
shrl $8, %r15d
movq %rbx, %rsi
movabsq $4294967296, %rbx # imm = 0x100000000
orq %rbx, %r15
movq 24(%rsp), %rdi
movq %rsi, 40(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
addq $256, %rbx # imm = 0x100
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl %r13d, 36(%rsp)
movl $1086324736, 32(%rsp) # imm = 0x40C00000
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16cuda_saxpy_mat_1ifPfS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movq 40(%rsp), %rbx # 8-byte Reload
jmp .LBB2_16
.LBB2_11: # %.critedge
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB2_16
# %bb.12: # %.preheader.lr.ph
movl %r13d, %eax
leaq (,%rax,4), %rcx
xorl %edx, %edx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rsi
movq %r14, %rdi
.p2align 4, 0x90
.LBB2_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
movq %rax, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rdi,%r9), %xmm1
movss %xmm1, (%rdi,%r9)
addq %rcx, %r9
decq %r8
jne .LBB2_14
# %bb.15: # %._crit_edge91
# in Loop: Header=BB2_13 Depth=1
incq %rdx
addq $4, %rdi
addq $4, %rsi
cmpq %rax, %rdx
jne .LBB2_13
.LBB2_16: # %._crit_edge97
callq clock
movq %rax, %r15
testb %bpl, %bpl
je .LBB2_18
# %bb.17:
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
.LBB2_18: # %.critedge80
leal -1(%r13), %eax
imull %r13d, %eax
cltq
leaq (%r14,%rax,4), %rax
movslq %r13d, %rcx
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss -4(%rax,%rcx,4), %xmm0
ja .LBB2_20
# %bb.19:
subq 8(%rsp), %r15 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI2_3(%rip), %xmm0
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_20:
.cfi_def_cfa_offset 208
movl $.Lstr, %edi
callq puts
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z15run_computationbi, .Lfunc_end2-_Z15run_computationbi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x4090000000000000 # double 1024
.LCPI3_1:
.quad 0x408f400000000000 # double 1000
.LCPI3_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movl $268435456, %esi # imm = 0x10000000
movb $1, %al
callq printf
callq clock
movq %rax, %rbx
movl $1, %edi
movl $16384, %esi # imm = 0x4000
callq _Z15run_computationbi
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd .LCPI3_2(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq clock
movq %rax, %rbx
xorl %edi, %edi
movl $16384, %esi # imm = 0x4000
callq _Z15run_computationbi
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd .LCPI3_2(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.5, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.6, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16cuda_saxpy_mat_1ifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16cuda_saxpy_mat_1ifPfS_,@object # @_Z16cuda_saxpy_mat_1ifPfS_
.section .rodata,"a",@progbits
.globl _Z16cuda_saxpy_mat_1ifPfS_
.p2align 3, 0x0
_Z16cuda_saxpy_mat_1ifPfS_:
.quad _Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.size _Z16cuda_saxpy_mat_1ifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Press any key to continue..."
.size .L.str, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Runtimes for N*N = %d (%f MB):\n\n"
.size .L.str.2, 33
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " CPU computation: %f ms\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " CPU total: %f ms\n\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " GPU computation: %f ms\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " GPU total: %f ms\n\n"
.size .L.str.6, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16cuda_saxpy_mat_1ifPfS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error detected. Stop.\n"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16cuda_saxpy_mat_1ifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16cuda_saxpy_mat_1ifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16cuda_saxpy_mat_1ifPfS_
.globl _Z16cuda_saxpy_mat_1ifPfS_
.p2align 8
.type _Z16cuda_saxpy_mat_1ifPfS_,@function
_Z16cuda_saxpy_mat_1ifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s3, s3, s3
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16cuda_saxpy_mat_1ifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16cuda_saxpy_mat_1ifPfS_, .Lfunc_end0-_Z16cuda_saxpy_mat_1ifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16cuda_saxpy_mat_1ifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16cuda_saxpy_mat_1ifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001c560_00000000-6_benchmarking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Press any key to continue..."
.text
.globl _Z4waitv
.type _Z4waitv, @function
_Z4waitv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdi
call puts@PLT
movq stdin(%rip), %rdi
call getc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4waitv, .-_Z4waitv
.globl _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_
.type _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_, @function
_Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16cuda_saxpy_mat_1ifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_, .-_Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_
.globl _Z16cuda_saxpy_mat_1ifPfS_
.type _Z16cuda_saxpy_mat_1ifPfS_, @function
_Z16cuda_saxpy_mat_1ifPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16cuda_saxpy_mat_1ifPfS_, .-_Z16cuda_saxpy_mat_1ifPfS_
.section .rodata.str1.1
.LC6:
.string "Error detected. Stop.\n\n"
.text
.globl _Z15run_computationbi
.type _Z15run_computationbi, @function
_Z15run_computationbi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r13d
movl %edi, 12(%rsp)
movl %esi, %r15d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %esi, %ebx
imull %esi, %ebx
movslq %ebx, %rax
leaq 0(,%rax,4), %r14
movq %r14, (%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
testb %r13b, %r13b
jne .L36
leal 510(%rbx), %eax
addl $255, %ebx
cmovns %ebx, %eax
sarl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
testl %r15d, %r15d
jle .L37
.L26:
movslq %r15d, %rcx
leaq 0(,%rcx,4), %r13
movl $0, %edx
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L16:
leaq 0(,%rdx,4), %rax
movl $0, %ebx
.L17:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
movl %ebx, %r14d
addl $1, %ebx
addq %r13, %rax
cmpl %ebx, %r15d
jne .L17
addq $1, %rdx
cmpq %rcx, %rdx
jne .L16
cmpb $0, 12(%rsp)
jne .L15
call clock@PLT
movq %rax, (%rsp)
movslq %ebx, %rbx
movl $0, %esi
movss .LC3(%rip), %xmm1
.L19:
leaq 0(,%rsi,4), %rax
movl $0, %edx
.L22:
movaps %xmm1, %xmm0
mulss (%r12,%rax), %xmm0
addss 0(%rbp,%rax), %xmm0
movss %xmm0, 0(%rbp,%rax)
movl %edx, %ecx
addl $1, %edx
addq %r13, %rax
cmpl %ecx, %r14d
jne .L22
addq $1, %rsi
cmpq %rsi, %rbx
jne .L19
.L23:
call clock@PLT
movq (%rsp), %rdi
subq %rdi, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq %xmm0, %rbx
jmp .L21
.L36:
leaq 16(%rsp), %rdi
movq (%rsp), %r14
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leal 510(%rbx), %eax
addl $255, %ebx
cmovns %ebx, %eax
sarl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
testl %r15d, %r15d
jg .L26
.L15:
movl $1, %ecx
movq (%rsp), %rbx
movq %rbx, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %rbx
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L20:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq %xmm0, %rbx
movl $2, %ecx
movq (%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
.L21:
leal -1(%r15), %eax
imull %r15d, %eax
cltq
movslq %r15d, %r15
addq %r15, %rax
movss .LC5(%rip), %xmm0
comiss -4(%rbp,%rax,4), %xmm0
ja .L39
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %xmm0
mulsd .LC7(%rip), %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movss .LC3(%rip), %xmm0
movl %r15d, %edi
call _Z40__device_stub__Z16cuda_saxpy_mat_1ifPfS_ifPfS_
jmp .L20
.L39:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
call clock@PLT
movq %rax, (%rsp)
jmp .L23
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z15run_computationbi, .-_Z15run_computationbi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "Runtimes for N*N = %d (%f MB):\n\n"
.section .rodata.str1.1
.LC10:
.string " CPU computation: %f ms\n"
.LC11:
.string " CPU total: %f ms\n\n"
.LC12:
.string " GPU computation: %f ms\n"
.LC13:
.string " GPU total: %f ms\n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movsd .LC8(%rip), %xmm0
movl $268435456, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $16384, %esi
movl $1, %edi
call _Z15run_computationbi
movsd %xmm0, (%rsp)
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC7(%rip), %xmm0
movapd %xmm0, %xmm1
divsd .LC4(%rip), %xmm1
movsd %xmm1, 8(%rsp)
call clock@PLT
movq %rax, %rbx
movl $16384, %esi
movl $0, %edi
call _Z15run_computationbi
movsd %xmm0, 16(%rsp)
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC7(%rip), %xmm0
movapd %xmm0, %xmm2
divsd .LC4(%rip), %xmm2
movsd %xmm2, 24(%rsp)
movsd 16(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z16cuda_saxpy_mat_1ifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z16cuda_saxpy_mat_1ifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1077936128
.align 4
.LC3:
.long 1086324736
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.section .rodata.cst4
.align 4
.LC5:
.long 1084227584
.section .rodata.cst8
.align 8
.LC7:
.long 0
.long 1083129856
.align 8
.LC8:
.long 0
.long 1083179008
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "benchmarking.hip"
.globl _Z31__device_stub__cuda_saxpy_mat_1ifPfS_ # -- Begin function _Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.p2align 4, 0x90
.type _Z31__device_stub__cuda_saxpy_mat_1ifPfS_,@function
_Z31__device_stub__cuda_saxpy_mat_1ifPfS_: # @_Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16cuda_saxpy_mat_1ifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__cuda_saxpy_mat_1ifPfS_, .Lfunc_end0-_Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.cfi_endproc
# -- End function
.globl _Z4waitv # -- Begin function _Z4waitv
.p2align 4, 0x90
.type _Z4waitv,@function
_Z4waitv: # @_Z4waitv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
callq puts
movq stdin(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp getc # TAILCALL
.Lfunc_end1:
.size _Z4waitv, .Lfunc_end1-_Z4waitv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15run_computationbi
.LCPI2_0:
.long 0x40c00000 # float 6
.LCPI2_1:
.long 0x40a00000 # float 5
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_3:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z15run_computationbi
.p2align 4, 0x90
.type _Z15run_computationbi,@function
_Z15run_computationbi: # @_Z15run_computationbi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r13d
movl %edi, %ebp
movl %esi, %r15d
imull %r15d, %r15d
leaq (,%r15,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
testl %ebp, %ebp
je .LBB2_2
# %bb.1:
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.LBB2_2:
testl %r13d, %r13d
jle .LBB2_7
# %bb.3: # %.preheader83.lr.ph
movl %r13d, %eax
leaq (,%rax,4), %rcx
xorl %edx, %edx
movq %rbx, %rsi
movq %r14, %rdi
.p2align 4, 0x90
.LBB2_4: # %.preheader83
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
movq %rax, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rsi,%r9) # imm = 0x3F800000
movl $1077936128, (%rdi,%r9) # imm = 0x40400000
addq %rcx, %r9
decq %r8
jne .LBB2_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB2_4 Depth=1
incq %rdx
addq $4, %rdi
addq $4, %rsi
cmpq %rax, %rdx
jne .LBB2_4
.LBB2_7: # %._crit_edge88
testb %bpl, %bpl
je .LBB2_11
# %bb.8:
addl $255, %r15d
shrl $8, %r15d
movq %rbx, %rsi
movabsq $4294967296, %rbx # imm = 0x100000000
orq %rbx, %r15
movq 24(%rsp), %rdi
movq %rsi, 40(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
addq $256, %rbx # imm = 0x100
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl %r13d, 36(%rsp)
movl $1086324736, 32(%rsp) # imm = 0x40C00000
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16cuda_saxpy_mat_1ifPfS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movq 40(%rsp), %rbx # 8-byte Reload
jmp .LBB2_16
.LBB2_11: # %.critedge
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB2_16
# %bb.12: # %.preheader.lr.ph
movl %r13d, %eax
leaq (,%rax,4), %rcx
xorl %edx, %edx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rsi
movq %r14, %rdi
.p2align 4, 0x90
.LBB2_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
movq %rax, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_14: # Parent Loop BB2_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rdi,%r9), %xmm1
movss %xmm1, (%rdi,%r9)
addq %rcx, %r9
decq %r8
jne .LBB2_14
# %bb.15: # %._crit_edge91
# in Loop: Header=BB2_13 Depth=1
incq %rdx
addq $4, %rdi
addq $4, %rsi
cmpq %rax, %rdx
jne .LBB2_13
.LBB2_16: # %._crit_edge97
callq clock
movq %rax, %r15
testb %bpl, %bpl
je .LBB2_18
# %bb.17:
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
.LBB2_18: # %.critedge80
leal -1(%r13), %eax
imull %r13d, %eax
cltq
leaq (%r14,%rax,4), %rax
movslq %r13d, %rcx
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss -4(%rax,%rcx,4), %xmm0
ja .LBB2_20
# %bb.19:
subq 8(%rsp), %r15 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI2_3(%rip), %xmm0
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_20:
.cfi_def_cfa_offset 208
movl $.Lstr, %edi
callq puts
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z15run_computationbi, .Lfunc_end2-_Z15run_computationbi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x4090000000000000 # double 1024
.LCPI3_1:
.quad 0x408f400000000000 # double 1000
.LCPI3_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movl $268435456, %esi # imm = 0x10000000
movb $1, %al
callq printf
callq clock
movq %rax, %rbx
movl $1, %edi
movl $16384, %esi # imm = 0x4000
callq _Z15run_computationbi
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd .LCPI3_2(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq clock
movq %rax, %rbx
xorl %edi, %edi
movl $16384, %esi # imm = 0x4000
callq _Z15run_computationbi
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd .LCPI3_2(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.5, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.6, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16cuda_saxpy_mat_1ifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16cuda_saxpy_mat_1ifPfS_,@object # @_Z16cuda_saxpy_mat_1ifPfS_
.section .rodata,"a",@progbits
.globl _Z16cuda_saxpy_mat_1ifPfS_
.p2align 3, 0x0
_Z16cuda_saxpy_mat_1ifPfS_:
.quad _Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.size _Z16cuda_saxpy_mat_1ifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Press any key to continue..."
.size .L.str, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Runtimes for N*N = %d (%f MB):\n\n"
.size .L.str.2, 33
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " CPU computation: %f ms\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " CPU total: %f ms\n\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " GPU computation: %f ms\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " GPU total: %f ms\n\n"
.size .L.str.6, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16cuda_saxpy_mat_1ifPfS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error detected. Stop.\n"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__cuda_saxpy_mat_1ifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16cuda_saxpy_mat_1ifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <iostream>
template<typename T>
struct ShouldSwap
{
__host__ __device__
virtual bool operator() (const T left, const T right) const;
};
template <typename T>
__host__ __device__ __inline__
void swap(T* a, T* r);
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap);
int main(int argc, char** argv)
{
// vector size
const unsigned int size = 10;
// host vector
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
// device vector
int *d_v = 0;
cudaMalloc((void**)&d_v, size * sizeof(int));
cudaMemcpy(d_v, h_v, size * sizeof(int), cudaMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size / 2, 1, 1);
ShouldSwap<int> shouldSwap;
bubbleSort<int> <<<grdDim, blkDim >>>(d_v, size, shouldSwap);
cudaDeviceSynchronize();
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess) {
printf("CUDA error: %s\n", cudaGetErrorString(error));
// system("pause"); // when using VisStudio
exit(-1);
}
cudaMemcpy(h_v, d_v, size * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size - 1 ? " ," : "}");
}
std::cout << std::endl;
// system("pause"); // when using VisStudio
return 0;
}
template<typename T>
__host__ __device__
bool ShouldSwap<T>::operator() (const T left, const T right) const {
return left > right;
}
template<typename T>
__host__ __device__ __inline__
void swap (T* a, T* b) {
T tmp = *a;
*a = *b;
*b = tmp;
}
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap) {
const unsigned int tIdx = threadIdx.x;
for (unsigned int i = 0; i < n; i++) {
unsigned int offset = i % 2;
unsigned int indiceGauche = 2 * tIdx + offset;
unsigned int indiceDroite = indiceGauche + 1;
if (indiceDroite < n) {
if (shouldSwap(v[indiceGauche], v[indiceDroite])) {
swap<T>(&v[indiceGauche], &v[indiceDroite]);
}
}
__syncthreads();
}
} | code for sm_80
Function : _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fda0003f05270 */
/*0020*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0080*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x001fd800078e00ff */
/*00b0*/ @!P0 BRA 0x3c0 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R8, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004087a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.WIDE.U32 R2, R0.reuse, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe200078e0003 */
/*0120*/ IADD3 R7, R0, 0x2, RZ ; /* 0x0000000200077810 */
/* 0x000fd20007ffe0ff */
/*0130*/ BSSY B0, 0x1c0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0140*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f26070 */
/*0150*/ @P0 BRA 0x1b0 ; /* 0x0000005000000947 */
/* 0x001fee0003800000 */
/*0160*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea4000c1e1900 */
/*0180*/ ISETP.GT.AND P2, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fda0003f44270 */
/*0190*/ @P2 STG.E [R2.64], R6 ; /* 0x0000000602002986 */
/* 0x0001e8000c101906 */
/*01a0*/ @P2 STG.E [R2.64+0x4], R5 ; /* 0x0000040502002986 */
/* 0x0001e4000c101906 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ BSSY B0, 0x250 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*01e0*/ @P1 BRA 0x240 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080602057981 */
/* 0x001ea8000c1e1900 */
/*0200*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea4000c1e1900 */
/*0210*/ ISETP.GT.AND P2, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x004fda0003f44270 */
/*0220*/ @P2 STG.E [R2.64+0x4], R5 ; /* 0x0000040502002986 */
/* 0x0001e8000c101906 */
/*0230*/ @P2 STG.E [R2.64+0x8], R6 ; /* 0x0000080602002986 */
/* 0x0001e4000c101906 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ BSSY B0, 0x2e0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0270*/ @P0 BRA 0x2d0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0280*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x001ea8000c1e1900 */
/*0290*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ ISETP.GT.AND P2, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fda0003f44270 */
/*02b0*/ @P2 STG.E [R2.64], R6 ; /* 0x0000000602002986 */
/* 0x0001e8000c101906 */
/*02c0*/ @P2 STG.E [R2.64+0x4], R5 ; /* 0x0000040502002986 */
/* 0x0001e4000c101906 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0300*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f45270 */
/*0310*/ BSSY B0, 0x390 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0320*/ @P1 BRA 0x380 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0330*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080602057981 */
/* 0x001ea8000c1e1900 */
/*0340*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea4000c1e1900 */
/*0350*/ ISETP.GT.AND P1, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x004fda0003f24270 */
/*0360*/ @P1 STG.E [R2.64+0x4], R5 ; /* 0x0000040502001986 */
/* 0x0001e8000c101906 */
/*0370*/ @P1 STG.E [R2.64+0x8], R6 ; /* 0x0000080602001986 */
/* 0x0001e4000c101906 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fca000fffe03f */
/*03b0*/ @P2 BRA 0x130 ; /* 0xfffffd7000002947 */
/* 0x000fea000383ffff */
/*03c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*03d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03e0*/ ULOP3.LUT UR5, UR4, 0x1, URZ, 0xc0, !UPT ; /* 0x0000000104057892 */
/* 0x000fe2000f8ec03f */
/*03f0*/ BSSY B0, 0x4c0 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R2, R0, UR5, RZ ; /* 0x0000000500027c10 */
/* 0x001fc8000fffe0ff */
/*0410*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0430*/ @P0 BRA 0x4b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0450*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0460*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040602057981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea4000c1e1900 */
/*0480*/ ISETP.GT.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x004fda0003f04270 */
/*0490*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e8000c101906 */
/*04a0*/ @P0 STG.E [R2.64+0x4], R6 ; /* 0x0000040602000986 */
/* 0x0001e4000c101906 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04e0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*04f0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0500*/ @P0 BRA 0x3e0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <iostream>
template<typename T>
struct ShouldSwap
{
__host__ __device__
virtual bool operator() (const T left, const T right) const;
};
template <typename T>
__host__ __device__ __inline__
void swap(T* a, T* r);
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap);
int main(int argc, char** argv)
{
// vector size
const unsigned int size = 10;
// host vector
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
// device vector
int *d_v = 0;
cudaMalloc((void**)&d_v, size * sizeof(int));
cudaMemcpy(d_v, h_v, size * sizeof(int), cudaMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size / 2, 1, 1);
ShouldSwap<int> shouldSwap;
bubbleSort<int> <<<grdDim, blkDim >>>(d_v, size, shouldSwap);
cudaDeviceSynchronize();
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess) {
printf("CUDA error: %s\n", cudaGetErrorString(error));
// system("pause"); // when using VisStudio
exit(-1);
}
cudaMemcpy(h_v, d_v, size * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size - 1 ? " ," : "}");
}
std::cout << std::endl;
// system("pause"); // when using VisStudio
return 0;
}
template<typename T>
__host__ __device__
bool ShouldSwap<T>::operator() (const T left, const T right) const {
return left > right;
}
template<typename T>
__host__ __device__ __inline__
void swap (T* a, T* b) {
T tmp = *a;
*a = *b;
*b = tmp;
}
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap) {
const unsigned int tIdx = threadIdx.x;
for (unsigned int i = 0; i < n; i++) {
unsigned int offset = i % 2;
unsigned int indiceGauche = 2 * tIdx + offset;
unsigned int indiceDroite = indiceGauche + 1;
if (indiceDroite < n) {
if (shouldSwap(v[indiceGauche], v[indiceDroite])) {
swap<T>(&v[indiceGauche], &v[indiceDroite]);
}
}
__syncthreads();
}
} | .file "tmpxft_0001466e_00000000-6_generic-bubble-sort.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._ZNK10ShouldSwapIiEclEii,"axG",@progbits,_ZNK10ShouldSwapIiEclEii,comdat
.align 2
.weak _ZNK10ShouldSwapIiEclEii
.type _ZNK10ShouldSwapIiEclEii, @function
_ZNK10ShouldSwapIiEclEii:
.LFB4336:
.cfi_startproc
endbr64
cmpl %edx, %esi
setg %al
ret
.cfi_endproc
.LFE4336:
.size _ZNK10ShouldSwapIiEclEii, .-_ZNK10ShouldSwapIiEclEii
.section .text._Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,"axG",@progbits,_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,comdat
.weak _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.type _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, @function
_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E:
.LFB4007:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rdx, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L6
.L2:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L7
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L2
.L7:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4007:
.size _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, .-_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3682:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3682:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "{"
.LC1:
.string ""
.LC2:
.string "CUDA error: %s\n"
.LC3:
.string "}"
.LC4:
.string " ,"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $3, 48(%rsp)
movl $7, 52(%rsp)
movl $1, 56(%rsp)
movl $10, 60(%rsp)
movl $6, 64(%rsp)
movl $9, 68(%rsp)
movl $5, 72(%rsp)
movl $2, 76(%rsp)
movl $8, 80(%rsp)
movl $4, 84(%rsp)
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L11:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC0(%rip), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC4(%rip), %r15
.L16:
testl %ebx, %ebx
movq %r13, %rbp
cmovne %r14, %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 48(%rsp,%rbx,4), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
cmpl $8, %ebx
ja .L24
movl $2, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
jmp .L16
.L22:
leaq 16+_ZTV10ShouldSwapIiE(%rip), %rax
movq %rax, 16(%rsp)
leaq 16(%rsp), %rdx
movl $10, %esi
movq 8(%rsp), %rdi
call _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
jmp .L11
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L16
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3707:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZTS10ShouldSwapIiE
.section .rodata._ZTS10ShouldSwapIiE,"aG",@progbits,_ZTS10ShouldSwapIiE,comdat
.align 16
.type _ZTS10ShouldSwapIiE, @object
.size _ZTS10ShouldSwapIiE, 16
_ZTS10ShouldSwapIiE:
.string "10ShouldSwapIiE"
.weak _ZTI10ShouldSwapIiE
.section .data.rel.ro._ZTI10ShouldSwapIiE,"awG",@progbits,_ZTI10ShouldSwapIiE,comdat
.align 8
.type _ZTI10ShouldSwapIiE, @object
.size _ZTI10ShouldSwapIiE, 16
_ZTI10ShouldSwapIiE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS10ShouldSwapIiE
.weak _ZTV10ShouldSwapIiE
.section .data.rel.ro.local._ZTV10ShouldSwapIiE,"awG",@progbits,_ZTV10ShouldSwapIiE,comdat
.align 8
.type _ZTV10ShouldSwapIiE, @object
.size _ZTV10ShouldSwapIiE, 24
_ZTV10ShouldSwapIiE:
.quad 0
.quad _ZTI10ShouldSwapIiE
.quad _ZNK10ShouldSwapIiEclEii
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <iostream>
template<typename T>
struct ShouldSwap
{
__host__ __device__
virtual bool operator() (const T left, const T right) const;
};
template <typename T>
__host__ __device__ __inline__
void swap(T* a, T* r);
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap);
int main(int argc, char** argv)
{
// vector size
const unsigned int size = 10;
// host vector
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
// device vector
int *d_v = 0;
cudaMalloc((void**)&d_v, size * sizeof(int));
cudaMemcpy(d_v, h_v, size * sizeof(int), cudaMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size / 2, 1, 1);
ShouldSwap<int> shouldSwap;
bubbleSort<int> <<<grdDim, blkDim >>>(d_v, size, shouldSwap);
cudaDeviceSynchronize();
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess) {
printf("CUDA error: %s\n", cudaGetErrorString(error));
// system("pause"); // when using VisStudio
exit(-1);
}
cudaMemcpy(h_v, d_v, size * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size - 1 ? " ," : "}");
}
std::cout << std::endl;
// system("pause"); // when using VisStudio
return 0;
}
template<typename T>
__host__ __device__
bool ShouldSwap<T>::operator() (const T left, const T right) const {
return left > right;
}
template<typename T>
__host__ __device__ __inline__
void swap (T* a, T* b) {
T tmp = *a;
*a = *b;
*b = tmp;
}
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap) {
const unsigned int tIdx = threadIdx.x;
for (unsigned int i = 0; i < n; i++) {
unsigned int offset = i % 2;
unsigned int indiceGauche = 2 * tIdx + offset;
unsigned int indiceDroite = indiceGauche + 1;
if (indiceDroite < n) {
if (shouldSwap(v[indiceGauche], v[indiceDroite])) {
swap<T>(&v[indiceGauche], &v[indiceDroite]);
}
}
__syncthreads();
}
} | #include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
template<typename T>
struct ShouldSwap
{
__host__ __device__
virtual bool operator() (const T left, const T right) const;
};
template <typename T>
__host__ __device__ __inline__
void swap(T* a, T* r);
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap);
int main(int argc, char** argv)
{
// vector size
const unsigned int size = 10;
// host vector
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
// device vector
int *d_v = 0;
hipMalloc((void**)&d_v, size * sizeof(int));
hipMemcpy(d_v, h_v, size * sizeof(int), hipMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size / 2, 1, 1);
ShouldSwap<int> shouldSwap;
bubbleSort<int> <<<grdDim, blkDim >>>(d_v, size, shouldSwap);
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if (error != hipSuccess) {
printf("CUDA error: %s\n", hipGetErrorString(error));
// system("pause"); // when using VisStudio
exit(-1);
}
hipMemcpy(h_v, d_v, size * sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size - 1 ? " ," : "}");
}
std::cout << std::endl;
// system("pause"); // when using VisStudio
return 0;
}
template<typename T>
__host__ __device__
bool ShouldSwap<T>::operator() (const T left, const T right) const {
return left > right;
}
template<typename T>
__host__ __device__ __inline__
void swap (T* a, T* b) {
T tmp = *a;
*a = *b;
*b = tmp;
}
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap) {
const unsigned int tIdx = threadIdx.x;
for (unsigned int i = 0; i < n; i++) {
unsigned int offset = i % 2;
unsigned int indiceGauche = 2 * tIdx + offset;
unsigned int indiceDroite = indiceGauche + 1;
if (indiceDroite < n) {
if (shouldSwap(v[indiceGauche], v[indiceDroite])) {
swap<T>(&v[indiceGauche], &v[indiceDroite]);
}
}
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
template<typename T>
struct ShouldSwap
{
__host__ __device__
virtual bool operator() (const T left, const T right) const;
};
template <typename T>
__host__ __device__ __inline__
void swap(T* a, T* r);
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap);
int main(int argc, char** argv)
{
// vector size
const unsigned int size = 10;
// host vector
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
// device vector
int *d_v = 0;
hipMalloc((void**)&d_v, size * sizeof(int));
hipMemcpy(d_v, h_v, size * sizeof(int), hipMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size / 2, 1, 1);
ShouldSwap<int> shouldSwap;
bubbleSort<int> <<<grdDim, blkDim >>>(d_v, size, shouldSwap);
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if (error != hipSuccess) {
printf("CUDA error: %s\n", hipGetErrorString(error));
// system("pause"); // when using VisStudio
exit(-1);
}
hipMemcpy(h_v, d_v, size * sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size - 1 ? " ," : "}");
}
std::cout << std::endl;
// system("pause"); // when using VisStudio
return 0;
}
template<typename T>
__host__ __device__
bool ShouldSwap<T>::operator() (const T left, const T right) const {
return left > right;
}
template<typename T>
__host__ __device__ __inline__
void swap (T* a, T* b) {
T tmp = *a;
*a = *b;
*b = tmp;
}
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap) {
const unsigned int tIdx = threadIdx.x;
for (unsigned int i = 0; i < n; i++) {
unsigned int offset = i % 2;
unsigned int indiceGauche = 2 * tIdx + offset;
unsigned int indiceDroite = indiceGauche + 1;
if (indiceDroite < n) {
if (shouldSwap(v[indiceGauche], v[indiceDroite])) {
swap<T>(&v[indiceGauche], &v[indiceDroite]);
}
}
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,"axG",@progbits,_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,comdat
.protected _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.globl _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.p2align 8
.type _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,@function
_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E:
s_load_b32 s2, s[0:1], 0x8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s2, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_or_b32 v2, s3, 1, v0
s_mov_b32 s4, exec_lo
v_add_nc_u32_e32 v1, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v4, 2, v2
v_lshlrev_b32_e32 v3, 2, v1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v4, s[0:1]
global_load_b32 v2, v3, s[0:1]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v4, s5, s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, null, s1, 0, s5
v_add_co_u32 v6, s5, s0, v3
v_add_co_ci_u32_e64 v7, null, s1, 0, s5
s_clause 0x1
global_store_b32 v[4:5], v2, off
global_store_b32 v[6:7], v1, off
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,"axG",@progbits,_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,comdat
.Lfunc_end0:
.size _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, .Lfunc_end0-_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
template<typename T>
struct ShouldSwap
{
__host__ __device__
virtual bool operator() (const T left, const T right) const;
};
template <typename T>
__host__ __device__ __inline__
void swap(T* a, T* r);
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap);
int main(int argc, char** argv)
{
// vector size
const unsigned int size = 10;
// host vector
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
// device vector
int *d_v = 0;
hipMalloc((void**)&d_v, size * sizeof(int));
hipMemcpy(d_v, h_v, size * sizeof(int), hipMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size / 2, 1, 1);
ShouldSwap<int> shouldSwap;
bubbleSort<int> <<<grdDim, blkDim >>>(d_v, size, shouldSwap);
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if (error != hipSuccess) {
printf("CUDA error: %s\n", hipGetErrorString(error));
// system("pause"); // when using VisStudio
exit(-1);
}
hipMemcpy(h_v, d_v, size * sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size - 1 ? " ," : "}");
}
std::cout << std::endl;
// system("pause"); // when using VisStudio
return 0;
}
template<typename T>
__host__ __device__
bool ShouldSwap<T>::operator() (const T left, const T right) const {
return left > right;
}
template<typename T>
__host__ __device__ __inline__
void swap (T* a, T* b) {
T tmp = *a;
*a = *b;
*b = tmp;
}
template<typename T>
__global__
void bubbleSort(T* v, const unsigned int n, ShouldSwap<T> shouldSwap) {
const unsigned int tIdx = threadIdx.x;
for (unsigned int i = 0; i < n; i++) {
unsigned int offset = i % 2;
unsigned int indiceGauche = 2 * tIdx + offset;
unsigned int indiceDroite = indiceGauche + 1;
if (indiceDroite < n) {
if (shouldSwap(v[indiceGauche], v[indiceDroite])) {
swap<T>(&v[indiceGauche], &v[indiceDroite]);
}
}
__syncthreads();
}
} | .text
.file "generic-bubble-sort.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 3 # 0x3
.long 7 # 0x7
.long 1 # 0x1
.long 10 # 0xa
.LCPI0_1:
.long 6 # 0x6
.long 9 # 0x9
.long 5 # 0x5
.long 2 # 0x2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [3,7,1,10]
movaps %xmm0, 112(%rsp)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [6,9,5,2]
movaps %xmm0, 128(%rsp)
movabsq $17179869192, %rax # imm = 0x400000008
movq %rax, 144(%rsp)
movq $0, (%rsp)
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq (%rsp), %rdi
leaq 112(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq (%rsp), %rax
movq $_ZTV10ShouldSwapIiE+16, 16(%rsp)
movq %rax, 72(%rsp)
movl $10, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB0_10
# %bb.3:
movq (%rsp), %rsi
leaq 112(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
movl $.L.str.1, %r14d
movl $.L.str.4, %r15d
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
xorl %edx, %edx
testq %rbx, %rbx
sete %dl
movl $.L.str.2, %esi
cmoveq %r14, %rsi
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 112(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
xorl %edx, %edx
cmpq $9, %rbx
movl $.L.str.3, %esi
cmoveq %r15, %rsi
setne %dl
incq %rdx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $10, %rbx
jne .LBB0_4
# %bb.5:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_8
# %bb.7:
movzbl 67(%rbx), %eax
jmp .LBB0_9
.LBB0_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_10:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB0_11:
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E,"axG",@progbits,_Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E,comdat
.weak _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E # -- Begin function _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.p2align 4, 0x90
.type _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E,@function
_Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E: # @_Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rdx, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E, .Lfunc_end1-_Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.cfi_endproc
# -- End function
.section .text._ZNK10ShouldSwapIiEclEii,"axG",@progbits,_ZNK10ShouldSwapIiEclEii,comdat
.weak _ZNK10ShouldSwapIiEclEii # -- Begin function _ZNK10ShouldSwapIiEclEii
.p2align 4, 0x90
.type _ZNK10ShouldSwapIiEclEii,@function
_ZNK10ShouldSwapIiEclEii: # @_ZNK10ShouldSwapIiEclEii
.cfi_startproc
# %bb.0:
cmpl %edx, %esi
setg %al
retq
.Lfunc_end2:
.size _ZNK10ShouldSwapIiEclEii, .Lfunc_end2-_ZNK10ShouldSwapIiEclEii
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,@object # @_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.section .rodata,"a",@progbits
.weak _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.p2align 3, 0x0
_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E:
.quad _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.size _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "{"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.zero 1
.size .L.str.2, 1
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ,"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "}"
.size .L.str.4, 2
.type _ZTV10ShouldSwapIiE,@object # @_ZTV10ShouldSwapIiE
.section .rodata._ZTV10ShouldSwapIiE,"aG",@progbits,_ZTV10ShouldSwapIiE,comdat
.weak _ZTV10ShouldSwapIiE
.p2align 3, 0x0
_ZTV10ShouldSwapIiE:
.quad 0
.quad _ZTI10ShouldSwapIiE
.quad _ZNK10ShouldSwapIiEclEii
.size _ZTV10ShouldSwapIiE, 24
.type _ZTS10ShouldSwapIiE,@object # @_ZTS10ShouldSwapIiE
.section .rodata._ZTS10ShouldSwapIiE,"aG",@progbits,_ZTS10ShouldSwapIiE,comdat
.weak _ZTS10ShouldSwapIiE
_ZTS10ShouldSwapIiE:
.asciz "10ShouldSwapIiE"
.size _ZTS10ShouldSwapIiE, 16
.type _ZTI10ShouldSwapIiE,@object # @_ZTI10ShouldSwapIiE
.section .rodata._ZTI10ShouldSwapIiE,"aG",@progbits,_ZTI10ShouldSwapIiE,comdat
.weak _ZTI10ShouldSwapIiE
.p2align 3, 0x0
_ZTI10ShouldSwapIiE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS10ShouldSwapIiE
.size _ZTI10ShouldSwapIiE, 16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.addrsig_sym _ZSt4cout
.addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE
.addrsig_sym _ZTS10ShouldSwapIiE
.addrsig_sym _ZTI10ShouldSwapIiE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fda0003f05270 */
/*0020*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0080*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x001fd800078e00ff */
/*00b0*/ @!P0 BRA 0x3c0 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R8, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004087a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.WIDE.U32 R2, R0.reuse, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe200078e0003 */
/*0120*/ IADD3 R7, R0, 0x2, RZ ; /* 0x0000000200077810 */
/* 0x000fd20007ffe0ff */
/*0130*/ BSSY B0, 0x1c0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0140*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f26070 */
/*0150*/ @P0 BRA 0x1b0 ; /* 0x0000005000000947 */
/* 0x001fee0003800000 */
/*0160*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea4000c1e1900 */
/*0180*/ ISETP.GT.AND P2, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fda0003f44270 */
/*0190*/ @P2 STG.E [R2.64], R6 ; /* 0x0000000602002986 */
/* 0x0001e8000c101906 */
/*01a0*/ @P2 STG.E [R2.64+0x4], R5 ; /* 0x0000040502002986 */
/* 0x0001e4000c101906 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ BSSY B0, 0x250 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*01e0*/ @P1 BRA 0x240 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080602057981 */
/* 0x001ea8000c1e1900 */
/*0200*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea4000c1e1900 */
/*0210*/ ISETP.GT.AND P2, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x004fda0003f44270 */
/*0220*/ @P2 STG.E [R2.64+0x4], R5 ; /* 0x0000040502002986 */
/* 0x0001e8000c101906 */
/*0230*/ @P2 STG.E [R2.64+0x8], R6 ; /* 0x0000080602002986 */
/* 0x0001e4000c101906 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ BSSY B0, 0x2e0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0270*/ @P0 BRA 0x2d0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0280*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x001ea8000c1e1900 */
/*0290*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ ISETP.GT.AND P2, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fda0003f44270 */
/*02b0*/ @P2 STG.E [R2.64], R6 ; /* 0x0000000602002986 */
/* 0x0001e8000c101906 */
/*02c0*/ @P2 STG.E [R2.64+0x4], R5 ; /* 0x0000040502002986 */
/* 0x0001e4000c101906 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0300*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f45270 */
/*0310*/ BSSY B0, 0x390 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0320*/ @P1 BRA 0x380 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0330*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080602057981 */
/* 0x001ea8000c1e1900 */
/*0340*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea4000c1e1900 */
/*0350*/ ISETP.GT.AND P1, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x004fda0003f24270 */
/*0360*/ @P1 STG.E [R2.64+0x4], R5 ; /* 0x0000040502001986 */
/* 0x0001e8000c101906 */
/*0370*/ @P1 STG.E [R2.64+0x8], R6 ; /* 0x0000080602001986 */
/* 0x0001e4000c101906 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fca000fffe03f */
/*03b0*/ @P2 BRA 0x130 ; /* 0xfffffd7000002947 */
/* 0x000fea000383ffff */
/*03c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*03d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03e0*/ ULOP3.LUT UR5, UR4, 0x1, URZ, 0xc0, !UPT ; /* 0x0000000104057892 */
/* 0x000fe2000f8ec03f */
/*03f0*/ BSSY B0, 0x4c0 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R2, R0, UR5, RZ ; /* 0x0000000500027c10 */
/* 0x001fc8000fffe0ff */
/*0410*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f06070 */
/*0430*/ @P0 BRA 0x4b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0450*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0460*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040602057981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea4000c1e1900 */
/*0480*/ ISETP.GT.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x004fda0003f04270 */
/*0490*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e8000c101906 */
/*04a0*/ @P0 STG.E [R2.64+0x4], R6 ; /* 0x0000040602000986 */
/* 0x0001e4000c101906 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04e0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*04f0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0500*/ @P0 BRA 0x3e0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,"axG",@progbits,_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,comdat
.protected _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.globl _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.p2align 8
.type _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,@function
_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E:
s_load_b32 s2, s[0:1], 0x8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s2, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_or_b32 v2, s3, 1, v0
s_mov_b32 s4, exec_lo
v_add_nc_u32_e32 v1, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v4, 2, v2
v_lshlrev_b32_e32 v3, 2, v1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v4, s[0:1]
global_load_b32 v2, v3, s[0:1]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v4, s5, s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, null, s1, 0, s5
v_add_co_u32 v6, s5, s0, v3
v_add_co_ci_u32_e64 v7, null, s1, 0, s5
s_clause 0x1
global_store_b32 v[4:5], v2, off
global_store_b32 v[6:7], v1, off
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,"axG",@progbits,_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,comdat
.Lfunc_end0:
.size _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, .Lfunc_end0-_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001466e_00000000-6_generic-bubble-sort.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._ZNK10ShouldSwapIiEclEii,"axG",@progbits,_ZNK10ShouldSwapIiEclEii,comdat
.align 2
.weak _ZNK10ShouldSwapIiEclEii
.type _ZNK10ShouldSwapIiEclEii, @function
_ZNK10ShouldSwapIiEclEii:
.LFB4336:
.cfi_startproc
endbr64
cmpl %edx, %esi
setg %al
ret
.cfi_endproc
.LFE4336:
.size _ZNK10ShouldSwapIiEclEii, .-_ZNK10ShouldSwapIiEclEii
.section .text._Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,"axG",@progbits,_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,comdat
.weak _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.type _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, @function
_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E:
.LFB4007:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rdx, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L6
.L2:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L7
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L2
.L7:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4007:
.size _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, .-_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3682:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3682:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "{"
.LC1:
.string ""
.LC2:
.string "CUDA error: %s\n"
.LC3:
.string "}"
.LC4:
.string " ,"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $3, 48(%rsp)
movl $7, 52(%rsp)
movl $1, 56(%rsp)
movl $10, 60(%rsp)
movl $6, 64(%rsp)
movl $9, 68(%rsp)
movl $5, 72(%rsp)
movl $2, 76(%rsp)
movl $8, 80(%rsp)
movl $4, 84(%rsp)
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L11:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC0(%rip), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC4(%rip), %r15
.L16:
testl %ebx, %ebx
movq %r13, %rbp
cmovne %r14, %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 48(%rsp,%rbx,4), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
cmpl $8, %ebx
ja .L24
movl $2, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
jmp .L16
.L22:
leaq 16+_ZTV10ShouldSwapIiE(%rip), %rax
movq %rax, 16(%rsp)
leaq 16(%rsp), %rdx
movl $10, %esi
movq 8(%rsp), %rdi
call _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
jmp .L11
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L16
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3707:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZTS10ShouldSwapIiE
.section .rodata._ZTS10ShouldSwapIiE,"aG",@progbits,_ZTS10ShouldSwapIiE,comdat
.align 16
.type _ZTS10ShouldSwapIiE, @object
.size _ZTS10ShouldSwapIiE, 16
_ZTS10ShouldSwapIiE:
.string "10ShouldSwapIiE"
.weak _ZTI10ShouldSwapIiE
.section .data.rel.ro._ZTI10ShouldSwapIiE,"awG",@progbits,_ZTI10ShouldSwapIiE,comdat
.align 8
.type _ZTI10ShouldSwapIiE, @object
.size _ZTI10ShouldSwapIiE, 16
_ZTI10ShouldSwapIiE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS10ShouldSwapIiE
.weak _ZTV10ShouldSwapIiE
.section .data.rel.ro.local._ZTV10ShouldSwapIiE,"awG",@progbits,_ZTV10ShouldSwapIiE,comdat
.align 8
.type _ZTV10ShouldSwapIiE, @object
.size _ZTV10ShouldSwapIiE, 24
_ZTV10ShouldSwapIiE:
.quad 0
.quad _ZTI10ShouldSwapIiE
.quad _ZNK10ShouldSwapIiEclEii
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "generic-bubble-sort.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 3 # 0x3
.long 7 # 0x7
.long 1 # 0x1
.long 10 # 0xa
.LCPI0_1:
.long 6 # 0x6
.long 9 # 0x9
.long 5 # 0x5
.long 2 # 0x2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [3,7,1,10]
movaps %xmm0, 112(%rsp)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [6,9,5,2]
movaps %xmm0, 128(%rsp)
movabsq $17179869192, %rax # imm = 0x400000008
movq %rax, 144(%rsp)
movq $0, (%rsp)
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq (%rsp), %rdi
leaq 112(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq (%rsp), %rax
movq $_ZTV10ShouldSwapIiE+16, 16(%rsp)
movq %rax, 72(%rsp)
movl $10, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB0_10
# %bb.3:
movq (%rsp), %rsi
leaq 112(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
movl $.L.str.1, %r14d
movl $.L.str.4, %r15d
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
xorl %edx, %edx
testq %rbx, %rbx
sete %dl
movl $.L.str.2, %esi
cmoveq %r14, %rsi
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 112(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
xorl %edx, %edx
cmpq $9, %rbx
movl $.L.str.3, %esi
cmoveq %r15, %rsi
setne %dl
incq %rdx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $10, %rbx
jne .LBB0_4
# %bb.5:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_8
# %bb.7:
movzbl 67(%rbx), %eax
jmp .LBB0_9
.LBB0_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_10:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB0_11:
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E,"axG",@progbits,_Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E,comdat
.weak _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E # -- Begin function _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.p2align 4, 0x90
.type _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E,@function
_Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E: # @_Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rdx, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E, .Lfunc_end1-_Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.cfi_endproc
# -- End function
.section .text._ZNK10ShouldSwapIiEclEii,"axG",@progbits,_ZNK10ShouldSwapIiEclEii,comdat
.weak _ZNK10ShouldSwapIiEclEii # -- Begin function _ZNK10ShouldSwapIiEclEii
.p2align 4, 0x90
.type _ZNK10ShouldSwapIiEclEii,@function
_ZNK10ShouldSwapIiEclEii: # @_ZNK10ShouldSwapIiEclEii
.cfi_startproc
# %bb.0:
cmpl %edx, %esi
setg %al
retq
.Lfunc_end2:
.size _ZNK10ShouldSwapIiEclEii, .Lfunc_end2-_ZNK10ShouldSwapIiEclEii
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E,@object # @_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.section .rodata,"a",@progbits
.weak _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.p2align 3, 0x0
_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E:
.quad _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.size _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "{"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.zero 1
.size .L.str.2, 1
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ,"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "}"
.size .L.str.4, 2
.type _ZTV10ShouldSwapIiE,@object # @_ZTV10ShouldSwapIiE
.section .rodata._ZTV10ShouldSwapIiE,"aG",@progbits,_ZTV10ShouldSwapIiE,comdat
.weak _ZTV10ShouldSwapIiE
.p2align 3, 0x0
_ZTV10ShouldSwapIiE:
.quad 0
.quad _ZTI10ShouldSwapIiE
.quad _ZNK10ShouldSwapIiEclEii
.size _ZTV10ShouldSwapIiE, 24
.type _ZTS10ShouldSwapIiE,@object # @_ZTS10ShouldSwapIiE
.section .rodata._ZTS10ShouldSwapIiE,"aG",@progbits,_ZTS10ShouldSwapIiE,comdat
.weak _ZTS10ShouldSwapIiE
_ZTS10ShouldSwapIiE:
.asciz "10ShouldSwapIiE"
.size _ZTS10ShouldSwapIiE, 16
.type _ZTI10ShouldSwapIiE,@object # @_ZTI10ShouldSwapIiE
.section .rodata._ZTI10ShouldSwapIiE,"aG",@progbits,_ZTI10ShouldSwapIiE,comdat
.weak _ZTI10ShouldSwapIiE
.p2align 3, 0x0
_ZTI10ShouldSwapIiE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS10ShouldSwapIiE
.size _ZTI10ShouldSwapIiE, 16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bubbleSortIiEvPT_j10ShouldSwapIS0_E
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bubbleSortIiEvPT_j10ShouldSwapIS0_E
.addrsig_sym _ZSt4cout
.addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE
.addrsig_sym _ZTS10ShouldSwapIiE
.addrsig_sym _ZTI10ShouldSwapIiE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
int main(void) {
// int* a = (int *)malloc(sizeof(int));
// *a = 4;
// printf("%p\n",a);
// printf("%d\n",*a);
int a = 5;
int* d_a = NULL;
d_a = &a;
printf("variable a = %d\n", a);
printf("contenido variable d_a = %d\n", *d_a);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
int main(void) {
// int* a = (int *)malloc(sizeof(int));
// *a = 4;
// printf("%p\n",a);
// printf("%d\n",*a);
int a = 5;
int* d_a = NULL;
d_a = &a;
printf("variable a = %d\n", a);
printf("contenido variable d_a = %d\n", *d_a);
return 0;
} | .file "tmpxft_0001b77e_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "variable a = %d\n"
.LC1:
.string "contenido variable d_a = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $5, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
int main(void) {
// int* a = (int *)malloc(sizeof(int));
// *a = 4;
// printf("%p\n",a);
// printf("%d\n",*a);
int a = 5;
int* d_a = NULL;
d_a = &a;
printf("variable a = %d\n", a);
printf("contenido variable d_a = %d\n", *d_a);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
int main(void) {
// int* a = (int *)malloc(sizeof(int));
// *a = 4;
// printf("%p\n",a);
// printf("%d\n",*a);
int a = 5;
int* d_a = NULL;
d_a = &a;
printf("variable a = %d\n", a);
printf("contenido variable d_a = %d\n", *d_a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
int main(void) {
// int* a = (int *)malloc(sizeof(int));
// *a = 4;
// printf("%p\n",a);
// printf("%d\n",*a);
int a = 5;
int* d_a = NULL;
d_a = &a;
printf("variable a = %d\n", a);
printf("contenido variable d_a = %d\n", *d_a);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
int main(void) {
// int* a = (int *)malloc(sizeof(int));
// *a = 4;
// printf("%p\n",a);
// printf("%d\n",*a);
int a = 5;
int* d_a = NULL;
d_a = &a;
printf("variable a = %d\n", a);
printf("contenido variable d_a = %d\n", *d_a);
return 0;
} | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl $5, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $5, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "variable a = %d\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "contenido variable d_a = %d\n"
.size .L.str.1, 29
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001b77e_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "variable a = %d\n"
.LC1:
.string "contenido variable d_a = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $5, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl $5, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $5, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "variable a = %d\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "contenido variable d_a = %d\n"
.size .L.str.1, 29
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //============================================================================
// Name : MF6.cpp
// Author : Sohrab
// Version : 1
// Copyright : Hi!
// Description : Matched Filter in C++, Ansi-style
//============================================================================
#include <iostream>
#include <string>
#include <cmath>
#include <math.h>
#include <ctime>
#include <complex>
#include <vector>
#include <string>
#include "stdio.h"
#include "stdlib.h"
#include "time.h"
#include <thrust/complex.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
// references
#define date_ref "1015"
#define obj_ref "1"
#define run_ref 2
// 0: down sampling, 1: averaging, 2: nothing
#define average 2
//internal distance
#define int_dst 2.615
// TX relative position to TX's starting point
#define Tx_pos_x 0.41
#define Tx_pos_y -0.028
#define Tx_pos_z -0.012
//starting point of using samples
#define N_spl_fr 1000
#define N_lfreq_spl 0
#define N_hfreq_spl 0
#define N_mfreq_spl (N_spl_fr/2)-N_lfreq_spl-N_hfreq_spl
#define N_mfreq_spl_slow 2*((N_spl_fr/2)-N_lfreq_spl-N_hfreq_spl)
// Number of frames for each axis
#define N_x_stg 20 //1667
#define N_z_stg 20
//constants
#define Ts 6e-3
#define Rs 5e5
#define lambda 4.983873e-3
//step size between each two frames considered
#define dlx 0.005 * 0.006
#define dlz lambda/2
#define linxmax -dlx/2-(N_x_stg-1)*dlx
#define linzmax -dlz/2-(N_z_stg-1)*dlz
// environment dimensions
#define xmin -5
#define xmax 5
#define ymin 0
#define ymax 10
#define zmin -1.5
#define zmax 1.5
//resolution
#define res 0.07
//scientific values for some constants
#define sci_fac 1e8
#define c_sci 2.9979
#define fc_sci 609
#define As1_sci 1.5001e4
#define As2_sci 7.5005e3
#define file_size 100020000
#define size1 3000
#define BLOCK_WIDTH 8
#define Beat_I(uu, vv, nn) Beat_I[uu*N_z_stg*size1 + vv*size1 + nn]
#define Beat_R(uu, vv, nn) Beat_R[uu*N_z_stg*size1 + vv*size1 + nn]
#define cell_MF(xx, yy, zz) cell_MF[xx*Ny*Nz + yy*Nz + zz]
#define deviceCellMF(xx, yy, zz) deviceCellMF[xx*Ny*Nz + yy*Nz + zz]
using namespace std;
/****************** FUNCTIONS ******************/
struct indices {
int kx;
int ky;
int kz;
};
indices idxfinder(int n1, int n2, int n3, int k) {
k = k % (n1 * n2 * n3);
indices I;
I.kx = k % n1;
I.ky = ((int) floor(k / n1)) % n2;
I.kz = ((int) floor(k / (n1 * n2))) % n3;
return I;
}
/****************************************************/
/************* KERNEL CALL *************************/
__global__ void matchedFilterKernel(float* Beat_R, float* Beat_I, thrust::complex<float>* cell_MF, int Nx, int Ny, int Nz) {
#define MF_x_axis(xx) (xx*res + xmin)
#define MF_y_axis(yy) (yy*res + ymin)
#define MF_z_axis(zz) (zz*res + zmin)
#define u_axis(uu) (-dlx/2 - uu*dlx)
#define v_axis(vv) (-dlz/2 - vv*dlz)
const float pi = acosf(-1);
const thrust::complex<double> i(0, 1);
const thrust::complex<float> i_float(0, 1);
int xx, yy, zz;
xx = blockIdx.x * blockDim.x + threadIdx.x;
yy = blockIdx.y * blockDim.y + threadIdx.y;
zz = blockIdx.z * blockDim.z + threadIdx.z;
if(xx < Nx && yy < Ny && zz < Nz) {
float cell_z = MF_z_axis(zz);
float cell_y = MF_y_axis(yy);
float cell_x = MF_x_axis(xx);
thrust::complex<float> cell_sum = 0;
// for(int nn = 0; nn < size1; nn++) // 3000
// Beat[nn] = Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn);
// __shared__ complex<float> Beat[size1]
float cell_dist_t = sqrtf(
(cell_x - Tx_pos_x) * (cell_x - Tx_pos_x)
+ (cell_y - Tx_pos_y) * (cell_y - Tx_pos_y)
+ (cell_z - Tx_pos_z) * (cell_z - Tx_pos_z));
for (int uu = 0; uu < N_x_stg; uu++) { // N_x_stg
float x_diff = (cell_x - u_axis(uu)) * (cell_x - u_axis(uu));
for (int vv = 0; vv < N_z_stg; vv++) { // 2d receiver 1667*20
float temp_tau = (cell_dist_t + int_dst * 2 + sqrtf( x_diff +
(cell_z - v_axis(vv)) * (cell_z - v_axis(vv)) + cell_y * cell_y) ) / c_sci;
thrust::complex<float> temp_sig = exp(-i_float * (float) fmod((float)2.0 * pi * fc_sci * temp_tau, 2*pi) );
thrust::complex<float> Beat[size1];
thrust::complex<float> cell_sig_fst_temp[N_mfreq_spl];
thrust::complex<float> cell_sig_slow_temp[N_mfreq_spl_slow];
for(int nn = 0; nn < size1; nn++) // 3000
Beat[nn] = Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn);
for (int nn = 0; nn < N_mfreq_spl; nn++) { // for each fixed receiver and object location, 3000 samples
cell_sig_fst_temp[nn] = temp_sig * exp(-i_float * (float) fmod((float)(2.0 * pi *
As1_sci * (N_lfreq_spl / Rs + nn / Rs) * temp_tau), 2*pi));
cell_sum += cell_sig_fst_temp[nn] * (Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn)); //Beat[nn];
}
for (int nn = N_mfreq_spl; nn < 2*N_mfreq_spl; nn++) {
cell_sum += cell_sig_fst_temp[2*N_mfreq_spl-1-nn] * Beat[nn];
}
for (int nn = 0; nn < N_mfreq_spl_slow; nn++) {
cell_sig_slow_temp[nn] = temp_sig * exp(-i_float * (float) fmod((float)(2.0 * pi
* As2_sci * (N_lfreq_spl * 2 / Rs + nn / Rs) * temp_tau), 2*pi) );
cell_sum += cell_sig_slow_temp[nn] * Beat[nn+2*N_mfreq_spl];
}
for (int nn = N_mfreq_spl_slow; nn < 2* N_mfreq_spl_slow; nn++) {
cell_sum += cell_sig_slow_temp[2*N_mfreq_spl_slow-1-nn] * Beat[nn+2*N_mfreq_spl];
}
}
}
cell_MF(xx, yy, zz) = cell_sum;
}
#undef MF_x_axis
#undef MF_y_axis
#undef MF_z_axis
#undef u_axis
#undef v_axis
}
/**************************************************/
int
main(void)
{
cudaError_t err = cudaSuccess;
/************* LARGE ARRAY DECLRATATIONS AND NX, NY, NZ************/
int Nx = 143; // (int) floor((xmax-xmin)/res)+1; //143
int Ny = 143; //(int) floor((ymax-ymin)/res)+1; //143
int Nz = 43; //(int) floor((zmax-zmin)/res)+1; //43
// complex<float> cell_sig_fst[N_x_stg][N_z_stg][N_mfreq_spl];
// complex<float> cell_sig_slow[N_x_stg][N_z_stg][N_mfreq_spl_slow];
// Allocate host memory
float* Beat_R = (float *)malloc(N_x_stg * N_z_stg * size1 * sizeof(float)); //[N_x_stg][N_z_stg][size1] = {};
float* Beat_I = (float *)malloc(N_x_stg * N_z_stg * size1 * sizeof(float)); //[N_x_stg][N_z_stg][size1] = {};
thrust::complex<float>* cell_MF = (thrust::complex<float>*)malloc(Nx * Ny * Nz * sizeof(thrust::complex<float>)); //[Nx][Ny][Nz] 143 * 143 *43
// Verify that allocations succeeded
if (Beat_R == NULL || Beat_I == NULL || cell_MF == NULL )
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
/**************************************************/
clock_t begin = clock();
clock_t end;
// srand (time(NULL));
// for (int ii = 0; ii < N_z_stg; ii++)
// for (int jj = 0; jj < N_x_stg; jj++)
// for (int kk = 0; kk < size1; kk++) {
// Beat_R(jj, ii, kk) = (rand()%10 + 1)/10;
// Beat_I(jj, ii, kk) = (rand()%10 + 1)/10;
// }
/*********** READ THE .BIN FILES ************/
FILE *fp = fopen("/home/synrg-gpu1/Desktop/MF6/testReal.bin","rb");
for (int ii = 0; ii < N_z_stg; ii++){
for (int jj = 0; jj < N_x_stg; jj++) {
float b[size1];
fseek(fp, (ii*N_x_stg + jj)*size1*4, SEEK_SET);
fread(b, sizeof *b, size1, fp);
for(int kk = 0; kk < size1; kk++) {
Beat_R(jj, ii, kk) = 1;
//if (ii == 0 && jj == 1 && kk < 500) cout << b[kk] << endl;
}
}
}
fclose(fp);
cout << "Successfully read the file in " << (double) (clock() - begin) / CLOCKS_PER_SEC << " seconds!" << endl;
FILE *fp2 = fopen("/home/synrg-gpu1/Desktop/MF6/testImag.bin","rb");
for (int ii = 0; ii < N_z_stg; ii++){
for (int jj = 0; jj < N_x_stg; jj++) {
float b[size1];
fseek(fp2, (ii*N_x_stg + jj)*size1*4, SEEK_SET);
fread(b, sizeof *b, size1, fp2);
for(int kk = 0; kk < size1; kk++) {
Beat_I(jj, ii, kk) = 0;
}
}
}
fclose(fp2);
cout << "Successfully read the files in " << (double) (clock() - begin) / CLOCKS_PER_SEC << " seconds!" << endl;
// cout << Beat_I(149, 14, 149)<< endl << endl;
/******************** END OF READ FILE *********************/
//some constants
const float pi = acos(-1);
const thrust::complex<double> i(0, 1);
const thrust::complex<float> i_float(0, 1);
for (int i = 0; i < 1; i++){
for (int j = 0; j < 1; j++){
for (int k = 0; k < 10; k++) {
cout << cell_MF(k, j, i) << " ";
}
std::endl( std::cout );
}
std::endl( std::cout );
}
float* deviceBeatI;
float* deviceBeatR;
thrust::complex<float>* deviceCellMF;
clock_t begin_mem = clock();
// Allocate GPU memory
err = cudaMalloc((void **) &deviceBeatR , N_z_stg * N_x_stg * size1 * sizeof(float));
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate deviceBeatR (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &deviceBeatI , N_z_stg * N_x_stg * size1 * sizeof(float));
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate deviceBeatI (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &deviceCellMF , Nx * Ny * Nz * sizeof(thrust::complex<float>));
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate deviceCellMF (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(deviceBeatR, Beat_R, N_z_stg * N_x_stg * size1 * sizeof(float), cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy deviceBeatR from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(deviceBeatI, Beat_I, N_z_stg * N_x_stg * size1 * sizeof(float), cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy deviceBeatI from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cout << "hi!" << endl;
dim3 DimGrid(ceil(Nx * 1.0 / BLOCK_WIDTH), ceil(Ny * 1.0 / BLOCK_WIDTH), ceil(Nz * 1.0 /BLOCK_WIDTH));
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH, BLOCK_WIDTH);
cout << "Allocating & copying memory DONE! Time taken:" << (double) (clock() - begin_mem) / CLOCKS_PER_SEC;
matchedFilterKernel<<<DimGrid, DimBlock>>>(deviceBeatR, deviceBeatI, deviceCellMF, Nx, Ny, Nz);
cudaDeviceSynchronize();
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch matchedFilterKernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
begin_mem = clock();
printf("Copy output data from the CUDA device to the host memory\n");
err = cudaMemcpy(cell_MF, deviceCellMF, Nx * Ny * Nz * sizeof(thrust::complex<float>), cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy deviceCellMF from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cout << "Copying memory back DONE! Time taken:" << (double) (clock() - begin_mem) / CLOCKS_PER_SEC;
cout << "Hi! \n";
cout << Nx << endl;
cout << Ny << endl;
cout << Nz << endl;
cout << N_x_stg << endl;
cout << N_z_stg << endl;
cout << N_mfreq_spl_slow << endl;
end = clock();
cout << "DONE! Time taken:" << (double) (end - begin) / CLOCKS_PER_SEC;
for (int i = 0; i < 1; i++){
for (int j = 0; j < 5; j++){
for (int k = 0; k < 5; k++) {
cout << cell_MF(k, j, i) << " ";
}
std::endl( std::cout );
}
std::endl( std::cout );
}
cudaFree(deviceBeatR);
cudaFree(deviceBeatI);
cudaFree(deviceCellMF);
free(Beat_R);
free(Beat_I);
free(cell_MF);
return 0;
} | .file "tmpxft_000b8950_00000000-6_MF6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6342:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6342:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9idxfinderiiii
.type _Z9idxfinderiiii, @function
_Z9idxfinderiiii:
.LFB6337:
.cfi_startproc
endbr64
movl %edx, %r9d
movl %ecx, %eax
movl %edi, %r10d
imull %esi, %r10d
movl %r10d, %edx
imull %r9d, %edx
movl %edx, %ecx
cltd
idivl %ecx
movl %edx, %r8d
movl %edx, %eax
cltd
idivl %edi
movl %edx, -20(%rsp)
cltd
idivl %esi
movl %edx, -16(%rsp)
movl %r8d, %eax
cltd
idivl %r10d
cltd
idivl %r9d
movq -20(%rsp), %rax
ret
.cfi_endproc
.LFE6337:
.size _Z9idxfinderiiii, .-_Z9idxfinderiiii
.globl _Z87__device_stub__Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiiiPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii
.type _Z87__device_stub__Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiiiPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii, @function
_Z87__device_stub__Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiiiPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii:
.LFB6364:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6364:
.size _Z87__device_stub__Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiiiPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii, .-_Z87__device_stub__Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiiiPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii
.globl _Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii
.type _Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii, @function
_Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii:
.LFB6365:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z87__device_stub__Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiiiPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6365:
.size _Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii, .-_Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii"
.align 8
.LC1:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std3__45__cpo5beginE"
.align 8
.LC2:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std3__45__cpo3endE"
.align 8
.LC3:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std3__45__cpo6cbeginE"
.align 8
.LC4:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std3__45__cpo4cendE"
.align 8
.LC5:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std3__438_GLOBAL__N__38402407_6_MF6_cu_6c3e07696ignoreE"
.align 8
.LC6:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std3__419piecewise_constructE"
.align 8
.LC7:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std3__48in_placeE"
.align 8
.LC8:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC9:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std6ranges3__45__cpo9iter_moveE"
.align 8
.LC10:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07694cuda3std6ranges3__45__cpo7advanceE"
.align 8
.LC11:
.string "_ZN36_INTERNAL_38402407_6_MF6_cu_6c3e07696thrust20THRUST_200700_800_NS6system6detail10sequential3seqE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6367:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo3endE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__438_GLOBAL__N__38402407_6_MF6_cu_6c3e07696ignoreE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__48in_placeE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6367:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN6thrust20THRUST_200700_800_NSlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES8_RKNS0_7complexIT_EE,"axG",@progbits,_ZN6thrust20THRUST_200700_800_NSlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES8_RKNS0_7complexIT_EE,comdat
.weak _ZN6thrust20THRUST_200700_800_NSlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES8_RKNS0_7complexIT_EE
.type _ZN6thrust20THRUST_200700_800_NSlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES8_RKNS0_7complexIT_EE, @function
_ZN6thrust20THRUST_200700_800_NSlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES8_RKNS0_7complexIT_EE:
.LFB6705:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movb $40, 7(%rsp)
movq (%rdi), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L15
leaq 7(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movb $44, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L17
leaq 7(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L18:
pxor %xmm0, %xmm0
cvtss2sd 4(%r12), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $41, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L19
leaq 7(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L20:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L23
movq %rbp, %rax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $40, %esi
call _ZNSo3putEc@PLT
movq %rbp, %rdi
jmp .L16
.L17:
movl $44, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L18
.L19:
movl $41, %esi
call _ZNSo3putEc@PLT
jmp .L20
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6705:
.size _ZN6thrust20THRUST_200700_800_NSlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES8_RKNS0_7complexIT_EE, .-_ZN6thrust20THRUST_200700_800_NSlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES8_RKNS0_7complexIT_EE
.section .rodata.str1.8
.align 8
.LC12:
.string "Failed to allocate host vectors!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC13:
.string "rb"
.section .rodata.str1.8
.align 8
.LC14:
.string "/home/synrg-gpu1/Desktop/MF6/testReal.bin"
.align 8
.LC16:
.string "Successfully read the file in "
.section .rodata.str1.1
.LC18:
.string " seconds!"
.section .rodata.str1.8
.align 8
.LC19:
.string "/home/synrg-gpu1/Desktop/MF6/testImag.bin"
.align 8
.LC21:
.string "Successfully read the files in "
.section .rodata.str1.1
.LC22:
.string " "
.section .rodata.str1.8
.align 8
.LC23:
.string "Failed to allocate deviceBeatR (error code %s)!\n"
.align 8
.LC24:
.string "Failed to allocate deviceBeatI (error code %s)!\n"
.align 8
.LC25:
.string "Failed to allocate deviceCellMF (error code %s)!\n"
.align 8
.LC26:
.string "Copy input data from the host memory to the CUDA device\n"
.align 8
.LC27:
.string "Failed to copy deviceBeatR from host to device (error code %s)!\n"
.align 8
.LC28:
.string "Failed to copy deviceBeatI from host to device (error code %s)!\n"
.section .rodata.str1.1
.LC29:
.string "hi!"
.section .rodata.str1.8
.align 8
.LC30:
.string "Allocating & copying memory DONE! Time taken:"
.align 8
.LC31:
.string "Failed to launch matchedFilterKernel (error code %s)!\n"
.align 8
.LC32:
.string "Copy output data from the CUDA device to the host memory\n"
.align 8
.LC33:
.string "Failed to copy deviceCellMF from device to host (error code %s)!\n"
.align 8
.LC34:
.string "Copying memory back DONE! Time taken:"
.section .rodata.str1.1
.LC35:
.string "Hi! \n"
.LC36:
.string "DONE! Time taken:"
.text
.globl main
.type main, @function
main:
.LFB6338:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $4096, %rsp
.cfi_def_cfa_offset 4152
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8248
orq $0, (%rsp)
subq $3928, %rsp
.cfi_def_cfa_offset 12176
movq %fs:40, %rax
movq %rax, 12104(%rsp)
xorl %eax, %eax
movl $4800000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4800000, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, 8(%rsp)
movl $7034456, %edi
call malloc@PLT
movq %rax, %rcx
movq %rax, (%rsp)
testq %rbx, %rbx
sete %al
testq %r14, %r14
sete %dl
orb %dl, %al
jne .L52
testq %rcx, %rcx
je .L52
call clock@PLT
movq %rax, 16(%rsp)
leaq .LC13(%rip), %rsi
leaq .LC14(%rip), %rdi
call fopen@PLT
movq %rax, %r15
leaq 12000(%rbx), %rsi
movl $0, %ecx
movl $0, %ebp
movl .LC15(%rip), %r12d
movq %rbx, 24(%rsp)
.L27:
movq %rsi, %r13
movl %ebp, %ebx
movq %rcx, %r14
movq %rcx, 32(%rsp)
movq %rsi, 40(%rsp)
.L29:
movl $0, %edx
movq %r14, %rsi
movq %r15, %rdi
call fseek@PLT
leaq 96(%rsp), %rdi
movq %r15, %r8
movl $3000, %ecx
movl $4, %edx
movl $12000, %esi
call __fread_chk@PLT
leaq -12000(%r13), %rax
.L28:
movl %r12d, (%rax)
addq $4, %rax
cmpq %r13, %rax
jne .L28
addq $12000, %r14
addl $60000, %ebx
addq $240000, %r13
leal 1200000(%rbp), %eax
cmpl %eax, %ebx
jne .L29
movq 32(%rsp), %rcx
movq 40(%rsp), %rsi
addl $3000, %ebp
addq $240000, %rcx
addq $12000, %rsi
cmpl $60000, %ebp
jne .L27
movq 24(%rsp), %rbx
movq %r15, %rdi
call fclose@PLT
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
call clock@PLT
movq 16(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
leaq .LC19(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq 8(%rsp), %rax
leaq 12000(%rax), %rcx
movl $0, %edx
movl $0, %r13d
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
movq %rbx, 40(%rsp)
movq %r12, %r15
movq %rdx, %rbx
movq %rcx, %r12
.L31:
movq %r12, %rbp
movl %r13d, 24(%rsp)
movq %rbx, %r14
.L33:
movl $0, %edx
movq %r14, %rsi
movq %r15, %rdi
call fseek@PLT
movq %r15, %r8
movl $3000, %ecx
movl $4, %edx
movl $12000, %esi
movq 32(%rsp), %rdi
call __fread_chk@PLT
leaq -12000(%rbp), %rax
.L32:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L32
addq $12000, %r14
addl $60000, 24(%rsp)
movl 24(%rsp), %ecx
addq $240000, %rbp
leal 1200000(%r13), %eax
cmpl %eax, %ecx
jne .L33
addl $3000, %r13d
addq $240000, %rbx
addq $12000, %r12
cmpl $60000, %r13d
jne .L31
movq 40(%rsp), %rbx
movq %r15, %rdi
call fclose@PLT
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
call clock@PLT
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %r12
leaq 491920(%r12), %r15
leaq _ZSt4cout(%rip), %r14
leaq .LC22(%rip), %r13
.L35:
movq %r12, %rsi
movq %r14, %rdi
call _ZN6thrust20THRUST_200700_800_NSlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES8_RKNS0_7complexIT_EE
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $49192, %r12
cmpq %r15, %r12
jne .L35
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %r12
leaq 56(%rsp), %rdi
movl $4800000, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L60
leaq 48(%rsp), %rdi
movl $4800000, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L61
leaq 64(%rsp), %rdi
movl $7034456, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L62
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4800000, %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L63
movl $1, %ecx
movl $4800000, %edx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L64
leaq .LC29(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $18, 72(%rsp)
movl $18, 76(%rsp)
movl $6, 80(%rsp)
movl $8, 84(%rsp)
movl $8, 88(%rsp)
movl $8, 92(%rsp)
leaq .LC30(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L41:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L66
call clock@PLT
movq %rax, %r14
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $7034456, %edx
movq 64(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L67
leaq .LC34(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC17(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC35(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $143, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $143, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $43, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $20, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $20, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1000, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %r13
leaq .LC36(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 16(%rsp), %rax
subq %rax, %r13
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
divsd .LC17(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq (%rsp), %rax
leaq 245960(%rax), %r12
leaq 247680(%rax), %r15
leaq _ZSt4cout(%rip), %r13
leaq .LC22(%rip), %r14
jmp .L44
.L52:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC27(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC28(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
movl $43, %r9d
movl $143, %r8d
movl $143, %ecx
movq 64(%rsp), %rdx
movq 48(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z87__device_stub__Z19matchedFilterKernelPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiiiPfS_PN6thrust20THRUST_200700_800_NS7complexIfEEiii
jmp .L41
.L66:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC31(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L67:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC33(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
movq 12104(%rsp), %rax
subq %fs:40, %rax
jne .L68
call _ZSt16__throw_bad_castv@PLT
.L68:
call __stack_chk_fail@PLT
.L48:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
.L49:
movsbl %al, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $344, %r12
cmpq %r15, %r12
je .L50
.L44:
leaq -245960(%r12), %rbp
.L45:
movq %rbp, %rsi
movq %r13, %rdi
call _ZN6thrust20THRUST_200700_800_NSlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES8_RKNS0_7complexIT_EE
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $49192, %rbp
cmpq %rbp, %r12
jne .L45
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .L69
cmpb $0, 56(%rbp)
je .L48
movzbl 67(%rbp), %eax
jmp .L49
.L50:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 12104(%rsp), %rax
subq %fs:40, %rax
jne .L70
movl $0, %eax
addq $12120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6338:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.type _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, @object
.size _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo7advanceE
.section .rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
.type _ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
.zero 1
.hidden _ZN4cuda3std3__438_GLOBAL__N__38402407_6_MF6_cu_6c3e07696ignoreE
.weak _ZN4cuda3std3__438_GLOBAL__N__38402407_6_MF6_cu_6c3e07696ignoreE
.section .rodata._ZN4cuda3std3__438_GLOBAL__N__38402407_6_MF6_cu_6c3e07696ignoreE,"aG",@progbits,_ZN4cuda3std3__438_GLOBAL__N__38402407_6_MF6_cu_6c3e07696ignoreE,comdat
.type _ZN4cuda3std3__438_GLOBAL__N__38402407_6_MF6_cu_6c3e07696ignoreE, @gnu_unique_object
.size _ZN4cuda3std3__438_GLOBAL__N__38402407_6_MF6_cu_6c3e07696ignoreE, 1
_ZN4cuda3std3__438_GLOBAL__N__38402407_6_MF6_cu_6c3e07696ignoreE:
.zero 1
.weak _ZN4cuda3std3__48in_placeE
.section .rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
.type _ZN4cuda3std3__48in_placeE, @gnu_unique_object
.size _ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
.zero 1
.weak _ZN4cuda3std3__45__cpo4cendE
.section .rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
.type _ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
.zero 1
.weak _ZN4cuda3std3__45__cpo6cbeginE
.section .rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
.type _ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
.zero 1
.weak _ZN4cuda3std3__45__cpo3endE
.section .rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
.type _ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
.zero 1
.weak _ZN4cuda3std3__45__cpo5beginE
.section .rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
.type _ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
.zero 1
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC17:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //============================================================================
// Name : MF6.cpp
// Author : Sohrab
// Version : 1
// Copyright : Hi!
// Description : Matched Filter in C++, Ansi-style
//============================================================================
#include <iostream>
#include <string>
#include <cmath>
#include <math.h>
#include <ctime>
#include <complex>
#include <vector>
#include <string>
#include "stdio.h"
#include "stdlib.h"
#include "time.h"
#include <thrust/complex.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
// references
#define date_ref "1015"
#define obj_ref "1"
#define run_ref 2
// 0: down sampling, 1: averaging, 2: nothing
#define average 2
//internal distance
#define int_dst 2.615
// TX relative position to TX's starting point
#define Tx_pos_x 0.41
#define Tx_pos_y -0.028
#define Tx_pos_z -0.012
//starting point of using samples
#define N_spl_fr 1000
#define N_lfreq_spl 0
#define N_hfreq_spl 0
#define N_mfreq_spl (N_spl_fr/2)-N_lfreq_spl-N_hfreq_spl
#define N_mfreq_spl_slow 2*((N_spl_fr/2)-N_lfreq_spl-N_hfreq_spl)
// Number of frames for each axis
#define N_x_stg 20 //1667
#define N_z_stg 20
//constants
#define Ts 6e-3
#define Rs 5e5
#define lambda 4.983873e-3
//step size between each two frames considered
#define dlx 0.005 * 0.006
#define dlz lambda/2
#define linxmax -dlx/2-(N_x_stg-1)*dlx
#define linzmax -dlz/2-(N_z_stg-1)*dlz
// environment dimensions
#define xmin -5
#define xmax 5
#define ymin 0
#define ymax 10
#define zmin -1.5
#define zmax 1.5
//resolution
#define res 0.07
//scientific values for some constants
#define sci_fac 1e8
#define c_sci 2.9979
#define fc_sci 609
#define As1_sci 1.5001e4
#define As2_sci 7.5005e3
#define file_size 100020000
#define size1 3000
#define BLOCK_WIDTH 8
#define Beat_I(uu, vv, nn) Beat_I[uu*N_z_stg*size1 + vv*size1 + nn]
#define Beat_R(uu, vv, nn) Beat_R[uu*N_z_stg*size1 + vv*size1 + nn]
#define cell_MF(xx, yy, zz) cell_MF[xx*Ny*Nz + yy*Nz + zz]
#define deviceCellMF(xx, yy, zz) deviceCellMF[xx*Ny*Nz + yy*Nz + zz]
using namespace std;
/****************** FUNCTIONS ******************/
struct indices {
int kx;
int ky;
int kz;
};
indices idxfinder(int n1, int n2, int n3, int k) {
k = k % (n1 * n2 * n3);
indices I;
I.kx = k % n1;
I.ky = ((int) floor(k / n1)) % n2;
I.kz = ((int) floor(k / (n1 * n2))) % n3;
return I;
}
/****************************************************/
/************* KERNEL CALL *************************/
__global__ void matchedFilterKernel(float* Beat_R, float* Beat_I, thrust::complex<float>* cell_MF, int Nx, int Ny, int Nz) {
#define MF_x_axis(xx) (xx*res + xmin)
#define MF_y_axis(yy) (yy*res + ymin)
#define MF_z_axis(zz) (zz*res + zmin)
#define u_axis(uu) (-dlx/2 - uu*dlx)
#define v_axis(vv) (-dlz/2 - vv*dlz)
const float pi = acosf(-1);
const thrust::complex<double> i(0, 1);
const thrust::complex<float> i_float(0, 1);
int xx, yy, zz;
xx = blockIdx.x * blockDim.x + threadIdx.x;
yy = blockIdx.y * blockDim.y + threadIdx.y;
zz = blockIdx.z * blockDim.z + threadIdx.z;
if(xx < Nx && yy < Ny && zz < Nz) {
float cell_z = MF_z_axis(zz);
float cell_y = MF_y_axis(yy);
float cell_x = MF_x_axis(xx);
thrust::complex<float> cell_sum = 0;
// for(int nn = 0; nn < size1; nn++) // 3000
// Beat[nn] = Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn);
// __shared__ complex<float> Beat[size1]
float cell_dist_t = sqrtf(
(cell_x - Tx_pos_x) * (cell_x - Tx_pos_x)
+ (cell_y - Tx_pos_y) * (cell_y - Tx_pos_y)
+ (cell_z - Tx_pos_z) * (cell_z - Tx_pos_z));
for (int uu = 0; uu < N_x_stg; uu++) { // N_x_stg
float x_diff = (cell_x - u_axis(uu)) * (cell_x - u_axis(uu));
for (int vv = 0; vv < N_z_stg; vv++) { // 2d receiver 1667*20
float temp_tau = (cell_dist_t + int_dst * 2 + sqrtf( x_diff +
(cell_z - v_axis(vv)) * (cell_z - v_axis(vv)) + cell_y * cell_y) ) / c_sci;
thrust::complex<float> temp_sig = exp(-i_float * (float) fmod((float)2.0 * pi * fc_sci * temp_tau, 2*pi) );
thrust::complex<float> Beat[size1];
thrust::complex<float> cell_sig_fst_temp[N_mfreq_spl];
thrust::complex<float> cell_sig_slow_temp[N_mfreq_spl_slow];
for(int nn = 0; nn < size1; nn++) // 3000
Beat[nn] = Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn);
for (int nn = 0; nn < N_mfreq_spl; nn++) { // for each fixed receiver and object location, 3000 samples
cell_sig_fst_temp[nn] = temp_sig * exp(-i_float * (float) fmod((float)(2.0 * pi *
As1_sci * (N_lfreq_spl / Rs + nn / Rs) * temp_tau), 2*pi));
cell_sum += cell_sig_fst_temp[nn] * (Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn)); //Beat[nn];
}
for (int nn = N_mfreq_spl; nn < 2*N_mfreq_spl; nn++) {
cell_sum += cell_sig_fst_temp[2*N_mfreq_spl-1-nn] * Beat[nn];
}
for (int nn = 0; nn < N_mfreq_spl_slow; nn++) {
cell_sig_slow_temp[nn] = temp_sig * exp(-i_float * (float) fmod((float)(2.0 * pi
* As2_sci * (N_lfreq_spl * 2 / Rs + nn / Rs) * temp_tau), 2*pi) );
cell_sum += cell_sig_slow_temp[nn] * Beat[nn+2*N_mfreq_spl];
}
for (int nn = N_mfreq_spl_slow; nn < 2* N_mfreq_spl_slow; nn++) {
cell_sum += cell_sig_slow_temp[2*N_mfreq_spl_slow-1-nn] * Beat[nn+2*N_mfreq_spl];
}
}
}
cell_MF(xx, yy, zz) = cell_sum;
}
#undef MF_x_axis
#undef MF_y_axis
#undef MF_z_axis
#undef u_axis
#undef v_axis
}
/**************************************************/
int
main(void)
{
cudaError_t err = cudaSuccess;
/************* LARGE ARRAY DECLRATATIONS AND NX, NY, NZ************/
int Nx = 143; // (int) floor((xmax-xmin)/res)+1; //143
int Ny = 143; //(int) floor((ymax-ymin)/res)+1; //143
int Nz = 43; //(int) floor((zmax-zmin)/res)+1; //43
// complex<float> cell_sig_fst[N_x_stg][N_z_stg][N_mfreq_spl];
// complex<float> cell_sig_slow[N_x_stg][N_z_stg][N_mfreq_spl_slow];
// Allocate host memory
float* Beat_R = (float *)malloc(N_x_stg * N_z_stg * size1 * sizeof(float)); //[N_x_stg][N_z_stg][size1] = {};
float* Beat_I = (float *)malloc(N_x_stg * N_z_stg * size1 * sizeof(float)); //[N_x_stg][N_z_stg][size1] = {};
thrust::complex<float>* cell_MF = (thrust::complex<float>*)malloc(Nx * Ny * Nz * sizeof(thrust::complex<float>)); //[Nx][Ny][Nz] 143 * 143 *43
// Verify that allocations succeeded
if (Beat_R == NULL || Beat_I == NULL || cell_MF == NULL )
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
/**************************************************/
clock_t begin = clock();
clock_t end;
// srand (time(NULL));
// for (int ii = 0; ii < N_z_stg; ii++)
// for (int jj = 0; jj < N_x_stg; jj++)
// for (int kk = 0; kk < size1; kk++) {
// Beat_R(jj, ii, kk) = (rand()%10 + 1)/10;
// Beat_I(jj, ii, kk) = (rand()%10 + 1)/10;
// }
/*********** READ THE .BIN FILES ************/
FILE *fp = fopen("/home/synrg-gpu1/Desktop/MF6/testReal.bin","rb");
for (int ii = 0; ii < N_z_stg; ii++){
for (int jj = 0; jj < N_x_stg; jj++) {
float b[size1];
fseek(fp, (ii*N_x_stg + jj)*size1*4, SEEK_SET);
fread(b, sizeof *b, size1, fp);
for(int kk = 0; kk < size1; kk++) {
Beat_R(jj, ii, kk) = 1;
//if (ii == 0 && jj == 1 && kk < 500) cout << b[kk] << endl;
}
}
}
fclose(fp);
cout << "Successfully read the file in " << (double) (clock() - begin) / CLOCKS_PER_SEC << " seconds!" << endl;
FILE *fp2 = fopen("/home/synrg-gpu1/Desktop/MF6/testImag.bin","rb");
for (int ii = 0; ii < N_z_stg; ii++){
for (int jj = 0; jj < N_x_stg; jj++) {
float b[size1];
fseek(fp2, (ii*N_x_stg + jj)*size1*4, SEEK_SET);
fread(b, sizeof *b, size1, fp2);
for(int kk = 0; kk < size1; kk++) {
Beat_I(jj, ii, kk) = 0;
}
}
}
fclose(fp2);
cout << "Successfully read the files in " << (double) (clock() - begin) / CLOCKS_PER_SEC << " seconds!" << endl;
// cout << Beat_I(149, 14, 149)<< endl << endl;
/******************** END OF READ FILE *********************/
//some constants
const float pi = acos(-1);
const thrust::complex<double> i(0, 1);
const thrust::complex<float> i_float(0, 1);
for (int i = 0; i < 1; i++){
for (int j = 0; j < 1; j++){
for (int k = 0; k < 10; k++) {
cout << cell_MF(k, j, i) << " ";
}
std::endl( std::cout );
}
std::endl( std::cout );
}
float* deviceBeatI;
float* deviceBeatR;
thrust::complex<float>* deviceCellMF;
clock_t begin_mem = clock();
// Allocate GPU memory
err = cudaMalloc((void **) &deviceBeatR , N_z_stg * N_x_stg * size1 * sizeof(float));
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate deviceBeatR (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &deviceBeatI , N_z_stg * N_x_stg * size1 * sizeof(float));
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate deviceBeatI (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &deviceCellMF , Nx * Ny * Nz * sizeof(thrust::complex<float>));
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate deviceCellMF (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(deviceBeatR, Beat_R, N_z_stg * N_x_stg * size1 * sizeof(float), cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy deviceBeatR from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(deviceBeatI, Beat_I, N_z_stg * N_x_stg * size1 * sizeof(float), cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy deviceBeatI from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cout << "hi!" << endl;
dim3 DimGrid(ceil(Nx * 1.0 / BLOCK_WIDTH), ceil(Ny * 1.0 / BLOCK_WIDTH), ceil(Nz * 1.0 /BLOCK_WIDTH));
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH, BLOCK_WIDTH);
cout << "Allocating & copying memory DONE! Time taken:" << (double) (clock() - begin_mem) / CLOCKS_PER_SEC;
matchedFilterKernel<<<DimGrid, DimBlock>>>(deviceBeatR, deviceBeatI, deviceCellMF, Nx, Ny, Nz);
cudaDeviceSynchronize();
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch matchedFilterKernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
begin_mem = clock();
printf("Copy output data from the CUDA device to the host memory\n");
err = cudaMemcpy(cell_MF, deviceCellMF, Nx * Ny * Nz * sizeof(thrust::complex<float>), cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy deviceCellMF from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cout << "Copying memory back DONE! Time taken:" << (double) (clock() - begin_mem) / CLOCKS_PER_SEC;
cout << "Hi! \n";
cout << Nx << endl;
cout << Ny << endl;
cout << Nz << endl;
cout << N_x_stg << endl;
cout << N_z_stg << endl;
cout << N_mfreq_spl_slow << endl;
end = clock();
cout << "DONE! Time taken:" << (double) (end - begin) / CLOCKS_PER_SEC;
for (int i = 0; i < 1; i++){
for (int j = 0; j < 5; j++){
for (int k = 0; k < 5; k++) {
cout << cell_MF(k, j, i) << " ";
}
std::endl( std::cout );
}
std::endl( std::cout );
}
cudaFree(deviceBeatR);
cudaFree(deviceBeatI);
cudaFree(deviceCellMF);
free(Beat_R);
free(Beat_I);
free(cell_MF);
return 0;
} | //============================================================================
// Name : MF6.cpp
// Author : Sohrab
// Version : 1
// Copyright : Hi!
// Description : Matched Filter in C++, Ansi-style
//============================================================================
#include <iostream>
#include <string>
#include <cmath>
#include <math.h>
#include <ctime>
#include <complex>
#include <vector>
#include <string>
#include "stdio.h"
#include "stdlib.h"
#include "time.h"
#include <thrust/complex.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
// references
#define date_ref "1015"
#define obj_ref "1"
#define run_ref 2
// 0: down sampling, 1: averaging, 2: nothing
#define average 2
//internal distance
#define int_dst 2.615
// TX relative position to TX's starting point
#define Tx_pos_x 0.41
#define Tx_pos_y -0.028
#define Tx_pos_z -0.012
//starting point of using samples
#define N_spl_fr 1000
#define N_lfreq_spl 0
#define N_hfreq_spl 0
#define N_mfreq_spl (N_spl_fr/2)-N_lfreq_spl-N_hfreq_spl
#define N_mfreq_spl_slow 2*((N_spl_fr/2)-N_lfreq_spl-N_hfreq_spl)
// Number of frames for each axis
#define N_x_stg 20 //1667
#define N_z_stg 20
//constants
#define Ts 6e-3
#define Rs 5e5
#define lambda 4.983873e-3
//step size between each two frames considered
#define dlx 0.005 * 0.006
#define dlz lambda/2
#define linxmax -dlx/2-(N_x_stg-1)*dlx
#define linzmax -dlz/2-(N_z_stg-1)*dlz
// environment dimensions
#define xmin -5
#define xmax 5
#define ymin 0
#define ymax 10
#define zmin -1.5
#define zmax 1.5
//resolution
#define res 0.07
//scientific values for some constants
#define sci_fac 1e8
#define c_sci 2.9979
#define fc_sci 609
#define As1_sci 1.5001e4
#define As2_sci 7.5005e3
#define file_size 100020000
#define size1 3000
#define BLOCK_WIDTH 8
#define Beat_I(uu, vv, nn) Beat_I[uu*N_z_stg*size1 + vv*size1 + nn]
#define Beat_R(uu, vv, nn) Beat_R[uu*N_z_stg*size1 + vv*size1 + nn]
#define cell_MF(xx, yy, zz) cell_MF[xx*Ny*Nz + yy*Nz + zz]
#define deviceCellMF(xx, yy, zz) deviceCellMF[xx*Ny*Nz + yy*Nz + zz]
using namespace std;
/****************** FUNCTIONS ******************/
struct indices {
int kx;
int ky;
int kz;
};
indices idxfinder(int n1, int n2, int n3, int k) {
k = k % (n1 * n2 * n3);
indices I;
I.kx = k % n1;
I.ky = ((int) floor(k / n1)) % n2;
I.kz = ((int) floor(k / (n1 * n2))) % n3;
return I;
}
/****************************************************/
/************* KERNEL CALL *************************/
__global__ void matchedFilterKernel(float* Beat_R, float* Beat_I, thrust::complex<float>* cell_MF, int Nx, int Ny, int Nz) {
#define MF_x_axis(xx) (xx*res + xmin)
#define MF_y_axis(yy) (yy*res + ymin)
#define MF_z_axis(zz) (zz*res + zmin)
#define u_axis(uu) (-dlx/2 - uu*dlx)
#define v_axis(vv) (-dlz/2 - vv*dlz)
const float pi = acosf(-1);
const thrust::complex<double> i(0, 1);
const thrust::complex<float> i_float(0, 1);
int xx, yy, zz;
xx = blockIdx.x * blockDim.x + threadIdx.x;
yy = blockIdx.y * blockDim.y + threadIdx.y;
zz = blockIdx.z * blockDim.z + threadIdx.z;
if(xx < Nx && yy < Ny && zz < Nz) {
float cell_z = MF_z_axis(zz);
float cell_y = MF_y_axis(yy);
float cell_x = MF_x_axis(xx);
thrust::complex<float> cell_sum = 0;
// for(int nn = 0; nn < size1; nn++) // 3000
// Beat[nn] = Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn);
// __shared__ complex<float> Beat[size1]
float cell_dist_t = sqrtf(
(cell_x - Tx_pos_x) * (cell_x - Tx_pos_x)
+ (cell_y - Tx_pos_y) * (cell_y - Tx_pos_y)
+ (cell_z - Tx_pos_z) * (cell_z - Tx_pos_z));
for (int uu = 0; uu < N_x_stg; uu++) { // N_x_stg
float x_diff = (cell_x - u_axis(uu)) * (cell_x - u_axis(uu));
for (int vv = 0; vv < N_z_stg; vv++) { // 2d receiver 1667*20
float temp_tau = (cell_dist_t + int_dst * 2 + sqrtf( x_diff +
(cell_z - v_axis(vv)) * (cell_z - v_axis(vv)) + cell_y * cell_y) ) / c_sci;
thrust::complex<float> temp_sig = exp(-i_float * (float) fmod((float)2.0 * pi * fc_sci * temp_tau, 2*pi) );
thrust::complex<float> Beat[size1];
thrust::complex<float> cell_sig_fst_temp[N_mfreq_spl];
thrust::complex<float> cell_sig_slow_temp[N_mfreq_spl_slow];
for(int nn = 0; nn < size1; nn++) // 3000
Beat[nn] = Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn);
for (int nn = 0; nn < N_mfreq_spl; nn++) { // for each fixed receiver and object location, 3000 samples
cell_sig_fst_temp[nn] = temp_sig * exp(-i_float * (float) fmod((float)(2.0 * pi *
As1_sci * (N_lfreq_spl / Rs + nn / Rs) * temp_tau), 2*pi));
cell_sum += cell_sig_fst_temp[nn] * (Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn)); //Beat[nn];
}
for (int nn = N_mfreq_spl; nn < 2*N_mfreq_spl; nn++) {
cell_sum += cell_sig_fst_temp[2*N_mfreq_spl-1-nn] * Beat[nn];
}
for (int nn = 0; nn < N_mfreq_spl_slow; nn++) {
cell_sig_slow_temp[nn] = temp_sig * exp(-i_float * (float) fmod((float)(2.0 * pi
* As2_sci * (N_lfreq_spl * 2 / Rs + nn / Rs) * temp_tau), 2*pi) );
cell_sum += cell_sig_slow_temp[nn] * Beat[nn+2*N_mfreq_spl];
}
for (int nn = N_mfreq_spl_slow; nn < 2* N_mfreq_spl_slow; nn++) {
cell_sum += cell_sig_slow_temp[2*N_mfreq_spl_slow-1-nn] * Beat[nn+2*N_mfreq_spl];
}
}
}
cell_MF(xx, yy, zz) = cell_sum;
}
#undef MF_x_axis
#undef MF_y_axis
#undef MF_z_axis
#undef u_axis
#undef v_axis
}
/**************************************************/
int
main(void)
{
hipError_t err = hipSuccess;
/************* LARGE ARRAY DECLRATATIONS AND NX, NY, NZ************/
int Nx = 143; // (int) floor((xmax-xmin)/res)+1; //143
int Ny = 143; //(int) floor((ymax-ymin)/res)+1; //143
int Nz = 43; //(int) floor((zmax-zmin)/res)+1; //43
// complex<float> cell_sig_fst[N_x_stg][N_z_stg][N_mfreq_spl];
// complex<float> cell_sig_slow[N_x_stg][N_z_stg][N_mfreq_spl_slow];
// Allocate host memory
float* Beat_R = (float *)malloc(N_x_stg * N_z_stg * size1 * sizeof(float)); //[N_x_stg][N_z_stg][size1] = {};
float* Beat_I = (float *)malloc(N_x_stg * N_z_stg * size1 * sizeof(float)); //[N_x_stg][N_z_stg][size1] = {};
thrust::complex<float>* cell_MF = (thrust::complex<float>*)malloc(Nx * Ny * Nz * sizeof(thrust::complex<float>)); //[Nx][Ny][Nz] 143 * 143 *43
// Verify that allocations succeeded
if (Beat_R == NULL || Beat_I == NULL || cell_MF == NULL )
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
/**************************************************/
clock_t begin = clock();
clock_t end;
// srand (time(NULL));
// for (int ii = 0; ii < N_z_stg; ii++)
// for (int jj = 0; jj < N_x_stg; jj++)
// for (int kk = 0; kk < size1; kk++) {
// Beat_R(jj, ii, kk) = (rand()%10 + 1)/10;
// Beat_I(jj, ii, kk) = (rand()%10 + 1)/10;
// }
/*********** READ THE .BIN FILES ************/
FILE *fp = fopen("/home/synrg-gpu1/Desktop/MF6/testReal.bin","rb");
for (int ii = 0; ii < N_z_stg; ii++){
for (int jj = 0; jj < N_x_stg; jj++) {
float b[size1];
fseek(fp, (ii*N_x_stg + jj)*size1*4, SEEK_SET);
fread(b, sizeof *b, size1, fp);
for(int kk = 0; kk < size1; kk++) {
Beat_R(jj, ii, kk) = 1;
//if (ii == 0 && jj == 1 && kk < 500) cout << b[kk] << endl;
}
}
}
fclose(fp);
cout << "Successfully read the file in " << (double) (clock() - begin) / CLOCKS_PER_SEC << " seconds!" << endl;
FILE *fp2 = fopen("/home/synrg-gpu1/Desktop/MF6/testImag.bin","rb");
for (int ii = 0; ii < N_z_stg; ii++){
for (int jj = 0; jj < N_x_stg; jj++) {
float b[size1];
fseek(fp2, (ii*N_x_stg + jj)*size1*4, SEEK_SET);
fread(b, sizeof *b, size1, fp2);
for(int kk = 0; kk < size1; kk++) {
Beat_I(jj, ii, kk) = 0;
}
}
}
fclose(fp2);
cout << "Successfully read the files in " << (double) (clock() - begin) / CLOCKS_PER_SEC << " seconds!" << endl;
// cout << Beat_I(149, 14, 149)<< endl << endl;
/******************** END OF READ FILE *********************/
//some constants
const float pi = acos(-1);
const thrust::complex<double> i(0, 1);
const thrust::complex<float> i_float(0, 1);
for (int i = 0; i < 1; i++){
for (int j = 0; j < 1; j++){
for (int k = 0; k < 10; k++) {
cout << cell_MF(k, j, i) << " ";
}
std::endl( std::cout );
}
std::endl( std::cout );
}
float* deviceBeatI;
float* deviceBeatR;
thrust::complex<float>* deviceCellMF;
clock_t begin_mem = clock();
// Allocate GPU memory
err = hipMalloc((void **) &deviceBeatR , N_z_stg * N_x_stg * size1 * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate deviceBeatR (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &deviceBeatI , N_z_stg * N_x_stg * size1 * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate deviceBeatI (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &deviceCellMF , Nx * Ny * Nz * sizeof(thrust::complex<float>));
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate deviceCellMF (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(deviceBeatR, Beat_R, N_z_stg * N_x_stg * size1 * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy deviceBeatR from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(deviceBeatI, Beat_I, N_z_stg * N_x_stg * size1 * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy deviceBeatI from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
cout << "hi!" << endl;
dim3 DimGrid(ceil(Nx * 1.0 / BLOCK_WIDTH), ceil(Ny * 1.0 / BLOCK_WIDTH), ceil(Nz * 1.0 /BLOCK_WIDTH));
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH, BLOCK_WIDTH);
cout << "Allocating & copying memory DONE! Time taken:" << (double) (clock() - begin_mem) / CLOCKS_PER_SEC;
matchedFilterKernel<<<DimGrid, DimBlock>>>(deviceBeatR, deviceBeatI, deviceCellMF, Nx, Ny, Nz);
hipDeviceSynchronize();
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch matchedFilterKernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
begin_mem = clock();
printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(cell_MF, deviceCellMF, Nx * Ny * Nz * sizeof(thrust::complex<float>), hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy deviceCellMF from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
cout << "Copying memory back DONE! Time taken:" << (double) (clock() - begin_mem) / CLOCKS_PER_SEC;
cout << "Hi! \n";
cout << Nx << endl;
cout << Ny << endl;
cout << Nz << endl;
cout << N_x_stg << endl;
cout << N_z_stg << endl;
cout << N_mfreq_spl_slow << endl;
end = clock();
cout << "DONE! Time taken:" << (double) (end - begin) / CLOCKS_PER_SEC;
for (int i = 0; i < 1; i++){
for (int j = 0; j < 5; j++){
for (int k = 0; k < 5; k++) {
cout << cell_MF(k, j, i) << " ";
}
std::endl( std::cout );
}
std::endl( std::cout );
}
hipFree(deviceBeatR);
hipFree(deviceBeatI);
hipFree(deviceCellMF);
free(Beat_R);
free(Beat_I);
free(cell_MF);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //============================================================================
// Name : MF6.cpp
// Author : Sohrab
// Version : 1
// Copyright : Hi!
// Description : Matched Filter in C++, Ansi-style
//============================================================================
#include <iostream>
#include <string>
#include <cmath>
#include <math.h>
#include <ctime>
#include <complex>
#include <vector>
#include <string>
#include "stdio.h"
#include "stdlib.h"
#include "time.h"
#include <thrust/complex.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
// references
#define date_ref "1015"
#define obj_ref "1"
#define run_ref 2
// 0: down sampling, 1: averaging, 2: nothing
#define average 2
//internal distance
#define int_dst 2.615
// TX relative position to TX's starting point
#define Tx_pos_x 0.41
#define Tx_pos_y -0.028
#define Tx_pos_z -0.012
//starting point of using samples
#define N_spl_fr 1000
#define N_lfreq_spl 0
#define N_hfreq_spl 0
#define N_mfreq_spl (N_spl_fr/2)-N_lfreq_spl-N_hfreq_spl
#define N_mfreq_spl_slow 2*((N_spl_fr/2)-N_lfreq_spl-N_hfreq_spl)
// Number of frames for each axis
#define N_x_stg 20 //1667
#define N_z_stg 20
//constants
#define Ts 6e-3
#define Rs 5e5
#define lambda 4.983873e-3
//step size between each two frames considered
#define dlx 0.005 * 0.006
#define dlz lambda/2
#define linxmax -dlx/2-(N_x_stg-1)*dlx
#define linzmax -dlz/2-(N_z_stg-1)*dlz
// environment dimensions
#define xmin -5
#define xmax 5
#define ymin 0
#define ymax 10
#define zmin -1.5
#define zmax 1.5
//resolution
#define res 0.07
//scientific values for some constants
#define sci_fac 1e8
#define c_sci 2.9979
#define fc_sci 609
#define As1_sci 1.5001e4
#define As2_sci 7.5005e3
#define file_size 100020000
#define size1 3000
#define BLOCK_WIDTH 8
#define Beat_I(uu, vv, nn) Beat_I[uu*N_z_stg*size1 + vv*size1 + nn]
#define Beat_R(uu, vv, nn) Beat_R[uu*N_z_stg*size1 + vv*size1 + nn]
#define cell_MF(xx, yy, zz) cell_MF[xx*Ny*Nz + yy*Nz + zz]
#define deviceCellMF(xx, yy, zz) deviceCellMF[xx*Ny*Nz + yy*Nz + zz]
using namespace std;
/****************** FUNCTIONS ******************/
struct indices {
int kx;
int ky;
int kz;
};
indices idxfinder(int n1, int n2, int n3, int k) {
k = k % (n1 * n2 * n3);
indices I;
I.kx = k % n1;
I.ky = ((int) floor(k / n1)) % n2;
I.kz = ((int) floor(k / (n1 * n2))) % n3;
return I;
}
/****************************************************/
/************* KERNEL CALL *************************/
__global__ void matchedFilterKernel(float* Beat_R, float* Beat_I, thrust::complex<float>* cell_MF, int Nx, int Ny, int Nz) {
#define MF_x_axis(xx) (xx*res + xmin)
#define MF_y_axis(yy) (yy*res + ymin)
#define MF_z_axis(zz) (zz*res + zmin)
#define u_axis(uu) (-dlx/2 - uu*dlx)
#define v_axis(vv) (-dlz/2 - vv*dlz)
const float pi = acosf(-1);
const thrust::complex<double> i(0, 1);
const thrust::complex<float> i_float(0, 1);
int xx, yy, zz;
xx = blockIdx.x * blockDim.x + threadIdx.x;
yy = blockIdx.y * blockDim.y + threadIdx.y;
zz = blockIdx.z * blockDim.z + threadIdx.z;
if(xx < Nx && yy < Ny && zz < Nz) {
float cell_z = MF_z_axis(zz);
float cell_y = MF_y_axis(yy);
float cell_x = MF_x_axis(xx);
thrust::complex<float> cell_sum = 0;
// for(int nn = 0; nn < size1; nn++) // 3000
// Beat[nn] = Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn);
// __shared__ complex<float> Beat[size1]
float cell_dist_t = sqrtf(
(cell_x - Tx_pos_x) * (cell_x - Tx_pos_x)
+ (cell_y - Tx_pos_y) * (cell_y - Tx_pos_y)
+ (cell_z - Tx_pos_z) * (cell_z - Tx_pos_z));
for (int uu = 0; uu < N_x_stg; uu++) { // N_x_stg
float x_diff = (cell_x - u_axis(uu)) * (cell_x - u_axis(uu));
for (int vv = 0; vv < N_z_stg; vv++) { // 2d receiver 1667*20
float temp_tau = (cell_dist_t + int_dst * 2 + sqrtf( x_diff +
(cell_z - v_axis(vv)) * (cell_z - v_axis(vv)) + cell_y * cell_y) ) / c_sci;
thrust::complex<float> temp_sig = exp(-i_float * (float) fmod((float)2.0 * pi * fc_sci * temp_tau, 2*pi) );
thrust::complex<float> Beat[size1];
thrust::complex<float> cell_sig_fst_temp[N_mfreq_spl];
thrust::complex<float> cell_sig_slow_temp[N_mfreq_spl_slow];
for(int nn = 0; nn < size1; nn++) // 3000
Beat[nn] = Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn);
for (int nn = 0; nn < N_mfreq_spl; nn++) { // for each fixed receiver and object location, 3000 samples
cell_sig_fst_temp[nn] = temp_sig * exp(-i_float * (float) fmod((float)(2.0 * pi *
As1_sci * (N_lfreq_spl / Rs + nn / Rs) * temp_tau), 2*pi));
cell_sum += cell_sig_fst_temp[nn] * (Beat_R(uu, vv, nn) + i_float * Beat_I(uu, vv, nn)); //Beat[nn];
}
for (int nn = N_mfreq_spl; nn < 2*N_mfreq_spl; nn++) {
cell_sum += cell_sig_fst_temp[2*N_mfreq_spl-1-nn] * Beat[nn];
}
for (int nn = 0; nn < N_mfreq_spl_slow; nn++) {
cell_sig_slow_temp[nn] = temp_sig * exp(-i_float * (float) fmod((float)(2.0 * pi
* As2_sci * (N_lfreq_spl * 2 / Rs + nn / Rs) * temp_tau), 2*pi) );
cell_sum += cell_sig_slow_temp[nn] * Beat[nn+2*N_mfreq_spl];
}
for (int nn = N_mfreq_spl_slow; nn < 2* N_mfreq_spl_slow; nn++) {
cell_sum += cell_sig_slow_temp[2*N_mfreq_spl_slow-1-nn] * Beat[nn+2*N_mfreq_spl];
}
}
}
cell_MF(xx, yy, zz) = cell_sum;
}
#undef MF_x_axis
#undef MF_y_axis
#undef MF_z_axis
#undef u_axis
#undef v_axis
}
/**************************************************/
int
main(void)
{
hipError_t err = hipSuccess;
/************* LARGE ARRAY DECLRATATIONS AND NX, NY, NZ************/
int Nx = 143; // (int) floor((xmax-xmin)/res)+1; //143
int Ny = 143; //(int) floor((ymax-ymin)/res)+1; //143
int Nz = 43; //(int) floor((zmax-zmin)/res)+1; //43
// complex<float> cell_sig_fst[N_x_stg][N_z_stg][N_mfreq_spl];
// complex<float> cell_sig_slow[N_x_stg][N_z_stg][N_mfreq_spl_slow];
// Allocate host memory
float* Beat_R = (float *)malloc(N_x_stg * N_z_stg * size1 * sizeof(float)); //[N_x_stg][N_z_stg][size1] = {};
float* Beat_I = (float *)malloc(N_x_stg * N_z_stg * size1 * sizeof(float)); //[N_x_stg][N_z_stg][size1] = {};
thrust::complex<float>* cell_MF = (thrust::complex<float>*)malloc(Nx * Ny * Nz * sizeof(thrust::complex<float>)); //[Nx][Ny][Nz] 143 * 143 *43
// Verify that allocations succeeded
if (Beat_R == NULL || Beat_I == NULL || cell_MF == NULL )
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
/**************************************************/
clock_t begin = clock();
clock_t end;
// srand (time(NULL));
// for (int ii = 0; ii < N_z_stg; ii++)
// for (int jj = 0; jj < N_x_stg; jj++)
// for (int kk = 0; kk < size1; kk++) {
// Beat_R(jj, ii, kk) = (rand()%10 + 1)/10;
// Beat_I(jj, ii, kk) = (rand()%10 + 1)/10;
// }
/*********** READ THE .BIN FILES ************/
FILE *fp = fopen("/home/synrg-gpu1/Desktop/MF6/testReal.bin","rb");
for (int ii = 0; ii < N_z_stg; ii++){
for (int jj = 0; jj < N_x_stg; jj++) {
float b[size1];
fseek(fp, (ii*N_x_stg + jj)*size1*4, SEEK_SET);
fread(b, sizeof *b, size1, fp);
for(int kk = 0; kk < size1; kk++) {
Beat_R(jj, ii, kk) = 1;
//if (ii == 0 && jj == 1 && kk < 500) cout << b[kk] << endl;
}
}
}
fclose(fp);
cout << "Successfully read the file in " << (double) (clock() - begin) / CLOCKS_PER_SEC << " seconds!" << endl;
FILE *fp2 = fopen("/home/synrg-gpu1/Desktop/MF6/testImag.bin","rb");
for (int ii = 0; ii < N_z_stg; ii++){
for (int jj = 0; jj < N_x_stg; jj++) {
float b[size1];
fseek(fp2, (ii*N_x_stg + jj)*size1*4, SEEK_SET);
fread(b, sizeof *b, size1, fp2);
for(int kk = 0; kk < size1; kk++) {
Beat_I(jj, ii, kk) = 0;
}
}
}
fclose(fp2);
cout << "Successfully read the files in " << (double) (clock() - begin) / CLOCKS_PER_SEC << " seconds!" << endl;
// cout << Beat_I(149, 14, 149)<< endl << endl;
/******************** END OF READ FILE *********************/
//some constants
const float pi = acos(-1);
const thrust::complex<double> i(0, 1);
const thrust::complex<float> i_float(0, 1);
for (int i = 0; i < 1; i++){
for (int j = 0; j < 1; j++){
for (int k = 0; k < 10; k++) {
cout << cell_MF(k, j, i) << " ";
}
std::endl( std::cout );
}
std::endl( std::cout );
}
float* deviceBeatI;
float* deviceBeatR;
thrust::complex<float>* deviceCellMF;
clock_t begin_mem = clock();
// Allocate GPU memory
err = hipMalloc((void **) &deviceBeatR , N_z_stg * N_x_stg * size1 * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate deviceBeatR (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &deviceBeatI , N_z_stg * N_x_stg * size1 * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate deviceBeatI (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &deviceCellMF , Nx * Ny * Nz * sizeof(thrust::complex<float>));
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate deviceCellMF (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(deviceBeatR, Beat_R, N_z_stg * N_x_stg * size1 * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy deviceBeatR from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(deviceBeatI, Beat_I, N_z_stg * N_x_stg * size1 * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy deviceBeatI from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
cout << "hi!" << endl;
dim3 DimGrid(ceil(Nx * 1.0 / BLOCK_WIDTH), ceil(Ny * 1.0 / BLOCK_WIDTH), ceil(Nz * 1.0 /BLOCK_WIDTH));
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH, BLOCK_WIDTH);
cout << "Allocating & copying memory DONE! Time taken:" << (double) (clock() - begin_mem) / CLOCKS_PER_SEC;
matchedFilterKernel<<<DimGrid, DimBlock>>>(deviceBeatR, deviceBeatI, deviceCellMF, Nx, Ny, Nz);
hipDeviceSynchronize();
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch matchedFilterKernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
begin_mem = clock();
printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(cell_MF, deviceCellMF, Nx * Ny * Nz * sizeof(thrust::complex<float>), hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy deviceCellMF from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
cout << "Copying memory back DONE! Time taken:" << (double) (clock() - begin_mem) / CLOCKS_PER_SEC;
cout << "Hi! \n";
cout << Nx << endl;
cout << Ny << endl;
cout << Nz << endl;
cout << N_x_stg << endl;
cout << N_z_stg << endl;
cout << N_mfreq_spl_slow << endl;
end = clock();
cout << "DONE! Time taken:" << (double) (end - begin) / CLOCKS_PER_SEC;
for (int i = 0; i < 1; i++){
for (int j = 0; j < 5; j++){
for (int k = 0; k < 5; k++) {
cout << cell_MF(k, j, i) << " ";
}
std::endl( std::cout );
}
std::endl( std::cout );
}
hipFree(deviceBeatR);
hipFree(deviceBeatI);
hipFree(deviceCellMF);
free(Beat_R);
free(Beat_I);
free(cell_MF);
return 0;
} | .text
.file "MF6.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9idxfinderiiii # -- Begin function _Z9idxfinderiiii
.p2align 4, 0x90
.type _Z9idxfinderiiii,@function
_Z9idxfinderiiii: # @_Z9idxfinderiiii
.cfi_startproc
# %bb.0:
movl %ecx, %eax
movl %edx, %ecx
movl %esi, %r9d
imull %edi, %r9d
movl %r9d, %r8d
imull %edx, %r8d
cltd
idivl %r8d
movl %edx, %r8d
movl %edx, %eax
cltd
idivl %edi
movl %edx, %edi
cltd
idivl %esi
movl %edx, %esi
movl %r8d, %eax
cltd
idivl %r9d
cltd
idivl %ecx
shlq $32, %rsi
orq %rsi, %rdi
movq %rdi, %rax
retq
.Lfunc_end0:
.size _Z9idxfinderiiii, .Lfunc_end0-_Z9idxfinderiiii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__matchedFilterKernelPfS_PN6thrust7complexIfEEiii # -- Begin function _Z34__device_stub__matchedFilterKernelPfS_PN6thrust7complexIfEEiii
.p2align 4, 0x90
.type _Z34__device_stub__matchedFilterKernelPfS_PN6thrust7complexIfEEiii,@function
_Z34__device_stub__matchedFilterKernelPfS_PN6thrust7complexIfEEiii: # @_Z34__device_stub__matchedFilterKernelPfS_PN6thrust7complexIfEEiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z34__device_stub__matchedFilterKernelPfS_PN6thrust7complexIfEEiii, .Lfunc_end1-_Z34__device_stub__matchedFilterKernelPfS_PN6thrust7complexIfEEiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $12168, %rsp # imm = 0x2F88
.cfi_def_cfa_offset 12224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4800000, %edi # imm = 0x493E00
callq malloc
movq %rax, %r14
movl $4800000, %edi # imm = 0x493E00
callq malloc
movq %rax, %rbx
movl $7034456, %edi # imm = 0x6B5658
callq malloc
testq %r14, %r14
je .LBB2_89
# %bb.1:
testq %rbx, %rbx
je .LBB2_89
# %bb.2:
testq %rax, %rax
je .LBB2_89
# %bb.3:
movq %rax, (%rsp) # 8-byte Spill
movq %rbx, 64(%rsp) # 8-byte Spill
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r13
xorl %ebx, %ebx
leaq 160(%rsp), %rbp
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %r12
.p2align 4, 0x90
.LBB2_4: # %.preheader214
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
# Child Loop BB2_6 Depth 3
leaq (,%rbx,4), %rax
leaq (%rax,%rax,4), %r15
movq %r12, 16(%rsp) # 8-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_4 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
leaq (%r14,%r15), %rax
imulq $12000, %rax, %rsi # imm = 0x2EE0
movq %r13, %rdi
xorl %edx, %edx
callq fseek
movl $4, %esi
movl $3000, %edx # imm = 0xBB8
movq %rbp, %rdi
movq %r13, %rcx
callq fread
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_4 Depth=1
# Parent Loop BB2_5 Depth=2
# => This Inner Loop Header: Depth=3
movl $1065353216, (%r12,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $3000, %rax # imm = 0xBB8
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=2
incq %r14
addq $240000, %r12 # imm = 0x3A980
cmpq $20, %r14
jne .LBB2_5
# %bb.8: # in Loop: Header=BB2_4 Depth=1
incq %rbx
movq 16(%rsp), %r12 # 8-byte Reload
addq $12000, %r12 # imm = 0x2EE0
cmpq $20, %rbx
jne .LBB2_4
# %bb.9:
movq %r13, %rdi
callq fclose
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq 8(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.4, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r12
testq %r12, %r12
je .LBB2_90
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i161
cmpb $0, 56(%r12)
je .LBB2_12
# %bb.11:
movzbl 67(%r12), %eax
jmp .LBB2_13
.LBB2_12:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit164
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.5, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r13
xorl %r12d, %r12d
leaq 160(%rsp), %rbp
movq 64(%rsp), %r15 # 8-byte Reload
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_14: # %.preheader213
# =>This Loop Header: Depth=1
# Child Loop BB2_15 Depth 2
movq %rax, 80(%rsp) # 8-byte Spill
movq $-4800000, %r14 # imm = 0xFFB6C200
movq %r12, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_15: # Parent Loop BB2_14 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%r14), %rbx
addq $4800000, %rbx # imm = 0x493E00
movq %r13, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq fseek
movl $4, %esi
movl $3000, %edx # imm = 0xBB8
movq %rbp, %rdi
movq %r13, %rcx
callq fread
movl $12000, %edx # imm = 0x2EE0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
addq $12000, %r12 # imm = 0x2EE0
addq $240000, %r14 # imm = 0x3A980
jne .LBB2_15
# %bb.16: # in Loop: Header=BB2_14 Depth=1
movq 80(%rsp), %rax # 8-byte Reload
incq %rax
movq 16(%rsp), %r12 # 8-byte Reload
addq $240000, %r12 # imm = 0x3A980
addq $12000, %r15 # imm = 0x2EE0
cmpq $20, %rax
jne .LBB2_14
# %bb.17: # %.critedge
movq %r13, %rdi
callq fclose
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq 8(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.4, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r12
testq %r12, %r12
je .LBB2_90
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i166
cmpb $0, 56(%r12)
movq 72(%rsp), %r15 # 8-byte Reload
movq 64(%rsp), %rbp # 8-byte Reload
je .LBB2_20
# %bb.19:
movzbl 67(%r12), %eax
jmp .LBB2_21
.LBB2_20:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit169
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
movq (%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB2_22: # =>This Inner Loop Header: Depth=1
leaq (%r14,%rbx), %rsi
movl $_ZSt4cout, %edi
callq _ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addq $49192, %rbx # imm = 0xC028
cmpq $491920, %rbx # imm = 0x78190
jne .LBB2_22
# %bb.23:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_90
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_26
# %bb.25:
movzbl 67(%r12), %eax
jmp .LBB2_27
.LBB2_26:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_90
# %bb.28: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i146
cmpb $0, 56(%r12)
je .LBB2_30
# %bb.29:
movzbl 67(%r12), %eax
jmp .LBB2_31
.LBB2_30:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_31: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit149
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %r13
leaq 32(%rsp), %rdi
movl $4800000, %esi # imm = 0x493E00
callq hipMalloc
testl %eax, %eax
jne .LBB2_32
# %bb.34:
leaq 40(%rsp), %rdi
movl $4800000, %esi # imm = 0x493E00
callq hipMalloc
testl %eax, %eax
jne .LBB2_35
# %bb.36:
leaq 24(%rsp), %rdi
movl $7034456, %esi # imm = 0x6B5658
callq hipMalloc
testl %eax, %eax
jne .LBB2_37
# %bb.38:
movl $.Lstr, %edi
callq puts@PLT
movq 32(%rsp), %rdi
movl $4800000, %edx # imm = 0x493E00
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_39
# %bb.40:
movq 40(%rsp), %rdi
movl $4800000, %edx # imm = 0x493E00
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_41
# %bb.42:
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_90
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i171
cmpb $0, 56(%r12)
je .LBB2_45
# %bb.44:
movzbl 67(%r12), %eax
jmp .LBB2_46
.LBB2_45:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit174
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq %r13, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movabsq $77309411346, %rdi # imm = 0x1200000012
movabsq $34359738376, %rdx # imm = 0x800000008
movl $6, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_48
# %bb.47:
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl $143, 60(%rsp)
movl $143, 56(%rsp)
movl $43, 52(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 60(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 52(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_48:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
movq (%rsp), %r14 # 8-byte Reload
jne .LBB2_49
# %bb.50:
callq clock
movq %rax, %r12
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rsi
movl $7034456, %edx # imm = 0x6B5658
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_51
# %bb.52: # %.critedge144
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq %r12, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $143, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_90
# %bb.53: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i176
cmpb $0, 56(%r12)
je .LBB2_55
# %bb.54:
movzbl 67(%r12), %ecx
jmp .LBB2_56
.LBB2_55:
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_56: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit179
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $143, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_90
# %bb.57: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i181
cmpb $0, 56(%r12)
je .LBB2_59
# %bb.58:
movzbl 67(%r12), %ecx
jmp .LBB2_60
.LBB2_59:
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_60: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit184
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $43, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_90
# %bb.61: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i186
cmpb $0, 56(%r12)
je .LBB2_63
# %bb.62:
movzbl 67(%r12), %ecx
jmp .LBB2_64
.LBB2_63:
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_64: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit189
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $20, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_90
# %bb.65: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i191
cmpb $0, 56(%r12)
je .LBB2_67
# %bb.66:
movzbl 67(%r12), %ecx
jmp .LBB2_68
.LBB2_67:
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_68: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit194
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $20, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_90
# %bb.69: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i196
cmpb $0, 56(%r12)
je .LBB2_71
# %bb.70:
movzbl 67(%r12), %ecx
jmp .LBB2_72
.LBB2_71:
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_72: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit199
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $1000, %esi # imm = 0x3E8
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_90
# %bb.73: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i201
cmpb $0, 56(%r12)
je .LBB2_75
# %bb.74:
movzbl 67(%r12), %ecx
jmp .LBB2_76
.LBB2_75:
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_76: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit204
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.21, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq 8(%rsp), %rbx # 8-byte Folded Reload
cvtsi2sd %rbx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
xorl %ebx, %ebx
movq %r14, %r13
jmp .LBB2_77
.p2align 4, 0x90
.LBB2_87: # in Loop: Header=BB2_77 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_88: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit159
# in Loop: Header=BB2_77 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
addq $344, %r13 # imm = 0x158
cmpq $5, %rbx
je .LBB2_82
.LBB2_77: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_78 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_78: # Parent Loop BB2_77 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r14,%r13), %rsi
movl $_ZSt4cout, %edi
callq _ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addq $49192, %r14 # imm = 0xC028
cmpq $245960, %r14 # imm = 0x3C0C8
jne .LBB2_78
# %bb.79: # in Loop: Header=BB2_77 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_90
# %bb.80: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i156
# in Loop: Header=BB2_77 Depth=1
cmpb $0, 56(%r12)
je .LBB2_87
# %bb.81: # in Loop: Header=BB2_77 Depth=1
movzbl 67(%r12), %eax
jmp .LBB2_88
.LBB2_82:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_90
# %bb.83: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i151
cmpb $0, 56(%r12)
movq (%rsp), %rbx # 8-byte Reload
je .LBB2_85
# %bb.84:
movzbl 67(%r12), %eax
jmp .LBB2_86
.LBB2_85:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_86: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit154
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %rbp, %rdi
callq free
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $12168, %rsp # imm = 0x2F88
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_90:
.cfi_def_cfa_offset 12224
callq _ZSt16__throw_bad_castv
.LBB2_89:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB2_33
.LBB2_35:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB2_33
.LBB2_37:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB2_33
.LBB2_39:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
jmp .LBB2_33
.LBB2_41:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB2_33
.LBB2_49:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
jmp .LBB2_33
.LBB2_51:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.18, %esi
.LBB2_33:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE,"axG",@progbits,_ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE,comdat
.weak _ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE # -- Begin function _ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE
.p2align 4, 0x90
.type _ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE,@function
_ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE: # @_ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq %rdi, %rbx
movb $40, 13(%rsp)
movq (%rdi), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .LBB3_2
# %bb.1:
leaq 13(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB3_3
.LBB3_2:
movq %rbx, %rdi
movl $40, %esi
callq _ZNSo3putEc
movq %rbx, %rdi
.LBB3_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
callq _ZNSo9_M_insertIdEERSoT_
movb $44, 14(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB3_5
# %bb.4:
leaq 14(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB3_6
.LBB3_5:
movq %rax, %r15
movq %rax, %rdi
movl $44, %esi
callq _ZNSo3putEc
movq %r15, %rdi
.LBB3_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit6
movss 4(%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
callq _ZNSo9_M_insertIdEERSoT_
movb $41, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB3_8
# %bb.7:
leaq 15(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_9
.LBB3_8:
movq %rax, %rdi
movl $41, %esi
callq _ZNSo3putEc
.LBB3_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit9
movq %rbx, %rax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE, .Lfunc_end3-_ZN6thrustlsIfcSt11char_traitsIcEEERSt13basic_ostreamIT0_T1_ES7_RKNS_7complexIT_EE
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii,@object # @_Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii
.section .rodata,"a",@progbits
.globl _Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii
.p2align 3, 0x0
_Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii:
.quad _Z34__device_stub__matchedFilterKernelPfS_PN6thrust7complexIfEEiii
.size _Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate host vectors!\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/synrg-gpu1/Desktop/MF6/testReal.bin"
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "rb"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Successfully read the file in "
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " seconds!"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/synrg-gpu1/Desktop/MF6/testImag.bin"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Successfully read the files in "
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " "
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate deviceBeatR (error code %s)!\n"
.size .L.str.8, 49
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to allocate deviceBeatI (error code %s)!\n"
.size .L.str.9, 49
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to allocate deviceCellMF (error code %s)!\n"
.size .L.str.10, 50
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to copy deviceBeatR from host to device (error code %s)!\n"
.size .L.str.12, 65
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to copy deviceBeatI from host to device (error code %s)!\n"
.size .L.str.13, 65
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "hi!"
.size .L.str.14, 4
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Allocating & copying memory DONE! Time taken:"
.size .L.str.15, 46
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Failed to launch matchedFilterKernel (error code %s)!\n"
.size .L.str.16, 56
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Failed to copy deviceCellMF from device to host (error code %s)!\n"
.size .L.str.18, 66
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Copying memory back DONE! Time taken:"
.size .L.str.19, 38
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Hi! \n"
.size .L.str.20, 6
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "DONE! Time taken:"
.size .L.str.21, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Copy input data from the host memory to the CUDA device"
.size .Lstr, 56
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Copy output data from the CUDA device to the host memory"
.size .Lstr.1, 57
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__matchedFilterKernelPfS_PN6thrust7complexIfEEiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19matchedFilterKernelPfS_PN6thrust7complexIfEEiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <fstream>
#include <iomanip>
#include <iostream>
#include <cstdio>
cudaEvent_t start, stop;
float elapsedTime = 0.0;
constexpr int N = 1000;
constexpr int BlkNum = 100;
__global__ void dot(double *a, double *b, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = 0;
for (int k = 0; k < N; k++)
c[i] += a[i * N + k] * b[k];
}
int main()
{
std::ios::sync_with_stdio(false);
std::ifstream in("in.txt");
if (!in)
{
std::cerr << "Err: input\n";
return -2;
}
auto a = new double[N * N], b = new double[N], res = new double[N];
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
in >> a[i * N + j];
for (int i = 0; i < N; i++)
in >> b[i];
in.close();
double *a1, *b1, *res1;
cudaMalloc(&a1, sizeof(double) * N * N);
cudaMemcpy(a1, a, sizeof(double) * N * N, cudaMemcpyHostToDevice);
cudaMalloc(&b1, sizeof(double) * N);
cudaMemcpy(b1, b, sizeof(double) * N, cudaMemcpyHostToDevice);
cudaMalloc(&res1, sizeof(double) * N);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
dot<<<BlkNum, N / BlkNum>>>(a1, b1, res1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(res, res1, sizeof(double) * N, cudaMemcpyDeviceToHost);
std::cout << "Running Time: " << elapsedTime << "s" << std::endl;
std::ofstream out("out.txt");
if (!out)
{
std::cerr << "Err: output\n";
return -1;
}
for (int i = 0; i < N; i++)
out << std::setprecision(15) << res[i] << "\n";
out.close();
free(a);
free(b);
free(res);
cudaFree(a1);
cudaFree(b1);
cudaFree(res1);
return 0;
} | code for sm_80
Function : _Z3dotPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*0070*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD R4, R0, 0x3e8, RZ ; /* 0x000003e800047824 */
/* 0x000fe200078e02ff */
/*00b0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101b04 */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00e0*/ IADD3 R10, P0, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fca0007f1e0ff */
/*00f0*/ IMAD.X R11, RZ, RZ, R5, P0 ; /* 0x000000ffff0b7224 */
/* 0x001fc600000e0605 */
/*0100*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*0120*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea8000c1e1b00 */
/*0130*/ LDG.E.64 R12, [R4.64+-0x20] ; /* 0xffffe004040c7981 */
/* 0x002ea4000c1e1b00 */
/*0140*/ DFMA R10, R10, R12, R8 ; /* 0x0000000c0a0a722b */
/* 0x004e0e0000000008 */
/*0150*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0160*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080406087981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ LDG.E.64 R12, [R4.64+-0x18] ; /* 0xffffe804040c7981 */
/* 0x000ea4000c1e1b00 */
/*0180*/ DFMA R8, R8, R12, R10 ; /* 0x0000000c0808722b */
/* 0x004e4e000000000a */
/*0190*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*01a0*/ LDG.E.64 R12, [R6.64+0x10] ; /* 0x00001004060c7981 */
/* 0x000ea8000c1e1b00 */
/*01b0*/ LDG.E.64 R14, [R4.64+-0x10] ; /* 0xfffff004040e7981 */
/* 0x000ea4000c1e1b00 */
/*01c0*/ DFMA R12, R12, R14, R8 ; /* 0x0000000e0c0c722b */
/* 0x004e8e0000000008 */
/*01d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*01e0*/ LDG.E.64 R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ee8000c1e1b00 */
/*01f0*/ LDG.E.64 R16, [R4.64+-0x8] ; /* 0xfffff80404107981 */
/* 0x000ee4000c1e1b00 */
/*0200*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0210*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0220*/ LDG.E.64 R10, [R6.64+0x20] ; /* 0x00002004060a7981 */
/* 0x001f28000c1e1b00 */
/*0230*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000f24000c1e1b00 */
/*0240*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0250*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0260*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x002f28000c1e1b00 */
/*0270*/ LDG.E.64 R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000f24000c1e1b00 */
/*0280*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0290*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*02a0*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x004ea8000c1e1b00 */
/*02b0*/ LDG.E.64 R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea4000c1e1b00 */
/*02c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*02d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*02e0*/ LDG.E.64 R14, [R6.64+0x38] ; /* 0x00003804060e7981 */
/* 0x008ee8000c1e1b00 */
/*02f0*/ LDG.E.64 R16, [R4.64+0x18] ; /* 0x0000180404107981 */
/* 0x000ee4000c1e1b00 */
/*0300*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0310*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0320*/ LDG.E.64 R10, [R6.64+0x40] ; /* 0x00004004060a7981 */
/* 0x001f28000c1e1b00 */
/*0330*/ LDG.E.64 R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000f24000c1e1b00 */
/*0340*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0350*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0360*/ LDG.E.64 R8, [R6.64+0x48] ; /* 0x0000480406087981 */
/* 0x002f28000c1e1b00 */
/*0370*/ LDG.E.64 R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000f24000c1e1b00 */
/*0380*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0390*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*03a0*/ LDG.E.64 R12, [R6.64+0x50] ; /* 0x00005004060c7981 */
/* 0x004ea8000c1e1b00 */
/*03b0*/ LDG.E.64 R16, [R4.64+0x30] ; /* 0x0000300404107981 */
/* 0x000ea4000c1e1b00 */
/*03c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*03d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*03e0*/ LDG.E.64 R14, [R6.64+0x58] ; /* 0x00005804060e7981 */
/* 0x008ee8000c1e1b00 */
/*03f0*/ LDG.E.64 R16, [R4.64+0x38] ; /* 0x0000380404107981 */
/* 0x000ee4000c1e1b00 */
/*0400*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0410*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0420*/ LDG.E.64 R10, [R6.64+0x60] ; /* 0x00006004060a7981 */
/* 0x001f28000c1e1b00 */
/*0430*/ LDG.E.64 R16, [R4.64+0x40] ; /* 0x0000400404107981 */
/* 0x000f24000c1e1b00 */
/*0440*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0450*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0460*/ LDG.E.64 R8, [R6.64+0x68] ; /* 0x0000680406087981 */
/* 0x002f28000c1e1b00 */
/*0470*/ LDG.E.64 R16, [R4.64+0x48] ; /* 0x0000480404107981 */
/* 0x000f24000c1e1b00 */
/*0480*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0490*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*04a0*/ LDG.E.64 R12, [R6.64+0x70] ; /* 0x00007004060c7981 */
/* 0x004ea8000c1e1b00 */
/*04b0*/ LDG.E.64 R16, [R4.64+0x50] ; /* 0x0000500404107981 */
/* 0x000ea4000c1e1b00 */
/*04c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*04d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*04e0*/ LDG.E.64 R14, [R6.64+0x78] ; /* 0x00007804060e7981 */
/* 0x008ee8000c1e1b00 */
/*04f0*/ LDG.E.64 R16, [R4.64+0x58] ; /* 0x0000580404107981 */
/* 0x000ee4000c1e1b00 */
/*0500*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0510*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0520*/ LDG.E.64 R10, [R6.64+0x80] ; /* 0x00008004060a7981 */
/* 0x001f28000c1e1b00 */
/*0530*/ LDG.E.64 R16, [R4.64+0x60] ; /* 0x0000600404107981 */
/* 0x000f24000c1e1b00 */
/*0540*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0550*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0560*/ LDG.E.64 R8, [R6.64+0x88] ; /* 0x0000880406087981 */
/* 0x002f28000c1e1b00 */
/*0570*/ LDG.E.64 R16, [R4.64+0x68] ; /* 0x0000680404107981 */
/* 0x000f24000c1e1b00 */
/*0580*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0590*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*05a0*/ LDG.E.64 R12, [R6.64+0x90] ; /* 0x00009004060c7981 */
/* 0x004ea8000c1e1b00 */
/*05b0*/ LDG.E.64 R16, [R4.64+0x70] ; /* 0x0000700404107981 */
/* 0x000ea4000c1e1b00 */
/*05c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*05d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*05e0*/ LDG.E.64 R14, [R6.64+0x98] ; /* 0x00009804060e7981 */
/* 0x008ee8000c1e1b00 */
/*05f0*/ LDG.E.64 R16, [R4.64+0x78] ; /* 0x0000780404107981 */
/* 0x000ee4000c1e1b00 */
/*0600*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0610*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0620*/ LDG.E.64 R10, [R6.64+0xa0] ; /* 0x0000a004060a7981 */
/* 0x001f28000c1e1b00 */
/*0630*/ LDG.E.64 R16, [R4.64+0x80] ; /* 0x0000800404107981 */
/* 0x000f24000c1e1b00 */
/*0640*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0650*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0660*/ LDG.E.64 R8, [R6.64+0xa8] ; /* 0x0000a80406087981 */
/* 0x002f28000c1e1b00 */
/*0670*/ LDG.E.64 R16, [R4.64+0x88] ; /* 0x0000880404107981 */
/* 0x000f24000c1e1b00 */
/*0680*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0690*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*06a0*/ LDG.E.64 R12, [R6.64+0xb0] ; /* 0x0000b004060c7981 */
/* 0x004ea8000c1e1b00 */
/*06b0*/ LDG.E.64 R16, [R4.64+0x90] ; /* 0x0000900404107981 */
/* 0x000ea4000c1e1b00 */
/*06c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*06d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*06e0*/ LDG.E.64 R14, [R6.64+0xb8] ; /* 0x0000b804060e7981 */
/* 0x008ee8000c1e1b00 */
/*06f0*/ LDG.E.64 R16, [R4.64+0x98] ; /* 0x0000980404107981 */
/* 0x000ee4000c1e1b00 */
/*0700*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0710*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0720*/ LDG.E.64 R10, [R6.64+0xc0] ; /* 0x0000c004060a7981 */
/* 0x001f28000c1e1b00 */
/*0730*/ LDG.E.64 R16, [R4.64+0xa0] ; /* 0x0000a00404107981 */
/* 0x000f24000c1e1b00 */
/*0740*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0750*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0760*/ LDG.E.64 R8, [R6.64+0xc8] ; /* 0x0000c80406087981 */
/* 0x002f28000c1e1b00 */
/*0770*/ LDG.E.64 R16, [R4.64+0xa8] ; /* 0x0000a80404107981 */
/* 0x000f24000c1e1b00 */
/*0780*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0790*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*07a0*/ LDG.E.64 R12, [R6.64+0xd0] ; /* 0x0000d004060c7981 */
/* 0x004ea8000c1e1b00 */
/*07b0*/ LDG.E.64 R16, [R4.64+0xb0] ; /* 0x0000b00404107981 */
/* 0x000ea4000c1e1b00 */
/*07c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*07d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*07e0*/ LDG.E.64 R14, [R6.64+0xd8] ; /* 0x0000d804060e7981 */
/* 0x008ee8000c1e1b00 */
/*07f0*/ LDG.E.64 R16, [R4.64+0xb8] ; /* 0x0000b80404107981 */
/* 0x000ee4000c1e1b00 */
/*0800*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0810*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0820*/ LDG.E.64 R10, [R6.64+0xe0] ; /* 0x0000e004060a7981 */
/* 0x001f28000c1e1b00 */
/*0830*/ LDG.E.64 R16, [R4.64+0xc0] ; /* 0x0000c00404107981 */
/* 0x000f24000c1e1b00 */
/*0840*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0850*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0860*/ LDG.E.64 R8, [R6.64+0xe8] ; /* 0x0000e80406087981 */
/* 0x002f28000c1e1b00 */
/*0870*/ LDG.E.64 R16, [R4.64+0xc8] ; /* 0x0000c80404107981 */
/* 0x000f24000c1e1b00 */
/*0880*/ DFMA R16, R8, R16, R10 ; /* 0x000000100810722b */
/* 0x010e4e000000000a */
/*0890*/ STG.E.64 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x002fe8000c101b04 */
/*08a0*/ LDG.E.64 R8, [R6.64+0xf0] ; /* 0x0000f00406087981 */
/* 0x000ee8000c1e1b00 */
/*08b0*/ LDG.E.64 R12, [R4.64+0xd0] ; /* 0x0000d004040c7981 */
/* 0x004ee4000c1e1b00 */
/*08c0*/ DFMA R14, R8, R12, R16 ; /* 0x0000000c080e722b */
/* 0x008e4e0000000010 */
/*08d0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0023e8000c101b04 */
/*08e0*/ LDG.E.64 R8, [R6.64+0xf8] ; /* 0x0000f80406087981 */
/* 0x000ea8000c1e1b00 */
/*08f0*/ LDG.E.64 R12, [R4.64+0xd8] ; /* 0x0000d804040c7981 */
/* 0x000ea4000c1e1b00 */
/*0900*/ DFMA R18, R8, R12, R14 ; /* 0x0000000c0812722b */
/* 0x004e8e000000000e */
/*0910*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x004fe8000c101b04 */
/*0920*/ LDG.E.64 R8, [R6.64+0x100] ; /* 0x0001000406087981 */
/* 0x000ea8000c1e1b00 */
/*0930*/ LDG.E.64 R10, [R4.64+0xe0] ; /* 0x0000e004040a7981 */
/* 0x001ea4000c1e1b00 */
/*0940*/ DFMA R8, R8, R10, R18 ; /* 0x0000000a0808722b */
/* 0x004e0e0000000012 */
/*0950*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0011e8000c101b04 */
/*0960*/ LDG.E.64 R10, [R6.64+0x108] ; /* 0x00010804060a7981 */
/* 0x000ea8000c1e1b00 */
/*0970*/ LDG.E.64 R12, [R4.64+0xe8] ; /* 0x0000e804040c7981 */
/* 0x000ea4000c1e1b00 */
/*0980*/ DFMA R10, R10, R12, R8 ; /* 0x0000000c0a0a722b */
/* 0x004e8e0000000008 */
/*0990*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*09a0*/ LDG.E.64 R12, [R6.64+0x110] ; /* 0x00011004060c7981 */
/* 0x000ee8000c1e1b00 */
/*09b0*/ LDG.E.64 R14, [R4.64+0xf0] ; /* 0x0000f004040e7981 */
/* 0x002ee4000c1e1b00 */
/*09c0*/ DFMA R12, R12, R14, R10 ; /* 0x0000000e0c0c722b */
/* 0x008e4e000000000a */
/*09d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b04 */
/*09e0*/ LDG.E.64 R14, [R6.64+0x118] ; /* 0x00011804060e7981 */
/* 0x000ee8000c1e1b00 */
/*09f0*/ LDG.E.64 R16, [R4.64+0xf8] ; /* 0x0000f80404107981 */
/* 0x000ee4000c1e1b00 */
/*0a00*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0a10*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0a20*/ LDG.E.64 R8, [R6.64+0x120] ; /* 0x0001200406087981 */
/* 0x001f28000c1e1b00 */
/*0a30*/ LDG.E.64 R16, [R4.64+0x100] ; /* 0x0001000404107981 */
/* 0x000f24000c1e1b00 */
/*0a40*/ DFMA R8, R8, R16, R14 ; /* 0x000000100808722b */
/* 0x010e0e000000000e */
/*0a50*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x001fe8000c101b04 */
/*0a60*/ LDG.E.64 R10, [R6.64+0x128] ; /* 0x00012804060a7981 */
/* 0x004ea8000c1e1b00 */
/*0a70*/ LDG.E.64 R16, [R4.64+0x108] ; /* 0x0001080404107981 */
/* 0x000ea4000c1e1b00 */
/*0a80*/ DFMA R10, R10, R16, R8 ; /* 0x000000100a0a722b */
/* 0x004e0e0000000008 */
/*0a90*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0aa0*/ LDG.E.64 R12, [R6.64+0x130] ; /* 0x00013004060c7981 */
/* 0x002ea8000c1e1b00 */
/*0ab0*/ LDG.E.64 R16, [R4.64+0x110] ; /* 0x0001100404107981 */
/* 0x000ea2000c1e1b00 */
/*0ac0*/ IADD3 R0, R0, 0x28, RZ ; /* 0x0000002800007810 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ DFMA R12, R12, R16, R10 ; /* 0x000000100c0c722b */
/* 0x004e4e000000000a */
/*0ae0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b04 */
/*0af0*/ LDG.E.64 R14, [R6.64+0x138] ; /* 0x00013804060e7981 */
/* 0x0084e8000c1e1b00 */
/*0b00*/ LDG.E.64 R16, [R4.64+0x118] ; /* 0x0001180404107981 */
/* 0x000ee2000c1e1b00 */
/*0b10*/ ISETP.NE.AND P0, PT, R0, 0x3e8, PT ; /* 0x000003e80000780c */
/* 0x000fe40003f05270 */
/*0b20*/ IADD3 R10, P1, R4, 0x140, RZ ; /* 0x00000140040a7810 */
/* 0x001fc40007f3e0ff */
/*0b30*/ IADD3 R6, P2, R6, 0x140, RZ ; /* 0x0000014006067810 */
/* 0x004fe40007f5e0ff */
/*0b40*/ IADD3.X R11, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0b7210 */
/* 0x000fe40000ffe4ff */
/*0b50*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe200017fe4ff */
/*0b60*/ DFMA R8, R14, R16, R12 ; /* 0x000000100e08722b */
/* 0x008e0e000000000c */
/*0b70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0013e2000c101b04 */
/*0b80*/ @P0 BRA 0x100 ; /* 0xfffff57000000947 */
/* 0x000fea000383ffff */
/*0b90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <fstream>
#include <iomanip>
#include <iostream>
#include <cstdio>
cudaEvent_t start, stop;
float elapsedTime = 0.0;
constexpr int N = 1000;
constexpr int BlkNum = 100;
__global__ void dot(double *a, double *b, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = 0;
for (int k = 0; k < N; k++)
c[i] += a[i * N + k] * b[k];
}
int main()
{
std::ios::sync_with_stdio(false);
std::ifstream in("in.txt");
if (!in)
{
std::cerr << "Err: input\n";
return -2;
}
auto a = new double[N * N], b = new double[N], res = new double[N];
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
in >> a[i * N + j];
for (int i = 0; i < N; i++)
in >> b[i];
in.close();
double *a1, *b1, *res1;
cudaMalloc(&a1, sizeof(double) * N * N);
cudaMemcpy(a1, a, sizeof(double) * N * N, cudaMemcpyHostToDevice);
cudaMalloc(&b1, sizeof(double) * N);
cudaMemcpy(b1, b, sizeof(double) * N, cudaMemcpyHostToDevice);
cudaMalloc(&res1, sizeof(double) * N);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
dot<<<BlkNum, N / BlkNum>>>(a1, b1, res1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(res, res1, sizeof(double) * N, cudaMemcpyDeviceToHost);
std::cout << "Running Time: " << elapsedTime << "s" << std::endl;
std::ofstream out("out.txt");
if (!out)
{
std::cerr << "Err: output\n";
return -1;
}
for (int i = 0; i < N; i++)
out << std::setprecision(15) << res[i] << "\n";
out.close();
free(a);
free(b);
free(res);
cudaFree(a1);
cudaFree(b1);
cudaFree(res1);
return 0;
} | .file "tmpxft_001759bd_00000000-6_dotvec.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPdS_S_PdS_S_
.type _Z26__device_stub__Z3dotPdS_S_PdS_S_, @function
_Z26__device_stub__Z3dotPdS_S_PdS_S_:
.LFB4064:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4064:
.size _Z26__device_stub__Z3dotPdS_S_PdS_S_, .-_Z26__device_stub__Z3dotPdS_S_PdS_S_
.globl _Z3dotPdS_S_
.type _Z3dotPdS_S_, @function
_Z3dotPdS_S_:
.LFB4065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4065:
.size _Z3dotPdS_S_, .-_Z3dotPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3dotPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "in.txt"
.LC2:
.string "Err: input\n"
.LC3:
.string "Running Time: "
.LC4:
.string "s"
.LC5:
.string "out.txt"
.LC6:
.string "Err: output\n"
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB4039:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4039
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
movl $0, %edi
.LEHB0:
call _ZNSt8ios_base15sync_with_stdioEb@PLT
leaq 576(%rsp), %rdi
movl $8, %edx
leaq .LC1(%rip), %rsi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
testb $5, 864(%rsp)
jne .L40
movl $8000000, %edi
.LEHB1:
call _Znam@PLT
jmp .L41
.L40:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L42
.L41:
movq %rax, %r15
movl $8000, %edi
call _Znam@PLT
movq %rax, %r14
movl $8000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
leaq 8000(%r15), %rbp
leaq 8008000(%r15), %r13
leaq 576(%rsp), %r12
jmp .L16
.L44:
addq $8, %rbx
cmpq %rbp, %rbx
je .L43
.L17:
movq %rbx, %rsi
movq %r12, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
jmp .L44
.L43:
addq $8000, %rbp
cmpq %r13, %rbp
je .L18
.L16:
leaq -8000(%rbp), %rbx
jmp .L17
.L18:
movq %r14, %rbx
leaq 8000(%r14), %rbp
leaq 576(%rsp), %r12
jmp .L19
.L46:
addq $8, %rbx
cmpq %rbp, %rbx
je .L45
.L19:
movq %rbx, %rsi
movq %r12, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
jmp .L46
.L45:
leaq 576(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq 16(%rsp), %rdi
movl $8000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000000, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq start(%rip), %rdi
call cudaEventCreate@PLT
leaq stop(%rip), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq start(%rip), %rdi
call cudaEventRecord@PLT
movl $10, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $100, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z3dotPdS_S_PdS_S_
.L20:
movl $0, %esi
movq stop(%rip), %rdi
call cudaEventRecord@PLT
movq stop(%rip), %rdi
call cudaEventSynchronize@PLT
movq stop(%rip), %rdx
movq start(%rip), %rsi
leaq elapsedTime(%rip), %rdi
call cudaEventElapsedTime@PLT
movq start(%rip), %rdi
call cudaEventDestroy@PLT
movq stop(%rip), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $8000, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd elapsedTime(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 64(%rsp), %rdi
movl $16, %edx
leaq .LC5(%rip), %rsi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
leaq 8000(%rbx), %rbp
leaq .LC7(%rip), %r12
movl 344(%rsp), %r13d
andl $5, %r13d
je .L23
leaq .LC6(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L47
.L49:
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rbx
cmpq %rbp, %rbx
je .L48
.L23:
movq 64(%rsp), %rax
movq -24(%rax), %rax
movq $15, 72(%rsp,%rax)
movsd (%rbx), %xmm0
leaq 64(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L49
.L48:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE2:
jmp .L22
.L47:
movl $-1, %r13d
.L22:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L15:
leaq 576(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl %r13d, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl $-2, %r13d
jmp .L15
.L31:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L25:
leaq 576(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
je .L26
call __stack_chk_fail@PLT
.L30:
endbr64
movq %rax, %rbx
jmp .L25
.L26:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4039:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4039-.LLSDACSB4039
.LLSDACSB4039:
.uleb128 .LEHB0-.LFB4039
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4039
.uleb128 .LEHE1-.LEHB1
.uleb128 .L30-.LFB4039
.uleb128 0
.uleb128 .LEHB2-.LFB4039
.uleb128 .LEHE2-.LEHB2
.uleb128 .L31-.LFB4039
.uleb128 0
.uleb128 .LEHB3-.LFB4039
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4039:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl elapsedTime
.bss
.align 4
.type elapsedTime, @object
.size elapsedTime, 4
elapsedTime:
.zero 4
.globl stop
.align 8
.type stop, @object
.size stop, 8
stop:
.zero 8
.globl start
.align 8
.type start, @object
.size start, 8
start:
.zero 8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <fstream>
#include <iomanip>
#include <iostream>
#include <cstdio>
cudaEvent_t start, stop;
float elapsedTime = 0.0;
constexpr int N = 1000;
constexpr int BlkNum = 100;
__global__ void dot(double *a, double *b, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = 0;
for (int k = 0; k < N; k++)
c[i] += a[i * N + k] * b[k];
}
int main()
{
std::ios::sync_with_stdio(false);
std::ifstream in("in.txt");
if (!in)
{
std::cerr << "Err: input\n";
return -2;
}
auto a = new double[N * N], b = new double[N], res = new double[N];
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
in >> a[i * N + j];
for (int i = 0; i < N; i++)
in >> b[i];
in.close();
double *a1, *b1, *res1;
cudaMalloc(&a1, sizeof(double) * N * N);
cudaMemcpy(a1, a, sizeof(double) * N * N, cudaMemcpyHostToDevice);
cudaMalloc(&b1, sizeof(double) * N);
cudaMemcpy(b1, b, sizeof(double) * N, cudaMemcpyHostToDevice);
cudaMalloc(&res1, sizeof(double) * N);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
dot<<<BlkNum, N / BlkNum>>>(a1, b1, res1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(res, res1, sizeof(double) * N, cudaMemcpyDeviceToHost);
std::cout << "Running Time: " << elapsedTime << "s" << std::endl;
std::ofstream out("out.txt");
if (!out)
{
std::cerr << "Err: output\n";
return -1;
}
for (int i = 0; i < N; i++)
out << std::setprecision(15) << res[i] << "\n";
out.close();
free(a);
free(b);
free(res);
cudaFree(a1);
cudaFree(b1);
cudaFree(res1);
return 0;
} | #include <hip/hip_runtime.h>
#include <fstream>
#include <iomanip>
#include <iostream>
#include <cstdio>
hipEvent_t start, stop;
float elapsedTime = 0.0;
constexpr int N = 1000;
constexpr int BlkNum = 100;
__global__ void dot(double *a, double *b, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = 0;
for (int k = 0; k < N; k++)
c[i] += a[i * N + k] * b[k];
}
int main()
{
std::ios::sync_with_stdio(false);
std::ifstream in("in.txt");
if (!in)
{
std::cerr << "Err: input\n";
return -2;
}
auto a = new double[N * N], b = new double[N], res = new double[N];
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
in >> a[i * N + j];
for (int i = 0; i < N; i++)
in >> b[i];
in.close();
double *a1, *b1, *res1;
hipMalloc(&a1, sizeof(double) * N * N);
hipMemcpy(a1, a, sizeof(double) * N * N, hipMemcpyHostToDevice);
hipMalloc(&b1, sizeof(double) * N);
hipMemcpy(b1, b, sizeof(double) * N, hipMemcpyHostToDevice);
hipMalloc(&res1, sizeof(double) * N);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
dot<<<BlkNum, N / BlkNum>>>(a1, b1, res1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(res, res1, sizeof(double) * N, hipMemcpyDeviceToHost);
std::cout << "Running Time: " << elapsedTime << "s" << std::endl;
std::ofstream out("out.txt");
if (!out)
{
std::cerr << "Err: output\n";
return -1;
}
for (int i = 0; i < N; i++)
out << std::setprecision(15) << res[i] << "\n";
out.close();
free(a);
free(b);
free(res);
hipFree(a1);
hipFree(b1);
hipFree(res1);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <fstream>
#include <iomanip>
#include <iostream>
#include <cstdio>
hipEvent_t start, stop;
float elapsedTime = 0.0;
constexpr int N = 1000;
constexpr int BlkNum = 100;
__global__ void dot(double *a, double *b, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = 0;
for (int k = 0; k < N; k++)
c[i] += a[i * N + k] * b[k];
}
int main()
{
std::ios::sync_with_stdio(false);
std::ifstream in("in.txt");
if (!in)
{
std::cerr << "Err: input\n";
return -2;
}
auto a = new double[N * N], b = new double[N], res = new double[N];
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
in >> a[i * N + j];
for (int i = 0; i < N; i++)
in >> b[i];
in.close();
double *a1, *b1, *res1;
hipMalloc(&a1, sizeof(double) * N * N);
hipMemcpy(a1, a, sizeof(double) * N * N, hipMemcpyHostToDevice);
hipMalloc(&b1, sizeof(double) * N);
hipMemcpy(b1, b, sizeof(double) * N, hipMemcpyHostToDevice);
hipMalloc(&res1, sizeof(double) * N);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
dot<<<BlkNum, N / BlkNum>>>(a1, b1, res1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(res, res1, sizeof(double) * N, hipMemcpyDeviceToHost);
std::cout << "Running Time: " << elapsedTime << "s" << std::endl;
std::ofstream out("out.txt");
if (!out)
{
std::cerr << "Err: output\n";
return -1;
}
for (int i = 0; i < N; i++)
out << std::setprecision(15) << res[i] << "\n";
out.close();
free(a);
free(b);
free(res);
hipFree(a1);
hipFree(b1);
hipFree(res1);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPdS_S_
.globl _Z3dotPdS_S_
.p2align 8
.type _Z3dotPdS_S_,@function
_Z3dotPdS_S_:
s_load_b32 s2, s[0:1], 0x24
v_mov_b32_e32 v7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v3, v1, 0x3e8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v4, 31, v3
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v8, v7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v5
v_lshlrev_b64 v[9:10], 3, v[3:4]
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v10, vcc_lo
s_mov_b64 s[0:1], 0
global_store_b64 v[2:3], v[7:8], off
.p2align 6
.LBB0_1:
v_add_co_u32 v7, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v5, vcc_lo
s_add_u32 s4, s2, s0
s_addc_u32 s5, s3, s1
global_load_b64 v[9:10], v6, s[4:5]
global_load_b64 v[7:8], v[7:8], off
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s0, 0x1f40
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], v[7:8], v[9:10], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPdS_S_, .Lfunc_end0-_Z3dotPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <fstream>
#include <iomanip>
#include <iostream>
#include <cstdio>
hipEvent_t start, stop;
float elapsedTime = 0.0;
constexpr int N = 1000;
constexpr int BlkNum = 100;
__global__ void dot(double *a, double *b, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = 0;
for (int k = 0; k < N; k++)
c[i] += a[i * N + k] * b[k];
}
int main()
{
std::ios::sync_with_stdio(false);
std::ifstream in("in.txt");
if (!in)
{
std::cerr << "Err: input\n";
return -2;
}
auto a = new double[N * N], b = new double[N], res = new double[N];
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
in >> a[i * N + j];
for (int i = 0; i < N; i++)
in >> b[i];
in.close();
double *a1, *b1, *res1;
hipMalloc(&a1, sizeof(double) * N * N);
hipMemcpy(a1, a, sizeof(double) * N * N, hipMemcpyHostToDevice);
hipMalloc(&b1, sizeof(double) * N);
hipMemcpy(b1, b, sizeof(double) * N, hipMemcpyHostToDevice);
hipMalloc(&res1, sizeof(double) * N);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
dot<<<BlkNum, N / BlkNum>>>(a1, b1, res1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(res, res1, sizeof(double) * N, hipMemcpyDeviceToHost);
std::cout << "Running Time: " << elapsedTime << "s" << std::endl;
std::ofstream out("out.txt");
if (!out)
{
std::cerr << "Err: output\n";
return -1;
}
for (int i = 0; i < N; i++)
out << std::setprecision(15) << res[i] << "\n";
out.close();
free(a);
free(b);
free(res);
hipFree(a1);
hipFree(b1);
hipFree(res1);
return 0;
} | .text
.file "dotvec.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__dotPdS_S_ # -- Begin function _Z18__device_stub__dotPdS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPdS_S_,@function
_Z18__device_stub__dotPdS_S_: # @_Z18__device_stub__dotPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPdS_S_, .Lfunc_end0-_Z18__device_stub__dotPdS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1144, %rsp # imm = 0x478
.cfi_def_cfa_offset 1200
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq _ZNSt8ios_base15sync_with_stdioEb
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
movl $.L.str, %esi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
movq 624(%rsp), %rax
movq -24(%rax), %rax
testb $5, 656(%rsp,%rax)
je .LBB1_3
# %bb.1:
movl $-2, %ebx
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
jmp .LBB1_2
.LBB1_3:
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $8000000, %edi # imm = 0x7A1200
callq _Znam
.Ltmp4:
# %bb.4:
.Ltmp6:
movq %rax, %rbp
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znam
.Ltmp7:
# %bb.5:
.Ltmp9:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znam
.Ltmp10:
# %bb.6: # %.preheader83.preheader
movq %rax, %r15
xorl %r13d, %r13d
leaq 624(%rsp), %r12
movq %rbp, 32(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_7: # %.preheader83
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%rbx,%rbp), %rsi
.Ltmp11:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSi10_M_extractIdEERSiRT_
.Ltmp12:
# %bb.9: # %_ZNSirsERd.exit
# in Loop: Header=BB1_8 Depth=2
addq $8, %rbx
cmpq $8000, %rbx # imm = 0x1F40
jne .LBB1_8
# %bb.10: # in Loop: Header=BB1_7 Depth=1
incq %r13
addq $8000, %rbp # imm = 0x1F40
cmpq $1000, %r13 # imm = 0x3E8
jne .LBB1_7
# %bb.11: # %.preheader82.preheader
xorl %r13d, %r13d
leaq 624(%rsp), %r12
.p2align 4, 0x90
.LBB1_12: # %.preheader82
# =>This Inner Loop Header: Depth=1
leaq (%r14,%r13), %rsi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSi10_M_extractIdEERSiRT_
.Ltmp15:
# %bb.13: # %_ZNSirsERd.exit50
# in Loop: Header=BB1_12 Depth=1
addq $8, %r13
cmpq $8000, %r13 # imm = 0x1F40
jne .LBB1_12
# %bb.14:
leaq 640(%rsp), %rdi
.Ltmp17:
.cfi_escape 0x2e, 0x00
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp18:
movq 32(%rsp), %rbx # 8-byte Reload
# %bb.15: # %.noexc
testq %rax, %rax
jne .LBB1_17
# %bb.16:
movq 624(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $624, %rdi # imm = 0x270
movl 656(%rsp,%rax), %esi
orl $4, %esi
.Ltmp19:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp20:
.LBB1_17: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
callq hipMalloc
.Ltmp23:
# %bb.18: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit
movq 24(%rsp), %rdi
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $8000000, %edx # imm = 0x7A1200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp25:
# %bb.19:
.Ltmp26:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp27:
# %bb.20: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit53
movq 16(%rsp), %rdi
.Ltmp28:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.21:
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp31:
# %bb.22: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit55
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $start, %edi
callq hipEventCreate
.Ltmp33:
# %bb.23:
.Ltmp34:
.cfi_escape 0x2e, 0x00
movl $stop, %edi
callq hipEventCreate
.Ltmp35:
# %bb.24:
movq start(%rip), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp37:
# %bb.25:
.Ltmp38:
.cfi_escape 0x2e, 0x00
movabsq $4294967396, %rdi # imm = 0x100000064
movabsq $4294967306, %rdx # imm = 0x10000000A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp39:
# %bb.26:
testl %eax, %eax
jne .LBB1_29
# %bb.27:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
.Ltmp40:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp41:
# %bb.28: # %.noexc56
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.Ltmp42:
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z3dotPdS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp43:
.LBB1_29:
movq stop(%rip), %rdi
.Ltmp44:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp45:
# %bb.30:
movq stop(%rip), %rdi
.Ltmp46:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp47:
# %bb.31:
movq start(%rip), %rsi
movq stop(%rip), %rdx
.Ltmp48:
.cfi_escape 0x2e, 0x00
movl $elapsedTime, %edi
callq hipEventElapsedTime
.Ltmp49:
# %bb.32:
movq start(%rip), %rdi
.Ltmp50:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp51:
# %bb.33:
movq stop(%rip), %rdi
.Ltmp52:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp53:
# %bb.34:
movq 8(%rsp), %rsi
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp55:
# %bb.35:
.Ltmp56:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp57:
# %bb.36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit59
movss elapsedTime(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp58:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp59:
# %bb.37: # %_ZNSolsEf.exit
.Ltmp60:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp61:
# %bb.38: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit62
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_39
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB1_47
# %bb.46:
movzbl 67(%r13), %eax
jmp .LBB1_49
.LBB1_47:
.Ltmp62:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp63:
# %bb.48: # %.noexc73
movq (%r13), %rax
.Ltmp64:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp65:
.LBB1_49: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp66:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp67:
# %bb.50: # %.noexc75
.Ltmp68:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp69:
# %bb.51: # %_ZNSolsEPFRSoS_E.exit
.Ltmp70:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
movl $.L.str.4, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp71:
# %bb.52:
movq 112(%rsp), %rax
movq -24(%rax), %rax
testb $5, 144(%rsp,%rax)
je .LBB1_53
# %bb.63:
movl $-1, %ebx
.Ltmp73:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp74:
jmp .LBB1_64
.LBB1_53: # %.preheader
xorl %r13d, %r13d
leaq 112(%rsp), %r12
.p2align 4, 0x90
.LBB1_54: # =>This Inner Loop Header: Depth=1
movq 112(%rsp), %rax
movq -24(%rax), %rax
movq $15, 120(%rsp,%rax)
movsd (%r15,%r13,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp75:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp76:
# %bb.55: # %_ZNSolsEd.exit
# in Loop: Header=BB1_54 Depth=1
.Ltmp77:
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp78:
# %bb.56: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit71
# in Loop: Header=BB1_54 Depth=1
incq %r13
cmpq $1000, %r13 # imm = 0x3E8
jne .LBB1_54
# %bb.57:
leaq 120(%rsp), %rdi
.Ltmp80:
.cfi_escape 0x2e, 0x00
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp81:
# %bb.58: # %.noexc67
testq %rax, %rax
jne .LBB1_60
# %bb.59:
movq 112(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $112, %rdi
movl 144(%rsp,%rax), %esi
orl $4, %esi
.Ltmp82:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp83:
.LBB1_60: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq free
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
.Ltmp84:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp85:
# %bb.61:
movq 16(%rsp), %rdi
.Ltmp86:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp87:
# %bb.62:
xorl %ebx, %ebx
movq 8(%rsp), %rdi
.Ltmp88:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp89:
.LBB1_64: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit65
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB1_2: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 880(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
movl %ebx, %eax
addq $1144, %rsp # imm = 0x478
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_39:
.cfi_def_cfa_offset 1200
.Ltmp91:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp92:
# %bb.44: # %.noexc72
.LBB1_65:
.Ltmp72:
jmp .LBB1_69
.LBB1_41:
.Ltmp8:
jmp .LBB1_69
.LBB1_40:
.Ltmp5:
jmp .LBB1_69
.LBB1_68:
.Ltmp2:
jmp .LBB1_69
.LBB1_66:
.Ltmp90:
jmp .LBB1_67
.LBB1_42:
.Ltmp21:
jmp .LBB1_69
.LBB1_72:
.Ltmp93:
jmp .LBB1_69
.LBB1_73:
.Ltmp79:
.LBB1_67:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
jmp .LBB1_70
.LBB1_71:
.Ltmp16:
jmp .LBB1_69
.LBB1_43:
.Ltmp13:
.LBB1_69:
movq %rax, %rbx
.LBB1_70:
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 880(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp20-.Ltmp17 # Call between .Ltmp17 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp69-.Ltmp22 # Call between .Ltmp22 and .Ltmp69
.uleb128 .Ltmp93-.Lfunc_begin0 # jumps to .Ltmp93
.byte 0 # On action: cleanup
.uleb128 .Ltmp70-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp71-.Ltmp70 # Call between .Ltmp70 and .Ltmp71
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp74-.Ltmp73 # Call between .Ltmp73 and .Ltmp74
.uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90
.byte 0 # On action: cleanup
.uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp78-.Ltmp75 # Call between .Ltmp75 and .Ltmp78
.uleb128 .Ltmp79-.Lfunc_begin0 # jumps to .Ltmp79
.byte 0 # On action: cleanup
.uleb128 .Ltmp80-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp89-.Ltmp80 # Call between .Ltmp80 and .Ltmp89
.uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90
.byte 0 # On action: cleanup
.uleb128 .Ltmp91-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp92-.Ltmp91 # Call between .Ltmp91 and .Ltmp92
.uleb128 .Ltmp93-.Lfunc_begin0 # jumps to .Ltmp93
.byte 0 # On action: cleanup
.uleb128 .Ltmp92-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Lfunc_end1-.Ltmp92 # Call between .Ltmp92 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.quad 0
.size start, 8
.type stop,@object # @stop
.globl stop
.p2align 3, 0x0
stop:
.quad 0
.size stop, 8
.type elapsedTime,@object # @elapsedTime
.globl elapsedTime
.p2align 2, 0x0
elapsedTime:
.long 0x00000000 # float 0
.size elapsedTime, 4
.type _Z3dotPdS_S_,@object # @_Z3dotPdS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPdS_S_
.p2align 3, 0x0
_Z3dotPdS_S_:
.quad _Z18__device_stub__dotPdS_S_
.size _Z3dotPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "in.txt"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Err: input\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Running Time: "
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "s"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "out.txt"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Err: output\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n"
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPdS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPdS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym start
.addrsig_sym stop
.addrsig_sym elapsedTime
.addrsig_sym _Z3dotPdS_S_
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3dotPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*0070*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD R4, R0, 0x3e8, RZ ; /* 0x000003e800047824 */
/* 0x000fe200078e02ff */
/*00b0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101b04 */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00e0*/ IADD3 R10, P0, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fca0007f1e0ff */
/*00f0*/ IMAD.X R11, RZ, RZ, R5, P0 ; /* 0x000000ffff0b7224 */
/* 0x001fc600000e0605 */
/*0100*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*0120*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea8000c1e1b00 */
/*0130*/ LDG.E.64 R12, [R4.64+-0x20] ; /* 0xffffe004040c7981 */
/* 0x002ea4000c1e1b00 */
/*0140*/ DFMA R10, R10, R12, R8 ; /* 0x0000000c0a0a722b */
/* 0x004e0e0000000008 */
/*0150*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0160*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080406087981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ LDG.E.64 R12, [R4.64+-0x18] ; /* 0xffffe804040c7981 */
/* 0x000ea4000c1e1b00 */
/*0180*/ DFMA R8, R8, R12, R10 ; /* 0x0000000c0808722b */
/* 0x004e4e000000000a */
/*0190*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*01a0*/ LDG.E.64 R12, [R6.64+0x10] ; /* 0x00001004060c7981 */
/* 0x000ea8000c1e1b00 */
/*01b0*/ LDG.E.64 R14, [R4.64+-0x10] ; /* 0xfffff004040e7981 */
/* 0x000ea4000c1e1b00 */
/*01c0*/ DFMA R12, R12, R14, R8 ; /* 0x0000000e0c0c722b */
/* 0x004e8e0000000008 */
/*01d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*01e0*/ LDG.E.64 R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ee8000c1e1b00 */
/*01f0*/ LDG.E.64 R16, [R4.64+-0x8] ; /* 0xfffff80404107981 */
/* 0x000ee4000c1e1b00 */
/*0200*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0210*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0220*/ LDG.E.64 R10, [R6.64+0x20] ; /* 0x00002004060a7981 */
/* 0x001f28000c1e1b00 */
/*0230*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000f24000c1e1b00 */
/*0240*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0250*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0260*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x002f28000c1e1b00 */
/*0270*/ LDG.E.64 R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000f24000c1e1b00 */
/*0280*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0290*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*02a0*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x004ea8000c1e1b00 */
/*02b0*/ LDG.E.64 R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea4000c1e1b00 */
/*02c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*02d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*02e0*/ LDG.E.64 R14, [R6.64+0x38] ; /* 0x00003804060e7981 */
/* 0x008ee8000c1e1b00 */
/*02f0*/ LDG.E.64 R16, [R4.64+0x18] ; /* 0x0000180404107981 */
/* 0x000ee4000c1e1b00 */
/*0300*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0310*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0320*/ LDG.E.64 R10, [R6.64+0x40] ; /* 0x00004004060a7981 */
/* 0x001f28000c1e1b00 */
/*0330*/ LDG.E.64 R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000f24000c1e1b00 */
/*0340*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0350*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0360*/ LDG.E.64 R8, [R6.64+0x48] ; /* 0x0000480406087981 */
/* 0x002f28000c1e1b00 */
/*0370*/ LDG.E.64 R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000f24000c1e1b00 */
/*0380*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0390*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*03a0*/ LDG.E.64 R12, [R6.64+0x50] ; /* 0x00005004060c7981 */
/* 0x004ea8000c1e1b00 */
/*03b0*/ LDG.E.64 R16, [R4.64+0x30] ; /* 0x0000300404107981 */
/* 0x000ea4000c1e1b00 */
/*03c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*03d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*03e0*/ LDG.E.64 R14, [R6.64+0x58] ; /* 0x00005804060e7981 */
/* 0x008ee8000c1e1b00 */
/*03f0*/ LDG.E.64 R16, [R4.64+0x38] ; /* 0x0000380404107981 */
/* 0x000ee4000c1e1b00 */
/*0400*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0410*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0420*/ LDG.E.64 R10, [R6.64+0x60] ; /* 0x00006004060a7981 */
/* 0x001f28000c1e1b00 */
/*0430*/ LDG.E.64 R16, [R4.64+0x40] ; /* 0x0000400404107981 */
/* 0x000f24000c1e1b00 */
/*0440*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0450*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0460*/ LDG.E.64 R8, [R6.64+0x68] ; /* 0x0000680406087981 */
/* 0x002f28000c1e1b00 */
/*0470*/ LDG.E.64 R16, [R4.64+0x48] ; /* 0x0000480404107981 */
/* 0x000f24000c1e1b00 */
/*0480*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0490*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*04a0*/ LDG.E.64 R12, [R6.64+0x70] ; /* 0x00007004060c7981 */
/* 0x004ea8000c1e1b00 */
/*04b0*/ LDG.E.64 R16, [R4.64+0x50] ; /* 0x0000500404107981 */
/* 0x000ea4000c1e1b00 */
/*04c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*04d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*04e0*/ LDG.E.64 R14, [R6.64+0x78] ; /* 0x00007804060e7981 */
/* 0x008ee8000c1e1b00 */
/*04f0*/ LDG.E.64 R16, [R4.64+0x58] ; /* 0x0000580404107981 */
/* 0x000ee4000c1e1b00 */
/*0500*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0510*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0520*/ LDG.E.64 R10, [R6.64+0x80] ; /* 0x00008004060a7981 */
/* 0x001f28000c1e1b00 */
/*0530*/ LDG.E.64 R16, [R4.64+0x60] ; /* 0x0000600404107981 */
/* 0x000f24000c1e1b00 */
/*0540*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0550*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0560*/ LDG.E.64 R8, [R6.64+0x88] ; /* 0x0000880406087981 */
/* 0x002f28000c1e1b00 */
/*0570*/ LDG.E.64 R16, [R4.64+0x68] ; /* 0x0000680404107981 */
/* 0x000f24000c1e1b00 */
/*0580*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0590*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*05a0*/ LDG.E.64 R12, [R6.64+0x90] ; /* 0x00009004060c7981 */
/* 0x004ea8000c1e1b00 */
/*05b0*/ LDG.E.64 R16, [R4.64+0x70] ; /* 0x0000700404107981 */
/* 0x000ea4000c1e1b00 */
/*05c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*05d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*05e0*/ LDG.E.64 R14, [R6.64+0x98] ; /* 0x00009804060e7981 */
/* 0x008ee8000c1e1b00 */
/*05f0*/ LDG.E.64 R16, [R4.64+0x78] ; /* 0x0000780404107981 */
/* 0x000ee4000c1e1b00 */
/*0600*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0610*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0620*/ LDG.E.64 R10, [R6.64+0xa0] ; /* 0x0000a004060a7981 */
/* 0x001f28000c1e1b00 */
/*0630*/ LDG.E.64 R16, [R4.64+0x80] ; /* 0x0000800404107981 */
/* 0x000f24000c1e1b00 */
/*0640*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0650*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0660*/ LDG.E.64 R8, [R6.64+0xa8] ; /* 0x0000a80406087981 */
/* 0x002f28000c1e1b00 */
/*0670*/ LDG.E.64 R16, [R4.64+0x88] ; /* 0x0000880404107981 */
/* 0x000f24000c1e1b00 */
/*0680*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0690*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*06a0*/ LDG.E.64 R12, [R6.64+0xb0] ; /* 0x0000b004060c7981 */
/* 0x004ea8000c1e1b00 */
/*06b0*/ LDG.E.64 R16, [R4.64+0x90] ; /* 0x0000900404107981 */
/* 0x000ea4000c1e1b00 */
/*06c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*06d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*06e0*/ LDG.E.64 R14, [R6.64+0xb8] ; /* 0x0000b804060e7981 */
/* 0x008ee8000c1e1b00 */
/*06f0*/ LDG.E.64 R16, [R4.64+0x98] ; /* 0x0000980404107981 */
/* 0x000ee4000c1e1b00 */
/*0700*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0710*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0720*/ LDG.E.64 R10, [R6.64+0xc0] ; /* 0x0000c004060a7981 */
/* 0x001f28000c1e1b00 */
/*0730*/ LDG.E.64 R16, [R4.64+0xa0] ; /* 0x0000a00404107981 */
/* 0x000f24000c1e1b00 */
/*0740*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0750*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0760*/ LDG.E.64 R8, [R6.64+0xc8] ; /* 0x0000c80406087981 */
/* 0x002f28000c1e1b00 */
/*0770*/ LDG.E.64 R16, [R4.64+0xa8] ; /* 0x0000a80404107981 */
/* 0x000f24000c1e1b00 */
/*0780*/ DFMA R8, R8, R16, R10 ; /* 0x000000100808722b */
/* 0x010e4e000000000a */
/*0790*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*07a0*/ LDG.E.64 R12, [R6.64+0xd0] ; /* 0x0000d004060c7981 */
/* 0x004ea8000c1e1b00 */
/*07b0*/ LDG.E.64 R16, [R4.64+0xb0] ; /* 0x0000b00404107981 */
/* 0x000ea4000c1e1b00 */
/*07c0*/ DFMA R12, R12, R16, R8 ; /* 0x000000100c0c722b */
/* 0x004e8e0000000008 */
/*07d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b04 */
/*07e0*/ LDG.E.64 R14, [R6.64+0xd8] ; /* 0x0000d804060e7981 */
/* 0x008ee8000c1e1b00 */
/*07f0*/ LDG.E.64 R16, [R4.64+0xb8] ; /* 0x0000b80404107981 */
/* 0x000ee4000c1e1b00 */
/*0800*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0810*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0820*/ LDG.E.64 R10, [R6.64+0xe0] ; /* 0x0000e004060a7981 */
/* 0x001f28000c1e1b00 */
/*0830*/ LDG.E.64 R16, [R4.64+0xc0] ; /* 0x0000c00404107981 */
/* 0x000f24000c1e1b00 */
/*0840*/ DFMA R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x010e0e000000000e */
/*0850*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0860*/ LDG.E.64 R8, [R6.64+0xe8] ; /* 0x0000e80406087981 */
/* 0x002f28000c1e1b00 */
/*0870*/ LDG.E.64 R16, [R4.64+0xc8] ; /* 0x0000c80404107981 */
/* 0x000f24000c1e1b00 */
/*0880*/ DFMA R16, R8, R16, R10 ; /* 0x000000100810722b */
/* 0x010e4e000000000a */
/*0890*/ STG.E.64 [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x002fe8000c101b04 */
/*08a0*/ LDG.E.64 R8, [R6.64+0xf0] ; /* 0x0000f00406087981 */
/* 0x000ee8000c1e1b00 */
/*08b0*/ LDG.E.64 R12, [R4.64+0xd0] ; /* 0x0000d004040c7981 */
/* 0x004ee4000c1e1b00 */
/*08c0*/ DFMA R14, R8, R12, R16 ; /* 0x0000000c080e722b */
/* 0x008e4e0000000010 */
/*08d0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0023e8000c101b04 */
/*08e0*/ LDG.E.64 R8, [R6.64+0xf8] ; /* 0x0000f80406087981 */
/* 0x000ea8000c1e1b00 */
/*08f0*/ LDG.E.64 R12, [R4.64+0xd8] ; /* 0x0000d804040c7981 */
/* 0x000ea4000c1e1b00 */
/*0900*/ DFMA R18, R8, R12, R14 ; /* 0x0000000c0812722b */
/* 0x004e8e000000000e */
/*0910*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x004fe8000c101b04 */
/*0920*/ LDG.E.64 R8, [R6.64+0x100] ; /* 0x0001000406087981 */
/* 0x000ea8000c1e1b00 */
/*0930*/ LDG.E.64 R10, [R4.64+0xe0] ; /* 0x0000e004040a7981 */
/* 0x001ea4000c1e1b00 */
/*0940*/ DFMA R8, R8, R10, R18 ; /* 0x0000000a0808722b */
/* 0x004e0e0000000012 */
/*0950*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0011e8000c101b04 */
/*0960*/ LDG.E.64 R10, [R6.64+0x108] ; /* 0x00010804060a7981 */
/* 0x000ea8000c1e1b00 */
/*0970*/ LDG.E.64 R12, [R4.64+0xe8] ; /* 0x0000e804040c7981 */
/* 0x000ea4000c1e1b00 */
/*0980*/ DFMA R10, R10, R12, R8 ; /* 0x0000000c0a0a722b */
/* 0x004e8e0000000008 */
/*0990*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*09a0*/ LDG.E.64 R12, [R6.64+0x110] ; /* 0x00011004060c7981 */
/* 0x000ee8000c1e1b00 */
/*09b0*/ LDG.E.64 R14, [R4.64+0xf0] ; /* 0x0000f004040e7981 */
/* 0x002ee4000c1e1b00 */
/*09c0*/ DFMA R12, R12, R14, R10 ; /* 0x0000000e0c0c722b */
/* 0x008e4e000000000a */
/*09d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b04 */
/*09e0*/ LDG.E.64 R14, [R6.64+0x118] ; /* 0x00011804060e7981 */
/* 0x000ee8000c1e1b00 */
/*09f0*/ LDG.E.64 R16, [R4.64+0xf8] ; /* 0x0000f80404107981 */
/* 0x000ee4000c1e1b00 */
/*0a00*/ DFMA R14, R14, R16, R12 ; /* 0x000000100e0e722b */
/* 0x008ece000000000c */
/*0a10*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b04 */
/*0a20*/ LDG.E.64 R8, [R6.64+0x120] ; /* 0x0001200406087981 */
/* 0x001f28000c1e1b00 */
/*0a30*/ LDG.E.64 R16, [R4.64+0x100] ; /* 0x0001000404107981 */
/* 0x000f24000c1e1b00 */
/*0a40*/ DFMA R8, R8, R16, R14 ; /* 0x000000100808722b */
/* 0x010e0e000000000e */
/*0a50*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x001fe8000c101b04 */
/*0a60*/ LDG.E.64 R10, [R6.64+0x128] ; /* 0x00012804060a7981 */
/* 0x004ea8000c1e1b00 */
/*0a70*/ LDG.E.64 R16, [R4.64+0x108] ; /* 0x0001080404107981 */
/* 0x000ea4000c1e1b00 */
/*0a80*/ DFMA R10, R10, R16, R8 ; /* 0x000000100a0a722b */
/* 0x004e0e0000000008 */
/*0a90*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b04 */
/*0aa0*/ LDG.E.64 R12, [R6.64+0x130] ; /* 0x00013004060c7981 */
/* 0x002ea8000c1e1b00 */
/*0ab0*/ LDG.E.64 R16, [R4.64+0x110] ; /* 0x0001100404107981 */
/* 0x000ea2000c1e1b00 */
/*0ac0*/ IADD3 R0, R0, 0x28, RZ ; /* 0x0000002800007810 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ DFMA R12, R12, R16, R10 ; /* 0x000000100c0c722b */
/* 0x004e4e000000000a */
/*0ae0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b04 */
/*0af0*/ LDG.E.64 R14, [R6.64+0x138] ; /* 0x00013804060e7981 */
/* 0x0084e8000c1e1b00 */
/*0b00*/ LDG.E.64 R16, [R4.64+0x118] ; /* 0x0001180404107981 */
/* 0x000ee2000c1e1b00 */
/*0b10*/ ISETP.NE.AND P0, PT, R0, 0x3e8, PT ; /* 0x000003e80000780c */
/* 0x000fe40003f05270 */
/*0b20*/ IADD3 R10, P1, R4, 0x140, RZ ; /* 0x00000140040a7810 */
/* 0x001fc40007f3e0ff */
/*0b30*/ IADD3 R6, P2, R6, 0x140, RZ ; /* 0x0000014006067810 */
/* 0x004fe40007f5e0ff */
/*0b40*/ IADD3.X R11, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0b7210 */
/* 0x000fe40000ffe4ff */
/*0b50*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe200017fe4ff */
/*0b60*/ DFMA R8, R14, R16, R12 ; /* 0x000000100e08722b */
/* 0x008e0e000000000c */
/*0b70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0013e2000c101b04 */
/*0b80*/ @P0 BRA 0x100 ; /* 0xfffff57000000947 */
/* 0x000fea000383ffff */
/*0b90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPdS_S_
.globl _Z3dotPdS_S_
.p2align 8
.type _Z3dotPdS_S_,@function
_Z3dotPdS_S_:
s_load_b32 s2, s[0:1], 0x24
v_mov_b32_e32 v7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v3, v1, 0x3e8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v4, 31, v3
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v8, v7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v5
v_lshlrev_b64 v[9:10], 3, v[3:4]
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v10, vcc_lo
s_mov_b64 s[0:1], 0
global_store_b64 v[2:3], v[7:8], off
.p2align 6
.LBB0_1:
v_add_co_u32 v7, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v5, vcc_lo
s_add_u32 s4, s2, s0
s_addc_u32 s5, s3, s1
global_load_b64 v[9:10], v6, s[4:5]
global_load_b64 v[7:8], v[7:8], off
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s0, 0x1f40
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], v[7:8], v[9:10], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPdS_S_, .Lfunc_end0-_Z3dotPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001759bd_00000000-6_dotvec.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPdS_S_PdS_S_
.type _Z26__device_stub__Z3dotPdS_S_PdS_S_, @function
_Z26__device_stub__Z3dotPdS_S_PdS_S_:
.LFB4064:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4064:
.size _Z26__device_stub__Z3dotPdS_S_PdS_S_, .-_Z26__device_stub__Z3dotPdS_S_PdS_S_
.globl _Z3dotPdS_S_
.type _Z3dotPdS_S_, @function
_Z3dotPdS_S_:
.LFB4065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4065:
.size _Z3dotPdS_S_, .-_Z3dotPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3dotPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "in.txt"
.LC2:
.string "Err: input\n"
.LC3:
.string "Running Time: "
.LC4:
.string "s"
.LC5:
.string "out.txt"
.LC6:
.string "Err: output\n"
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB4039:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4039
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
movl $0, %edi
.LEHB0:
call _ZNSt8ios_base15sync_with_stdioEb@PLT
leaq 576(%rsp), %rdi
movl $8, %edx
leaq .LC1(%rip), %rsi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
testb $5, 864(%rsp)
jne .L40
movl $8000000, %edi
.LEHB1:
call _Znam@PLT
jmp .L41
.L40:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L42
.L41:
movq %rax, %r15
movl $8000, %edi
call _Znam@PLT
movq %rax, %r14
movl $8000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
leaq 8000(%r15), %rbp
leaq 8008000(%r15), %r13
leaq 576(%rsp), %r12
jmp .L16
.L44:
addq $8, %rbx
cmpq %rbp, %rbx
je .L43
.L17:
movq %rbx, %rsi
movq %r12, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
jmp .L44
.L43:
addq $8000, %rbp
cmpq %r13, %rbp
je .L18
.L16:
leaq -8000(%rbp), %rbx
jmp .L17
.L18:
movq %r14, %rbx
leaq 8000(%r14), %rbp
leaq 576(%rsp), %r12
jmp .L19
.L46:
addq $8, %rbx
cmpq %rbp, %rbx
je .L45
.L19:
movq %rbx, %rsi
movq %r12, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
jmp .L46
.L45:
leaq 576(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq 16(%rsp), %rdi
movl $8000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000000, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq start(%rip), %rdi
call cudaEventCreate@PLT
leaq stop(%rip), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq start(%rip), %rdi
call cudaEventRecord@PLT
movl $10, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $100, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z3dotPdS_S_PdS_S_
.L20:
movl $0, %esi
movq stop(%rip), %rdi
call cudaEventRecord@PLT
movq stop(%rip), %rdi
call cudaEventSynchronize@PLT
movq stop(%rip), %rdx
movq start(%rip), %rsi
leaq elapsedTime(%rip), %rdi
call cudaEventElapsedTime@PLT
movq start(%rip), %rdi
call cudaEventDestroy@PLT
movq stop(%rip), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $8000, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd elapsedTime(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 64(%rsp), %rdi
movl $16, %edx
leaq .LC5(%rip), %rsi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
leaq 8000(%rbx), %rbp
leaq .LC7(%rip), %r12
movl 344(%rsp), %r13d
andl $5, %r13d
je .L23
leaq .LC6(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L47
.L49:
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rbx
cmpq %rbp, %rbx
je .L48
.L23:
movq 64(%rsp), %rax
movq -24(%rax), %rax
movq $15, 72(%rsp,%rax)
movsd (%rbx), %xmm0
leaq 64(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L49
.L48:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
.LEHE2:
jmp .L22
.L47:
movl $-1, %r13d
.L22:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L15:
leaq 576(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl %r13d, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl $-2, %r13d
jmp .L15
.L31:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L25:
leaq 576(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
je .L26
call __stack_chk_fail@PLT
.L30:
endbr64
movq %rax, %rbx
jmp .L25
.L26:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4039:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4039-.LLSDACSB4039
.LLSDACSB4039:
.uleb128 .LEHB0-.LFB4039
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4039
.uleb128 .LEHE1-.LEHB1
.uleb128 .L30-.LFB4039
.uleb128 0
.uleb128 .LEHB2-.LFB4039
.uleb128 .LEHE2-.LEHB2
.uleb128 .L31-.LFB4039
.uleb128 0
.uleb128 .LEHB3-.LFB4039
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4039:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl elapsedTime
.bss
.align 4
.type elapsedTime, @object
.size elapsedTime, 4
elapsedTime:
.zero 4
.globl stop
.align 8
.type stop, @object
.size stop, 8
stop:
.zero 8
.globl start
.align 8
.type start, @object
.size start, 8
start:
.zero 8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dotvec.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__dotPdS_S_ # -- Begin function _Z18__device_stub__dotPdS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPdS_S_,@function
_Z18__device_stub__dotPdS_S_: # @_Z18__device_stub__dotPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPdS_S_, .Lfunc_end0-_Z18__device_stub__dotPdS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1144, %rsp # imm = 0x478
.cfi_def_cfa_offset 1200
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq _ZNSt8ios_base15sync_with_stdioEb
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
movl $.L.str, %esi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
movq 624(%rsp), %rax
movq -24(%rax), %rax
testb $5, 656(%rsp,%rax)
je .LBB1_3
# %bb.1:
movl $-2, %ebx
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
jmp .LBB1_2
.LBB1_3:
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $8000000, %edi # imm = 0x7A1200
callq _Znam
.Ltmp4:
# %bb.4:
.Ltmp6:
movq %rax, %rbp
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znam
.Ltmp7:
# %bb.5:
.Ltmp9:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znam
.Ltmp10:
# %bb.6: # %.preheader83.preheader
movq %rax, %r15
xorl %r13d, %r13d
leaq 624(%rsp), %r12
movq %rbp, 32(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_7: # %.preheader83
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%rbx,%rbp), %rsi
.Ltmp11:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSi10_M_extractIdEERSiRT_
.Ltmp12:
# %bb.9: # %_ZNSirsERd.exit
# in Loop: Header=BB1_8 Depth=2
addq $8, %rbx
cmpq $8000, %rbx # imm = 0x1F40
jne .LBB1_8
# %bb.10: # in Loop: Header=BB1_7 Depth=1
incq %r13
addq $8000, %rbp # imm = 0x1F40
cmpq $1000, %r13 # imm = 0x3E8
jne .LBB1_7
# %bb.11: # %.preheader82.preheader
xorl %r13d, %r13d
leaq 624(%rsp), %r12
.p2align 4, 0x90
.LBB1_12: # %.preheader82
# =>This Inner Loop Header: Depth=1
leaq (%r14,%r13), %rsi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSi10_M_extractIdEERSiRT_
.Ltmp15:
# %bb.13: # %_ZNSirsERd.exit50
# in Loop: Header=BB1_12 Depth=1
addq $8, %r13
cmpq $8000, %r13 # imm = 0x1F40
jne .LBB1_12
# %bb.14:
leaq 640(%rsp), %rdi
.Ltmp17:
.cfi_escape 0x2e, 0x00
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp18:
movq 32(%rsp), %rbx # 8-byte Reload
# %bb.15: # %.noexc
testq %rax, %rax
jne .LBB1_17
# %bb.16:
movq 624(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $624, %rdi # imm = 0x270
movl 656(%rsp,%rax), %esi
orl $4, %esi
.Ltmp19:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp20:
.LBB1_17: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
callq hipMalloc
.Ltmp23:
# %bb.18: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit
movq 24(%rsp), %rdi
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $8000000, %edx # imm = 0x7A1200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp25:
# %bb.19:
.Ltmp26:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp27:
# %bb.20: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit53
movq 16(%rsp), %rdi
.Ltmp28:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.21:
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp31:
# %bb.22: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit55
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $start, %edi
callq hipEventCreate
.Ltmp33:
# %bb.23:
.Ltmp34:
.cfi_escape 0x2e, 0x00
movl $stop, %edi
callq hipEventCreate
.Ltmp35:
# %bb.24:
movq start(%rip), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp37:
# %bb.25:
.Ltmp38:
.cfi_escape 0x2e, 0x00
movabsq $4294967396, %rdi # imm = 0x100000064
movabsq $4294967306, %rdx # imm = 0x10000000A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp39:
# %bb.26:
testl %eax, %eax
jne .LBB1_29
# %bb.27:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
.Ltmp40:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp41:
# %bb.28: # %.noexc56
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.Ltmp42:
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z3dotPdS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp43:
.LBB1_29:
movq stop(%rip), %rdi
.Ltmp44:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp45:
# %bb.30:
movq stop(%rip), %rdi
.Ltmp46:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp47:
# %bb.31:
movq start(%rip), %rsi
movq stop(%rip), %rdx
.Ltmp48:
.cfi_escape 0x2e, 0x00
movl $elapsedTime, %edi
callq hipEventElapsedTime
.Ltmp49:
# %bb.32:
movq start(%rip), %rdi
.Ltmp50:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp51:
# %bb.33:
movq stop(%rip), %rdi
.Ltmp52:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp53:
# %bb.34:
movq 8(%rsp), %rsi
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp55:
# %bb.35:
.Ltmp56:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp57:
# %bb.36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit59
movss elapsedTime(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp58:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp59:
# %bb.37: # %_ZNSolsEf.exit
.Ltmp60:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp61:
# %bb.38: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit62
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_39
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB1_47
# %bb.46:
movzbl 67(%r13), %eax
jmp .LBB1_49
.LBB1_47:
.Ltmp62:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp63:
# %bb.48: # %.noexc73
movq (%r13), %rax
.Ltmp64:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp65:
.LBB1_49: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp66:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp67:
# %bb.50: # %.noexc75
.Ltmp68:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp69:
# %bb.51: # %_ZNSolsEPFRSoS_E.exit
.Ltmp70:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
movl $.L.str.4, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp71:
# %bb.52:
movq 112(%rsp), %rax
movq -24(%rax), %rax
testb $5, 144(%rsp,%rax)
je .LBB1_53
# %bb.63:
movl $-1, %ebx
.Ltmp73:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp74:
jmp .LBB1_64
.LBB1_53: # %.preheader
xorl %r13d, %r13d
leaq 112(%rsp), %r12
.p2align 4, 0x90
.LBB1_54: # =>This Inner Loop Header: Depth=1
movq 112(%rsp), %rax
movq -24(%rax), %rax
movq $15, 120(%rsp,%rax)
movsd (%r15,%r13,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp75:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp76:
# %bb.55: # %_ZNSolsEd.exit
# in Loop: Header=BB1_54 Depth=1
.Ltmp77:
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp78:
# %bb.56: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit71
# in Loop: Header=BB1_54 Depth=1
incq %r13
cmpq $1000, %r13 # imm = 0x3E8
jne .LBB1_54
# %bb.57:
leaq 120(%rsp), %rdi
.Ltmp80:
.cfi_escape 0x2e, 0x00
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp81:
# %bb.58: # %.noexc67
testq %rax, %rax
jne .LBB1_60
# %bb.59:
movq 112(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $112, %rdi
movl 144(%rsp,%rax), %esi
orl $4, %esi
.Ltmp82:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp83:
.LBB1_60: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq free
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
.Ltmp84:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp85:
# %bb.61:
movq 16(%rsp), %rdi
.Ltmp86:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp87:
# %bb.62:
xorl %ebx, %ebx
movq 8(%rsp), %rdi
.Ltmp88:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp89:
.LBB1_64: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit65
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB1_2: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 880(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
movl %ebx, %eax
addq $1144, %rsp # imm = 0x478
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_39:
.cfi_def_cfa_offset 1200
.Ltmp91:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp92:
# %bb.44: # %.noexc72
.LBB1_65:
.Ltmp72:
jmp .LBB1_69
.LBB1_41:
.Ltmp8:
jmp .LBB1_69
.LBB1_40:
.Ltmp5:
jmp .LBB1_69
.LBB1_68:
.Ltmp2:
jmp .LBB1_69
.LBB1_66:
.Ltmp90:
jmp .LBB1_67
.LBB1_42:
.Ltmp21:
jmp .LBB1_69
.LBB1_72:
.Ltmp93:
jmp .LBB1_69
.LBB1_73:
.Ltmp79:
.LBB1_67:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
jmp .LBB1_70
.LBB1_71:
.Ltmp16:
jmp .LBB1_69
.LBB1_43:
.Ltmp13:
.LBB1_69:
movq %rax, %rbx
.LBB1_70:
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 880(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp20-.Ltmp17 # Call between .Ltmp17 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp69-.Ltmp22 # Call between .Ltmp22 and .Ltmp69
.uleb128 .Ltmp93-.Lfunc_begin0 # jumps to .Ltmp93
.byte 0 # On action: cleanup
.uleb128 .Ltmp70-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp71-.Ltmp70 # Call between .Ltmp70 and .Ltmp71
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp74-.Ltmp73 # Call between .Ltmp73 and .Ltmp74
.uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90
.byte 0 # On action: cleanup
.uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp78-.Ltmp75 # Call between .Ltmp75 and .Ltmp78
.uleb128 .Ltmp79-.Lfunc_begin0 # jumps to .Ltmp79
.byte 0 # On action: cleanup
.uleb128 .Ltmp80-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp89-.Ltmp80 # Call between .Ltmp80 and .Ltmp89
.uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90
.byte 0 # On action: cleanup
.uleb128 .Ltmp91-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp92-.Ltmp91 # Call between .Ltmp91 and .Ltmp92
.uleb128 .Ltmp93-.Lfunc_begin0 # jumps to .Ltmp93
.byte 0 # On action: cleanup
.uleb128 .Ltmp92-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Lfunc_end1-.Ltmp92 # Call between .Ltmp92 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.quad 0
.size start, 8
.type stop,@object # @stop
.globl stop
.p2align 3, 0x0
stop:
.quad 0
.size stop, 8
.type elapsedTime,@object # @elapsedTime
.globl elapsedTime
.p2align 2, 0x0
elapsedTime:
.long 0x00000000 # float 0
.size elapsedTime, 4
.type _Z3dotPdS_S_,@object # @_Z3dotPdS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPdS_S_
.p2align 3, 0x0
_Z3dotPdS_S_:
.quad _Z18__device_stub__dotPdS_S_
.size _Z3dotPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "in.txt"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Err: input\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Running Time: "
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "s"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "out.txt"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Err: output\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n"
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPdS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPdS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym start
.addrsig_sym stop
.addrsig_sym elapsedTime
.addrsig_sym _Z3dotPdS_S_
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
using namespace std;
#define BLOCK_SIZE_1D 1024
#define BLOCK_SIZE_2D 32
/**
* CUDA kernel responsible for multiplying two matrices 'A' and 'B', using the
* naive approach, and storing result in matrix 'Y'
*
* @param use2D Defines whether 2D blocks and grid are used. This only affects
* the way the indices 'i' and 'j' are calculated.
*/
__global__ void naiveMMKernel(int n, double *A, double *B, double *Y, bool use2D) {
int i, j;
if (use2D) {
i = threadIdx.y + (blockIdx.y * blockDim.y);
j = threadIdx.x + (blockIdx.x * blockDim.x);
} else {
i = (threadIdx.x + (blockIdx.x * blockDim.x)) / n;
j = (threadIdx.x + (blockIdx.x * blockDim.x)) - (i * n);
}
if (i >= n || j >= n) {
return;
}
double res = 0;
for (int k = 0; k < n; k++) {
res += A[i * n + k] * B[k * n + j];
}
Y[i * n + j] = res;
}
/**
* Multiplies matrices 'd_A' and 'd_B' using the naive approach and stores the
* result in matrix 'd_Y'
*
* The input matrices have to reference the device memory
*
* @param use2D Defines whether 2D blocks and grid should be used for the
* kernel configuration
*/
void naiveMM(int n, double *d_A, double *d_B, double *d_Y, bool use2D) {
dim3 dimGrid, dimBlock;
if (use2D) {
// Total of 1024 threads
dimBlock = dim3(BLOCK_SIZE_2D, BLOCK_SIZE_2D);
int dimSize = (n + BLOCK_SIZE_2D - 1) / BLOCK_SIZE_2D;
dimGrid = dim3(dimSize, dimSize);
} else {
dimBlock = dim3(BLOCK_SIZE_1D);
dimGrid = dim3((n * n + BLOCK_SIZE_1D - 1) / BLOCK_SIZE_1D);
}
naiveMMKernel<<<dimGrid, dimBlock>>>(n, d_A, d_B, d_Y, use2D);
cudaThreadSynchronize();
cout << dimBlock.x << "x" << dimBlock.y << "\t\t";
cout << dimGrid.x << "x" << dimGrid.y << "\t\t";
} | code for sm_80
Function : _Z13naiveMMKerneliPdS_S_b
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ULDC.S8 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000200 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*0030*/ @!P0 BRA 0xb0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0060*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0070*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R3, R0, c[0x0][0x4], R3 ; /* 0x0000010000037a24 */
/* 0x001fc400078e0203 */
/*0090*/ IMAD R0, R2, c[0x0][0x0], R5 ; /* 0x0000000002007a24 */
/* 0x002fe200078e0205 */
/*00a0*/ BRA 0x220 ; /* 0x0000017000007947 */
/* 0x000fea0003800000 */
/*00b0*/ I2F.U32.RP R0, c[0x0][0x160] ; /* 0x0000580000007b06 */
/* 0x000e220000209000 */
/*00c0*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fc60003f45070 */
/*00e0*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e660000002500 */
/*00f0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e220000001000 */
/*0100*/ IMAD R7, R7, c[0x0][0x0], R4 ; /* 0x0000000007077a24 */
/* 0x002fe200078e0204 */
/*0110*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0140*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a24 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0190*/ IMAD R0, R0, c[0x0][0x160], R7 ; /* 0x0000580000007a24 */
/* 0x000fca00078e0207 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R0, R0, -c[0x0][0x160], RZ ; /* 0x8000580000000a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff03aa12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R0, -R3, RZ, RZ ; /* 0x000000ff03007210 */
/* 0x000fca0007ffe1ff */
/*0210*/ IMAD R0, R0, c[0x0][0x160], R7 ; /* 0x0000580000007a24 */
/* 0x000fca00078e0207 */
/*0220*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06270 */
/*0230*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x160], P0 ; /* 0x0000580003007a0c */
/* 0x000fda0000706670 */
/*0240*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0250*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0260*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0270*/ IMAD R3, R3, c[0x0][0x160], RZ ; /* 0x0000580003037a24 */
/* 0x000fe200078e02ff */
/*0280*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0290*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*02a0*/ @!P0 BRA 0xdf0 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*02c0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*02d0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*02e0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*02f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd800078e00ff */
/*0300*/ @!P0 BRA 0xcb0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0310*/ IADD3 R26, -R5, c[0x0][0x160], RZ ; /* 0x00005800051a7a10 */
/* 0x000fe20007ffe1ff */
/*0320*/ HFMA2.MMA R23, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff177435 */
/* 0x000fe200000001ff */
/*0330*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0340*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*0350*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0360*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fcc0003f04270 */
/*0370*/ IMAD.WIDE R22, R0, R23, c[0x0][0x170] ; /* 0x00005c0000167625 */
/* 0x000fce00078e0217 */
/*0380*/ @!P0 BRA 0xb20 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*03a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*03b0*/ @!P1 BRA 0x860 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*03c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03d0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*03e0*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*03f0*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0400*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0410*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0420*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0430*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0440*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*0450*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*0460*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0470*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0480*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0490*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*04a0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*04b0*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*04c0*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*04d0*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*04e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*04f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0500*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0510*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0520*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0530*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0540*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0550*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*0560*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*0570*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*0580*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*0590*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*05a0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*05b0*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*05c0*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*05d0*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*05e0*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*05f0*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0600*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0610*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0620*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0630*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0640*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*0650*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*0660*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*0670*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*0680*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*0690*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*06a0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*06b0*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*06c0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*06d0*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*06e0*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*06f0*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0700*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0710*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0720*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0730*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0740*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*0750*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*0760*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*0770*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*0780*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*0790*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*07a0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*07b0*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*07c0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*07d0*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*07e0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*07f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0800*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0810*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0820*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0830*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0840*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*0850*/ @P1 BRA 0x3d0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0860*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*0870*/ @!P1 BRA 0xb00 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0880*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0890*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*08a0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea6000c1e1b00 */
/*08b0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*08c0*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*08d0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*08e0*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*08f0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0900*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0910*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0920*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0930*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0940*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*0950*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*0960*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0970*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*0980*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*0990*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*09a0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*09b0*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*09c0*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*09d0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*09e0*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*09f0*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0a00*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0a10*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0a20*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0a30*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0a40*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0a50*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*0a60*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*0a70*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*0a80*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0a90*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0aa0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0ae0*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0af0*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0b00*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0b10*/ @!P0 BRA 0xcb0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0b20*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0b30*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a2000c1e1b00 */
/*0b40*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0b50*/ IMAD.WIDE R10, R2, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x000fc800078e0216 */
/*0b60*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fe200078e021c */
/*0b70*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0010e8000c1e1b00 */
/*0b80*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*0b90*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*0ba0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f28000c1e1b00 */
/*0bb0*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001ee8000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000128000c1e1b00 */
/*0bd0*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f62000c1e1b00 */
/*0be0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x001fca00078e0210 */
/*0bf0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0c00*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0c10*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0c20*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0c30*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0c40*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c50*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004ecc0000000008 */
/*0c60*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x008f0c0000000016 */
/*0c70*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x010f620000000006 */
/*0c80*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0c90*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0ca0*/ @P0 BRA 0xb20 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 BRA 0xdf0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0cd0*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0ce0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe400078e00ff */
/*0cf0*/ IMAD R4, R4, c[0x0][0x160], R0 ; /* 0x0000580004047a24 */
/* 0x000fe400078e0200 */
/*0d00*/ IMAD.WIDE R6, R6, R11, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e020b */
/*0d10*/ IMAD.WIDE R10, R4, R11, c[0x0][0x170] ; /* 0x00005c00040a7625 */
/* 0x000fe200078e020b */
/*0d20*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0d30*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc80000000f00 */
/*0d40*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x001fe20000000f00 */
/*0d50*/ IMAD.MOV.U32 R13, RZ, RZ, R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000f */
/*0d60*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0d70*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0d80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0d90*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0da0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0db0*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0dc0*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0dd0*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0de0*/ @P0 BRA 0xd40 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0df0*/ IADD3 R3, R3, R0, RZ ; /* 0x0000000003037210 */
/* 0x000fe40007ffe0ff */
/*0e00*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0e10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fca00078e0202 */
/*0e20*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
using namespace std;
#define BLOCK_SIZE_1D 1024
#define BLOCK_SIZE_2D 32
/**
* CUDA kernel responsible for multiplying two matrices 'A' and 'B', using the
* naive approach, and storing result in matrix 'Y'
*
* @param use2D Defines whether 2D blocks and grid are used. This only affects
* the way the indices 'i' and 'j' are calculated.
*/
__global__ void naiveMMKernel(int n, double *A, double *B, double *Y, bool use2D) {
int i, j;
if (use2D) {
i = threadIdx.y + (blockIdx.y * blockDim.y);
j = threadIdx.x + (blockIdx.x * blockDim.x);
} else {
i = (threadIdx.x + (blockIdx.x * blockDim.x)) / n;
j = (threadIdx.x + (blockIdx.x * blockDim.x)) - (i * n);
}
if (i >= n || j >= n) {
return;
}
double res = 0;
for (int k = 0; k < n; k++) {
res += A[i * n + k] * B[k * n + j];
}
Y[i * n + j] = res;
}
/**
* Multiplies matrices 'd_A' and 'd_B' using the naive approach and stores the
* result in matrix 'd_Y'
*
* The input matrices have to reference the device memory
*
* @param use2D Defines whether 2D blocks and grid should be used for the
* kernel configuration
*/
void naiveMM(int n, double *d_A, double *d_B, double *d_Y, bool use2D) {
dim3 dimGrid, dimBlock;
if (use2D) {
// Total of 1024 threads
dimBlock = dim3(BLOCK_SIZE_2D, BLOCK_SIZE_2D);
int dimSize = (n + BLOCK_SIZE_2D - 1) / BLOCK_SIZE_2D;
dimGrid = dim3(dimSize, dimSize);
} else {
dimBlock = dim3(BLOCK_SIZE_1D);
dimGrid = dim3((n * n + BLOCK_SIZE_1D - 1) / BLOCK_SIZE_1D);
}
naiveMMKernel<<<dimGrid, dimBlock>>>(n, d_A, d_B, d_Y, use2D);
cudaThreadSynchronize();
cout << dimBlock.x << "x" << dimBlock.y << "\t\t";
cout << dimGrid.x << "x" << dimGrid.y << "\t\t";
} | .file "tmpxft_00073350_00000000-6_NaiveMatrixMulti.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b
.type _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b, @function
_Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movb %r8b, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13naiveMMKerneliPdS_S_b(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b, .-_Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b
.globl _Z13naiveMMKerneliPdS_S_b
.type _Z13naiveMMKerneliPdS_S_b, @function
_Z13naiveMMKerneliPdS_S_b:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13naiveMMKerneliPdS_S_b, .-_Z13naiveMMKerneliPdS_S_b
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "x"
.LC1:
.string "\t\t"
.text
.globl _Z7naiveMMiPdS_S_b
.type _Z7naiveMMiPdS_S_b, @function
_Z7naiveMMiPdS_S_b:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r12d
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, %r15d
movl $1, 48(%rsp)
movl $1, 60(%rsp)
testb %r8b, %r8b
je .L12
leal 62(%rdi), %ebx
movl %edi, %eax
addl $31, %eax
cmovns %eax, %ebx
sarl $5, %ebx
movl %ebx, %ebp
movl $32, %r13d
movl $32, %r14d
.L13:
movl %ebp, 40(%rsp)
movl %ebx, 44(%rsp)
movl %r14d, 52(%rsp)
movl %r13d, 56(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
call cudaThreadSynchronize@PLT
movl %r14d, %esi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %r15
movl $1, %edx
leaq .LC0(%rip), %r12
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %r15, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl %edi, %eax
imull %edi, %eax
leal 2046(%rax), %ebp
addl $1023, %eax
cmovns %eax, %ebp
sarl $10, %ebp
movl $1, %r13d
movl $1024, %r14d
movl $1, %ebx
jmp .L13
.L16:
movzbl %r15b, %r8d
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl %r12d, %edi
call _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b
jmp .L14
.cfi_endproc
.LFE3669:
.size _Z7naiveMMiPdS_S_b, .-_Z7naiveMMiPdS_S_b
.section .rodata.str1.1
.LC2:
.string "_Z13naiveMMKerneliPdS_S_b"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13naiveMMKerneliPdS_S_b(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
using namespace std;
#define BLOCK_SIZE_1D 1024
#define BLOCK_SIZE_2D 32
/**
* CUDA kernel responsible for multiplying two matrices 'A' and 'B', using the
* naive approach, and storing result in matrix 'Y'
*
* @param use2D Defines whether 2D blocks and grid are used. This only affects
* the way the indices 'i' and 'j' are calculated.
*/
__global__ void naiveMMKernel(int n, double *A, double *B, double *Y, bool use2D) {
int i, j;
if (use2D) {
i = threadIdx.y + (blockIdx.y * blockDim.y);
j = threadIdx.x + (blockIdx.x * blockDim.x);
} else {
i = (threadIdx.x + (blockIdx.x * blockDim.x)) / n;
j = (threadIdx.x + (blockIdx.x * blockDim.x)) - (i * n);
}
if (i >= n || j >= n) {
return;
}
double res = 0;
for (int k = 0; k < n; k++) {
res += A[i * n + k] * B[k * n + j];
}
Y[i * n + j] = res;
}
/**
* Multiplies matrices 'd_A' and 'd_B' using the naive approach and stores the
* result in matrix 'd_Y'
*
* The input matrices have to reference the device memory
*
* @param use2D Defines whether 2D blocks and grid should be used for the
* kernel configuration
*/
void naiveMM(int n, double *d_A, double *d_B, double *d_Y, bool use2D) {
dim3 dimGrid, dimBlock;
if (use2D) {
// Total of 1024 threads
dimBlock = dim3(BLOCK_SIZE_2D, BLOCK_SIZE_2D);
int dimSize = (n + BLOCK_SIZE_2D - 1) / BLOCK_SIZE_2D;
dimGrid = dim3(dimSize, dimSize);
} else {
dimBlock = dim3(BLOCK_SIZE_1D);
dimGrid = dim3((n * n + BLOCK_SIZE_1D - 1) / BLOCK_SIZE_1D);
}
naiveMMKernel<<<dimGrid, dimBlock>>>(n, d_A, d_B, d_Y, use2D);
cudaThreadSynchronize();
cout << dimBlock.x << "x" << dimBlock.y << "\t\t";
cout << dimGrid.x << "x" << dimGrid.y << "\t\t";
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
using namespace std;
#define BLOCK_SIZE_1D 1024
#define BLOCK_SIZE_2D 32
/**
* CUDA kernel responsible for multiplying two matrices 'A' and 'B', using the
* naive approach, and storing result in matrix 'Y'
*
* @param use2D Defines whether 2D blocks and grid are used. This only affects
* the way the indices 'i' and 'j' are calculated.
*/
__global__ void naiveMMKernel(int n, double *A, double *B, double *Y, bool use2D) {
int i, j;
if (use2D) {
i = threadIdx.y + (blockIdx.y * blockDim.y);
j = threadIdx.x + (blockIdx.x * blockDim.x);
} else {
i = (threadIdx.x + (blockIdx.x * blockDim.x)) / n;
j = (threadIdx.x + (blockIdx.x * blockDim.x)) - (i * n);
}
if (i >= n || j >= n) {
return;
}
double res = 0;
for (int k = 0; k < n; k++) {
res += A[i * n + k] * B[k * n + j];
}
Y[i * n + j] = res;
}
/**
* Multiplies matrices 'd_A' and 'd_B' using the naive approach and stores the
* result in matrix 'd_Y'
*
* The input matrices have to reference the device memory
*
* @param use2D Defines whether 2D blocks and grid should be used for the
* kernel configuration
*/
void naiveMM(int n, double *d_A, double *d_B, double *d_Y, bool use2D) {
dim3 dimGrid, dimBlock;
if (use2D) {
// Total of 1024 threads
dimBlock = dim3(BLOCK_SIZE_2D, BLOCK_SIZE_2D);
int dimSize = (n + BLOCK_SIZE_2D - 1) / BLOCK_SIZE_2D;
dimGrid = dim3(dimSize, dimSize);
} else {
dimBlock = dim3(BLOCK_SIZE_1D);
dimGrid = dim3((n * n + BLOCK_SIZE_1D - 1) / BLOCK_SIZE_1D);
}
naiveMMKernel<<<dimGrid, dimBlock>>>(n, d_A, d_B, d_Y, use2D);
hipDeviceSynchronize();
cout << dimBlock.x << "x" << dimBlock.y << "\t\t";
cout << dimGrid.x << "x" << dimGrid.y << "\t\t";
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
using namespace std;
#define BLOCK_SIZE_1D 1024
#define BLOCK_SIZE_2D 32
/**
* CUDA kernel responsible for multiplying two matrices 'A' and 'B', using the
* naive approach, and storing result in matrix 'Y'
*
* @param use2D Defines whether 2D blocks and grid are used. This only affects
* the way the indices 'i' and 'j' are calculated.
*/
__global__ void naiveMMKernel(int n, double *A, double *B, double *Y, bool use2D) {
int i, j;
if (use2D) {
i = threadIdx.y + (blockIdx.y * blockDim.y);
j = threadIdx.x + (blockIdx.x * blockDim.x);
} else {
i = (threadIdx.x + (blockIdx.x * blockDim.x)) / n;
j = (threadIdx.x + (blockIdx.x * blockDim.x)) - (i * n);
}
if (i >= n || j >= n) {
return;
}
double res = 0;
for (int k = 0; k < n; k++) {
res += A[i * n + k] * B[k * n + j];
}
Y[i * n + j] = res;
}
/**
* Multiplies matrices 'd_A' and 'd_B' using the naive approach and stores the
* result in matrix 'd_Y'
*
* The input matrices have to reference the device memory
*
* @param use2D Defines whether 2D blocks and grid should be used for the
* kernel configuration
*/
void naiveMM(int n, double *d_A, double *d_B, double *d_Y, bool use2D) {
dim3 dimGrid, dimBlock;
if (use2D) {
// Total of 1024 threads
dimBlock = dim3(BLOCK_SIZE_2D, BLOCK_SIZE_2D);
int dimSize = (n + BLOCK_SIZE_2D - 1) / BLOCK_SIZE_2D;
dimGrid = dim3(dimSize, dimSize);
} else {
dimBlock = dim3(BLOCK_SIZE_1D);
dimGrid = dim3((n * n + BLOCK_SIZE_1D - 1) / BLOCK_SIZE_1D);
}
naiveMMKernel<<<dimGrid, dimBlock>>>(n, d_A, d_B, d_Y, use2D);
hipDeviceSynchronize();
cout << dimBlock.x << "x" << dimBlock.y << "\t\t";
cout << dimGrid.x << "x" << dimGrid.y << "\t\t";
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13naiveMMKerneliPdS_S_b
.globl _Z13naiveMMKerneliPdS_S_b
.p2align 8
.type _Z13naiveMMKerneliPdS_S_b,@function
_Z13naiveMMKerneliPdS_S_b:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 1
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_cmp_eq_u32 s3, 0
s_mov_b32 s3, 0
s_cbranch_scc0 .LBB0_2
v_cvt_f32_u32_e32 v1, s2
s_load_b32 s6, s[4:5], 0xc
s_sub_i32 s7, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v4, v1
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s7, v4
v_mul_hi_u32 v5, v4, v2
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v4, v5
v_mul_hi_u32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v1, s2
v_add_nc_u32_e32 v4, 1, v1
v_sub_nc_u32_e32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v5, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v1, s2
v_sub_nc_u32_e32 v2, v2, v3
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_3
s_branch .LBB0_4
.LBB0_2:
.LBB0_3:
s_load_b32 s3, s[4:5], 0xc
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s3, v[0:1]
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v1, v2
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_10
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_8
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v5, v1, s2
v_ashrrev_i32_e32 v3, 31, v2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 3, v[2:3]
v_mov_b32_e32 v3, 0
v_ashrrev_i32_e32 v6, 31, v5
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v10, vcc_lo
s_lshl_b64 s[4:5], s[2:3], 3
s_mov_b32 s3, s2
.LBB0_7:
global_load_b64 v[9:10], v[7:8], off
global_load_b64 v[11:12], v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[9:10], v[11:12], v[3:4]
s_cbranch_scc0 .LBB0_7
s_branch .LBB0_9
.LBB0_8:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, s2, v[2:3]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13naiveMMKerneliPdS_S_b
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13naiveMMKerneliPdS_S_b, .Lfunc_end0-_Z13naiveMMKerneliPdS_S_b
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 1
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13naiveMMKerneliPdS_S_b
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13naiveMMKerneliPdS_S_b.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
using namespace std;
#define BLOCK_SIZE_1D 1024
#define BLOCK_SIZE_2D 32
/**
* CUDA kernel responsible for multiplying two matrices 'A' and 'B', using the
* naive approach, and storing result in matrix 'Y'
*
* @param use2D Defines whether 2D blocks and grid are used. This only affects
* the way the indices 'i' and 'j' are calculated.
*/
__global__ void naiveMMKernel(int n, double *A, double *B, double *Y, bool use2D) {
int i, j;
if (use2D) {
i = threadIdx.y + (blockIdx.y * blockDim.y);
j = threadIdx.x + (blockIdx.x * blockDim.x);
} else {
i = (threadIdx.x + (blockIdx.x * blockDim.x)) / n;
j = (threadIdx.x + (blockIdx.x * blockDim.x)) - (i * n);
}
if (i >= n || j >= n) {
return;
}
double res = 0;
for (int k = 0; k < n; k++) {
res += A[i * n + k] * B[k * n + j];
}
Y[i * n + j] = res;
}
/**
* Multiplies matrices 'd_A' and 'd_B' using the naive approach and stores the
* result in matrix 'd_Y'
*
* The input matrices have to reference the device memory
*
* @param use2D Defines whether 2D blocks and grid should be used for the
* kernel configuration
*/
void naiveMM(int n, double *d_A, double *d_B, double *d_Y, bool use2D) {
dim3 dimGrid, dimBlock;
if (use2D) {
// Total of 1024 threads
dimBlock = dim3(BLOCK_SIZE_2D, BLOCK_SIZE_2D);
int dimSize = (n + BLOCK_SIZE_2D - 1) / BLOCK_SIZE_2D;
dimGrid = dim3(dimSize, dimSize);
} else {
dimBlock = dim3(BLOCK_SIZE_1D);
dimGrid = dim3((n * n + BLOCK_SIZE_1D - 1) / BLOCK_SIZE_1D);
}
naiveMMKernel<<<dimGrid, dimBlock>>>(n, d_A, d_B, d_Y, use2D);
hipDeviceSynchronize();
cout << dimBlock.x << "x" << dimBlock.y << "\t\t";
cout << dimGrid.x << "x" << dimGrid.y << "\t\t";
} | .text
.file "NaiveMatrixMulti.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__naiveMMKerneliPdS_S_b # -- Begin function _Z28__device_stub__naiveMMKerneliPdS_S_b
.p2align 4, 0x90
.type _Z28__device_stub__naiveMMKerneliPdS_S_b,@function
_Z28__device_stub__naiveMMKerneliPdS_S_b: # @_Z28__device_stub__naiveMMKerneliPdS_S_b
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movb %r8b, 3(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 3(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13naiveMMKerneliPdS_S_b, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__naiveMMKerneliPdS_S_b, .Lfunc_end0-_Z28__device_stub__naiveMMKerneliPdS_S_b
.cfi_endproc
# -- End function
.globl _Z7naiveMMiPdS_S_b # -- Begin function _Z7naiveMMiPdS_S_b
.p2align 4, 0x90
.type _Z7naiveMMiPdS_S_b,@function
_Z7naiveMMiPdS_S_b: # @_Z7naiveMMiPdS_S_b
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movq %rcx, 16(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movl %edi, %r15d
movabsq $4294967296, %rbx # imm = 0x100000000
testl %r8d, %r8d
je .LBB1_2
# %bb.1:
leal 31(%r15), %eax
leal 62(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
incq %rbx
imulq %rcx, %rbx
movabsq $137438953504, %r14 # imm = 0x2000000020
jmp .LBB1_3
.LBB1_2:
movl %r15d, %eax
imull %eax, %eax
addl $1023, %eax # imm = 0x3FF
shrl $10, %eax
orq %rbx, %rax
addq $1024, %rbx # imm = 0x400
movq %rbx, %r14
movq %rax, %rbx
.LBB1_3:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movl %r15d, 12(%rsp)
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movb %bpl, 11(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 11(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13naiveMMKerneliPdS_S_b, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
callq hipDeviceSynchronize
movl %r14d, %esi
andl $1056, %esi # imm = 0x420
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
shrq $32, %r14
movq %r15, %rdi
movq %r14, %rsi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %esi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
shrq $32, %rbx
movq %r14, %rdi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7naiveMMiPdS_S_b, .Lfunc_end1-_Z7naiveMMiPdS_S_b
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13naiveMMKerneliPdS_S_b, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13naiveMMKerneliPdS_S_b,@object # @_Z13naiveMMKerneliPdS_S_b
.section .rodata,"a",@progbits
.globl _Z13naiveMMKerneliPdS_S_b
.p2align 3, 0x0
_Z13naiveMMKerneliPdS_S_b:
.quad _Z28__device_stub__naiveMMKerneliPdS_S_b
.size _Z13naiveMMKerneliPdS_S_b, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "x"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t\t"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13naiveMMKerneliPdS_S_b"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__naiveMMKerneliPdS_S_b
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13naiveMMKerneliPdS_S_b
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13naiveMMKerneliPdS_S_b
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ULDC.S8 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000200 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*0030*/ @!P0 BRA 0xb0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0060*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0070*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R3, R0, c[0x0][0x4], R3 ; /* 0x0000010000037a24 */
/* 0x001fc400078e0203 */
/*0090*/ IMAD R0, R2, c[0x0][0x0], R5 ; /* 0x0000000002007a24 */
/* 0x002fe200078e0205 */
/*00a0*/ BRA 0x220 ; /* 0x0000017000007947 */
/* 0x000fea0003800000 */
/*00b0*/ I2F.U32.RP R0, c[0x0][0x160] ; /* 0x0000580000007b06 */
/* 0x000e220000209000 */
/*00c0*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fc60003f45070 */
/*00e0*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e660000002500 */
/*00f0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e220000001000 */
/*0100*/ IMAD R7, R7, c[0x0][0x0], R4 ; /* 0x0000000007077a24 */
/* 0x002fe200078e0204 */
/*0110*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0140*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a24 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0190*/ IMAD R0, R0, c[0x0][0x160], R7 ; /* 0x0000580000007a24 */
/* 0x000fca00078e0207 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R0, R0, -c[0x0][0x160], RZ ; /* 0x8000580000000a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff03aa12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R0, -R3, RZ, RZ ; /* 0x000000ff03007210 */
/* 0x000fca0007ffe1ff */
/*0210*/ IMAD R0, R0, c[0x0][0x160], R7 ; /* 0x0000580000007a24 */
/* 0x000fca00078e0207 */
/*0220*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06270 */
/*0230*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x160], P0 ; /* 0x0000580003007a0c */
/* 0x000fda0000706670 */
/*0240*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0250*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0260*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0270*/ IMAD R3, R3, c[0x0][0x160], RZ ; /* 0x0000580003037a24 */
/* 0x000fe200078e02ff */
/*0280*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0290*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*02a0*/ @!P0 BRA 0xdf0 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*02c0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*02d0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*02e0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*02f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd800078e00ff */
/*0300*/ @!P0 BRA 0xcb0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0310*/ IADD3 R26, -R5, c[0x0][0x160], RZ ; /* 0x00005800051a7a10 */
/* 0x000fe20007ffe1ff */
/*0320*/ HFMA2.MMA R23, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff177435 */
/* 0x000fe200000001ff */
/*0330*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0340*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*0350*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0360*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fcc0003f04270 */
/*0370*/ IMAD.WIDE R22, R0, R23, c[0x0][0x170] ; /* 0x00005c0000167625 */
/* 0x000fce00078e0217 */
/*0380*/ @!P0 BRA 0xb20 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*03a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*03b0*/ @!P1 BRA 0x860 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*03c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03d0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*03e0*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*03f0*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0400*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0410*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0420*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0430*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0440*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*0450*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*0460*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0470*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0480*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0490*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*04a0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*04b0*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*04c0*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*04d0*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*04e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*04f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0500*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0510*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0520*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0530*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0540*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0550*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*0560*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*0570*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*0580*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*0590*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*05a0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*05b0*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*05c0*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*05d0*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*05e0*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*05f0*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0600*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0610*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0620*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0630*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0640*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*0650*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*0660*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*0670*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*0680*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*0690*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*06a0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*06b0*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*06c0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*06d0*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*06e0*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*06f0*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0700*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0710*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0720*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0730*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0740*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*0750*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*0760*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*0770*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*0780*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*0790*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*07a0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*07b0*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*07c0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*07d0*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*07e0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*07f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0800*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0810*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0820*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0830*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0840*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*0850*/ @P1 BRA 0x3d0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0860*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*0870*/ @!P1 BRA 0xb00 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0880*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0890*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*08a0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea6000c1e1b00 */
/*08b0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*08c0*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*08d0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*08e0*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*08f0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0900*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0910*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0920*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0930*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0940*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*0950*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*0960*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0970*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*0980*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*0990*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*09a0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*09b0*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*09c0*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*09d0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*09e0*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*09f0*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0a00*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0a10*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0a20*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0a30*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0a40*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0a50*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*0a60*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*0a70*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*0a80*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0a90*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0aa0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0ae0*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0af0*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0b00*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0b10*/ @!P0 BRA 0xcb0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0b20*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0b30*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a2000c1e1b00 */
/*0b40*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0b50*/ IMAD.WIDE R10, R2, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x000fc800078e0216 */
/*0b60*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fe200078e021c */
/*0b70*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0010e8000c1e1b00 */
/*0b80*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*0b90*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*0ba0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f28000c1e1b00 */
/*0bb0*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001ee8000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000128000c1e1b00 */
/*0bd0*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f62000c1e1b00 */
/*0be0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x001fca00078e0210 */
/*0bf0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0c00*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0c10*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0c20*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0c30*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0c40*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c50*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004ecc0000000008 */
/*0c60*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x008f0c0000000016 */
/*0c70*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x010f620000000006 */
/*0c80*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0c90*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0ca0*/ @P0 BRA 0xb20 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 BRA 0xdf0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0cd0*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0ce0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe400078e00ff */
/*0cf0*/ IMAD R4, R4, c[0x0][0x160], R0 ; /* 0x0000580004047a24 */
/* 0x000fe400078e0200 */
/*0d00*/ IMAD.WIDE R6, R6, R11, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e020b */
/*0d10*/ IMAD.WIDE R10, R4, R11, c[0x0][0x170] ; /* 0x00005c00040a7625 */
/* 0x000fe200078e020b */
/*0d20*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0d30*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc80000000f00 */
/*0d40*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x001fe20000000f00 */
/*0d50*/ IMAD.MOV.U32 R13, RZ, RZ, R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000f */
/*0d60*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0d70*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0d80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0d90*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0da0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0db0*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0dc0*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0dd0*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0de0*/ @P0 BRA 0xd40 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0df0*/ IADD3 R3, R3, R0, RZ ; /* 0x0000000003037210 */
/* 0x000fe40007ffe0ff */
/*0e00*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0e10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fca00078e0202 */
/*0e20*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13naiveMMKerneliPdS_S_b
.globl _Z13naiveMMKerneliPdS_S_b
.p2align 8
.type _Z13naiveMMKerneliPdS_S_b,@function
_Z13naiveMMKerneliPdS_S_b:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 1
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_cmp_eq_u32 s3, 0
s_mov_b32 s3, 0
s_cbranch_scc0 .LBB0_2
v_cvt_f32_u32_e32 v1, s2
s_load_b32 s6, s[4:5], 0xc
s_sub_i32 s7, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v4, v1
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s7, v4
v_mul_hi_u32 v5, v4, v2
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v4, v5
v_mul_hi_u32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v1, s2
v_add_nc_u32_e32 v4, 1, v1
v_sub_nc_u32_e32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v5, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v1, s2
v_sub_nc_u32_e32 v2, v2, v3
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_3
s_branch .LBB0_4
.LBB0_2:
.LBB0_3:
s_load_b32 s3, s[4:5], 0xc
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s3, v[0:1]
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v1, v2
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_10
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_8
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v5, v1, s2
v_ashrrev_i32_e32 v3, 31, v2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 3, v[2:3]
v_mov_b32_e32 v3, 0
v_ashrrev_i32_e32 v6, 31, v5
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v10, vcc_lo
s_lshl_b64 s[4:5], s[2:3], 3
s_mov_b32 s3, s2
.LBB0_7:
global_load_b64 v[9:10], v[7:8], off
global_load_b64 v[11:12], v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[9:10], v[11:12], v[3:4]
s_cbranch_scc0 .LBB0_7
s_branch .LBB0_9
.LBB0_8:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, s2, v[2:3]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13naiveMMKerneliPdS_S_b
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13naiveMMKerneliPdS_S_b, .Lfunc_end0-_Z13naiveMMKerneliPdS_S_b
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 1
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13naiveMMKerneliPdS_S_b
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13naiveMMKerneliPdS_S_b.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00073350_00000000-6_NaiveMatrixMulti.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b
.type _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b, @function
_Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movb %r8b, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13naiveMMKerneliPdS_S_b(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b, .-_Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b
.globl _Z13naiveMMKerneliPdS_S_b
.type _Z13naiveMMKerneliPdS_S_b, @function
_Z13naiveMMKerneliPdS_S_b:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13naiveMMKerneliPdS_S_b, .-_Z13naiveMMKerneliPdS_S_b
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "x"
.LC1:
.string "\t\t"
.text
.globl _Z7naiveMMiPdS_S_b
.type _Z7naiveMMiPdS_S_b, @function
_Z7naiveMMiPdS_S_b:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r12d
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, %r15d
movl $1, 48(%rsp)
movl $1, 60(%rsp)
testb %r8b, %r8b
je .L12
leal 62(%rdi), %ebx
movl %edi, %eax
addl $31, %eax
cmovns %eax, %ebx
sarl $5, %ebx
movl %ebx, %ebp
movl $32, %r13d
movl $32, %r14d
.L13:
movl %ebp, 40(%rsp)
movl %ebx, 44(%rsp)
movl %r14d, 52(%rsp)
movl %r13d, 56(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
call cudaThreadSynchronize@PLT
movl %r14d, %esi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %r15
movl $1, %edx
leaq .LC0(%rip), %r12
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %r15, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl %edi, %eax
imull %edi, %eax
leal 2046(%rax), %ebp
addl $1023, %eax
cmovns %eax, %ebp
sarl $10, %ebp
movl $1, %r13d
movl $1024, %r14d
movl $1, %ebx
jmp .L13
.L16:
movzbl %r15b, %r8d
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl %r12d, %edi
call _Z39__device_stub__Z13naiveMMKerneliPdS_S_biPdS_S_b
jmp .L14
.cfi_endproc
.LFE3669:
.size _Z7naiveMMiPdS_S_b, .-_Z7naiveMMiPdS_S_b
.section .rodata.str1.1
.LC2:
.string "_Z13naiveMMKerneliPdS_S_b"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13naiveMMKerneliPdS_S_b(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NaiveMatrixMulti.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__naiveMMKerneliPdS_S_b # -- Begin function _Z28__device_stub__naiveMMKerneliPdS_S_b
.p2align 4, 0x90
.type _Z28__device_stub__naiveMMKerneliPdS_S_b,@function
_Z28__device_stub__naiveMMKerneliPdS_S_b: # @_Z28__device_stub__naiveMMKerneliPdS_S_b
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movb %r8b, 3(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 3(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13naiveMMKerneliPdS_S_b, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__naiveMMKerneliPdS_S_b, .Lfunc_end0-_Z28__device_stub__naiveMMKerneliPdS_S_b
.cfi_endproc
# -- End function
.globl _Z7naiveMMiPdS_S_b # -- Begin function _Z7naiveMMiPdS_S_b
.p2align 4, 0x90
.type _Z7naiveMMiPdS_S_b,@function
_Z7naiveMMiPdS_S_b: # @_Z7naiveMMiPdS_S_b
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movq %rcx, 16(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movl %edi, %r15d
movabsq $4294967296, %rbx # imm = 0x100000000
testl %r8d, %r8d
je .LBB1_2
# %bb.1:
leal 31(%r15), %eax
leal 62(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
incq %rbx
imulq %rcx, %rbx
movabsq $137438953504, %r14 # imm = 0x2000000020
jmp .LBB1_3
.LBB1_2:
movl %r15d, %eax
imull %eax, %eax
addl $1023, %eax # imm = 0x3FF
shrl $10, %eax
orq %rbx, %rax
addq $1024, %rbx # imm = 0x400
movq %rbx, %r14
movq %rax, %rbx
.LBB1_3:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movl %r15d, 12(%rsp)
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movb %bpl, 11(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 11(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13naiveMMKerneliPdS_S_b, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
callq hipDeviceSynchronize
movl %r14d, %esi
andl $1056, %esi # imm = 0x420
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
shrq $32, %r14
movq %r15, %rdi
movq %r14, %rsi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %esi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
shrq $32, %rbx
movq %r14, %rdi
movq %rbx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7naiveMMiPdS_S_b, .Lfunc_end1-_Z7naiveMMiPdS_S_b
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13naiveMMKerneliPdS_S_b, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13naiveMMKerneliPdS_S_b,@object # @_Z13naiveMMKerneliPdS_S_b
.section .rodata,"a",@progbits
.globl _Z13naiveMMKerneliPdS_S_b
.p2align 3, 0x0
_Z13naiveMMKerneliPdS_S_b:
.quad _Z28__device_stub__naiveMMKerneliPdS_S_b
.size _Z13naiveMMKerneliPdS_S_b, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "x"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t\t"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13naiveMMKerneliPdS_S_b"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__naiveMMKerneliPdS_S_b
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13naiveMMKerneliPdS_S_b
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void mul1(int *A, int *B, int *C, int n, int q){
int id = threadIdx.x, i,j;
for(i=0;i<q;i++){
C[id*q+i] = 0;
for(j=0;j<n;j++)
C[id*q+i] += A[id*n+j] * B[j*q+i];
}
}
__global__ void mul2(int *A, int *B, int *C, int m, int q){
int id = threadIdx.x, i, j, n = blockDim.x;
for(i=0;i<m;i++){
C[i*q+id] = 0;
for(j=0;j<n;j++)
C[i*q+id] += A[i*n+j] * B[j*q+id];
}
}
__global__ void mul3(int *A, int *B, int *C, int n){
int bid = blockIdx.x, tid = threadIdx.x, q = blockDim.x,i;
C[bid*q+tid] = 0;
for(i=0;i<n;i++)
C[bid*q+tid] += A[bid*n+i] * B[i*q+tid];
}
int main(){
int *a,*b,*c,*da,*db,*dc,m,n,p,q,i,j;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size1 = sizeof(int)*m*n;
a = (int *)malloc(size1);
printf("Enter first matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
printf("Enter p: ");
scanf("%d",&p);
printf("Enter q: ");
scanf("%d",&q);
int size2 = sizeof(int)*p*q;
b = (int *)malloc(size2);
printf("Enter second matrix:\n");
for(i=0;i<p*q;i++)
scanf("%d",&b[i]);
if(n!=p){
printf("%d != %d. Cannot multiply.\n",n,p);
exit(0);
}
int size3 = sizeof(int)*m*q;
c = (int *)malloc(size3);
cudaMalloc((void **)&da,size1);
cudaMalloc((void **)&db,size2);
cudaMalloc((void **)&dc,size3);
cudaMemcpy(da,a,size1,cudaMemcpyHostToDevice);
cudaMemcpy(db,b,size2,cudaMemcpyHostToDevice);
printf("Result 1)Thread per row:\n");
mul1<<<1,m>>>(da,db,dc,n,q);
cudaMemcpy(c,dc,size3,cudaMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 2)Thread per column:\n");
mul2<<<1,n>>>(da,db,dc,m,q);
cudaMemcpy(c,dc,size3,cudaMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 3)Thread per element:\n");
mul3<<<m,q>>>(da,db,dc,n);
cudaMemcpy(c,dc,size3,cudaMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
cudaFree(da);
cudaFree(db);
cudaFree(dc);
return 0;
} | .file "tmpxft_00054d3a_00000000-6_q3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii
.type _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii, @function
_Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4mul1PiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii, .-_Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii
.globl _Z4mul1PiS_S_ii
.type _Z4mul1PiS_S_ii, @function
_Z4mul1PiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4mul1PiS_S_ii, .-_Z4mul1PiS_S_ii
.globl _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii
.type _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii, @function
_Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4mul2PiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii, .-_Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii
.globl _Z4mul2PiS_S_ii
.type _Z4mul2PiS_S_ii, @function
_Z4mul2PiS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4mul2PiS_S_ii, .-_Z4mul2PiS_S_ii
.globl _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i
.type _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i, @function
_Z28__device_stub__Z4mul3PiS_S_iPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4mul3PiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i, .-_Z28__device_stub__Z4mul3PiS_S_iPiS_S_i
.globl _Z4mul3PiS_S_i
.type _Z4mul3PiS_S_i, @function
_Z4mul3PiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z4mul3PiS_S_i, .-_Z4mul3PiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter m: "
.LC1:
.string "%d"
.LC2:
.string "Enter n: "
.LC3:
.string "Enter first matrix:\n"
.LC4:
.string "Enter p: "
.LC5:
.string "Enter q: "
.LC6:
.string "Enter second matrix:\n"
.LC7:
.string "%d != %d. Cannot multiply.\n"
.LC8:
.string "Result 1)Thread per row:\n"
.LC9:
.string "%d "
.LC10:
.string "\n"
.LC11:
.string "Result 2)Thread per column:\n"
.LC12:
.string "Result 3)Thread per element:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 24(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %r14d
imull 24(%rsp), %r14d
sall $2, %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %eax
imull 28(%rsp), %eax
testl %eax, %eax
jle .L28
movq %r15, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L29:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 24(%rsp), %eax
imull 28(%rsp), %eax
cmpl %ebx, %eax
jg .L29
.L28:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 36(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 36(%rsp), %r13d
imull 32(%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 8(%rsp)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rsp), %ecx
movl 36(%rsp), %eax
movl %ecx, %edx
imull %eax, %edx
testl %edx, %edx
jle .L30
movl $0, %ebx
leaq .LC1(%rip), %r12
.L31:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 32(%rsp), %ecx
movl 36(%rsp), %eax
addq $4, %rbp
movl %ecx, %edx
imull %eax, %edx
cmpl %ebx, %edx
jg .L31
.L30:
movl 28(%rsp), %edx
cmpl %ecx, %edx
je .L32
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L32:
imull 24(%rsp), %eax
leal 0(,%rax,4), %ebp
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L33:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r13d
leaq .LC9(%rip), %r14
leaq .LC10(%rip), %r15
cmpl $0, 24(%rsp)
jg .L34
.L35:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L38:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r13d
leaq .LC9(%rip), %r14
leaq .LC10(%rip), %r15
cmpl $0, 24(%rsp)
jg .L39
.L40:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 36(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 24(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L43:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
leaq .LC9(%rip), %r13
leaq .LC10(%rip), %r14
cmpl $0, 24(%rsp)
jg .L44
.L45:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L70
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movl 36(%rsp), %r8d
movl 28(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii
jmp .L33
.L36:
imull %r13d, %eax
addl %r12d, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
movl 36(%rsp), %eax
cmpl %r12d, %eax
jg .L36
.L37:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
cmpl %r13d, 24(%rsp)
jle .L35
.L34:
movl 36(%rsp), %eax
movl $0, %r12d
testl %eax, %eax
jg .L36
jmp .L37
.L68:
movl 36(%rsp), %r8d
movl 24(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii
jmp .L38
.L41:
imull %r13d, %eax
addl %r12d, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
movl 36(%rsp), %eax
cmpl %r12d, %eax
jg .L41
.L42:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
cmpl %r13d, 24(%rsp)
jle .L40
.L39:
movl 36(%rsp), %eax
movl $0, %r12d
testl %eax, %eax
jg .L41
jmp .L42
.L69:
movl 28(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i
jmp .L43
.L46:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 36(%rsp), %eax
cmpl %ebp, %eax
jg .L46
.L47:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 24(%rsp)
jle .L45
.L44:
movl 36(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L46
jmp .L47
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z4mul3PiS_S_i"
.LC14:
.string "_Z4mul2PiS_S_ii"
.LC15:
.string "_Z4mul1PiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mul3PiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mul2PiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mul1PiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void mul1(int *A, int *B, int *C, int n, int q){
int id = threadIdx.x, i,j;
for(i=0;i<q;i++){
C[id*q+i] = 0;
for(j=0;j<n;j++)
C[id*q+i] += A[id*n+j] * B[j*q+i];
}
}
__global__ void mul2(int *A, int *B, int *C, int m, int q){
int id = threadIdx.x, i, j, n = blockDim.x;
for(i=0;i<m;i++){
C[i*q+id] = 0;
for(j=0;j<n;j++)
C[i*q+id] += A[i*n+j] * B[j*q+id];
}
}
__global__ void mul3(int *A, int *B, int *C, int n){
int bid = blockIdx.x, tid = threadIdx.x, q = blockDim.x,i;
C[bid*q+tid] = 0;
for(i=0;i<n;i++)
C[bid*q+tid] += A[bid*n+i] * B[i*q+tid];
}
int main(){
int *a,*b,*c,*da,*db,*dc,m,n,p,q,i,j;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size1 = sizeof(int)*m*n;
a = (int *)malloc(size1);
printf("Enter first matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
printf("Enter p: ");
scanf("%d",&p);
printf("Enter q: ");
scanf("%d",&q);
int size2 = sizeof(int)*p*q;
b = (int *)malloc(size2);
printf("Enter second matrix:\n");
for(i=0;i<p*q;i++)
scanf("%d",&b[i]);
if(n!=p){
printf("%d != %d. Cannot multiply.\n",n,p);
exit(0);
}
int size3 = sizeof(int)*m*q;
c = (int *)malloc(size3);
cudaMalloc((void **)&da,size1);
cudaMalloc((void **)&db,size2);
cudaMalloc((void **)&dc,size3);
cudaMemcpy(da,a,size1,cudaMemcpyHostToDevice);
cudaMemcpy(db,b,size2,cudaMemcpyHostToDevice);
printf("Result 1)Thread per row:\n");
mul1<<<1,m>>>(da,db,dc,n,q);
cudaMemcpy(c,dc,size3,cudaMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 2)Thread per column:\n");
mul2<<<1,n>>>(da,db,dc,m,q);
cudaMemcpy(c,dc,size3,cudaMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 3)Thread per element:\n");
mul3<<<m,q>>>(da,db,dc,n);
cudaMemcpy(c,dc,size3,cudaMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
cudaFree(da);
cudaFree(db);
cudaFree(dc);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void mul1(int *A, int *B, int *C, int n, int q){
int id = threadIdx.x, i,j;
for(i=0;i<q;i++){
C[id*q+i] = 0;
for(j=0;j<n;j++)
C[id*q+i] += A[id*n+j] * B[j*q+i];
}
}
__global__ void mul2(int *A, int *B, int *C, int m, int q){
int id = threadIdx.x, i, j, n = blockDim.x;
for(i=0;i<m;i++){
C[i*q+id] = 0;
for(j=0;j<n;j++)
C[i*q+id] += A[i*n+j] * B[j*q+id];
}
}
__global__ void mul3(int *A, int *B, int *C, int n){
int bid = blockIdx.x, tid = threadIdx.x, q = blockDim.x,i;
C[bid*q+tid] = 0;
for(i=0;i<n;i++)
C[bid*q+tid] += A[bid*n+i] * B[i*q+tid];
}
int main(){
int *a,*b,*c,*da,*db,*dc,m,n,p,q,i,j;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size1 = sizeof(int)*m*n;
a = (int *)malloc(size1);
printf("Enter first matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
printf("Enter p: ");
scanf("%d",&p);
printf("Enter q: ");
scanf("%d",&q);
int size2 = sizeof(int)*p*q;
b = (int *)malloc(size2);
printf("Enter second matrix:\n");
for(i=0;i<p*q;i++)
scanf("%d",&b[i]);
if(n!=p){
printf("%d != %d. Cannot multiply.\n",n,p);
exit(0);
}
int size3 = sizeof(int)*m*q;
c = (int *)malloc(size3);
hipMalloc((void **)&da,size1);
hipMalloc((void **)&db,size2);
hipMalloc((void **)&dc,size3);
hipMemcpy(da,a,size1,hipMemcpyHostToDevice);
hipMemcpy(db,b,size2,hipMemcpyHostToDevice);
printf("Result 1)Thread per row:\n");
mul1<<<1,m>>>(da,db,dc,n,q);
hipMemcpy(c,dc,size3,hipMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 2)Thread per column:\n");
mul2<<<1,n>>>(da,db,dc,m,q);
hipMemcpy(c,dc,size3,hipMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 3)Thread per element:\n");
mul3<<<m,q>>>(da,db,dc,n);
hipMemcpy(c,dc,size3,hipMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
hipFree(da);
hipFree(db);
hipFree(dc);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void mul1(int *A, int *B, int *C, int n, int q){
int id = threadIdx.x, i,j;
for(i=0;i<q;i++){
C[id*q+i] = 0;
for(j=0;j<n;j++)
C[id*q+i] += A[id*n+j] * B[j*q+i];
}
}
__global__ void mul2(int *A, int *B, int *C, int m, int q){
int id = threadIdx.x, i, j, n = blockDim.x;
for(i=0;i<m;i++){
C[i*q+id] = 0;
for(j=0;j<n;j++)
C[i*q+id] += A[i*n+j] * B[j*q+id];
}
}
__global__ void mul3(int *A, int *B, int *C, int n){
int bid = blockIdx.x, tid = threadIdx.x, q = blockDim.x,i;
C[bid*q+tid] = 0;
for(i=0;i<n;i++)
C[bid*q+tid] += A[bid*n+i] * B[i*q+tid];
}
int main(){
int *a,*b,*c,*da,*db,*dc,m,n,p,q,i,j;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size1 = sizeof(int)*m*n;
a = (int *)malloc(size1);
printf("Enter first matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
printf("Enter p: ");
scanf("%d",&p);
printf("Enter q: ");
scanf("%d",&q);
int size2 = sizeof(int)*p*q;
b = (int *)malloc(size2);
printf("Enter second matrix:\n");
for(i=0;i<p*q;i++)
scanf("%d",&b[i]);
if(n!=p){
printf("%d != %d. Cannot multiply.\n",n,p);
exit(0);
}
int size3 = sizeof(int)*m*q;
c = (int *)malloc(size3);
hipMalloc((void **)&da,size1);
hipMalloc((void **)&db,size2);
hipMalloc((void **)&dc,size3);
hipMemcpy(da,a,size1,hipMemcpyHostToDevice);
hipMemcpy(db,b,size2,hipMemcpyHostToDevice);
printf("Result 1)Thread per row:\n");
mul1<<<1,m>>>(da,db,dc,n,q);
hipMemcpy(c,dc,size3,hipMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 2)Thread per column:\n");
mul2<<<1,n>>>(da,db,dc,m,q);
hipMemcpy(c,dc,size3,hipMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 3)Thread per element:\n");
mul3<<<m,q>>>(da,db,dc,n);
hipMemcpy(c,dc,size3,hipMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
hipFree(da);
hipFree(db);
hipFree(dc);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4mul1PiS_S_ii
.globl _Z4mul1PiS_S_ii
.p2align 8
.type _Z4mul1PiS_S_ii,@function
_Z4mul1PiS_S_ii:
s_load_b32 s8, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x2
s_load_b32 s9, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v2, 0
v_mul_lo_u32 v8, v0, s8
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v0, s9
s_cmp_gt_i32 s9, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v0, 0, 1, s0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, 1, v0
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s5, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, s8
s_cbranch_scc0 .LBB0_6
.LBB0_3:
v_add_nc_u32_e32 v1, s1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_and_b32 vcc_lo, exec_lo, s0
global_store_b32 v[0:1], v2, off
s_cbranch_vccnz .LBB0_2
global_load_b32 v7, v[0:1], off
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_mov_b32 s4, s1
s_mov_b32 s10, s9
.p2align 6
.LBB0_5:
s_lshl_b64 s[12:13], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s6, s12
s_addc_u32 s13, s7, s13
global_load_b32 v11, v[5:6], off
global_load_b32 v12, v2, s[12:13]
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s10, s10, -1
s_add_i32 s4, s4, s8
s_cmp_lg_u32 s10, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v12, v11, v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v7, v9
global_store_b32 v[0:1], v9, off
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4mul1PiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 14
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4mul1PiS_S_ii, .Lfunc_end0-_Z4mul1PiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4mul2PiS_S_ii
.globl _Z4mul2PiS_S_ii
.p2align 8
.type _Z4mul2PiS_S_ii,@function
_Z4mul2PiS_S_ii:
s_load_b32 s14, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s14, 1
s_cbranch_scc1 .LBB1_6
s_clause 0x3
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s10, s11
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s3, 0xffff
s_ashr_i32 s3, s2, 31
s_cmp_lg_u32 s1, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0, 1, s0
v_add_co_u32 v1, s0, s6, v1
v_add_co_ci_u32_e64 v2, null, s7, 0, s0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, 1, v3
s_lshl_b64 s[6:7], s[2:3], 2
s_mov_b32 s3, s11
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_add_i32 s3, s3, 1
s_add_i32 s10, s10, s1
s_cmp_lg_u32 s3, s14
s_cbranch_scc0 .LBB1_6
.LBB1_3:
v_mad_u64_u32 v[3:4], null, s3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_and_b32 vcc_lo, exec_lo, s0
global_store_b32 v[3:4], v8, off
s_cbranch_vccnz .LBB1_2
global_load_b32 v7, v[3:4], off
s_lshl_b64 s[12:13], s[10:11], 2
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_mov_b32 s15, s1
.p2align 6
.LBB1_5:
global_load_b32 v11, v8, s[12:13]
global_load_b32 v12, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s6
s_add_i32 s15, s15, -1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_add_u32 s12, s12, 4
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s15, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v12, v11, v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v7, v9
global_store_b32 v[3:4], v9, off
s_cbranch_scc1 .LBB1_5
s_branch .LBB1_2
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4mul2PiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4mul2PiS_S_ii, .Lfunc_end1-_Z4mul2PiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4mul3PiS_S_i
.globl _Z4mul3PiS_S_i
.p2align 8
.type _Z4mul3PiS_S_i,@function
_Z4mul3PiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b32 s2, s[0:1], 0x18
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_store_b32 v[1:2], v6, off
s_cbranch_scc1 .LBB2_3
global_load_b32 v5, v[1:2], off
s_load_b128 s[8:11], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_mul_i32 s0, s15, s2
s_lshl_b32 s4, s4, 2
s_ashr_i32 s1, s0, 31
s_mov_b32 s3, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s5, s10, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s11, 0, s5
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
.p2align 6
.LBB2_2:
global_load_b32 v0, v6, s[0:1]
global_load_b32 v9, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, s4
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v0, v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v5, v7
global_store_b32 v[1:2], v7, off
s_cbranch_scc1 .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4mul3PiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z4mul3PiS_S_i, .Lfunc_end2-_Z4mul3PiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4mul1PiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4mul1PiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4mul2PiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4mul2PiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4mul3PiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4mul3PiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void mul1(int *A, int *B, int *C, int n, int q){
int id = threadIdx.x, i,j;
for(i=0;i<q;i++){
C[id*q+i] = 0;
for(j=0;j<n;j++)
C[id*q+i] += A[id*n+j] * B[j*q+i];
}
}
__global__ void mul2(int *A, int *B, int *C, int m, int q){
int id = threadIdx.x, i, j, n = blockDim.x;
for(i=0;i<m;i++){
C[i*q+id] = 0;
for(j=0;j<n;j++)
C[i*q+id] += A[i*n+j] * B[j*q+id];
}
}
__global__ void mul3(int *A, int *B, int *C, int n){
int bid = blockIdx.x, tid = threadIdx.x, q = blockDim.x,i;
C[bid*q+tid] = 0;
for(i=0;i<n;i++)
C[bid*q+tid] += A[bid*n+i] * B[i*q+tid];
}
int main(){
int *a,*b,*c,*da,*db,*dc,m,n,p,q,i,j;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size1 = sizeof(int)*m*n;
a = (int *)malloc(size1);
printf("Enter first matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
printf("Enter p: ");
scanf("%d",&p);
printf("Enter q: ");
scanf("%d",&q);
int size2 = sizeof(int)*p*q;
b = (int *)malloc(size2);
printf("Enter second matrix:\n");
for(i=0;i<p*q;i++)
scanf("%d",&b[i]);
if(n!=p){
printf("%d != %d. Cannot multiply.\n",n,p);
exit(0);
}
int size3 = sizeof(int)*m*q;
c = (int *)malloc(size3);
hipMalloc((void **)&da,size1);
hipMalloc((void **)&db,size2);
hipMalloc((void **)&dc,size3);
hipMemcpy(da,a,size1,hipMemcpyHostToDevice);
hipMemcpy(db,b,size2,hipMemcpyHostToDevice);
printf("Result 1)Thread per row:\n");
mul1<<<1,m>>>(da,db,dc,n,q);
hipMemcpy(c,dc,size3,hipMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 2)Thread per column:\n");
mul2<<<1,n>>>(da,db,dc,m,q);
hipMemcpy(c,dc,size3,hipMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
printf("Result 3)Thread per element:\n");
mul3<<<m,q>>>(da,db,dc,n);
hipMemcpy(c,dc,size3,hipMemcpyDeviceToHost);
for(i=0;i<m;i++){
for(j=0;j<q;j++)
printf("%d ",c[i*q+j]);
printf("\n");
}
hipFree(da);
hipFree(db);
hipFree(dc);
return 0;
} | .text
.file "q3.hip"
.globl _Z19__device_stub__mul1PiS_S_ii # -- Begin function _Z19__device_stub__mul1PiS_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__mul1PiS_S_ii,@function
_Z19__device_stub__mul1PiS_S_ii: # @_Z19__device_stub__mul1PiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4mul1PiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__mul1PiS_S_ii, .Lfunc_end0-_Z19__device_stub__mul1PiS_S_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__mul2PiS_S_ii # -- Begin function _Z19__device_stub__mul2PiS_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__mul2PiS_S_ii,@function
_Z19__device_stub__mul2PiS_S_ii: # @_Z19__device_stub__mul2PiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4mul2PiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z19__device_stub__mul2PiS_S_ii, .Lfunc_end1-_Z19__device_stub__mul2PiS_S_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__mul3PiS_S_i # -- Begin function _Z19__device_stub__mul3PiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__mul3PiS_S_i,@function
_Z19__device_stub__mul3PiS_S_i: # @_Z19__device_stub__mul3PiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4mul3PiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z19__device_stub__mul3PiS_S_i, .Lfunc_end2-_Z19__device_stub__mul3PiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %eax
imull 16(%rsp), %eax
shll $2, %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
movl $.Lstr, %edi
callq puts@PLT
movl 16(%rsp), %eax
imull 8(%rsp), %eax
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movq %r12, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 8(%rsp), %rax
movslq 16(%rsp), %rcx
imulq %rax, %rcx
addq $4, %rbx
cmpq %rcx, %r14
jl .LBB3_2
.LBB3_3: # %._crit_edge
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 32(%rsp), %eax
imull 12(%rsp), %eax
shll $2, %eax
movslq %eax, %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbp
movl $.Lstr.1, %edi
callq puts@PLT
movl 32(%rsp), %edx
movl 12(%rsp), %eax
movl %eax, %ecx
imull %edx, %ecx
testl %ecx, %ecx
jle .LBB3_6
# %bb.4: # %.lr.ph104.preheader
movq %rbp, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph104
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movl 32(%rsp), %edx
movl 12(%rsp), %eax
movl %eax, %ecx
imull %edx, %ecx
movslq %ecx, %rcx
addq $4, %rbx
cmpq %rcx, %r14
jl .LBB3_5
.LBB3_6: # %._crit_edge105
movl 16(%rsp), %esi
cmpl %edx, %esi
jne .LBB3_32
# %bb.7:
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r12, %rsi
movabsq $4294967296, %r12 # imm = 0x100000000
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %rbp, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl 8(%rsp), %edx
orq %r12, %rdx
leaq 1(%r12), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movl 16(%rsp), %esi
movl 12(%rsp), %edi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 20(%rsp)
movl %edi, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4mul1PiS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp)
jle .LBB3_15
# %bb.10: # %.preheader99.preheader
xorl %ebp, %ebp
jmp .LBB3_11
.p2align 4, 0x90
.LBB3_14: # %._crit_edge109
# in Loop: Header=BB3_11 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB3_15
.LBB3_11: # %.preheader99
# =>This Loop Header: Depth=1
# Child Loop BB3_13 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_14
# %bb.12: # %.lr.ph108.preheader
# in Loop: Header=BB3_11 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_13: # %.lr.ph108
# Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r15, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB3_13
jmp .LBB3_14
.LBB3_15: # %._crit_edge111
movl $.Lstr.3, %edi
callq puts@PLT
movl 16(%rsp), %edx
orq %r12, %rdx
leaq 1(%r12), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movl 8(%rsp), %esi
movl 12(%rsp), %edi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 20(%rsp)
movl %edi, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4mul2PiS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_17:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp)
jle .LBB3_23
# %bb.18: # %.preheader98.preheader
xorl %ebp, %ebp
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_22: # %._crit_edge114
# in Loop: Header=BB3_19 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB3_23
.LBB3_19: # %.preheader98
# =>This Loop Header: Depth=1
# Child Loop BB3_21 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_22
# %bb.20: # %.lr.ph113.preheader
# in Loop: Header=BB3_19 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_21: # %.lr.ph113
# Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r15, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB3_21
jmp .LBB3_22
.LBB3_23: # %._crit_edge116
movl $.Lstr.4, %edi
callq puts@PLT
movl 8(%rsp), %edi
movl 12(%rsp), %edx
orq %r12, %rdi
orq %r12, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_25
# %bb.24:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movl 16(%rsp), %esi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 20(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4mul3PiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_25:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp)
jle .LBB3_31
# %bb.26: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB3_27
.p2align 4, 0x90
.LBB3_30: # %._crit_edge119
# in Loop: Header=BB3_27 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB3_31
.LBB3_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_29 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_30
# %bb.28: # %.lr.ph118.preheader
# in Loop: Header=BB3_27 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_29: # %.lr.ph118
# Parent Loop BB3_27 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB3_29
jmp .LBB3_30
.LBB3_31: # %._crit_edge121
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_32:
.cfi_def_cfa_offset 224
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mul1PiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mul2PiS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mul3PiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4mul1PiS_S_ii,@object # @_Z4mul1PiS_S_ii
.section .rodata,"a",@progbits
.globl _Z4mul1PiS_S_ii
.p2align 3, 0x0
_Z4mul1PiS_S_ii:
.quad _Z19__device_stub__mul1PiS_S_ii
.size _Z4mul1PiS_S_ii, 8
.type _Z4mul2PiS_S_ii,@object # @_Z4mul2PiS_S_ii
.globl _Z4mul2PiS_S_ii
.p2align 3, 0x0
_Z4mul2PiS_S_ii:
.quad _Z19__device_stub__mul2PiS_S_ii
.size _Z4mul2PiS_S_ii, 8
.type _Z4mul3PiS_S_i,@object # @_Z4mul3PiS_S_i
.globl _Z4mul3PiS_S_i
.p2align 3, 0x0
_Z4mul3PiS_S_i:
.quad _Z19__device_stub__mul3PiS_S_i
.size _Z4mul3PiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter m: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Enter n: "
.size .L.str.2, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Enter p: "
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Enter q: "
.size .L.str.5, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d != %d. Cannot multiply.\n"
.size .L.str.7, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d "
.size .L.str.9, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4mul1PiS_S_ii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4mul2PiS_S_ii"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z4mul3PiS_S_i"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter first matrix:"
.size .Lstr, 20
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter second matrix:"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Result 1)Thread per row:"
.size .Lstr.2, 25
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Result 2)Thread per column:"
.size .Lstr.3, 28
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Result 3)Thread per element:"
.size .Lstr.4, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__mul1PiS_S_ii
.addrsig_sym _Z19__device_stub__mul2PiS_S_ii
.addrsig_sym _Z19__device_stub__mul3PiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4mul1PiS_S_ii
.addrsig_sym _Z4mul2PiS_S_ii
.addrsig_sym _Z4mul3PiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00054d3a_00000000-6_q3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii
.type _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii, @function
_Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4mul1PiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii, .-_Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii
.globl _Z4mul1PiS_S_ii
.type _Z4mul1PiS_S_ii, @function
_Z4mul1PiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4mul1PiS_S_ii, .-_Z4mul1PiS_S_ii
.globl _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii
.type _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii, @function
_Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4mul2PiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii, .-_Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii
.globl _Z4mul2PiS_S_ii
.type _Z4mul2PiS_S_ii, @function
_Z4mul2PiS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4mul2PiS_S_ii, .-_Z4mul2PiS_S_ii
.globl _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i
.type _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i, @function
_Z28__device_stub__Z4mul3PiS_S_iPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4mul3PiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i, .-_Z28__device_stub__Z4mul3PiS_S_iPiS_S_i
.globl _Z4mul3PiS_S_i
.type _Z4mul3PiS_S_i, @function
_Z4mul3PiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z4mul3PiS_S_i, .-_Z4mul3PiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter m: "
.LC1:
.string "%d"
.LC2:
.string "Enter n: "
.LC3:
.string "Enter first matrix:\n"
.LC4:
.string "Enter p: "
.LC5:
.string "Enter q: "
.LC6:
.string "Enter second matrix:\n"
.LC7:
.string "%d != %d. Cannot multiply.\n"
.LC8:
.string "Result 1)Thread per row:\n"
.LC9:
.string "%d "
.LC10:
.string "\n"
.LC11:
.string "Result 2)Thread per column:\n"
.LC12:
.string "Result 3)Thread per element:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 24(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %r14d
imull 24(%rsp), %r14d
sall $2, %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %eax
imull 28(%rsp), %eax
testl %eax, %eax
jle .L28
movq %r15, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L29:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 24(%rsp), %eax
imull 28(%rsp), %eax
cmpl %ebx, %eax
jg .L29
.L28:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 36(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 36(%rsp), %r13d
imull 32(%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 8(%rsp)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rsp), %ecx
movl 36(%rsp), %eax
movl %ecx, %edx
imull %eax, %edx
testl %edx, %edx
jle .L30
movl $0, %ebx
leaq .LC1(%rip), %r12
.L31:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 32(%rsp), %ecx
movl 36(%rsp), %eax
addq $4, %rbp
movl %ecx, %edx
imull %eax, %edx
cmpl %ebx, %edx
jg .L31
.L30:
movl 28(%rsp), %edx
cmpl %ecx, %edx
je .L32
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L32:
imull 24(%rsp), %eax
leal 0(,%rax,4), %ebp
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L33:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r13d
leaq .LC9(%rip), %r14
leaq .LC10(%rip), %r15
cmpl $0, 24(%rsp)
jg .L34
.L35:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L38:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r13d
leaq .LC9(%rip), %r14
leaq .LC10(%rip), %r15
cmpl $0, 24(%rsp)
jg .L39
.L40:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 36(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 24(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L43:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
leaq .LC9(%rip), %r13
leaq .LC10(%rip), %r14
cmpl $0, 24(%rsp)
jg .L44
.L45:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L70
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movl 36(%rsp), %r8d
movl 28(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z4mul1PiS_S_iiPiS_S_ii
jmp .L33
.L36:
imull %r13d, %eax
addl %r12d, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
movl 36(%rsp), %eax
cmpl %r12d, %eax
jg .L36
.L37:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
cmpl %r13d, 24(%rsp)
jle .L35
.L34:
movl 36(%rsp), %eax
movl $0, %r12d
testl %eax, %eax
jg .L36
jmp .L37
.L68:
movl 36(%rsp), %r8d
movl 24(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z4mul2PiS_S_iiPiS_S_ii
jmp .L38
.L41:
imull %r13d, %eax
addl %r12d, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
movl 36(%rsp), %eax
cmpl %r12d, %eax
jg .L41
.L42:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
cmpl %r13d, 24(%rsp)
jle .L40
.L39:
movl 36(%rsp), %eax
movl $0, %r12d
testl %eax, %eax
jg .L41
jmp .L42
.L69:
movl 28(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z28__device_stub__Z4mul3PiS_S_iPiS_S_i
jmp .L43
.L46:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 36(%rsp), %eax
cmpl %ebp, %eax
jg .L46
.L47:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 24(%rsp)
jle .L45
.L44:
movl 36(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L46
jmp .L47
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z4mul3PiS_S_i"
.LC14:
.string "_Z4mul2PiS_S_ii"
.LC15:
.string "_Z4mul1PiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mul3PiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mul2PiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mul1PiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q3.hip"
.globl _Z19__device_stub__mul1PiS_S_ii # -- Begin function _Z19__device_stub__mul1PiS_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__mul1PiS_S_ii,@function
_Z19__device_stub__mul1PiS_S_ii: # @_Z19__device_stub__mul1PiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4mul1PiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__mul1PiS_S_ii, .Lfunc_end0-_Z19__device_stub__mul1PiS_S_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__mul2PiS_S_ii # -- Begin function _Z19__device_stub__mul2PiS_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__mul2PiS_S_ii,@function
_Z19__device_stub__mul2PiS_S_ii: # @_Z19__device_stub__mul2PiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4mul2PiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z19__device_stub__mul2PiS_S_ii, .Lfunc_end1-_Z19__device_stub__mul2PiS_S_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__mul3PiS_S_i # -- Begin function _Z19__device_stub__mul3PiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__mul3PiS_S_i,@function
_Z19__device_stub__mul3PiS_S_i: # @_Z19__device_stub__mul3PiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4mul3PiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z19__device_stub__mul3PiS_S_i, .Lfunc_end2-_Z19__device_stub__mul3PiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %eax
imull 16(%rsp), %eax
shll $2, %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
movl $.Lstr, %edi
callq puts@PLT
movl 16(%rsp), %eax
imull 8(%rsp), %eax
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movq %r12, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 8(%rsp), %rax
movslq 16(%rsp), %rcx
imulq %rax, %rcx
addq $4, %rbx
cmpq %rcx, %r14
jl .LBB3_2
.LBB3_3: # %._crit_edge
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 32(%rsp), %eax
imull 12(%rsp), %eax
shll $2, %eax
movslq %eax, %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbp
movl $.Lstr.1, %edi
callq puts@PLT
movl 32(%rsp), %edx
movl 12(%rsp), %eax
movl %eax, %ecx
imull %edx, %ecx
testl %ecx, %ecx
jle .LBB3_6
# %bb.4: # %.lr.ph104.preheader
movq %rbp, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph104
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movl 32(%rsp), %edx
movl 12(%rsp), %eax
movl %eax, %ecx
imull %edx, %ecx
movslq %ecx, %rcx
addq $4, %rbx
cmpq %rcx, %r14
jl .LBB3_5
.LBB3_6: # %._crit_edge105
movl 16(%rsp), %esi
cmpl %edx, %esi
jne .LBB3_32
# %bb.7:
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r12, %rsi
movabsq $4294967296, %r12 # imm = 0x100000000
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %rbp, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl 8(%rsp), %edx
orq %r12, %rdx
leaq 1(%r12), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movl 16(%rsp), %esi
movl 12(%rsp), %edi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 20(%rsp)
movl %edi, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4mul1PiS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp)
jle .LBB3_15
# %bb.10: # %.preheader99.preheader
xorl %ebp, %ebp
jmp .LBB3_11
.p2align 4, 0x90
.LBB3_14: # %._crit_edge109
# in Loop: Header=BB3_11 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB3_15
.LBB3_11: # %.preheader99
# =>This Loop Header: Depth=1
# Child Loop BB3_13 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_14
# %bb.12: # %.lr.ph108.preheader
# in Loop: Header=BB3_11 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_13: # %.lr.ph108
# Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r15, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB3_13
jmp .LBB3_14
.LBB3_15: # %._crit_edge111
movl $.Lstr.3, %edi
callq puts@PLT
movl 16(%rsp), %edx
orq %r12, %rdx
leaq 1(%r12), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movl 8(%rsp), %esi
movl 12(%rsp), %edi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 20(%rsp)
movl %edi, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4mul2PiS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_17:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp)
jle .LBB3_23
# %bb.18: # %.preheader98.preheader
xorl %ebp, %ebp
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_22: # %._crit_edge114
# in Loop: Header=BB3_19 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB3_23
.LBB3_19: # %.preheader98
# =>This Loop Header: Depth=1
# Child Loop BB3_21 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_22
# %bb.20: # %.lr.ph113.preheader
# in Loop: Header=BB3_19 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_21: # %.lr.ph113
# Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r15, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB3_21
jmp .LBB3_22
.LBB3_23: # %._crit_edge116
movl $.Lstr.4, %edi
callq puts@PLT
movl 8(%rsp), %edi
movl 12(%rsp), %edx
orq %r12, %rdi
orq %r12, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_25
# %bb.24:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movl 16(%rsp), %esi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 20(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4mul3PiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_25:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp)
jle .LBB3_31
# %bb.26: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB3_27
.p2align 4, 0x90
.LBB3_30: # %._crit_edge119
# in Loop: Header=BB3_27 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB3_31
.LBB3_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_29 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_30
# %bb.28: # %.lr.ph118.preheader
# in Loop: Header=BB3_27 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_29: # %.lr.ph118
# Parent Loop BB3_27 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB3_29
jmp .LBB3_30
.LBB3_31: # %._crit_edge121
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_32:
.cfi_def_cfa_offset 224
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mul1PiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mul2PiS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mul3PiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4mul1PiS_S_ii,@object # @_Z4mul1PiS_S_ii
.section .rodata,"a",@progbits
.globl _Z4mul1PiS_S_ii
.p2align 3, 0x0
_Z4mul1PiS_S_ii:
.quad _Z19__device_stub__mul1PiS_S_ii
.size _Z4mul1PiS_S_ii, 8
.type _Z4mul2PiS_S_ii,@object # @_Z4mul2PiS_S_ii
.globl _Z4mul2PiS_S_ii
.p2align 3, 0x0
_Z4mul2PiS_S_ii:
.quad _Z19__device_stub__mul2PiS_S_ii
.size _Z4mul2PiS_S_ii, 8
.type _Z4mul3PiS_S_i,@object # @_Z4mul3PiS_S_i
.globl _Z4mul3PiS_S_i
.p2align 3, 0x0
_Z4mul3PiS_S_i:
.quad _Z19__device_stub__mul3PiS_S_i
.size _Z4mul3PiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter m: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Enter n: "
.size .L.str.2, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Enter p: "
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Enter q: "
.size .L.str.5, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d != %d. Cannot multiply.\n"
.size .L.str.7, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d "
.size .L.str.9, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4mul1PiS_S_ii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4mul2PiS_S_ii"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z4mul3PiS_S_i"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter first matrix:"
.size .Lstr, 20
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter second matrix:"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Result 1)Thread per row:"
.size .Lstr.2, 25
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Result 2)Thread per column:"
.size .Lstr.3, 28
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Result 3)Thread per element:"
.size .Lstr.4, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__mul1PiS_S_ii
.addrsig_sym _Z19__device_stub__mul2PiS_S_ii
.addrsig_sym _Z19__device_stub__mul3PiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4mul1PiS_S_ii
.addrsig_sym _Z4mul2PiS_S_ii
.addrsig_sym _Z4mul3PiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__device__ static int *arrptr;
__device__ static int x;
extern "C" {
__device__ void sub1_()
{
arrptr = (int *) malloc (10);
x = 11;
printf ("sub1: arrptr=%p\n", arrptr);
printf ("sub1: x=%d\n", x);
}
__device__ void sub2_()
{
printf ("sub2: arrptr=%p\n", arrptr);
printf ("sub2: x=%d\n", x);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__device__ static int *arrptr;
__device__ static int x;
extern "C" {
__device__ void sub1_()
{
arrptr = (int *) malloc (10);
x = 11;
printf ("sub1: arrptr=%p\n", arrptr);
printf ("sub1: x=%d\n", x);
}
__device__ void sub2_()
{
printf ("sub2: arrptr=%p\n", arrptr);
printf ("sub2: x=%d\n", x);
}
} | .file "tmpxft_0010f723_00000000-6_subs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl sub1_
.type sub1_, @function
sub1_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size sub1_, .-sub1_
.globl sub2_
.type sub2_, @function
sub2_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size sub2_, .-sub2_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "arrptr"
.LC1:
.string "x"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6arrptr(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1x(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1x
.comm _ZL1x,4,4
.local _ZL6arrptr
.comm _ZL6arrptr,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__device__ static int *arrptr;
__device__ static int x;
extern "C" {
__device__ void sub1_()
{
arrptr = (int *) malloc (10);
x = 11;
printf ("sub1: arrptr=%p\n", arrptr);
printf ("sub1: x=%d\n", x);
}
__device__ void sub2_()
{
printf ("sub2: arrptr=%p\n", arrptr);
printf ("sub2: x=%d\n", x);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ static int *arrptr;
__device__ static int x;
extern "C" {
__device__ void sub1_()
{
arrptr = (int *) malloc (10);
x = 11;
printf ("sub1: arrptr=%p\n", arrptr);
printf ("sub1: x=%d\n", x);
}
__device__ void sub2_()
{
printf ("sub2: arrptr=%p\n", arrptr);
printf ("sub2: x=%d\n", x);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ static int *arrptr;
__device__ static int x;
extern "C" {
__device__ void sub1_()
{
arrptr = (int *) malloc (10);
x = 11;
printf ("sub1: arrptr=%p\n", arrptr);
printf ("sub1: x=%d\n", x);
}
__device__ void sub2_()
{
printf ("sub2: arrptr=%p\n", arrptr);
printf ("sub2: x=%d\n", x);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ static int *arrptr;
__device__ static int x;
extern "C" {
__device__ void sub1_()
{
arrptr = (int *) malloc (10);
x = 11;
printf ("sub1: arrptr=%p\n", arrptr);
printf ("sub1: x=%d\n", x);
}
__device__ void sub2_()
{
printf ("sub2: arrptr=%p\n", arrptr);
printf ("sub2: x=%d\n", x);
}
} | .text
.file "subs.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010f723_00000000-6_subs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl sub1_
.type sub1_, @function
sub1_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size sub1_, .-sub1_
.globl sub2_
.type sub2_, @function
sub2_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size sub2_, .-sub2_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "arrptr"
.LC1:
.string "x"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6arrptr(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1x(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1x
.comm _ZL1x,4,4
.local _ZL6arrptr
.comm _ZL6arrptr,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "subs.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
__global__ void fillMonoThread(int* vector, std::size_t size){
for(std::size_t i=0; i<size; ++i){
vector[i] = 1;
}
}
void testMonoThread(){
std::size_t size = 10;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
cudaMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
fillMonoThread<<<1,1>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
cudaMemcpy(vector_h, vector_d, size*sizeof(int), cudaMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << std::endl;
}
cudaFree(vector_d);
}
__global__ void fillMutliThreads(int* vector, std::size_t size){
vector[threadIdx.x] = threadIdx.x;
}
void testMultiThreads(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
cudaMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliThreads<<<1,size>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
cudaMemcpy(vector_h, vector_d, size*sizeof(int), cudaMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
cudaFree(vector_d);
}
__global__ void fillMutliBlocs(int* vector, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
vector[threadId] = threadId;
}
void testMultiBlocs(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
cudaMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliBlocs<<<2,size/2>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
cudaMemcpy(vector_h, vector_d, size*sizeof(int), cudaMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
cudaFree(vector_d);
}
__global__ void addVector(int* v1, int* v2, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
if(threadId < size){
v1[threadId] += v2[threadId];
}
}
void testAdd(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
cudaError_t cudaError;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
cudaMallocHost(&vector0_h, size * sizeof(int));
cudaMallocHost(&vector1_h, size * sizeof(int));
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
cudaError = cudaMalloc(&vector0_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaError = cudaMalloc(&vector1_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaMemcpy(vector0_d, vector0_h, size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(vector1_d, vector1_h, size * sizeof(int), cudaMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVector<<<grid, block>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
cudaMemcpy(vector0_h, vector0_d, size * sizeof(int), cudaMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
cudaFree(vector0_d);
cudaFree(vector1_d);
cudaFreeHost(vector0_h);
cudaFreeHost(vector1_h);
}
__global__ void addMatrix(int* m1, int* m2, std::size_t width, std::size_t height){
// index of thread in X dim
int threadIdX = blockIdx.x * blockDim.x + threadIdx.x;
// index of thread in Y dim
int threadIdY = blockIdx.y * blockDim.y + threadIdx.y;
if(threadIdX < width && threadIdY < height){
// make a 2D index into 1D
int matrixIndex = width * threadIdY + threadIdX;
m1[matrixIndex] += m2[matrixIndex];
}
}
void testAddMatrice(){
std::size_t const width = 100;
std::size_t const height = 100;
std::size_t const size = width * height;
int* matrix0_h = nullptr;
int* matrix1_h = nullptr;
int* matrix0_d = nullptr;
int* matrix1_d = nullptr;
cudaError_t cudaError;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
cudaMallocHost(&matrix0_h, size * sizeof(int));
cudaMallocHost(&matrix1_h, size * sizeof(int));
// fill matrixs
for(int i=0; i<size; ++i){
matrix0_h[i] = matrix1_h[i] = i;
}
// allocate memory device
cudaError = cudaMalloc(&matrix0_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaError = cudaMalloc(&matrix1_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaMemcpy(matrix0_d, matrix0_h, size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(matrix1_d, matrix1_h, size * sizeof(int), cudaMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32, 32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((width-1)/block.x + 1, (height-1)/block.y + 1);
addMatrix<<<grid, block>>>(matrix0_d, matrix1_d, width, height);
// put back GPU result to CPU
cudaMemcpy(matrix0_h, matrix0_d, size * sizeof(int), cudaMemcpyDeviceToHost);
// check add result matrixs
for(int i=0; i<size; ++i){
std::cout << matrix0_h[i] << ' ' ;
}
// free memory on GPU and CPU
cudaFree(matrix0_d);
cudaFree(matrix1_d);
cudaFreeHost(matrix0_h);
cudaFreeHost(matrix1_h);
}
__global__ void addVectorShared(int* v1, int* v2, std::size_t size){
extern __shared__ int shared[];
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
shared[threadIdx.x] = v2[threadId];
if(threadId < size){
v1[threadId] += shared[threadIdx.x];
}
}
void testAddShared(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
cudaError_t cudaError;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
cudaMallocHost(&vector0_h, size * sizeof(int));
cudaMallocHost(&vector1_h, size * sizeof(int));
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
cudaError = cudaMalloc(&vector0_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaError = cudaMalloc(&vector1_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaMemcpy(vector0_d, vector0_h, size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(vector1_d, vector1_h, size * sizeof(int), cudaMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVectorShared<<<grid, block, block.x * sizeof(int)>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
cudaMemcpy(vector0_h, vector0_d, size * sizeof(int), cudaMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
cudaFree(vector0_d);
cudaFree(vector1_d);
cudaFreeHost(vector0_h);
cudaFreeHost(vector1_h);
}
int main(){
// testMonoThread();
// testMultiThreads();
// testMultiBlocs();
// testAdd();
testAddShared();
return 0;
} | code for sm_80
Function : _Z15addVectorSharedPiS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0090*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fc80000011400 */
/*00a0*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x174], PT, P0 ; /* 0x00005d0007007a0c */
/* 0x000fe20003f06100 */
/*00b0*/ STS [R5.X4], R4 ; /* 0x0000000405007388 */
/* 0x0041d80000004800 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*00e0*/ LEA.HI.X R3, R0, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1407 */
/*00f0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea4000c1e1900 */
/*0100*/ IMAD.IADD R5, R4, 0x1, R5 ; /* 0x0000000104057824 */
/* 0x004fca00078e0205 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addMatrixPiS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f26070 */
/*0070*/ SHF.R.S32.HI R4, RZ, 0x1f, R3 ; /* 0x0000001fff047819 */
/* 0x000fe20000011403 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0205 */
/*0090*/ ISETP.GE.U32.AND.EX P1, PT, R4, c[0x0][0x17c], PT, P1 ; /* 0x00005f0004007a0c */
/* 0x000fe40003f26110 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*00b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*00c0*/ ISETP.GE.U32.OR.EX P0, PT, R2, c[0x0][0x174], P1, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0000f06500 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fe200078e0200 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0110*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0120*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe400078e0205 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addVectorPiS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R2, R0.reuse, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P0, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f1e0ff */
/*00c0*/ IADD3 R2, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe40007f3e0ff */
/*00d0*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe400007fe4ff */
/*00e0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590000037a10 */
/* 0x000fc80000ffe4ff */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IMAD.IADD R7, R0, 0x1, R5 ; /* 0x0000000100077824 */
/* 0x004fca00078e0205 */
/*0120*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14fillMutliBlocsPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16fillMutliThreadsPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x001fca00078e0002 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14fillMonoThreadPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc80003f05070 */
/*0020*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f05300 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0050*/ UMOV UR8, 0x3 ; /* 0x0000000300087882 */
/* 0x000fe20000000000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0080*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe20007f1e1ff */
/*0090*/ ULOP3.LUT UR8, UR8, UR4, URZ, 0xc0, !UPT ; /* 0x0000000408087292 */
/* 0x000fe4000f8ec03f */
/*00a0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*00c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00d0*/ IADD3.X R0, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02007810 */
/* 0x000fe200007fe4ff */
/*00e0*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ ISETP.NE.U32.AND P0, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fc4000bf05070 */
/*0100*/ ISETP.GE.U32.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fe40003f26110 */
/*0110*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0120*/ @!P1 BRA 0x2a0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0130*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe200078e00ff */
/*0150*/ UIADD3 UR6, UP0, UR8, -UR6, URZ ; /* 0x8000000608067290 */
/* 0x000fe2000ff1e03f */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0190*/ UIADD3.X UR7, URZ, ~UR7, URZ, UP0, !UPT ; /* 0x800000073f077290 */
/* 0x000fe400087fe43f */
/*01a0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*01b0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000ff1e03f */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0005 */
/*01e0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc400087fe43f */
/*01f0*/ UIADD3 UR9, UP0, UR4, UR6, URZ ; /* 0x0000000604097290 */
/* 0x000fe2000ff1e03f */
/*0200*/ IADD3 R0, P2, R2, 0x10, RZ ; /* 0x0000001002007810 */
/* 0x000fe20007f5e0ff */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c10190a */
/*0220*/ UIADD3.X UR12, UR5, UR7, URZ, UP0, !UPT ; /* 0x00000007050c7290 */
/* 0x000fe400087fe43f */
/*0230*/ ISETP.NE.U32.AND P1, PT, RZ, UR9, PT ; /* 0x00000009ff007c0c */
/* 0x000fe2000bf25070 */
/*0240*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c10190a */
/*0250*/ IMAD.X R5, RZ, RZ, R3, P2 ; /* 0x000000ffff057224 */
/* 0x000fe400010e0603 */
/*0260*/ ISETP.NE.AND.EX P1, PT, RZ, UR12, PT, P1 ; /* 0x0000000cff007c0c */
/* 0x000fe2000bf25310 */
/*0270*/ STG.E [R2.64+0x8], R7 ; /* 0x0000080702007986 */
/* 0x0001e8000c10190a */
/*0280*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x0001f0000c10190a */
/*0290*/ @P1 BRA 0x1b0 ; /* 0xffffff1000001947 */
/* 0x000fea000383ffff */
/*02a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02b0*/ UIADD3 UR6, UP1, URZ, -UR8, URZ ; /* 0x800000083f067290 */
/* 0x000fe2000ff3e03f */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc400078e00ff */
/*02d0*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe40000000a00 */
/*02e0*/ ULEA UR7, UP0, UR4, UR8, 0x2 ; /* 0x0000000804077291 */
/* 0x000fe4000f80103f */
/*02f0*/ UIADD3.X UR8, URZ, -0x1, URZ, UP1, !UPT ; /* 0xffffffff3f087890 */
/* 0x000fe40008ffe43f */
/*0300*/ ULEA.HI.X UR4, UR4, UR9, UR5, 0x2, UP0 ; /* 0x0000000904047291 */
/* 0x000fc600080f1405 */
/*0310*/ UIADD3 UR6, UP0, UR6, 0x1, URZ ; /* 0x0000000106067890 */
/* 0x000fe2000ff1e03f */
/*0320*/ IMAD.U32 R2, RZ, RZ, UR7 ; /* 0x00000007ff027e24 */
/* 0x001fe4000f8e00ff */
/*0330*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fe2000f8e00ff */
/*0340*/ UIADD3.X UR8, URZ, UR8, URZ, UP0, !UPT ; /* 0x000000083f087290 */
/* 0x000fc400087fe43f */
/*0350*/ ISETP.NE.U32.AND P0, PT, RZ, UR6, PT ; /* 0x00000006ff007c0c */
/* 0x000fe2000bf05070 */
/*0360*/ UIADD3 UR7, UP0, UR7, 0x4, URZ ; /* 0x0000000407077890 */
/* 0x000fe2000ff1e03f */
/*0370*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c10190a */
/*0380*/ ISETP.NE.AND.EX P0, PT, RZ, UR8, PT, P0 ; /* 0x00000008ff007c0c */
/* 0x000fe2000bf05300 */
/*0390*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fd800087fe43f */
/*03a0*/ @P0 BRA 0x310 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
__global__ void fillMonoThread(int* vector, std::size_t size){
for(std::size_t i=0; i<size; ++i){
vector[i] = 1;
}
}
void testMonoThread(){
std::size_t size = 10;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
cudaMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
fillMonoThread<<<1,1>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
cudaMemcpy(vector_h, vector_d, size*sizeof(int), cudaMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << std::endl;
}
cudaFree(vector_d);
}
__global__ void fillMutliThreads(int* vector, std::size_t size){
vector[threadIdx.x] = threadIdx.x;
}
void testMultiThreads(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
cudaMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliThreads<<<1,size>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
cudaMemcpy(vector_h, vector_d, size*sizeof(int), cudaMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
cudaFree(vector_d);
}
__global__ void fillMutliBlocs(int* vector, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
vector[threadId] = threadId;
}
void testMultiBlocs(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
cudaMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliBlocs<<<2,size/2>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
cudaMemcpy(vector_h, vector_d, size*sizeof(int), cudaMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
cudaFree(vector_d);
}
__global__ void addVector(int* v1, int* v2, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
if(threadId < size){
v1[threadId] += v2[threadId];
}
}
void testAdd(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
cudaError_t cudaError;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
cudaMallocHost(&vector0_h, size * sizeof(int));
cudaMallocHost(&vector1_h, size * sizeof(int));
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
cudaError = cudaMalloc(&vector0_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaError = cudaMalloc(&vector1_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaMemcpy(vector0_d, vector0_h, size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(vector1_d, vector1_h, size * sizeof(int), cudaMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVector<<<grid, block>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
cudaMemcpy(vector0_h, vector0_d, size * sizeof(int), cudaMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
cudaFree(vector0_d);
cudaFree(vector1_d);
cudaFreeHost(vector0_h);
cudaFreeHost(vector1_h);
}
__global__ void addMatrix(int* m1, int* m2, std::size_t width, std::size_t height){
// index of thread in X dim
int threadIdX = blockIdx.x * blockDim.x + threadIdx.x;
// index of thread in Y dim
int threadIdY = blockIdx.y * blockDim.y + threadIdx.y;
if(threadIdX < width && threadIdY < height){
// make a 2D index into 1D
int matrixIndex = width * threadIdY + threadIdX;
m1[matrixIndex] += m2[matrixIndex];
}
}
void testAddMatrice(){
std::size_t const width = 100;
std::size_t const height = 100;
std::size_t const size = width * height;
int* matrix0_h = nullptr;
int* matrix1_h = nullptr;
int* matrix0_d = nullptr;
int* matrix1_d = nullptr;
cudaError_t cudaError;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
cudaMallocHost(&matrix0_h, size * sizeof(int));
cudaMallocHost(&matrix1_h, size * sizeof(int));
// fill matrixs
for(int i=0; i<size; ++i){
matrix0_h[i] = matrix1_h[i] = i;
}
// allocate memory device
cudaError = cudaMalloc(&matrix0_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaError = cudaMalloc(&matrix1_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaMemcpy(matrix0_d, matrix0_h, size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(matrix1_d, matrix1_h, size * sizeof(int), cudaMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32, 32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((width-1)/block.x + 1, (height-1)/block.y + 1);
addMatrix<<<grid, block>>>(matrix0_d, matrix1_d, width, height);
// put back GPU result to CPU
cudaMemcpy(matrix0_h, matrix0_d, size * sizeof(int), cudaMemcpyDeviceToHost);
// check add result matrixs
for(int i=0; i<size; ++i){
std::cout << matrix0_h[i] << ' ' ;
}
// free memory on GPU and CPU
cudaFree(matrix0_d);
cudaFree(matrix1_d);
cudaFreeHost(matrix0_h);
cudaFreeHost(matrix1_h);
}
__global__ void addVectorShared(int* v1, int* v2, std::size_t size){
extern __shared__ int shared[];
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
shared[threadIdx.x] = v2[threadId];
if(threadId < size){
v1[threadId] += shared[threadIdx.x];
}
}
void testAddShared(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
cudaError_t cudaError;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
cudaMallocHost(&vector0_h, size * sizeof(int));
cudaMallocHost(&vector1_h, size * sizeof(int));
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
cudaError = cudaMalloc(&vector0_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaError = cudaMalloc(&vector1_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaMemcpy(vector0_d, vector0_h, size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(vector1_d, vector1_h, size * sizeof(int), cudaMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVectorShared<<<grid, block, block.x * sizeof(int)>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
cudaMemcpy(vector0_h, vector0_d, size * sizeof(int), cudaMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
cudaFree(vector0_d);
cudaFree(vector1_d);
cudaFreeHost(vector0_h);
cudaFreeHost(vector1_h);
}
int main(){
// testMonoThread();
// testMultiThreads();
// testMultiBlocs();
// testAdd();
testAddShared();
return 0;
} | .file "tmpxft_0003d711_00000000-6_basic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3678:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14fillMonoThreadPimPim
.type _Z35__device_stub__Z14fillMonoThreadPimPim, @function
_Z35__device_stub__Z14fillMonoThreadPimPim:
.LFB3700:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14fillMonoThreadPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z35__device_stub__Z14fillMonoThreadPimPim, .-_Z35__device_stub__Z14fillMonoThreadPimPim
.globl _Z14fillMonoThreadPim
.type _Z14fillMonoThreadPim, @function
_Z14fillMonoThreadPim:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14fillMonoThreadPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z14fillMonoThreadPim, .-_Z14fillMonoThreadPim
.globl _Z14testMonoThreadv
.type _Z14testMonoThreadv, @function
_Z14testMonoThreadv:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $40, %edi
call _Znam@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %r12
addq $40, %r13
leaq _ZSt4cout(%rip), %r14
jmp .L17
.L21:
movl $10, %esi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z14fillMonoThreadPimPim
jmp .L12
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r12, %r13
je .L23
.L17:
movl (%r12), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L24
cmpb $0, 56(%rbp)
je .L15
movzbl 67(%rbp), %esi
jmp .L16
.L23:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z14testMonoThreadv, .-_Z14testMonoThreadv
.globl _Z37__device_stub__Z16fillMutliThreadsPimPim
.type _Z37__device_stub__Z16fillMutliThreadsPimPim, @function
_Z37__device_stub__Z16fillMutliThreadsPimPim:
.LFB3702:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16fillMutliThreadsPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z37__device_stub__Z16fillMutliThreadsPimPim, .-_Z37__device_stub__Z16fillMutliThreadsPimPim
.globl _Z16fillMutliThreadsPim
.type _Z16fillMutliThreadsPim, @function
_Z16fillMutliThreadsPim:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16fillMutliThreadsPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z16fillMutliThreadsPim, .-_Z16fillMutliThreadsPim
.globl _Z16testMultiThreadsv
.type _Z16testMultiThreadsv, @function
_Z16testMultiThreadsv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4096, %edi
call _Znam@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L35:
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $4096, %rbp
leaq _ZSt4cout(%rip), %r12
jmp .L38
.L42:
movl $1024, %esi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z16fillMutliThreadsPimPim
jmp .L35
.L36:
movl $32, %esi
call _ZNSo3putEc@PLT
.L37:
addq $4, %rbx
cmpq %rbp, %rbx
je .L43
.L38:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 28(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L36
leaq 28(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L37
.L43:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z16testMultiThreadsv, .-_Z16testMultiThreadsv
.globl _Z35__device_stub__Z14fillMutliBlocsPimPim
.type _Z35__device_stub__Z14fillMutliBlocsPimPim, @function
_Z35__device_stub__Z14fillMutliBlocsPimPim:
.LFB3704:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14fillMutliBlocsPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _Z35__device_stub__Z14fillMutliBlocsPimPim, .-_Z35__device_stub__Z14fillMutliBlocsPimPim
.globl _Z14fillMutliBlocsPim
.type _Z14fillMutliBlocsPim, @function
_Z14fillMutliBlocsPim:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14fillMutliBlocsPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _Z14fillMutliBlocsPim, .-_Z14fillMutliBlocsPim
.globl _Z14testMultiBlocsv
.type _Z14testMultiBlocsv, @function
_Z14testMultiBlocsv:
.LFB3671:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4096, %edi
call _Znam@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L54:
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $4096, %rbp
leaq _ZSt4cout(%rip), %r12
jmp .L57
.L61:
movl $1024, %esi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z14fillMutliBlocsPimPim
jmp .L54
.L55:
movl $32, %esi
call _ZNSo3putEc@PLT
.L56:
addq $4, %rbx
cmpq %rbp, %rbx
je .L62
.L57:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 28(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L55
leaq 28(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L56
.L62:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z14testMultiBlocsv, .-_Z14testMultiBlocsv
.globl _Z31__device_stub__Z9addVectorPiS_mPiS_m
.type _Z31__device_stub__Z9addVectorPiS_mPiS_m, @function
_Z31__device_stub__Z9addVectorPiS_mPiS_m:
.LFB3706:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L68
.L64:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L69
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPiS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3706:
.size _Z31__device_stub__Z9addVectorPiS_mPiS_m, .-_Z31__device_stub__Z9addVectorPiS_mPiS_m
.globl _Z9addVectorPiS_m
.type _Z9addVectorPiS_m, @function
_Z9addVectorPiS_m:
.LFB3707:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9addVectorPiS_mPiS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _Z9addVectorPiS_m, .-_Z9addVectorPiS_m
.globl _Z7testAddv
.type _Z7testAddv, @function
_Z7testAddv:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leaq 16(%rsp), %rdi
movl $0, %edx
movl $400, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movl $400, %esi
call cudaHostAlloc@PLT
movl $0, %eax
.L73:
movq 24(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $100, %rax
jne .L73
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L86
leaq 40(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L87
movl $1, %ecx
movl $400, %edx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L88
.L78:
movl $2, %ecx
movl $400, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
jmp .L81
.L86:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq 16+_ZTVSt9exception(%rip), %rax
movq %rax, (%rdi)
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L89
movq _ZNSt9exceptionD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt9exception(%rip), %rsi
call __cxa_throw@PLT
.L89:
call __stack_chk_fail@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq 16+_ZTVSt9exception(%rip), %rax
movq %rax, (%rdi)
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L90
movq _ZNSt9exceptionD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt9exception(%rip), %rsi
call __cxa_throw@PLT
.L90:
call __stack_chk_fail@PLT
.L88:
movl $100, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z31__device_stub__Z9addVectorPiS_mPiS_m
jmp .L78
.L79:
movl $32, %esi
call _ZNSo3putEc@PLT
.L80:
addq $4, %rbx
cmpq $400, %rbx
je .L91
.L81:
movq 16(%rsp), %rax
movl (%rax,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 15(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L79
leaq 15(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L80
.L91:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L92
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L92:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z7testAddv, .-_Z7testAddv
.globl _Z32__device_stub__Z9addMatrixPiS_mmPiS_mm
.type _Z32__device_stub__Z9addMatrixPiS_mmPiS_mm, @function
_Z32__device_stub__Z9addMatrixPiS_mmPiS_mm:
.LFB3708:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L97
.L93:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L98
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L97:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addMatrixPiS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L93
.L98:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size _Z32__device_stub__Z9addMatrixPiS_mmPiS_mm, .-_Z32__device_stub__Z9addMatrixPiS_mmPiS_mm
.globl _Z9addMatrixPiS_mm
.type _Z9addMatrixPiS_mm, @function
_Z9addMatrixPiS_mm:
.LFB3709:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addMatrixPiS_mmPiS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size _Z9addMatrixPiS_mm, .-_Z9addMatrixPiS_mm
.globl _Z14testAddMatricev
.type _Z14testAddMatricev, @function
_Z14testAddMatricev:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leaq 16(%rsp), %rdi
movl $0, %edx
movl $40000, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movl $40000, %esi
call cudaHostAlloc@PLT
movl $0, %eax
.L102:
movq 24(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $10000, %rax
jne .L102
leaq 32(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L115
leaq 40(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L116
movl $1, %ecx
movl $40000, %edx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
movl $4, 60(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L117
.L107:
movl $2, %ecx
movl $40000, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
jmp .L110
.L115:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq 16+_ZTVSt9exception(%rip), %rax
movq %rax, (%rdi)
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L118
movq _ZNSt9exceptionD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt9exception(%rip), %rsi
call __cxa_throw@PLT
.L118:
call __stack_chk_fail@PLT
.L116:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq 16+_ZTVSt9exception(%rip), %rax
movq %rax, (%rdi)
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L119
movq _ZNSt9exceptionD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt9exception(%rip), %rsi
call __cxa_throw@PLT
.L119:
call __stack_chk_fail@PLT
.L117:
movl $100, %ecx
movl $100, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z9addMatrixPiS_mmPiS_mm
jmp .L107
.L108:
movl $32, %esi
call _ZNSo3putEc@PLT
.L109:
addq $4, %rbx
cmpq $40000, %rbx
je .L120
.L110:
movq 16(%rsp), %rax
movl (%rax,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 15(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L108
leaq 15(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L109
.L120:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L121
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L121:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size _Z14testAddMatricev, .-_Z14testAddMatricev
.globl _Z38__device_stub__Z15addVectorSharedPiS_mPiS_m
.type _Z38__device_stub__Z15addVectorSharedPiS_mPiS_m, @function
_Z38__device_stub__Z15addVectorSharedPiS_mPiS_m:
.LFB3710:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L126
.L122:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L127
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L126:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15addVectorSharedPiS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L122
.L127:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3710:
.size _Z38__device_stub__Z15addVectorSharedPiS_mPiS_m, .-_Z38__device_stub__Z15addVectorSharedPiS_mPiS_m
.globl _Z15addVectorSharedPiS_m
.type _Z15addVectorSharedPiS_m, @function
_Z15addVectorSharedPiS_m:
.LFB3711:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15addVectorSharedPiS_mPiS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _Z15addVectorSharedPiS_m, .-_Z15addVectorSharedPiS_m
.globl _Z13testAddSharedv
.type _Z13testAddSharedv, @function
_Z13testAddSharedv:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leaq 16(%rsp), %rdi
movl $0, %edx
movl $400, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movl $400, %esi
call cudaHostAlloc@PLT
movl $0, %eax
.L131:
movq 24(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $100, %rax
jne .L131
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L144
leaq 40(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L145
movl $1, %ecx
movl $400, %edx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $128, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L146
.L136:
movl $2, %ecx
movl $400, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
jmp .L139
.L144:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq 16+_ZTVSt9exception(%rip), %rax
movq %rax, (%rdi)
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L147
movq _ZNSt9exceptionD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt9exception(%rip), %rsi
call __cxa_throw@PLT
.L147:
call __stack_chk_fail@PLT
.L145:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
leaq 16+_ZTVSt9exception(%rip), %rax
movq %rax, (%rdi)
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L148
movq _ZNSt9exceptionD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt9exception(%rip), %rsi
call __cxa_throw@PLT
.L148:
call __stack_chk_fail@PLT
.L146:
movl $100, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z38__device_stub__Z15addVectorSharedPiS_mPiS_m
jmp .L136
.L137:
movl $32, %esi
call _ZNSo3putEc@PLT
.L138:
addq $4, %rbx
cmpq $400, %rbx
je .L149
.L139:
movq 16(%rsp), %rax
movl (%rax,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 15(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L137
leaq 15(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L138
.L149:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L150
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L150:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size _Z13testAddSharedv, .-_Z13testAddSharedv
.globl main
.type main, @function
main:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z13testAddSharedv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15addVectorSharedPiS_m"
.LC1:
.string "_Z9addMatrixPiS_mm"
.LC2:
.string "_Z9addVectorPiS_m"
.LC3:
.string "_Z14fillMutliBlocsPim"
.LC4:
.string "_Z16fillMutliThreadsPim"
.LC5:
.string "_Z14fillMonoThreadPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3713:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15addVectorSharedPiS_m(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addMatrixPiS_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPiS_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14fillMutliBlocsPim(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z16fillMutliThreadsPim(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14fillMonoThreadPim(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3713:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
__global__ void fillMonoThread(int* vector, std::size_t size){
for(std::size_t i=0; i<size; ++i){
vector[i] = 1;
}
}
void testMonoThread(){
std::size_t size = 10;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
cudaMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
fillMonoThread<<<1,1>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
cudaMemcpy(vector_h, vector_d, size*sizeof(int), cudaMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << std::endl;
}
cudaFree(vector_d);
}
__global__ void fillMutliThreads(int* vector, std::size_t size){
vector[threadIdx.x] = threadIdx.x;
}
void testMultiThreads(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
cudaMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliThreads<<<1,size>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
cudaMemcpy(vector_h, vector_d, size*sizeof(int), cudaMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
cudaFree(vector_d);
}
__global__ void fillMutliBlocs(int* vector, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
vector[threadId] = threadId;
}
void testMultiBlocs(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
cudaMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliBlocs<<<2,size/2>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
cudaMemcpy(vector_h, vector_d, size*sizeof(int), cudaMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
cudaFree(vector_d);
}
__global__ void addVector(int* v1, int* v2, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
if(threadId < size){
v1[threadId] += v2[threadId];
}
}
void testAdd(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
cudaError_t cudaError;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
cudaMallocHost(&vector0_h, size * sizeof(int));
cudaMallocHost(&vector1_h, size * sizeof(int));
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
cudaError = cudaMalloc(&vector0_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaError = cudaMalloc(&vector1_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaMemcpy(vector0_d, vector0_h, size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(vector1_d, vector1_h, size * sizeof(int), cudaMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVector<<<grid, block>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
cudaMemcpy(vector0_h, vector0_d, size * sizeof(int), cudaMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
cudaFree(vector0_d);
cudaFree(vector1_d);
cudaFreeHost(vector0_h);
cudaFreeHost(vector1_h);
}
__global__ void addMatrix(int* m1, int* m2, std::size_t width, std::size_t height){
// index of thread in X dim
int threadIdX = blockIdx.x * blockDim.x + threadIdx.x;
// index of thread in Y dim
int threadIdY = blockIdx.y * blockDim.y + threadIdx.y;
if(threadIdX < width && threadIdY < height){
// make a 2D index into 1D
int matrixIndex = width * threadIdY + threadIdX;
m1[matrixIndex] += m2[matrixIndex];
}
}
void testAddMatrice(){
std::size_t const width = 100;
std::size_t const height = 100;
std::size_t const size = width * height;
int* matrix0_h = nullptr;
int* matrix1_h = nullptr;
int* matrix0_d = nullptr;
int* matrix1_d = nullptr;
cudaError_t cudaError;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
cudaMallocHost(&matrix0_h, size * sizeof(int));
cudaMallocHost(&matrix1_h, size * sizeof(int));
// fill matrixs
for(int i=0; i<size; ++i){
matrix0_h[i] = matrix1_h[i] = i;
}
// allocate memory device
cudaError = cudaMalloc(&matrix0_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaError = cudaMalloc(&matrix1_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaMemcpy(matrix0_d, matrix0_h, size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(matrix1_d, matrix1_h, size * sizeof(int), cudaMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32, 32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((width-1)/block.x + 1, (height-1)/block.y + 1);
addMatrix<<<grid, block>>>(matrix0_d, matrix1_d, width, height);
// put back GPU result to CPU
cudaMemcpy(matrix0_h, matrix0_d, size * sizeof(int), cudaMemcpyDeviceToHost);
// check add result matrixs
for(int i=0; i<size; ++i){
std::cout << matrix0_h[i] << ' ' ;
}
// free memory on GPU and CPU
cudaFree(matrix0_d);
cudaFree(matrix1_d);
cudaFreeHost(matrix0_h);
cudaFreeHost(matrix1_h);
}
__global__ void addVectorShared(int* v1, int* v2, std::size_t size){
extern __shared__ int shared[];
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
shared[threadIdx.x] = v2[threadId];
if(threadId < size){
v1[threadId] += shared[threadIdx.x];
}
}
void testAddShared(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
cudaError_t cudaError;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
cudaMallocHost(&vector0_h, size * sizeof(int));
cudaMallocHost(&vector1_h, size * sizeof(int));
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
cudaError = cudaMalloc(&vector0_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaError = cudaMalloc(&vector1_d, size * sizeof(int));
if(cudaError != cudaSuccess){
std::cout << cudaGetErrorString(cudaError) << std::endl;
throw std::exception();
}
cudaMemcpy(vector0_d, vector0_h, size * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(vector1_d, vector1_h, size * sizeof(int), cudaMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVectorShared<<<grid, block, block.x * sizeof(int)>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
cudaMemcpy(vector0_h, vector0_d, size * sizeof(int), cudaMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
cudaFree(vector0_d);
cudaFree(vector1_d);
cudaFreeHost(vector0_h);
cudaFreeHost(vector1_h);
}
int main(){
// testMonoThread();
// testMultiThreads();
// testMultiBlocs();
// testAdd();
testAddShared();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void fillMonoThread(int* vector, std::size_t size){
for(std::size_t i=0; i<size; ++i){
vector[i] = 1;
}
}
void testMonoThread(){
std::size_t size = 10;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
hipMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
fillMonoThread<<<1,1>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
hipMemcpy(vector_h, vector_d, size*sizeof(int), hipMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << std::endl;
}
hipFree(vector_d);
}
__global__ void fillMutliThreads(int* vector, std::size_t size){
vector[threadIdx.x] = threadIdx.x;
}
void testMultiThreads(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
hipMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliThreads<<<1,size>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
hipMemcpy(vector_h, vector_d, size*sizeof(int), hipMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
hipFree(vector_d);
}
__global__ void fillMutliBlocs(int* vector, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
vector[threadId] = threadId;
}
void testMultiBlocs(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
hipMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliBlocs<<<2,size/2>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
hipMemcpy(vector_h, vector_d, size*sizeof(int), hipMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
hipFree(vector_d);
}
__global__ void addVector(int* v1, int* v2, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
if(threadId < size){
v1[threadId] += v2[threadId];
}
}
void testAdd(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
hipError_t hipError_t;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
hipHostMalloc(&vector0_h, size * sizeof(int), hipHostMallocDefault);
hipHostMalloc(&vector1_h, size * sizeof(int), hipHostMallocDefault);
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
hipError_t = hipMalloc(&vector0_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipError_t = hipMalloc(&vector1_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipMemcpy(vector0_d, vector0_h, size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(vector1_d, vector1_h, size * sizeof(int), hipMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVector<<<grid, block>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
hipMemcpy(vector0_h, vector0_d, size * sizeof(int), hipMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
hipFree(vector0_d);
hipFree(vector1_d);
hipHostFree(vector0_h);
hipHostFree(vector1_h);
}
__global__ void addMatrix(int* m1, int* m2, std::size_t width, std::size_t height){
// index of thread in X dim
int threadIdX = blockIdx.x * blockDim.x + threadIdx.x;
// index of thread in Y dim
int threadIdY = blockIdx.y * blockDim.y + threadIdx.y;
if(threadIdX < width && threadIdY < height){
// make a 2D index into 1D
int matrixIndex = width * threadIdY + threadIdX;
m1[matrixIndex] += m2[matrixIndex];
}
}
void testAddMatrice(){
std::size_t const width = 100;
std::size_t const height = 100;
std::size_t const size = width * height;
int* matrix0_h = nullptr;
int* matrix1_h = nullptr;
int* matrix0_d = nullptr;
int* matrix1_d = nullptr;
hipError_t hipError_t;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
hipHostMalloc(&matrix0_h, size * sizeof(int), hipHostMallocDefault);
hipHostMalloc(&matrix1_h, size * sizeof(int), hipHostMallocDefault);
// fill matrixs
for(int i=0; i<size; ++i){
matrix0_h[i] = matrix1_h[i] = i;
}
// allocate memory device
hipError_t = hipMalloc(&matrix0_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipError_t = hipMalloc(&matrix1_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipMemcpy(matrix0_d, matrix0_h, size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(matrix1_d, matrix1_h, size * sizeof(int), hipMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32, 32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((width-1)/block.x + 1, (height-1)/block.y + 1);
addMatrix<<<grid, block>>>(matrix0_d, matrix1_d, width, height);
// put back GPU result to CPU
hipMemcpy(matrix0_h, matrix0_d, size * sizeof(int), hipMemcpyDeviceToHost);
// check add result matrixs
for(int i=0; i<size; ++i){
std::cout << matrix0_h[i] << ' ' ;
}
// free memory on GPU and CPU
hipFree(matrix0_d);
hipFree(matrix1_d);
hipHostFree(matrix0_h);
hipHostFree(matrix1_h);
}
__global__ void addVectorShared(int* v1, int* v2, std::size_t size){
extern __shared__ int shared[];
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
shared[threadIdx.x] = v2[threadId];
if(threadId < size){
v1[threadId] += shared[threadIdx.x];
}
}
void testAddShared(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
hipError_t hipError_t;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
hipHostMalloc(&vector0_h, size * sizeof(int), hipHostMallocDefault);
hipHostMalloc(&vector1_h, size * sizeof(int), hipHostMallocDefault);
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
hipError_t = hipMalloc(&vector0_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipError_t = hipMalloc(&vector1_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipMemcpy(vector0_d, vector0_h, size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(vector1_d, vector1_h, size * sizeof(int), hipMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVectorShared<<<grid, block, block.x * sizeof(int)>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
hipMemcpy(vector0_h, vector0_d, size * sizeof(int), hipMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
hipFree(vector0_d);
hipFree(vector1_d);
hipHostFree(vector0_h);
hipHostFree(vector1_h);
}
int main(){
// testMonoThread();
// testMultiThreads();
// testMultiBlocs();
// testAdd();
testAddShared();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void fillMonoThread(int* vector, std::size_t size){
for(std::size_t i=0; i<size; ++i){
vector[i] = 1;
}
}
void testMonoThread(){
std::size_t size = 10;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
hipMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
fillMonoThread<<<1,1>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
hipMemcpy(vector_h, vector_d, size*sizeof(int), hipMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << std::endl;
}
hipFree(vector_d);
}
__global__ void fillMutliThreads(int* vector, std::size_t size){
vector[threadIdx.x] = threadIdx.x;
}
void testMultiThreads(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
hipMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliThreads<<<1,size>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
hipMemcpy(vector_h, vector_d, size*sizeof(int), hipMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
hipFree(vector_d);
}
__global__ void fillMutliBlocs(int* vector, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
vector[threadId] = threadId;
}
void testMultiBlocs(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
hipMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliBlocs<<<2,size/2>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
hipMemcpy(vector_h, vector_d, size*sizeof(int), hipMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
hipFree(vector_d);
}
__global__ void addVector(int* v1, int* v2, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
if(threadId < size){
v1[threadId] += v2[threadId];
}
}
void testAdd(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
hipError_t hipError_t;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
hipHostMalloc(&vector0_h, size * sizeof(int), hipHostMallocDefault);
hipHostMalloc(&vector1_h, size * sizeof(int), hipHostMallocDefault);
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
hipError_t = hipMalloc(&vector0_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipError_t = hipMalloc(&vector1_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipMemcpy(vector0_d, vector0_h, size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(vector1_d, vector1_h, size * sizeof(int), hipMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVector<<<grid, block>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
hipMemcpy(vector0_h, vector0_d, size * sizeof(int), hipMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
hipFree(vector0_d);
hipFree(vector1_d);
hipHostFree(vector0_h);
hipHostFree(vector1_h);
}
__global__ void addMatrix(int* m1, int* m2, std::size_t width, std::size_t height){
// index of thread in X dim
int threadIdX = blockIdx.x * blockDim.x + threadIdx.x;
// index of thread in Y dim
int threadIdY = blockIdx.y * blockDim.y + threadIdx.y;
if(threadIdX < width && threadIdY < height){
// make a 2D index into 1D
int matrixIndex = width * threadIdY + threadIdX;
m1[matrixIndex] += m2[matrixIndex];
}
}
void testAddMatrice(){
std::size_t const width = 100;
std::size_t const height = 100;
std::size_t const size = width * height;
int* matrix0_h = nullptr;
int* matrix1_h = nullptr;
int* matrix0_d = nullptr;
int* matrix1_d = nullptr;
hipError_t hipError_t;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
hipHostMalloc(&matrix0_h, size * sizeof(int), hipHostMallocDefault);
hipHostMalloc(&matrix1_h, size * sizeof(int), hipHostMallocDefault);
// fill matrixs
for(int i=0; i<size; ++i){
matrix0_h[i] = matrix1_h[i] = i;
}
// allocate memory device
hipError_t = hipMalloc(&matrix0_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipError_t = hipMalloc(&matrix1_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipMemcpy(matrix0_d, matrix0_h, size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(matrix1_d, matrix1_h, size * sizeof(int), hipMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32, 32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((width-1)/block.x + 1, (height-1)/block.y + 1);
addMatrix<<<grid, block>>>(matrix0_d, matrix1_d, width, height);
// put back GPU result to CPU
hipMemcpy(matrix0_h, matrix0_d, size * sizeof(int), hipMemcpyDeviceToHost);
// check add result matrixs
for(int i=0; i<size; ++i){
std::cout << matrix0_h[i] << ' ' ;
}
// free memory on GPU and CPU
hipFree(matrix0_d);
hipFree(matrix1_d);
hipHostFree(matrix0_h);
hipHostFree(matrix1_h);
}
__global__ void addVectorShared(int* v1, int* v2, std::size_t size){
extern __shared__ int shared[];
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
shared[threadIdx.x] = v2[threadId];
if(threadId < size){
v1[threadId] += shared[threadIdx.x];
}
}
void testAddShared(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
hipError_t hipError_t;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
hipHostMalloc(&vector0_h, size * sizeof(int), hipHostMallocDefault);
hipHostMalloc(&vector1_h, size * sizeof(int), hipHostMallocDefault);
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
hipError_t = hipMalloc(&vector0_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipError_t = hipMalloc(&vector1_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipMemcpy(vector0_d, vector0_h, size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(vector1_d, vector1_h, size * sizeof(int), hipMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVectorShared<<<grid, block, block.x * sizeof(int)>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
hipMemcpy(vector0_h, vector0_d, size * sizeof(int), hipMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
hipFree(vector0_d);
hipFree(vector1_d);
hipHostFree(vector0_h);
hipHostFree(vector1_h);
}
int main(){
// testMonoThread();
// testMultiThreads();
// testMultiBlocs();
// testAdd();
testAddShared();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14fillMonoThreadPim
.globl _Z14fillMonoThreadPim
.p2align 8
.type _Z14fillMonoThreadPim,@function
_Z14fillMonoThreadPim:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
.LBB0_2:
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14fillMonoThreadPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14fillMonoThreadPim, .Lfunc_end0-_Z14fillMonoThreadPim
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16fillMutliThreadsPim
.globl _Z16fillMutliThreadsPim
.p2align 8
.type _Z16fillMutliThreadsPim,@function
_Z16fillMutliThreadsPim:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16fillMutliThreadsPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16fillMutliThreadsPim, .Lfunc_end1-_Z16fillMutliThreadsPim
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14fillMutliBlocsPim
.globl _Z14fillMutliBlocsPim
.p2align 8
.type _Z14fillMutliBlocsPim,@function
_Z14fillMutliBlocsPim:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14fillMutliBlocsPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14fillMutliBlocsPim, .Lfunc_end2-_Z14fillMutliBlocsPim
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9addVectorPiS_m
.globl _Z9addVectorPiS_m
.p2align 8
.type _Z9addVectorPiS_m,@function
_Z9addVectorPiS_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB3_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPiS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z9addVectorPiS_m, .Lfunc_end3-_Z9addVectorPiS_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9addMatrixPiS_mm
.globl _Z9addMatrixPiS_mm
.p2align 8
.type _Z9addMatrixPiS_mm,@function
_Z9addMatrixPiS_mm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s6, v[3:4]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB4_3
s_load_b32 s3, s[4:5], 0xc
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB4_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addMatrixPiS_mm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z9addMatrixPiS_mm, .Lfunc_end4-_Z9addMatrixPiS_mm
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15addVectorSharedPiS_m
.globl _Z15addVectorSharedPiS_m
.p2align 8
.type _Z15addVectorSharedPiS_m,@function
_Z15addVectorSharedPiS_m:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
v_lshl_add_u32 v0, v0, 2, 0
s_mov_b32 s2, exec_lo
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[4:5]
v_add_co_u32 v6, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v3
v_cmpx_gt_u64_e64 s[6:7], v[4:5]
s_cbranch_execz .LBB5_2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15addVectorSharedPiS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z15addVectorSharedPiS_m, .Lfunc_end5-_Z15addVectorSharedPiS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14fillMonoThreadPim
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z14fillMonoThreadPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16fillMutliThreadsPim
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z16fillMutliThreadsPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14fillMutliBlocsPim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14fillMutliBlocsPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPiS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addVectorPiS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addMatrixPiS_mm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addMatrixPiS_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15addVectorSharedPiS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15addVectorSharedPiS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void fillMonoThread(int* vector, std::size_t size){
for(std::size_t i=0; i<size; ++i){
vector[i] = 1;
}
}
void testMonoThread(){
std::size_t size = 10;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
hipMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
fillMonoThread<<<1,1>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
hipMemcpy(vector_h, vector_d, size*sizeof(int), hipMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << std::endl;
}
hipFree(vector_d);
}
__global__ void fillMutliThreads(int* vector, std::size_t size){
vector[threadIdx.x] = threadIdx.x;
}
void testMultiThreads(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
hipMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliThreads<<<1,size>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
hipMemcpy(vector_h, vector_d, size*sizeof(int), hipMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
hipFree(vector_d);
}
__global__ void fillMutliBlocs(int* vector, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
vector[threadId] = threadId;
}
void testMultiBlocs(){
std::size_t size = 1024;
int* vector_h = new int[size];
int* vector_d;
// allocate memory on GPU
hipMalloc(&vector_d, size * sizeof(int));
// run cuda code on GPU
// on size threads
fillMutliBlocs<<<2,size/2>>>(vector_d, size);
// once it's done transfert GPU data to CPU
// thus we could use it here, on CPU host
hipMemcpy(vector_h, vector_d, size*sizeof(int), hipMemcpyDeviceToHost);
for(std::size_t i=0; i<size; ++i){
std::cout << vector_h[i] << ' ' ;
}
hipFree(vector_d);
}
__global__ void addVector(int* v1, int* v2, std::size_t size){
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
if(threadId < size){
v1[threadId] += v2[threadId];
}
}
void testAdd(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
hipError_t hipError_t;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
hipHostMalloc(&vector0_h, size * sizeof(int), hipHostMallocDefault);
hipHostMalloc(&vector1_h, size * sizeof(int), hipHostMallocDefault);
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
hipError_t = hipMalloc(&vector0_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipError_t = hipMalloc(&vector1_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipMemcpy(vector0_d, vector0_h, size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(vector1_d, vector1_h, size * sizeof(int), hipMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVector<<<grid, block>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
hipMemcpy(vector0_h, vector0_d, size * sizeof(int), hipMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
hipFree(vector0_d);
hipFree(vector1_d);
hipHostFree(vector0_h);
hipHostFree(vector1_h);
}
__global__ void addMatrix(int* m1, int* m2, std::size_t width, std::size_t height){
// index of thread in X dim
int threadIdX = blockIdx.x * blockDim.x + threadIdx.x;
// index of thread in Y dim
int threadIdY = blockIdx.y * blockDim.y + threadIdx.y;
if(threadIdX < width && threadIdY < height){
// make a 2D index into 1D
int matrixIndex = width * threadIdY + threadIdX;
m1[matrixIndex] += m2[matrixIndex];
}
}
void testAddMatrice(){
std::size_t const width = 100;
std::size_t const height = 100;
std::size_t const size = width * height;
int* matrix0_h = nullptr;
int* matrix1_h = nullptr;
int* matrix0_d = nullptr;
int* matrix1_d = nullptr;
hipError_t hipError_t;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
hipHostMalloc(&matrix0_h, size * sizeof(int), hipHostMallocDefault);
hipHostMalloc(&matrix1_h, size * sizeof(int), hipHostMallocDefault);
// fill matrixs
for(int i=0; i<size; ++i){
matrix0_h[i] = matrix1_h[i] = i;
}
// allocate memory device
hipError_t = hipMalloc(&matrix0_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipError_t = hipMalloc(&matrix1_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipMemcpy(matrix0_d, matrix0_h, size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(matrix1_d, matrix1_h, size * sizeof(int), hipMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32, 32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((width-1)/block.x + 1, (height-1)/block.y + 1);
addMatrix<<<grid, block>>>(matrix0_d, matrix1_d, width, height);
// put back GPU result to CPU
hipMemcpy(matrix0_h, matrix0_d, size * sizeof(int), hipMemcpyDeviceToHost);
// check add result matrixs
for(int i=0; i<size; ++i){
std::cout << matrix0_h[i] << ' ' ;
}
// free memory on GPU and CPU
hipFree(matrix0_d);
hipFree(matrix1_d);
hipHostFree(matrix0_h);
hipHostFree(matrix1_h);
}
__global__ void addVectorShared(int* v1, int* v2, std::size_t size){
extern __shared__ int shared[];
int threadId = blockIdx.x * blockDim.x + threadIdx.x;
shared[threadIdx.x] = v2[threadId];
if(threadId < size){
v1[threadId] += shared[threadIdx.x];
}
}
void testAddShared(){
std::size_t const size = 100;
int* vector0_h = nullptr;
int* vector1_h = nullptr;
int* vector0_d = nullptr;
int* vector1_d = nullptr;
hipError_t hipError_t;
// http://horacio9573.no-ip.org/cuda/group__CUDART__MEMORY_g9f93d9600f4504e0d637ceb43c91ebad.html
// allocate memory host
hipHostMalloc(&vector0_h, size * sizeof(int), hipHostMallocDefault);
hipHostMalloc(&vector1_h, size * sizeof(int), hipHostMallocDefault);
// fill vectors
for(int i=0; i<size; ++i){
vector0_h[i] = vector1_h[i] = i;
}
// allocate memory device
hipError_t = hipMalloc(&vector0_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipError_t = hipMalloc(&vector1_d, size * sizeof(int));
if(hipError_t != hipSuccess){
std::cout << hipGetErrorString(hipError_t) << std::endl;
throw std::exception();
}
hipMemcpy(vector0_d, vector0_h, size * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(vector1_d, vector1_h, size * sizeof(int), hipMemcpyHostToDevice);
// call cuda Kernel
// generic block / grid parametrization
dim3 block(32);
// little tweak to get a correct grid in case of size/block < 0
dim3 grid((size-1)/block.x + 1);
addVectorShared<<<grid, block, block.x * sizeof(int)>>>(vector0_d, vector1_d, size);
// put back GPU result to CPU
hipMemcpy(vector0_h, vector0_d, size * sizeof(int), hipMemcpyDeviceToHost);
// check add result vectors
for(int i=0; i<size; ++i){
std::cout << vector0_h[i] << ' ' ;
}
// free memory on GPU and CPU
hipFree(vector0_d);
hipFree(vector1_d);
hipHostFree(vector0_h);
hipHostFree(vector1_h);
}
int main(){
// testMonoThread();
// testMultiThreads();
// testMultiBlocs();
// testAdd();
testAddShared();
return 0;
} | .text
.file "basic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__fillMonoThreadPim # -- Begin function _Z29__device_stub__fillMonoThreadPim
.p2align 4, 0x90
.type _Z29__device_stub__fillMonoThreadPim,@function
_Z29__device_stub__fillMonoThreadPim: # @_Z29__device_stub__fillMonoThreadPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14fillMonoThreadPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__fillMonoThreadPim, .Lfunc_end0-_Z29__device_stub__fillMonoThreadPim
.cfi_endproc
# -- End function
.globl _Z14testMonoThreadv # -- Begin function _Z14testMonoThreadv
.p2align 4, 0x90
.type _Z14testMonoThreadv,@function
_Z14testMonoThreadv: # @_Z14testMonoThreadv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq $10, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14fillMonoThreadPim, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_3 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_3 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $10, %r15
je .LBB1_8
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_3 Depth=1
cmpb $0, 56(%r14)
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_7
.LBB1_8:
movq 8(%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z14testMonoThreadv, .Lfunc_end1-_Z14testMonoThreadv
.cfi_endproc
# -- End function
.globl _Z31__device_stub__fillMutliThreadsPim # -- Begin function _Z31__device_stub__fillMutliThreadsPim
.p2align 4, 0x90
.type _Z31__device_stub__fillMutliThreadsPim,@function
_Z31__device_stub__fillMutliThreadsPim: # @_Z31__device_stub__fillMutliThreadsPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16fillMutliThreadsPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z31__device_stub__fillMutliThreadsPim, .Lfunc_end2-_Z31__device_stub__fillMutliThreadsPim
.cfi_endproc
# -- End function
.globl _Z16testMultiThreadsv # -- Begin function _Z16testMultiThreadsv
.p2align 4, 0x90
.type _Z16testMultiThreadsv,@function
_Z16testMultiThreadsv: # @_Z16testMultiThreadsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq $1024, 80(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rax
movq %rax, 24(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z16fillMutliThreadsPim, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
leaq 16(%rsp), %r14
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB3_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB3_3 Depth=1
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB3_7
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 16(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_6
.LBB3_7:
movq 8(%rsp), %rdi
callq hipFree
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z16testMultiThreadsv, .Lfunc_end3-_Z16testMultiThreadsv
.cfi_endproc
# -- End function
.globl _Z29__device_stub__fillMutliBlocsPim # -- Begin function _Z29__device_stub__fillMutliBlocsPim
.p2align 4, 0x90
.type _Z29__device_stub__fillMutliBlocsPim,@function
_Z29__device_stub__fillMutliBlocsPim: # @_Z29__device_stub__fillMutliBlocsPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14fillMutliBlocsPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z29__device_stub__fillMutliBlocsPim, .Lfunc_end4-_Z29__device_stub__fillMutliBlocsPim
.cfi_endproc
# -- End function
.globl _Z14testMultiBlocsv # -- Begin function _Z14testMultiBlocsv
.p2align 4, 0x90
.type _Z14testMultiBlocsv,@function
_Z14testMultiBlocsv: # @_Z14testMultiBlocsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 510(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq $1024, 80(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rax
movq %rax, 24(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14fillMutliBlocsPim, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
leaq 16(%rsp), %r14
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_3 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB5_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB5_3 Depth=1
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB5_7
.LBB5_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 16(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB5_6
.LBB5_7:
movq 8(%rsp), %rdi
callq hipFree
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z14testMultiBlocsv, .Lfunc_end5-_Z14testMultiBlocsv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addVectorPiS_m # -- Begin function _Z24__device_stub__addVectorPiS_m
.p2align 4, 0x90
.type _Z24__device_stub__addVectorPiS_m,@function
_Z24__device_stub__addVectorPiS_m: # @_Z24__device_stub__addVectorPiS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addVectorPiS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z24__device_stub__addVectorPiS_m, .Lfunc_end6-_Z24__device_stub__addVectorPiS_m
.cfi_endproc
# -- End function
.globl _Z7testAddv # -- Begin function _Z7testAddv
.p2align 4, 0x90
.type _Z7testAddv,@function
_Z7testAddv: # @_Z7testAddv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, (%rsp)
movq $0, 24(%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq %rsp, %rdi
xorl %ebx, %ebx
movl $400, %esi # imm = 0x190
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
xorl %edx, %edx
callq hipHostMalloc
movq 24(%rsp), %rax
movq (%rsp), %rcx
.p2align 4, 0x90
.LBB7_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rax,%rbx,4)
movl %ebx, (%rcx,%rbx,4)
incq %rbx
cmpq $100, %rbx
jne .LBB7_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB7_12
# %bb.3:
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB7_12
# %bb.4:
movq 8(%rsp), %rdi
movq (%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 28(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_6
# %bb.5:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq $100, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z9addVectorPiS_m, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_6:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
leaq 32(%rsp), %rbx
jmp .LBB7_7
.p2align 4, 0x90
.LBB7_9: # in Loop: Header=BB7_7 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB7_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB7_7 Depth=1
incq %r14
cmpq $100, %r14
je .LBB7_11
.LBB7_7: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB7_9
# %bb.8: # in Loop: Header=BB7_7 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB7_10
.LBB7_11:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB7_12:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $8, %edi
callq __cxa_allocate_exception
movq $_ZTVSt9exception+16, (%rax)
movl $_ZTISt9exception, %esi
movl $_ZNSt9exceptionD1Ev, %edx
movq %rax, %rdi
callq __cxa_throw
.Lfunc_end7:
.size _Z7testAddv, .Lfunc_end7-_Z7testAddv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addMatrixPiS_mm # -- Begin function _Z24__device_stub__addMatrixPiS_mm
.p2align 4, 0x90
.type _Z24__device_stub__addMatrixPiS_mm,@function
_Z24__device_stub__addMatrixPiS_mm: # @_Z24__device_stub__addMatrixPiS_mm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addMatrixPiS_mm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end8:
.size _Z24__device_stub__addMatrixPiS_mm, .Lfunc_end8-_Z24__device_stub__addMatrixPiS_mm
.cfi_endproc
# -- End function
.globl _Z14testAddMatricev # -- Begin function _Z14testAddMatricev
.p2align 4, 0x90
.type _Z14testAddMatricev,@function
_Z14testAddMatricev: # @_Z14testAddMatricev
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, (%rsp)
movq $0, 24(%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq %rsp, %rdi
xorl %ebx, %ebx
movl $40000, %esi # imm = 0x9C40
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
xorl %edx, %edx
callq hipHostMalloc
movq 24(%rsp), %rax
movq (%rsp), %rcx
.p2align 4, 0x90
.LBB9_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rax,%rbx,4)
movl %ebx, (%rcx,%rbx,4)
incq %rbx
cmpq $10000, %rbx # imm = 0x2710
jne .LBB9_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
jne .LBB9_12
# %bb.3:
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
jne .LBB9_12
# %bb.4:
movq 8(%rsp), %rdi
movq (%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movabsq $17179869188, %rdi # imm = 0x400000004
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_6
# %bb.5:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq $100, 88(%rsp)
movq $100, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9addMatrixPiS_mm, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_6:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
leaq 112(%rsp), %rbx
jmp .LBB9_7
.p2align 4, 0x90
.LBB9_9: # in Loop: Header=BB9_7 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB9_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB9_7 Depth=1
incq %r14
cmpq $10000, %r14 # imm = 0x2710
je .LBB9_11
.LBB9_7: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 112(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB9_9
# %bb.8: # in Loop: Header=BB9_7 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB9_10
.LBB9_11:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB9_12:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $8, %edi
callq __cxa_allocate_exception
movq $_ZTVSt9exception+16, (%rax)
movl $_ZTISt9exception, %esi
movl $_ZNSt9exceptionD1Ev, %edx
movq %rax, %rdi
callq __cxa_throw
.Lfunc_end9:
.size _Z14testAddMatricev, .Lfunc_end9-_Z14testAddMatricev
.cfi_endproc
# -- End function
.globl _Z30__device_stub__addVectorSharedPiS_m # -- Begin function _Z30__device_stub__addVectorSharedPiS_m
.p2align 4, 0x90
.type _Z30__device_stub__addVectorSharedPiS_m,@function
_Z30__device_stub__addVectorSharedPiS_m: # @_Z30__device_stub__addVectorSharedPiS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15addVectorSharedPiS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end10:
.size _Z30__device_stub__addVectorSharedPiS_m, .Lfunc_end10-_Z30__device_stub__addVectorSharedPiS_m
.cfi_endproc
# -- End function
.globl _Z13testAddSharedv # -- Begin function _Z13testAddSharedv
.p2align 4, 0x90
.type _Z13testAddSharedv,@function
_Z13testAddSharedv: # @_Z13testAddSharedv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, (%rsp)
movq $0, 24(%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq %rsp, %rdi
xorl %ebx, %ebx
movl $400, %esi # imm = 0x190
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
xorl %edx, %edx
callq hipHostMalloc
movq 24(%rsp), %rax
movq (%rsp), %rcx
.p2align 4, 0x90
.LBB11_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rax,%rbx,4)
movl %ebx, (%rcx,%rbx,4)
incq %rbx
cmpq $100, %rbx
jne .LBB11_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB11_12
# %bb.3:
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB11_12
# %bb.4:
movq 8(%rsp), %rdi
movq (%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 28(%rdi), %rdx
movl $128, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB11_6
# %bb.5:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq $100, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z15addVectorSharedPiS_m, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB11_6:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
leaq 32(%rsp), %rbx
jmp .LBB11_7
.p2align 4, 0x90
.LBB11_9: # in Loop: Header=BB11_7 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB11_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB11_7 Depth=1
incq %r14
cmpq $100, %r14
je .LBB11_11
.LBB11_7: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB11_9
# %bb.8: # in Loop: Header=BB11_7 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB11_10
.LBB11_11:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB11_12:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $8, %edi
callq __cxa_allocate_exception
movq $_ZTVSt9exception+16, (%rax)
movl $_ZTISt9exception, %esi
movl $_ZNSt9exceptionD1Ev, %edx
movq %rax, %rdi
callq __cxa_throw
.Lfunc_end11:
.size _Z13testAddSharedv, .Lfunc_end11-_Z13testAddSharedv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z13testAddSharedv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size main, .Lfunc_end12-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB13_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB13_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14fillMonoThreadPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16fillMutliThreadsPim, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14fillMutliBlocsPim, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPiS_m, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addMatrixPiS_mm, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15addVectorSharedPiS_m, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end13:
.size __hip_module_ctor, .Lfunc_end13-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB14_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB14_2:
retq
.Lfunc_end14:
.size __hip_module_dtor, .Lfunc_end14-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14fillMonoThreadPim,@object # @_Z14fillMonoThreadPim
.section .rodata,"a",@progbits
.globl _Z14fillMonoThreadPim
.p2align 3, 0x0
_Z14fillMonoThreadPim:
.quad _Z29__device_stub__fillMonoThreadPim
.size _Z14fillMonoThreadPim, 8
.type _Z16fillMutliThreadsPim,@object # @_Z16fillMutliThreadsPim
.globl _Z16fillMutliThreadsPim
.p2align 3, 0x0
_Z16fillMutliThreadsPim:
.quad _Z31__device_stub__fillMutliThreadsPim
.size _Z16fillMutliThreadsPim, 8
.type _Z14fillMutliBlocsPim,@object # @_Z14fillMutliBlocsPim
.globl _Z14fillMutliBlocsPim
.p2align 3, 0x0
_Z14fillMutliBlocsPim:
.quad _Z29__device_stub__fillMutliBlocsPim
.size _Z14fillMutliBlocsPim, 8
.type _Z9addVectorPiS_m,@object # @_Z9addVectorPiS_m
.globl _Z9addVectorPiS_m
.p2align 3, 0x0
_Z9addVectorPiS_m:
.quad _Z24__device_stub__addVectorPiS_m
.size _Z9addVectorPiS_m, 8
.type _Z9addMatrixPiS_mm,@object # @_Z9addMatrixPiS_mm
.globl _Z9addMatrixPiS_mm
.p2align 3, 0x0
_Z9addMatrixPiS_mm:
.quad _Z24__device_stub__addMatrixPiS_mm
.size _Z9addMatrixPiS_mm, 8
.type _Z15addVectorSharedPiS_m,@object # @_Z15addVectorSharedPiS_m
.globl _Z15addVectorSharedPiS_m
.p2align 3, 0x0
_Z15addVectorSharedPiS_m:
.quad _Z30__device_stub__addVectorSharedPiS_m
.size _Z15addVectorSharedPiS_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14fillMonoThreadPim"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16fillMutliThreadsPim"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14fillMutliBlocsPim"
.size .L__unnamed_3, 22
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z9addVectorPiS_m"
.size .L__unnamed_4, 18
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z9addMatrixPiS_mm"
.size .L__unnamed_5, 19
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z15addVectorSharedPiS_m"
.size .L__unnamed_6, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__fillMonoThreadPim
.addrsig_sym _Z31__device_stub__fillMutliThreadsPim
.addrsig_sym _Z29__device_stub__fillMutliBlocsPim
.addrsig_sym _Z24__device_stub__addVectorPiS_m
.addrsig_sym _Z24__device_stub__addMatrixPiS_mm
.addrsig_sym _Z30__device_stub__addVectorSharedPiS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14fillMonoThreadPim
.addrsig_sym _ZSt4cout
.addrsig_sym _Z16fillMutliThreadsPim
.addrsig_sym _Z14fillMutliBlocsPim
.addrsig_sym _Z9addVectorPiS_m
.addrsig_sym _ZTISt9exception
.addrsig_sym _Z9addMatrixPiS_mm
.addrsig_sym _Z15addVectorSharedPiS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void hello() {
printf("Hello world from block (%d,%d), thread (%d,%d,%d).\n",
blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, threadIdx.z);
__syncthreads();
}
int main(void) {
int devID;
cudaDeviceProp p;
cudaGetDevice(&devID);
cudaGetDeviceProperties(&p, devID);
printf("Running on device %d \"%s\" with capability %d.%d.\n",
devID, p.name, p.major, p.minor);
if (p.major < 2) {
printf("Program incompatible with existing architecture; terminating.\n");
return 1;
}
dim3 dimGrid(2,2);
dim3 dimBlock(2,2,2);
hello<<<dimGrid,dimBlock>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z5hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.Y ; /* 0x00000000000b7919 */
/* 0x000e220000002600 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*0090*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000ee40000002200 */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*00b0*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000ee80000002100 */
/*00c0*/ S2R R8, SR_TID.Z ; /* 0x0000000000087919 */
/* 0x000f280000002300 */
/*00d0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0013e80000100a00 */
/*00e0*/ STL.64 [R1+0x8], R12 ; /* 0x0000080c01007387 */
/* 0x0083e80000100a00 */
/*00f0*/ STL [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0103e40000100800 */
/*0100*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0110*/ MOV R11, 0x180 ; /* 0x00000180000b7802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R20, 0x100 ; /* 0x0000010000147802 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0150*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0160*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0170*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0180*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void hello() {
printf("Hello world from block (%d,%d), thread (%d,%d,%d).\n",
blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, threadIdx.z);
__syncthreads();
}
int main(void) {
int devID;
cudaDeviceProp p;
cudaGetDevice(&devID);
cudaGetDeviceProperties(&p, devID);
printf("Running on device %d \"%s\" with capability %d.%d.\n",
devID, p.name, p.major, p.minor);
if (p.major < 2) {
printf("Program incompatible with existing architecture; terminating.\n");
return 1;
}
dim3 dimGrid(2,2);
dim3 dimBlock(2,2,2);
hello<<<dimGrid,dimBlock>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000a9940_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Running on device %d \"%s\" with capability %d.%d.\n"
.align 8
.LC1:
.string "Program incompatible with existing architecture; terminating.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1072, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq 32(%rsp), %rbx
movl 4(%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 396(%rsp), %r9d
movl 392(%rsp), %r8d
movq %rbx, %rcx
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $1, 392(%rsp)
jle .L17
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $2, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
call cudaDeviceSynchronize@PLT
movl $0, %eax
.L11:
movq 1064(%rsp), %rdx
subq %fs:40, %rdx
jne .L19
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L18:
call _Z23__device_stub__Z5hellovv
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void hello() {
printf("Hello world from block (%d,%d), thread (%d,%d,%d).\n",
blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, threadIdx.z);
__syncthreads();
}
int main(void) {
int devID;
cudaDeviceProp p;
cudaGetDevice(&devID);
cudaGetDeviceProperties(&p, devID);
printf("Running on device %d \"%s\" with capability %d.%d.\n",
devID, p.name, p.major, p.minor);
if (p.major < 2) {
printf("Program incompatible with existing architecture; terminating.\n");
return 1;
}
dim3 dimGrid(2,2);
dim3 dimBlock(2,2,2);
hello<<<dimGrid,dimBlock>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hello() {
printf("Hello world from block (%d,%d), thread (%d,%d,%d).\n",
blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, threadIdx.z);
__syncthreads();
}
int main(void) {
int devID;
hipDeviceProp_t p;
hipGetDevice(&devID);
hipGetDeviceProperties(&p, devID);
printf("Running on device %d \"%s\" with capability %d.%d.\n",
devID, p.name, p.major, p.minor);
if (p.major < 2) {
printf("Program incompatible with existing architecture; terminating.\n");
return 1;
}
dim3 dimGrid(2,2);
dim3 dimBlock(2,2,2);
hello<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hello() {
printf("Hello world from block (%d,%d), thread (%d,%d,%d).\n",
blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, threadIdx.z);
__syncthreads();
}
int main(void) {
int devID;
hipDeviceProp_t p;
hipGetDevice(&devID);
hipGetDeviceProperties(&p, devID);
printf("Running on device %d \"%s\" with capability %d.%d.\n",
devID, p.name, p.major, p.minor);
if (p.major < 2) {
printf("Program incompatible with existing architecture; terminating.\n");
return 1;
}
dim3 dimGrid(2,2);
dim3 dimBlock(2,2,2);
hello<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 1568
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 80(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl 12(%rsp), %esi
movl 440(%rsp), %ecx
movl 444(%rsp), %r8d
movl $.L.str, %edi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
cmpl $1, 440(%rsp)
jg .LBB1_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
jmp .LBB1_5
.LBB1_2:
xorl %ebx, %ebx
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $2, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5hellov, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
.LBB1_5:
movl %ebx, %eax
addq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Running on device %d \"%s\" with capability %d.%d.\n"
.size .L.str, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Program incompatible with existing architecture
.size .Lstr, 62
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a9940_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Running on device %d \"%s\" with capability %d.%d.\n"
.align 8
.LC1:
.string "Program incompatible with existing architecture; terminating.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1072, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq 32(%rsp), %rbx
movl 4(%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 396(%rsp), %r9d
movl 392(%rsp), %r8d
movq %rbx, %rcx
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $1, 392(%rsp)
jle .L17
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $2, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
call cudaDeviceSynchronize@PLT
movl $0, %eax
.L11:
movq 1064(%rsp), %rdx
subq %fs:40, %rdx
jne .L19
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L18:
call _Z23__device_stub__Z5hellovv
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 1568
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 80(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl 12(%rsp), %esi
movl 440(%rsp), %ecx
movl 444(%rsp), %r8d
movl $.L.str, %edi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
cmpl $1, 440(%rsp)
jg .LBB1_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
jmp .LBB1_5
.LBB1_2:
xorl %ebx, %ebx
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $2, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5hellov, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
.LBB1_5:
movl %ebx, %eax
addq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Running on device %d \"%s\" with capability %d.%d.\n"
.size .L.str, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Program incompatible with existing architecture
.size .Lstr, 62
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
//Vector Size
#define N 32
//Device Function
__global__ void add(int* a, int* b, int* c)
{
//perfrom single addition
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
//store result in c
}
//Generate N random integers, store in a
void random_ints(int* a)
{
int i;
for(i=0; i < N; i++)
{
a[i] = rand() % 10;
printf("%02d ", a[i]);
}
printf("\n");
}
int main(void)
{
//Host Arrays
int *a, *b, *c;
//Device Arrays
int *d_a, *d_b, *d_c;
//Total mem size
int size = N * sizeof(int);
//Allocate device mem
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
a = (int *)malloc(size); random_ints(a);
b = (int *)malloc(size); random_ints(b);
//Allocate and populate a,b
c = (int *)malloc(size);
//Allocate c
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
//Copy a and b to device memory, store in d_a and d_b
//Execute in 1 block, N threads
add<<<1,N>>>(d_a, d_b, d_c);
//Copy result back from device
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
for(int i=0; i < N; i++)
{
printf("%02d ", c[i]);
}
printf("\n");
//--Free Memory--//
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
//---------------//
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
//Vector Size
#define N 32
//Device Function
__global__ void add(int* a, int* b, int* c)
{
//perfrom single addition
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
//store result in c
}
//Generate N random integers, store in a
void random_ints(int* a)
{
int i;
for(i=0; i < N; i++)
{
a[i] = rand() % 10;
printf("%02d ", a[i]);
}
printf("\n");
}
int main(void)
{
//Host Arrays
int *a, *b, *c;
//Device Arrays
int *d_a, *d_b, *d_c;
//Total mem size
int size = N * sizeof(int);
//Allocate device mem
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
a = (int *)malloc(size); random_ints(a);
b = (int *)malloc(size); random_ints(b);
//Allocate and populate a,b
c = (int *)malloc(size);
//Allocate c
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
//Copy a and b to device memory, store in d_a and d_b
//Execute in 1 block, N threads
add<<<1,N>>>(d_a, d_b, d_c);
//Copy result back from device
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
for(int i=0; i < N; i++)
{
printf("%02d ", c[i]);
}
printf("\n");
//--Free Memory--//
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
//---------------//
return 0;
} | .file "tmpxft_001a12a9_00000000-6_thread_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%02d "
.LC1:
.string "\n"
.text
.globl _Z11random_intsPi
.type _Z11random_intsPi, @function
_Z11random_intsPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 128(%rdi), %r12
leaq .LC0(%rip), %rbp
.L4:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
addl %ecx, %ecx
subl %ecx, %eax
movl %eax, %edx
movl %eax, (%rbx)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L4
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPi, .-_Z11random_intsPi
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $128, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, %rdi
call _Z11random_intsPi
movl $128, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, %rdi
call _Z11random_intsPi
movl $128, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %ecx
movl $128, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L16:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 128(%r13), %r12
leaq .LC0(%rip), %rbp
.L17:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L16
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
//Vector Size
#define N 32
//Device Function
__global__ void add(int* a, int* b, int* c)
{
//perfrom single addition
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
//store result in c
}
//Generate N random integers, store in a
void random_ints(int* a)
{
int i;
for(i=0; i < N; i++)
{
a[i] = rand() % 10;
printf("%02d ", a[i]);
}
printf("\n");
}
int main(void)
{
//Host Arrays
int *a, *b, *c;
//Device Arrays
int *d_a, *d_b, *d_c;
//Total mem size
int size = N * sizeof(int);
//Allocate device mem
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
a = (int *)malloc(size); random_ints(a);
b = (int *)malloc(size); random_ints(b);
//Allocate and populate a,b
c = (int *)malloc(size);
//Allocate c
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
//Copy a and b to device memory, store in d_a and d_b
//Execute in 1 block, N threads
add<<<1,N>>>(d_a, d_b, d_c);
//Copy result back from device
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
for(int i=0; i < N; i++)
{
printf("%02d ", c[i]);
}
printf("\n");
//--Free Memory--//
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
//---------------//
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
//Vector Size
#define N 32
//Device Function
__global__ void add(int* a, int* b, int* c)
{
//perfrom single addition
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
//store result in c
}
//Generate N random integers, store in a
void random_ints(int* a)
{
int i;
for(i=0; i < N; i++)
{
a[i] = rand() % 10;
printf("%02d ", a[i]);
}
printf("\n");
}
int main(void)
{
//Host Arrays
int *a, *b, *c;
//Device Arrays
int *d_a, *d_b, *d_c;
//Total mem size
int size = N * sizeof(int);
//Allocate device mem
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
a = (int *)malloc(size); random_ints(a);
b = (int *)malloc(size); random_ints(b);
//Allocate and populate a,b
c = (int *)malloc(size);
//Allocate c
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
//Copy a and b to device memory, store in d_a and d_b
//Execute in 1 block, N threads
add<<<1,N>>>(d_a, d_b, d_c);
//Copy result back from device
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
for(int i=0; i < N; i++)
{
printf("%02d ", c[i]);
}
printf("\n");
//--Free Memory--//
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
//---------------//
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
//Vector Size
#define N 32
//Device Function
__global__ void add(int* a, int* b, int* c)
{
//perfrom single addition
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
//store result in c
}
//Generate N random integers, store in a
void random_ints(int* a)
{
int i;
for(i=0; i < N; i++)
{
a[i] = rand() % 10;
printf("%02d ", a[i]);
}
printf("\n");
}
int main(void)
{
//Host Arrays
int *a, *b, *c;
//Device Arrays
int *d_a, *d_b, *d_c;
//Total mem size
int size = N * sizeof(int);
//Allocate device mem
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
a = (int *)malloc(size); random_ints(a);
b = (int *)malloc(size); random_ints(b);
//Allocate and populate a,b
c = (int *)malloc(size);
//Allocate c
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
//Copy a and b to device memory, store in d_a and d_b
//Execute in 1 block, N threads
add<<<1,N>>>(d_a, d_b, d_c);
//Copy result back from device
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
for(int i=0; i < N; i++)
{
printf("%02d ", c[i]);
}
printf("\n");
//--Free Memory--//
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
//---------------//
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
//Vector Size
#define N 32
//Device Function
__global__ void add(int* a, int* b, int* c)
{
//perfrom single addition
c[threadIdx.x] = a[threadIdx.x] + b[threadIdx.x];
//store result in c
}
//Generate N random integers, store in a
void random_ints(int* a)
{
int i;
for(i=0; i < N; i++)
{
a[i] = rand() % 10;
printf("%02d ", a[i]);
}
printf("\n");
}
int main(void)
{
//Host Arrays
int *a, *b, *c;
//Device Arrays
int *d_a, *d_b, *d_c;
//Total mem size
int size = N * sizeof(int);
//Allocate device mem
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
a = (int *)malloc(size); random_ints(a);
b = (int *)malloc(size); random_ints(b);
//Allocate and populate a,b
c = (int *)malloc(size);
//Allocate c
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
//Copy a and b to device memory, store in d_a and d_b
//Execute in 1 block, N threads
add<<<1,N>>>(d_a, d_b, d_c);
//Copy result back from device
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
for(int i=0; i < N; i++)
{
printf("%02d ", c[i]);
}
printf("\n");
//--Free Memory--//
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
//---------------//
return 0;
} | .text
.file "thread_add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPi # -- Begin function _Z11random_intsPi
.p2align 4, 0x90
.type _Z11random_intsPi,@function
_Z11random_intsPi: # @_Z11random_intsPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $34, %rax
addl %ecx, %eax
addl %eax, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movl %esi, (%rbx,%r14,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB1_1
# %bb.2:
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z11random_intsPi, .Lfunc_end1-_Z11random_intsPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movl $128, %edi
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $34, %rax
addl %ecx, %eax
addl %eax, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movl %esi, (%rbx,%r14,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB2_1
# %bb.2: # %_Z11random_intsPi.exit
movl $10, %edi
callq putchar@PLT
movl $128, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $34, %rax
addl %ecx, %eax
addl %eax, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movl %esi, (%r14,%r15,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r15
cmpq $32, %r15
jne .LBB2_3
# %bb.4: # %_Z11random_intsPi.exit26
movl $10, %edi
callq putchar@PLT
movl $128, %edi
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $128, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $128, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $32, %r12
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%02d "
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a12a9_00000000-6_thread_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%02d "
.LC1:
.string "\n"
.text
.globl _Z11random_intsPi
.type _Z11random_intsPi, @function
_Z11random_intsPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 128(%rdi), %r12
leaq .LC0(%rip), %rbp
.L4:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
addl %ecx, %ecx
subl %ecx, %eax
movl %eax, %edx
movl %eax, (%rbx)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L4
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPi, .-_Z11random_intsPi
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $128, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, %rdi
call _Z11random_intsPi
movl $128, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, %rdi
call _Z11random_intsPi
movl $128, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %ecx
movl $128, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L16:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 128(%r13), %r12
leaq .LC0(%rip), %rbp
.L17:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L16
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "thread_add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPi # -- Begin function _Z11random_intsPi
.p2align 4, 0x90
.type _Z11random_intsPi,@function
_Z11random_intsPi: # @_Z11random_intsPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $34, %rax
addl %ecx, %eax
addl %eax, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movl %esi, (%rbx,%r14,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB1_1
# %bb.2:
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z11random_intsPi, .Lfunc_end1-_Z11random_intsPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movl $128, %edi
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $34, %rax
addl %ecx, %eax
addl %eax, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movl %esi, (%rbx,%r14,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB2_1
# %bb.2: # %_Z11random_intsPi.exit
movl $10, %edi
callq putchar@PLT
movl $128, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $34, %rax
addl %ecx, %eax
addl %eax, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movl %esi, (%r14,%r15,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r15
cmpq $32, %r15
jne .LBB2_3
# %bb.4: # %_Z11random_intsPi.exit26
movl $10, %edi
callq putchar@PLT
movl $128, %edi
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $128, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $128, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $32, %r12
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%02d "
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void pw_copy_rc_cu_z(const double *din, double *zout, const int n) {
const int igpt =
(gridDim.x * blockIdx.y + blockIdx.x) * blockDim.x + threadIdx.x;
if (igpt < n) {
zout[2 * igpt] = din[igpt];
zout[2 * igpt + 1] = 0.0e0;
}
} | code for sm_80
Function : _Z15pw_copy_rc_cu_zPKdPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ SHF.L.U32 R4, R0, 0x1, RZ ; /* 0x0000000100047819 */
/* 0x000fca00000006ff */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00e0*/ STG.E.64 [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x000fe8000c101b04 */
/*00f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void pw_copy_rc_cu_z(const double *din, double *zout, const int n) {
const int igpt =
(gridDim.x * blockIdx.y + blockIdx.x) * blockDim.x + threadIdx.x;
if (igpt < n) {
zout[2 * igpt] = din[igpt];
zout[2 * igpt + 1] = 0.0e0;
}
} | .file "tmpxft_0011a9df_00000000-6_pw_copy_rc_cu_z.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi
.type _Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi, @function
_Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15pw_copy_rc_cu_zPKdPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi, .-_Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi
.globl _Z15pw_copy_rc_cu_zPKdPdi
.type _Z15pw_copy_rc_cu_zPKdPdi, @function
_Z15pw_copy_rc_cu_zPKdPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15pw_copy_rc_cu_zPKdPdi, .-_Z15pw_copy_rc_cu_zPKdPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15pw_copy_rc_cu_zPKdPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15pw_copy_rc_cu_zPKdPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void pw_copy_rc_cu_z(const double *din, double *zout, const int n) {
const int igpt =
(gridDim.x * blockIdx.y + blockIdx.x) * blockDim.x + threadIdx.x;
if (igpt < n) {
zout[2 * igpt] = din[igpt];
zout[2 * igpt + 1] = 0.0e0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pw_copy_rc_cu_z(const double *din, double *zout, const int n) {
const int igpt =
(gridDim.x * blockIdx.y + blockIdx.x) * blockDim.x + threadIdx.x;
if (igpt < n) {
zout[2 * igpt] = din[igpt];
zout[2 * igpt + 1] = 0.0e0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pw_copy_rc_cu_z(const double *din, double *zout, const int n) {
const int igpt =
(gridDim.x * blockIdx.y + blockIdx.x) * blockDim.x + threadIdx.x;
if (igpt < n) {
zout[2 * igpt] = din[igpt];
zout[2 * igpt + 1] = 0.0e0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15pw_copy_rc_cu_zPKdPdi
.globl _Z15pw_copy_rc_cu_zPKdPdi
.p2align 8
.type _Z15pw_copy_rc_cu_zPKdPdi,@function
_Z15pw_copy_rc_cu_zPKdPdi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_lshlrev_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_mov_b32_e32 v7, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v4, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b64 v[0:1], v[2:3], off
global_store_b64 v[4:5], v[6:7], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15pw_copy_rc_cu_zPKdPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15pw_copy_rc_cu_zPKdPdi, .Lfunc_end0-_Z15pw_copy_rc_cu_zPKdPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15pw_copy_rc_cu_zPKdPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15pw_copy_rc_cu_zPKdPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pw_copy_rc_cu_z(const double *din, double *zout, const int n) {
const int igpt =
(gridDim.x * blockIdx.y + blockIdx.x) * blockDim.x + threadIdx.x;
if (igpt < n) {
zout[2 * igpt] = din[igpt];
zout[2 * igpt + 1] = 0.0e0;
}
} | .text
.file "pw_copy_rc_cu_z.hip"
.globl _Z30__device_stub__pw_copy_rc_cu_zPKdPdi # -- Begin function _Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.p2align 4, 0x90
.type _Z30__device_stub__pw_copy_rc_cu_zPKdPdi,@function
_Z30__device_stub__pw_copy_rc_cu_zPKdPdi: # @_Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15pw_copy_rc_cu_zPKdPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__pw_copy_rc_cu_zPKdPdi, .Lfunc_end0-_Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15pw_copy_rc_cu_zPKdPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15pw_copy_rc_cu_zPKdPdi,@object # @_Z15pw_copy_rc_cu_zPKdPdi
.section .rodata,"a",@progbits
.globl _Z15pw_copy_rc_cu_zPKdPdi
.p2align 3, 0x0
_Z15pw_copy_rc_cu_zPKdPdi:
.quad _Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.size _Z15pw_copy_rc_cu_zPKdPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15pw_copy_rc_cu_zPKdPdi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15pw_copy_rc_cu_zPKdPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15pw_copy_rc_cu_zPKdPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ SHF.L.U32 R4, R0, 0x1, RZ ; /* 0x0000000100047819 */
/* 0x000fca00000006ff */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00e0*/ STG.E.64 [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x000fe8000c101b04 */
/*00f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15pw_copy_rc_cu_zPKdPdi
.globl _Z15pw_copy_rc_cu_zPKdPdi
.p2align 8
.type _Z15pw_copy_rc_cu_zPKdPdi,@function
_Z15pw_copy_rc_cu_zPKdPdi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_lshlrev_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_mov_b32_e32 v7, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v4, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b64 v[0:1], v[2:3], off
global_store_b64 v[4:5], v[6:7], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15pw_copy_rc_cu_zPKdPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15pw_copy_rc_cu_zPKdPdi, .Lfunc_end0-_Z15pw_copy_rc_cu_zPKdPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15pw_copy_rc_cu_zPKdPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15pw_copy_rc_cu_zPKdPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011a9df_00000000-6_pw_copy_rc_cu_z.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi
.type _Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi, @function
_Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15pw_copy_rc_cu_zPKdPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi, .-_Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi
.globl _Z15pw_copy_rc_cu_zPKdPdi
.type _Z15pw_copy_rc_cu_zPKdPdi, @function
_Z15pw_copy_rc_cu_zPKdPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15pw_copy_rc_cu_zPKdPdiPKdPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15pw_copy_rc_cu_zPKdPdi, .-_Z15pw_copy_rc_cu_zPKdPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15pw_copy_rc_cu_zPKdPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15pw_copy_rc_cu_zPKdPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pw_copy_rc_cu_z.hip"
.globl _Z30__device_stub__pw_copy_rc_cu_zPKdPdi # -- Begin function _Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.p2align 4, 0x90
.type _Z30__device_stub__pw_copy_rc_cu_zPKdPdi,@function
_Z30__device_stub__pw_copy_rc_cu_zPKdPdi: # @_Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15pw_copy_rc_cu_zPKdPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__pw_copy_rc_cu_zPKdPdi, .Lfunc_end0-_Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15pw_copy_rc_cu_zPKdPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15pw_copy_rc_cu_zPKdPdi,@object # @_Z15pw_copy_rc_cu_zPKdPdi
.section .rodata,"a",@progbits
.globl _Z15pw_copy_rc_cu_zPKdPdi
.p2align 3, 0x0
_Z15pw_copy_rc_cu_zPKdPdi:
.quad _Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.size _Z15pw_copy_rc_cu_zPKdPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15pw_copy_rc_cu_zPKdPdi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__pw_copy_rc_cu_zPKdPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15pw_copy_rc_cu_zPKdPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void convert_float2bgr(float* annd, unsigned char* bgr, int w, int h, float minval, float maxval)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x < w && y < h)
{
int id = y * w + x;
int err = max(min((annd[id] - minval) / (maxval - minval), 1.f), 0.f) * 255.f;
bgr[id] = err;
}
} | code for sm_80
Function : _Z17convert_float2bgrPfPhiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0100*/ BSSY B0, 0x1e0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0110*/ FADD R5, R5, -c[0x0][0x178] ; /* 0x80005e0005057621 */
/* 0x000fc80000000000 */
/*0120*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*0130*/ FFMA R7, -R5, R6, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000106 */
/*0140*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fe40000000006 */
/*0150*/ FADD R4, R2, -c[0x0][0x178] ; /* 0x80005e0002047621 */
/* 0x004fc80000000000 */
/*0160*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000e220000000000 */
/*0170*/ FFMA R6, R4, R7, RZ ; /* 0x0000000704067223 */
/* 0x000fc800000000ff */
/*0180*/ FFMA R8, -R5, R6, R4 ; /* 0x0000000605087223 */
/* 0x000fc80000000104 */
/*0190*/ FFMA R6, R7, R8, R6 ; /* 0x0000000807067223 */
/* 0x000fe20000000006 */
/*01a0*/ @!P0 BRA 0x1d0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*01b0*/ MOV R2, 0x1d0 ; /* 0x000001d000027802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x250 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ FADD.SAT R6, RZ, R6 ; /* 0x00000006ff067221 */
/* 0x000fe20000002000 */
/*01f0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc60007f1e0ff */
/*0200*/ FMUL R6, R6, 255 ; /* 0x437f000006067820 */
/* 0x000fe20000400000 */
/*0210*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fc600000f0eff */
/*0220*/ F2I.TRUNC.NTZ R5, R6 ; /* 0x0000000600057305 */
/* 0x000e24000020f100 */
/*0230*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101104 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ SHF.R.U32.HI R6, RZ, 0x17, R5.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011605 */
/*0260*/ BSSY B1, 0x8b0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0270*/ SHF.R.U32.HI R3, RZ, 0x17, R4.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011604 */
/*0280*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0290*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*02b0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*02c0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ IADD3 R10, R3, -0x1, RZ ; /* 0xffffffff030a7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*02f0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0300*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0310*/ @!P0 BRA 0x490 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0330*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0340*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0350*/ @P0 BRA 0x890 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0370*/ @!P0 BRA 0x870 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0380*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0390*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*03a0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*03b0*/ @!P1 BRA !P2, 0x870 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03c0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*03d0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03e0*/ @P1 BRA 0x850 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0400*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0410*/ @P0 BRA 0x820 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0430*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0440*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0450*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0460*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*0470*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0480*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0490*/ LEA R5, R6, 0xc0800000, 0x17 ; /* 0xc080000006057811 */
/* 0x000fe200078eb8ff */
/*04a0*/ BSSY B2, 0x810 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*04b0*/ IADD3 R4, R3, -0x7f, RZ ; /* 0xffffff8103047810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ IMAD.IADD R5, R8, 0x1, -R5 ; /* 0x0000000108057824 */
/* 0x000fe200078e0a05 */
/*04d0*/ IADD3 R6, R4.reuse, 0x7f, -R6 ; /* 0x0000007f04067810 */
/* 0x040fe20007ffe806 */
/*04e0*/ IMAD R7, R4, -0x800000, R7 ; /* 0xff80000004077824 */
/* 0x000fe400078e0207 */
/*04f0*/ MUFU.RCP R8, R5 ; /* 0x0000000500087308 */
/* 0x000e220000001000 */
/*0500*/ FADD.FTZ R10, -R5, -RZ ; /* 0x800000ff050a7221 */
/* 0x000fe40000010100 */
/*0510*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0520*/ FFMA R3, R8, R10, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000a */
/*0530*/ FFMA R12, R8, R3, R8 ; /* 0x00000003080c7223 */
/* 0x000fc80000000008 */
/*0540*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0550*/ FFMA R8, R10, R3, R7 ; /* 0x000000030a087223 */
/* 0x000fc80000000007 */
/*0560*/ FFMA R11, R12, R8, R3 ; /* 0x000000080c0b7223 */
/* 0x000fc80000000003 */
/*0570*/ FFMA R7, R10, R11, R7 ; /* 0x0000000b0a077223 */
/* 0x000fc80000000007 */
/*0580*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0590*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*05a0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*05b0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*05c0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*05e0*/ @!P0 BRA 0x7f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0600*/ @P0 BRA 0x7c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0620*/ @P0 BRA 0x800 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0640*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0650*/ @!P0 BRA 0x800 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0660*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0670*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0680*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0690*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*06a0*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*06b0*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*06c0*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*06e0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*06f0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0700*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0710*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0720*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0730*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0740*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0750*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0760*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0770*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0780*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0790*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*07a0*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x800 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*07d0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07e0*/ BRA 0x800 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0800*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x8a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0830*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0840*/ BRA 0x8a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0850*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0860*/ BRA 0x8a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0870*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0880*/ BRA 0x8a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0890*/ FADD.FTZ R3, R4, R5 ; /* 0x0000000504037221 */
/* 0x000fe40000010000 */
/*08a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08b0*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0003 */
/*08c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08d0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff72002007950 */
/* 0x000fea0003c3ffff */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convert_float2bgr(float* annd, unsigned char* bgr, int w, int h, float minval, float maxval)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x < w && y < h)
{
int id = y * w + x;
int err = max(min((annd[id] - minval) / (maxval - minval), 1.f), 0.f) * 255.f;
bgr[id] = err;
}
} | .file "tmpxft_001a3f39_00000000-6_convert_float2bgr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff
.type _Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff, @function
_Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17convert_float2bgrPfPhiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff, .-_Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff
.globl _Z17convert_float2bgrPfPhiiff
.type _Z17convert_float2bgrPfPhiiff, @function
_Z17convert_float2bgrPfPhiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17convert_float2bgrPfPhiiff, .-_Z17convert_float2bgrPfPhiiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17convert_float2bgrPfPhiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17convert_float2bgrPfPhiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convert_float2bgr(float* annd, unsigned char* bgr, int w, int h, float minval, float maxval)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x < w && y < h)
{
int id = y * w + x;
int err = max(min((annd[id] - minval) / (maxval - minval), 1.f), 0.f) * 255.f;
bgr[id] = err;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convert_float2bgr(float* annd, unsigned char* bgr, int w, int h, float minval, float maxval)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x < w && y < h)
{
int id = y * w + x;
int err = max(min((annd[id] - minval) / (maxval - minval), 1.f), 0.f) * 255.f;
bgr[id] = err;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convert_float2bgr(float* annd, unsigned char* bgr, int w, int h, float minval, float maxval)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x < w && y < h)
{
int id = y * w + x;
int err = max(min((annd[id] - minval) / (maxval - minval), 1.f), 0.f) * 255.f;
bgr[id] = err;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17convert_float2bgrPfPhiiff
.globl _Z17convert_float2bgrPfPhiiff
.p2align 8
.type _Z17convert_float2bgrPfPhiiff,@function
_Z17convert_float2bgrPfPhiiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_sub_f32_e64 v1, s1, s0
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v0, s0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v1, v1, v0
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v7, vcc_lo, v0, v1, v0
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v4, v1, v0
v_minmax_f32 v0, v0, 1.0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, 0x437f0000, v0
v_cvt_i32_f32_e32 v4, v0
v_add_co_u32 v0, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17convert_float2bgrPfPhiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17convert_float2bgrPfPhiiff, .Lfunc_end0-_Z17convert_float2bgrPfPhiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17convert_float2bgrPfPhiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17convert_float2bgrPfPhiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convert_float2bgr(float* annd, unsigned char* bgr, int w, int h, float minval, float maxval)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x < w && y < h)
{
int id = y * w + x;
int err = max(min((annd[id] - minval) / (maxval - minval), 1.f), 0.f) * 255.f;
bgr[id] = err;
}
} | .text
.file "convert_float2bgr.hip"
.globl _Z32__device_stub__convert_float2bgrPfPhiiff # -- Begin function _Z32__device_stub__convert_float2bgrPfPhiiff
.p2align 4, 0x90
.type _Z32__device_stub__convert_float2bgrPfPhiiff,@function
_Z32__device_stub__convert_float2bgrPfPhiiff: # @_Z32__device_stub__convert_float2bgrPfPhiiff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17convert_float2bgrPfPhiiff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z32__device_stub__convert_float2bgrPfPhiiff, .Lfunc_end0-_Z32__device_stub__convert_float2bgrPfPhiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17convert_float2bgrPfPhiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17convert_float2bgrPfPhiiff,@object # @_Z17convert_float2bgrPfPhiiff
.section .rodata,"a",@progbits
.globl _Z17convert_float2bgrPfPhiiff
.p2align 3, 0x0
_Z17convert_float2bgrPfPhiiff:
.quad _Z32__device_stub__convert_float2bgrPfPhiiff
.size _Z17convert_float2bgrPfPhiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17convert_float2bgrPfPhiiff"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__convert_float2bgrPfPhiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17convert_float2bgrPfPhiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17convert_float2bgrPfPhiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0100*/ BSSY B0, 0x1e0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0110*/ FADD R5, R5, -c[0x0][0x178] ; /* 0x80005e0005057621 */
/* 0x000fc80000000000 */
/*0120*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*0130*/ FFMA R7, -R5, R6, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000106 */
/*0140*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fe40000000006 */
/*0150*/ FADD R4, R2, -c[0x0][0x178] ; /* 0x80005e0002047621 */
/* 0x004fc80000000000 */
/*0160*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000e220000000000 */
/*0170*/ FFMA R6, R4, R7, RZ ; /* 0x0000000704067223 */
/* 0x000fc800000000ff */
/*0180*/ FFMA R8, -R5, R6, R4 ; /* 0x0000000605087223 */
/* 0x000fc80000000104 */
/*0190*/ FFMA R6, R7, R8, R6 ; /* 0x0000000807067223 */
/* 0x000fe20000000006 */
/*01a0*/ @!P0 BRA 0x1d0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*01b0*/ MOV R2, 0x1d0 ; /* 0x000001d000027802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x250 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ FADD.SAT R6, RZ, R6 ; /* 0x00000006ff067221 */
/* 0x000fe20000002000 */
/*01f0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc60007f1e0ff */
/*0200*/ FMUL R6, R6, 255 ; /* 0x437f000006067820 */
/* 0x000fe20000400000 */
/*0210*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fc600000f0eff */
/*0220*/ F2I.TRUNC.NTZ R5, R6 ; /* 0x0000000600057305 */
/* 0x000e24000020f100 */
/*0230*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101104 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ SHF.R.U32.HI R6, RZ, 0x17, R5.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011605 */
/*0260*/ BSSY B1, 0x8b0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0270*/ SHF.R.U32.HI R3, RZ, 0x17, R4.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011604 */
/*0280*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0290*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*02b0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*02c0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ IADD3 R10, R3, -0x1, RZ ; /* 0xffffffff030a7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*02f0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0300*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0310*/ @!P0 BRA 0x490 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0330*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0340*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0350*/ @P0 BRA 0x890 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0370*/ @!P0 BRA 0x870 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0380*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0390*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*03a0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*03b0*/ @!P1 BRA !P2, 0x870 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03c0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*03d0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03e0*/ @P1 BRA 0x850 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0400*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0410*/ @P0 BRA 0x820 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0430*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0440*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0450*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0460*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*0470*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0480*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0490*/ LEA R5, R6, 0xc0800000, 0x17 ; /* 0xc080000006057811 */
/* 0x000fe200078eb8ff */
/*04a0*/ BSSY B2, 0x810 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*04b0*/ IADD3 R4, R3, -0x7f, RZ ; /* 0xffffff8103047810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ IMAD.IADD R5, R8, 0x1, -R5 ; /* 0x0000000108057824 */
/* 0x000fe200078e0a05 */
/*04d0*/ IADD3 R6, R4.reuse, 0x7f, -R6 ; /* 0x0000007f04067810 */
/* 0x040fe20007ffe806 */
/*04e0*/ IMAD R7, R4, -0x800000, R7 ; /* 0xff80000004077824 */
/* 0x000fe400078e0207 */
/*04f0*/ MUFU.RCP R8, R5 ; /* 0x0000000500087308 */
/* 0x000e220000001000 */
/*0500*/ FADD.FTZ R10, -R5, -RZ ; /* 0x800000ff050a7221 */
/* 0x000fe40000010100 */
/*0510*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0520*/ FFMA R3, R8, R10, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000a */
/*0530*/ FFMA R12, R8, R3, R8 ; /* 0x00000003080c7223 */
/* 0x000fc80000000008 */
/*0540*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0550*/ FFMA R8, R10, R3, R7 ; /* 0x000000030a087223 */
/* 0x000fc80000000007 */
/*0560*/ FFMA R11, R12, R8, R3 ; /* 0x000000080c0b7223 */
/* 0x000fc80000000003 */
/*0570*/ FFMA R7, R10, R11, R7 ; /* 0x0000000b0a077223 */
/* 0x000fc80000000007 */
/*0580*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0590*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*05a0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*05b0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*05c0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*05e0*/ @!P0 BRA 0x7f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0600*/ @P0 BRA 0x7c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0620*/ @P0 BRA 0x800 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0640*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0650*/ @!P0 BRA 0x800 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0660*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0670*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0680*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0690*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*06a0*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*06b0*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*06c0*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*06e0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*06f0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0700*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0710*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0720*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0730*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0740*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0750*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0760*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0770*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0780*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0790*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*07a0*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x800 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*07d0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07e0*/ BRA 0x800 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0800*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x8a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0830*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0840*/ BRA 0x8a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0850*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0860*/ BRA 0x8a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0870*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0880*/ BRA 0x8a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0890*/ FADD.FTZ R3, R4, R5 ; /* 0x0000000504037221 */
/* 0x000fe40000010000 */
/*08a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08b0*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0003 */
/*08c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08d0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff72002007950 */
/* 0x000fea0003c3ffff */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17convert_float2bgrPfPhiiff
.globl _Z17convert_float2bgrPfPhiiff
.p2align 8
.type _Z17convert_float2bgrPfPhiiff,@function
_Z17convert_float2bgrPfPhiiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_sub_f32_e64 v1, s1, s0
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v0, s0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v1, v1, v0
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v7, vcc_lo, v0, v1, v0
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v4, v1, v0
v_minmax_f32 v0, v0, 1.0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, 0x437f0000, v0
v_cvt_i32_f32_e32 v4, v0
v_add_co_u32 v0, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17convert_float2bgrPfPhiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17convert_float2bgrPfPhiiff, .Lfunc_end0-_Z17convert_float2bgrPfPhiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17convert_float2bgrPfPhiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17convert_float2bgrPfPhiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a3f39_00000000-6_convert_float2bgr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff
.type _Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff, @function
_Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17convert_float2bgrPfPhiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff, .-_Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff
.globl _Z17convert_float2bgrPfPhiiff
.type _Z17convert_float2bgrPfPhiiff, @function
_Z17convert_float2bgrPfPhiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17convert_float2bgrPfPhiiffPfPhiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17convert_float2bgrPfPhiiff, .-_Z17convert_float2bgrPfPhiiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17convert_float2bgrPfPhiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17convert_float2bgrPfPhiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convert_float2bgr.hip"
.globl _Z32__device_stub__convert_float2bgrPfPhiiff # -- Begin function _Z32__device_stub__convert_float2bgrPfPhiiff
.p2align 4, 0x90
.type _Z32__device_stub__convert_float2bgrPfPhiiff,@function
_Z32__device_stub__convert_float2bgrPfPhiiff: # @_Z32__device_stub__convert_float2bgrPfPhiiff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17convert_float2bgrPfPhiiff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z32__device_stub__convert_float2bgrPfPhiiff, .Lfunc_end0-_Z32__device_stub__convert_float2bgrPfPhiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17convert_float2bgrPfPhiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17convert_float2bgrPfPhiiff,@object # @_Z17convert_float2bgrPfPhiiff
.section .rodata,"a",@progbits
.globl _Z17convert_float2bgrPfPhiiff
.p2align 3, 0x0
_Z17convert_float2bgrPfPhiiff:
.quad _Z32__device_stub__convert_float2bgrPfPhiiff
.size _Z17convert_float2bgrPfPhiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17convert_float2bgrPfPhiiff"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__convert_float2bgrPfPhiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17convert_float2bgrPfPhiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
__global__ void arradd(int* md, int* nd, int* pd)
{
int myid = threadIdx.x;
pd[myid] = md[myid] + nd[myid];
}
int main()
{
int size = 200 * sizeof(int);
int m[200], n[200], p[200],*md, *nd,*pd;
int i=0;
for(i=0; i<200; i++ )
{
m[i] = i;
n[i] = i;
p[i] = 0;
}
cudaMalloc(&md, size);
cudaMemcpy(md, m, size, cudaMemcpyHostToDevice);
cudaMalloc(&nd, size);
cudaMemcpy(nd, n, size, cudaMemcpyHostToDevice);
cudaMalloc(&pd, size);
dim3 DimGrid(1, 1);
dim3 DimBlock(200, 1);
arradd<<< DimGrid,DimBlock >>>(md,nd,pd);
cudaMemcpy(p, pd, size, cudaMemcpyDeviceToHost);
for(i=0; i<200; i++ )
{
printf("\t%d",p[i]);
}
cudaFree(md);
cudaFree(nd);
cudaFree(pd);
} | code for sm_80
Function : _Z6arraddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
__global__ void arradd(int* md, int* nd, int* pd)
{
int myid = threadIdx.x;
pd[myid] = md[myid] + nd[myid];
}
int main()
{
int size = 200 * sizeof(int);
int m[200], n[200], p[200],*md, *nd,*pd;
int i=0;
for(i=0; i<200; i++ )
{
m[i] = i;
n[i] = i;
p[i] = 0;
}
cudaMalloc(&md, size);
cudaMemcpy(md, m, size, cudaMemcpyHostToDevice);
cudaMalloc(&nd, size);
cudaMemcpy(nd, n, size, cudaMemcpyHostToDevice);
cudaMalloc(&pd, size);
dim3 DimGrid(1, 1);
dim3 DimBlock(200, 1);
arradd<<< DimGrid,DimBlock >>>(md,nd,pd);
cudaMemcpy(p, pd, size, cudaMemcpyDeviceToHost);
for(i=0; i<200; i++ )
{
printf("\t%d",p[i]);
}
cudaFree(md);
cudaFree(nd);
cudaFree(pd);
} | .file "tmpxft_00149573_00000000-6_vector_add_1D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6arraddPiS_S_PiS_S_
.type _Z29__device_stub__Z6arraddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6arraddPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6arraddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6arraddPiS_S_PiS_S_, .-_Z29__device_stub__Z6arraddPiS_S_PiS_S_
.globl _Z6arraddPiS_S_
.type _Z6arraddPiS_S_, @function
_Z6arraddPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6arraddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6arraddPiS_S_, .-_Z6arraddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\t%d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $2464, %rsp
.cfi_def_cfa_offset 2496
movq %fs:40, %rax
movq %rax, 2456(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %eax, 848(%rsp,%rax,4)
movl $0, 1648(%rsp,%rax,4)
addq $1, %rax
cmpq $200, %rax
jne .L12
movq %rsp, %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $800, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 848(%rsp), %rsi
movl $1, %ecx
movl $800, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $200, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 1648(%rsp), %rbx
movl $2, %ecx
movl $800, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 2448(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 2456(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $2464, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6arraddPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6arraddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6arraddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
__global__ void arradd(int* md, int* nd, int* pd)
{
int myid = threadIdx.x;
pd[myid] = md[myid] + nd[myid];
}
int main()
{
int size = 200 * sizeof(int);
int m[200], n[200], p[200],*md, *nd,*pd;
int i=0;
for(i=0; i<200; i++ )
{
m[i] = i;
n[i] = i;
p[i] = 0;
}
cudaMalloc(&md, size);
cudaMemcpy(md, m, size, cudaMemcpyHostToDevice);
cudaMalloc(&nd, size);
cudaMemcpy(nd, n, size, cudaMemcpyHostToDevice);
cudaMalloc(&pd, size);
dim3 DimGrid(1, 1);
dim3 DimBlock(200, 1);
arradd<<< DimGrid,DimBlock >>>(md,nd,pd);
cudaMemcpy(p, pd, size, cudaMemcpyDeviceToHost);
for(i=0; i<200; i++ )
{
printf("\t%d",p[i]);
}
cudaFree(md);
cudaFree(nd);
cudaFree(pd);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void arradd(int* md, int* nd, int* pd)
{
int myid = threadIdx.x;
pd[myid] = md[myid] + nd[myid];
}
int main()
{
int size = 200 * sizeof(int);
int m[200], n[200], p[200],*md, *nd,*pd;
int i=0;
for(i=0; i<200; i++ )
{
m[i] = i;
n[i] = i;
p[i] = 0;
}
hipMalloc(&md, size);
hipMemcpy(md, m, size, hipMemcpyHostToDevice);
hipMalloc(&nd, size);
hipMemcpy(nd, n, size, hipMemcpyHostToDevice);
hipMalloc(&pd, size);
dim3 DimGrid(1, 1);
dim3 DimBlock(200, 1);
arradd<<< DimGrid,DimBlock >>>(md,nd,pd);
hipMemcpy(p, pd, size, hipMemcpyDeviceToHost);
for(i=0; i<200; i++ )
{
printf("\t%d",p[i]);
}
hipFree(md);
hipFree(nd);
hipFree(pd);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void arradd(int* md, int* nd, int* pd)
{
int myid = threadIdx.x;
pd[myid] = md[myid] + nd[myid];
}
int main()
{
int size = 200 * sizeof(int);
int m[200], n[200], p[200],*md, *nd,*pd;
int i=0;
for(i=0; i<200; i++ )
{
m[i] = i;
n[i] = i;
p[i] = 0;
}
hipMalloc(&md, size);
hipMemcpy(md, m, size, hipMemcpyHostToDevice);
hipMalloc(&nd, size);
hipMemcpy(nd, n, size, hipMemcpyHostToDevice);
hipMalloc(&pd, size);
dim3 DimGrid(1, 1);
dim3 DimBlock(200, 1);
arradd<<< DimGrid,DimBlock >>>(md,nd,pd);
hipMemcpy(p, pd, size, hipMemcpyDeviceToHost);
for(i=0; i<200; i++ )
{
printf("\t%d",p[i]);
}
hipFree(md);
hipFree(nd);
hipFree(pd);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6arraddPiS_S_
.globl _Z6arraddPiS_S_
.p2align 8
.type _Z6arraddPiS_S_,@function
_Z6arraddPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6arraddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6arraddPiS_S_, .Lfunc_end0-_Z6arraddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6arraddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6arraddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void arradd(int* md, int* nd, int* pd)
{
int myid = threadIdx.x;
pd[myid] = md[myid] + nd[myid];
}
int main()
{
int size = 200 * sizeof(int);
int m[200], n[200], p[200],*md, *nd,*pd;
int i=0;
for(i=0; i<200; i++ )
{
m[i] = i;
n[i] = i;
p[i] = 0;
}
hipMalloc(&md, size);
hipMemcpy(md, m, size, hipMemcpyHostToDevice);
hipMalloc(&nd, size);
hipMemcpy(nd, n, size, hipMemcpyHostToDevice);
hipMalloc(&pd, size);
dim3 DimGrid(1, 1);
dim3 DimBlock(200, 1);
arradd<<< DimGrid,DimBlock >>>(md,nd,pd);
hipMemcpy(p, pd, size, hipMemcpyDeviceToHost);
for(i=0; i<200; i++ )
{
printf("\t%d",p[i]);
}
hipFree(md);
hipFree(nd);
hipFree(pd);
} | .text
.file "vector_add_1D.hip"
.globl _Z21__device_stub__arraddPiS_S_ # -- Begin function _Z21__device_stub__arraddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__arraddPiS_S_,@function
_Z21__device_stub__arraddPiS_S_: # @_Z21__device_stub__arraddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6arraddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__arraddPiS_S_, .Lfunc_end0-_Z21__device_stub__arraddPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2528, %rsp # imm = 0x9E0
.cfi_def_cfa_offset 2544
.cfi_offset %rbx, -16
leaq 128(%rsp), %rdi
xorl %ebx, %ebx
movl $800, %edx # imm = 0x320
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 1728(%rsp,%rbx,4)
movl %ebx, 928(%rsp,%rbx,4)
incq %rbx
cmpq $200, %rbx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq 16(%rsp), %rdi
leaq 1728(%rsp), %rsi
movl $800, %edx # imm = 0x320
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq 8(%rsp), %rdi
leaq 928(%rsp), %rsi
movl $800, %edx # imm = 0x320
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 199(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6arraddPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $800, %edx # imm = 0x320
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $200, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $2528, %rsp # imm = 0x9E0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6arraddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6arraddPiS_S_,@object # @_Z6arraddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6arraddPiS_S_
.p2align 3, 0x0
_Z6arraddPiS_S_:
.quad _Z21__device_stub__arraddPiS_S_
.size _Z6arraddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\t%d"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6arraddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__arraddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6arraddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6arraddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6arraddPiS_S_
.globl _Z6arraddPiS_S_
.p2align 8
.type _Z6arraddPiS_S_,@function
_Z6arraddPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6arraddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6arraddPiS_S_, .Lfunc_end0-_Z6arraddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6arraddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6arraddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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