system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <algorithm>
#include <cfloat>
#include <chrono>
#include <fstream>
#include <iostream>
#include <random>
#include <sstream>
#include <vector>
struct Data {
Data(int size) : size(size), bytes(size * sizeof(float)) {
cudaMalloc(&x, bytes);
cudaMalloc(&y, bytes);
}
Data(int size, std::vector<float>& h_x, std::vector<float>& h_y)
: size(size), bytes(size * sizeof(float)) {
cudaMalloc(&x, bytes);
cudaMalloc(&y, bytes);
cudaMemcpy(x, h_x.data(), bytes, cudaMemcpyHostToDevice);
cudaMemcpy(y, h_y.data(), bytes, cudaMemcpyHostToDevice);
}
~Data() {
cudaFree(x);
cudaFree(y);
}
void clear() {
cudaMemset(x, 0, bytes);
cudaMemset(y, 0, bytes);
}
float* x{nullptr};
float* y{nullptr};
int size{0};
int bytes{0};
};
__device__ float
squared_l2_distance(float x_1, float y_1, float x_2, float y_2) {
return (x_1 - x_2) * (x_1 - x_2) + (y_1 - y_2) * (y_1 - y_2);
}
__global__ void assign_clusters(const float* __restrict__ data_x,
const float* __restrict__ data_y,
int data_size,
const float* __restrict__ means_x,
const float* __restrict__ means_y,
float* __restrict__ new_sums_x,
float* __restrict__ new_sums_y,
int k,
int* __restrict__ counts) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= data_size) return;
// Make global loads once.
const float x = data_x[index];
const float y = data_y[index];
float best_distance = FLT_MAX;
int best_cluster = 0;
for (int cluster = 0; cluster < k; ++cluster) {
const float distance =
squared_l2_distance(x, y, means_x[cluster], means_y[cluster]);
if (distance < best_distance) {
best_distance = distance;
best_cluster = cluster;
}
}
atomicAdd(&new_sums_x[best_cluster], x);
atomicAdd(&new_sums_y[best_cluster], y);
atomicAdd(&counts[best_cluster], 1);
}
__global__ void compute_new_means(float* __restrict__ means_x,
float* __restrict__ means_y,
const float* __restrict__ new_sum_x,
const float* __restrict__ new_sum_y,
const int* __restrict__ counts) {
const int cluster = threadIdx.x;
const int count = max(1, counts[cluster]);
means_x[cluster] = new_sum_x[cluster] / count;
means_y[cluster] = new_sum_y[cluster] / count;
}
int main(int argc, const char* argv[]) {
if (argc < 4) {
std::cerr << "usage: assign_clusters <data-file> <k> [iterations]"
<< std::endl;
std::exit(EXIT_FAILURE);
}
const auto k = std::atoi(argv[3]);
std::cout<<argc<<std::endl;
const auto number_of_iterations = (argc == 4) ? std::atoi(argv[4]) : 300;
std::vector<float> h_x;
std::vector<float> h_y;
std::ifstream stream(argv[2]);
std::string line;
while (std::getline(stream, line)) {
std::istringstream line_stream(line);
float x, y;
uint16_t label;
line_stream >> x >> y >> label;
h_x.push_back(x);
h_y.push_back(y);
}
const size_t number_of_elements = h_x.size();
Data d_data(number_of_elements, h_x, h_y);
std::mt19937 rng(std::random_device{}());
std::shuffle(h_x.begin(), h_x.end(), rng);
std::shuffle(h_y.begin(), h_y.end(), rng);
Data d_means(k, h_x, h_y);
Data d_sums(k);
int* d_counts;
cudaMalloc(&d_counts, k * sizeof(int));
cudaMemset(d_counts, 0, k * sizeof(int));
const int threads = 1024;
const int blocks = (number_of_elements + threads - 1) / threads;
const auto start = std::chrono::high_resolution_clock::now();
for (size_t iteration = 0; iteration < number_of_iterations; ++iteration) {
cudaMemset(d_counts, 0, k * sizeof(int));
d_sums.clear();
assign_clusters<<<blocks, threads>>>(d_data.x,
d_data.y,
d_data.size,
d_means.x,
d_means.y,
d_sums.x,
d_sums.y,
k,
d_counts);
cudaDeviceSynchronize();
compute_new_means<<<1, k>>>(d_means.x,
d_means.y,
d_sums.x,
d_sums.y,
d_counts);
cudaDeviceSynchronize();
}
const auto end = std::chrono::high_resolution_clock::now();
const auto duration =
std::chrono::duration_cast<std::chrono::duration<float>>(end - start);
std::cerr << "Took: " << duration.count() << "s" << " " << std::endl;
cudaFree(d_counts);
std::vector<float> mean_x(k, 0);
std::vector<float> mean_y(k, 0);
cudaMemcpy(mean_x.data(), d_means.x, d_means.bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(mean_y.data(), d_means.y, d_means.bytes, cudaMemcpyDeviceToHost);
for (size_t cluster = 0; cluster < k; ++cluster) {
std::cout << mean_x[cluster] << " " << mean_y[cluster] << std::endl;
}
} | code for sm_80
Function : _Z17compute_new_meansPfS_PKfS1_PKi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R4, R0, R7, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x001fcc00078e0207 */
/*0050*/ LDG.E.CONSTANT R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e9900 */
/*0060*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E.CONSTANT R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e9900 */
/*0080*/ BSSY B0, 0x160 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0090*/ IMNMX R2, R4, 0x1, !PT ; /* 0x0000000104027817 */
/* 0x004fcc0007800200 */
/*00a0*/ I2F R2, R2 ; /* 0x0000000200027306 */
/* 0x000e300000201400 */
/*00b0*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x001e300000001000 */
/*00c0*/ FCHK P0, R7, R2 ; /* 0x0000000207007302 */
/* 0x008e620000000000 */
/*00d0*/ FFMA R8, -R2, R3, 1 ; /* 0x3f80000002087423 */
/* 0x001fc80000000103 */
/*00e0*/ FFMA R8, R3, R8, R3 ; /* 0x0000000803087223 */
/* 0x000fc80000000003 */
/*00f0*/ FFMA R3, R7, R8, RZ ; /* 0x0000000807037223 */
/* 0x000fc800000000ff */
/*0100*/ FFMA R9, -R2, R3, R7 ; /* 0x0000000302097223 */
/* 0x000fc80000000107 */
/*0110*/ FFMA R3, R8, R9, R3 ; /* 0x0000000908037223 */
/* 0x000fe20000000003 */
/*0120*/ @!P0 BRA 0x150 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0130*/ MOV R4, 0x150 ; /* 0x0000015000047802 */
/* 0x000fe40000000f00 */
/*0140*/ CALL.REL.NOINC 0x2c0 ; /* 0x0000017000007944 */
/* 0x000fea0003c00000 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.WIDE R6, R0, R5, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fcc00078e0205 */
/*0180*/ LDG.E.CONSTANT R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e9900 */
/*0190*/ MUFU.RCP R9, R2 ; /* 0x0000000200097308 */
/* 0x000e620000001000 */
/*01a0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0205 */
/*01b0*/ BSSY B0, 0x280 ; /* 0x000000c000007945 */
/* 0x000fe80003800000 */
/*01c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011e2000c101904 */
/*01d0*/ FFMA R8, -R2, R9, 1 ; /* 0x3f80000002087423 */
/* 0x002fc80000000109 */
/*01e0*/ FFMA R10, R9, R8, R9 ; /* 0x00000008090a7223 */
/* 0x000fe20000000009 */
/*01f0*/ FCHK P0, R7, R2 ; /* 0x0000000207007302 */
/* 0x004e660000000000 */
/*0200*/ FFMA R8, R10, R7, RZ ; /* 0x000000070a087223 */
/* 0x000fc800000000ff */
/*0210*/ FFMA R9, -R2, R8, R7 ; /* 0x0000000802097223 */
/* 0x000fc80000000107 */
/*0220*/ FFMA R9, R10, R9, R8 ; /* 0x000000090a097223 */
/* 0x000fe20000000008 */
/*0230*/ @!P0 BRA 0x270 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0240*/ MOV R4, 0x260 ; /* 0x0000026000047802 */
/* 0x001fe40000000f00 */
/*0250*/ CALL.REL.NOINC 0x2c0 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*0260*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0003 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0280*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ SHF.R.U32.HI R5, RZ, 0x17, R2.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011602 */
/*02d0*/ BSSY B1, 0x920 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*02e0*/ SHF.R.U32.HI R3, RZ, 0x17, R7.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011607 */
/*02f0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0300*/ LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050b7812 */
/* 0x000fe400078ec0ff */
/*0310*/ LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03097812 */
/* 0x000fe200078ec0ff */
/*0320*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*0330*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R8, R9, -0x1, RZ ; /* 0xffffffff09087810 */
/* 0x000fc40007ffe0ff */
/*0350*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0360*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*0370*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff058224 */
/* 0x000fe200078e00ff */
/*0380*/ @!P0 BRA 0x500 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0390*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1c200 */
/*03a0*/ FSETP.GTU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f3c200 */
/*03b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03c0*/ @P0 BRA 0x900 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*03d0*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c803 */
/*03e0*/ @!P0 BRA 0x8e0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03f0*/ FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ; /* 0x7f8000000700780b */
/* 0x040fe40003f5d200 */
/*0400*/ FSETP.NEU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f3d200 */
/*0410*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fd60003f1d200 */
/*0420*/ @!P1 BRA !P2, 0x8e0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0430*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*0440*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0450*/ @P1 BRA 0x8c0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0460*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0470*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0480*/ @P0 BRA 0x890 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0490*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*04a0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*04b0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe400078e00ff */
/*04c0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ; /* 0xffffffc0ff058424 */
/* 0x000fe400078e00ff */
/*04d0*/ @!P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007038823 */
/* 0x000fe400000000ff */
/*04e0*/ @!P1 FFMA R6, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002069823 */
/* 0x000fe200000000ff */
/*04f0*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*0500*/ LEA R7, R11, 0xc0800000, 0x17 ; /* 0xc08000000b077811 */
/* 0x000fe200078eb8ff */
/*0510*/ BSSY B2, 0x880 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0520*/ IMAD.IADD R7, R6, 0x1, -R7 ; /* 0x0000000106077824 */
/* 0x000fe200078e0a07 */
/*0530*/ IADD3 R6, R9, -0x7f, RZ ; /* 0xffffff8109067810 */
/* 0x000fc60007ffe0ff */
/*0540*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e220000001000 */
/*0550*/ FADD.FTZ R10, -R7, -RZ ; /* 0x800000ff070a7221 */
/* 0x000fe40000010100 */
/*0560*/ IMAD R3, R6, -0x800000, R3 ; /* 0xff80000006037824 */
/* 0x000fe400078e0203 */
/*0570*/ FFMA R9, R8, R10, 1 ; /* 0x3f80000008097423 */
/* 0x001fc8000000000a */
/*0580*/ FFMA R12, R8, R9, R8 ; /* 0x00000009080c7223 */
/* 0x000fc80000000008 */
/*0590*/ FFMA R8, R3, R12, RZ ; /* 0x0000000c03087223 */
/* 0x000fc800000000ff */
/*05a0*/ FFMA R9, R10, R8, R3 ; /* 0x000000080a097223 */
/* 0x000fc80000000003 */
/*05b0*/ FFMA R9, R12, R9, R8 ; /* 0x000000090c097223 */
/* 0x000fe20000000008 */
/*05c0*/ IADD3 R8, R6, 0x7f, -R11 ; /* 0x0000007f06087810 */
/* 0x000fc60007ffe80b */
/*05d0*/ FFMA R10, R10, R9, R3 ; /* 0x000000090a0a7223 */
/* 0x000fe40000000003 */
/*05e0*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fe400078e0205 */
/*05f0*/ FFMA R3, R12, R10, R9 ; /* 0x0000000a0c037223 */
/* 0x000fca0000000009 */
/*0600*/ SHF.R.U32.HI R6, RZ, 0x17, R3 ; /* 0x00000017ff067819 */
/* 0x000fc80000011603 */
/*0610*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*0620*/ IMAD.IADD R11, R6, 0x1, R8 ; /* 0x00000001060b7824 */
/* 0x000fca00078e0208 */
/*0630*/ IADD3 R5, R11, -0x1, RZ ; /* 0xffffffff0b057810 */
/* 0x000fc80007ffe0ff */
/*0640*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0650*/ @!P0 BRA 0x860 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0660*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0670*/ @P0 BRA 0x830 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0690*/ @P0 BRA 0x870 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*06a0*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*06b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*06c0*/ @!P0 BRA 0x870 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*06d0*/ FFMA.RZ R5, R12.reuse, R10.reuse, R9.reuse ; /* 0x0000000a0c057223 */
/* 0x1c0fe2000000c009 */
/*06e0*/ IADD3 R8, R11.reuse, 0x20, RZ ; /* 0x000000200b087810 */
/* 0x040fe20007ffe0ff */
/*06f0*/ FFMA.RM R6, R12.reuse, R10.reuse, R9.reuse ; /* 0x0000000a0c067223 */
/* 0x1c0fe20000004009 */
/*0700*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0710*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0720*/ FFMA.RP R5, R12, R10, R9 ; /* 0x0000000a0c057223 */
/* 0x000fe20000008009 */
/*0730*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*0740*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0b */
/*0750*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0760*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0770*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0780*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0790*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*07a0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*07b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*07c0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*07d0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*07e0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*07f0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0800*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*0810*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*0820*/ BRA 0x870 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0840*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ IMAD R3, R8, 0x800000, R3 ; /* 0x0080000008037824 */
/* 0x000fe400078e0203 */
/*0870*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0880*/ BRA 0x910 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0890*/ LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fc800078e4803 */
/*08a0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*08b0*/ BRA 0x910 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fe200078e4803 */
/*08d0*/ BRA 0x910 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*08e0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*08f0*/ BRA 0x910 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0900*/ FADD.FTZ R3, R7, R2 ; /* 0x0000000207037221 */
/* 0x000fe40000010000 */
/*0910*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0920*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0930*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff6c004007950 */
/* 0x000fea0003c3ffff */
/*0940*/ BRA 0x940; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff087624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD.WIDE R4, R6, R3, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R6, R6, R3, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0203 */
/*00c0*/ LDG.E.CONSTANT R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000168000c1e9900 */
/*00d0*/ LDG.E.CONSTANT R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000362000c1e9900 */
/*00e0*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x001fe4000001ff00 */
/*00f0*/ @!P0 BRA 0x620 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R8.reuse, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x002fe200078e00ff */
/*0120*/ LOP3.LUT R5, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308057812 */
/* 0x000fc400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0160*/ MOV R7, 0x7f7fffff ; /* 0x7f7fffff00077802 */
/* 0x000fd20000000f00 */
/*0170*/ @!P1 BRA 0x450 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R16, -R5, c[0x0][0x198], RZ ; /* 0x0000660005107a10 */
/* 0x000fe20007ffe1ff */
/*0190*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*01a0*/ MOV R7, 0x7f7fffff ; /* 0x7f7fffff00077802 */
/* 0x000fc60000000f00 */
/*01b0*/ IMAD.WIDE R10, R6, R3, c[0x0][0x180] ; /* 0x00006000060a7625 */
/* 0x000fc800078e0203 */
/*01c0*/ IMAD.WIDE R8, R6, R3, c[0x0][0x178] ; /* 0x00005e0006087625 */
/* 0x000fe200078e0203 */
/*01d0*/ LDG.E.CONSTANT R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ea8000c1e9900 */
/*01e0*/ LDG.E.CONSTANT R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ee8000c1e9900 */
/*01f0*/ LDG.E.CONSTANT R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000f28000c1e9900 */
/*0200*/ LDG.E.CONSTANT R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x000f28000c1e9900 */
/*0210*/ LDG.E.CONSTANT R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f28000c1e9900 */
/*0220*/ LDG.E.CONSTANT R13, [R8.64+0x8] ; /* 0x00000804080d7981 */
/* 0x000f28000c1e9900 */
/*0230*/ LDG.E.CONSTANT R15, [R10.64+0xc] ; /* 0x00000c040a0f7981 */
/* 0x000f28000c1e9900 */
/*0240*/ LDG.E.CONSTANT R17, [R8.64+0xc] ; /* 0x00000c0408117981 */
/* 0x000122000c1e9900 */
/*0250*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fe20007ffe0ff */
/*0260*/ FADD R21, R2, -R21 ; /* 0x8000001502157221 */
/* 0x024fc40000000000 */
/*0270*/ FADD R19, R0, -R19 ; /* 0x8000001300137221 */
/* 0x008fe40000000000 */
/*0280*/ FMUL R12, R21, R21 ; /* 0x00000015150c7220 */
/* 0x000fe40000400000 */
/*0290*/ FADD R25, R2, -R25 ; /* 0x8000001902197221 */
/* 0x010fe40000000000 */
/*02a0*/ FFMA R12, R19, R19, R12 ; /* 0x00000013130c7223 */
/* 0x000fe4000000000c */
/*02b0*/ FADD R23, R0, -R23 ; /* 0x8000001700177221 */
/* 0x000fe40000000000 */
/*02c0*/ FMUL R14, R25, R25 ; /* 0x00000019190e7220 */
/* 0x000fe20000400000 */
/*02d0*/ FSETP.GEU.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720b */
/* 0x000fe20003f4e000 */
/*02e0*/ FADD R27, R2, -R27 ; /* 0x8000001b021b7221 */
/* 0x000fc40000000000 */
/*02f0*/ FFMA R14, R23, R23, R14 ; /* 0x00000017170e7223 */
/* 0x000fe2000000000e */
/*0300*/ FSEL R7, R12, R7, !P2 ; /* 0x000000070c077208 */
/* 0x000fe20005000000 */
/*0310*/ FADD R13, R0, -R13 ; /* 0x8000000d000d7221 */
/* 0x000fe20000000000 */
/*0320*/ SEL R4, R6, R4, !P2 ; /* 0x0000000406047207 */
/* 0x000fe20005000000 */
/*0330*/ FMUL R8, R27, R27 ; /* 0x0000001b1b087220 */
/* 0x001fe20000400000 */
/*0340*/ FSETP.GEU.AND P3, PT, R14, R7, PT ; /* 0x000000070e00720b */
/* 0x000fe20003f6e000 */
/*0350*/ FADD R15, R2, -R15 ; /* 0x8000000f020f7221 */
/* 0x000fe20000000000 */
/*0360*/ ISETP.NE.AND P2, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f45270 */
/*0370*/ FFMA R8, R13, R13, R8 ; /* 0x0000000d0d087223 */
/* 0x000fe20000000008 */
/*0380*/ FSEL R7, R14, R7, !P3 ; /* 0x000000070e077208 */
/* 0x000fe20005800000 */
/*0390*/ FADD R17, R0, -R17 ; /* 0x8000001100117221 */
/* 0x000fc40000000000 */
/*03a0*/ FMUL R10, R15, R15 ; /* 0x0000000f0f0a7220 */
/* 0x000fe20000400000 */
/*03b0*/ FSETP.GEU.AND P4, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x000fc60003f8e000 */
/*03c0*/ FFMA R10, R17, R17, R10 ; /* 0x00000011110a7223 */
/* 0x000fe2000000000a */
/*03d0*/ FSEL R7, R8, R7, !P4 ; /* 0x0000000708077208 */
/* 0x000fe40006000000 */
/*03e0*/ @!P3 IADD3 R4, R6, 0x1, RZ ; /* 0x000000010604b810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ FSETP.GEU.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x000fc80003f2e000 */
/*0400*/ FSEL R7, R10, R7, !P1 ; /* 0x000000070a077208 */
/* 0x000fe40004800000 */
/*0410*/ @!P4 IADD3 R4, R6, 0x2, RZ ; /* 0x000000020604c810 */
/* 0x000fce0007ffe0ff */
/*0420*/ @!P1 IADD3 R4, R6.reuse, 0x3, RZ ; /* 0x0000000306049810 */
/* 0x040fe40007ffe0ff */
/*0430*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0440*/ @P2 BRA 0x1b0 ; /* 0xfffffd6000002947 */
/* 0x000fea000383ffff */
/*0450*/ @!P0 BRA 0x610 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0460*/ IMAD.WIDE R8, R6, R3, c[0x0][0x180] ; /* 0x0000600006087625 */
/* 0x000fc800078e0203 */
/*0470*/ IMAD.WIDE R10, R6, R3, c[0x0][0x178] ; /* 0x00005e00060a7625 */
/* 0x000fe200078e0203 */
/*0480*/ MOV R15, R9 ; /* 0x00000009000f7202 */
/* 0x000fc60000000f00 */
/*0490*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0008 */
/*04a0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*04b0*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e000b */
/*04c0*/ MOV R8, R14 ; /* 0x0000000e00087202 */
/* 0x000fe20000000f00 */
/*04d0*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000f */
/*04e0*/ LDG.E.CONSTANT R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a4000c1e9900 */
/*04f0*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x001fe200078e000c */
/*0500*/ MOV R9, R13 ; /* 0x0000000d00097202 */
/* 0x000fca0000000f00 */
/*0510*/ LDG.E.CONSTANT R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x000ee2000c1e9900 */
/*0520*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R14, P2, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007f5e0ff */
/*0540*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f25270 */
/*0550*/ IADD3 R12, P3, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007f7e0ff */
/*0560*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fc800010e060f */
/*0570*/ IMAD.X R13, RZ, RZ, R13, P3 ; /* 0x000000ffff0d7224 */
/* 0x000fe400018e060d */
/*0580*/ FADD R11, R2, -R11 ; /* 0x8000000b020b7221 */
/* 0x024fc80000000000 */
/*0590*/ FMUL R10, R11, R11 ; /* 0x0000000b0b0a7220 */
/* 0x000fe40000400000 */
/*05a0*/ FADD R3, R0, -R3 ; /* 0x8000000300037221 */
/* 0x008fc80000000000 */
/*05b0*/ FFMA R10, R3, R3, R10 ; /* 0x00000003030a7223 */
/* 0x000fca000000000a */
/*05c0*/ FSETP.GEU.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x000fc80003f0e000 */
/*05d0*/ SEL R4, R6, R4, !P0 ; /* 0x0000000406047207 */
/* 0x000fe40004000000 */
/*05e0*/ FSEL R7, R10, R7, !P0 ; /* 0x000000070a077208 */
/* 0x000fe40004000000 */
/*05f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0600*/ @P1 BRA 0x4c0 ; /* 0xfffffeb000001947 */
/* 0x000fea000383ffff */
/*0610*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*0620*/ SHF.L.U32 R8, R4.reuse, 0x2, RZ ; /* 0x0000000204087819 */
/* 0x040fe400000006ff */
/*0630*/ SHF.L.U64.HI R3, R4, 0x2, R5 ; /* 0x0000000204037819 */
/* 0x000fe40000010205 */
/*0640*/ IADD3 R4, P0, R8.reuse, c[0x0][0x188], RZ ; /* 0x0000620008047a10 */
/* 0x040fe40007f1e0ff */
/*0650*/ IADD3 R6, P1, R8, c[0x0][0x190], RZ ; /* 0x0000640008067a10 */
/* 0x002fc40007f3e0ff */
/*0660*/ IADD3 R8, P2, R8, c[0x0][0x1a0], RZ ; /* 0x0000680008087a10 */
/* 0x000fe40007f5e0ff */
/*0670*/ IADD3.X R5, R3.reuse, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630003057a10 */
/* 0x040fe400007fe4ff */
/*0680*/ IADD3.X R7, R3.reuse, c[0x0][0x194], RZ, P1, !PT ; /* 0x0000650003077a10 */
/* 0x040fe40000ffe4ff */
/*0690*/ IADD3.X R9, R3, c[0x0][0x1a4], RZ, P2, !PT ; /* 0x0000690003097a10 */
/* 0x000fe200017fe4ff */
/*06a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*06b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R0 ; /* 0x000000000400798e */
/* 0x020fe8000c10e784 */
/*06c0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R2 ; /* 0x000000020600798e */
/* 0x000fe8000c10e784 */
/*06d0*/ RED.E.ADD.STRONG.GPU [R8.64], R3 ; /* 0x000000030800798e */
/* 0x000fe2000c10e184 */
/*06e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06f0*/ BRA 0x6f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <algorithm>
#include <cfloat>
#include <chrono>
#include <fstream>
#include <iostream>
#include <random>
#include <sstream>
#include <vector>
struct Data {
Data(int size) : size(size), bytes(size * sizeof(float)) {
cudaMalloc(&x, bytes);
cudaMalloc(&y, bytes);
}
Data(int size, std::vector<float>& h_x, std::vector<float>& h_y)
: size(size), bytes(size * sizeof(float)) {
cudaMalloc(&x, bytes);
cudaMalloc(&y, bytes);
cudaMemcpy(x, h_x.data(), bytes, cudaMemcpyHostToDevice);
cudaMemcpy(y, h_y.data(), bytes, cudaMemcpyHostToDevice);
}
~Data() {
cudaFree(x);
cudaFree(y);
}
void clear() {
cudaMemset(x, 0, bytes);
cudaMemset(y, 0, bytes);
}
float* x{nullptr};
float* y{nullptr};
int size{0};
int bytes{0};
};
__device__ float
squared_l2_distance(float x_1, float y_1, float x_2, float y_2) {
return (x_1 - x_2) * (x_1 - x_2) + (y_1 - y_2) * (y_1 - y_2);
}
__global__ void assign_clusters(const float* __restrict__ data_x,
const float* __restrict__ data_y,
int data_size,
const float* __restrict__ means_x,
const float* __restrict__ means_y,
float* __restrict__ new_sums_x,
float* __restrict__ new_sums_y,
int k,
int* __restrict__ counts) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= data_size) return;
// Make global loads once.
const float x = data_x[index];
const float y = data_y[index];
float best_distance = FLT_MAX;
int best_cluster = 0;
for (int cluster = 0; cluster < k; ++cluster) {
const float distance =
squared_l2_distance(x, y, means_x[cluster], means_y[cluster]);
if (distance < best_distance) {
best_distance = distance;
best_cluster = cluster;
}
}
atomicAdd(&new_sums_x[best_cluster], x);
atomicAdd(&new_sums_y[best_cluster], y);
atomicAdd(&counts[best_cluster], 1);
}
__global__ void compute_new_means(float* __restrict__ means_x,
float* __restrict__ means_y,
const float* __restrict__ new_sum_x,
const float* __restrict__ new_sum_y,
const int* __restrict__ counts) {
const int cluster = threadIdx.x;
const int count = max(1, counts[cluster]);
means_x[cluster] = new_sum_x[cluster] / count;
means_y[cluster] = new_sum_y[cluster] / count;
}
int main(int argc, const char* argv[]) {
if (argc < 4) {
std::cerr << "usage: assign_clusters <data-file> <k> [iterations]"
<< std::endl;
std::exit(EXIT_FAILURE);
}
const auto k = std::atoi(argv[3]);
std::cout<<argc<<std::endl;
const auto number_of_iterations = (argc == 4) ? std::atoi(argv[4]) : 300;
std::vector<float> h_x;
std::vector<float> h_y;
std::ifstream stream(argv[2]);
std::string line;
while (std::getline(stream, line)) {
std::istringstream line_stream(line);
float x, y;
uint16_t label;
line_stream >> x >> y >> label;
h_x.push_back(x);
h_y.push_back(y);
}
const size_t number_of_elements = h_x.size();
Data d_data(number_of_elements, h_x, h_y);
std::mt19937 rng(std::random_device{}());
std::shuffle(h_x.begin(), h_x.end(), rng);
std::shuffle(h_y.begin(), h_y.end(), rng);
Data d_means(k, h_x, h_y);
Data d_sums(k);
int* d_counts;
cudaMalloc(&d_counts, k * sizeof(int));
cudaMemset(d_counts, 0, k * sizeof(int));
const int threads = 1024;
const int blocks = (number_of_elements + threads - 1) / threads;
const auto start = std::chrono::high_resolution_clock::now();
for (size_t iteration = 0; iteration < number_of_iterations; ++iteration) {
cudaMemset(d_counts, 0, k * sizeof(int));
d_sums.clear();
assign_clusters<<<blocks, threads>>>(d_data.x,
d_data.y,
d_data.size,
d_means.x,
d_means.y,
d_sums.x,
d_sums.y,
k,
d_counts);
cudaDeviceSynchronize();
compute_new_means<<<1, k>>>(d_means.x,
d_means.y,
d_sums.x,
d_sums.y,
d_counts);
cudaDeviceSynchronize();
}
const auto end = std::chrono::high_resolution_clock::now();
const auto duration =
std::chrono::duration_cast<std::chrono::duration<float>>(end - start);
std::cerr << "Took: " << duration.count() << "s" << " " << std::endl;
cudaFree(d_counts);
std::vector<float> mean_x(k, 0);
std::vector<float> mean_y(k, 0);
cudaMemcpy(mean_x.data(), d_means.x, d_means.bytes, cudaMemcpyDeviceToHost);
cudaMemcpy(mean_y.data(), d_means.y, d_means.bytes, cudaMemcpyDeviceToHost);
for (size_t cluster = 0; cluster < k; ++cluster) {
std::cout << mean_x[cluster] << " " << mean_y[cluster] << std::endl;
}
} | #include <hip/hip_runtime.h>
#include <algorithm>
#include <cfloat>
#include <chrono>
#include <fstream>
#include <iostream>
#include <random>
#include <sstream>
#include <vector>
struct Data {
Data(int size) : size(size), bytes(size * sizeof(float)) {
hipMalloc(&x, bytes);
hipMalloc(&y, bytes);
}
Data(int size, std::vector<float>& h_x, std::vector<float>& h_y)
: size(size), bytes(size * sizeof(float)) {
hipMalloc(&x, bytes);
hipMalloc(&y, bytes);
hipMemcpy(x, h_x.data(), bytes, hipMemcpyHostToDevice);
hipMemcpy(y, h_y.data(), bytes, hipMemcpyHostToDevice);
}
~Data() {
hipFree(x);
hipFree(y);
}
void clear() {
hipMemset(x, 0, bytes);
hipMemset(y, 0, bytes);
}
float* x{nullptr};
float* y{nullptr};
int size{0};
int bytes{0};
};
__device__ float
squared_l2_distance(float x_1, float y_1, float x_2, float y_2) {
return (x_1 - x_2) * (x_1 - x_2) + (y_1 - y_2) * (y_1 - y_2);
}
__global__ void assign_clusters(const float* __restrict__ data_x,
const float* __restrict__ data_y,
int data_size,
const float* __restrict__ means_x,
const float* __restrict__ means_y,
float* __restrict__ new_sums_x,
float* __restrict__ new_sums_y,
int k,
int* __restrict__ counts) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= data_size) return;
// Make global loads once.
const float x = data_x[index];
const float y = data_y[index];
float best_distance = FLT_MAX;
int best_cluster = 0;
for (int cluster = 0; cluster < k; ++cluster) {
const float distance =
squared_l2_distance(x, y, means_x[cluster], means_y[cluster]);
if (distance < best_distance) {
best_distance = distance;
best_cluster = cluster;
}
}
atomicAdd(&new_sums_x[best_cluster], x);
atomicAdd(&new_sums_y[best_cluster], y);
atomicAdd(&counts[best_cluster], 1);
}
__global__ void compute_new_means(float* __restrict__ means_x,
float* __restrict__ means_y,
const float* __restrict__ new_sum_x,
const float* __restrict__ new_sum_y,
const int* __restrict__ counts) {
const int cluster = threadIdx.x;
const int count = max(1, counts[cluster]);
means_x[cluster] = new_sum_x[cluster] / count;
means_y[cluster] = new_sum_y[cluster] / count;
}
int main(int argc, const char* argv[]) {
if (argc < 4) {
std::cerr << "usage: assign_clusters <data-file> <k> [iterations]"
<< std::endl;
std::exit(EXIT_FAILURE);
}
const auto k = std::atoi(argv[3]);
std::cout<<argc<<std::endl;
const auto number_of_iterations = (argc == 4) ? std::atoi(argv[4]) : 300;
std::vector<float> h_x;
std::vector<float> h_y;
std::ifstream stream(argv[2]);
std::string line;
while (std::getline(stream, line)) {
std::istringstream line_stream(line);
float x, y;
uint16_t label;
line_stream >> x >> y >> label;
h_x.push_back(x);
h_y.push_back(y);
}
const size_t number_of_elements = h_x.size();
Data d_data(number_of_elements, h_x, h_y);
std::mt19937 rng(std::random_device{}());
std::shuffle(h_x.begin(), h_x.end(), rng);
std::shuffle(h_y.begin(), h_y.end(), rng);
Data d_means(k, h_x, h_y);
Data d_sums(k);
int* d_counts;
hipMalloc(&d_counts, k * sizeof(int));
hipMemset(d_counts, 0, k * sizeof(int));
const int threads = 1024;
const int blocks = (number_of_elements + threads - 1) / threads;
const auto start = std::chrono::high_resolution_clock::now();
for (size_t iteration = 0; iteration < number_of_iterations; ++iteration) {
hipMemset(d_counts, 0, k * sizeof(int));
d_sums.clear();
assign_clusters<<<blocks, threads>>>(d_data.x,
d_data.y,
d_data.size,
d_means.x,
d_means.y,
d_sums.x,
d_sums.y,
k,
d_counts);
hipDeviceSynchronize();
compute_new_means<<<1, k>>>(d_means.x,
d_means.y,
d_sums.x,
d_sums.y,
d_counts);
hipDeviceSynchronize();
}
const auto end = std::chrono::high_resolution_clock::now();
const auto duration =
std::chrono::duration_cast<std::chrono::duration<float>>(end - start);
std::cerr << "Took: " << duration.count() << "s" << " " << std::endl;
hipFree(d_counts);
std::vector<float> mean_x(k, 0);
std::vector<float> mean_y(k, 0);
hipMemcpy(mean_x.data(), d_means.x, d_means.bytes, hipMemcpyDeviceToHost);
hipMemcpy(mean_y.data(), d_means.y, d_means.bytes, hipMemcpyDeviceToHost);
for (size_t cluster = 0; cluster < k; ++cluster) {
std::cout << mean_x[cluster] << " " << mean_y[cluster] << std::endl;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <algorithm>
#include <cfloat>
#include <chrono>
#include <fstream>
#include <iostream>
#include <random>
#include <sstream>
#include <vector>
struct Data {
Data(int size) : size(size), bytes(size * sizeof(float)) {
hipMalloc(&x, bytes);
hipMalloc(&y, bytes);
}
Data(int size, std::vector<float>& h_x, std::vector<float>& h_y)
: size(size), bytes(size * sizeof(float)) {
hipMalloc(&x, bytes);
hipMalloc(&y, bytes);
hipMemcpy(x, h_x.data(), bytes, hipMemcpyHostToDevice);
hipMemcpy(y, h_y.data(), bytes, hipMemcpyHostToDevice);
}
~Data() {
hipFree(x);
hipFree(y);
}
void clear() {
hipMemset(x, 0, bytes);
hipMemset(y, 0, bytes);
}
float* x{nullptr};
float* y{nullptr};
int size{0};
int bytes{0};
};
__device__ float
squared_l2_distance(float x_1, float y_1, float x_2, float y_2) {
return (x_1 - x_2) * (x_1 - x_2) + (y_1 - y_2) * (y_1 - y_2);
}
__global__ void assign_clusters(const float* __restrict__ data_x,
const float* __restrict__ data_y,
int data_size,
const float* __restrict__ means_x,
const float* __restrict__ means_y,
float* __restrict__ new_sums_x,
float* __restrict__ new_sums_y,
int k,
int* __restrict__ counts) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= data_size) return;
// Make global loads once.
const float x = data_x[index];
const float y = data_y[index];
float best_distance = FLT_MAX;
int best_cluster = 0;
for (int cluster = 0; cluster < k; ++cluster) {
const float distance =
squared_l2_distance(x, y, means_x[cluster], means_y[cluster]);
if (distance < best_distance) {
best_distance = distance;
best_cluster = cluster;
}
}
atomicAdd(&new_sums_x[best_cluster], x);
atomicAdd(&new_sums_y[best_cluster], y);
atomicAdd(&counts[best_cluster], 1);
}
__global__ void compute_new_means(float* __restrict__ means_x,
float* __restrict__ means_y,
const float* __restrict__ new_sum_x,
const float* __restrict__ new_sum_y,
const int* __restrict__ counts) {
const int cluster = threadIdx.x;
const int count = max(1, counts[cluster]);
means_x[cluster] = new_sum_x[cluster] / count;
means_y[cluster] = new_sum_y[cluster] / count;
}
int main(int argc, const char* argv[]) {
if (argc < 4) {
std::cerr << "usage: assign_clusters <data-file> <k> [iterations]"
<< std::endl;
std::exit(EXIT_FAILURE);
}
const auto k = std::atoi(argv[3]);
std::cout<<argc<<std::endl;
const auto number_of_iterations = (argc == 4) ? std::atoi(argv[4]) : 300;
std::vector<float> h_x;
std::vector<float> h_y;
std::ifstream stream(argv[2]);
std::string line;
while (std::getline(stream, line)) {
std::istringstream line_stream(line);
float x, y;
uint16_t label;
line_stream >> x >> y >> label;
h_x.push_back(x);
h_y.push_back(y);
}
const size_t number_of_elements = h_x.size();
Data d_data(number_of_elements, h_x, h_y);
std::mt19937 rng(std::random_device{}());
std::shuffle(h_x.begin(), h_x.end(), rng);
std::shuffle(h_y.begin(), h_y.end(), rng);
Data d_means(k, h_x, h_y);
Data d_sums(k);
int* d_counts;
hipMalloc(&d_counts, k * sizeof(int));
hipMemset(d_counts, 0, k * sizeof(int));
const int threads = 1024;
const int blocks = (number_of_elements + threads - 1) / threads;
const auto start = std::chrono::high_resolution_clock::now();
for (size_t iteration = 0; iteration < number_of_iterations; ++iteration) {
hipMemset(d_counts, 0, k * sizeof(int));
d_sums.clear();
assign_clusters<<<blocks, threads>>>(d_data.x,
d_data.y,
d_data.size,
d_means.x,
d_means.y,
d_sums.x,
d_sums.y,
k,
d_counts);
hipDeviceSynchronize();
compute_new_means<<<1, k>>>(d_means.x,
d_means.y,
d_sums.x,
d_sums.y,
d_counts);
hipDeviceSynchronize();
}
const auto end = std::chrono::high_resolution_clock::now();
const auto duration =
std::chrono::duration_cast<std::chrono::duration<float>>(end - start);
std::cerr << "Took: " << duration.count() << "s" << " " << std::endl;
hipFree(d_counts);
std::vector<float> mean_x(k, 0);
std::vector<float> mean_y(k, 0);
hipMemcpy(mean_x.data(), d_means.x, d_means.bytes, hipMemcpyDeviceToHost);
hipMemcpy(mean_y.data(), d_means.y, d_means.bytes, hipMemcpyDeviceToHost);
for (size_t cluster = 0; cluster < k; ++cluster) {
std::cout << mean_x[cluster] << " " << mean_y[cluster] << std::endl;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi
.globl _Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi
.p2align 8
.type _Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi,@function
_Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x28
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
global_load_b32 v7, v[2:3], off
global_load_b32 v6, v[0:1], off
s_clause 0x1
s_load_b32 s10, s[0:1], 0x38
s_load_b64 s[8:9], s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[0:3], s[0:1], 0x18
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7f7fffff
s_mov_b32 s11, 0
.p2align 6
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s12, s[2:3], 0x0
s_load_b32 s13, s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_subrev_f32 v2, s12, v6 :: v_dual_subrev_f32 v3, s13, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
v_fmac_f32_e32 v2, v3, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v2, v1
v_cndmask_b32_e64 v0, v0, s11, vcc_lo
s_add_i32 s11, s11, 1
s_add_u32 s0, s0, 4
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_addc_u32 s1, s1, 0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s10, s11
s_cbranch_scc0 .LBB0_3
v_ashrrev_i32_e32 v1, 31, v0
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_mov_b32 s0, 0
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v5, v[2:3], off
.LBB0_7:
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v7
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v5, v[2:3], off
.LBB0_9:
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v6
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_9
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi, .Lfunc_end0-_Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17compute_new_meansPfS_PKfS1_PKi
.globl _Z17compute_new_meansPfS_PKfS1_PKi
.p2align 8
.type _Z17compute_new_meansPfS_PKfS1_PKi,@function
_Z17compute_new_meansPfS_PKfS1_PKi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[8:9]
global_load_b32 v3, v0, s[10:11]
s_waitcnt vmcnt(2)
v_max_i32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
s_waitcnt vmcnt(1)
v_div_scale_f32 v4, null, v1, v1, v2
s_waitcnt vmcnt(0)
v_div_scale_f32 v5, null, v1, v1, v3
v_div_scale_f32 v10, vcc_lo, v2, v1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v7, v9, v7 :: v_dual_fmac_f32 v6, v8, v6
v_div_scale_f32 v8, s0, v3, v1, v3
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, -v5, v11, v8
v_fmac_f32_e32 v11, v13, v7
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v11, v8
v_fma_f32 v12, -v4, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v12, v6
v_fma_f32 v4, -v4, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v5, v5, v7, v11
v_div_fixup_f32 v2, v4, v1, v2
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v1, v5, v1, v3
s_clause 0x1
global_store_b32 v0, v2, s[4:5]
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17compute_new_meansPfS_PKfS1_PKi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17compute_new_meansPfS_PKfS1_PKi, .Lfunc_end1-_Z17compute_new_meansPfS_PKfS1_PKi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15assign_clustersPKfS0_iS0_S0_PfS1_iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .actual_access: write_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17compute_new_meansPfS_PKfS1_PKi
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z17compute_new_meansPfS_PKfS1_PKi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "array.cuh"
double * malloc_2d(int num_cols, int num_rows) {
int size = num_cols * num_rows;
double * data;
cudaMallocManaged(&data, size * sizeof(double));
return data;
}
double * calloc_2d(int num_cols, int num_rows) {
int size = num_cols * num_rows;
double * data;
cudaMallocManaged(&data, size * sizeof(double));
for (int iter = 0; iter < num_rows * num_cols; iter++) {
data[iter] = 0.0;
}
return data;
}
void free_2d(double * data) {
cudaFree(data);
}
__global__ void large_matrix_multiply_kernel(double *x, double *y, double *z, int num_cols, int num_rows, bool is_sigma) {
int row = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0;
if (row < num_rows) {
for (int col = 0; col < num_cols-1; col++) {
sum += x[row * num_cols + col] * y[col];
}
sum += x[row * (num_cols - 1)];
z[row] = sum;
if (is_sigma)
z[row] = z[row] / 3;
}
}
__global__ void matrix_multiply_kernel(double *x, double *y, double *z, int num_cols) {
int row = blockIdx.x;
int index = threadIdx.x;
int stride = blockDim.x;
double sum = 0;
for (int cord = index; cord < num_cols - 1; cord += stride) {
sum += x[row * num_cols + cord] * y[cord];
}
z[row * 32 + index] = sum;
}
void matrix_m(double * M1, double * M2, double * M3, double *Buffer, int num_cols, int num_rows, double(*modifier)(double)) {
/*large_matrix_multiply_kernel << < num_rows / 32 + 1, 32 >> > (M1, M2, M3, num_cols, num_rows, false);
cudaDeviceSynchronize();*/
if (num_rows >= num_cols) {
large_matrix_multiply_kernel << < num_rows / 32 + 1, 32 >> > (M1, M2, M3, num_cols, num_rows, false);
cudaDeviceSynchronize();
} else {
matrix_multiply_kernel << < num_rows, 32 >> > (M1, M2, Buffer, num_cols);
cudaDeviceSynchronize();
for (int row = 0; row < num_rows; row++) {
double sum = 0.0;
for (int thr = 0; thr < 32; thr++) {
sum += Buffer[row * 32 + thr];
}
sum += M1[row * num_cols + num_cols - 1];
M3[row] = modifier(sum);
}
}
}
double ** _malloc_2d(int num_cols, int num_rows) {
double ** res = (double **)malloc(num_rows * sizeof(double *));
for (int iter = 0; iter < num_rows; iter++) {
res[iter] = (double *)calloc(num_cols, sizeof(double));
}
return res;
}
void _zerro_2d(double ** res, int num_cols, int num_rows) {
for (int iter = 0; iter < num_rows; iter++) {
memset(res[iter], 0.0, num_cols * sizeof(double));
}
} | .file "tmpxft_00003535_00000000-6_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9malloc_2dii
.type _Z9malloc_2dii, @function
_Z9malloc_2dii:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
imull %esi, %edi
movslq %edi, %rsi
salq $3, %rsi
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9malloc_2dii, .-_Z9malloc_2dii
.globl _Z9calloc_2dii
.type _Z9calloc_2dii, @function
_Z9calloc_2dii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
imull %esi, %edi
movl %edi, %ebp
movslq %edi, %rbx
salq $3, %rbx
movq %rsp, %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
testl %ebp, %ebp
jle .L8
movl $0, %eax
.L9:
movq (%rsp), %rdx
movq $0x000000000, (%rdx,%rax)
addq $8, %rax
cmpq %rax, %rbx
jne .L9
.L8:
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L13
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9calloc_2dii, .-_Z9calloc_2dii
.globl _Z7free_2dPd
.type _Z7free_2dPd, @function
_Z7free_2dPd:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7free_2dPd, .-_Z7free_2dPd
.globl _Z10_malloc_2dii
.type _Z10_malloc_2dii, @function
_Z10_malloc_2dii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r12d
movl %esi, %ebx
movslq %esi, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L16
movq %rax, %rbx
addq %rax, %rbp
movslq %r12d, %r12
.L18:
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L18
.L16:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z10_malloc_2dii, .-_Z10_malloc_2dii
.globl _Z9_zerro_2dPPdii
.type _Z9_zerro_2dPPdii, @function
_Z9_zerro_2dPPdii:
.LFB2062:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L26
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movslq %esi, %rsi
leaq 0(,%rsi,8), %rbp
movq %rdi, %rbx
movslq %edx, %rdx
leaq (%rdi,%rdx,8), %r12
.L23:
movq (%rbx), %rdi
movq %rbp, %rdx
movl $0, %esi
call memset@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L23
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2062:
.size _Z9_zerro_2dPPdii, .-_Z9_zerro_2dPPdii
.globl _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib
.type _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib, @function
_Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movb %r9b, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28large_matrix_multiply_kernelPdS_S_iib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib, .-_Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib
.globl _Z28large_matrix_multiply_kernelPdS_S_iib
.type _Z28large_matrix_multiply_kernelPdS_S_iib, @function
_Z28large_matrix_multiply_kernelPdS_S_iib:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r9b, %r9d
call _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z28large_matrix_multiply_kernelPdS_S_iib, .-_Z28large_matrix_multiply_kernelPdS_S_iib
.globl _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i
.type _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i, @function
_Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22matrix_multiply_kernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i, .-_Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i
.globl _Z22matrix_multiply_kernelPdS_S_i
.type _Z22matrix_multiply_kernelPdS_S_i, @function
_Z22matrix_multiply_kernelPdS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z22matrix_multiply_kernelPdS_S_i, .-_Z22matrix_multiply_kernelPdS_S_i
.globl _Z8matrix_mPdS_S_S_iiPFddE
.type _Z8matrix_mPdS_S_S_iiPFddE, @function
_Z8matrix_mPdS_S_S_iiPFddE:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r14
movq %rdx, %r15
movl %r8d, %ebp
movl %r9d, %r13d
cmpl %r8d, %r9d
jl .L46
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leal 31(%r9), %eax
testl %r9d, %r9d
cmovns %r9d, %eax
sarl $5, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L47:
call cudaDeviceSynchronize@PLT
.L45:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl $0, %r9d
movl %r13d, %r8d
movl %ebp, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib
jmp .L47
.L46:
movq %rcx, %rbx
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %r9d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L49:
call cudaDeviceSynchronize@PLT
testl %r13d, %r13d
jle .L45
movslq %ebp, %rbp
leaq 0(,%rbp,8), %r14
addq %r14, %r12
addq $256, %rbx
movslq %r13d, %r13
movl $0, %ebp
.L50:
leaq -256(%rbx), %rax
pxor %xmm0, %xmm0
.L51:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rbx, %rax
jne .L51
addsd -8(%r12), %xmm0
call *96(%rsp)
movsd %xmm0, (%r15,%rbp,8)
addq $1, %rbp
addq %r14, %r12
addq $256, %rbx
cmpq %r13, %rbp
jne .L50
jmp .L45
.L55:
movl %ebp, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i
jmp .L49
.cfi_endproc
.LFE2060:
.size _Z8matrix_mPdS_S_S_iiPFddE, .-_Z8matrix_mPdS_S_S_iiPFddE
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z22matrix_multiply_kernelPdS_S_i"
.align 8
.LC2:
.string "_Z28large_matrix_multiply_kernelPdS_S_iib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22matrix_multiply_kernelPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z28large_matrix_multiply_kernelPdS_S_iib(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "array.cuh"
double * malloc_2d(int num_cols, int num_rows) {
int size = num_cols * num_rows;
double * data;
cudaMallocManaged(&data, size * sizeof(double));
return data;
}
double * calloc_2d(int num_cols, int num_rows) {
int size = num_cols * num_rows;
double * data;
cudaMallocManaged(&data, size * sizeof(double));
for (int iter = 0; iter < num_rows * num_cols; iter++) {
data[iter] = 0.0;
}
return data;
}
void free_2d(double * data) {
cudaFree(data);
}
__global__ void large_matrix_multiply_kernel(double *x, double *y, double *z, int num_cols, int num_rows, bool is_sigma) {
int row = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0;
if (row < num_rows) {
for (int col = 0; col < num_cols-1; col++) {
sum += x[row * num_cols + col] * y[col];
}
sum += x[row * (num_cols - 1)];
z[row] = sum;
if (is_sigma)
z[row] = z[row] / 3;
}
}
__global__ void matrix_multiply_kernel(double *x, double *y, double *z, int num_cols) {
int row = blockIdx.x;
int index = threadIdx.x;
int stride = blockDim.x;
double sum = 0;
for (int cord = index; cord < num_cols - 1; cord += stride) {
sum += x[row * num_cols + cord] * y[cord];
}
z[row * 32 + index] = sum;
}
void matrix_m(double * M1, double * M2, double * M3, double *Buffer, int num_cols, int num_rows, double(*modifier)(double)) {
/*large_matrix_multiply_kernel << < num_rows / 32 + 1, 32 >> > (M1, M2, M3, num_cols, num_rows, false);
cudaDeviceSynchronize();*/
if (num_rows >= num_cols) {
large_matrix_multiply_kernel << < num_rows / 32 + 1, 32 >> > (M1, M2, M3, num_cols, num_rows, false);
cudaDeviceSynchronize();
} else {
matrix_multiply_kernel << < num_rows, 32 >> > (M1, M2, Buffer, num_cols);
cudaDeviceSynchronize();
for (int row = 0; row < num_rows; row++) {
double sum = 0.0;
for (int thr = 0; thr < 32; thr++) {
sum += Buffer[row * 32 + thr];
}
sum += M1[row * num_cols + num_cols - 1];
M3[row] = modifier(sum);
}
}
}
double ** _malloc_2d(int num_cols, int num_rows) {
double ** res = (double **)malloc(num_rows * sizeof(double *));
for (int iter = 0; iter < num_rows; iter++) {
res[iter] = (double *)calloc(num_cols, sizeof(double));
}
return res;
}
void _zerro_2d(double ** res, int num_cols, int num_rows) {
for (int iter = 0; iter < num_rows; iter++) {
memset(res[iter], 0.0, num_cols * sizeof(double));
}
} | #pragma once
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
double * malloc_2d(int, int);
double * calloc_2d(int, int);
void free_2d(double *);
void matrix_m(double *, double *, double *, double *, int, int, double(*)(double));
double ** _malloc_2d(int, int);
void _zerro_2d(double **, int, int); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
double * malloc_2d(int, int);
double * calloc_2d(int, int);
void free_2d(double *);
void matrix_m(double *, double *, double *, double *, int, int, double(*)(double));
double ** _malloc_2d(int, int);
void _zerro_2d(double **, int, int); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <string.h>
double * malloc_2d(int, int);
double * calloc_2d(int, int);
void free_2d(double *);
void matrix_m(double *, double *, double *, double *, int, int, double(*)(double));
double ** _malloc_2d(int, int);
void _zerro_2d(double **, int, int); | .text
.file "array.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00003535_00000000-6_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9malloc_2dii
.type _Z9malloc_2dii, @function
_Z9malloc_2dii:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
imull %esi, %edi
movslq %edi, %rsi
salq $3, %rsi
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9malloc_2dii, .-_Z9malloc_2dii
.globl _Z9calloc_2dii
.type _Z9calloc_2dii, @function
_Z9calloc_2dii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
imull %esi, %edi
movl %edi, %ebp
movslq %edi, %rbx
salq $3, %rbx
movq %rsp, %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
testl %ebp, %ebp
jle .L8
movl $0, %eax
.L9:
movq (%rsp), %rdx
movq $0x000000000, (%rdx,%rax)
addq $8, %rax
cmpq %rax, %rbx
jne .L9
.L8:
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L13
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9calloc_2dii, .-_Z9calloc_2dii
.globl _Z7free_2dPd
.type _Z7free_2dPd, @function
_Z7free_2dPd:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7free_2dPd, .-_Z7free_2dPd
.globl _Z10_malloc_2dii
.type _Z10_malloc_2dii, @function
_Z10_malloc_2dii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r12d
movl %esi, %ebx
movslq %esi, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L16
movq %rax, %rbx
addq %rax, %rbp
movslq %r12d, %r12
.L18:
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L18
.L16:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z10_malloc_2dii, .-_Z10_malloc_2dii
.globl _Z9_zerro_2dPPdii
.type _Z9_zerro_2dPPdii, @function
_Z9_zerro_2dPPdii:
.LFB2062:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L26
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movslq %esi, %rsi
leaq 0(,%rsi,8), %rbp
movq %rdi, %rbx
movslq %edx, %rdx
leaq (%rdi,%rdx,8), %r12
.L23:
movq (%rbx), %rdi
movq %rbp, %rdx
movl $0, %esi
call memset@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L23
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2062:
.size _Z9_zerro_2dPPdii, .-_Z9_zerro_2dPPdii
.globl _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib
.type _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib, @function
_Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movb %r9b, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28large_matrix_multiply_kernelPdS_S_iib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib, .-_Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib
.globl _Z28large_matrix_multiply_kernelPdS_S_iib
.type _Z28large_matrix_multiply_kernelPdS_S_iib, @function
_Z28large_matrix_multiply_kernelPdS_S_iib:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r9b, %r9d
call _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z28large_matrix_multiply_kernelPdS_S_iib, .-_Z28large_matrix_multiply_kernelPdS_S_iib
.globl _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i
.type _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i, @function
_Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22matrix_multiply_kernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i, .-_Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i
.globl _Z22matrix_multiply_kernelPdS_S_i
.type _Z22matrix_multiply_kernelPdS_S_i, @function
_Z22matrix_multiply_kernelPdS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z22matrix_multiply_kernelPdS_S_i, .-_Z22matrix_multiply_kernelPdS_S_i
.globl _Z8matrix_mPdS_S_S_iiPFddE
.type _Z8matrix_mPdS_S_S_iiPFddE, @function
_Z8matrix_mPdS_S_S_iiPFddE:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r14
movq %rdx, %r15
movl %r8d, %ebp
movl %r9d, %r13d
cmpl %r8d, %r9d
jl .L46
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leal 31(%r9), %eax
testl %r9d, %r9d
cmovns %r9d, %eax
sarl $5, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L47:
call cudaDeviceSynchronize@PLT
.L45:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl $0, %r9d
movl %r13d, %r8d
movl %ebp, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z55__device_stub__Z28large_matrix_multiply_kernelPdS_S_iibPdS_S_iib
jmp .L47
.L46:
movq %rcx, %rbx
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %r9d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L49:
call cudaDeviceSynchronize@PLT
testl %r13d, %r13d
jle .L45
movslq %ebp, %rbp
leaq 0(,%rbp,8), %r14
addq %r14, %r12
addq $256, %rbx
movslq %r13d, %r13
movl $0, %ebp
.L50:
leaq -256(%rbx), %rax
pxor %xmm0, %xmm0
.L51:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rbx, %rax
jne .L51
addsd -8(%r12), %xmm0
call *96(%rsp)
movsd %xmm0, (%r15,%rbp,8)
addq $1, %rbp
addq %r14, %r12
addq $256, %rbx
cmpq %r13, %rbp
jne .L50
jmp .L45
.L55:
movl %ebp, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_iPdS_S_i
jmp .L49
.cfi_endproc
.LFE2060:
.size _Z8matrix_mPdS_S_S_iiPFddE, .-_Z8matrix_mPdS_S_S_iiPFddE
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z22matrix_multiply_kernelPdS_S_i"
.align 8
.LC2:
.string "_Z28large_matrix_multiply_kernelPdS_S_iib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22matrix_multiply_kernelPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z28large_matrix_multiply_kernelPdS_S_iib(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "array.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 20
#define BLOCK_DIM 20
double mat_a[N][N]; //matriz A
double mat_b[N][N]; //matrz B
double mat_result[N][N]; //matriz C
//Contadores de los loops for
int i,j,m;
//Flag para imprimir los resultados
int flag;
__global__ void multiplica(double *A, double *B, double *C, int dim) {
//índices de los hilos
int columna = threadIdx.x + blockDim.x * blockIdx.x;
int renglon = threadIdx.y + blockDim.y * blockIdx.y;
//multiplicación
int k;
double suma = 0;
if(columna < dim && renglon < dim){
for(k = 0; k< dim; k++)
suma = suma + A[renglon*dim + k]*B[k*dim + columna];
C[renglon*dim + columna] = suma;
}
}
void inicializa_matrices();
void imprime_matrices();
int main(int argc, char *argv[]){
//Inicializa matrices A y B
inicializa_matrices();
//Se imprimen resultados?
flag = atoi(argv[1]);
//Variables utilizadas por el device
int size = N*N*sizeof(double);
double *pA, *pB, *pC;
//Memory allocation en el device
cudaMalloc((void**)&pA, size);
cudaMalloc((void**)&pB, size);
cudaMalloc((void**)&pC, size);
//Se copian las matrices del host al device
cudaMemcpy(pA, mat_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(pB, mat_b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(N,N);
dim3 dimGrid(1,1);
multiplica<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
cudaMemcpy(mat_result, pC, size, cudaMemcpyDeviceToHost);
if (flag !=0){
imprime_matrices();
}
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
return 0;
}
void inicializa_matrices()
{
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_a[i][j] = i + j;
}
}
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_b[i][j] = i*j;
}
}
}
void imprime_matrices()
{ printf("Matriz A \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_a[i][j]);
}
printf("\n\n\n");
printf("Matriz B \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_b[i][j]);
}
printf("\n\n\n");
printf("Matriz C = A * B\n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_result[i][j]);
}
printf("\n\n");
} | code for sm_80
Function : _Z10multiplicaPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 20
#define BLOCK_DIM 20
double mat_a[N][N]; //matriz A
double mat_b[N][N]; //matrz B
double mat_result[N][N]; //matriz C
//Contadores de los loops for
int i,j,m;
//Flag para imprimir los resultados
int flag;
__global__ void multiplica(double *A, double *B, double *C, int dim) {
//índices de los hilos
int columna = threadIdx.x + blockDim.x * blockIdx.x;
int renglon = threadIdx.y + blockDim.y * blockIdx.y;
//multiplicación
int k;
double suma = 0;
if(columna < dim && renglon < dim){
for(k = 0; k< dim; k++)
suma = suma + A[renglon*dim + k]*B[k*dim + columna];
C[renglon*dim + columna] = suma;
}
}
void inicializa_matrices();
void imprime_matrices();
int main(int argc, char *argv[]){
//Inicializa matrices A y B
inicializa_matrices();
//Se imprimen resultados?
flag = atoi(argv[1]);
//Variables utilizadas por el device
int size = N*N*sizeof(double);
double *pA, *pB, *pC;
//Memory allocation en el device
cudaMalloc((void**)&pA, size);
cudaMalloc((void**)&pB, size);
cudaMalloc((void**)&pC, size);
//Se copian las matrices del host al device
cudaMemcpy(pA, mat_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(pB, mat_b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(N,N);
dim3 dimGrid(1,1);
multiplica<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
cudaMemcpy(mat_result, pC, size, cudaMemcpyDeviceToHost);
if (flag !=0){
imprime_matrices();
}
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
return 0;
}
void inicializa_matrices()
{
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_a[i][j] = i + j;
}
}
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_b[i][j] = i*j;
}
}
}
void imprime_matrices()
{ printf("Matriz A \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_a[i][j]);
}
printf("\n\n\n");
printf("Matriz B \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_b[i][j]);
}
printf("\n\n\n");
printf("Matriz C = A * B\n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_result[i][j]);
}
printf("\n\n");
} | .file "tmpxft_0018d5f8_00000000-6_mat_mult_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19inicializa_matricesv
.type _Z19inicializa_matricesv, @function
_Z19inicializa_matricesv:
.LFB2058:
.cfi_startproc
endbr64
leaq mat_a(%rip), %rsi
movl $20, %ecx
.L5:
leal -20(%rcx), %eax
movq %rsi, %rdx
.L4:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rdx)
addl $1, %eax
addq $8, %rdx
cmpl %ecx, %eax
jne .L4
addq $160, %rsi
addl $1, %ecx
cmpl $40, %ecx
jne .L5
leaq 160+mat_b(%rip), %rcx
movl $0, %edi
.L7:
movl %edi, %esi
leaq -160(%rcx), %rax
movl $0, %edx
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, (%rax)
addl %esi, %edx
addq $8, %rax
cmpq %rcx, %rax
jne .L6
addq $1, %rdi
addq $160, %rcx
cmpq $20, %rdi
jne .L7
movl $20, j(%rip)
movl $20, i(%rip)
ret
.cfi_endproc
.LFE2058:
.size _Z19inicializa_matricesv, .-_Z19inicializa_matricesv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matriz A \n"
.LC1:
.string "\n"
.LC2:
.string "%8.2f "
.LC3:
.string "\n\n\n"
.LC4:
.string "Matriz B \n"
.LC5:
.string "Matriz C = A * B\n"
.LC6:
.string "\n\n"
.text
.globl _Z16imprime_matricesv
.type _Z16imprime_matricesv, @function
_Z16imprime_matricesv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, i(%rip)
leaq .LC1(%rip), %r12
leaq mat_a(%rip), %rbp
leaq .LC2(%rip), %rbx
.L14:
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, j(%rip)
movl $0, %eax
.L13:
cltq
movslq i(%rip), %rdx
leaq (%rdx,%rdx,4), %rdx
leaq (%rax,%rdx,4), %rax
movsd 0(%rbp,%rax,8), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl j(%rip), %eax
addl $1, %eax
movl %eax, j(%rip)
cmpl $19, %eax
jle .L13
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
cmpl $19, %eax
jle .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, i(%rip)
leaq .LC1(%rip), %r12
leaq mat_b(%rip), %rbp
leaq .LC2(%rip), %rbx
.L16:
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, j(%rip)
movl $0, %eax
.L15:
cltq
movslq i(%rip), %rdx
leaq (%rdx,%rdx,4), %rdx
leaq (%rax,%rdx,4), %rax
movsd 0(%rbp,%rax,8), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl j(%rip), %eax
addl $1, %eax
movl %eax, j(%rip)
cmpl $19, %eax
jle .L15
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
cmpl $19, %eax
jle .L16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, i(%rip)
leaq .LC1(%rip), %r12
leaq mat_result(%rip), %rbp
leaq .LC2(%rip), %rbx
.L18:
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, j(%rip)
movl $0, %eax
.L17:
cltq
movslq i(%rip), %rdx
leaq (%rdx,%rdx,4), %rdx
leaq (%rax,%rdx,4), %rax
movsd 0(%rbp,%rax,8), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl j(%rip), %eax
addl $1, %eax
movl %eax, j(%rip)
cmpl $19, %eax
jle .L17
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
cmpl $19, %eax
jle .L18
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z16imprime_matricesv, .-_Z16imprime_matricesv
.globl _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i
.type _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i, @function
_Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10multiplicaPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i, .-_Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i
.globl _Z10multiplicaPdS_S_i
.type _Z10multiplicaPdS_S_i, @function
_Z10multiplicaPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10multiplicaPdS_S_i, .-_Z10multiplicaPdS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Z19inicializa_matricesv
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, flag(%rip)
leaq 8(%rsp), %rdi
movl $3200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $3200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $3200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $3200, %edx
leaq mat_a(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $3200, %edx
leaq mat_b(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $20, 32(%rsp)
movl $20, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movl $2, %ecx
movl $3200, %edx
movq 24(%rsp), %rsi
leaq mat_result(%rip), %rdi
call cudaMemcpy@PLT
cmpl $0, flag(%rip)
jne .L40
.L36:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $20, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i
jmp .L35
.L40:
call _Z16imprime_matricesv
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10multiplicaPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10multiplicaPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl flag
.bss
.align 4
.type flag, @object
.size flag, 4
flag:
.zero 4
.globl m
.align 4
.type m, @object
.size m, 4
m:
.zero 4
.globl j
.align 4
.type j, @object
.size j, 4
j:
.zero 4
.globl i
.align 4
.type i, @object
.size i, 4
i:
.zero 4
.globl mat_result
.align 32
.type mat_result, @object
.size mat_result, 3200
mat_result:
.zero 3200
.globl mat_b
.align 32
.type mat_b, @object
.size mat_b, 3200
mat_b:
.zero 3200
.globl mat_a
.align 32
.type mat_a, @object
.size mat_a, 3200
mat_a:
.zero 3200
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 20
#define BLOCK_DIM 20
double mat_a[N][N]; //matriz A
double mat_b[N][N]; //matrz B
double mat_result[N][N]; //matriz C
//Contadores de los loops for
int i,j,m;
//Flag para imprimir los resultados
int flag;
__global__ void multiplica(double *A, double *B, double *C, int dim) {
//índices de los hilos
int columna = threadIdx.x + blockDim.x * blockIdx.x;
int renglon = threadIdx.y + blockDim.y * blockIdx.y;
//multiplicación
int k;
double suma = 0;
if(columna < dim && renglon < dim){
for(k = 0; k< dim; k++)
suma = suma + A[renglon*dim + k]*B[k*dim + columna];
C[renglon*dim + columna] = suma;
}
}
void inicializa_matrices();
void imprime_matrices();
int main(int argc, char *argv[]){
//Inicializa matrices A y B
inicializa_matrices();
//Se imprimen resultados?
flag = atoi(argv[1]);
//Variables utilizadas por el device
int size = N*N*sizeof(double);
double *pA, *pB, *pC;
//Memory allocation en el device
cudaMalloc((void**)&pA, size);
cudaMalloc((void**)&pB, size);
cudaMalloc((void**)&pC, size);
//Se copian las matrices del host al device
cudaMemcpy(pA, mat_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(pB, mat_b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(N,N);
dim3 dimGrid(1,1);
multiplica<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
cudaMemcpy(mat_result, pC, size, cudaMemcpyDeviceToHost);
if (flag !=0){
imprime_matrices();
}
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
return 0;
}
void inicializa_matrices()
{
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_a[i][j] = i + j;
}
}
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_b[i][j] = i*j;
}
}
}
void imprime_matrices()
{ printf("Matriz A \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_a[i][j]);
}
printf("\n\n\n");
printf("Matriz B \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_b[i][j]);
}
printf("\n\n\n");
printf("Matriz C = A * B\n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_result[i][j]);
}
printf("\n\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 20
#define BLOCK_DIM 20
double mat_a[N][N]; //matriz A
double mat_b[N][N]; //matrz B
double mat_result[N][N]; //matriz C
//Contadores de los loops for
int i,j,m;
//Flag para imprimir los resultados
int flag;
__global__ void multiplica(double *A, double *B, double *C, int dim) {
//índices de los hilos
int columna = threadIdx.x + blockDim.x * blockIdx.x;
int renglon = threadIdx.y + blockDim.y * blockIdx.y;
//multiplicación
int k;
double suma = 0;
if(columna < dim && renglon < dim){
for(k = 0; k< dim; k++)
suma = suma + A[renglon*dim + k]*B[k*dim + columna];
C[renglon*dim + columna] = suma;
}
}
void inicializa_matrices();
void imprime_matrices();
int main(int argc, char *argv[]){
//Inicializa matrices A y B
inicializa_matrices();
//Se imprimen resultados?
flag = atoi(argv[1]);
//Variables utilizadas por el device
int size = N*N*sizeof(double);
double *pA, *pB, *pC;
//Memory allocation en el device
hipMalloc((void**)&pA, size);
hipMalloc((void**)&pB, size);
hipMalloc((void**)&pC, size);
//Se copian las matrices del host al device
hipMemcpy(pA, mat_a, size, hipMemcpyHostToDevice);
hipMemcpy(pB, mat_b, size, hipMemcpyHostToDevice);
dim3 dimBlock(N,N);
dim3 dimGrid(1,1);
multiplica<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
hipMemcpy(mat_result, pC, size, hipMemcpyDeviceToHost);
if (flag !=0){
imprime_matrices();
}
hipFree(pA);
hipFree(pB);
hipFree(pC);
return 0;
}
void inicializa_matrices()
{
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_a[i][j] = i + j;
}
}
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_b[i][j] = i*j;
}
}
}
void imprime_matrices()
{ printf("Matriz A \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_a[i][j]);
}
printf("\n\n\n");
printf("Matriz B \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_b[i][j]);
}
printf("\n\n\n");
printf("Matriz C = A * B\n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_result[i][j]);
}
printf("\n\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 20
#define BLOCK_DIM 20
double mat_a[N][N]; //matriz A
double mat_b[N][N]; //matrz B
double mat_result[N][N]; //matriz C
//Contadores de los loops for
int i,j,m;
//Flag para imprimir los resultados
int flag;
__global__ void multiplica(double *A, double *B, double *C, int dim) {
//índices de los hilos
int columna = threadIdx.x + blockDim.x * blockIdx.x;
int renglon = threadIdx.y + blockDim.y * blockIdx.y;
//multiplicación
int k;
double suma = 0;
if(columna < dim && renglon < dim){
for(k = 0; k< dim; k++)
suma = suma + A[renglon*dim + k]*B[k*dim + columna];
C[renglon*dim + columna] = suma;
}
}
void inicializa_matrices();
void imprime_matrices();
int main(int argc, char *argv[]){
//Inicializa matrices A y B
inicializa_matrices();
//Se imprimen resultados?
flag = atoi(argv[1]);
//Variables utilizadas por el device
int size = N*N*sizeof(double);
double *pA, *pB, *pC;
//Memory allocation en el device
hipMalloc((void**)&pA, size);
hipMalloc((void**)&pB, size);
hipMalloc((void**)&pC, size);
//Se copian las matrices del host al device
hipMemcpy(pA, mat_a, size, hipMemcpyHostToDevice);
hipMemcpy(pB, mat_b, size, hipMemcpyHostToDevice);
dim3 dimBlock(N,N);
dim3 dimGrid(1,1);
multiplica<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
hipMemcpy(mat_result, pC, size, hipMemcpyDeviceToHost);
if (flag !=0){
imprime_matrices();
}
hipFree(pA);
hipFree(pB);
hipFree(pC);
return 0;
}
void inicializa_matrices()
{
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_a[i][j] = i + j;
}
}
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_b[i][j] = i*j;
}
}
}
void imprime_matrices()
{ printf("Matriz A \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_a[i][j]);
}
printf("\n\n\n");
printf("Matriz B \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_b[i][j]);
}
printf("\n\n\n");
printf("Matriz C = A * B\n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_result[i][j]);
}
printf("\n\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10multiplicaPdS_S_i
.globl _Z10multiplicaPdS_S_i
.p2align 8
.type _Z10multiplicaPdS_S_i,@function
_Z10multiplicaPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10multiplicaPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10multiplicaPdS_S_i, .Lfunc_end0-_Z10multiplicaPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10multiplicaPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10multiplicaPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 20
#define BLOCK_DIM 20
double mat_a[N][N]; //matriz A
double mat_b[N][N]; //matrz B
double mat_result[N][N]; //matriz C
//Contadores de los loops for
int i,j,m;
//Flag para imprimir los resultados
int flag;
__global__ void multiplica(double *A, double *B, double *C, int dim) {
//índices de los hilos
int columna = threadIdx.x + blockDim.x * blockIdx.x;
int renglon = threadIdx.y + blockDim.y * blockIdx.y;
//multiplicación
int k;
double suma = 0;
if(columna < dim && renglon < dim){
for(k = 0; k< dim; k++)
suma = suma + A[renglon*dim + k]*B[k*dim + columna];
C[renglon*dim + columna] = suma;
}
}
void inicializa_matrices();
void imprime_matrices();
int main(int argc, char *argv[]){
//Inicializa matrices A y B
inicializa_matrices();
//Se imprimen resultados?
flag = atoi(argv[1]);
//Variables utilizadas por el device
int size = N*N*sizeof(double);
double *pA, *pB, *pC;
//Memory allocation en el device
hipMalloc((void**)&pA, size);
hipMalloc((void**)&pB, size);
hipMalloc((void**)&pC, size);
//Se copian las matrices del host al device
hipMemcpy(pA, mat_a, size, hipMemcpyHostToDevice);
hipMemcpy(pB, mat_b, size, hipMemcpyHostToDevice);
dim3 dimBlock(N,N);
dim3 dimGrid(1,1);
multiplica<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
hipMemcpy(mat_result, pC, size, hipMemcpyDeviceToHost);
if (flag !=0){
imprime_matrices();
}
hipFree(pA);
hipFree(pB);
hipFree(pC);
return 0;
}
void inicializa_matrices()
{
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_a[i][j] = i + j;
}
}
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
mat_b[i][j] = i*j;
}
}
}
void imprime_matrices()
{ printf("Matriz A \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_a[i][j]);
}
printf("\n\n\n");
printf("Matriz B \n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_b[i][j]);
}
printf("\n\n\n");
printf("Matriz C = A * B\n");
for (i = 0; i < N; i++) {
printf("\n");
for (j = 0; j < N; j++)
printf("%8.2f ", mat_result[i][j]);
}
printf("\n\n");
} | .text
.file "mat_mult_cuda.hip"
.globl _Z25__device_stub__multiplicaPdS_S_i # -- Begin function _Z25__device_stub__multiplicaPdS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__multiplicaPdS_S_i,@function
_Z25__device_stub__multiplicaPdS_S_i: # @_Z25__device_stub__multiplicaPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10multiplicaPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__multiplicaPdS_S_i, .Lfunc_end0-_Z25__device_stub__multiplicaPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl $mat_a, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader6.i
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdx), %edi
xorps %xmm0, %xmm0
cvtsi2sd %edi, %xmm0
movsd %xmm0, (%rax,%rdx,8)
incq %rdx
cmpq $20, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $160, %rax
cmpq $20, %rcx
jne .LBB1_1
# %bb.4: # %.preheader5.i
movl $20, i(%rip)
movl $20, j(%rip)
movl $mat_b, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %edx, %edx
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd %xmm0, (%rax,%rdi,8)
incq %rdi
addl %ecx, %edx
cmpq $20, %rdi
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $160, %rax
cmpq $20, %rcx
jne .LBB1_5
# %bb.8: # %_Z19inicializa_matricesv.exit
movl $20, i(%rip)
movl $20, j(%rip)
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, flag(%rip)
leaq 24(%rsp), %rdi
movl $3200, %esi # imm = 0xC80
callq hipMalloc
leaq 16(%rsp), %rdi
movl $3200, %esi # imm = 0xC80
callq hipMalloc
leaq 8(%rsp), %rdi
movl $3200, %esi # imm = 0xC80
callq hipMalloc
movq 24(%rsp), %rdi
movl $mat_a, %esi
movl $3200, %edx # imm = 0xC80
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $mat_b, %esi
movl $3200, %edx # imm = 0xC80
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $85899345940, %rdx # imm = 0x1400000014
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $20, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10multiplicaPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rsi
movl $mat_result, %edi
movl $3200, %edx # imm = 0xC80
movl $2, %ecx
callq hipMemcpy
cmpl $0, flag(%rip)
je .LBB1_12
# %bb.11:
callq _Z16imprime_matricesv
.LBB1_12:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z19inicializa_matricesv # -- Begin function _Z19inicializa_matricesv
.p2align 4, 0x90
.type _Z19inicializa_matricesv,@function
_Z19inicializa_matricesv: # @_Z19inicializa_matricesv
.cfi_startproc
# %bb.0:
movl $mat_a, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # %.preheader6
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdx), %esi
xorps %xmm0, %xmm0
cvtsi2sd %esi, %xmm0
movsd %xmm0, (%rax,%rdx,8)
incq %rdx
cmpq $20, %rdx
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rcx
addq $160, %rax
cmpq $20, %rcx
jne .LBB2_1
# %bb.4: # %.preheader5
movl $20, i(%rip)
movl $20, j(%rip)
movl $mat_b, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd %xmm0, (%rax,%rsi,8)
incq %rsi
addl %ecx, %edx
cmpq $20, %rsi
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
incq %rcx
addq $160, %rax
cmpq $20, %rcx
jne .LBB2_5
# %bb.8:
movl $20, i(%rip)
movl $20, j(%rip)
retq
.Lfunc_end2:
.size _Z19inicializa_matricesv, .Lfunc_end2-_Z19inicializa_matricesv
.cfi_endproc
# -- End function
.globl _Z16imprime_matricesv # -- Begin function _Z16imprime_matricesv
.p2align 4, 0x90
.type _Z16imprime_matricesv,@function
_Z16imprime_matricesv: # @_Z16imprime_matricesv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $0, i(%rip)
.p2align 4, 0x90
.LBB3_1: # =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movl $10, %edi
callq putchar@PLT
movl $0, j(%rip)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movslq i(%rip), %rcx
cltq
leaq (%rcx,%rcx,4), %rcx
shlq $5, %rcx
movsd mat_a(%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl j(%rip), %ecx
leal 1(%rcx), %eax
movl %eax, j(%rip)
cmpl $19, %ecx
jl .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
movl i(%rip), %eax
leal 1(%rax), %ecx
movl %ecx, i(%rip)
cmpl $19, %eax
jl .LBB3_1
# %bb.4:
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $0, i(%rip)
.p2align 4, 0x90
.LBB3_5: # =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl $10, %edi
callq putchar@PLT
movl $0, j(%rip)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movslq i(%rip), %rcx
cltq
leaq (%rcx,%rcx,4), %rcx
shlq $5, %rcx
movsd mat_b(%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl j(%rip), %ecx
leal 1(%rcx), %eax
movl %eax, j(%rip)
cmpl $19, %ecx
jl .LBB3_6
# %bb.7: # in Loop: Header=BB3_5 Depth=1
movl i(%rip), %eax
leal 1(%rax), %ecx
movl %ecx, i(%rip)
cmpl $19, %eax
jl .LBB3_5
# %bb.8:
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $0, i(%rip)
.p2align 4, 0x90
.LBB3_9: # =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
movl $10, %edi
callq putchar@PLT
movl $0, j(%rip)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
movslq i(%rip), %rcx
cltq
leaq (%rcx,%rcx,4), %rcx
shlq $5, %rcx
movsd mat_result(%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl j(%rip), %ecx
leal 1(%rcx), %eax
movl %eax, j(%rip)
cmpl $19, %ecx
jl .LBB3_10
# %bb.11: # in Loop: Header=BB3_9 Depth=1
movl i(%rip), %eax
leal 1(%rax), %ecx
movl %ecx, i(%rip)
cmpl $19, %eax
jl .LBB3_9
# %bb.12:
movl $.Lstr.5, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z16imprime_matricesv, .Lfunc_end3-_Z16imprime_matricesv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10multiplicaPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type mat_a,@object # @mat_a
.bss
.globl mat_a
.p2align 4, 0x0
mat_a:
.zero 3200
.size mat_a, 3200
.type mat_b,@object # @mat_b
.globl mat_b
.p2align 4, 0x0
mat_b:
.zero 3200
.size mat_b, 3200
.type mat_result,@object # @mat_result
.globl mat_result
.p2align 4, 0x0
mat_result:
.zero 3200
.size mat_result, 3200
.type i,@object # @i
.globl i
.p2align 2, 0x0
i:
.long 0 # 0x0
.size i, 4
.type j,@object # @j
.globl j
.p2align 2, 0x0
j:
.long 0 # 0x0
.size j, 4
.type m,@object # @m
.globl m
.p2align 2, 0x0
m:
.long 0 # 0x0
.size m, 4
.type flag,@object # @flag
.globl flag
.p2align 2, 0x0
flag:
.long 0 # 0x0
.size flag, 4
.type _Z10multiplicaPdS_S_i,@object # @_Z10multiplicaPdS_S_i
.section .rodata,"a",@progbits
.globl _Z10multiplicaPdS_S_i
.p2align 3, 0x0
_Z10multiplicaPdS_S_i:
.quad _Z25__device_stub__multiplicaPdS_S_i
.size _Z10multiplicaPdS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%8.2f "
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10multiplicaPdS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matriz A "
.size .Lstr, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Matriz B "
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n\n"
.size .Lstr.3, 3
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Matriz C = A * B"
.size .Lstr.4, 17
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\n"
.size .Lstr.5, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__multiplicaPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mat_a
.addrsig_sym mat_b
.addrsig_sym mat_result
.addrsig_sym _Z10multiplicaPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10multiplicaPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10multiplicaPdS_S_i
.globl _Z10multiplicaPdS_S_i
.p2align 8
.type _Z10multiplicaPdS_S_i,@function
_Z10multiplicaPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10multiplicaPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10multiplicaPdS_S_i, .Lfunc_end0-_Z10multiplicaPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10multiplicaPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10multiplicaPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018d5f8_00000000-6_mat_mult_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19inicializa_matricesv
.type _Z19inicializa_matricesv, @function
_Z19inicializa_matricesv:
.LFB2058:
.cfi_startproc
endbr64
leaq mat_a(%rip), %rsi
movl $20, %ecx
.L5:
leal -20(%rcx), %eax
movq %rsi, %rdx
.L4:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rdx)
addl $1, %eax
addq $8, %rdx
cmpl %ecx, %eax
jne .L4
addq $160, %rsi
addl $1, %ecx
cmpl $40, %ecx
jne .L5
leaq 160+mat_b(%rip), %rcx
movl $0, %edi
.L7:
movl %edi, %esi
leaq -160(%rcx), %rax
movl $0, %edx
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, (%rax)
addl %esi, %edx
addq $8, %rax
cmpq %rcx, %rax
jne .L6
addq $1, %rdi
addq $160, %rcx
cmpq $20, %rdi
jne .L7
movl $20, j(%rip)
movl $20, i(%rip)
ret
.cfi_endproc
.LFE2058:
.size _Z19inicializa_matricesv, .-_Z19inicializa_matricesv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matriz A \n"
.LC1:
.string "\n"
.LC2:
.string "%8.2f "
.LC3:
.string "\n\n\n"
.LC4:
.string "Matriz B \n"
.LC5:
.string "Matriz C = A * B\n"
.LC6:
.string "\n\n"
.text
.globl _Z16imprime_matricesv
.type _Z16imprime_matricesv, @function
_Z16imprime_matricesv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, i(%rip)
leaq .LC1(%rip), %r12
leaq mat_a(%rip), %rbp
leaq .LC2(%rip), %rbx
.L14:
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, j(%rip)
movl $0, %eax
.L13:
cltq
movslq i(%rip), %rdx
leaq (%rdx,%rdx,4), %rdx
leaq (%rax,%rdx,4), %rax
movsd 0(%rbp,%rax,8), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl j(%rip), %eax
addl $1, %eax
movl %eax, j(%rip)
cmpl $19, %eax
jle .L13
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
cmpl $19, %eax
jle .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, i(%rip)
leaq .LC1(%rip), %r12
leaq mat_b(%rip), %rbp
leaq .LC2(%rip), %rbx
.L16:
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, j(%rip)
movl $0, %eax
.L15:
cltq
movslq i(%rip), %rdx
leaq (%rdx,%rdx,4), %rdx
leaq (%rax,%rdx,4), %rax
movsd 0(%rbp,%rax,8), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl j(%rip), %eax
addl $1, %eax
movl %eax, j(%rip)
cmpl $19, %eax
jle .L15
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
cmpl $19, %eax
jle .L16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, i(%rip)
leaq .LC1(%rip), %r12
leaq mat_result(%rip), %rbp
leaq .LC2(%rip), %rbx
.L18:
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, j(%rip)
movl $0, %eax
.L17:
cltq
movslq i(%rip), %rdx
leaq (%rdx,%rdx,4), %rdx
leaq (%rax,%rdx,4), %rax
movsd 0(%rbp,%rax,8), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl j(%rip), %eax
addl $1, %eax
movl %eax, j(%rip)
cmpl $19, %eax
jle .L17
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
cmpl $19, %eax
jle .L18
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z16imprime_matricesv, .-_Z16imprime_matricesv
.globl _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i
.type _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i, @function
_Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10multiplicaPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i, .-_Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i
.globl _Z10multiplicaPdS_S_i
.type _Z10multiplicaPdS_S_i, @function
_Z10multiplicaPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10multiplicaPdS_S_i, .-_Z10multiplicaPdS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Z19inicializa_matricesv
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, flag(%rip)
leaq 8(%rsp), %rdi
movl $3200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $3200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $3200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $3200, %edx
leaq mat_a(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $3200, %edx
leaq mat_b(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $20, 32(%rsp)
movl $20, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movl $2, %ecx
movl $3200, %edx
movq 24(%rsp), %rsi
leaq mat_result(%rip), %rdi
call cudaMemcpy@PLT
cmpl $0, flag(%rip)
jne .L40
.L36:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $20, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10multiplicaPdS_S_iPdS_S_i
jmp .L35
.L40:
call _Z16imprime_matricesv
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10multiplicaPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10multiplicaPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl flag
.bss
.align 4
.type flag, @object
.size flag, 4
flag:
.zero 4
.globl m
.align 4
.type m, @object
.size m, 4
m:
.zero 4
.globl j
.align 4
.type j, @object
.size j, 4
j:
.zero 4
.globl i
.align 4
.type i, @object
.size i, 4
i:
.zero 4
.globl mat_result
.align 32
.type mat_result, @object
.size mat_result, 3200
mat_result:
.zero 3200
.globl mat_b
.align 32
.type mat_b, @object
.size mat_b, 3200
mat_b:
.zero 3200
.globl mat_a
.align 32
.type mat_a, @object
.size mat_a, 3200
mat_a:
.zero 3200
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mult_cuda.hip"
.globl _Z25__device_stub__multiplicaPdS_S_i # -- Begin function _Z25__device_stub__multiplicaPdS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__multiplicaPdS_S_i,@function
_Z25__device_stub__multiplicaPdS_S_i: # @_Z25__device_stub__multiplicaPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10multiplicaPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__multiplicaPdS_S_i, .Lfunc_end0-_Z25__device_stub__multiplicaPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl $mat_a, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader6.i
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdx), %edi
xorps %xmm0, %xmm0
cvtsi2sd %edi, %xmm0
movsd %xmm0, (%rax,%rdx,8)
incq %rdx
cmpq $20, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $160, %rax
cmpq $20, %rcx
jne .LBB1_1
# %bb.4: # %.preheader5.i
movl $20, i(%rip)
movl $20, j(%rip)
movl $mat_b, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %edx, %edx
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd %xmm0, (%rax,%rdi,8)
incq %rdi
addl %ecx, %edx
cmpq $20, %rdi
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $160, %rax
cmpq $20, %rcx
jne .LBB1_5
# %bb.8: # %_Z19inicializa_matricesv.exit
movl $20, i(%rip)
movl $20, j(%rip)
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, flag(%rip)
leaq 24(%rsp), %rdi
movl $3200, %esi # imm = 0xC80
callq hipMalloc
leaq 16(%rsp), %rdi
movl $3200, %esi # imm = 0xC80
callq hipMalloc
leaq 8(%rsp), %rdi
movl $3200, %esi # imm = 0xC80
callq hipMalloc
movq 24(%rsp), %rdi
movl $mat_a, %esi
movl $3200, %edx # imm = 0xC80
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $mat_b, %esi
movl $3200, %edx # imm = 0xC80
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $85899345940, %rdx # imm = 0x1400000014
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $20, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10multiplicaPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rsi
movl $mat_result, %edi
movl $3200, %edx # imm = 0xC80
movl $2, %ecx
callq hipMemcpy
cmpl $0, flag(%rip)
je .LBB1_12
# %bb.11:
callq _Z16imprime_matricesv
.LBB1_12:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z19inicializa_matricesv # -- Begin function _Z19inicializa_matricesv
.p2align 4, 0x90
.type _Z19inicializa_matricesv,@function
_Z19inicializa_matricesv: # @_Z19inicializa_matricesv
.cfi_startproc
# %bb.0:
movl $mat_a, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # %.preheader6
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdx), %esi
xorps %xmm0, %xmm0
cvtsi2sd %esi, %xmm0
movsd %xmm0, (%rax,%rdx,8)
incq %rdx
cmpq $20, %rdx
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rcx
addq $160, %rax
cmpq $20, %rcx
jne .LBB2_1
# %bb.4: # %.preheader5
movl $20, i(%rip)
movl $20, j(%rip)
movl $mat_b, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd %xmm0, (%rax,%rsi,8)
incq %rsi
addl %ecx, %edx
cmpq $20, %rsi
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
incq %rcx
addq $160, %rax
cmpq $20, %rcx
jne .LBB2_5
# %bb.8:
movl $20, i(%rip)
movl $20, j(%rip)
retq
.Lfunc_end2:
.size _Z19inicializa_matricesv, .Lfunc_end2-_Z19inicializa_matricesv
.cfi_endproc
# -- End function
.globl _Z16imprime_matricesv # -- Begin function _Z16imprime_matricesv
.p2align 4, 0x90
.type _Z16imprime_matricesv,@function
_Z16imprime_matricesv: # @_Z16imprime_matricesv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $0, i(%rip)
.p2align 4, 0x90
.LBB3_1: # =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movl $10, %edi
callq putchar@PLT
movl $0, j(%rip)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movslq i(%rip), %rcx
cltq
leaq (%rcx,%rcx,4), %rcx
shlq $5, %rcx
movsd mat_a(%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl j(%rip), %ecx
leal 1(%rcx), %eax
movl %eax, j(%rip)
cmpl $19, %ecx
jl .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
movl i(%rip), %eax
leal 1(%rax), %ecx
movl %ecx, i(%rip)
cmpl $19, %eax
jl .LBB3_1
# %bb.4:
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $0, i(%rip)
.p2align 4, 0x90
.LBB3_5: # =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl $10, %edi
callq putchar@PLT
movl $0, j(%rip)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movslq i(%rip), %rcx
cltq
leaq (%rcx,%rcx,4), %rcx
shlq $5, %rcx
movsd mat_b(%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl j(%rip), %ecx
leal 1(%rcx), %eax
movl %eax, j(%rip)
cmpl $19, %ecx
jl .LBB3_6
# %bb.7: # in Loop: Header=BB3_5 Depth=1
movl i(%rip), %eax
leal 1(%rax), %ecx
movl %ecx, i(%rip)
cmpl $19, %eax
jl .LBB3_5
# %bb.8:
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $0, i(%rip)
.p2align 4, 0x90
.LBB3_9: # =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
movl $10, %edi
callq putchar@PLT
movl $0, j(%rip)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
movslq i(%rip), %rcx
cltq
leaq (%rcx,%rcx,4), %rcx
shlq $5, %rcx
movsd mat_result(%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl j(%rip), %ecx
leal 1(%rcx), %eax
movl %eax, j(%rip)
cmpl $19, %ecx
jl .LBB3_10
# %bb.11: # in Loop: Header=BB3_9 Depth=1
movl i(%rip), %eax
leal 1(%rax), %ecx
movl %ecx, i(%rip)
cmpl $19, %eax
jl .LBB3_9
# %bb.12:
movl $.Lstr.5, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z16imprime_matricesv, .Lfunc_end3-_Z16imprime_matricesv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10multiplicaPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type mat_a,@object # @mat_a
.bss
.globl mat_a
.p2align 4, 0x0
mat_a:
.zero 3200
.size mat_a, 3200
.type mat_b,@object # @mat_b
.globl mat_b
.p2align 4, 0x0
mat_b:
.zero 3200
.size mat_b, 3200
.type mat_result,@object # @mat_result
.globl mat_result
.p2align 4, 0x0
mat_result:
.zero 3200
.size mat_result, 3200
.type i,@object # @i
.globl i
.p2align 2, 0x0
i:
.long 0 # 0x0
.size i, 4
.type j,@object # @j
.globl j
.p2align 2, 0x0
j:
.long 0 # 0x0
.size j, 4
.type m,@object # @m
.globl m
.p2align 2, 0x0
m:
.long 0 # 0x0
.size m, 4
.type flag,@object # @flag
.globl flag
.p2align 2, 0x0
flag:
.long 0 # 0x0
.size flag, 4
.type _Z10multiplicaPdS_S_i,@object # @_Z10multiplicaPdS_S_i
.section .rodata,"a",@progbits
.globl _Z10multiplicaPdS_S_i
.p2align 3, 0x0
_Z10multiplicaPdS_S_i:
.quad _Z25__device_stub__multiplicaPdS_S_i
.size _Z10multiplicaPdS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%8.2f "
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10multiplicaPdS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matriz A "
.size .Lstr, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Matriz B "
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n\n"
.size .Lstr.3, 3
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Matriz C = A * B"
.size .Lstr.4, 17
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\n"
.size .Lstr.5, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__multiplicaPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mat_a
.addrsig_sym mat_b
.addrsig_sym mat_result
.addrsig_sym _Z10multiplicaPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdint.h>
#include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <stdlib.h>
#include <sys/mman.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
inline double diff_s(struct timeval start, struct timeval end)
{
return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}
__global__ void readKernel(uint64_t *memory, uint64_t *memoryToRead)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
//memory[tid]=memoryToRead[tid];
//__shared__ uint64_t temp;
uint64_t temp = memoryToRead[tid];
if(!temp)
__syncthreads();
}
__global__ void writeKernel(uint64_t *memory)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
memory[tid]=5;
}
__global__ void nullKernel(int *memory)
{
}
__global__ void initCudaMallocd(uint64_t *memory, int N)
{
int tid =threadIdx.x;
if(tid==0){
for(int k=0;k< N ;k++)
memory[k]=5;
}
}
void verify(uint64_t* memory, int N)
{
int error = 0;
for(int i =0; i<N; i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(uint64_t* memory, int N)
{
int tid=threadIdx.x;
if(tid==0) {
int error = 0;
for(int i =0; i<N; i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
}
int
main( int argc, char *argv[] )
{
uint64_t *hostAllocd, *cudaMallocd, *cpuMallocd;
int ITERATIONS = 100000;
int numBytes = 1;
struct timeval tv1, tv2;
int opt;
int read=0; //read benchmark? or write?
int benchmarkType = 0;
int locked = 0; //mlock data?
int dryRun = 0; //dry run to measure noise TLB misses/...etc
while ((opt = getopt(argc, argv, "m:b:i:r:ld")) != -1) {
switch (opt) {
case 'm':
numBytes = atoi(optarg);
//assert(numBytes%16 == 0 && numBytes<=1024);
break;
case 'b':
benchmarkType = atoi(optarg);
break;
case 'i':
ITERATIONS = atoi(optarg);
break;
case 'r':
read = atoi(optarg);
break;
case 'l':
locked = 1;
break;
case 'd':
dryRun = 1;
break;
default: /* '?' */
break;
}
}
int num_of_blocks=1;
int num_of_threads_per_block=numBytes;
if(numBytes>1024){
num_of_blocks = 16;
num_of_threads_per_block = numBytes/16;
}
if(benchmarkType == 0 || benchmarkType == 1)
HANDLE_ERROR(cudaFree(0));
switch (benchmarkType) {
case 0: {//read/Write to hostAlloc'd data
HANDLE_ERROR( cudaHostAlloc( &hostAllocd, sizeof(uint64_t)*numBytes, 0 ) );
for(int k=0;k< numBytes ;k++){
hostAllocd[k]=1;
}
if(read)
{
uint64_t *memoryToRead;
HANDLE_ERROR( cudaHostAlloc( &memoryToRead, sizeof(uint64_t)*numBytes, 0 ) );
for(int k=0;k< numBytes ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFreeHost(memoryToRead);
//verify(hostAllocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
verify(hostAllocd,numBytes);
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("HostAlloc [%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
cudaFreeHost(hostAllocd);
break;
}
case 1: {//read/Write to cudaMalloc'd data
cpuMallocd = (uint64_t *)malloc(sizeof(uint64_t)*numBytes);
assert(cpuMallocd);
for(int k=0;k< numBytes ;k++){
cpuMallocd[k]=1;
}
HANDLE_ERROR( cudaMalloc( &cudaMallocd, sizeof(uint64_t)*numBytes) );
HANDLE_ERROR( cudaMemcpy( cudaMallocd,cpuMallocd, sizeof(uint64_t)*numBytes,cudaMemcpyDefault) );
if(read)
{
uint64_t *memoryToRead;
HANDLE_ERROR( cudaMalloc( &memoryToRead, sizeof(uint64_t)*numBytes ) );
initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
HANDLE_ERROR( cudaDeviceSynchronize());
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFree(memoryToRead);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("CudaMalloc [%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
free(cpuMallocd);
cudaFree(cudaMallocd);
break;
}
case 2:
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 3: {//read/Write to cpu mallocd data
uint64_t *memory_to_access = (uint64_t *)malloc(sizeof(uint64_t)*numBytes );
if(!dryRun) {
if(locked)
mlock(memory_to_access,sizeof(uint64_t)*numBytes);
assert(memory_to_access);
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu malloc [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
free(memory_to_access);
break;
}
case 4: {//read/Write to cpu but hostsllocd data
uint64_t *memory_to_access;
HANDLE_ERROR(cudaSetDevice(0));
HANDLE_ERROR(cudaSetDeviceFlags(cudaDeviceMapHost));
HANDLE_ERROR(cudaFree(0));
HANDLE_ERROR(cudaHostAlloc(&memory_to_access,sizeof(uint64_t)*numBytes,cudaHostAllocMapped));
if(!dryRun) {
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu hostAlloc [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
cudaFreeHost(memory_to_access);
break;
}
case 5: {//read/Write to cpu but mallocManaged data
uint64_t *memory_to_access;
HANDLE_ERROR(cudaMallocManaged(&memory_to_access,sizeof(uint64_t)*numBytes));
if(!dryRun) {
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu mallocManaged [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
cudaFree(memory_to_access);
break;
}
}
if(benchmarkType == 0 || benchmarkType == 1)
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z17verifyCudaMallocdPmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0060*/ @!P0 BRA 0x120 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R2, 0x5, PT ; /* 0x000000050200780c */
/* 0x004fc80003f05070 */
/*00d0*/ ISETP.NE.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0003f05300 */
/*00e0*/ @P0 BRA 0x200 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0110*/ @!P0 BRA 0x90 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0140*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0160*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0220*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0240*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0250*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0260*/ MOV R11, 0x2d0 ; /* 0x000002d0000b7802 */
/* 0x000fe40000000f00 */
/*0270*/ MOV R20, 0x250 ; /* 0x0000025000147802 */
/* 0x000fe40000000f00 */
/*0280*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0290*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*02a0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*02b0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*02c0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15initCudaMallocdPmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0030*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f06270 */
/*0040*/ ISETP.NE.OR P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720c */
/* 0x001fda0004705670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0070*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0080*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0090*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*00b0*/ @!P0 BRA 0x530 ; /* 0x0000047000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R6, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*00f0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd800078e00ff */
/*0110*/ @!P0 BRA 0x450 ; /* 0x0000033000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x300 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, 0x5 ; /* 0x00000005ff047424 */
/* 0x000fe200078e00ff */
/*0180*/ IADD3 R7, P2, R2, 0x80, RZ ; /* 0x0000008002077810 */
/* 0x000fe20007f5e0ff */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe200078e00ff */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*01b0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*01c0*/ IMAD.X R8, RZ, RZ, R3, P2 ; /* 0x000000ffff087224 */
/* 0x000fe200010e0603 */
/*01d0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101b08 */
/*01e0*/ STG.E.64 [R2.64+0x8], R4 ; /* 0x0000080402007986 */
/* 0x000fe8000c101b08 */
/*01f0*/ STG.E.64 [R2.64+0x10], R4 ; /* 0x0000100402007986 */
/* 0x000fe8000c101b08 */
/*0200*/ STG.E.64 [R2.64+0x18], R4 ; /* 0x0000180402007986 */
/* 0x000fe8000c101b08 */
/*0210*/ STG.E.64 [R2.64+0x20], R4 ; /* 0x0000200402007986 */
/* 0x000fe8000c101b08 */
/*0220*/ STG.E.64 [R2.64+0x28], R4 ; /* 0x0000280402007986 */
/* 0x000fe8000c101b08 */
/*0230*/ STG.E.64 [R2.64+0x30], R4 ; /* 0x0000300402007986 */
/* 0x000fe8000c101b08 */
/*0240*/ STG.E.64 [R2.64+0x38], R4 ; /* 0x0000380402007986 */
/* 0x000fe8000c101b08 */
/*0250*/ STG.E.64 [R2.64+0x40], R4 ; /* 0x0000400402007986 */
/* 0x000fe8000c101b08 */
/*0260*/ STG.E.64 [R2.64+0x48], R4 ; /* 0x0000480402007986 */
/* 0x000fe8000c101b08 */
/*0270*/ STG.E.64 [R2.64+0x50], R4 ; /* 0x0000500402007986 */
/* 0x000fe8000c101b08 */
/*0280*/ STG.E.64 [R2.64+0x58], R4 ; /* 0x0000580402007986 */
/* 0x000fe8000c101b08 */
/*0290*/ STG.E.64 [R2.64+0x60], R4 ; /* 0x0000600402007986 */
/* 0x000fe8000c101b08 */
/*02a0*/ STG.E.64 [R2.64+0x68], R4 ; /* 0x0000680402007986 */
/* 0x000fe8000c101b08 */
/*02b0*/ STG.E.64 [R2.64+0x70], R4 ; /* 0x0000700402007986 */
/* 0x000fe8000c101b08 */
/*02c0*/ STG.E.64 [R2.64+0x78], R4 ; /* 0x0000780402007986 */
/* 0x0001e4000c101b08 */
/*02d0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*02f0*/ @P1 BRA 0x160 ; /* 0xfffffe6000001947 */
/* 0x000fea000383ffff */
/*0300*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0310*/ @!P1 BRA 0x430 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0320*/ IADD3 R7, P1, R2, 0x40, RZ ; /* 0x0000004002077810 */
/* 0x000fe20007f3e0ff */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, 0x5 ; /* 0x00000005ff047424 */
/* 0x000fe200078e00ff */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0350*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe200078e00ff */
/*0360*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0370*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0603 */
/*0380*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe4000fffe03f */
/*0390*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101b08 */
/*03a0*/ STG.E.64 [R2.64+0x8], R4 ; /* 0x0000080402007986 */
/* 0x000fe8000c101b08 */
/*03b0*/ STG.E.64 [R2.64+0x10], R4 ; /* 0x0000100402007986 */
/* 0x000fe8000c101b08 */
/*03c0*/ STG.E.64 [R2.64+0x18], R4 ; /* 0x0000180402007986 */
/* 0x000fe8000c101b08 */
/*03d0*/ STG.E.64 [R2.64+0x20], R4 ; /* 0x0000200402007986 */
/* 0x000fe8000c101b08 */
/*03e0*/ STG.E.64 [R2.64+0x28], R4 ; /* 0x0000280402007986 */
/* 0x000fe8000c101b08 */
/*03f0*/ STG.E.64 [R2.64+0x30], R4 ; /* 0x0000300402007986 */
/* 0x000fe8000c101b08 */
/*0400*/ STG.E.64 [R2.64+0x38], R4 ; /* 0x0000380402007986 */
/* 0x0001e4000c101b08 */
/*0410*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0420*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0008 */
/*0430*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0440*/ @!P0 BRA 0x530 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0450*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0460*/ IMAD.MOV.U32 R4, RZ, RZ, 0x5 ; /* 0x00000005ff047424 */
/* 0x000fe200078e00ff */
/*0470*/ IADD3 R7, P1, R2, 0x20, RZ ; /* 0x0000002002077810 */
/* 0x000fe20007f3e0ff */
/*0480*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe200078e00ff */
/*0490*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*04a0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*04b0*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0603 */
/*04c0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101b08 */
/*04d0*/ STG.E.64 [R2.64+0x8], R4 ; /* 0x0000080402007986 */
/* 0x000fe8000c101b08 */
/*04e0*/ STG.E.64 [R2.64+0x10], R4 ; /* 0x0000100402007986 */
/* 0x000fe8000c101b08 */
/*04f0*/ STG.E.64 [R2.64+0x18], R4 ; /* 0x0000180402007986 */
/* 0x0001e4000c101b08 */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0510*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*0520*/ @P0 BRA 0x450 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0530*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0540*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, 0x5 ; /* 0x00000005ff047424 */
/* 0x000fe200078e00ff */
/*0560*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe20000000000 */
/*0570*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe200078e00ff */
/*0580*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0590*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e0206 */
/*05a0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x001fe2000f8e00ff */
/*05c0*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000ff1e03f */
/*05d0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*05e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*05f0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc400087fe43f */
/*0600*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001f2000c101b08 */
/*0610*/ @P0 BRA 0x5a0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10nullKernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11writeKernelPm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R4, 0x5 ; /* 0x0000000500047802 */
/* 0x000fe20000000f00 */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0080*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0090*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10readKernelPmS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E.64.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e9b00 */
/*0080*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc80003f05070 */
/*0090*/ ISETP.NE.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0003f05300 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdint.h>
#include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <stdlib.h>
#include <sys/mman.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
inline double diff_s(struct timeval start, struct timeval end)
{
return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}
__global__ void readKernel(uint64_t *memory, uint64_t *memoryToRead)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
//memory[tid]=memoryToRead[tid];
//__shared__ uint64_t temp;
uint64_t temp = memoryToRead[tid];
if(!temp)
__syncthreads();
}
__global__ void writeKernel(uint64_t *memory)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
memory[tid]=5;
}
__global__ void nullKernel(int *memory)
{
}
__global__ void initCudaMallocd(uint64_t *memory, int N)
{
int tid =threadIdx.x;
if(tid==0){
for(int k=0;k< N ;k++)
memory[k]=5;
}
}
void verify(uint64_t* memory, int N)
{
int error = 0;
for(int i =0; i<N; i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(uint64_t* memory, int N)
{
int tid=threadIdx.x;
if(tid==0) {
int error = 0;
for(int i =0; i<N; i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
}
int
main( int argc, char *argv[] )
{
uint64_t *hostAllocd, *cudaMallocd, *cpuMallocd;
int ITERATIONS = 100000;
int numBytes = 1;
struct timeval tv1, tv2;
int opt;
int read=0; //read benchmark? or write?
int benchmarkType = 0;
int locked = 0; //mlock data?
int dryRun = 0; //dry run to measure noise TLB misses/...etc
while ((opt = getopt(argc, argv, "m:b:i:r:ld")) != -1) {
switch (opt) {
case 'm':
numBytes = atoi(optarg);
//assert(numBytes%16 == 0 && numBytes<=1024);
break;
case 'b':
benchmarkType = atoi(optarg);
break;
case 'i':
ITERATIONS = atoi(optarg);
break;
case 'r':
read = atoi(optarg);
break;
case 'l':
locked = 1;
break;
case 'd':
dryRun = 1;
break;
default: /* '?' */
break;
}
}
int num_of_blocks=1;
int num_of_threads_per_block=numBytes;
if(numBytes>1024){
num_of_blocks = 16;
num_of_threads_per_block = numBytes/16;
}
if(benchmarkType == 0 || benchmarkType == 1)
HANDLE_ERROR(cudaFree(0));
switch (benchmarkType) {
case 0: {//read/Write to hostAlloc'd data
HANDLE_ERROR( cudaHostAlloc( &hostAllocd, sizeof(uint64_t)*numBytes, 0 ) );
for(int k=0;k< numBytes ;k++){
hostAllocd[k]=1;
}
if(read)
{
uint64_t *memoryToRead;
HANDLE_ERROR( cudaHostAlloc( &memoryToRead, sizeof(uint64_t)*numBytes, 0 ) );
for(int k=0;k< numBytes ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFreeHost(memoryToRead);
//verify(hostAllocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
verify(hostAllocd,numBytes);
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("HostAlloc [%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
cudaFreeHost(hostAllocd);
break;
}
case 1: {//read/Write to cudaMalloc'd data
cpuMallocd = (uint64_t *)malloc(sizeof(uint64_t)*numBytes);
assert(cpuMallocd);
for(int k=0;k< numBytes ;k++){
cpuMallocd[k]=1;
}
HANDLE_ERROR( cudaMalloc( &cudaMallocd, sizeof(uint64_t)*numBytes) );
HANDLE_ERROR( cudaMemcpy( cudaMallocd,cpuMallocd, sizeof(uint64_t)*numBytes,cudaMemcpyDefault) );
if(read)
{
uint64_t *memoryToRead;
HANDLE_ERROR( cudaMalloc( &memoryToRead, sizeof(uint64_t)*numBytes ) );
initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
HANDLE_ERROR( cudaDeviceSynchronize());
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFree(memoryToRead);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("CudaMalloc [%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
free(cpuMallocd);
cudaFree(cudaMallocd);
break;
}
case 2:
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 3: {//read/Write to cpu mallocd data
uint64_t *memory_to_access = (uint64_t *)malloc(sizeof(uint64_t)*numBytes );
if(!dryRun) {
if(locked)
mlock(memory_to_access,sizeof(uint64_t)*numBytes);
assert(memory_to_access);
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu malloc [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
free(memory_to_access);
break;
}
case 4: {//read/Write to cpu but hostsllocd data
uint64_t *memory_to_access;
HANDLE_ERROR(cudaSetDevice(0));
HANDLE_ERROR(cudaSetDeviceFlags(cudaDeviceMapHost));
HANDLE_ERROR(cudaFree(0));
HANDLE_ERROR(cudaHostAlloc(&memory_to_access,sizeof(uint64_t)*numBytes,cudaHostAllocMapped));
if(!dryRun) {
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu hostAlloc [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
cudaFreeHost(memory_to_access);
break;
}
case 5: {//read/Write to cpu but mallocManaged data
uint64_t *memory_to_access;
HANDLE_ERROR(cudaMallocManaged(&memory_to_access,sizeof(uint64_t)*numBytes));
if(!dryRun) {
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu mallocManaged [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
cudaFree(memory_to_access);
break;
}
}
if(benchmarkType == 0 || benchmarkType == 1)
cudaDeviceReset();
return 0;
} | .file "tmpxft_0007df94_00000000-6_latencyTest.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2070:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC1:
.string "verified SUCCESS\n"
.LC2:
.string "error in verification\n"
.text
.globl _Z6verifyPmi
.type _Z6verifyPmi, @function
_Z6verifyPmi:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %esi, %esi
jle .L10
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rdx
.L12:
cmpq $5, (%rax)
jne .L11
addq $8, %rax
cmpq %rdx, %rax
jne .L12
.L10:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L9:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.cfi_endproc
.LFE2072:
.size _Z6verifyPmi, .-_Z6verifyPmi
.globl _Z32__device_stub__Z10readKernelPmS_PmS_
.type _Z32__device_stub__Z10readKernelPmS_PmS_, @function
_Z32__device_stub__Z10readKernelPmS_PmS_:
.LFB2098:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10readKernelPmS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z32__device_stub__Z10readKernelPmS_PmS_, .-_Z32__device_stub__Z10readKernelPmS_PmS_
.globl _Z10readKernelPmS_
.type _Z10readKernelPmS_, @function
_Z10readKernelPmS_:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10readKernelPmS_PmS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z10readKernelPmS_, .-_Z10readKernelPmS_
.globl _Z31__device_stub__Z11writeKernelPmPm
.type _Z31__device_stub__Z11writeKernelPmPm, @function
_Z31__device_stub__Z11writeKernelPmPm:
.LFB2100:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11writeKernelPm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z31__device_stub__Z11writeKernelPmPm, .-_Z31__device_stub__Z11writeKernelPmPm
.globl _Z11writeKernelPm
.type _Z11writeKernelPm, @function
_Z11writeKernelPm:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11writeKernelPmPm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z11writeKernelPm, .-_Z11writeKernelPm
.globl _Z30__device_stub__Z10nullKernelPiPi
.type _Z30__device_stub__Z10nullKernelPiPi, @function
_Z30__device_stub__Z10nullKernelPiPi:
.LFB2102:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10nullKernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z30__device_stub__Z10nullKernelPiPi, .-_Z30__device_stub__Z10nullKernelPiPi
.globl _Z10nullKernelPi
.type _Z10nullKernelPi, @function
_Z10nullKernelPi:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10nullKernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _Z10nullKernelPi, .-_Z10nullKernelPi
.globl _Z36__device_stub__Z15initCudaMallocdPmiPmi
.type _Z36__device_stub__Z15initCudaMallocdPmiPmi, @function
_Z36__device_stub__Z15initCudaMallocdPmiPmi:
.LFB2104:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15initCudaMallocdPmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z36__device_stub__Z15initCudaMallocdPmiPmi, .-_Z36__device_stub__Z15initCudaMallocdPmiPmi
.globl _Z15initCudaMallocdPmi
.type _Z15initCudaMallocdPmi, @function
_Z15initCudaMallocdPmi:
.LFB2105:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15initCudaMallocdPmiPmi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z15initCudaMallocdPmi, .-_Z15initCudaMallocdPmi
.section .rodata.str1.1
.LC3:
.string "read"
.LC4:
.string "write"
.LC5:
.string "m:b:i:r:ld"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mkdashti/bandwidthTest/master/latency-64b/latencyTest.cu"
.align 8
.LC8:
.string "HostAlloc [%s] Latency including kernel launch overhead = %f us\n"
.align 8
.LC9:
.string "CudaMalloc [%s] Latency including kernel launch overhead = %f us\n"
.align 8
.LC10:
.string "null kernel launch overhead = %f us\n"
.align 8
.LC11:
.string "cpu malloc [%s] Latency = %f us\n"
.align 8
.LC12:
.string "cpu hostAlloc [%s] Latency = %f us\n"
.align 8
.LC13:
.string "cpu mallocManaged [%s] Latency = %f us\n"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %r12d
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, 8(%rsp)
movl $0, 12(%rsp)
movl $0, (%rsp)
movl $0, 4(%rsp)
movl $1, %ebx
movl $100000, %r14d
leaq .LC5(%rip), %r15
leaq .L52(%rip), %r13
jmp .L49
.L53:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
.L49:
movq %r15, %rdx
movq %rbp, %rsi
movl %r12d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L212
subl $98, %eax
cmpl $16, %eax
ja .L49
movl %eax, %eax
movslq 0(%r13,%rax,4), %rax
addq %r13, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L52:
.long .L57-.L52
.long .L49-.L52
.long .L56-.L52
.long .L49-.L52
.long .L49-.L52
.long .L49-.L52
.long .L49-.L52
.long .L55-.L52
.long .L49-.L52
.long .L49-.L52
.long .L164-.L52
.long .L53-.L52
.long .L49-.L52
.long .L49-.L52
.long .L49-.L52
.long .L49-.L52
.long .L51-.L52
.text
.L57:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, (%rsp)
jmp .L49
.L55:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r14d
jmp .L49
.L51:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
jmp .L49
.L56:
movl $1, 8(%rsp)
jmp .L49
.L164:
movl $1, 12(%rsp)
jmp .L49
.L212:
cmpl $1024, %ebx
jle .L165
movl $16, %ecx
movl %ebx, %eax
cltd
idivl %ecx
movl %eax, %r12d
movl $16, %ebp
.L59:
cmpl $1, (%rsp)
jbe .L213
.L60:
movl (%rsp), %eax
cmpl $5, %eax
ja .L61
movl %eax, %eax
leaq .L63(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L63:
.long .L68-.L63
.long .L67-.L63
.long .L66-.L63
.long .L65-.L63
.long .L64-.L63
.long .L62-.L63
.text
.L165:
movl %ebx, %r12d
movl $1, %ebp
jmp .L59
.L213:
movl $0, %edi
call cudaFree@PLT
movl %eax, %edi
movl $143, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
jmp .L60
.L68:
movslq %ebx, %rax
leaq 0(,%rax,8), %r13
leaq 24(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $146, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
testl %ebx, %ebx
jle .L69
movl $0, %eax
.L70:
movq 24(%rsp), %rdx
movq $1, (%rdx,%rax)
addq $8, %rax
cmpq %rax, %r13
jne .L70
.L69:
cmpl $0, 4(%rsp)
je .L71
leaq 40(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $154, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %eax
jmp .L72
.L73:
movq 40(%rsp), %rdx
movq $5, (%rdx,%rax,8)
addq $1, %rax
.L72:
cmpl %eax, %ebx
jg .L73
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq .LC6(%rip), %rbx
jmp .L74
.L75:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $160, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, (%rsp)
.L74:
movl (%rsp), %eax
cmpl %eax, %r14d
jle .L214
movl %r12d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L75
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z10readKernelPmS_PmS_
jmp .L75
.L214:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
.L77:
call cudaGetLastError@PLT
movl %eax, %edi
movl $176, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC7(%rip), %xmm1
divsd %xmm1, %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
cmpl $1, 4(%rsp)
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rax
cmove %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
.L82:
call cudaDeviceReset@PLT
.L61:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L215
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 4(%rsp), %r13d
leaq .LC6(%rip), %r15
jmp .L78
.L79:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $171, %edx
movq %r15, %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, %r13d
.L78:
cmpl %r13d, %r14d
jle .L216
movl %r12d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L79
movq 24(%rsp), %rdi
call _Z31__device_stub__Z11writeKernelPmPm
jmp .L79
.L216:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %ebx, %esi
movq 24(%rsp), %rdi
call _Z6verifyPmi
jmp .L77
.L67:
movslq %ebx, %r13
salq $3, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L83
leaq 0(%r13,%rax), %rdx
.L84:
movq $1, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L84
.L83:
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $191, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $4, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $192, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpl $0, 4(%rsp)
je .L85
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $197, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L217
.L86:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $199, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %ebx
leaq .LC6(%rip), %r13
jmp .L87
.L217:
movl %ebx, %esi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z15initCudaMallocdPmiPmi
jmp .L86
.L88:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $203, %edx
movq %r13, %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, %ebx
.L87:
cmpl %ebx, %r14d
jle .L218
movl %r12d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L88
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z10readKernelPmS_PmS_
jmp .L88
.L218:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.L90:
call cudaGetLastError@PLT
movl %eax, %edi
movl $221, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC7(%rip), %xmm1
divsd %xmm1, %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
cmpl $1, 4(%rsp)
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rax
cmove %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
jmp .L82
.L85:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 4(%rsp), %ebx
leaq .LC6(%rip), %r13
jmp .L91
.L92:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $215, %edx
movq %r13, %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, %ebx
.L91:
cmpl %ebx, %r14d
jle .L219
movl %r12d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L92
movq 32(%rsp), %rdi
call _Z31__device_stub__Z11writeKernelPmPm
jmp .L92
.L219:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L90
.L66:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %r14d, %r14d
jle .L95
movl $0, %ebx
leaq .LC6(%rip), %r13
jmp .L97
.L96:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $234, %edx
movq %r13, %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, %ebx
cmpl %ebx, %r14d
je .L95
.L97:
movl %r12d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L96
movl $0, %edi
call _Z30__device_stub__Z10nullKernelPiPi
jmp .L96
.L95:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
call cudaGetLastError@PLT
movl %eax, %edi
movl $237, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC7(%rip), %xmm1
divsd %xmm1, %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L61
.L65:
movslq %ebx, %rax
leaq 0(,%rax,8), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
cmpl $0, 8(%rsp)
jne .L99
cmpl $0, 12(%rsp)
jne .L220
.L100:
cmpl $0, 4(%rsp)
jne .L168
cmpl $7, %ebx
jg .L112
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
addq %rbp, %r12
jmp .L113
.L220:
movq %r12, %rsi
movq %rax, %rdi
call mlock@PLT
jmp .L100
.L103:
movq $5, 0(%rbp,%rax,8)
addq $1, %rax
.L101:
cmpl %eax, %ebx
jg .L103
cmpl $7, %ebx
jg .L104
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 8(%rsp), %edx
jmp .L105
.L168:
movl $0, %eax
jmp .L101
.L106:
addl $1, %eax
cmpl %eax, %ebx
jne .L106
.L108:
addl $1, %edx
.L105:
cmpl %edx, %r14d
jle .L107
movl 8(%rsp), %eax
testl %ebx, %ebx
jg .L106
jmp .L108
.L107:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
.L109:
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC7(%rip), %xmm2
divsd %xmm2, %xmm1
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
cmpl $1, 4(%rsp)
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rax
cmove %rax, %rdx
jmp .L120
.L104:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 8(%rsp), %edx
jmp .L110
.L222:
addl $1, %edx
.L110:
cmpl %edx, %r14d
jle .L221
movl 8(%rsp), %eax
.L111:
addl $8, %eax
cmpl %eax, %ebx
jg .L111
jmp .L222
.L221:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L109
.L114:
movq $5, (%rax)
addq $8, %rax
cmpq %r12, %rax
jne .L114
.L116:
addl $1, 4(%rsp)
.L113:
movl 4(%rsp), %eax
cmpl %eax, %r14d
jle .L115
movq %rbp, %rax
testl %ebx, %ebx
jg .L114
jmp .L116
.L115:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
.L117:
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC7(%rip), %xmm2
divsd %xmm2, %xmm1
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
leaq .LC4(%rip), %rdx
.L120:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L99:
movl %ebx, %esi
movq %rbp, %rdi
call _Z6verifyPmi
movq %rbp, %rdi
call free@PLT
jmp .L61
.L112:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leal -1(%rbx), %edx
shrl $3, %edx
addl $1, %edx
movl %edx, %edx
salq $6, %rdx
addq %rbp, %rdx
jmp .L118
.L224:
addl $1, 4(%rsp)
.L118:
movl 4(%rsp), %eax
cmpl %eax, %r14d
jle .L223
movq %rbp, %rax
.L119:
movq $5, (%rax)
movq $5, 8(%rax)
movq $5, 16(%rax)
movq $5, 24(%rax)
movq $5, 32(%rax)
movq $5, 40(%rax)
movq $5, 48(%rax)
movq $5, 56(%rax)
addq $64, %rax
cmpq %rdx, %rax
jne .L119
jmp .L224
.L223:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L117
.L64:
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $322, %edx
leaq .LC6(%rip), %r12
movq %r12, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $8, %edi
call cudaSetDeviceFlags@PLT
movl %eax, %edi
movl $323, %edx
movq %r12, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %edi
call cudaFree@PLT
movl %eax, %edi
movl $324, %edx
movq %r12, %rsi
call _ZL11HandleError9cudaErrorPKci
movslq %ebx, %rbp
salq $3, %rbp
leaq 48(%rsp), %rdi
movl $2, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $325, %edx
movq %r12, %rsi
call _ZL11HandleError9cudaErrorPKci
cmpl $0, 8(%rsp)
jne .L121
cmpl $0, 4(%rsp)
jne .L174
cmpl $7, %ebx
jg .L133
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L134
.L124:
movq 48(%rsp), %rdx
movq $5, (%rdx,%rax,8)
addq $1, %rax
.L122:
cmpl %eax, %ebx
jg .L124
cmpl $7, %ebx
jg .L125
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 8(%rsp), %edx
jmp .L126
.L174:
movl $0, %eax
jmp .L122
.L127:
addl $1, %eax
cmpl %eax, %ebx
jne .L127
.L129:
addl $1, %edx
.L126:
cmpl %edx, %r14d
jle .L128
movl 8(%rsp), %eax
testl %ebx, %ebx
jg .L127
jmp .L129
.L128:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
.L130:
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC7(%rip), %xmm2
divsd %xmm2, %xmm1
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
cmpl $1, 4(%rsp)
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rax
cmove %rax, %rdx
jmp .L141
.L125:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 8(%rsp), %edx
jmp .L131
.L226:
addl $1, %edx
.L131:
cmpl %edx, %r14d
jle .L225
movl 8(%rsp), %eax
.L132:
addl $8, %eax
cmpl %eax, %ebx
jg .L132
jmp .L226
.L225:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L130
.L135:
movq 48(%rsp), %rdx
movq $5, (%rdx,%rax)
addq $8, %rax
cmpq %rax, %rbp
jne .L135
.L137:
addl $1, 4(%rsp)
.L134:
movl 4(%rsp), %eax
cmpl %eax, %r14d
jle .L136
movl $0, %eax
testl %ebx, %ebx
jg .L135
jmp .L137
.L136:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
.L138:
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC7(%rip), %xmm2
divsd %xmm2, %xmm1
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
leaq .LC4(%rip), %rdx
.L141:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L121:
movl %ebx, %esi
movq 48(%rsp), %rdi
call _Z6verifyPmi
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
jmp .L61
.L133:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leal -1(%rbx), %ecx
shrl $3, %ecx
addl $1, %ecx
movl %ecx, %ecx
salq $6, %rcx
jmp .L139
.L228:
addl $1, 4(%rsp)
.L139:
movl 4(%rsp), %eax
cmpl %eax, %r14d
jle .L227
movl $0, %eax
.L140:
movq 48(%rsp), %rdx
movq $5, (%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 8(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 16(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 24(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 32(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 40(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 48(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 56(%rdx,%rax)
addq $64, %rax
cmpq %rcx, %rax
jne .L140
jmp .L228
.L227:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L138
.L62:
movslq %ebx, %rbp
salq $3, %rbp
leaq 48(%rsp), %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $401, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
cmpl $0, 8(%rsp)
jne .L142
cmpl $0, 4(%rsp)
jne .L180
cmpl $7, %ebx
jg .L154
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L155
.L145:
movq 48(%rsp), %rdx
movq $5, (%rdx,%rax,8)
addq $1, %rax
.L143:
cmpl %eax, %ebx
jg .L145
cmpl $7, %ebx
jg .L146
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 8(%rsp), %edx
jmp .L147
.L180:
movl $0, %eax
jmp .L143
.L148:
addl $1, %eax
cmpl %eax, %ebx
jne .L148
.L150:
addl $1, %edx
.L147:
cmpl %edx, %r14d
jle .L149
movl 8(%rsp), %eax
testl %ebx, %ebx
jg .L148
jmp .L150
.L149:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
.L151:
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC7(%rip), %xmm2
divsd %xmm2, %xmm1
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
cmpl $1, 4(%rsp)
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rax
cmove %rax, %rdx
jmp .L162
.L146:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 8(%rsp), %edx
jmp .L152
.L230:
addl $1, %edx
.L152:
cmpl %edx, %r14d
jle .L229
movl 8(%rsp), %eax
.L153:
addl $8, %eax
cmpl %eax, %ebx
jg .L153
jmp .L230
.L229:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L151
.L156:
movq 48(%rsp), %rdx
movq $5, (%rdx,%rax)
addq $8, %rax
cmpq %rax, %rbp
jne .L156
.L158:
addl $1, 4(%rsp)
.L155:
movl 4(%rsp), %eax
cmpl %eax, %r14d
jle .L157
movl $0, %eax
testl %ebx, %ebx
jg .L156
jmp .L158
.L157:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
.L159:
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC7(%rip), %xmm2
divsd %xmm2, %xmm1
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
leaq .LC4(%rip), %rdx
.L162:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L142:
movl %ebx, %esi
movq 48(%rsp), %rdi
call _Z6verifyPmi
movq 48(%rsp), %rdi
call cudaFree@PLT
jmp .L61
.L154:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leal -1(%rbx), %ecx
shrl $3, %ecx
addl $1, %ecx
movl %ecx, %ecx
salq $6, %rcx
jmp .L160
.L232:
addl $1, 4(%rsp)
.L160:
movl 4(%rsp), %eax
cmpl %eax, %r14d
jle .L231
movl $0, %eax
.L161:
movq 48(%rsp), %rdx
movq $5, (%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 8(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 16(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 24(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 32(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 40(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 48(%rdx,%rax)
movq 48(%rsp), %rdx
movq $5, 56(%rdx,%rax)
addq $64, %rax
cmpq %rcx, %rax
jne .L161
jmp .L232
.L231:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L159
.L215:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size main, .-main
.globl _Z38__device_stub__Z17verifyCudaMallocdPmiPmi
.type _Z38__device_stub__Z17verifyCudaMallocdPmiPmi, @function
_Z38__device_stub__Z17verifyCudaMallocdPmiPmi:
.LFB2106:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L237
.L233:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L238
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L237:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17verifyCudaMallocdPmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L233
.L238:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z38__device_stub__Z17verifyCudaMallocdPmiPmi, .-_Z38__device_stub__Z17verifyCudaMallocdPmiPmi
.globl _Z17verifyCudaMallocdPmi
.type _Z17verifyCudaMallocdPmi, @function
_Z17verifyCudaMallocdPmi:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z17verifyCudaMallocdPmiPmi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z17verifyCudaMallocdPmi, .-_Z17verifyCudaMallocdPmi
.section .rodata.str1.1
.LC14:
.string "_Z17verifyCudaMallocdPmi"
.LC15:
.string "_Z15initCudaMallocdPmi"
.LC16:
.string "_Z10nullKernelPi"
.LC17:
.string "_Z11writeKernelPm"
.LC18:
.string "_Z10readKernelPmS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2109:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z17verifyCudaMallocdPmi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z15initCudaMallocdPmi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z10nullKernelPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z11writeKernelPm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z10readKernelPmS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
#include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <stdlib.h>
#include <sys/mman.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
inline double diff_s(struct timeval start, struct timeval end)
{
return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}
__global__ void readKernel(uint64_t *memory, uint64_t *memoryToRead)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
//memory[tid]=memoryToRead[tid];
//__shared__ uint64_t temp;
uint64_t temp = memoryToRead[tid];
if(!temp)
__syncthreads();
}
__global__ void writeKernel(uint64_t *memory)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
memory[tid]=5;
}
__global__ void nullKernel(int *memory)
{
}
__global__ void initCudaMallocd(uint64_t *memory, int N)
{
int tid =threadIdx.x;
if(tid==0){
for(int k=0;k< N ;k++)
memory[k]=5;
}
}
void verify(uint64_t* memory, int N)
{
int error = 0;
for(int i =0; i<N; i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(uint64_t* memory, int N)
{
int tid=threadIdx.x;
if(tid==0) {
int error = 0;
for(int i =0; i<N; i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
}
int
main( int argc, char *argv[] )
{
uint64_t *hostAllocd, *cudaMallocd, *cpuMallocd;
int ITERATIONS = 100000;
int numBytes = 1;
struct timeval tv1, tv2;
int opt;
int read=0; //read benchmark? or write?
int benchmarkType = 0;
int locked = 0; //mlock data?
int dryRun = 0; //dry run to measure noise TLB misses/...etc
while ((opt = getopt(argc, argv, "m:b:i:r:ld")) != -1) {
switch (opt) {
case 'm':
numBytes = atoi(optarg);
//assert(numBytes%16 == 0 && numBytes<=1024);
break;
case 'b':
benchmarkType = atoi(optarg);
break;
case 'i':
ITERATIONS = atoi(optarg);
break;
case 'r':
read = atoi(optarg);
break;
case 'l':
locked = 1;
break;
case 'd':
dryRun = 1;
break;
default: /* '?' */
break;
}
}
int num_of_blocks=1;
int num_of_threads_per_block=numBytes;
if(numBytes>1024){
num_of_blocks = 16;
num_of_threads_per_block = numBytes/16;
}
if(benchmarkType == 0 || benchmarkType == 1)
HANDLE_ERROR(cudaFree(0));
switch (benchmarkType) {
case 0: {//read/Write to hostAlloc'd data
HANDLE_ERROR( cudaHostAlloc( &hostAllocd, sizeof(uint64_t)*numBytes, 0 ) );
for(int k=0;k< numBytes ;k++){
hostAllocd[k]=1;
}
if(read)
{
uint64_t *memoryToRead;
HANDLE_ERROR( cudaHostAlloc( &memoryToRead, sizeof(uint64_t)*numBytes, 0 ) );
for(int k=0;k< numBytes ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFreeHost(memoryToRead);
//verify(hostAllocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
verify(hostAllocd,numBytes);
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("HostAlloc [%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
cudaFreeHost(hostAllocd);
break;
}
case 1: {//read/Write to cudaMalloc'd data
cpuMallocd = (uint64_t *)malloc(sizeof(uint64_t)*numBytes);
assert(cpuMallocd);
for(int k=0;k< numBytes ;k++){
cpuMallocd[k]=1;
}
HANDLE_ERROR( cudaMalloc( &cudaMallocd, sizeof(uint64_t)*numBytes) );
HANDLE_ERROR( cudaMemcpy( cudaMallocd,cpuMallocd, sizeof(uint64_t)*numBytes,cudaMemcpyDefault) );
if(read)
{
uint64_t *memoryToRead;
HANDLE_ERROR( cudaMalloc( &memoryToRead, sizeof(uint64_t)*numBytes ) );
initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
HANDLE_ERROR( cudaDeviceSynchronize());
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFree(memoryToRead);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("CudaMalloc [%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
free(cpuMallocd);
cudaFree(cudaMallocd);
break;
}
case 2:
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 3: {//read/Write to cpu mallocd data
uint64_t *memory_to_access = (uint64_t *)malloc(sizeof(uint64_t)*numBytes );
if(!dryRun) {
if(locked)
mlock(memory_to_access,sizeof(uint64_t)*numBytes);
assert(memory_to_access);
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu malloc [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
free(memory_to_access);
break;
}
case 4: {//read/Write to cpu but hostsllocd data
uint64_t *memory_to_access;
HANDLE_ERROR(cudaSetDevice(0));
HANDLE_ERROR(cudaSetDeviceFlags(cudaDeviceMapHost));
HANDLE_ERROR(cudaFree(0));
HANDLE_ERROR(cudaHostAlloc(&memory_to_access,sizeof(uint64_t)*numBytes,cudaHostAllocMapped));
if(!dryRun) {
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu hostAlloc [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
cudaFreeHost(memory_to_access);
break;
}
case 5: {//read/Write to cpu but mallocManaged data
uint64_t *memory_to_access;
HANDLE_ERROR(cudaMallocManaged(&memory_to_access,sizeof(uint64_t)*numBytes));
if(!dryRun) {
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu mallocManaged [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
cudaFree(memory_to_access);
break;
}
}
if(benchmarkType == 0 || benchmarkType == 1)
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdint.h>
#include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <stdlib.h>
#include <sys/mman.h>
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
inline double diff_s(struct timeval start, struct timeval end)
{
return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}
__global__ void readKernel(uint64_t *memory, uint64_t *memoryToRead)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
//memory[tid]=memoryToRead[tid];
//__shared__ uint64_t temp;
uint64_t temp = memoryToRead[tid];
if(!temp)
__syncthreads();
}
__global__ void writeKernel(uint64_t *memory)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
memory[tid]=5;
}
__global__ void nullKernel(int *memory)
{
}
__global__ void initCudaMallocd(uint64_t *memory, int N)
{
int tid =threadIdx.x;
if(tid==0){
for(int k=0;k< N ;k++)
memory[k]=5;
}
}
void verify(uint64_t* memory, int N)
{
int error = 0;
for(int i =0; i<N; i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(uint64_t* memory, int N)
{
int tid=threadIdx.x;
if(tid==0) {
int error = 0;
for(int i =0; i<N; i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
}
int
main( int argc, char *argv[] )
{
uint64_t *hostAllocd, *cudaMallocd, *cpuMallocd;
int ITERATIONS = 100000;
int numBytes = 1;
struct timeval tv1, tv2;
int opt;
int read=0; //read benchmark? or write?
int benchmarkType = 0;
int locked = 0; //mlock data?
int dryRun = 0; //dry run to measure noise TLB misses/...etc
while ((opt = getopt(argc, argv, "m:b:i:r:ld")) != -1) {
switch (opt) {
case 'm':
numBytes = atoi(optarg);
//assert(numBytes%16 == 0 && numBytes<=1024);
break;
case 'b':
benchmarkType = atoi(optarg);
break;
case 'i':
ITERATIONS = atoi(optarg);
break;
case 'r':
read = atoi(optarg);
break;
case 'l':
locked = 1;
break;
case 'd':
dryRun = 1;
break;
default: /* '?' */
break;
}
}
int num_of_blocks=1;
int num_of_threads_per_block=numBytes;
if(numBytes>1024){
num_of_blocks = 16;
num_of_threads_per_block = numBytes/16;
}
if(benchmarkType == 0 || benchmarkType == 1)
HANDLE_ERROR(hipFree(0));
switch (benchmarkType) {
case 0: {//read/Write to hostAlloc'd data
HANDLE_ERROR( hipHostAlloc( &hostAllocd, sizeof(uint64_t)*numBytes, 0 ) );
for(int k=0;k< numBytes ;k++){
hostAllocd[k]=1;
}
if(read)
{
uint64_t *memoryToRead;
HANDLE_ERROR( hipHostAlloc( &memoryToRead, sizeof(uint64_t)*numBytes, 0 ) );
for(int k=0;k< numBytes ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
hipHostFree(memoryToRead);
//verify(hostAllocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
verify(hostAllocd,numBytes);
}
HANDLE_ERROR( hipGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("HostAlloc [%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
hipHostFree(hostAllocd);
break;
}
case 1: {//read/Write to cudaMalloc'd data
cpuMallocd = (uint64_t *)malloc(sizeof(uint64_t)*numBytes);
assert(cpuMallocd);
for(int k=0;k< numBytes ;k++){
cpuMallocd[k]=1;
}
HANDLE_ERROR( hipMalloc( &cudaMallocd, sizeof(uint64_t)*numBytes) );
HANDLE_ERROR( hipMemcpy( cudaMallocd,cpuMallocd, sizeof(uint64_t)*numBytes,hipMemcpyDefault) );
if(read)
{
uint64_t *memoryToRead;
HANDLE_ERROR( hipMalloc( &memoryToRead, sizeof(uint64_t)*numBytes ) );
initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
HANDLE_ERROR( hipDeviceSynchronize());
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
hipFree(memoryToRead);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
HANDLE_ERROR( hipGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("CudaMalloc [%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
free(cpuMallocd);
hipFree(cudaMallocd);
break;
}
case 2:
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
HANDLE_ERROR( hipGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 3: {//read/Write to cpu mallocd data
uint64_t *memory_to_access = (uint64_t *)malloc(sizeof(uint64_t)*numBytes );
if(!dryRun) {
if(locked)
mlock(memory_to_access,sizeof(uint64_t)*numBytes);
assert(memory_to_access);
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu malloc [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
free(memory_to_access);
break;
}
case 4: {//read/Write to cpu but hostsllocd data
uint64_t *memory_to_access;
HANDLE_ERROR(hipSetDevice(0));
HANDLE_ERROR(hipSetDeviceFlags(hipDeviceMapHost));
HANDLE_ERROR(hipFree(0));
HANDLE_ERROR(hipHostAlloc(&memory_to_access,sizeof(uint64_t)*numBytes,hipHostMallocMapped));
if(!dryRun) {
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu hostAlloc [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
hipHostFree(memory_to_access);
break;
}
case 5: {//read/Write to cpu but mallocManaged data
uint64_t *memory_to_access;
HANDLE_ERROR(hipMallocManaged(&memory_to_access,sizeof(uint64_t)*numBytes));
if(!dryRun) {
if(read)
{
for(int k=0;k< numBytes ;k++)
memory_to_access[k]=5;
uint64_t fake;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
fake += memory_to_access[j];
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
fake += memory_to_access[j];
fake += memory_to_access[j + 1];
fake += memory_to_access[j + 2];
fake += memory_to_access[j + 3];
fake += memory_to_access[j + 4];
fake += memory_to_access[j + 5];
fake += memory_to_access[j + 6];
fake += memory_to_access[j + 7];
}
}
gettimeofday(&tv2, NULL);
}
}
else
{
uint64_t fake=5;
if(numBytes<8) {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j++) {
memory_to_access[j] = fake;
}
}
gettimeofday(&tv2, NULL);
}
else {
gettimeofday(&tv1, NULL);
for(int i=0; i<ITERATIONS; i++) {
for (int j = 0; j < (numBytes); j += 8) {
memory_to_access[j] = fake;
memory_to_access[j + 1] = fake;
memory_to_access[j + 2] = fake;
memory_to_access[j + 3] = fake;
memory_to_access[j + 4] = fake;
memory_to_access[j + 5] = fake;
memory_to_access[j + 6] = fake;
memory_to_access[j + 7] = fake;
}
}
gettimeofday(&tv2, NULL);
}
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("cpu mallocManaged [%s] Latency = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
// printf("Press enter to continue...\n");
// getchar();
verify(memory_to_access,numBytes);
hipFree(memory_to_access);
break;
}
}
if(benchmarkType == 0 || benchmarkType == 1)
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void matrixTransposeSqr(double *P, double* M, int width, int height)
{
unsigned int xIdx = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int yIdx = blockDim.y * blockIdx.y + threadIdx.y;
if (xIdx < width && yIdx < height)
{
unsigned int inIdx = xIdx + width * yIdx;
unsigned int outIdx= yIdx + height * xIdx;
P[outIdx] = M[inIdx];
}
} | code for sm_80
Function : _Z18matrixTransposeSqrPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void matrixTransposeSqr(double *P, double* M, int width, int height)
{
unsigned int xIdx = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int yIdx = blockDim.y * blockIdx.y + threadIdx.y;
if (xIdx < width && yIdx < height)
{
unsigned int inIdx = xIdx + width * yIdx;
unsigned int outIdx= yIdx + height * xIdx;
P[outIdx] = M[inIdx];
}
} | .file "tmpxft_000955aa_00000000-6_matrixTransposeSqr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii
.type _Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii, @function
_Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18matrixTransposeSqrPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii, .-_Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii
.globl _Z18matrixTransposeSqrPdS_ii
.type _Z18matrixTransposeSqrPdS_ii, @function
_Z18matrixTransposeSqrPdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18matrixTransposeSqrPdS_ii, .-_Z18matrixTransposeSqrPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18matrixTransposeSqrPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrixTransposeSqrPdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void matrixTransposeSqr(double *P, double* M, int width, int height)
{
unsigned int xIdx = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int yIdx = blockDim.y * blockIdx.y + threadIdx.y;
if (xIdx < width && yIdx < height)
{
unsigned int inIdx = xIdx + width * yIdx;
unsigned int outIdx= yIdx + height * xIdx;
P[outIdx] = M[inIdx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void matrixTransposeSqr(double *P, double* M, int width, int height)
{
unsigned int xIdx = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int yIdx = blockDim.y * blockIdx.y + threadIdx.y;
if (xIdx < width && yIdx < height)
{
unsigned int inIdx = xIdx + width * yIdx;
unsigned int outIdx= yIdx + height * xIdx;
P[outIdx] = M[inIdx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void matrixTransposeSqr(double *P, double* M, int width, int height)
{
unsigned int xIdx = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int yIdx = blockDim.y * blockIdx.y + threadIdx.y;
if (xIdx < width && yIdx < height)
{
unsigned int inIdx = xIdx + width * yIdx;
unsigned int outIdx= yIdx + height * xIdx;
P[outIdx] = M[inIdx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixTransposeSqrPdS_ii
.globl _Z18matrixTransposeSqrPdS_ii
.p2align 8
.type _Z18matrixTransposeSqrPdS_ii,@function
_Z18matrixTransposeSqrPdS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mad_u64_u32 v[6:7], null, v0, s5, v[1:2]
v_mov_b32_e32 v7, v3
v_lshlrev_b64 v[0:1], 3, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[4:5], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matrixTransposeSqrPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matrixTransposeSqrPdS_ii, .Lfunc_end0-_Z18matrixTransposeSqrPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matrixTransposeSqrPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matrixTransposeSqrPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void matrixTransposeSqr(double *P, double* M, int width, int height)
{
unsigned int xIdx = blockDim.x * blockIdx.x + threadIdx.x;
unsigned int yIdx = blockDim.y * blockIdx.y + threadIdx.y;
if (xIdx < width && yIdx < height)
{
unsigned int inIdx = xIdx + width * yIdx;
unsigned int outIdx= yIdx + height * xIdx;
P[outIdx] = M[inIdx];
}
} | .text
.file "matrixTransposeSqr.hip"
.globl _Z33__device_stub__matrixTransposeSqrPdS_ii # -- Begin function _Z33__device_stub__matrixTransposeSqrPdS_ii
.p2align 4, 0x90
.type _Z33__device_stub__matrixTransposeSqrPdS_ii,@function
_Z33__device_stub__matrixTransposeSqrPdS_ii: # @_Z33__device_stub__matrixTransposeSqrPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matrixTransposeSqrPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__matrixTransposeSqrPdS_ii, .Lfunc_end0-_Z33__device_stub__matrixTransposeSqrPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrixTransposeSqrPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matrixTransposeSqrPdS_ii,@object # @_Z18matrixTransposeSqrPdS_ii
.section .rodata,"a",@progbits
.globl _Z18matrixTransposeSqrPdS_ii
.p2align 3, 0x0
_Z18matrixTransposeSqrPdS_ii:
.quad _Z33__device_stub__matrixTransposeSqrPdS_ii
.size _Z18matrixTransposeSqrPdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matrixTransposeSqrPdS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrixTransposeSqrPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrixTransposeSqrPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18matrixTransposeSqrPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixTransposeSqrPdS_ii
.globl _Z18matrixTransposeSqrPdS_ii
.p2align 8
.type _Z18matrixTransposeSqrPdS_ii,@function
_Z18matrixTransposeSqrPdS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mad_u64_u32 v[6:7], null, v0, s5, v[1:2]
v_mov_b32_e32 v7, v3
v_lshlrev_b64 v[0:1], 3, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[4:5], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matrixTransposeSqrPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matrixTransposeSqrPdS_ii, .Lfunc_end0-_Z18matrixTransposeSqrPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matrixTransposeSqrPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matrixTransposeSqrPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000955aa_00000000-6_matrixTransposeSqr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii
.type _Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii, @function
_Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18matrixTransposeSqrPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii, .-_Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii
.globl _Z18matrixTransposeSqrPdS_ii
.type _Z18matrixTransposeSqrPdS_ii, @function
_Z18matrixTransposeSqrPdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18matrixTransposeSqrPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18matrixTransposeSqrPdS_ii, .-_Z18matrixTransposeSqrPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18matrixTransposeSqrPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrixTransposeSqrPdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixTransposeSqr.hip"
.globl _Z33__device_stub__matrixTransposeSqrPdS_ii # -- Begin function _Z33__device_stub__matrixTransposeSqrPdS_ii
.p2align 4, 0x90
.type _Z33__device_stub__matrixTransposeSqrPdS_ii,@function
_Z33__device_stub__matrixTransposeSqrPdS_ii: # @_Z33__device_stub__matrixTransposeSqrPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matrixTransposeSqrPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__matrixTransposeSqrPdS_ii, .Lfunc_end0-_Z33__device_stub__matrixTransposeSqrPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrixTransposeSqrPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matrixTransposeSqrPdS_ii,@object # @_Z18matrixTransposeSqrPdS_ii
.section .rodata,"a",@progbits
.globl _Z18matrixTransposeSqrPdS_ii
.p2align 3, 0x0
_Z18matrixTransposeSqrPdS_ii:
.quad _Z33__device_stub__matrixTransposeSqrPdS_ii
.size _Z18matrixTransposeSqrPdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matrixTransposeSqrPdS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrixTransposeSqrPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrixTransposeSqrPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/inner_product.h>
int main(void)
{
float vec1[3] = {1.0f, 2.0f, 5.0f};
float vec2[3] = {4.0f, 1.0f, 5.0f};
float result = thrust::inner_product(vec1, vec1 + 3, vec2, 0.0f, thrust::plus<float>(), thrust::multiplies<float>());
// print the sum
std::cout << "reulst is " << result << std::endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/inner_product.h>
int main(void)
{
float vec1[3] = {1.0f, 2.0f, 5.0f};
float vec2[3] = {4.0f, 1.0f, 5.0f};
float result = thrust::inner_product(vec1, vec1 + 3, vec2, 0.0f, thrust::plus<float>(), thrust::multiplies<float>());
// print the sum
std::cout << "reulst is " << result << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/inner_product.h>
int main(void)
{
float vec1[3] = {1.0f, 2.0f, 5.0f};
float vec2[3] = {4.0f, 1.0f, 5.0f};
float result = thrust::inner_product(vec1, vec1 + 3, vec2, 0.0f, thrust::plus<float>(), thrust::multiplies<float>());
// print the sum
std::cout << "reulst is " << result << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/inner_product.h>
int main(void)
{
float vec1[3] = {1.0f, 2.0f, 5.0f};
float vec2[3] = {4.0f, 1.0f, 5.0f};
float result = thrust::inner_product(vec1, vec1 + 3, vec2, 0.0f, thrust::plus<float>(), thrust::multiplies<float>());
// print the sum
std::cout << "reulst is " << result << std::endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/inner_product.h>
int main(void)
{
float vec1[3] = {1.0f, 2.0f, 5.0f};
float vec2[3] = {4.0f, 1.0f, 5.0f};
float result = thrust::inner_product(vec1, vec1 + 3, vec2, 0.0f, thrust::plus<float>(), thrust::multiplies<float>());
// print the sum
std::cout << "reulst is " << result << std::endl;
return 0;
} | .text
.file "inner_product.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4611686019492741120, %rax # imm = 0x400000003F800000
movq %rax, 28(%rsp)
movl $1084227584, 36(%rsp) # imm = 0x40A00000
movabsq $4575657222490554368, %rax # imm = 0x3F80000040800000
movq %rax, 16(%rsp)
movl $1084227584, 24(%rsp) # imm = 0x40A00000
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movss 28(%rsp,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss 16(%rsp,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $12, %rax
jne .LBB0_1
# %bb.2: # %_ZN6thrust13inner_productIPfS1_fNS_4plusIfEENS_10multipliesIfEEEET1_T_S7_T0_S6_T2_T3_.exit
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $10, %edx
movss %xmm1, 12(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB0_6
.LBB0_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_7:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "reulst is "
.size .L.str, 11
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <iostream>
#include <fstream>
#include <sstream>
#include <vector>
#include "assert.h"
using namespace std;
std::vector<int> readFile(string filename)
{
ifstream infile (filename);
vector<int> vnum;
string line;
int index = 0;
while(getline(infile, line))
{
stringstream ss (line);
string sint;
while(getline(ss, sint, ','))
{
vnum.push_back(stoi(sint));
index += 1;
}
}
return vnum;
}
void writeFile(const char* filename, int* data, int limit)
{
ofstream myfile(filename);
if (myfile.is_open())
{
for (int i = 0; i < limit; i++)
{
myfile << data[i];
if(i!= limit-1)
myfile << ", ";
}
myfile.close();
}
else
{
printf("Unable to open/write to file %s", filename);
}
}
__global__ void q2a_global_counter(int* gpu_out, int* gpu_in, int n)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int numbersPerBlockThread = (n / (blockDim.x * gridDim.x)) + 1;
int start = idx * numbersPerBlockThread;
int stop = min(n, (start + numbersPerBlockThread));
for(int i=start; i<stop; i++)
{
int hundreds_value = gpu_in[i] / 100;
atomicAdd(&(gpu_out[hundreds_value]), 1);
}
__syncthreads();
}
__global__ void q2b_shared_mem_counter(int* gpu_out, int* gpu_in, int n)
{
extern __shared__ int shared_out[];
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int incrementalAdd = 0;
if(threadIdx.x == 0)
{
shared_out[10] = {0};
}
while(idx + incrementalAdd < n)
{
int hundreds_val = gpu_in[idx + incrementalAdd] / 100;
atomicAdd(&shared_out[hundreds_val], 1);
incrementalAdd += (blockIdx.x+1) * blockDim.x;
}
__syncthreads();
if(idx == 0)
{
for(int i=0; i < 10; i++)
{
atomicAdd(&(gpu_out[i]), shared_out[i]);
__syncthreads();
}
}
}
__global__ void q2c_prll_prfx_sum(int* gpu_out, int* gpu_in, int n)
{
// gpu_in = [510,1095,1051,1035,1063,1012,1067,1053,1053,1061]
// gpu_out =[510, 1605, 2656, 3691, 4754, 5766, 6833, 7886, 8939, 10000]
extern __shared__ int shared_mem[];
int tidx = threadIdx.x;
int idx = tidx + blockIdx.x * blockDim.x;;
int offset = 1;
int n2 = (int)pow(2.0, ceil(log((double)n)/log(2.0))); // next power of 2
if(tidx == 0)
{
for(int i=0;i<n2;i++)
{
if(i<n)
shared_mem[i] = gpu_in[i];
else
shared_mem[i] = 0; // extend non-power-of-2 entries to 0.
}
}
__syncthreads();
// UPWARD FIRST PASS SUM
for(int depth_idx = n2 >> 1; depth_idx > 0; depth_idx >>= 1)
{
__syncthreads();
if(tidx < depth_idx)
{
int ai = offset*(2*tidx+1)-1;
int bi = offset*(2*tidx+2)-1;
shared_mem[bi] += shared_mem[ai];
}
offset <<= 1;
}
__syncthreads();
// UPWARD FIRST PASS ENDS AND 2nd DOWNWARD PASS BEGINS
if(tidx == 0)
{
shared_mem[n2-1] = 0;
}
for(int depth_idx=1; depth_idx<n2; depth_idx<<=1)
{
offset >>= 1;
__syncthreads();
if(tidx < depth_idx)
{
int ai = offset*(2*tidx+1)-1;
int bi = offset*(2*tidx+2)-1;
if(ai < 0 || bi < 0)
continue;
int temp = shared_mem[ai];
shared_mem[ai] = shared_mem[bi];
shared_mem[bi] += temp;
}
}
__syncthreads();
if(idx < n)
{
gpu_out[idx] = shared_mem[idx+1];
}
}
int main(int argc, char **argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev);
cudaDeviceProp devProps;
if (cudaGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d: %s\nglobal mem: %dB; compute v%d.%d; clock: %d kHz\n",
dev, devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
printf("sharedMemPerBlock: %zu sharedMemPerMultiprocessor: %zu\n", devProps.sharedMemPerBlock, devProps.sharedMemPerMultiprocessor);
printf("regsPerMultiprocessor: %d\n", devProps.regsPerMultiprocessor);
}
vector<int> vnum = readFile("inp.txt");
// vector<int> vnum = readFile("inp1mil.txt");
const int IN_SIZE = vnum.size();
const int IN_BYTES = IN_SIZE * sizeof(int);
const int OUT_SIZE = 10; //this is specific to the output range.
const int OUT_BYTES = OUT_SIZE * sizeof(int);
int* numbers;
numbers = (int *)malloc(IN_BYTES);
for(int i=0; i < vnum.size(); i++)
numbers[i] = vnum[i];
// int MAX_THREADS_PER_BLOCK = 512;
int threads = 32;
int blocks = 8;
printf("Input size: %d blocks: %d threads: %d\n\n", IN_SIZE, blocks, threads);
int *gpu_in;
int *gpu_out_2a;
int *gpu_out_2b;
int *gpu_out_2c;
int cpu_out_2a[OUT_SIZE] = {0};
int cpu_out_2b[OUT_SIZE] = {0};
int cpu_out_2c[OUT_SIZE] = {0};
cudaError_t ret;
float elapsedTime_2a;
float elapsedTime_2b;
float elapsedTime_2c;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
ret = cudaMalloc((void **) &gpu_in, IN_BYTES);
printf("gpu_in Malloc %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
ret = cudaMalloc((void **) &gpu_out_2a, OUT_BYTES);
printf("gpu_out_2a Malloc %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
ret = cudaMalloc((void **) &gpu_out_2b, OUT_BYTES);
printf("gpu_out_2b Malloc %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
ret = cudaMalloc((void **) &gpu_out_2c, OUT_BYTES);
printf("gpu_out_2c Malloc %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
ret = cudaMemcpy((void *)gpu_in, (void *)numbers, IN_BYTES , cudaMemcpyHostToDevice);
printf("gpu_in Memcpy %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
// see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#execution-configuration
// for <<<Dg, Db, Ns, S>>> parameter explanation.
cudaEventRecord(start, 0);
q2a_global_counter<<<blocks, threads>>>(gpu_out_2a, gpu_in, IN_SIZE);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime_2a, start, stop);
cudaEventRecord(start, 0);
q2b_shared_mem_counter<<<blocks, threads, OUT_SIZE*sizeof(int)>>>(gpu_out_2b, gpu_in, IN_SIZE);
// ret = cudaPeekAtLastError();
// printf("cudaPeekAtLastError %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime_2b, start, stop);
cudaEventRecord(start, 0);
int n2 = (int)pow(2.0, ceil(log((double)OUT_SIZE)/log(2.0))); // next power of 2
q2c_prll_prfx_sum<<<blocks, threads, (n2)*sizeof(int)>>>(gpu_out_2c, gpu_out_2a, OUT_SIZE);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime_2c, start, stop);
ret = cudaMemcpy(cpu_out_2a, gpu_out_2a, OUT_BYTES, cudaMemcpyDeviceToHost);
printf("cpu_out_2a Memcpy %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
ret = cudaMemcpy(cpu_out_2b, gpu_out_2b, OUT_BYTES, cudaMemcpyDeviceToHost);
printf("cpu_out_2b Memcpy %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
ret = cudaMemcpy(cpu_out_2c, gpu_out_2c, OUT_BYTES, cudaMemcpyDeviceToHost);
printf("cpu_out_2c Memcpy %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
// correct output:
// 2a & b): 510, 1095, 1051, 1035, 1063, 1012, 1067, 1053, 1053, 1061
// 2c) 510, 1605, 2656, 3691, 4754, 5766, 6833, 7886, 8939, 10000
printf("\n\n2a: %f\n", elapsedTime_2a);
for(int i=0;i<OUT_SIZE;i++)
{
printf("%d=%d ", i, cpu_out_2a[i]);
}
writeFile("q2a.txt", cpu_out_2a, OUT_SIZE);
printf("\n\n2b: %f\n", elapsedTime_2b);
for(int i=0;i<OUT_SIZE;i++)
{
printf("%d=%d ", i, cpu_out_2b[i]);
}
writeFile("q2b.txt", cpu_out_2b, OUT_SIZE);
printf("\n\n2c: %f\n", elapsedTime_2c);
for(int i=0;i<OUT_SIZE;i++)
{
printf("%d=%d ", i, cpu_out_2c[i]);
}
writeFile("q2c.txt", cpu_out_2c, OUT_SIZE);
printf("\n\n");
cudaFree(gpu_in);
cudaFree(gpu_out_2a);
cudaFree(gpu_out_2b);
cudaFree(gpu_out_2c);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <sstream>
#include <vector>
#include "assert.h"
using namespace std;
std::vector<int> readFile(string filename)
{
ifstream infile (filename);
vector<int> vnum;
string line;
int index = 0;
while(getline(infile, line))
{
stringstream ss (line);
string sint;
while(getline(ss, sint, ','))
{
vnum.push_back(stoi(sint));
index += 1;
}
}
return vnum;
}
void writeFile(const char* filename, int* data, int limit)
{
ofstream myfile(filename);
if (myfile.is_open())
{
for (int i = 0; i < limit; i++)
{
myfile << data[i];
if(i!= limit-1)
myfile << ", ";
}
myfile.close();
}
else
{
printf("Unable to open/write to file %s", filename);
}
}
__global__ void q2a_global_counter(int* gpu_out, int* gpu_in, int n)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int numbersPerBlockThread = (n / (blockDim.x * gridDim.x)) + 1;
int start = idx * numbersPerBlockThread;
int stop = min(n, (start + numbersPerBlockThread));
for(int i=start; i<stop; i++)
{
int hundreds_value = gpu_in[i] / 100;
atomicAdd(&(gpu_out[hundreds_value]), 1);
}
__syncthreads();
}
__global__ void q2b_shared_mem_counter(int* gpu_out, int* gpu_in, int n)
{
extern __shared__ int shared_out[];
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int incrementalAdd = 0;
if(threadIdx.x == 0)
{
shared_out[10] = {0};
}
while(idx + incrementalAdd < n)
{
int hundreds_val = gpu_in[idx + incrementalAdd] / 100;
atomicAdd(&shared_out[hundreds_val], 1);
incrementalAdd += (blockIdx.x+1) * blockDim.x;
}
__syncthreads();
if(idx == 0)
{
for(int i=0; i < 10; i++)
{
atomicAdd(&(gpu_out[i]), shared_out[i]);
__syncthreads();
}
}
}
__global__ void q2c_prll_prfx_sum(int* gpu_out, int* gpu_in, int n)
{
// gpu_in = [510,1095,1051,1035,1063,1012,1067,1053,1053,1061]
// gpu_out =[510, 1605, 2656, 3691, 4754, 5766, 6833, 7886, 8939, 10000]
extern __shared__ int shared_mem[];
int tidx = threadIdx.x;
int idx = tidx + blockIdx.x * blockDim.x;;
int offset = 1;
int n2 = (int)pow(2.0, ceil(log((double)n)/log(2.0))); // next power of 2
if(tidx == 0)
{
for(int i=0;i<n2;i++)
{
if(i<n)
shared_mem[i] = gpu_in[i];
else
shared_mem[i] = 0; // extend non-power-of-2 entries to 0.
}
}
__syncthreads();
// UPWARD FIRST PASS SUM
for(int depth_idx = n2 >> 1; depth_idx > 0; depth_idx >>= 1)
{
__syncthreads();
if(tidx < depth_idx)
{
int ai = offset*(2*tidx+1)-1;
int bi = offset*(2*tidx+2)-1;
shared_mem[bi] += shared_mem[ai];
}
offset <<= 1;
}
__syncthreads();
// UPWARD FIRST PASS ENDS AND 2nd DOWNWARD PASS BEGINS
if(tidx == 0)
{
shared_mem[n2-1] = 0;
}
for(int depth_idx=1; depth_idx<n2; depth_idx<<=1)
{
offset >>= 1;
__syncthreads();
if(tidx < depth_idx)
{
int ai = offset*(2*tidx+1)-1;
int bi = offset*(2*tidx+2)-1;
if(ai < 0 || bi < 0)
continue;
int temp = shared_mem[ai];
shared_mem[ai] = shared_mem[bi];
shared_mem[bi] += temp;
}
}
__syncthreads();
if(idx < n)
{
gpu_out[idx] = shared_mem[idx+1];
}
}
int main(int argc, char **argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
hipDeviceProp_t devProps;
if (hipGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d: %s\nglobal mem: %dB; compute v%d.%d; clock: %d kHz\n",
dev, devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
printf("sharedMemPerBlock: %zu sharedMemPerMultiprocessor: %zu\n", devProps.sharedMemPerBlock, devProps.sharedMemPerMultiprocessor);
printf("regsPerMultiprocessor: %d\n", devProps.regsPerMultiprocessor);
}
vector<int> vnum = readFile("inp.txt");
// vector<int> vnum = readFile("inp1mil.txt");
const int IN_SIZE = vnum.size();
const int IN_BYTES = IN_SIZE * sizeof(int);
const int OUT_SIZE = 10; //this is specific to the output range.
const int OUT_BYTES = OUT_SIZE * sizeof(int);
int* numbers;
numbers = (int *)malloc(IN_BYTES);
for(int i=0; i < vnum.size(); i++)
numbers[i] = vnum[i];
// int MAX_THREADS_PER_BLOCK = 512;
int threads = 32;
int blocks = 8;
printf("Input size: %d blocks: %d threads: %d\n\n", IN_SIZE, blocks, threads);
int *gpu_in;
int *gpu_out_2a;
int *gpu_out_2b;
int *gpu_out_2c;
int cpu_out_2a[OUT_SIZE] = {0};
int cpu_out_2b[OUT_SIZE] = {0};
int cpu_out_2c[OUT_SIZE] = {0};
hipError_t ret;
float elapsedTime_2a;
float elapsedTime_2b;
float elapsedTime_2c;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
ret = hipMalloc((void **) &gpu_in, IN_BYTES);
printf("gpu_in Malloc %s\n", ret == hipSuccess ? "Success!": hipGetErrorString(ret));
ret = hipMalloc((void **) &gpu_out_2a, OUT_BYTES);
printf("gpu_out_2a Malloc %s\n", ret == hipSuccess ? "Success!": hipGetErrorString(ret));
ret = hipMalloc((void **) &gpu_out_2b, OUT_BYTES);
printf("gpu_out_2b Malloc %s\n", ret == hipSuccess ? "Success!": hipGetErrorString(ret));
ret = hipMalloc((void **) &gpu_out_2c, OUT_BYTES);
printf("gpu_out_2c Malloc %s\n", ret == hipSuccess ? "Success!": hipGetErrorString(ret));
ret = hipMemcpy((void *)gpu_in, (void *)numbers, IN_BYTES , hipMemcpyHostToDevice);
printf("gpu_in Memcpy %s\n", ret == hipSuccess ? "Success!": hipGetErrorString(ret));
// see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#execution-configuration
// for <<<Dg, Db, Ns, S>>> parameter explanation.
hipEventRecord(start, 0);
q2a_global_counter<<<blocks, threads>>>(gpu_out_2a, gpu_in, IN_SIZE);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime_2a, start, stop);
hipEventRecord(start, 0);
q2b_shared_mem_counter<<<blocks, threads, OUT_SIZE*sizeof(int)>>>(gpu_out_2b, gpu_in, IN_SIZE);
// ret = cudaPeekAtLastError();
// printf("cudaPeekAtLastError %s\n", ret == cudaSuccess ? "Success!": cudaGetErrorString(ret));
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime_2b, start, stop);
hipEventRecord(start, 0);
int n2 = (int)pow(2.0, ceil(log((double)OUT_SIZE)/log(2.0))); // next power of 2
q2c_prll_prfx_sum<<<blocks, threads, (n2)*sizeof(int)>>>(gpu_out_2c, gpu_out_2a, OUT_SIZE);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime_2c, start, stop);
ret = hipMemcpy(cpu_out_2a, gpu_out_2a, OUT_BYTES, hipMemcpyDeviceToHost);
printf("cpu_out_2a Memcpy %s\n", ret == hipSuccess ? "Success!": hipGetErrorString(ret));
ret = hipMemcpy(cpu_out_2b, gpu_out_2b, OUT_BYTES, hipMemcpyDeviceToHost);
printf("cpu_out_2b Memcpy %s\n", ret == hipSuccess ? "Success!": hipGetErrorString(ret));
ret = hipMemcpy(cpu_out_2c, gpu_out_2c, OUT_BYTES, hipMemcpyDeviceToHost);
printf("cpu_out_2c Memcpy %s\n", ret == hipSuccess ? "Success!": hipGetErrorString(ret));
// correct output:
// 2a & b): 510, 1095, 1051, 1035, 1063, 1012, 1067, 1053, 1053, 1061
// 2c) 510, 1605, 2656, 3691, 4754, 5766, 6833, 7886, 8939, 10000
printf("\n\n2a: %f\n", elapsedTime_2a);
for(int i=0;i<OUT_SIZE;i++)
{
printf("%d=%d ", i, cpu_out_2a[i]);
}
writeFile("q2a.txt", cpu_out_2a, OUT_SIZE);
printf("\n\n2b: %f\n", elapsedTime_2b);
for(int i=0;i<OUT_SIZE;i++)
{
printf("%d=%d ", i, cpu_out_2b[i]);
}
writeFile("q2b.txt", cpu_out_2b, OUT_SIZE);
printf("\n\n2c: %f\n", elapsedTime_2c);
for(int i=0;i<OUT_SIZE;i++)
{
printf("%d=%d ", i, cpu_out_2c[i]);
}
writeFile("q2c.txt", cpu_out_2c, OUT_SIZE);
printf("\n\n");
hipFree(gpu_in);
hipFree(gpu_out_2a);
hipFree(gpu_out_2b);
hipFree(gpu_out_2c);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "solve_jacobi.cuh"
//#include <stdio.h>
__global__ void solve1(float* dx, float* dA, float* db, float* dnextX, int size) {
//printf("kernel launched!\n");
float sum = 0;
for (int j = 0; j < size; j++) {
if (threadIdx.x != j) {
sum += dA[threadIdx.x*size+j] * dx[j];
}
}
dnextX[threadIdx.x] = (db[threadIdx.x] - sum) / dA[threadIdx.x*size+threadIdx.x];
}
__global__ void solve2(float* dx, float* dA, float* db, float* dnextX, int size) {
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
//int A_index = tidx;
float sum = 0;
for (int j = 0; j < size; j++) {
if (tidx != j) sum += dA[tidx*size + j] * dx[j];
}
dnextX[tidx] = (db[tidx] - sum) / dA[tidx*size + tidx];
}
__global__ void solve3(float* dx, float* dA, float* db, float* dnextX, int size) {
extern __shared__ float shared_dx[];
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
//write to shared memory
for(int i=threadIdx.x; i < size; i = i+blockDim.x)
{
shared_dx[i] = dx[i];
}
__syncthreads();
float sum = 0;
for (int j = 0; j < size; j++) {
if (tidx != j) sum += dA[tidx*size + j] * shared_dx[j];
}
dnextX[tidx] = (db[tidx] - sum) / dA[tidx*size + tidx];
}
// loop unrolling 2
__global__ void solve4(float* dx, float* dA, float* db, float* dnextX, int size) {
extern __shared__ float shared_dx[];
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
//write to shared memory
for(int i=threadIdx.x; i < size; i = i+blockDim.x)
{
shared_dx[i] = dx[i];
}
__syncthreads();
float sum = 0;
for (int j = 0; j < size; j = j+2) {
if (tidx != j) sum += dA[tidx*size + j] * shared_dx[j];
if (tidx != j+1) sum += dA[tidx*size + j+1] * shared_dx[j+1];
}
dnextX[tidx] = (db[tidx] - sum) / dA[tidx*size + tidx];
}
__global__ void solve5(float* dx, float* dA, float* db, float* dnextX, int size) {
extern __shared__ float shared_dx[];
} | .file "tmpxft_00026273_00000000-6_solve_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve1PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i
.globl _Z6solve1PfS_S_S_i
.type _Z6solve1PfS_S_S_i, @function
_Z6solve1PfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6solve1PfS_S_S_i, .-_Z6solve1PfS_S_S_i
.globl _Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve2PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i
.globl _Z6solve2PfS_S_S_i
.type _Z6solve2PfS_S_S_i, @function
_Z6solve2PfS_S_S_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z6solve2PfS_S_S_i, .-_Z6solve2PfS_S_S_i
.globl _Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve3PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i
.globl _Z6solve3PfS_S_S_i
.type _Z6solve3PfS_S_S_i, @function
_Z6solve3PfS_S_S_i:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z6solve3PfS_S_S_i, .-_Z6solve3PfS_S_S_i
.globl _Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve4PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i
.globl _Z6solve4PfS_S_S_i
.type _Z6solve4PfS_S_S_i, @function
_Z6solve4PfS_S_S_i:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z6solve4PfS_S_S_i, .-_Z6solve4PfS_S_S_i
.globl _Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i:
.LFB2059:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve5PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i
.globl _Z6solve5PfS_S_S_i
.type _Z6solve5PfS_S_S_i, @function
_Z6solve5PfS_S_S_i:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z6solve5PfS_S_S_i, .-_Z6solve5PfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6solve5PfS_S_S_i"
.LC1:
.string "_Z6solve4PfS_S_S_i"
.LC2:
.string "_Z6solve3PfS_S_S_i"
.LC3:
.string "_Z6solve2PfS_S_S_i"
.LC4:
.string "_Z6solve1PfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve5PfS_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve4PfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve3PfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve2PfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve1PfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "solve_jacobi.cuh"
//#include <stdio.h>
__global__ void solve1(float* dx, float* dA, float* db, float* dnextX, int size) {
//printf("kernel launched!\n");
float sum = 0;
for (int j = 0; j < size; j++) {
if (threadIdx.x != j) {
sum += dA[threadIdx.x*size+j] * dx[j];
}
}
dnextX[threadIdx.x] = (db[threadIdx.x] - sum) / dA[threadIdx.x*size+threadIdx.x];
}
__global__ void solve2(float* dx, float* dA, float* db, float* dnextX, int size) {
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
//int A_index = tidx;
float sum = 0;
for (int j = 0; j < size; j++) {
if (tidx != j) sum += dA[tidx*size + j] * dx[j];
}
dnextX[tidx] = (db[tidx] - sum) / dA[tidx*size + tidx];
}
__global__ void solve3(float* dx, float* dA, float* db, float* dnextX, int size) {
extern __shared__ float shared_dx[];
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
//write to shared memory
for(int i=threadIdx.x; i < size; i = i+blockDim.x)
{
shared_dx[i] = dx[i];
}
__syncthreads();
float sum = 0;
for (int j = 0; j < size; j++) {
if (tidx != j) sum += dA[tidx*size + j] * shared_dx[j];
}
dnextX[tidx] = (db[tidx] - sum) / dA[tidx*size + tidx];
}
// loop unrolling 2
__global__ void solve4(float* dx, float* dA, float* db, float* dnextX, int size) {
extern __shared__ float shared_dx[];
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
//write to shared memory
for(int i=threadIdx.x; i < size; i = i+blockDim.x)
{
shared_dx[i] = dx[i];
}
__syncthreads();
float sum = 0;
for (int j = 0; j < size; j = j+2) {
if (tidx != j) sum += dA[tidx*size + j] * shared_dx[j];
if (tidx != j+1) sum += dA[tidx*size + j+1] * shared_dx[j+1];
}
dnextX[tidx] = (db[tidx] - sum) / dA[tidx*size + tidx];
}
__global__ void solve5(float* dx, float* dA, float* db, float* dnextX, int size) {
extern __shared__ float shared_dx[];
} | #ifndef SOLVE_JACOBI_CUH
#define SOLVE_JACOBI_CUH
__global__ void solve1(float* dx, float* dA, float* db, float* dnextX, int size);
//__global__ void solve2_sum(float* dx, float* dA, float* db, float* dnextX, int size, int nTile);
__global__ void solve2(float* dx, float* dA, float* db, float* dnextX, int size);
__global__ void solve3(float* dx, float* dA, float* db, float* dnextX, int size);
__global__ void solve4(float* dx, float* dA, float* db, float* dnextX, int size);
__global__ void solve5(float* dx, float* dA, float* db, float* dnextX, int size);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef SOLVE_JACOBI_CUH
#define SOLVE_JACOBI_CUH
__global__ void solve1(float* dx, float* dA, float* db, float* dnextX, int size);
//__global__ void solve2_sum(float* dx, float* dA, float* db, float* dnextX, int size, int nTile);
__global__ void solve2(float* dx, float* dA, float* db, float* dnextX, int size);
__global__ void solve3(float* dx, float* dA, float* db, float* dnextX, int size);
__global__ void solve4(float* dx, float* dA, float* db, float* dnextX, int size);
__global__ void solve5(float* dx, float* dA, float* db, float* dnextX, int size);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef SOLVE_JACOBI_CUH
#define SOLVE_JACOBI_CUH
__global__ void solve1(float* dx, float* dA, float* db, float* dnextX, int size);
//__global__ void solve2_sum(float* dx, float* dA, float* db, float* dnextX, int size, int nTile);
__global__ void solve2(float* dx, float* dA, float* db, float* dnextX, int size);
__global__ void solve3(float* dx, float* dA, float* db, float* dnextX, int size);
__global__ void solve4(float* dx, float* dA, float* db, float* dnextX, int size);
__global__ void solve5(float* dx, float* dA, float* db, float* dnextX, int size);
#endif | .text
.file "solve_jacobi.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00026273_00000000-6_solve_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve1PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i
.globl _Z6solve1PfS_S_S_i
.type _Z6solve1PfS_S_S_i, @function
_Z6solve1PfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve1PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6solve1PfS_S_S_i, .-_Z6solve1PfS_S_S_i
.globl _Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve2PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i
.globl _Z6solve2PfS_S_S_i
.type _Z6solve2PfS_S_S_i, @function
_Z6solve2PfS_S_S_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve2PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z6solve2PfS_S_S_i, .-_Z6solve2PfS_S_S_i
.globl _Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve3PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i
.globl _Z6solve3PfS_S_S_i
.type _Z6solve3PfS_S_S_i, @function
_Z6solve3PfS_S_S_i:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve3PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z6solve3PfS_S_S_i, .-_Z6solve3PfS_S_S_i
.globl _Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve4PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i
.globl _Z6solve4PfS_S_S_i
.type _Z6solve4PfS_S_S_i, @function
_Z6solve4PfS_S_S_i:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve4PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z6solve4PfS_S_S_i, .-_Z6solve4PfS_S_S_i
.globl _Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i:
.LFB2059:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6solve5PfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i
.globl _Z6solve5PfS_S_S_i
.type _Z6solve5PfS_S_S_i, @function
_Z6solve5PfS_S_S_i:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6solve5PfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z6solve5PfS_S_S_i, .-_Z6solve5PfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6solve5PfS_S_S_i"
.LC1:
.string "_Z6solve4PfS_S_S_i"
.LC2:
.string "_Z6solve3PfS_S_S_i"
.LC3:
.string "_Z6solve2PfS_S_S_i"
.LC4:
.string "_Z6solve1PfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve5PfS_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve4PfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve3PfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve2PfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6solve1PfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "solve_jacobi.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Kernel10(int N, int M, int P, float *A, float *B, float *C) {
__shared__ float sA[SIZE][SIZE];
__shared__ float sB[SIZE][SIZE];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int row = by * SIZE + ty;
int col = bx * SIZE + tx;
float tmp = 0.0;
for (int m=0; m < P; m=m+SIZE) {
sA[ty][tx] = A[row*P + m + tx];
sB[ty][tx] = B[col + (m + ty)*M];
__syncthreads();
for (int k=0; k<SIZE; k++)
tmp += sA[ty][k] * sB[k][tx];
__syncthreads();
}
C[row*M+col] = tmp;
} | .file "tmpxft_000a0b1e_00000000-6_Kernel10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_
.type _Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_, @function
_Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8Kernel10iiiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_, .-_Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_
.globl _Z8Kernel10iiiPfS_S_
.type _Z8Kernel10iiiPfS_S_, @function
_Z8Kernel10iiiPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8Kernel10iiiPfS_S_, .-_Z8Kernel10iiiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8Kernel10iiiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8Kernel10iiiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Kernel10(int N, int M, int P, float *A, float *B, float *C) {
__shared__ float sA[SIZE][SIZE];
__shared__ float sB[SIZE][SIZE];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int row = by * SIZE + ty;
int col = bx * SIZE + tx;
float tmp = 0.0;
for (int m=0; m < P; m=m+SIZE) {
sA[ty][tx] = A[row*P + m + tx];
sB[ty][tx] = B[col + (m + ty)*M];
__syncthreads();
for (int k=0; k<SIZE; k++)
tmp += sA[ty][k] * sB[k][tx];
__syncthreads();
}
C[row*M+col] = tmp;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Kernel10(int N, int M, int P, float *A, float *B, float *C) {
__shared__ float sA[SIZE][SIZE];
__shared__ float sB[SIZE][SIZE];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int row = by * SIZE + ty;
int col = bx * SIZE + tx;
float tmp = 0.0;
for (int m=0; m < P; m=m+SIZE) {
sA[ty][tx] = A[row*P + m + tx];
sB[ty][tx] = B[col + (m + ty)*M];
__syncthreads();
for (int k=0; k<SIZE; k++)
tmp += sA[ty][k] * sB[k][tx];
__syncthreads();
}
C[row*M+col] = tmp;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Kernel10(int N, int M, int P, float *A, float *B, float *C) {
__shared__ float sA[SIZE][SIZE];
__shared__ float sB[SIZE][SIZE];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int row = by * SIZE + ty;
int col = bx * SIZE + tx;
float tmp = 0.0;
for (int m=0; m < P; m=m+SIZE) {
sA[ty][tx] = A[row*P + m + tx];
sB[ty][tx] = B[col + (m + ty)*M];
__syncthreads();
for (int k=0; k<SIZE; k++)
tmp += sA[ty][k] * sB[k][tx];
__syncthreads();
}
C[row*M+col] = tmp;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8Kernel10iiiPfS_S_
.globl _Z8Kernel10iiiPfS_S_
.p2align 8
.type _Z8Kernel10iiiPfS_S_,@function
_Z8Kernel10iiiPfS_S_:
s_load_b64 s[2:3], s[0:1], 0x4
v_bfe_u32 v5, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 6, v5
v_mad_u64_u32 v[1:2], null, v4, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 0x400, v8
v_add_nc_u32_e32 v3, v6, v8
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, v7, v6
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v10, s8, v5
v_add_nc_u32_e32 v9, s8, v1
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_eq_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v2, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8Kernel10iiiPfS_S_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8Kernel10iiiPfS_S_, .Lfunc_end0-_Z8Kernel10iiiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8Kernel10iiiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8Kernel10iiiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Kernel10(int N, int M, int P, float *A, float *B, float *C) {
__shared__ float sA[SIZE][SIZE];
__shared__ float sB[SIZE][SIZE];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
int row = by * SIZE + ty;
int col = bx * SIZE + tx;
float tmp = 0.0;
for (int m=0; m < P; m=m+SIZE) {
sA[ty][tx] = A[row*P + m + tx];
sB[ty][tx] = B[col + (m + ty)*M];
__syncthreads();
for (int k=0; k<SIZE; k++)
tmp += sA[ty][k] * sB[k][tx];
__syncthreads();
}
C[row*M+col] = tmp;
} | .text
.file "Kernel10.hip"
.globl _Z23__device_stub__Kernel10iiiPfS_S_ # -- Begin function _Z23__device_stub__Kernel10iiiPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__Kernel10iiiPfS_S_,@function
_Z23__device_stub__Kernel10iiiPfS_S_: # @_Z23__device_stub__Kernel10iiiPfS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8Kernel10iiiPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__Kernel10iiiPfS_S_, .Lfunc_end0-_Z23__device_stub__Kernel10iiiPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8Kernel10iiiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8Kernel10iiiPfS_S_,@object # @_Z8Kernel10iiiPfS_S_
.section .rodata,"a",@progbits
.globl _Z8Kernel10iiiPfS_S_
.p2align 3, 0x0
_Z8Kernel10iiiPfS_S_:
.quad _Z23__device_stub__Kernel10iiiPfS_S_
.size _Z8Kernel10iiiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8Kernel10iiiPfS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__Kernel10iiiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8Kernel10iiiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a0b1e_00000000-6_Kernel10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_
.type _Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_, @function
_Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8Kernel10iiiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_, .-_Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_
.globl _Z8Kernel10iiiPfS_S_
.type _Z8Kernel10iiiPfS_S_, @function
_Z8Kernel10iiiPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8Kernel10iiiPfS_S_iiiPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8Kernel10iiiPfS_S_, .-_Z8Kernel10iiiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8Kernel10iiiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8Kernel10iiiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Kernel10.hip"
.globl _Z23__device_stub__Kernel10iiiPfS_S_ # -- Begin function _Z23__device_stub__Kernel10iiiPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__Kernel10iiiPfS_S_,@function
_Z23__device_stub__Kernel10iiiPfS_S_: # @_Z23__device_stub__Kernel10iiiPfS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8Kernel10iiiPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__Kernel10iiiPfS_S_, .Lfunc_end0-_Z23__device_stub__Kernel10iiiPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8Kernel10iiiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8Kernel10iiiPfS_S_,@object # @_Z8Kernel10iiiPfS_S_
.section .rodata,"a",@progbits
.globl _Z8Kernel10iiiPfS_S_
.p2align 3, 0x0
_Z8Kernel10iiiPfS_S_:
.quad _Z23__device_stub__Kernel10iiiPfS_S_
.size _Z8Kernel10iiiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8Kernel10iiiPfS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__Kernel10iiiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8Kernel10iiiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuInsertionSort(float *dist, int dist_pitch, int *ind, int ind_pitch, int width, int height, int k){
// Variables
int l, i, j;
float *p_dist;
int *p_ind;
float curr_dist, max_dist;
int curr_row, max_row;
unsigned int xIndex = blockIdx.x * blockDim.x + threadIdx.x;
if (xIndex<width){
// Pointer shift, initialization, and max value
p_dist = dist + xIndex;
p_ind = ind + xIndex;
max_dist = p_dist[0];
p_ind[0] = 1;
// Part 1 : sort kth firt elementZ
for (l = 1; l<k; l++){
curr_row = l * dist_pitch;
curr_dist = p_dist[curr_row];
if (curr_dist<max_dist){
i = l - 1;
for (int a = 0; a<l - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = l; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
}
else
p_ind[l*ind_pitch] = l + 1;
max_dist = p_dist[curr_row];
}
// Part 2 : insert element in the k-th first lines
max_row = (k - 1)*dist_pitch;
for (l = k; l<height; l++){
curr_dist = p_dist[l*dist_pitch];
if (curr_dist<max_dist){
i = k - 1;
for (int a = 0; a<k - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = k - 1; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
max_dist = p_dist[max_row];
}
}
}
} | .file "tmpxft_000dbb55_00000000-6_cuInsertionSort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii
.type _Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii, @function
_Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15cuInsertionSortPfiPiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii, .-_Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii
.globl _Z15cuInsertionSortPfiPiiiii
.type _Z15cuInsertionSortPfiPiiiii, @function
_Z15cuInsertionSortPfiPiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15cuInsertionSortPfiPiiiii, .-_Z15cuInsertionSortPfiPiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15cuInsertionSortPfiPiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cuInsertionSortPfiPiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuInsertionSort(float *dist, int dist_pitch, int *ind, int ind_pitch, int width, int height, int k){
// Variables
int l, i, j;
float *p_dist;
int *p_ind;
float curr_dist, max_dist;
int curr_row, max_row;
unsigned int xIndex = blockIdx.x * blockDim.x + threadIdx.x;
if (xIndex<width){
// Pointer shift, initialization, and max value
p_dist = dist + xIndex;
p_ind = ind + xIndex;
max_dist = p_dist[0];
p_ind[0] = 1;
// Part 1 : sort kth firt elementZ
for (l = 1; l<k; l++){
curr_row = l * dist_pitch;
curr_dist = p_dist[curr_row];
if (curr_dist<max_dist){
i = l - 1;
for (int a = 0; a<l - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = l; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
}
else
p_ind[l*ind_pitch] = l + 1;
max_dist = p_dist[curr_row];
}
// Part 2 : insert element in the k-th first lines
max_row = (k - 1)*dist_pitch;
for (l = k; l<height; l++){
curr_dist = p_dist[l*dist_pitch];
if (curr_dist<max_dist){
i = k - 1;
for (int a = 0; a<k - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = k - 1; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
max_dist = p_dist[max_row];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuInsertionSort(float *dist, int dist_pitch, int *ind, int ind_pitch, int width, int height, int k){
// Variables
int l, i, j;
float *p_dist;
int *p_ind;
float curr_dist, max_dist;
int curr_row, max_row;
unsigned int xIndex = blockIdx.x * blockDim.x + threadIdx.x;
if (xIndex<width){
// Pointer shift, initialization, and max value
p_dist = dist + xIndex;
p_ind = ind + xIndex;
max_dist = p_dist[0];
p_ind[0] = 1;
// Part 1 : sort kth firt elementZ
for (l = 1; l<k; l++){
curr_row = l * dist_pitch;
curr_dist = p_dist[curr_row];
if (curr_dist<max_dist){
i = l - 1;
for (int a = 0; a<l - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = l; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
}
else
p_ind[l*ind_pitch] = l + 1;
max_dist = p_dist[curr_row];
}
// Part 2 : insert element in the k-th first lines
max_row = (k - 1)*dist_pitch;
for (l = k; l<height; l++){
curr_dist = p_dist[l*dist_pitch];
if (curr_dist<max_dist){
i = k - 1;
for (int a = 0; a<k - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = k - 1; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
max_dist = p_dist[max_row];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuInsertionSort(float *dist, int dist_pitch, int *ind, int ind_pitch, int width, int height, int k){
// Variables
int l, i, j;
float *p_dist;
int *p_ind;
float curr_dist, max_dist;
int curr_row, max_row;
unsigned int xIndex = blockIdx.x * blockDim.x + threadIdx.x;
if (xIndex<width){
// Pointer shift, initialization, and max value
p_dist = dist + xIndex;
p_ind = ind + xIndex;
max_dist = p_dist[0];
p_ind[0] = 1;
// Part 1 : sort kth firt elementZ
for (l = 1; l<k; l++){
curr_row = l * dist_pitch;
curr_dist = p_dist[curr_row];
if (curr_dist<max_dist){
i = l - 1;
for (int a = 0; a<l - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = l; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
}
else
p_ind[l*ind_pitch] = l + 1;
max_dist = p_dist[curr_row];
}
// Part 2 : insert element in the k-th first lines
max_row = (k - 1)*dist_pitch;
for (l = k; l<height; l++){
curr_dist = p_dist[l*dist_pitch];
if (curr_dist<max_dist){
i = k - 1;
for (int a = 0; a<k - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = k - 1; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
max_dist = p_dist[max_row];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15cuInsertionSortPfiPiiiii
.globl _Z15cuInsertionSortPfiPiiiii
.p2align 8
.type _Z15cuInsertionSortPfiPiiiii,@function
_Z15cuInsertionSortPfiPiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_29
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s13, s[0:1], 0x24
v_mov_b32_e32 v2, 0
s_clause 0x2
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b32 s12, s[0:1], 0x18
v_mov_b32_e32 v4, 1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v6, v[0:1], off
s_cmp_lt_i32 s13, 2
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_15
s_ashr_i32 s5, s4, 31
s_mov_b32 s3, 1
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s5, 0
s_mov_b32 s14, 0
s_branch .LBB0_5
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s16
v_mul_lo_u32 v6, v9, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, v1, v7, vcc_lo
global_store_b32 v[6:7], v8, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s15
global_load_b32 v6, v[4:5], off
v_mul_lo_u32 v4, v9, s12
s_add_i32 s3, s3, 1
s_add_i32 s14, s14, s12
v_mov_b32_e32 v7, s3
s_add_i32 s5, s5, s4
s_cmp_lg_u32 s3, s13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, v3, v5, vcc_lo
global_store_b32 v[4:5], v7, off
s_cbranch_scc0 .LBB0_15
.LBB0_5:
s_mul_i32 s8, s3, s4
v_mov_b32_e32 v9, s3
s_ashr_i32 s9, s8, 31
s_mov_b32 s15, exec_lo
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v4, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
global_load_b32 v8, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 v8, v6
s_cbranch_execz .LBB0_4
s_add_i32 s2, s3, -1
s_cmp_lt_u32 s3, 2
v_mov_b32_e32 v9, s2
s_cbranch_scc1 .LBB0_12
v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
s_mov_b32 s8, 0
s_mov_b32 s9, 0
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s11, exec_lo, s10
s_or_b32 s8, s11, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_11
.LBB0_9:
global_load_b32 v9, v[6:7], off
s_or_b32 s10, s10, exec_lo
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, v9, v8
v_mov_b32_e32 v9, s9
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_8
s_add_i32 s9, s9, 1
v_add_co_u32 v6, vcc_lo, v6, s6
s_cmp_ge_u32 s9, s2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_cselect_b32 s16, -1, 0
v_mov_b32_e32 v9, s2
s_and_not1_b32 s10, s10, exec_lo
s_and_b32 s16, s16, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s10, s16
s_branch .LBB0_8
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s16, exec_lo
v_cmpx_gt_u32_e64 s3, v9
s_cbranch_execz .LBB0_3
s_mov_b32 s17, 0
s_mov_b32 s8, s5
s_mov_b32 s10, s14
s_mov_b32 s18, s3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_14:
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[20:21], s[8:9], 2
s_add_i32 s22, s12, s10
v_add_co_u32 v6, vcc_lo, v0, s20
v_add_co_ci_u32_e32 v7, vcc_lo, s21, v1, vcc_lo
s_lshl_b64 s[20:21], s[10:11], 2
s_ashr_i32 s23, s22, 31
v_add_co_u32 v10, vcc_lo, v2, s20
v_add_co_ci_u32_e32 v11, vcc_lo, s21, v3, vcc_lo
global_load_b32 v12, v[6:7], off
global_load_b32 v13, v[10:11], off
s_add_i32 s20, s4, s8
s_add_i32 s18, s18, -1
s_ashr_i32 s21, s20, 31
s_lshl_b64 s[22:23], s[22:23], 2
s_lshl_b64 s[20:21], s[20:21], 2
v_cmp_le_i32_e32 vcc_lo, s18, v9
v_add_co_u32 v6, s2, v0, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, s21, v1, s2
v_add_co_u32 v10, s2, v2, s22
v_add_co_ci_u32_e64 v11, s2, s23, v3, s2
s_sub_i32 s10, s10, s12
s_sub_i32 s8, s8, s4
s_or_b32 s17, vcc_lo, s17
s_waitcnt vmcnt(1)
global_store_b32 v[6:7], v12, off
s_waitcnt vmcnt(0)
global_store_b32 v[10:11], v13, off
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_14
s_branch .LBB0_3
.LBB0_15:
s_load_b32 s1, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s13, s1
s_cbranch_scc1 .LBB0_29
s_add_i32 s8, s13, -1
s_cmp_gt_i32 s13, 1
s_mul_i32 s2, s8, s4
s_cselect_b32 s9, -1, 0
s_ashr_i32 s3, s2, 31
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[2:3], 2
s_add_i32 s0, s13, -2
v_add_co_u32 v4, vcc_lo, v0, s6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_lshl_b64 s[6:7], s[4:5], 2
s_mul_i32 s3, s12, s8
s_mul_i32 s5, s4, s0
s_mul_i32 s10, s12, s0
s_branch .LBB0_19
.LBB0_17:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s14
v_mul_lo_u32 v6, v9, s4
s_add_i32 s0, s13, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, v1, v7, vcc_lo
global_store_b32 v[6:7], v8, off
global_load_b32 v6, v[4:5], off
v_mul_lo_u32 v7, v9, s12
v_mov_b32_e32 v9, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, v3, v8, vcc_lo
global_store_b32 v[7:8], v9, off
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s13, s1
s_cbranch_scc0 .LBB0_29
.LBB0_19:
s_mul_i32 s14, s13, s4
s_mov_b32 s11, exec_lo
s_ashr_i32 s15, s14, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[14:15], 2
v_add_co_u32 v7, vcc_lo, v0, s14
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v1, vcc_lo
global_load_b32 v8, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_lt_f32_e32 v8, v6
s_cbranch_execz .LBB0_18
v_mov_b32_e32 v9, s8
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_26
v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
s_mov_b32 s0, 0
s_mov_b32 s14, 0
s_branch .LBB0_23
.p2align 6
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s16, exec_lo, s15
s_or_b32 s0, s16, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_25
.LBB0_23:
global_load_b32 v9, v[6:7], off
s_or_b32 s15, s15, exec_lo
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, v9, v8
v_mov_b32_e32 v9, s14
s_and_saveexec_b32 s16, vcc_lo
s_cbranch_execz .LBB0_22
s_add_i32 s14, s14, 1
v_add_co_u32 v6, vcc_lo, v6, s6
s_cmp_eq_u32 s8, s14
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_cselect_b32 s17, -1, 0
v_mov_b32_e32 v9, s8
s_and_not1_b32 s15, s15, exec_lo
s_and_b32 s17, s17, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s15, s15, s17
s_branch .LBB0_22
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_26:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 s14, exec_lo
v_cmpx_gt_i32_e64 s8, v9
s_cbranch_execz .LBB0_17
s_mov_b32 s15, 0
s_mov_b32 s16, 0
s_mov_b32 s17, 0
s_mov_b32 s18, s8
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_28:
s_add_i32 s20, s5, s16
s_add_i32 s22, s10, s17
s_ashr_i32 s21, s20, 31
s_ashr_i32 s23, s22, 31
s_lshl_b64 s[20:21], s[20:21], 2
s_lshl_b64 s[22:23], s[22:23], 2
v_add_co_u32 v6, vcc_lo, v0, s20
v_add_co_ci_u32_e32 v7, vcc_lo, s21, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, v2, s22
v_add_co_ci_u32_e32 v11, vcc_lo, s23, v3, vcc_lo
s_add_i32 s20, s2, s16
global_load_b32 v12, v[6:7], off
global_load_b32 v13, v[10:11], off
s_ashr_i32 s21, s20, 31
s_add_i32 s22, s3, s17
s_lshl_b64 s[20:21], s[20:21], 2
s_ashr_i32 s23, s22, 31
s_add_i32 s18, s18, -1
v_add_co_u32 v6, s0, v0, s20
s_lshl_b64 s[22:23], s[22:23], 2
v_cmp_le_i32_e32 vcc_lo, s18, v9
v_add_co_ci_u32_e64 v7, s0, s21, v1, s0
v_add_co_u32 v10, s0, v2, s22
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s23, v3, s0
s_sub_i32 s17, s17, s12
s_sub_i32 s16, s16, s4
s_or_b32 s15, vcc_lo, s15
s_waitcnt vmcnt(1)
global_store_b32 v[6:7], v12, off
s_waitcnt vmcnt(0)
global_store_b32 v[10:11], v13, off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_28
s_branch .LBB0_17
.LBB0_29:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15cuInsertionSortPfiPiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15cuInsertionSortPfiPiiiii, .Lfunc_end0-_Z15cuInsertionSortPfiPiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15cuInsertionSortPfiPiiiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z15cuInsertionSortPfiPiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuInsertionSort(float *dist, int dist_pitch, int *ind, int ind_pitch, int width, int height, int k){
// Variables
int l, i, j;
float *p_dist;
int *p_ind;
float curr_dist, max_dist;
int curr_row, max_row;
unsigned int xIndex = blockIdx.x * blockDim.x + threadIdx.x;
if (xIndex<width){
// Pointer shift, initialization, and max value
p_dist = dist + xIndex;
p_ind = ind + xIndex;
max_dist = p_dist[0];
p_ind[0] = 1;
// Part 1 : sort kth firt elementZ
for (l = 1; l<k; l++){
curr_row = l * dist_pitch;
curr_dist = p_dist[curr_row];
if (curr_dist<max_dist){
i = l - 1;
for (int a = 0; a<l - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = l; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
}
else
p_ind[l*ind_pitch] = l + 1;
max_dist = p_dist[curr_row];
}
// Part 2 : insert element in the k-th first lines
max_row = (k - 1)*dist_pitch;
for (l = k; l<height; l++){
curr_dist = p_dist[l*dist_pitch];
if (curr_dist<max_dist){
i = k - 1;
for (int a = 0; a<k - 1; a++){
if (p_dist[a*dist_pitch]>curr_dist){
i = a;
break;
}
}
for (j = k - 1; j>i; j--){
p_dist[j*dist_pitch] = p_dist[(j - 1)*dist_pitch];
p_ind[j*ind_pitch] = p_ind[(j - 1)*ind_pitch];
}
p_dist[i*dist_pitch] = curr_dist;
p_ind[i*ind_pitch] = l + 1;
max_dist = p_dist[max_row];
}
}
}
} | .text
.file "cuInsertionSort.hip"
.globl _Z30__device_stub__cuInsertionSortPfiPiiiii # -- Begin function _Z30__device_stub__cuInsertionSortPfiPiiiii
.p2align 4, 0x90
.type _Z30__device_stub__cuInsertionSortPfiPiiiii,@function
_Z30__device_stub__cuInsertionSortPfiPiiiii: # @_Z30__device_stub__cuInsertionSortPfiPiiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15cuInsertionSortPfiPiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z30__device_stub__cuInsertionSortPfiPiiiii, .Lfunc_end0-_Z30__device_stub__cuInsertionSortPfiPiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cuInsertionSortPfiPiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15cuInsertionSortPfiPiiiii,@object # @_Z15cuInsertionSortPfiPiiiii
.section .rodata,"a",@progbits
.globl _Z15cuInsertionSortPfiPiiiii
.p2align 3, 0x0
_Z15cuInsertionSortPfiPiiiii:
.quad _Z30__device_stub__cuInsertionSortPfiPiiiii
.size _Z15cuInsertionSortPfiPiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15cuInsertionSortPfiPiiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__cuInsertionSortPfiPiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15cuInsertionSortPfiPiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dbb55_00000000-6_cuInsertionSort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii
.type _Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii, @function
_Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15cuInsertionSortPfiPiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii, .-_Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii
.globl _Z15cuInsertionSortPfiPiiiii
.type _Z15cuInsertionSortPfiPiiiii, @function
_Z15cuInsertionSortPfiPiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z15cuInsertionSortPfiPiiiiiPfiPiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15cuInsertionSortPfiPiiiii, .-_Z15cuInsertionSortPfiPiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15cuInsertionSortPfiPiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15cuInsertionSortPfiPiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuInsertionSort.hip"
.globl _Z30__device_stub__cuInsertionSortPfiPiiiii # -- Begin function _Z30__device_stub__cuInsertionSortPfiPiiiii
.p2align 4, 0x90
.type _Z30__device_stub__cuInsertionSortPfiPiiiii,@function
_Z30__device_stub__cuInsertionSortPfiPiiiii: # @_Z30__device_stub__cuInsertionSortPfiPiiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15cuInsertionSortPfiPiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z30__device_stub__cuInsertionSortPfiPiiiii, .Lfunc_end0-_Z30__device_stub__cuInsertionSortPfiPiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15cuInsertionSortPfiPiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15cuInsertionSortPfiPiiiii,@object # @_Z15cuInsertionSortPfiPiiiii
.section .rodata,"a",@progbits
.globl _Z15cuInsertionSortPfiPiiiii
.p2align 3, 0x0
_Z15cuInsertionSortPfiPiiiii:
.quad _Z30__device_stub__cuInsertionSortPfiPiiiii
.size _Z15cuInsertionSortPfiPiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15cuInsertionSortPfiPiiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__cuInsertionSortPfiPiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15cuInsertionSortPfiPiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void bestFilterUpdate(const double *Params, const float *data, const float *mu, float *err, float *eloss, int *ftype, const int *st, const int *id, const int *counter){
int tid, ind, i,t, NT, Nfilt, ibest = 0, nt0;
float Cf, Cbest, lam, b, a, Cnextbest;
tid = threadIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
lam = (float) Params[7];
nt0 = (int) Params[4];
// we only need to compute this at updated locations
ind = counter[1] + blockIdx.x;
if (ind<counter[0]){
t = st[ind]-nt0 + tid;
if (t>=0 && t<NT){
Cbest = 0.0f;
for (i=0; i<Nfilt;i++){
a = 1+ lam;
b = max(0.0f, data[t + NT * i]) + lam * mu[i];
Cf = b*b/a - lam * mu[i]*mu[i];
if (Cf > Cbest + 1e-6){
Cnextbest = Cbest;
Cbest = Cf;
ibest = i;
}
else
if (Cf > Cnextbest + 1e-6)
Cnextbest = Cf;
}
err[t] = Cbest;
ftype[t] = ibest;
}
}
} | code for sm_80
Function : _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea8000c1e1900 */
/*0050*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ee2000c1e1900 */
/*0060*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000ea40000002500 */
/*0070*/ IADD3 R0, R0, UR6, RZ ; /* 0x0000000600007c10 */
/* 0x004fc8000fffe0ff */
/*0080*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x008fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*00c0*/ LDG.E.64 R6, [R2.64+0x20] ; /* 0x0000200402067981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x4 ; /* 0x00000004ff157424 */
/* 0x000fc600078e00ff */
/*00e0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ IMAD.WIDE R20, R0, R21, c[0x0][0x190] ; /* 0x0000640000147625 */
/* 0x000fcc00078e0215 */
/*0100*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1900 */
/*0110*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000f220000002100 */
/*0120*/ F2I.F64.TRUNC R18, R6 ; /* 0x0000000600127311 */
/* 0x004f30000030d100 */
/*0130*/ F2I.F64.TRUNC R13, R4 ; /* 0x00000004000d7311 */
/* 0x008e22000030d100 */
/*0140*/ IADD3 R12, R19, R20, -R18 ; /* 0x00000014130c7210 */
/* 0x010fc80007ffe812 */
/*0150*/ ISETP.GE.AND P0, PT, R12, R13, PT ; /* 0x0000000d0c00720c */
/* 0x001fc80003f06270 */
/*0160*/ ISETP.LT.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0000701670 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ LDG.E.64 R4, [R2.64+0x8] ; /* 0x0000080402047981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*01a0*/ F2I.F64.TRUNC R5, R4 ; /* 0x0000000400057311 */
/* 0x004e24000030d100 */
/*01b0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x001fda0003f06270 */
/*01c0*/ @!P0 BRA 0xc00 ; /* 0x00000a3000008947 */
/* 0x000fea0003800000 */
/*01d0*/ LDG.E.64 R2, [R2.64+0x38] ; /* 0x0000380402027981 */
/* 0x000ea2000c1e1b00 */
/*01e0*/ IADD3 R0, R5.reuse, -0x1, RZ ; /* 0xffffffff05007810 */
/* 0x040fe20007ffe0ff */
/*01f0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0200*/ LOP3.LUT R8, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305087812 */
/* 0x000fe200078ec0ff */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0230*/ F2F.F32.F64 R9, R2 ; /* 0x0000000200097310 */
/* 0x004e240000301000 */
/*0240*/ FADD R6, R9, 1 ; /* 0x3f80000009067421 */
/* 0x001fd40000000000 */
/*0250*/ @!P0 BRA 0x980 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105057824 */
/* 0x000fe200078e0a08 */
/*0270*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe4000001ff00 */
/*0280*/ HFMA2.MMA R14, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0e7435 */
/* 0x000fe200000001ff */
/*0290*/ IMAD R16, R13, R7, R12 ; /* 0x000000070d107224 */
/* 0x000fd200078e020c */
/*02a0*/ IMAD.WIDE R16, R16, R14, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fc800078e020e */
/*02b0*/ IMAD.WIDE R14, R7, R14, c[0x0][0x170] ; /* 0x00005c00070e7625 */
/* 0x000fe200078e020e */
/*02c0*/ LDG.E R0, [R16.64] ; /* 0x0000000410007981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R28, [R14.64] ; /* 0x000000040e1c7981 */
/* 0x000ee2000c1e1900 */
/*02e0*/ MUFU.RCP R3, R6 ; /* 0x0000000600037308 */
/* 0x000e220000001000 */
/*02f0*/ BSSY B0, 0x3e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0300*/ FFMA R2, -R6, R3, 1 ; /* 0x3f80000006027423 */
/* 0x001fc80000000103 */
/*0310*/ FFMA R2, R3, R2, R3 ; /* 0x0000000203027223 */
/* 0x000fe20000000003 */
/*0320*/ FMNMX R0, RZ, R0, !PT ; /* 0x00000000ff007209 */
/* 0x004fe20007800000 */
/*0330*/ FMUL R27, R9, R28 ; /* 0x0000001c091b7220 */
/* 0x008fc80000400000 */
/*0340*/ FADD R0, R0, R27 ; /* 0x0000001b00007221 */
/* 0x000fc80000000000 */
/*0350*/ FMUL R23, R0, R0 ; /* 0x0000000000177220 */
/* 0x000fc80000400000 */
/*0360*/ FCHK P0, R23, R6 ; /* 0x0000000617007302 */
/* 0x000e220000000000 */
/*0370*/ FFMA R3, R23, R2, RZ ; /* 0x0000000217037223 */
/* 0x000fc800000000ff */
/*0380*/ FFMA R0, -R6, R3, R23 ; /* 0x0000000306007223 */
/* 0x000fc80000000117 */
/*0390*/ FFMA R0, R2, R0, R3 ; /* 0x0000000002007223 */
/* 0x000fe20000000003 */
/*03a0*/ @!P0 BRA 0x3d0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*03b0*/ MOV R22, 0x3d0 ; /* 0x000003d000167802 */
/* 0x000fe40000000f00 */
/*03c0*/ CALL.REL.NOINC 0xc60 ; /* 0x0000089000007944 */
/* 0x000fea0003c00000 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.WIDE R16, R13, 0x4, R16 ; /* 0x000000040d107825 */
/* 0x000fe200078e0210 */
/*03f0*/ LDG.E R4, [R14.64+0x4] ; /* 0x000004040e047981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000ee2000c1e1900 */
/*0410*/ MUFU.RCP R21, R6 ; /* 0x0000000600157308 */
/* 0x000e220000001000 */
/*0420*/ FFMA R28, -R28, R27, R0 ; /* 0x0000001b1c1c7223 */
/* 0x000fce0000000100 */
/*0430*/ F2F.F64.F32 R2, R11 ; /* 0x0000000b00027310 */
/* 0x000e620000201800 */
/*0440*/ FFMA R0, -R6, R21, 1 ; /* 0x3f80000006007423 */
/* 0x001fce0000000115 */
/*0450*/ F2F.F64.F32 R22, R28 ; /* 0x0000001c00167310 */
/* 0x000e220000201800 */
/*0460*/ FFMA R26, R21, R0, R21 ; /* 0x00000000151a7223 */
/* 0x000fe20000000015 */
/*0470*/ DADD R2, R2, c[0x2][0x0] ; /* 0x0080000002027629 */
/* 0x002e220000000000 */
/*0480*/ BSSY B0, 0x590 ; /* 0x0000010000007945 */
/* 0x000fea0003800000 */
/*0490*/ DSETP.GEU.AND P1, PT, R2, R22, PT ; /* 0x000000160200722a */
/* 0x001e0c0003f2e000 */
/*04a0*/ FSEL R11, R28, R11, !P1 ; /* 0x0000000b1c0b7208 */
/* 0x001fe40004800000 */
/*04b0*/ SEL R10, R7, R10, !P1 ; /* 0x0000000a070a7207 */
/* 0x000fe20004800000 */
/*04c0*/ FMUL R27, R9, R4 ; /* 0x00000004091b7220 */
/* 0x004fe20000400000 */
/*04d0*/ FMNMX R24, RZ, R24, !PT ; /* 0x00000018ff187209 */
/* 0x008fca0007800000 */
/*04e0*/ FADD R24, R24, R27 ; /* 0x0000001b18187221 */
/* 0x000fc80000000000 */
/*04f0*/ FMUL R21, R24, R24 ; /* 0x0000001818157220 */
/* 0x000fc80000400000 */
/*0500*/ FCHK P0, R21, R6 ; /* 0x0000000615007302 */
/* 0x000e220000000000 */
/*0510*/ FFMA R0, R26, R21, RZ ; /* 0x000000151a007223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R3, -R6, R0, R21 ; /* 0x0000000006037223 */
/* 0x000fc80000000115 */
/*0530*/ FFMA R0, R26, R3, R0 ; /* 0x000000031a007223 */
/* 0x000fe20000000000 */
/*0540*/ @!P0 BRA 0x580 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0550*/ IMAD.MOV.U32 R23, RZ, RZ, R21 ; /* 0x000000ffff177224 */
/* 0x000fe200078e0015 */
/*0560*/ MOV R22, 0x580 ; /* 0x0000058000167802 */
/* 0x000fe40000000f00 */
/*0570*/ CALL.REL.NOINC 0xc60 ; /* 0x000006e000007944 */
/* 0x000fea0003c00000 */
/*0580*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0590*/ IMAD.WIDE R28, R13, 0x4, R16 ; /* 0x000000040d1c7825 */
/* 0x000fe400078e0210 */
/*05a0*/ LDG.E R16, [R14.64+0x8] ; /* 0x000008040e107981 */
/* 0x000ea8000c1e1900 */
/*05b0*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x000ee2000c1e1900 */
/*05c0*/ F2F.F64.F32 R2, R11 ; /* 0x0000000b00027310 */
/* 0x000e220000201800 */
/*05d0*/ FFMA R4, -R4, R27, R0 ; /* 0x0000001b04047223 */
/* 0x000fce0000000100 */
/*05e0*/ F2F.F64.F32 R22, R4 ; /* 0x0000000400167310 */
/* 0x000e700000201800 */
/*05f0*/ MUFU.RCP R21, R6 ; /* 0x0000000600157308 */
/* 0x000f220000001000 */
/*0600*/ DADD R2, R2, c[0x2][0x0] ; /* 0x0080000002027629 */
/* 0x001e4c0000000000 */
/*0610*/ DSETP.GEU.AND P1, PT, R2, R22, PT ; /* 0x000000160200722a */
/* 0x0028240003f2e000 */
/*0620*/ FFMA R2, -R6, R21, 1 ; /* 0x3f80000006027423 */
/* 0x010fc80000000115 */
/*0630*/ FFMA R2, R21, R2, R21 ; /* 0x0000000215027223 */
/* 0x000fe20000000015 */
/*0640*/ BSSY B0, 0x730 ; /* 0x000000e000007945 */
/* 0x000fee0003800000 */
/*0650*/ @!P1 IADD3 R10, R7, 0x1, RZ ; /* 0x00000001070a9810 */
/* 0x001fe40007ffe0ff */
/*0660*/ FSEL R11, R4, R11, !P1 ; /* 0x0000000b040b7208 */
/* 0x000fc40004800000 */
/*0670*/ FMNMX R0, RZ, R17, !PT ; /* 0x00000011ff007209 */
/* 0x008fe20007800000 */
/*0680*/ FMUL R17, R9, R16 ; /* 0x0000001009117220 */
/* 0x004fc80000400000 */
/*0690*/ FADD R0, R0, R17 ; /* 0x0000001100007221 */
/* 0x000fc80000000000 */
/*06a0*/ FMUL R23, R0, R0 ; /* 0x0000000000177220 */
/* 0x000fc80000400000 */
/*06b0*/ FCHK P0, R23, R6 ; /* 0x0000000617007302 */
/* 0x000e220000000000 */
/*06c0*/ FFMA R3, R2, R23, RZ ; /* 0x0000001702037223 */
/* 0x000fc800000000ff */
/*06d0*/ FFMA R0, -R6, R3, R23 ; /* 0x0000000306007223 */
/* 0x000fc80000000117 */
/*06e0*/ FFMA R0, R2, R0, R3 ; /* 0x0000000002007223 */
/* 0x000fe20000000003 */
/*06f0*/ @!P0 BRA 0x720 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0700*/ MOV R22, 0x720 ; /* 0x0000072000167802 */
/* 0x000fe40000000f00 */
/*0710*/ CALL.REL.NOINC 0xc60 ; /* 0x0000054000007944 */
/* 0x000fea0003c00000 */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ IMAD.WIDE R28, R13, 0x4, R28 ; /* 0x000000040d1c7825 */
/* 0x000fe200078e021c */
/*0740*/ LDG.E R14, [R14.64+0xc] ; /* 0x00000c040e0e7981 */
/* 0x000eaa000c1e1900 */
/*0750*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ee2000c1e1900 */
/*0760*/ F2F.F64.F32 R2, R11 ; /* 0x0000000b00027310 */
/* 0x000e220000201800 */
/*0770*/ FFMA R4, -R16, R17, R0 ; /* 0x0000001110047223 */
/* 0x000fce0000000100 */
/*0780*/ F2F.F64.F32 R22, R4 ; /* 0x0000000400167310 */
/* 0x000e700000201800 */
/*0790*/ MUFU.RCP R21, R6 ; /* 0x0000000600157308 */
/* 0x000f220000001000 */
/*07a0*/ DADD R2, R2, c[0x2][0x0] ; /* 0x0080000002027629 */
/* 0x001e4c0000000000 */
/*07b0*/ DSETP.GEU.AND P1, PT, R2, R22, PT ; /* 0x000000160200722a */
/* 0x0028240003f2e000 */
/*07c0*/ FFMA R2, -R6, R21, 1 ; /* 0x3f80000006027423 */
/* 0x010fc80000000115 */
/*07d0*/ FFMA R2, R21, R2, R21 ; /* 0x0000000215027223 */
/* 0x000fe20000000015 */
/*07e0*/ BSSY B0, 0x8d0 ; /* 0x000000e000007945 */
/* 0x000fee0003800000 */
/*07f0*/ @!P1 IADD3 R10, R7, 0x2, RZ ; /* 0x00000002070a9810 */
/* 0x001fe40007ffe0ff */
/*0800*/ FSEL R4, R4, R11, !P1 ; /* 0x0000000b04047208 */
/* 0x000fe20004800000 */
/*0810*/ FMUL R17, R9, R14 ; /* 0x0000000e09117220 */
/* 0x004fe20000400000 */
/*0820*/ FMNMX R0, RZ, R28, !PT ; /* 0x0000001cff007209 */
/* 0x008fca0007800000 */
/*0830*/ FADD R0, R0, R17 ; /* 0x0000001100007221 */
/* 0x000fc80000000000 */
/*0840*/ FMUL R23, R0, R0 ; /* 0x0000000000177220 */
/* 0x000fc80000400000 */
/*0850*/ FCHK P0, R23, R6 ; /* 0x0000000617007302 */
/* 0x000e220000000000 */
/*0860*/ FFMA R3, R2, R23, RZ ; /* 0x0000001702037223 */
/* 0x000fc800000000ff */
/*0870*/ FFMA R0, -R6, R3, R23 ; /* 0x0000000306007223 */
/* 0x000fc80000000117 */
/*0880*/ FFMA R0, R2, R0, R3 ; /* 0x0000000002007223 */
/* 0x000fe20000000003 */
/*0890*/ @!P0 BRA 0x8c0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*08a0*/ MOV R22, 0x8c0 ; /* 0x000008c000167802 */
/* 0x000fe40000000f00 */
/*08b0*/ CALL.REL.NOINC 0xc60 ; /* 0x000003a000007944 */
/* 0x000fea0003c00000 */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ F2F.F64.F32 R2, R4 ; /* 0x0000000400027310 */
/* 0x000e220000201800 */
/*08e0*/ FFMA R17, -R14, R17, R0 ; /* 0x000000110e117223 */
/* 0x000fe20000000100 */
/*08f0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0900*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f25270 */
/*0910*/ F2F.F64.F32 R14, R17 ; /* 0x00000011000e7310 */
/* 0x000e620000201800 */
/*0920*/ DADD R2, R2, c[0x2][0x0] ; /* 0x0080000002027629 */
/* 0x001e4c0000000000 */
/*0930*/ DSETP.GEU.AND P0, PT, R2, R14, PT ; /* 0x0000000e0200722a */
/* 0x002e0c0003f0e000 */
/*0940*/ FSEL R11, R17, R4, !P0 ; /* 0x00000004110b7208 */
/* 0x001fd00004000000 */
/*0950*/ @!P0 IADD3 R10, R7.reuse, 0x3, RZ ; /* 0x00000003070a8810 */
/* 0x040fe40007ffe0ff */
/*0960*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0970*/ @P1 BRA 0x280 ; /* 0xfffff90000001947 */
/* 0x000fea000383ffff */
/*0980*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0990*/ @!P0 BRA 0xc00 ; /* 0x0000026000008947 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.IADD R20, R20, 0x1, R19 ; /* 0x0000000114147824 */
/* 0x000fe400078e0213 */
/*09b0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe400078e00ff */
/*09c0*/ IMAD R3, R13, R7, R20 ; /* 0x000000070d037224 */
/* 0x000fe400078e0214 */
/*09d0*/ IMAD.WIDE R14, R7, R16, c[0x0][0x170] ; /* 0x00005c00070e7625 */
/* 0x000fc600078e0210 */
/*09e0*/ IADD3 R3, -R18, R3, RZ ; /* 0x0000000312037210 */
/* 0x000fca0007ffe1ff */
/*09f0*/ IMAD.WIDE R16, R3, R16, c[0x0][0x168] ; /* 0x00005a0003107625 */
/* 0x000fca00078e0210 */
/*0a00*/ LDG.E R0, [R16.64] ; /* 0x0000000410007981 */
/* 0x000ea8000c1e1900 */
/*0a10*/ LDG.E R5, [R14.64] ; /* 0x000000040e057981 */
/* 0x000ee2000c1e1900 */
/*0a20*/ MUFU.RCP R19, R6 ; /* 0x0000000600137308 */
/* 0x000e220000001000 */
/*0a30*/ BSSY B0, 0xb20 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0a40*/ FMNMX R3, RZ, R0, !PT ; /* 0x00000000ff037209 */
/* 0x004fe20007800000 */
/*0a50*/ FFMA R0, -R6, R19, 1 ; /* 0x3f80000006007423 */
/* 0x001fe40000000113 */
/*0a60*/ FMUL R4, R9, R5 ; /* 0x0000000509047220 */
/* 0x008fc40000400000 */
/*0a70*/ FFMA R2, R19, R0, R19 ; /* 0x0000000013027223 */
/* 0x000fe40000000013 */
/*0a80*/ FADD R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fc80000000000 */
/*0a90*/ FMUL R23, R3, R3 ; /* 0x0000000303177220 */
/* 0x000fc80000400000 */
/*0aa0*/ FCHK P0, R23, R6 ; /* 0x0000000617007302 */
/* 0x000e220000000000 */
/*0ab0*/ FFMA R3, R2, R23, RZ ; /* 0x0000001702037223 */
/* 0x000fc800000000ff */
/*0ac0*/ FFMA R0, -R6, R3, R23 ; /* 0x0000000306007223 */
/* 0x000fc80000000117 */
/*0ad0*/ FFMA R0, R2, R0, R3 ; /* 0x0000000002007223 */
/* 0x000fe20000000003 */
/*0ae0*/ @!P0 BRA 0xb10 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0af0*/ MOV R22, 0xb10 ; /* 0x00000b1000167802 */
/* 0x000fe40000000f00 */
/*0b00*/ CALL.REL.NOINC 0xc60 ; /* 0x0000015000007944 */
/* 0x000fea0003c00000 */
/*0b10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b20*/ F2F.F64.F32 R2, R11 ; /* 0x0000000b00027310 */
/* 0x000e220000201800 */
/*0b30*/ FFMA R0, -R5, R4, R0 ; /* 0x0000000405007223 */
/* 0x000fe20000000100 */
/*0b40*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ IMAD.WIDE R16, R13, 0x4, R16 ; /* 0x000000040d107825 */
/* 0x000fe200078e0210 */
/*0b60*/ IADD3 R14, P2, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007f5e0ff */
/*0b70*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0b80*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x000e620000201800 */
/*0b90*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e060f */
/*0ba0*/ DADD R2, R2, c[0x2][0x0] ; /* 0x0080000002027629 */
/* 0x001e4c0000000000 */
/*0bb0*/ DSETP.GEU.AND P0, PT, R2, R4, PT ; /* 0x000000040200722a */
/* 0x002e0c0003f0e000 */
/*0bc0*/ SEL R10, R7.reuse, R10, !P0 ; /* 0x0000000a070a7207 */
/* 0x041fe40004000000 */
/*0bd0*/ FSEL R11, R0, R11, !P0 ; /* 0x0000000b000b7208 */
/* 0x000fe40004000000 */
/*0be0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0bf0*/ @P1 BRA 0xa00 ; /* 0xfffffe0000001947 */
/* 0x000fea000383ffff */
/*0c00*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0c10*/ IMAD.WIDE R2, R12, R13, c[0x0][0x178] ; /* 0x00005e000c027625 */
/* 0x000fc800078e020d */
/*0c20*/ IMAD.WIDE R12, R12, R13, c[0x0][0x188] ; /* 0x000062000c0c7625 */
/* 0x000fe200078e020d */
/*0c30*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0c40*/ STG.E [R12.64], R10 ; /* 0x0000000a0c007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ SHF.R.U32.HI R3, RZ, 0x17, R6.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011606 */
/*0c70*/ BSSY B1, 0x12b0 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*0c80*/ SHF.R.U32.HI R24, RZ, 0x17, R23 ; /* 0x00000017ff187819 */
/* 0x000fe20000011617 */
/*0c90*/ IMAD.MOV.U32 R26, RZ, RZ, R6 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0006 */
/*0ca0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fc400078ec0ff */
/*0cb0*/ LOP3.LUT R24, R24, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff18187812 */
/* 0x000fe400078ec0ff */
/*0cc0*/ IADD3 R0, R3, -0x1, RZ ; /* 0xffffffff03007810 */
/* 0x000fe40007ffe0ff */
/*0cd0*/ IADD3 R21, R24, -0x1, RZ ; /* 0xffffffff18157810 */
/* 0x000fe40007ffe0ff */
/*0ce0*/ ISETP.GT.U32.AND P0, PT, R0, 0xfd, PT ; /* 0x000000fd0000780c */
/* 0x000fc80003f04070 */
/*0cf0*/ ISETP.GT.U32.OR P0, PT, R21, 0xfd, P0 ; /* 0x000000fd1500780c */
/* 0x000fda0000704470 */
/*0d00*/ @!P0 MOV R2, RZ ; /* 0x000000ff00028202 */
/* 0x000fe20000000f00 */
/*0d10*/ @!P0 BRA 0xe90 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0d20*/ FSETP.GTU.FTZ.AND P0, PT, |R23|, +INF , PT ; /* 0x7f8000001700780b */
/* 0x000fe40003f1c200 */
/*0d30*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0d40*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0d50*/ @P0 BRA 0x1290 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0d60*/ LOP3.LUT P0, RZ, R26, 0x7fffffff, R23, 0xc8, !PT ; /* 0x7fffffff1aff7812 */
/* 0x000fda000780c817 */
/*0d70*/ @!P0 BRA 0x1270 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0d80*/ FSETP.NEU.FTZ.AND P2, PT, |R23|.reuse, +INF , PT ; /* 0x7f8000001700780b */
/* 0x040fe40003f5d200 */
/*0d90*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0da0*/ FSETP.NEU.FTZ.AND P0, PT, |R23|, +INF , PT ; /* 0x7f8000001700780b */
/* 0x000fd60003f1d200 */
/*0db0*/ @!P1 BRA !P2, 0x1270 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0dc0*/ LOP3.LUT P2, RZ, R23, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff17ff7812 */
/* 0x000fc8000784c0ff */
/*0dd0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0de0*/ @P1 BRA 0x1250 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0df0*/ LOP3.LUT P1, RZ, R26, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff1aff7812 */
/* 0x000fc8000782c0ff */
/*0e00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0e10*/ @P0 BRA 0x1220 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0e20*/ ISETP.GE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f06270 */
/*0e30*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f26270 */
/*0e40*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff020224 */
/* 0x000fe400078e00ff */
/*0e50*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, -0x40 ; /* 0xffffffc0ff028424 */
/* 0x000fe400078e00ff */
/*0e60*/ @!P0 FFMA R23, R23, 1.84467440737095516160e+19, RZ ; /* 0x5f80000017178823 */
/* 0x000fe400000000ff */
/*0e70*/ @!P1 FFMA R26, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f800000061a9823 */
/* 0x000fe200000000ff */
/*0e80*/ @!P1 IADD3 R2, R2, 0x40, RZ ; /* 0x0000004002029810 */
/* 0x000fe40007ffe0ff */
/*0e90*/ LEA R21, R3, 0xc0800000, 0x17 ; /* 0xc080000003157811 */
/* 0x000fe200078eb8ff */
/*0ea0*/ BSSY B2, 0x1210 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0eb0*/ IADD3 R24, R24, -0x7f, RZ ; /* 0xffffff8118187810 */
/* 0x000fc60007ffe0ff */
/*0ec0*/ IMAD.IADD R26, R26, 0x1, -R21 ; /* 0x000000011a1a7824 */
/* 0x000fc800078e0a15 */
/*0ed0*/ MUFU.RCP R0, R26 ; /* 0x0000001a00007308 */
/* 0x0000620000001000 */
/*0ee0*/ FADD.FTZ R21, -R26, -RZ ; /* 0x800000ff1a157221 */
/* 0x000fe40000010100 */
/*0ef0*/ IMAD R26, R24.reuse, -0x800000, R23 ; /* 0xff800000181a7824 */
/* 0x041fe200078e0217 */
/*0f00*/ IADD3 R24, R24, 0x7f, -R3 ; /* 0x0000007f18187810 */
/* 0x000fc80007ffe803 */
/*0f10*/ IADD3 R24, R24, R2, RZ ; /* 0x0000000218187210 */
/* 0x000fe20007ffe0ff */
/*0f20*/ FFMA R25, R0, R21, 1 ; /* 0x3f80000000197423 */
/* 0x002fc80000000015 */
/*0f30*/ FFMA R0, R0, R25, R0 ; /* 0x0000001900007223 */
/* 0x000fc80000000000 */
/*0f40*/ FFMA R23, R26, R0, RZ ; /* 0x000000001a177223 */
/* 0x000fc800000000ff */
/*0f50*/ FFMA R25, R21, R23, R26 ; /* 0x0000001715197223 */
/* 0x000fc8000000001a */
/*0f60*/ FFMA R25, R0, R25, R23 ; /* 0x0000001900197223 */
/* 0x000fc80000000017 */
/*0f70*/ FFMA R21, R21, R25, R26 ; /* 0x0000001915157223 */
/* 0x000fc8000000001a */
/*0f80*/ FFMA R23, R0, R21, R25 ; /* 0x0000001500177223 */
/* 0x000fca0000000019 */
/*0f90*/ SHF.R.U32.HI R3, RZ, 0x17, R23 ; /* 0x00000017ff037819 */
/* 0x000fc80000011617 */
/*0fa0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*0fb0*/ IMAD.IADD R2, R3, 0x1, R24 ; /* 0x0000000103027824 */
/* 0x000fca00078e0218 */
/*0fc0*/ IADD3 R3, R2, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x000fc80007ffe0ff */
/*0fd0*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*0fe0*/ @!P0 BRA 0x11f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0ff0*/ ISETP.GT.AND P0, PT, R2, 0xfe, PT ; /* 0x000000fe0200780c */
/* 0x000fda0003f04270 */
/*1000*/ @P0 BRA 0x11c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*1010*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*1020*/ @P0 BRA 0x1200 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*1030*/ ISETP.GE.AND P0, PT, R2, -0x18, PT ; /* 0xffffffe80200780c */
/* 0x000fe40003f06270 */
/*1040*/ LOP3.LUT R23, R23, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000017177812 */
/* 0x000fd600078ec0ff */
/*1050*/ @!P0 BRA 0x1200 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*1060*/ FFMA.RZ R3, R0, R21.reuse, R25.reuse ; /* 0x0000001500037223 */
/* 0x180fe2000000c019 */
/*1070*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f45270 */
/*1080*/ FFMA.RP R24, R0, R21.reuse, R25.reuse ; /* 0x0000001500187223 */
/* 0x180fe20000008019 */
/*1090*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*10a0*/ FFMA.RM R21, R0, R21, R25 ; /* 0x0000001500157223 */
/* 0x000fe20000004019 */
/*10b0*/ LOP3.LUT R3, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03037812 */
/* 0x000fe400078ec0ff */
/*10c0*/ IADD3 R0, R2, 0x20, RZ ; /* 0x0000002002007810 */
/* 0x000fe20007ffe0ff */
/*10d0*/ IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0a02 */
/*10e0*/ LOP3.LUT R3, R3, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000003037812 */
/* 0x000fe400078efcff */
/*10f0*/ FSETP.NEU.FTZ.AND P0, PT, R24, R21, PT ; /* 0x000000151800720b */
/* 0x000fc40003f1d000 */
/*1100*/ SHF.L.U32 R0, R3, R0, RZ ; /* 0x0000000003007219 */
/* 0x000fe400000006ff */
/*1110*/ SEL R2, R2, RZ, P2 ; /* 0x000000ff02027207 */
/* 0x000fe40001000000 */
/*1120*/ ISETP.NE.AND P1, PT, R0, RZ, P1 ; /* 0x000000ff0000720c */
/* 0x000fe40000f25270 */
/*1130*/ SHF.R.U32.HI R3, RZ, R2, R3 ; /* 0x00000002ff037219 */
/* 0x000fe40000011603 */
/*1140*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*1150*/ SHF.R.U32.HI R2, RZ, 0x1, R3 ; /* 0x00000001ff027819 */
/* 0x000fc40000011603 */
/*1160*/ SEL R21, RZ, 0x1, !P0 ; /* 0x00000001ff157807 */
/* 0x000fc80004000000 */
/*1170*/ LOP3.LUT R0, R21, 0x1, R2, 0xf8, !PT ; /* 0x0000000115007812 */
/* 0x000fc800078ef802 */
/*1180*/ LOP3.LUT R3, R0, R3, RZ, 0xc0, !PT ; /* 0x0000000300037212 */
/* 0x000fca00078ec0ff */
/*1190*/ IMAD.IADD R2, R2, 0x1, R3 ; /* 0x0000000102027824 */
/* 0x000fca00078e0203 */
/*11a0*/ LOP3.LUT R23, R2, R23, RZ, 0xfc, !PT ; /* 0x0000001702177212 */
/* 0x000fe200078efcff */
/*11b0*/ BRA 0x1200 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*11c0*/ LOP3.LUT R23, R23, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000017177812 */
/* 0x000fc800078ec0ff */
/*11d0*/ LOP3.LUT R23, R23, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000017177812 */
/* 0x000fe200078efcff */
/*11e0*/ BRA 0x1200 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*11f0*/ LEA R23, R24, R23, 0x17 ; /* 0x0000001718177211 */
/* 0x000fe400078eb8ff */
/*1200*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1210*/ BRA 0x12a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1220*/ LOP3.LUT R23, R26, 0x80000000, R23, 0x48, !PT ; /* 0x800000001a177812 */
/* 0x000fc800078e4817 */
/*1230*/ LOP3.LUT R23, R23, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000017177812 */
/* 0x000fe200078efcff */
/*1240*/ BRA 0x12a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1250*/ LOP3.LUT R23, R26, 0x80000000, R23, 0x48, !PT ; /* 0x800000001a177812 */
/* 0x000fe200078e4817 */
/*1260*/ BRA 0x12a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1270*/ MUFU.RSQ R23, -QNAN ; /* 0xffc0000000177908 */
/* 0x000e220000001400 */
/*1280*/ BRA 0x12a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1290*/ FADD.FTZ R23, R23, R6 ; /* 0x0000000617177221 */
/* 0x000fe40000010000 */
/*12a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*12b0*/ IMAD.MOV.U32 R0, RZ, RZ, R23 ; /* 0x000000ffff007224 */
/* 0x001fe400078e0017 */
/*12c0*/ IMAD.MOV.U32 R23, RZ, RZ, 0x0 ; /* 0x00000000ff177424 */
/* 0x000fc800078e00ff */
/*12d0*/ RET.REL.NODEC R22 0x0 ; /* 0xffffed2016007950 */
/* 0x000fea0003c3ffff */
/*12e0*/ BRA 0x12e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void bestFilterUpdate(const double *Params, const float *data, const float *mu, float *err, float *eloss, int *ftype, const int *st, const int *id, const int *counter){
int tid, ind, i,t, NT, Nfilt, ibest = 0, nt0;
float Cf, Cbest, lam, b, a, Cnextbest;
tid = threadIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
lam = (float) Params[7];
nt0 = (int) Params[4];
// we only need to compute this at updated locations
ind = counter[1] + blockIdx.x;
if (ind<counter[0]){
t = st[ind]-nt0 + tid;
if (t>=0 && t<NT){
Cbest = 0.0f;
for (i=0; i<Nfilt;i++){
a = 1+ lam;
b = max(0.0f, data[t + NT * i]) + lam * mu[i];
Cf = b*b/a - lam * mu[i]*mu[i];
if (Cf > Cbest + 1e-6){
Cnextbest = Cbest;
Cbest = Cf;
ibest = i;
}
else
if (Cf > Cnextbest + 1e-6)
Cnextbest = Cf;
}
err[t] = Cbest;
ftype[t] = ibest;
}
}
} | .file "tmpxft_00098d92_00000000-6_bestFilterUpdate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_
.type _Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_, @function
_Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_, .-_Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_
.globl _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.type _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, @function
_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, .-_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void bestFilterUpdate(const double *Params, const float *data, const float *mu, float *err, float *eloss, int *ftype, const int *st, const int *id, const int *counter){
int tid, ind, i,t, NT, Nfilt, ibest = 0, nt0;
float Cf, Cbest, lam, b, a, Cnextbest;
tid = threadIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
lam = (float) Params[7];
nt0 = (int) Params[4];
// we only need to compute this at updated locations
ind = counter[1] + blockIdx.x;
if (ind<counter[0]){
t = st[ind]-nt0 + tid;
if (t>=0 && t<NT){
Cbest = 0.0f;
for (i=0; i<Nfilt;i++){
a = 1+ lam;
b = max(0.0f, data[t + NT * i]) + lam * mu[i];
Cf = b*b/a - lam * mu[i]*mu[i];
if (Cf > Cbest + 1e-6){
Cnextbest = Cbest;
Cbest = Cf;
ibest = i;
}
else
if (Cf > Cnextbest + 1e-6)
Cnextbest = Cf;
}
err[t] = Cbest;
ftype[t] = ibest;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void bestFilterUpdate(const double *Params, const float *data, const float *mu, float *err, float *eloss, int *ftype, const int *st, const int *id, const int *counter){
int tid, ind, i,t, NT, Nfilt, ibest = 0, nt0;
float Cf, Cbest, lam, b, a, Cnextbest;
tid = threadIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
lam = (float) Params[7];
nt0 = (int) Params[4];
// we only need to compute this at updated locations
ind = counter[1] + blockIdx.x;
if (ind<counter[0]){
t = st[ind]-nt0 + tid;
if (t>=0 && t<NT){
Cbest = 0.0f;
for (i=0; i<Nfilt;i++){
a = 1+ lam;
b = max(0.0f, data[t + NT * i]) + lam * mu[i];
Cf = b*b/a - lam * mu[i]*mu[i];
if (Cf > Cbest + 1e-6){
Cnextbest = Cbest;
Cbest = Cf;
ibest = i;
}
else
if (Cf > Cnextbest + 1e-6)
Cnextbest = Cf;
}
err[t] = Cbest;
ftype[t] = ibest;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void bestFilterUpdate(const double *Params, const float *data, const float *mu, float *err, float *eloss, int *ftype, const int *st, const int *id, const int *counter){
int tid, ind, i,t, NT, Nfilt, ibest = 0, nt0;
float Cf, Cbest, lam, b, a, Cnextbest;
tid = threadIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
lam = (float) Params[7];
nt0 = (int) Params[4];
// we only need to compute this at updated locations
ind = counter[1] + blockIdx.x;
if (ind<counter[0]){
t = st[ind]-nt0 + tid;
if (t>=0 && t<NT){
Cbest = 0.0f;
for (i=0; i<Nfilt;i++){
a = 1+ lam;
b = max(0.0f, data[t + NT * i]) + lam * mu[i];
Cf = b*b/a - lam * mu[i]*mu[i];
if (Cf > Cbest + 1e-6){
Cnextbest = Cbest;
Cbest = Cf;
ibest = i;
}
else
if (Cf > Cnextbest + 1e-6)
Cnextbest = Cf;
}
err[t] = Cbest;
ftype[t] = ibest;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.globl _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.p2align 8
.type _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_,@function
_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_:
s_load_b64 s[2:3], s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s5, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s2, s4
s_cbranch_scc1 .LBB0_12
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x30
s_ashr_i32 s3, s2, 31
s_waitcnt lgkmcnt(0)
s_clause 0x1
s_load_b64 s[8:9], s[4:5], 0x20
s_load_b64 s[10:11], s[4:5], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v1, s[8:9]
v_cvt_i32_f64_e32 v4, s[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, s2, v1
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
v_cmp_lt_i32_e64 s2, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
s_load_b64 s[2:3], s[4:5], 0x8
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v5, s[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v5
s_cbranch_vccnz .LBB0_10
s_load_b64 s[2:3], s[4:5], 0x38
s_load_b128 s[4:7], s[0:1], 0x8
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_f64_e32 v6, s[2:3]
s_mov_b32 s3, 0x3eb0c6f7
s_mov_b32 s2, 0xa0b5ed8d
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v7, 1.0, v6
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s9, s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_max_f32_e32 v2, v2, v2
v_max_f32_e32 v2, 0, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, s9, v6
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v7, v7, v2
v_div_scale_f32 v14, vcc_lo, v2, v7, v2
v_rcp_f32_e32 v11, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v3, v11, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v12, v11
v_cvt_f64_f32_e32 v[12:13], v8
v_mul_f32_e32 v15, v14, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v3, v15, v14
v_fmac_f32_e32 v15, v16, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v15, v14
v_div_fmas_f32 v3, v3, v11, v15
v_mul_f32_e32 v11, s9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v7, v2
v_fma_f32 v11, -s9, v11, v2
v_add_f64 v[12:13], v[12:13], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v11
v_cmp_nlt_f64_e32 vcc_lo, v[12:13], v[2:3]
v_mov_b32_e32 v12, s8
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_8
v_cvt_f64_f32_e32 v[12:13], v10
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[12:13], s[2:3]
v_cmpx_lt_f64_e32 v[12:13], v[2:3]
v_mov_b32_e32 v10, v11
s_or_b32 exec_lo, exec_lo, s10
v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v9
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v8, v10
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s9
s_add_i32 s8, s8, 1
v_add_nc_u32_e32 v1, v1, v4
v_cmp_ne_u32_e32 vcc_lo, s8, v5
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cbranch_vccz .LBB0_11
v_mov_b32_e32 v10, v8
v_dual_mov_b32 v9, v12 :: v_dual_mov_b32 v8, v11
s_branch .LBB0_4
.LBB0_10:
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v11, 0
.LBB0_11:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x28
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[2:3], v11, off
global_store_b32 v[0:1], v12, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, .Lfunc_end0-_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void bestFilterUpdate(const double *Params, const float *data, const float *mu, float *err, float *eloss, int *ftype, const int *st, const int *id, const int *counter){
int tid, ind, i,t, NT, Nfilt, ibest = 0, nt0;
float Cf, Cbest, lam, b, a, Cnextbest;
tid = threadIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
lam = (float) Params[7];
nt0 = (int) Params[4];
// we only need to compute this at updated locations
ind = counter[1] + blockIdx.x;
if (ind<counter[0]){
t = st[ind]-nt0 + tid;
if (t>=0 && t<NT){
Cbest = 0.0f;
for (i=0; i<Nfilt;i++){
a = 1+ lam;
b = max(0.0f, data[t + NT * i]) + lam * mu[i];
Cf = b*b/a - lam * mu[i]*mu[i];
if (Cf > Cbest + 1e-6){
Cnextbest = Cbest;
Cbest = Cf;
ibest = i;
}
else
if (Cf > Cnextbest + 1e-6)
Cnextbest = Cf;
}
err[t] = Cbest;
ftype[t] = ibest;
}
}
} | .text
.file "bestFilterUpdate.hip"
.globl _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_ # -- Begin function _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.p2align 4, 0x90
.type _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_,@function
_Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_: # @_Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, .Lfunc_end0-_Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_,@object # @_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.section .rodata,"a",@progbits
.globl _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.p2align 3, 0x0
_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_:
.quad _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.size _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00098d92_00000000-6_bestFilterUpdate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_
.type _Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_, @function
_Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_, .-_Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_
.globl _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.type _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, @function
_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z59__device_stub__Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_PKdPKfS2_PfS3_PiPKiS6_S6_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, .-_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bestFilterUpdate.hip"
.globl _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_ # -- Begin function _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.p2align 4, 0x90
.type _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_,@function
_Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_: # @_Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, .Lfunc_end0-_Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_,@object # @_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.section .rodata,"a",@progbits
.globl _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.p2align 3, 0x0
_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_:
.quad _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.size _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16bestFilterUpdatePKdPKfS2_PfS3_PiPKiS6_S6_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
#include <stdio.h>
__global__ void add(int n, float *x, float *y, float *c) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= n) {
return;
}
c[idx] = x[idx] + y[idx];
}
void FillWithData(int n, float* x, float* y) {
for (int i = 0; i < n; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
}
void FillWith(int n, float value, float* x) {
for (int i = 0; i < n; i++) {
x[i] = value;
}
}
void CheckCudaError() {
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) {
printf("Error: %s\n", cudaGetErrorString(err));
exit(-1);
}
}
int main(void) {
int N = 1<<20;
// int N = 200000;
//int N = 1024;
// int N = 1 << 20;
float *x, *y, *c;
float *d_x, *d_y, *d_c;
int size = N * sizeof(float);
x = (float*) malloc(size);
y = (float*) malloc(size);
c = (float*) malloc(size);
FillWithData(N, x, y);
FillWith(N, 0.0f, c);
cudaMalloc(&d_x, size);
cudaMalloc(&d_y, size);
cudaMalloc(&d_c, size);
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
add<<<N/(1024-1), 1024>>>(N, d_x, d_y, d_c);
CheckCudaError();
cudaDeviceSynchronize();
// cudaDeviceSync();
// cudaMemcpy(x, d_x, size, cudaMemcpyDeviceToHost);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
int i = 0;
int sample_rate = N / 100;
for (i = 0; i < N; i=i+sample_rate) {
printf("Value %d - %f + %f = %f\n" , i, x[i], y[i], c[i]);
}
// Free memory
free(x); free(y);
cudaFree(d_x); cudaFree(d_y);
return 0;
} | code for sm_80
Function : _Z3addiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
#include <stdio.h>
__global__ void add(int n, float *x, float *y, float *c) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= n) {
return;
}
c[idx] = x[idx] + y[idx];
}
void FillWithData(int n, float* x, float* y) {
for (int i = 0; i < n; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
}
void FillWith(int n, float value, float* x) {
for (int i = 0; i < n; i++) {
x[i] = value;
}
}
void CheckCudaError() {
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) {
printf("Error: %s\n", cudaGetErrorString(err));
exit(-1);
}
}
int main(void) {
int N = 1<<20;
// int N = 200000;
//int N = 1024;
// int N = 1 << 20;
float *x, *y, *c;
float *d_x, *d_y, *d_c;
int size = N * sizeof(float);
x = (float*) malloc(size);
y = (float*) malloc(size);
c = (float*) malloc(size);
FillWithData(N, x, y);
FillWith(N, 0.0f, c);
cudaMalloc(&d_x, size);
cudaMalloc(&d_y, size);
cudaMalloc(&d_c, size);
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
add<<<N/(1024-1), 1024>>>(N, d_x, d_y, d_c);
CheckCudaError();
cudaDeviceSynchronize();
// cudaDeviceSync();
// cudaMemcpy(x, d_x, size, cudaMemcpyDeviceToHost);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
int i = 0;
int sample_rate = N / 100;
for (i = 0; i < N; i=i+sample_rate) {
printf("Value %d - %f + %f = %f\n" , i, x[i], y[i], c[i]);
}
// Free memory
free(x); free(y);
cudaFree(d_x); cudaFree(d_y);
return 0;
} | .file "tmpxft_00003fac_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12FillWithDataiPfS_
.type _Z12FillWithDataiPfS_, @function
_Z12FillWithDataiPfS_:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L5:
movss %xmm1, (%rsi,%rax)
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z12FillWithDataiPfS_, .-_Z12FillWithDataiPfS_
.globl _Z8FillWithifPf
.type _Z8FillWithifPf, @function
_Z8FillWithifPf:
.LFB3670:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L7
movq %rsi, %rax
movslq %edi, %rdi
leaq (%rsi,%rdi,4), %rdx
.L9:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE3670:
.size _Z8FillWithifPf, .-_Z8FillWithifPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Error: %s\n"
.text
.globl _Z14CheckCudaErrorv
.type _Z14CheckCudaErrorv, @function
_Z14CheckCudaErrorv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L14
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3671:
.size _Z14CheckCudaErrorv, .-_Z14CheckCudaErrorv
.globl _Z27__device_stub__Z3addiPfS_S_iPfS_S_
.type _Z27__device_stub__Z3addiPfS_S_iPfS_S_, @function
_Z27__device_stub__Z3addiPfS_S_iPfS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z27__device_stub__Z3addiPfS_S_iPfS_S_, .-_Z27__device_stub__Z3addiPfS_S_iPfS_S_
.globl _Z3addiPfS_S_
.type _Z3addiPfS_S_, @function
_Z3addiPfS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z3addiPfS_S_, .-_Z3addiPfS_S_
.section .rodata.str1.1
.LC4:
.string "Value %d - %f + %f = %f\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdx
movq %r12, %rsi
movl $1048576, %edi
call _Z12FillWithDataiPfS_
movq %r13, %rsi
pxor %xmm0, %xmm0
movl $1048576, %edi
call _Z8FillWithifPf
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1025, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L24:
call _Z14CheckCudaErrorv
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC4(%rip), %r14
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 0(%r13,%rbx,4), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%rbx,4), %xmm1
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $10485, %rbx
cmpq $1058985, %rbx
jne .L25
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $1048576, %edi
call _Z27__device_stub__Z3addiPfS_S_iPfS_S_
jmp .L24
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3addiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <stdio.h>
__global__ void add(int n, float *x, float *y, float *c) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= n) {
return;
}
c[idx] = x[idx] + y[idx];
}
void FillWithData(int n, float* x, float* y) {
for (int i = 0; i < n; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
}
void FillWith(int n, float value, float* x) {
for (int i = 0; i < n; i++) {
x[i] = value;
}
}
void CheckCudaError() {
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) {
printf("Error: %s\n", cudaGetErrorString(err));
exit(-1);
}
}
int main(void) {
int N = 1<<20;
// int N = 200000;
//int N = 1024;
// int N = 1 << 20;
float *x, *y, *c;
float *d_x, *d_y, *d_c;
int size = N * sizeof(float);
x = (float*) malloc(size);
y = (float*) malloc(size);
c = (float*) malloc(size);
FillWithData(N, x, y);
FillWith(N, 0.0f, c);
cudaMalloc(&d_x, size);
cudaMalloc(&d_y, size);
cudaMalloc(&d_c, size);
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
add<<<N/(1024-1), 1024>>>(N, d_x, d_y, d_c);
CheckCudaError();
cudaDeviceSynchronize();
// cudaDeviceSync();
// cudaMemcpy(x, d_x, size, cudaMemcpyDeviceToHost);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
int i = 0;
int sample_rate = N / 100;
for (i = 0; i < N; i=i+sample_rate) {
printf("Value %d - %f + %f = %f\n" , i, x[i], y[i], c[i]);
}
// Free memory
free(x); free(y);
cudaFree(d_x); cudaFree(d_y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <stdio.h>
__global__ void add(int n, float *x, float *y, float *c) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= n) {
return;
}
c[idx] = x[idx] + y[idx];
}
void FillWithData(int n, float* x, float* y) {
for (int i = 0; i < n; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
}
void FillWith(int n, float value, float* x) {
for (int i = 0; i < n; i++) {
x[i] = value;
}
}
void CheckCudaError() {
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
printf("Error: %s\n", hipGetErrorString(err));
exit(-1);
}
}
int main(void) {
int N = 1<<20;
// int N = 200000;
//int N = 1024;
// int N = 1 << 20;
float *x, *y, *c;
float *d_x, *d_y, *d_c;
int size = N * sizeof(float);
x = (float*) malloc(size);
y = (float*) malloc(size);
c = (float*) malloc(size);
FillWithData(N, x, y);
FillWith(N, 0.0f, c);
hipMalloc(&d_x, size);
hipMalloc(&d_y, size);
hipMalloc(&d_c, size);
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
add<<<N/(1024-1), 1024>>>(N, d_x, d_y, d_c);
CheckCudaError();
hipDeviceSynchronize();
// cudaDeviceSync();
// cudaMemcpy(x, d_x, size, cudaMemcpyDeviceToHost);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
int i = 0;
int sample_rate = N / 100;
for (i = 0; i < N; i=i+sample_rate) {
printf("Value %d - %f + %f = %f\n" , i, x[i], y[i], c[i]);
}
// Free memory
free(x); free(y);
hipFree(d_x); hipFree(d_y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <stdio.h>
__global__ void add(int n, float *x, float *y, float *c) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= n) {
return;
}
c[idx] = x[idx] + y[idx];
}
void FillWithData(int n, float* x, float* y) {
for (int i = 0; i < n; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
}
void FillWith(int n, float value, float* x) {
for (int i = 0; i < n; i++) {
x[i] = value;
}
}
void CheckCudaError() {
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
printf("Error: %s\n", hipGetErrorString(err));
exit(-1);
}
}
int main(void) {
int N = 1<<20;
// int N = 200000;
//int N = 1024;
// int N = 1 << 20;
float *x, *y, *c;
float *d_x, *d_y, *d_c;
int size = N * sizeof(float);
x = (float*) malloc(size);
y = (float*) malloc(size);
c = (float*) malloc(size);
FillWithData(N, x, y);
FillWith(N, 0.0f, c);
hipMalloc(&d_x, size);
hipMalloc(&d_y, size);
hipMalloc(&d_c, size);
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
add<<<N/(1024-1), 1024>>>(N, d_x, d_y, d_c);
CheckCudaError();
hipDeviceSynchronize();
// cudaDeviceSync();
// cudaMemcpy(x, d_x, size, cudaMemcpyDeviceToHost);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
int i = 0;
int sample_rate = N / 100;
for (i = 0; i < N; i=i+sample_rate) {
printf("Value %d - %f + %f = %f\n" , i, x[i], y[i], c[i]);
}
// Free memory
free(x); free(y);
hipFree(d_x); hipFree(d_y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_S_
.globl _Z3addiPfS_S_
.p2align 8
.type _Z3addiPfS_S_,@function
_Z3addiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_S_, .Lfunc_end0-_Z3addiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <stdio.h>
__global__ void add(int n, float *x, float *y, float *c) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= n) {
return;
}
c[idx] = x[idx] + y[idx];
}
void FillWithData(int n, float* x, float* y) {
for (int i = 0; i < n; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
}
void FillWith(int n, float value, float* x) {
for (int i = 0; i < n; i++) {
x[i] = value;
}
}
void CheckCudaError() {
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
printf("Error: %s\n", hipGetErrorString(err));
exit(-1);
}
}
int main(void) {
int N = 1<<20;
// int N = 200000;
//int N = 1024;
// int N = 1 << 20;
float *x, *y, *c;
float *d_x, *d_y, *d_c;
int size = N * sizeof(float);
x = (float*) malloc(size);
y = (float*) malloc(size);
c = (float*) malloc(size);
FillWithData(N, x, y);
FillWith(N, 0.0f, c);
hipMalloc(&d_x, size);
hipMalloc(&d_y, size);
hipMalloc(&d_c, size);
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
add<<<N/(1024-1), 1024>>>(N, d_x, d_y, d_c);
CheckCudaError();
hipDeviceSynchronize();
// cudaDeviceSync();
// cudaMemcpy(x, d_x, size, cudaMemcpyDeviceToHost);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
int i = 0;
int sample_rate = N / 100;
for (i = 0; i < N; i=i+sample_rate) {
printf("Value %d - %f + %f = %f\n" , i, x[i], y[i], c[i]);
}
// Free memory
free(x); free(y);
hipFree(d_x); hipFree(d_y);
return 0;
} | .text
.file "vector_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_S_ # -- Begin function _Z18__device_stub__addiPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_S_,@function
_Z18__device_stub__addiPfS_S_: # @_Z18__device_stub__addiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_S_, .Lfunc_end0-_Z18__device_stub__addiPfS_S_
.cfi_endproc
# -- End function
.globl _Z12FillWithDataiPfS_ # -- Begin function _Z12FillWithDataiPfS_
.p2align 4, 0x90
.type _Z12FillWithDataiPfS_,@function
_Z12FillWithDataiPfS_: # @_Z12FillWithDataiPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rsi,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z12FillWithDataiPfS_, .Lfunc_end1-_Z12FillWithDataiPfS_
.cfi_endproc
# -- End function
.globl _Z8FillWithifPf # -- Begin function _Z8FillWithifPf
.p2align 4, 0x90
.type _Z8FillWithifPf,@function
_Z8FillWithifPf: # @_Z8FillWithifPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z8FillWithifPf, .Lfunc_end2-_Z8FillWithifPf
.cfi_endproc
# -- End function
.globl _Z14CheckCudaErrorv # -- Begin function _Z14CheckCudaErrorv
.p2align 4, 0x90
.type _Z14CheckCudaErrorv,@function
_Z14CheckCudaErrorv: # @_Z14CheckCudaErrorv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %eax, %eax
jne .LBB3_2
# %bb.1:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end3:
.size _Z14CheckCudaErrorv, .Lfunc_end3-_Z14CheckCudaErrorv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB4_1
# %bb.2: # %.lr.ph.i35.preheader
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_8
# %bb.5: # %_Z14CheckCudaErrorv.exit
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_6: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r15,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.1, %edi
movl %r12d, %esi
movb $3, %al
callq printf
leaq 10485(%r12), %rax
cmpq $1038091, %r12 # imm = 0xFD70B
movq %rax, %r12
jb .LBB4_6
# %bb.7:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_8:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_S_,@object # @_Z3addiPfS_S_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_S_
.p2align 3, 0x0
_Z3addiPfS_S_:
.quad _Z18__device_stub__addiPfS_S_
.size _Z3addiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Value %d - %f + %f = %f\n"
.size .L.str.1, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_S_
.globl _Z3addiPfS_S_
.p2align 8
.type _Z3addiPfS_S_,@function
_Z3addiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_S_, .Lfunc_end0-_Z3addiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00003fac_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12FillWithDataiPfS_
.type _Z12FillWithDataiPfS_, @function
_Z12FillWithDataiPfS_:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L5:
movss %xmm1, (%rsi,%rax)
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z12FillWithDataiPfS_, .-_Z12FillWithDataiPfS_
.globl _Z8FillWithifPf
.type _Z8FillWithifPf, @function
_Z8FillWithifPf:
.LFB3670:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L7
movq %rsi, %rax
movslq %edi, %rdi
leaq (%rsi,%rdi,4), %rdx
.L9:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE3670:
.size _Z8FillWithifPf, .-_Z8FillWithifPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Error: %s\n"
.text
.globl _Z14CheckCudaErrorv
.type _Z14CheckCudaErrorv, @function
_Z14CheckCudaErrorv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L14
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3671:
.size _Z14CheckCudaErrorv, .-_Z14CheckCudaErrorv
.globl _Z27__device_stub__Z3addiPfS_S_iPfS_S_
.type _Z27__device_stub__Z3addiPfS_S_iPfS_S_, @function
_Z27__device_stub__Z3addiPfS_S_iPfS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z27__device_stub__Z3addiPfS_S_iPfS_S_, .-_Z27__device_stub__Z3addiPfS_S_iPfS_S_
.globl _Z3addiPfS_S_
.type _Z3addiPfS_S_, @function
_Z3addiPfS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z3addiPfS_S_, .-_Z3addiPfS_S_
.section .rodata.str1.1
.LC4:
.string "Value %d - %f + %f = %f\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdx
movq %r12, %rsi
movl $1048576, %edi
call _Z12FillWithDataiPfS_
movq %r13, %rsi
pxor %xmm0, %xmm0
movl $1048576, %edi
call _Z8FillWithifPf
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1025, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L24:
call _Z14CheckCudaErrorv
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC4(%rip), %r14
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 0(%r13,%rbx,4), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%rbx,4), %xmm1
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $10485, %rbx
cmpq $1058985, %rbx
jne .L25
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $1048576, %edi
call _Z27__device_stub__Z3addiPfS_S_iPfS_S_
jmp .L24
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3addiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_S_ # -- Begin function _Z18__device_stub__addiPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_S_,@function
_Z18__device_stub__addiPfS_S_: # @_Z18__device_stub__addiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_S_, .Lfunc_end0-_Z18__device_stub__addiPfS_S_
.cfi_endproc
# -- End function
.globl _Z12FillWithDataiPfS_ # -- Begin function _Z12FillWithDataiPfS_
.p2align 4, 0x90
.type _Z12FillWithDataiPfS_,@function
_Z12FillWithDataiPfS_: # @_Z12FillWithDataiPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rsi,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z12FillWithDataiPfS_, .Lfunc_end1-_Z12FillWithDataiPfS_
.cfi_endproc
# -- End function
.globl _Z8FillWithifPf # -- Begin function _Z8FillWithifPf
.p2align 4, 0x90
.type _Z8FillWithifPf,@function
_Z8FillWithifPf: # @_Z8FillWithifPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z8FillWithifPf, .Lfunc_end2-_Z8FillWithifPf
.cfi_endproc
# -- End function
.globl _Z14CheckCudaErrorv # -- Begin function _Z14CheckCudaErrorv
.p2align 4, 0x90
.type _Z14CheckCudaErrorv,@function
_Z14CheckCudaErrorv: # @_Z14CheckCudaErrorv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %eax, %eax
jne .LBB3_2
# %bb.1:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end3:
.size _Z14CheckCudaErrorv, .Lfunc_end3-_Z14CheckCudaErrorv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB4_1
# %bb.2: # %.lr.ph.i35.preheader
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_8
# %bb.5: # %_Z14CheckCudaErrorv.exit
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_6: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r15,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.1, %edi
movl %r12d, %esi
movb $3, %al
callq printf
leaq 10485(%r12), %rax
cmpq $1038091, %r12 # imm = 0xFD70B
movq %rax, %r12
jb .LBB4_6
# %bb.7:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_8:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_S_,@object # @_Z3addiPfS_S_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_S_
.p2align 3, 0x0
_Z3addiPfS_S_:
.quad _Z18__device_stub__addiPfS_S_
.size _Z3addiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %s\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Value %d - %f + %f = %f\n"
.size .L.str.1, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <limits>
void GetInt(int *in)
{
if (!std::cin)
{
std::cin.clear();
std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
}
std::cin>>*in;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <limits>
void GetInt(int *in)
{
if (!std::cin)
{
std::cin.clear();
std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
}
std::cin>>*in;
} | .file "tmpxft_00156c92_00000000-6_Function.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6GetIntPi
.type _Z6GetIntPi, @function
_Z6GetIntPi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
testb $5, 48+_ZSt3cin(%rip)
jne .L6
.L4:
movq %rbx, %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl $0, %esi
leaq 16+_ZSt3cin(%rip), %rdi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
movl $10, %edx
movabsq $9223372036854775807, %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSi6ignoreEli@PLT
jmp .L4
.cfi_endproc
.LFE3669:
.size _Z6GetIntPi, .-_Z6GetIntPi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <limits>
void GetInt(int *in)
{
if (!std::cin)
{
std::cin.clear();
std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
}
std::cin>>*in;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <limits>
void GetInt(int *in)
{
if (!std::cin)
{
std::cin.clear();
std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
}
std::cin>>*in;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <limits>
void GetInt(int *in)
{
if (!std::cin)
{
std::cin.clear();
std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
}
std::cin>>*in;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <limits>
void GetInt(int *in)
{
if (!std::cin)
{
std::cin.clear();
std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
}
std::cin>>*in;
} | .text
.file "Function.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6GetIntPi # -- Begin function _Z6GetIntPi
.p2align 4, 0x90
.type _Z6GetIntPi,@function
_Z6GetIntPi: # @_Z6GetIntPi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq _ZSt3cin(%rip), %rax
movq -24(%rax), %rax
testb $5, _ZSt3cin+32(%rax)
je .LBB0_2
# %bb.1:
leaq _ZSt3cin(%rax), %rdi
xorl %esi, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
movl $_ZSt3cin, %edi
movl $10, %edx
callq _ZNSi6ignoreEli
.LBB0_2:
movl $_ZSt3cin, %edi
movq %rbx, %rsi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSirsERi # TAILCALL
.Lfunc_end0:
.size _Z6GetIntPi, .Lfunc_end0-_Z6GetIntPi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00156c92_00000000-6_Function.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6GetIntPi
.type _Z6GetIntPi, @function
_Z6GetIntPi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
testb $5, 48+_ZSt3cin(%rip)
jne .L6
.L4:
movq %rbx, %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl $0, %esi
leaq 16+_ZSt3cin(%rip), %rdi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
movl $10, %edx
movabsq $9223372036854775807, %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSi6ignoreEli@PLT
jmp .L4
.cfi_endproc
.LFE3669:
.size _Z6GetIntPi, .-_Z6GetIntPi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Function.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6GetIntPi # -- Begin function _Z6GetIntPi
.p2align 4, 0x90
.type _Z6GetIntPi,@function
_Z6GetIntPi: # @_Z6GetIntPi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq _ZSt3cin(%rip), %rax
movq -24(%rax), %rax
testb $5, _ZSt3cin+32(%rax)
je .LBB0_2
# %bb.1:
leaq _ZSt3cin(%rax), %rdi
xorl %esi, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
movl $_ZSt3cin, %edi
movl $10, %edx
callq _ZNSi6ignoreEli
.LBB0_2:
movl $_ZSt3cin, %edi
movq %rbx, %rsi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSirsERi # TAILCALL
.Lfunc_end0:
.size _Z6GetIntPi, .Lfunc_end0-_Z6GetIntPi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************************
* PROGRAM: copyStruture
* PURPOSE: This program is a test which test the ability to transfer multilevel
* C++ structured data from host to device, modify them and transfer back.
*
*
* NAME: Vuong Pham-Duy.
* College student.
* Faculty of Computer Science and Technology.
* Ho Chi Minh University of Technology, Viet Nam.
* vuongpd95@gmail.com
*
* DATE: 5/10/2017
*
******************************************************************************/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", \
cudaGetErrorString(code), file, line);
if (abort)
exit(code);
}
}
/* Structure *****************************************************************/
typedef struct {
int64_t rbeg;
int32_t qbeg, len;
int score;
} mem_seed_t; // unaligned memory
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
mem_seed_t *seeds;
} mem_chain_t;
typedef struct {
size_t n, m;
mem_chain_t *a;
} mem_chain_v;
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
} flat_mem_chain_t;
typedef struct {
size_t n, m;
} flat_mem_chain_v;
__global__ void func(int n, int n_a, int n_seeds, flat_mem_chain_v *chns, \
flat_mem_chain_t *a, mem_seed_t *seeds, int *d_b) {
int i, j;
*d_b = 0;
for(i = 0; i < n; i++) {
*d_b += chns[i].n;
for(j = 0; j < n_a; j++) {
*d_b += a[j].n;
}
}
}
/* Structure *****************************************************************/
int main(int argc, char *argv[])
{
// Assumptions
int b;
int *d_b;
gpuErrchk(cudaMalloc(&d_b, sizeof(int)));
// Begin Assumptions
int n, i, j, k;
n = 10;
mem_chain_v *chns;
chns = (mem_chain_v*)malloc(sizeof(mem_chain_v) * n);
for(i = 0; i < n; i++) {
chns[i].n = 10;
chns[i].a = (mem_chain_t*)malloc(\
chns[i].n * sizeof(mem_chain_t));
for(j = 0; j < chns[i].n; j++) {
chns[i].a[j].n = 10;
chns[i].a[j].seeds = (mem_seed_t*)malloc(\
chns[i].a[j].n * sizeof(mem_seed_t));
for(k = 0; k < chns[i].a[j].n; k++) {
chns[i].a[j].seeds[k].score = i + j + k;
}
}
}
// End Assumptions
int n_a, n_seeds;
n_a = 0; n_seeds = 0;
for(i = 0; i < n; i++) {
n_a += chns[i].n;
for(j = 0; j < chns[i].n; j++) {
n_seeds += chns[i].a[j].n;
}
}
flat_mem_chain_v *f_chns, *df_chns;
flat_mem_chain_t *f_a, *df_a;
mem_seed_t *seeds, *d_seeds;
// Flattened the nested structure
f_chns = (flat_mem_chain_v*)malloc(n * sizeof(flat_mem_chain_v));
f_a = (flat_mem_chain_t*)malloc(n_a * sizeof(flat_mem_chain_t));
seeds = (mem_seed_t*)malloc(n_seeds * sizeof(mem_seed_t));
int acc_a, acc_seeds;
acc_a = 0; acc_seeds = 0;
for(i = 0; i < n; i++) {
f_chns[i].n = chns[i].n;
f_chns[i].m = chns[i].m;
for(j = 0; j < chns[i].n; j++) {
// int n, m, first, rid;
// uint32_t w:29, kept:2, is_alt:1;
// float frac_rep;
// int64_t pos;
mem_chain_t *tmp;
tmp = &chns[i].a[j];
f_a[acc_a].n = tmp->n;
f_a[acc_a].m = tmp->m;
f_a[acc_a].first = tmp->first;
f_a[acc_a].rid = tmp->rid;
f_a[acc_a].w = tmp->w;
f_a[acc_a].kept = tmp->kept;
f_a[acc_a].is_alt = tmp->is_alt;
f_a[acc_a].frac_rep = tmp->frac_rep;
f_a[acc_a].pos = tmp->pos;
for(k = 0; k < chns[i].a[j].n; k++) {
// int64_t rbeg;
// int32_t qbeg, len;
// int score;
mem_seed_t *tmp0;
tmp0 = &chns[i].a[j].seeds[k];
seeds[acc_seeds].rbeg = tmp0->rbeg;
seeds[acc_seeds].qbeg = tmp0->qbeg;
seeds[acc_seeds].len = tmp0->len;
seeds[acc_seeds].score = tmp0->score;
}
acc_seeds += chns[i].a[j].n;
}
acc_a += chns[i].n;
}
// Copy the flattened structure to kernel
gpuErrchk(cudaMalloc(&df_chns, n * sizeof(flat_mem_chain_v)));
gpuErrchk(cudaMalloc(&df_a, n_a * sizeof(flat_mem_chain_t)));
gpuErrchk(cudaMalloc(&d_seeds, n_seeds * sizeof(mem_seed_t)));
gpuErrchk(cudaMemcpy(df_chns, f_chns, n * sizeof(flat_mem_chain_v), \
cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(df_a, f_a, n_a * sizeof(flat_mem_chain_t), \
cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_seeds, seeds, n_seeds * sizeof(mem_seed_t), \
cudaMemcpyHostToDevice));
printf("n = %d, n_a = %d\n", n, n_a);
func<<<1, 1>>>(n, n_a, n_seeds, df_chns, df_a, d_seeds, d_b);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(&b, d_b, sizeof(int), cudaMemcpyDeviceToHost));
printf("d_b = %d\n", b);
cudaFree(df_chns);
cudaFree(df_a);
cudaFree(d_seeds);
cudaFree(d_b);
return 0;
} | code for sm_80
Function : _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x18c] ; /* 0x0000630000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f06270 */
/*0060*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f6000c101904 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x001fda0003f01270 */
/*0090*/ @P0 BRA 0x950 ; /* 0x000008b000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*00c0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd800078e00ff */
/*00f0*/ @!P0 BRA 0x890 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R5, -R0, c[0x0][0x160], RZ ; /* 0x0000580000057a10 */
/* 0x000fe20007ffe1ff */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*0120*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f04270 */
/*0130*/ @!P0 BRA 0x770 ; /* 0x0000063000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x540 ; /* 0x000003d000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ HFMA2.MMA R7, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff077435 */
/* 0x000fd400000001ff */
/*0190*/ IMAD.WIDE R8, R4, R7, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x004fca00078e0207 */
/*01a0*/ LDG.E R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ IMAD.IADD R13, R6, 0x1, R11 ; /* 0x00000001060d7824 */
/* 0x004fca00078e020b */
/*01c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*01d0*/ LDG.E R6, [R8.64+0x10] ; /* 0x0000100408067981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ IMAD.IADD R15, R13, 0x1, R6 ; /* 0x000000010d0f7824 */
/* 0x004fca00078e0206 */
/*01f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0200*/ LDG.E R6, [R8.64+0x20] ; /* 0x0000200408067981 */
/* 0x000ea4000c1e1900 */
/*0210*/ IMAD.IADD R17, R15, 0x1, R6 ; /* 0x000000010f117824 */
/* 0x004fca00078e0206 */
/*0220*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*0230*/ LDG.E R6, [R8.64+0x30] ; /* 0x0000300408067981 */
/* 0x000ee2000c1e1900 */
/*0240*/ IADD3 R10, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.WIDE R10, R10, R7, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fe200078e0207 */
/*0260*/ IADD3 R19, R17, R6, RZ ; /* 0x0000000611137210 */
/* 0x008fca0007ffe0ff */
/*0270*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0007e8000c101904 */
/*0280*/ LDG.E R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x000e24000c1e1900 */
/*0290*/ IMAD.IADD R13, R19, 0x1, R6 ; /* 0x00000001130d7824 */
/* 0x001fca00078e0206 */
/*02a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R6, [R10.64+0x10] ; /* 0x000010040a067981 */
/* 0x000e64000c1e1900 */
/*02c0*/ IMAD.IADD R15, R13, 0x1, R6 ; /* 0x000000010d0f7824 */
/* 0x002fca00078e0206 */
/*02d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R6, [R10.64+0x20] ; /* 0x000020040a067981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IMAD.IADD R17, R15, 0x1, R6 ; /* 0x000000010f117824 */
/* 0x004fca00078e0206 */
/*0300*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R6, [R10.64+0x30] ; /* 0x000030040a067981 */
/* 0x000ee2000c1e1900 */
/*0320*/ IADD3 R8, R4, 0x8, RZ ; /* 0x0000000804087810 */
/* 0x000fca0007ffe0ff */
/*0330*/ IMAD.WIDE R8, R8, R7, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0207 */
/*0340*/ IADD3 R19, R17, R6, RZ ; /* 0x0000000611137210 */
/* 0x008fca0007ffe0ff */
/*0350*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0360*/ LDG.E R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000e24000c1e1900 */
/*0370*/ IMAD.IADD R13, R19, 0x1, R6 ; /* 0x00000001130d7824 */
/* 0x001fca00078e0206 */
/*0380*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R6, [R8.64+0x10] ; /* 0x0000100408067981 */
/* 0x000e64000c1e1900 */
/*03a0*/ IMAD.IADD R15, R13, 0x1, R6 ; /* 0x000000010d0f7824 */
/* 0x002fca00078e0206 */
/*03b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R6, [R8.64+0x20] ; /* 0x0000200408067981 */
/* 0x000ee4000c1e1900 */
/*03d0*/ IMAD.IADD R11, R15, 0x1, R6 ; /* 0x000000010f0b7824 */
/* 0x008fca00078e0206 */
/*03e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e8000c101904 */
/*03f0*/ LDG.E R6, [R8.64+0x30] ; /* 0x0000300408067981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IADD3 R10, R4, 0xc, RZ ; /* 0x0000000c040a7810 */
/* 0x000fe40007ffe0ff */
/*0410*/ IADD3 R17, R11, R6, RZ ; /* 0x000000060b117210 */
/* 0x004fc60007ffe0ff */
/*0420*/ IMAD.WIDE R6, R10, R7, c[0x0][0x170] ; /* 0x00005c000a067625 */
/* 0x000fe400078e0207 */
/*0430*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*0440*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000e24000c1e1900 */
/*0450*/ IMAD.IADD R13, R17, 0x1, R10 ; /* 0x00000001110d7824 */
/* 0x001fca00078e020a */
/*0460*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0470*/ LDG.E R10, [R6.64+0x10] ; /* 0x00001004060a7981 */
/* 0x000e64000c1e1900 */
/*0480*/ IMAD.IADD R15, R13, 0x1, R10 ; /* 0x000000010d0f7824 */
/* 0x002fca00078e020a */
/*0490*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*04a0*/ LDG.E R8, [R6.64+0x20] ; /* 0x0000200406087981 */
/* 0x000f22000c1e1900 */
/*04b0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ IMAD.IADD R9, R15, 0x1, R8 ; /* 0x000000010f097824 */
/* 0x010fca00078e0208 */
/*04d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e8000c101904 */
/*04e0*/ LDG.E R8, [R6.64+0x30] ; /* 0x0000300406087981 */
/* 0x000ee2000c1e1900 */
/*04f0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0500*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007ffe0ff */
/*0510*/ IADD3 R11, R9, R8, RZ ; /* 0x00000008090b7210 */
/* 0x008fca0007ffe0ff */
/*0520*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0530*/ @P1 BRA 0x180 ; /* 0xfffffc4000001947 */
/* 0x000fea000383ffff */
/*0540*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0550*/ @!P1 BRA 0x750 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.MOV.U32 R10, RZ, RZ, 0x10 ; /* 0x00000010ff0a7424 */
/* 0x000fc800078e00ff */
/*0570*/ IMAD.WIDE R6, R4, R10, c[0x0][0x170] ; /* 0x00005c0004067625 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ee4000c1e1900 */
/*0590*/ IMAD.IADD R11, R11, 0x1, R8 ; /* 0x000000010b0b7824 */
/* 0x00cfca00078e0208 */
/*05a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*05b0*/ LDG.E R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000ea4000c1e1900 */
/*05c0*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x004fca00078e0208 */
/*05d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*05e0*/ LDG.E R8, [R6.64+0x20] ; /* 0x0000200406087981 */
/* 0x000ea4000c1e1900 */
/*05f0*/ IADD3 R15, R13, R8, RZ ; /* 0x000000080d0f7210 */
/* 0x004fca0007ffe0ff */
/*0600*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0610*/ LDG.E R8, [R6.64+0x30] ; /* 0x0000300406087981 */
/* 0x000ea2000c1e1900 */
/*0620*/ IADD3 R9, R4, 0x4, RZ ; /* 0x0000000404097810 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD.IADD R17, R15, 0x1, R8 ; /* 0x000000010f117824 */
/* 0x004fc800078e0208 */
/*0640*/ IMAD.WIDE R8, R9, R10, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fe200078e020a */
/*0650*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0660*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea4000c1e1900 */
/*0670*/ IMAD.IADD R19, R17, 0x1, R10 ; /* 0x0000000111137824 */
/* 0x004fca00078e020a */
/*0680*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0690*/ LDG.E R10, [R8.64+0x10] ; /* 0x00001004080a7981 */
/* 0x000e24000c1e1900 */
/*06a0*/ IMAD.IADD R13, R19, 0x1, R10 ; /* 0x00000001130d7824 */
/* 0x001fca00078e020a */
/*06b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*06c0*/ LDG.E R6, [R8.64+0x20] ; /* 0x0000200408067981 */
/* 0x000ea4000c1e1900 */
/*06d0*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x004fca0007ffe0ff */
/*06e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c101904 */
/*06f0*/ LDG.E R6, [R8.64+0x30] ; /* 0x0000300408067981 */
/* 0x000ea2000c1e1900 */
/*0700*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0710*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe40007ffe0ff */
/*0720*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0730*/ IMAD.IADD R11, R7, 0x1, R6 ; /* 0x00000001070b7824 */
/* 0x004fca00078e0206 */
/*0740*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e6000c101904 */
/*0750*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0760*/ @!P0 BRA 0x890 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD.MOV.U32 R7, RZ, RZ, 0x10 ; /* 0x00000010ff077424 */
/* 0x002fc800078e00ff */
/*0780*/ IMAD.WIDE R6, R4, R7, c[0x0][0x170] ; /* 0x00005c0004067625 */
/* 0x000fca00078e0207 */
/*0790*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ee4000c1e1900 */
/*07a0*/ IMAD.IADD R9, R8, 0x1, R11 ; /* 0x0000000108097824 */
/* 0x00cfca00078e020b */
/*07b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*07c0*/ LDG.E R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000ea4000c1e1900 */
/*07d0*/ IADD3 R13, R9, R8, RZ ; /* 0x00000008090d7210 */
/* 0x004fca0007ffe0ff */
/*07e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*07f0*/ LDG.E R8, [R6.64+0x20] ; /* 0x0000200406087981 */
/* 0x000ea2000c1e1900 */
/*0800*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*0810*/ IMAD.IADD R15, R13, 0x1, R8 ; /* 0x000000010d0f7824 */
/* 0x004fca00078e0208 */
/*0820*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e8000c101904 */
/*0830*/ LDG.E R8, [R6.64+0x30] ; /* 0x0000300406087981 */
/* 0x000ea2000c1e1900 */
/*0840*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0850*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*0860*/ IMAD.IADD R11, R15, 0x1, R8 ; /* 0x000000010f0b7824 */
/* 0x004fca00078e0208 */
/*0870*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001ea000c101904 */
/*0880*/ @P0 BRA 0x770 ; /* 0xfffffee000000947 */
/* 0x001fea000383ffff */
/*0890*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*08a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x10 ; /* 0x00000010ff077424 */
/* 0x002fc800078e00ff */
/*08c0*/ IMAD.WIDE R6, R4, R7, c[0x0][0x170] ; /* 0x00005c0004067625 */
/* 0x000fcc00078e0207 */
/*08d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*08e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*08f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0900*/ IADD3 R11, R6, R11, RZ ; /* 0x0000000b060b7210 */
/* 0x00dfca0007ffe0ff */
/*0910*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001ec000c101904 */
/*0920*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0930*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe20007ffe0ff */
/*0940*/ BRA 0x8b0 ; /* 0xffffff6000007947 */
/* 0x000fea000383ffff */
/*0950*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff067624 */
/* 0x000fe400078e00ff */
/*0960*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0970*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0980*/ LOP3.LUT R12, R6, 0x3, RZ, 0xc0, !PT ; /* 0x00000003060c7812 */
/* 0x000fc400078ec0ff */
/*0990*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ IADD3 R7, -R12, c[0x0][0x164], RZ ; /* 0x000059000c077a10 */
/* 0x000fe40007ffe1ff */
/*09b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*09c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fcc00078e0205 */
/*09d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*09f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0a00*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*0a10*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f26270 */
/*0a20*/ IMAD.IADD R11, R4, 0x1, R11 ; /* 0x00000001040b7824 */
/* 0x00dfca00078e020b */
/*0a30*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e2000c101904 */
/*0a40*/ @!P0 BRA 0x11e0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f04270 */
/*0a60*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0a70*/ MOV R8, R7 ; /* 0x0000000700087202 */
/* 0x000fe20000000f00 */
/*0a80*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0a90*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fd000078e00ff */
/*0aa0*/ @!P0 BRA 0x10a0 ; /* 0x000005f000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ ISETP.GT.AND P2, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f44270 */
/*0ac0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0ad0*/ @!P2 BRA 0xe70 ; /* 0x000003900000a947 */
/* 0x000fea0003800000 */
/*0ae0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0af0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x00dfca00078e020b */
/*0b10*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0b20*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */
/* 0x000ea4000c1e1900 */
/*0b30*/ IADD3 R13, R11, R10, RZ ; /* 0x0000000a0b0d7210 */
/* 0x004fca0007ffe0ff */
/*0b40*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0b50*/ LDG.E R10, [R4.64+0x40] ; /* 0x00004004040a7981 */
/* 0x000ea4000c1e1900 */
/*0b60*/ IMAD.IADD R15, R13, 0x1, R10 ; /* 0x000000010d0f7824 */
/* 0x004fca00078e020a */
/*0b70*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0b80*/ LDG.E R10, [R4.64+0x60] ; /* 0x00006004040a7981 */
/* 0x000ee4000c1e1900 */
/*0b90*/ IMAD.IADD R17, R15, 0x1, R10 ; /* 0x000000010f117824 */
/* 0x008fca00078e020a */
/*0ba0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0bb0*/ LDG.E R10, [R4.64+0x80] ; /* 0x00008004040a7981 */
/* 0x000e24000c1e1900 */
/*0bc0*/ IMAD.IADD R11, R17, 0x1, R10 ; /* 0x00000001110b7824 */
/* 0x001fca00078e020a */
/*0bd0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0be0*/ LDG.E R10, [R4.64+0xa0] ; /* 0x0000a004040a7981 */
/* 0x000e64000c1e1900 */
/*0bf0*/ IADD3 R13, R11, R10, RZ ; /* 0x0000000a0b0d7210 */
/* 0x002fca0007ffe0ff */
/*0c00*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0c10*/ LDG.E R10, [R4.64+0xc0] ; /* 0x0000c004040a7981 */
/* 0x000ea4000c1e1900 */
/*0c20*/ IMAD.IADD R15, R13, 0x1, R10 ; /* 0x000000010d0f7824 */
/* 0x004fca00078e020a */
/*0c30*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0c40*/ LDG.E R10, [R4.64+0xe0] ; /* 0x0000e004040a7981 */
/* 0x000ee4000c1e1900 */
/*0c50*/ IMAD.IADD R17, R15, 0x1, R10 ; /* 0x000000010f117824 */
/* 0x008fca00078e020a */
/*0c60*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0c70*/ LDG.E R10, [R4.64+0x100] ; /* 0x00010004040a7981 */
/* 0x000e24000c1e1900 */
/*0c80*/ IMAD.IADD R11, R17, 0x1, R10 ; /* 0x00000001110b7824 */
/* 0x001fca00078e020a */
/*0c90*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0ca0*/ LDG.E R10, [R4.64+0x120] ; /* 0x00012004040a7981 */
/* 0x000e64000c1e1900 */
/*0cb0*/ IADD3 R13, R11, R10, RZ ; /* 0x0000000a0b0d7210 */
/* 0x002fca0007ffe0ff */
/*0cc0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0cd0*/ LDG.E R10, [R4.64+0x140] ; /* 0x00014004040a7981 */
/* 0x000ea4000c1e1900 */
/*0ce0*/ IMAD.IADD R15, R13, 0x1, R10 ; /* 0x000000010d0f7824 */
/* 0x004fca00078e020a */
/*0cf0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0d00*/ LDG.E R10, [R4.64+0x160] ; /* 0x00016004040a7981 */
/* 0x000ee4000c1e1900 */
/*0d10*/ IMAD.IADD R17, R15, 0x1, R10 ; /* 0x000000010f117824 */
/* 0x008fca00078e020a */
/*0d20*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*0d30*/ LDG.E R10, [R4.64+0x180] ; /* 0x00018004040a7981 */
/* 0x000ee4000c1e1900 */
/*0d40*/ IMAD.IADD R19, R17, 0x1, R10 ; /* 0x0000000111137824 */
/* 0x008fca00078e020a */
/*0d50*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0007e8000c101904 */
/*0d60*/ LDG.E R10, [R4.64+0x1a0] ; /* 0x0001a004040a7981 */
/* 0x000e24000c1e1900 */
/*0d70*/ IADD3 R13, R19, R10, RZ ; /* 0x0000000a130d7210 */
/* 0x001fca0007ffe0ff */
/*0d80*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0d90*/ LDG.E R10, [R4.64+0x1c0] ; /* 0x0001c004040a7981 */
/* 0x000e62000c1e1900 */
/*0da0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0db0*/ IMAD.IADD R15, R13, 0x1, R10 ; /* 0x000000010d0f7824 */
/* 0x002fca00078e020a */
/*0dc0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0dd0*/ LDG.E R10, [R4.64+0x1e0] ; /* 0x0001e004040a7981 */
/* 0x000f22000c1e1900 */
/*0de0*/ ISETP.GT.AND P2, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f44270 */
/*0df0*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe20007ffe0ff */
/*0e00*/ IMAD.IADD R11, R15, 0x1, R10 ; /* 0x000000010f0b7824 */
/* 0x010fe200078e020a */
/*0e10*/ IADD3 R10, P3, R4, 0x200, RZ ; /* 0x00000200040a7810 */
/* 0x000fc80007f7e0ff */
/*0e20*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e2000c101904 */
/*0e30*/ IMAD.X R17, RZ, RZ, R5, P3 ; /* 0x000000ffff117224 */
/* 0x004fe200018e0605 */
/*0e40*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fc60000000f00 */
/*0e50*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0011 */
/*0e60*/ @P2 BRA 0xaf0 ; /* 0xfffffc8000002947 */
/* 0x000fea000383ffff */
/*0e70*/ ISETP.GT.AND P2, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f44270 */
/*0e80*/ @!P2 BRA 0x1080 ; /* 0x000001f00000a947 */
/* 0x000fea0003800000 */
/*0e90*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0ea0*/ IMAD.IADD R11, R11, 0x1, R10 ; /* 0x000000010b0b7824 */
/* 0x00dfca00078e020a */
/*0eb0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0ec0*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */
/* 0x000ea4000c1e1900 */
/*0ed0*/ IMAD.IADD R13, R11, 0x1, R10 ; /* 0x000000010b0d7824 */
/* 0x004fca00078e020a */
/*0ee0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0ef0*/ LDG.E R10, [R4.64+0x40] ; /* 0x00004004040a7981 */
/* 0x000ea4000c1e1900 */
/*0f00*/ IADD3 R15, R13, R10, RZ ; /* 0x0000000a0d0f7210 */
/* 0x004fca0007ffe0ff */
/*0f10*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0f20*/ LDG.E R10, [R4.64+0x60] ; /* 0x00006004040a7981 */
/* 0x000ea4000c1e1900 */
/*0f30*/ IMAD.IADD R17, R15, 0x1, R10 ; /* 0x000000010f117824 */
/* 0x004fca00078e020a */
/*0f40*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*0f50*/ LDG.E R10, [R4.64+0x80] ; /* 0x00008004040a7981 */
/* 0x000ee4000c1e1900 */
/*0f60*/ IMAD.IADD R19, R17, 0x1, R10 ; /* 0x0000000111137824 */
/* 0x008fca00078e020a */
/*0f70*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0007e8000c101904 */
/*0f80*/ LDG.E R10, [R4.64+0xa0] ; /* 0x0000a004040a7981 */
/* 0x000e24000c1e1900 */
/*0f90*/ IADD3 R13, R19, R10, RZ ; /* 0x0000000a130d7210 */
/* 0x001fca0007ffe0ff */
/*0fa0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0fb0*/ LDG.E R10, [R4.64+0xc0] ; /* 0x0000c004040a7981 */
/* 0x000e64000c1e1900 */
/*0fc0*/ IMAD.IADD R15, R13, 0x1, R10 ; /* 0x000000010d0f7824 */
/* 0x002fca00078e020a */
/*0fd0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0fe0*/ LDG.E R10, [R4.64+0xe0] ; /* 0x0000e004040a7981 */
/* 0x000f22000c1e1900 */
/*0ff0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*1000*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe40007ffe0ff */
/*1010*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*1020*/ IMAD.IADD R11, R15, 0x1, R10 ; /* 0x000000010f0b7824 */
/* 0x010fe200078e020a */
/*1030*/ IADD3 R10, P2, R4, 0x100, RZ ; /* 0x00000100040a7810 */
/* 0x000fc80007f5e0ff */
/*1040*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e2000c101904 */
/*1050*/ IADD3.X R17, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff117210 */
/* 0x004fe200017fe4ff */
/*1060*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fc800078e000a */
/*1070*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0011 */
/*1080*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*1090*/ @!P0 BRA 0x11e0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*10a0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*10b0*/ IADD3 R13, R10, R11, RZ ; /* 0x0000000b0a0d7210 */
/* 0x00cfca0007ffe0ff */
/*10c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*10d0*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */
/* 0x000ea4000c1e1900 */
/*10e0*/ IMAD.IADD R15, R13, 0x1, R10 ; /* 0x000000010d0f7824 */
/* 0x004fca00078e020a */
/*10f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*1100*/ LDG.E R10, [R4.64+0x40] ; /* 0x00004004040a7981 */
/* 0x000ee2000c1e1900 */
/*1110*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*1120*/ IMAD.IADD R17, R15, 0x1, R10 ; /* 0x000000010f117824 */
/* 0x008fca00078e020a */
/*1130*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e8000c101904 */
/*1140*/ LDG.E R10, [R4.64+0x60] ; /* 0x00006004040a7981 */
/* 0x000ee2000c1e1900 */
/*1150*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*1160*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*1170*/ IADD3 R11, R17, R10, RZ ; /* 0x0000000a110b7210 */
/* 0x009fe40007ffe0ff */
/*1180*/ IADD3 R10, P2, R4, 0x80, RZ ; /* 0x00000080040a7810 */
/* 0x000fc60007f5e0ff */
/*1190*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e4000c101904 */
/*11a0*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x002fe400010e0605 */
/*11b0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fc600078e000a */
/*11c0*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fe20000000f00 */
/*11d0*/ @P0 BRA 0x10a0 ; /* 0xfffffec000000947 */
/* 0x004fea000383ffff */
/*11e0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05270 */
/*11f0*/ @!P0 BRA 0x12f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*1200*/ IMAD.MOV.U32 R4, RZ, RZ, 0x20 ; /* 0x00000020ff047424 */
/* 0x000fc800078e00ff */
/*1210*/ IMAD.WIDE R4, R9, R4, c[0x0][0x178] ; /* 0x00005e0009047625 */
/* 0x000fca00078e0204 */
/*1220*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*1230*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe20003f05270 */
/*1240*/ IMAD.IADD R11, R11, 0x1, R8 ; /* 0x000000010b0b7824 */
/* 0x00dfca00078e0208 */
/*1250*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001ee000c101904 */
/*1260*/ @!P0 BRA 0x12f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*1270*/ LDG.E R8, [R4.64+0x20] ; /* 0x0000200404087981 */
/* 0x000ea2000c1e1900 */
/*1280*/ ISETP.NE.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f05270 */
/*1290*/ IADD3 R11, R11, R8, RZ ; /* 0x000000080b0b7210 */
/* 0x005fca0007ffe0ff */
/*12a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001ec000c101904 */
/*12b0*/ @!P0 BRA 0x12f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*12c0*/ LDG.E R4, [R4.64+0x40] ; /* 0x0000400404047981 */
/* 0x000ea4000c1e1900 */
/*12d0*/ IMAD.IADD R11, R11, 0x1, R4 ; /* 0x000000010b0b7824 */
/* 0x005fca00078e0204 */
/*12e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101904 */
/*12f0*/ @!P1 BRA 0x9b0 ; /* 0xfffff6b000009947 */
/* 0x000fea000383ffff */
/*1300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1310*/ BRA 0x1310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
* PROGRAM: copyStruture
* PURPOSE: This program is a test which test the ability to transfer multilevel
* C++ structured data from host to device, modify them and transfer back.
*
*
* NAME: Vuong Pham-Duy.
* College student.
* Faculty of Computer Science and Technology.
* Ho Chi Minh University of Technology, Viet Nam.
* vuongpd95@gmail.com
*
* DATE: 5/10/2017
*
******************************************************************************/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", \
cudaGetErrorString(code), file, line);
if (abort)
exit(code);
}
}
/* Structure *****************************************************************/
typedef struct {
int64_t rbeg;
int32_t qbeg, len;
int score;
} mem_seed_t; // unaligned memory
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
mem_seed_t *seeds;
} mem_chain_t;
typedef struct {
size_t n, m;
mem_chain_t *a;
} mem_chain_v;
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
} flat_mem_chain_t;
typedef struct {
size_t n, m;
} flat_mem_chain_v;
__global__ void func(int n, int n_a, int n_seeds, flat_mem_chain_v *chns, \
flat_mem_chain_t *a, mem_seed_t *seeds, int *d_b) {
int i, j;
*d_b = 0;
for(i = 0; i < n; i++) {
*d_b += chns[i].n;
for(j = 0; j < n_a; j++) {
*d_b += a[j].n;
}
}
}
/* Structure *****************************************************************/
int main(int argc, char *argv[])
{
// Assumptions
int b;
int *d_b;
gpuErrchk(cudaMalloc(&d_b, sizeof(int)));
// Begin Assumptions
int n, i, j, k;
n = 10;
mem_chain_v *chns;
chns = (mem_chain_v*)malloc(sizeof(mem_chain_v) * n);
for(i = 0; i < n; i++) {
chns[i].n = 10;
chns[i].a = (mem_chain_t*)malloc(\
chns[i].n * sizeof(mem_chain_t));
for(j = 0; j < chns[i].n; j++) {
chns[i].a[j].n = 10;
chns[i].a[j].seeds = (mem_seed_t*)malloc(\
chns[i].a[j].n * sizeof(mem_seed_t));
for(k = 0; k < chns[i].a[j].n; k++) {
chns[i].a[j].seeds[k].score = i + j + k;
}
}
}
// End Assumptions
int n_a, n_seeds;
n_a = 0; n_seeds = 0;
for(i = 0; i < n; i++) {
n_a += chns[i].n;
for(j = 0; j < chns[i].n; j++) {
n_seeds += chns[i].a[j].n;
}
}
flat_mem_chain_v *f_chns, *df_chns;
flat_mem_chain_t *f_a, *df_a;
mem_seed_t *seeds, *d_seeds;
// Flattened the nested structure
f_chns = (flat_mem_chain_v*)malloc(n * sizeof(flat_mem_chain_v));
f_a = (flat_mem_chain_t*)malloc(n_a * sizeof(flat_mem_chain_t));
seeds = (mem_seed_t*)malloc(n_seeds * sizeof(mem_seed_t));
int acc_a, acc_seeds;
acc_a = 0; acc_seeds = 0;
for(i = 0; i < n; i++) {
f_chns[i].n = chns[i].n;
f_chns[i].m = chns[i].m;
for(j = 0; j < chns[i].n; j++) {
// int n, m, first, rid;
// uint32_t w:29, kept:2, is_alt:1;
// float frac_rep;
// int64_t pos;
mem_chain_t *tmp;
tmp = &chns[i].a[j];
f_a[acc_a].n = tmp->n;
f_a[acc_a].m = tmp->m;
f_a[acc_a].first = tmp->first;
f_a[acc_a].rid = tmp->rid;
f_a[acc_a].w = tmp->w;
f_a[acc_a].kept = tmp->kept;
f_a[acc_a].is_alt = tmp->is_alt;
f_a[acc_a].frac_rep = tmp->frac_rep;
f_a[acc_a].pos = tmp->pos;
for(k = 0; k < chns[i].a[j].n; k++) {
// int64_t rbeg;
// int32_t qbeg, len;
// int score;
mem_seed_t *tmp0;
tmp0 = &chns[i].a[j].seeds[k];
seeds[acc_seeds].rbeg = tmp0->rbeg;
seeds[acc_seeds].qbeg = tmp0->qbeg;
seeds[acc_seeds].len = tmp0->len;
seeds[acc_seeds].score = tmp0->score;
}
acc_seeds += chns[i].a[j].n;
}
acc_a += chns[i].n;
}
// Copy the flattened structure to kernel
gpuErrchk(cudaMalloc(&df_chns, n * sizeof(flat_mem_chain_v)));
gpuErrchk(cudaMalloc(&df_a, n_a * sizeof(flat_mem_chain_t)));
gpuErrchk(cudaMalloc(&d_seeds, n_seeds * sizeof(mem_seed_t)));
gpuErrchk(cudaMemcpy(df_chns, f_chns, n * sizeof(flat_mem_chain_v), \
cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(df_a, f_a, n_a * sizeof(flat_mem_chain_t), \
cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_seeds, seeds, n_seeds * sizeof(mem_seed_t), \
cudaMemcpyHostToDevice));
printf("n = %d, n_a = %d\n", n, n_a);
func<<<1, 1>>>(n, n_a, n_seeds, df_chns, df_a, d_seeds, d_b);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(&b, d_b, sizeof(int), cudaMemcpyDeviceToHost));
printf("d_b = %d\n", b);
cudaFree(df_chns);
cudaFree(df_a);
cudaFree(d_seeds);
cudaFree(d_b);
return 0;
} | .file "tmpxft_000710e4_00000000-6_deepCopy_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.text
.globl _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.globl _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.type _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, @function
_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .-_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.globl _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.type _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, @function
_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .-_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/vuongpd95/cuda-test/master/deepCopy_2/deepCopy_2.cu"
.section .rodata.str1.1
.LC2:
.string "n = %d, n_a = %d\n"
.LC3:
.string "d_b = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $240, %edi
call malloc@PLT
movq %rax, %r15
movl $0, %r14d
movq %rax, (%rsp)
movq %rax, 8(%rsp)
jmp .L22
.L43:
addl $1, %ebp
addq $40, %r12
cmpl %r13d, %ebp
je .L42
.L21:
movq %r12, %rbx
movl $10, -32(%r12)
movl $240, %edi
call malloc@PLT
movq %rax, (%r12)
movl $0, %edx
movl $0, %eax
.L20:
movq (%rbx), %rcx
leal (%rax,%rbp), %esi
movl %esi, 16(%rcx,%rdx)
addl $1, %eax
addq $24, %rdx
cmpl %eax, -32(%rbx)
jg .L20
jmp .L43
.L42:
addl $1, %r14d
addq $24, %r15
cmpl $10, %r14d
je .L44
.L22:
movq $10, (%r15)
movl $400, %edi
call malloc@PLT
movq %rax, 16(%r15)
leaq 32(%rax), %r12
movl %r14d, %ebp
leal 10(%r14), %r13d
jmp .L21
.L44:
movq (%rsp), %rbx
movq 8(%rsp), %rbp
leaq 240(%rbp), %r13
movq %rbp, %rcx
movl $0, %ebp
movl $0, %esi
jmp .L25
.L24:
addl (%rax), %ebp
addq $40, %rax
cmpq %rdx, %rax
jne .L24
.L23:
addq $24, %rcx
cmpq %r13, %rcx
je .L45
.L25:
movq (%rcx), %rdx
leal (%rsi,%rdx), %r14d
movl %r14d, %esi
testq %rdx, %rdx
je .L23
movq 16(%rcx), %rax
leaq (%rdx,%rdx,4), %rdx
leaq (%rax,%rdx,8), %rdx
jmp .L24
.L45:
movl $160, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movslq %r14d, %rax
salq $5, %rax
movq %rax, %rdi
movq %rax, 16(%rsp)
call malloc@PLT
movq %rax, %r15
movslq %ebp, %rax
leaq (%rax,%rax,2), %rax
leaq 0(,%rax,8), %rdi
movq %rdi, 32(%rsp)
call malloc@PLT
movq %rax, %r12
movq 24(%rsp), %rdx
movl $0, %r9d
movl $0, %edi
movl %r14d, 44(%rsp)
movl %ebp, %ecx
jmp .L30
.L29:
movl (%rsi), %r14d
movl %r14d, (%r8)
movl 4(%rsi), %eax
movl %eax, 4(%r8)
movl 8(%rsi), %eax
movl %eax, 8(%r8)
movl 12(%rsi), %eax
movl %eax, 12(%r8)
movl 16(%rsi), %eax
andl $536870911, %eax
movl 16(%r8), %r10d
andl $-536870912, %r10d
orl %eax, %r10d
movl %r10d, %eax
shrl $24, %eax
movl %r10d, 16(%r8)
movzbl 19(%rsi), %r10d
andl $96, %r10d
andl $-97, %eax
orl %r10d, %eax
movb %al, 19(%r8)
movzbl 19(%rsi), %r10d
andl $-128, %r10d
andl $127, %eax
orl %r10d, %eax
movb %al, 19(%r8)
movss 20(%rsi), %xmm0
movss %xmm0, 20(%r8)
movq 24(%rsi), %rax
movq %rax, 24(%r8)
testl %r14d, %r14d
jle .L27
movslq %r9d, %rax
leaq (%rax,%rax,2), %rax
leaq (%r12,%rax,8), %r10
movq 32(%rsi), %rax
movslq %r14d, %r11
leaq (%r11,%r11,2), %r11
leaq (%rax,%r11,8), %r11
movq %rdx, (%rsp)
.L28:
movq (%rax), %rdx
movq %rdx, (%r10)
movl 8(%rax), %edx
movl %edx, 8(%r10)
movl 12(%rax), %edx
movl %edx, 12(%r10)
movl 16(%rax), %edx
movl %edx, 16(%r10)
addq $24, %rax
cmpq %rax, %r11
jne .L28
movq (%rsp), %rdx
.L27:
addl %r14d, %r9d
addq $40, %rsi
cmpq %rbp, %rsi
jne .L29
movq 8(%rsp), %rax
.L26:
addl %eax, %edi
addq $24, %rbx
addq $16, %rdx
cmpq %r13, %rbx
je .L46
.L30:
movq (%rbx), %rax
movq %rax, (%rdx)
movq 8(%rbx), %rsi
movq %rsi, 8(%rdx)
testq %rax, %rax
je .L26
movslq %edi, %r8
salq $5, %r8
addq %r15, %r8
movq 16(%rbx), %rsi
leaq (%rax,%rax,4), %r10
leaq (%rsi,%r10,8), %rbp
movq %rax, 8(%rsp)
jmp .L29
.L46:
movl 44(%rsp), %r14d
movl %ecx, %ebp
leaq 56(%rsp), %rdi
movl $160, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $163, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 64(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $164, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 72(%rsp), %rdi
movq 32(%rsp), %r13
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $165, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $160, %edx
movq 24(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $167, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq 16(%rsp), %rdx
movq %r15, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $169, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $171, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl %r14d, %ecx
movl $10, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L31:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $177, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $178, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 92(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $179, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl 92(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
movq 88(%rsp), %r9
movq 80(%rsp), %r8
movq 72(%rsp), %rcx
movl %ebp, %edx
movl %r14d, %esi
movl $10, %edi
call _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L31
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
* PROGRAM: copyStruture
* PURPOSE: This program is a test which test the ability to transfer multilevel
* C++ structured data from host to device, modify them and transfer back.
*
*
* NAME: Vuong Pham-Duy.
* College student.
* Faculty of Computer Science and Technology.
* Ho Chi Minh University of Technology, Viet Nam.
* vuongpd95@gmail.com
*
* DATE: 5/10/2017
*
******************************************************************************/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", \
cudaGetErrorString(code), file, line);
if (abort)
exit(code);
}
}
/* Structure *****************************************************************/
typedef struct {
int64_t rbeg;
int32_t qbeg, len;
int score;
} mem_seed_t; // unaligned memory
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
mem_seed_t *seeds;
} mem_chain_t;
typedef struct {
size_t n, m;
mem_chain_t *a;
} mem_chain_v;
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
} flat_mem_chain_t;
typedef struct {
size_t n, m;
} flat_mem_chain_v;
__global__ void func(int n, int n_a, int n_seeds, flat_mem_chain_v *chns, \
flat_mem_chain_t *a, mem_seed_t *seeds, int *d_b) {
int i, j;
*d_b = 0;
for(i = 0; i < n; i++) {
*d_b += chns[i].n;
for(j = 0; j < n_a; j++) {
*d_b += a[j].n;
}
}
}
/* Structure *****************************************************************/
int main(int argc, char *argv[])
{
// Assumptions
int b;
int *d_b;
gpuErrchk(cudaMalloc(&d_b, sizeof(int)));
// Begin Assumptions
int n, i, j, k;
n = 10;
mem_chain_v *chns;
chns = (mem_chain_v*)malloc(sizeof(mem_chain_v) * n);
for(i = 0; i < n; i++) {
chns[i].n = 10;
chns[i].a = (mem_chain_t*)malloc(\
chns[i].n * sizeof(mem_chain_t));
for(j = 0; j < chns[i].n; j++) {
chns[i].a[j].n = 10;
chns[i].a[j].seeds = (mem_seed_t*)malloc(\
chns[i].a[j].n * sizeof(mem_seed_t));
for(k = 0; k < chns[i].a[j].n; k++) {
chns[i].a[j].seeds[k].score = i + j + k;
}
}
}
// End Assumptions
int n_a, n_seeds;
n_a = 0; n_seeds = 0;
for(i = 0; i < n; i++) {
n_a += chns[i].n;
for(j = 0; j < chns[i].n; j++) {
n_seeds += chns[i].a[j].n;
}
}
flat_mem_chain_v *f_chns, *df_chns;
flat_mem_chain_t *f_a, *df_a;
mem_seed_t *seeds, *d_seeds;
// Flattened the nested structure
f_chns = (flat_mem_chain_v*)malloc(n * sizeof(flat_mem_chain_v));
f_a = (flat_mem_chain_t*)malloc(n_a * sizeof(flat_mem_chain_t));
seeds = (mem_seed_t*)malloc(n_seeds * sizeof(mem_seed_t));
int acc_a, acc_seeds;
acc_a = 0; acc_seeds = 0;
for(i = 0; i < n; i++) {
f_chns[i].n = chns[i].n;
f_chns[i].m = chns[i].m;
for(j = 0; j < chns[i].n; j++) {
// int n, m, first, rid;
// uint32_t w:29, kept:2, is_alt:1;
// float frac_rep;
// int64_t pos;
mem_chain_t *tmp;
tmp = &chns[i].a[j];
f_a[acc_a].n = tmp->n;
f_a[acc_a].m = tmp->m;
f_a[acc_a].first = tmp->first;
f_a[acc_a].rid = tmp->rid;
f_a[acc_a].w = tmp->w;
f_a[acc_a].kept = tmp->kept;
f_a[acc_a].is_alt = tmp->is_alt;
f_a[acc_a].frac_rep = tmp->frac_rep;
f_a[acc_a].pos = tmp->pos;
for(k = 0; k < chns[i].a[j].n; k++) {
// int64_t rbeg;
// int32_t qbeg, len;
// int score;
mem_seed_t *tmp0;
tmp0 = &chns[i].a[j].seeds[k];
seeds[acc_seeds].rbeg = tmp0->rbeg;
seeds[acc_seeds].qbeg = tmp0->qbeg;
seeds[acc_seeds].len = tmp0->len;
seeds[acc_seeds].score = tmp0->score;
}
acc_seeds += chns[i].a[j].n;
}
acc_a += chns[i].n;
}
// Copy the flattened structure to kernel
gpuErrchk(cudaMalloc(&df_chns, n * sizeof(flat_mem_chain_v)));
gpuErrchk(cudaMalloc(&df_a, n_a * sizeof(flat_mem_chain_t)));
gpuErrchk(cudaMalloc(&d_seeds, n_seeds * sizeof(mem_seed_t)));
gpuErrchk(cudaMemcpy(df_chns, f_chns, n * sizeof(flat_mem_chain_v), \
cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(df_a, f_a, n_a * sizeof(flat_mem_chain_t), \
cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_seeds, seeds, n_seeds * sizeof(mem_seed_t), \
cudaMemcpyHostToDevice));
printf("n = %d, n_a = %d\n", n, n_a);
func<<<1, 1>>>(n, n_a, n_seeds, df_chns, df_a, d_seeds, d_b);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(&b, d_b, sizeof(int), cudaMemcpyDeviceToHost));
printf("d_b = %d\n", b);
cudaFree(df_chns);
cudaFree(df_a);
cudaFree(d_seeds);
cudaFree(d_b);
return 0;
} | /******************************************************************************
* PROGRAM: copyStruture
* PURPOSE: This program is a test which test the ability to transfer multilevel
* C++ structured data from host to device, modify them and transfer back.
*
*
* NAME: Vuong Pham-Duy.
* College student.
* Faculty of Computer Science and Technology.
* Ho Chi Minh University of Technology, Viet Nam.
* vuongpd95@gmail.com
*
* DATE: 5/10/2017
*
******************************************************************************/
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if (code != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", \
hipGetErrorString(code), file, line);
if (abort)
exit(code);
}
}
/* Structure *****************************************************************/
typedef struct {
int64_t rbeg;
int32_t qbeg, len;
int score;
} mem_seed_t; // unaligned memory
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
mem_seed_t *seeds;
} mem_chain_t;
typedef struct {
size_t n, m;
mem_chain_t *a;
} mem_chain_v;
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
} flat_mem_chain_t;
typedef struct {
size_t n, m;
} flat_mem_chain_v;
__global__ void func(int n, int n_a, int n_seeds, flat_mem_chain_v *chns, \
flat_mem_chain_t *a, mem_seed_t *seeds, int *d_b) {
int i, j;
*d_b = 0;
for(i = 0; i < n; i++) {
*d_b += chns[i].n;
for(j = 0; j < n_a; j++) {
*d_b += a[j].n;
}
}
}
/* Structure *****************************************************************/
int main(int argc, char *argv[])
{
// Assumptions
int b;
int *d_b;
gpuErrchk(hipMalloc(&d_b, sizeof(int)));
// Begin Assumptions
int n, i, j, k;
n = 10;
mem_chain_v *chns;
chns = (mem_chain_v*)malloc(sizeof(mem_chain_v) * n);
for(i = 0; i < n; i++) {
chns[i].n = 10;
chns[i].a = (mem_chain_t*)malloc(\
chns[i].n * sizeof(mem_chain_t));
for(j = 0; j < chns[i].n; j++) {
chns[i].a[j].n = 10;
chns[i].a[j].seeds = (mem_seed_t*)malloc(\
chns[i].a[j].n * sizeof(mem_seed_t));
for(k = 0; k < chns[i].a[j].n; k++) {
chns[i].a[j].seeds[k].score = i + j + k;
}
}
}
// End Assumptions
int n_a, n_seeds;
n_a = 0; n_seeds = 0;
for(i = 0; i < n; i++) {
n_a += chns[i].n;
for(j = 0; j < chns[i].n; j++) {
n_seeds += chns[i].a[j].n;
}
}
flat_mem_chain_v *f_chns, *df_chns;
flat_mem_chain_t *f_a, *df_a;
mem_seed_t *seeds, *d_seeds;
// Flattened the nested structure
f_chns = (flat_mem_chain_v*)malloc(n * sizeof(flat_mem_chain_v));
f_a = (flat_mem_chain_t*)malloc(n_a * sizeof(flat_mem_chain_t));
seeds = (mem_seed_t*)malloc(n_seeds * sizeof(mem_seed_t));
int acc_a, acc_seeds;
acc_a = 0; acc_seeds = 0;
for(i = 0; i < n; i++) {
f_chns[i].n = chns[i].n;
f_chns[i].m = chns[i].m;
for(j = 0; j < chns[i].n; j++) {
// int n, m, first, rid;
// uint32_t w:29, kept:2, is_alt:1;
// float frac_rep;
// int64_t pos;
mem_chain_t *tmp;
tmp = &chns[i].a[j];
f_a[acc_a].n = tmp->n;
f_a[acc_a].m = tmp->m;
f_a[acc_a].first = tmp->first;
f_a[acc_a].rid = tmp->rid;
f_a[acc_a].w = tmp->w;
f_a[acc_a].kept = tmp->kept;
f_a[acc_a].is_alt = tmp->is_alt;
f_a[acc_a].frac_rep = tmp->frac_rep;
f_a[acc_a].pos = tmp->pos;
for(k = 0; k < chns[i].a[j].n; k++) {
// int64_t rbeg;
// int32_t qbeg, len;
// int score;
mem_seed_t *tmp0;
tmp0 = &chns[i].a[j].seeds[k];
seeds[acc_seeds].rbeg = tmp0->rbeg;
seeds[acc_seeds].qbeg = tmp0->qbeg;
seeds[acc_seeds].len = tmp0->len;
seeds[acc_seeds].score = tmp0->score;
}
acc_seeds += chns[i].a[j].n;
}
acc_a += chns[i].n;
}
// Copy the flattened structure to kernel
gpuErrchk(hipMalloc(&df_chns, n * sizeof(flat_mem_chain_v)));
gpuErrchk(hipMalloc(&df_a, n_a * sizeof(flat_mem_chain_t)));
gpuErrchk(hipMalloc(&d_seeds, n_seeds * sizeof(mem_seed_t)));
gpuErrchk(hipMemcpy(df_chns, f_chns, n * sizeof(flat_mem_chain_v), \
hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(df_a, f_a, n_a * sizeof(flat_mem_chain_t), \
hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_seeds, seeds, n_seeds * sizeof(mem_seed_t), \
hipMemcpyHostToDevice));
printf("n = %d, n_a = %d\n", n, n_a);
func<<<1, 1>>>(n, n_a, n_seeds, df_chns, df_a, d_seeds, d_b);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(&b, d_b, sizeof(int), hipMemcpyDeviceToHost));
printf("d_b = %d\n", b);
hipFree(df_chns);
hipFree(df_a);
hipFree(d_seeds);
hipFree(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /******************************************************************************
* PROGRAM: copyStruture
* PURPOSE: This program is a test which test the ability to transfer multilevel
* C++ structured data from host to device, modify them and transfer back.
*
*
* NAME: Vuong Pham-Duy.
* College student.
* Faculty of Computer Science and Technology.
* Ho Chi Minh University of Technology, Viet Nam.
* vuongpd95@gmail.com
*
* DATE: 5/10/2017
*
******************************************************************************/
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if (code != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", \
hipGetErrorString(code), file, line);
if (abort)
exit(code);
}
}
/* Structure *****************************************************************/
typedef struct {
int64_t rbeg;
int32_t qbeg, len;
int score;
} mem_seed_t; // unaligned memory
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
mem_seed_t *seeds;
} mem_chain_t;
typedef struct {
size_t n, m;
mem_chain_t *a;
} mem_chain_v;
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
} flat_mem_chain_t;
typedef struct {
size_t n, m;
} flat_mem_chain_v;
__global__ void func(int n, int n_a, int n_seeds, flat_mem_chain_v *chns, \
flat_mem_chain_t *a, mem_seed_t *seeds, int *d_b) {
int i, j;
*d_b = 0;
for(i = 0; i < n; i++) {
*d_b += chns[i].n;
for(j = 0; j < n_a; j++) {
*d_b += a[j].n;
}
}
}
/* Structure *****************************************************************/
int main(int argc, char *argv[])
{
// Assumptions
int b;
int *d_b;
gpuErrchk(hipMalloc(&d_b, sizeof(int)));
// Begin Assumptions
int n, i, j, k;
n = 10;
mem_chain_v *chns;
chns = (mem_chain_v*)malloc(sizeof(mem_chain_v) * n);
for(i = 0; i < n; i++) {
chns[i].n = 10;
chns[i].a = (mem_chain_t*)malloc(\
chns[i].n * sizeof(mem_chain_t));
for(j = 0; j < chns[i].n; j++) {
chns[i].a[j].n = 10;
chns[i].a[j].seeds = (mem_seed_t*)malloc(\
chns[i].a[j].n * sizeof(mem_seed_t));
for(k = 0; k < chns[i].a[j].n; k++) {
chns[i].a[j].seeds[k].score = i + j + k;
}
}
}
// End Assumptions
int n_a, n_seeds;
n_a = 0; n_seeds = 0;
for(i = 0; i < n; i++) {
n_a += chns[i].n;
for(j = 0; j < chns[i].n; j++) {
n_seeds += chns[i].a[j].n;
}
}
flat_mem_chain_v *f_chns, *df_chns;
flat_mem_chain_t *f_a, *df_a;
mem_seed_t *seeds, *d_seeds;
// Flattened the nested structure
f_chns = (flat_mem_chain_v*)malloc(n * sizeof(flat_mem_chain_v));
f_a = (flat_mem_chain_t*)malloc(n_a * sizeof(flat_mem_chain_t));
seeds = (mem_seed_t*)malloc(n_seeds * sizeof(mem_seed_t));
int acc_a, acc_seeds;
acc_a = 0; acc_seeds = 0;
for(i = 0; i < n; i++) {
f_chns[i].n = chns[i].n;
f_chns[i].m = chns[i].m;
for(j = 0; j < chns[i].n; j++) {
// int n, m, first, rid;
// uint32_t w:29, kept:2, is_alt:1;
// float frac_rep;
// int64_t pos;
mem_chain_t *tmp;
tmp = &chns[i].a[j];
f_a[acc_a].n = tmp->n;
f_a[acc_a].m = tmp->m;
f_a[acc_a].first = tmp->first;
f_a[acc_a].rid = tmp->rid;
f_a[acc_a].w = tmp->w;
f_a[acc_a].kept = tmp->kept;
f_a[acc_a].is_alt = tmp->is_alt;
f_a[acc_a].frac_rep = tmp->frac_rep;
f_a[acc_a].pos = tmp->pos;
for(k = 0; k < chns[i].a[j].n; k++) {
// int64_t rbeg;
// int32_t qbeg, len;
// int score;
mem_seed_t *tmp0;
tmp0 = &chns[i].a[j].seeds[k];
seeds[acc_seeds].rbeg = tmp0->rbeg;
seeds[acc_seeds].qbeg = tmp0->qbeg;
seeds[acc_seeds].len = tmp0->len;
seeds[acc_seeds].score = tmp0->score;
}
acc_seeds += chns[i].a[j].n;
}
acc_a += chns[i].n;
}
// Copy the flattened structure to kernel
gpuErrchk(hipMalloc(&df_chns, n * sizeof(flat_mem_chain_v)));
gpuErrchk(hipMalloc(&df_a, n_a * sizeof(flat_mem_chain_t)));
gpuErrchk(hipMalloc(&d_seeds, n_seeds * sizeof(mem_seed_t)));
gpuErrchk(hipMemcpy(df_chns, f_chns, n * sizeof(flat_mem_chain_v), \
hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(df_a, f_a, n_a * sizeof(flat_mem_chain_t), \
hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_seeds, seeds, n_seeds * sizeof(mem_seed_t), \
hipMemcpyHostToDevice));
printf("n = %d, n_a = %d\n", n, n_a);
func<<<1, 1>>>(n, n_a, n_seeds, df_chns, df_a, d_seeds, d_b);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(&b, d_b, sizeof(int), hipMemcpyDeviceToHost));
printf("d_b = %d\n", b);
hipFree(df_chns);
hipFree(df_a);
hipFree(d_seeds);
hipFree(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.globl _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.p2align 8
.type _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi,@function
_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
s_clause 0x1
s_load_b32 s12, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
global_store_b32 v0, v0, s[2:3]
s_cbranch_scc1 .LBB0_6
global_load_b32 v1, v0, s[2:3]
s_clause 0x1
s_load_b32 s13, s[0:1], 0x4
s_load_b128 s[4:7], s[0:1], 0x10
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_mov_b32 s8, s9
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s13, 0
s_cselect_b32 s0, -1, 0
v_cndmask_b32_e64 v2, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, s12
s_cbranch_scc0 .LBB0_6
.LBB0_3:
s_lshl_b64 s[10:11], s[8:9], 4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_and_b32 vcc_lo, exec_lo, s0
s_load_b32 s1, s[10:11], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, s1, v1
global_store_b32 v0, v1, s[2:3]
s_cbranch_vccnz .LBB0_2
s_mov_b64 s[10:11], s[6:7]
s_mov_b32 s1, s13
.LBB0_5:
global_load_b32 v2, v0, s[10:11]
s_add_i32 s1, s1, -1
s_add_u32 s10, s10, 32
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s1, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v1, v2
global_store_b32 v0, v1, s[2:3]
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 14
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .Lfunc_end0-_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /******************************************************************************
* PROGRAM: copyStruture
* PURPOSE: This program is a test which test the ability to transfer multilevel
* C++ structured data from host to device, modify them and transfer back.
*
*
* NAME: Vuong Pham-Duy.
* College student.
* Faculty of Computer Science and Technology.
* Ho Chi Minh University of Technology, Viet Nam.
* vuongpd95@gmail.com
*
* DATE: 5/10/2017
*
******************************************************************************/
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if (code != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", \
hipGetErrorString(code), file, line);
if (abort)
exit(code);
}
}
/* Structure *****************************************************************/
typedef struct {
int64_t rbeg;
int32_t qbeg, len;
int score;
} mem_seed_t; // unaligned memory
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
mem_seed_t *seeds;
} mem_chain_t;
typedef struct {
size_t n, m;
mem_chain_t *a;
} mem_chain_v;
typedef struct {
int n, m, first, rid;
uint32_t w:29, kept:2, is_alt:1;
float frac_rep;
int64_t pos;
} flat_mem_chain_t;
typedef struct {
size_t n, m;
} flat_mem_chain_v;
__global__ void func(int n, int n_a, int n_seeds, flat_mem_chain_v *chns, \
flat_mem_chain_t *a, mem_seed_t *seeds, int *d_b) {
int i, j;
*d_b = 0;
for(i = 0; i < n; i++) {
*d_b += chns[i].n;
for(j = 0; j < n_a; j++) {
*d_b += a[j].n;
}
}
}
/* Structure *****************************************************************/
int main(int argc, char *argv[])
{
// Assumptions
int b;
int *d_b;
gpuErrchk(hipMalloc(&d_b, sizeof(int)));
// Begin Assumptions
int n, i, j, k;
n = 10;
mem_chain_v *chns;
chns = (mem_chain_v*)malloc(sizeof(mem_chain_v) * n);
for(i = 0; i < n; i++) {
chns[i].n = 10;
chns[i].a = (mem_chain_t*)malloc(\
chns[i].n * sizeof(mem_chain_t));
for(j = 0; j < chns[i].n; j++) {
chns[i].a[j].n = 10;
chns[i].a[j].seeds = (mem_seed_t*)malloc(\
chns[i].a[j].n * sizeof(mem_seed_t));
for(k = 0; k < chns[i].a[j].n; k++) {
chns[i].a[j].seeds[k].score = i + j + k;
}
}
}
// End Assumptions
int n_a, n_seeds;
n_a = 0; n_seeds = 0;
for(i = 0; i < n; i++) {
n_a += chns[i].n;
for(j = 0; j < chns[i].n; j++) {
n_seeds += chns[i].a[j].n;
}
}
flat_mem_chain_v *f_chns, *df_chns;
flat_mem_chain_t *f_a, *df_a;
mem_seed_t *seeds, *d_seeds;
// Flattened the nested structure
f_chns = (flat_mem_chain_v*)malloc(n * sizeof(flat_mem_chain_v));
f_a = (flat_mem_chain_t*)malloc(n_a * sizeof(flat_mem_chain_t));
seeds = (mem_seed_t*)malloc(n_seeds * sizeof(mem_seed_t));
int acc_a, acc_seeds;
acc_a = 0; acc_seeds = 0;
for(i = 0; i < n; i++) {
f_chns[i].n = chns[i].n;
f_chns[i].m = chns[i].m;
for(j = 0; j < chns[i].n; j++) {
// int n, m, first, rid;
// uint32_t w:29, kept:2, is_alt:1;
// float frac_rep;
// int64_t pos;
mem_chain_t *tmp;
tmp = &chns[i].a[j];
f_a[acc_a].n = tmp->n;
f_a[acc_a].m = tmp->m;
f_a[acc_a].first = tmp->first;
f_a[acc_a].rid = tmp->rid;
f_a[acc_a].w = tmp->w;
f_a[acc_a].kept = tmp->kept;
f_a[acc_a].is_alt = tmp->is_alt;
f_a[acc_a].frac_rep = tmp->frac_rep;
f_a[acc_a].pos = tmp->pos;
for(k = 0; k < chns[i].a[j].n; k++) {
// int64_t rbeg;
// int32_t qbeg, len;
// int score;
mem_seed_t *tmp0;
tmp0 = &chns[i].a[j].seeds[k];
seeds[acc_seeds].rbeg = tmp0->rbeg;
seeds[acc_seeds].qbeg = tmp0->qbeg;
seeds[acc_seeds].len = tmp0->len;
seeds[acc_seeds].score = tmp0->score;
}
acc_seeds += chns[i].a[j].n;
}
acc_a += chns[i].n;
}
// Copy the flattened structure to kernel
gpuErrchk(hipMalloc(&df_chns, n * sizeof(flat_mem_chain_v)));
gpuErrchk(hipMalloc(&df_a, n_a * sizeof(flat_mem_chain_t)));
gpuErrchk(hipMalloc(&d_seeds, n_seeds * sizeof(mem_seed_t)));
gpuErrchk(hipMemcpy(df_chns, f_chns, n * sizeof(flat_mem_chain_v), \
hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(df_a, f_a, n_a * sizeof(flat_mem_chain_t), \
hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_seeds, seeds, n_seeds * sizeof(mem_seed_t), \
hipMemcpyHostToDevice));
printf("n = %d, n_a = %d\n", n, n_a);
func<<<1, 1>>>(n, n_a, n_seeds, df_chns, df_a, d_seeds, d_b);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(&b, d_b, sizeof(int), hipMemcpyDeviceToHost));
printf("d_b = %d\n", b);
hipFree(df_chns);
hipFree(df_a);
hipFree(d_seeds);
hipFree(d_b);
return 0;
} | .text
.file "deepCopy_2.hip"
.globl _Z9gpuAssert10hipError_tPKcib # -- Begin function _Z9gpuAssert10hipError_tPKcib
.p2align 4, 0x90
.type _Z9gpuAssert10hipError_tPKcib,@function
_Z9gpuAssert10hipError_tPKcib: # @_Z9gpuAssert10hipError_tPKcib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edi, %edi
jne .LBB0_1
.LBB0_2:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %r14
movl %edi, %ebx
movl %ecx, %r12d
movl %edx, %ebp
movq %rsi, %r15
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rax, %rdx
movq %r15, %rcx
movl %ebp, %r8d
xorl %eax, %eax
callq fprintf
testb %r12b, %r12b
je .LBB0_2
# %bb.3:
movl %ebx, %edi
callq exit
.Lfunc_end0:
.size _Z9gpuAssert10hipError_tPKcib, .Lfunc_end0-_Z9gpuAssert10hipError_tPKcib
.cfi_endproc
# -- End function
.globl _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi # -- Begin function _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.p2align 4, 0x90
.type _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi,@function
_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi: # @_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .Lfunc_end1-_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movl $240, %edi
callq malloc
movq %rax, %r13
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
# Child Loop BB2_6 Depth 3
leaq (%r15,%r15,2), %r14
movq $10, (%r13,%r14,8)
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movq %rax, 16(%r13,%r14,8)
movl %r15d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_4 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
leaq (%r14,%r14,4), %r12
movl $10, (%rbx,%r12,8)
movl $240, %edi
callq malloc
movq %rax, 32(%rbx,%r12,8)
movl $16, %ecx
movl %ebp, %edx
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_4 Depth=1
# Parent Loop BB2_5 Depth=2
# => This Inner Loop Header: Depth=3
movl %edx, (%rax,%rcx)
incl %edx
addq $24, %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=2
incq %r14
incl %ebp
cmpq $10, %r14
jne .LBB2_5
# %bb.8: # in Loop: Header=BB2_4 Depth=1
incq %r15
cmpq $10, %r15
jne .LBB2_4
# %bb.9: # %.preheader.preheader
xorl %eax, %eax
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB2_10
.p2align 4, 0x90
.LBB2_13: # %._crit_edge
# in Loop: Header=BB2_10 Depth=1
addl %ecx, %ebx
incq %rax
cmpq $10, %rax
je .LBB2_14
.LBB2_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
leaq (%rax,%rax,2), %rdx
movq (%r13,%rdx,8), %rcx
testq %rcx, %rcx
je .LBB2_13
# %bb.11: # %.lr.ph
# in Loop: Header=BB2_10 Depth=1
movq 16(%r13,%rdx,8), %rdx
movq %rcx, %rsi
.p2align 4, 0x90
.LBB2_12: # Parent Loop BB2_10 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rdx), %r12d
addq $40, %rdx
decq %rsi
jne .LBB2_12
jmp .LBB2_13
.LBB2_14:
movl $160, %edi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movl %ebx, 36(%rsp) # 4-byte Spill
movslq %ebx, %rdi
shlq $5, %rdi
movq %rdi, 80(%rsp) # 8-byte Spill
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movslq %r12d, %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdi
movq %rdi, 88(%rsp) # 8-byte Spill
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
xorl %ecx, %ecx
movl $-2147483648, %esi # imm = 0x80000000
xorl %r11d, %r11d
xorl %r9d, %r9d
movq %r13, 96(%rsp) # 8-byte Spill
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_15 Depth=1
movl %r9d, %r14d
.LBB2_22: # %._crit_edge194
# in Loop: Header=BB2_15 Depth=1
movl 40(%rsp), %r11d # 4-byte Reload
addl %r8d, %r11d
movq 104(%rsp), %rcx # 8-byte Reload
incq %rcx
movl %r14d, %r9d
cmpq $10, %rcx
movq 96(%rsp), %r13 # 8-byte Reload
je .LBB2_23
.LBB2_15: # =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
# Child Loop BB2_20 Depth 3
leaq (%rcx,%rcx,2), %rax
movq (%r13,%rax,8), %r8
movq %rcx, 104(%rsp) # 8-byte Spill
shlq $4, %rcx
movq 64(%rsp), %rdx # 8-byte Reload
movq %r8, (%rdx,%rcx)
movq 8(%r13,%rax,8), %rdi
movq %rdi, 8(%rdx,%rcx)
testq %r8, %r8
movl %r11d, 40(%rsp) # 4-byte Spill
je .LBB2_16
# %bb.17: # %.lr.ph193
# in Loop: Header=BB2_15 Depth=1
movq 16(%r13,%rax,8), %r10
movslq %r11d, %rax
shlq $5, %rax
movq 56(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax), %r11
leaq (%rcx,%rax), %rbp
addq $4, %rbp
movl 16(%rcx,%rax), %r15d
xorl %ebx, %ebx
jmp .LBB2_18
.p2align 4, 0x90
.LBB2_21: # %._crit_edge188
# in Loop: Header=BB2_18 Depth=2
addl %r9d, %r14d
incq %rbx
movl %r14d, %r9d
cmpq %r8, %rbx
je .LBB2_22
.LBB2_18: # Parent Loop BB2_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_20 Depth 3
leaq (%rbx,%rbx,4), %rdi
movl (%r10,%rdi,8), %eax
movl %eax, (%r11)
movl 4(%r10,%rdi,8), %eax
movl %eax, (%rbp)
movl 8(%r10,%rdi,8), %eax
movl %eax, 4(%rbp)
movl 12(%r10,%rdi,8), %eax
movl %eax, 8(%rbp)
movl 16(%r10,%rdi,8), %eax
movl $536870911, %ecx # imm = 0x1FFFFFFF
andl %ecx, %eax
andl $-536870912, %r15d # imm = 0xE0000000
orl %eax, %r15d
movl %r15d, 12(%rbp)
movl 16(%r10,%rdi,8), %ecx
movl $1610612736, %edx # imm = 0x60000000
andl %edx, %ecx
andl $-1610612737, %r15d # imm = 0x9FFFFFFF
orl %ecx, %r15d
movl %r15d, 12(%rbp)
movl 16(%r10,%rdi,8), %r15d
andl %esi, %r15d
orl %eax, %r15d
orl %ecx, %r15d
movl %r15d, 12(%rbp)
movss 20(%r10,%rdi,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rbp)
movq 24(%r10,%rdi,8), %rax
movq %rax, 20(%rbp)
movl (%r10,%rdi,8), %r14d
testl %r14d, %r14d
jle .LBB2_21
# %bb.19: # %.lr.ph187
# in Loop: Header=BB2_18 Depth=2
movq 32(%r10,%rdi,8), %rdi
movslq %r9d, %rax
leaq (%rax,%rax,2), %rax
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r13
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_20: # Parent Loop BB2_15 Depth=1
# Parent Loop BB2_18 Depth=2
# => This Inner Loop Header: Depth=3
movq (%rdi,%rcx), %rdx
movq %rdx, (%r13)
movl 8(%rdi,%rcx), %edx
movl %edx, 8(%r13)
movl 12(%rdi,%rcx), %edx
movl %edx, 12(%r13)
movl 16(%rdi,%rcx), %edx
movl %edx, 16(%r13)
addq $24, %rcx
cmpq %rcx, %rax
jne .LBB2_20
jmp .LBB2_21
.LBB2_23:
leaq 16(%rsp), %rdi
movl $160, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit157
leaq 8(%rsp), %rdi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
movl 36(%rsp), %ebx # 4-byte Reload
movq 88(%rsp), %r14 # 8-byte Reload
jne .LBB2_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit159
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_28
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit161
movq 16(%rsp), %rdi
movl $160, %edx
movq 64(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit163
movq 8(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_32
# %bb.33: # %_Z9gpuAssert10hipError_tPKcib.exit165
movq (%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_34
# %bb.35: # %_Z9gpuAssert10hipError_tPKcib.exit167
movl $.L.str.2, %edi
movl $10, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_37
# %bb.36:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq 24(%rsp), %rsi
movl $10, 52(%rsp)
movl %ebx, 48(%rsp)
movl %r12d, 44(%rsp)
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movq %rsi, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 44(%rsp), %rax
movq %rax, 208(%rsp)
leaq 184(%rsp), %rax
movq %rax, 216(%rsp)
leaq 176(%rsp), %rax
movq %rax, 224(%rsp)
leaq 168(%rsp), %rax
movq %rax, 232(%rsp)
leaq 160(%rsp), %rax
movq %rax, 240(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_37:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB2_38
# %bb.39: # %_Z9gpuAssert10hipError_tPKcib.exit169
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_40
# %bb.41: # %_Z9gpuAssert10hipError_tPKcib.exit171
movq 24(%rsp), %rsi
leaq 192(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_42
# %bb.43: # %_Z9gpuAssert10hipError_tPKcib.exit173
movl 192(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 304
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB2_2
.LBB2_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $163, %r8d
jmp .LBB2_2
.LBB2_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $164, %r8d
jmp .LBB2_2
.LBB2_28:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $165, %r8d
jmp .LBB2_2
.LBB2_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $168, %r8d
jmp .LBB2_2
.LBB2_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $170, %r8d
jmp .LBB2_2
.LBB2_34:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $172, %r8d
jmp .LBB2_2
.LBB2_38:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $177, %r8d
jmp .LBB2_2
.LBB2_40:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $178, %r8d
jmp .LBB2_2
.LBB2_42:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $179, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPUassert: %s %s %d\n"
.size .L.str, 21
.type _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi,@object # @_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.section .rodata,"a",@progbits
.globl _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.p2align 3, 0x0
_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
.quad _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.size _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/vuongpd95/cuda-test/master/deepCopy_2/deepCopy_2.hip"
.size .L.str.1, 110
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "n = %d, n_a = %d\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "d_b = %d\n"
.size .L.str.3, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi"
.size .L__unnamed_1, 64
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000710e4_00000000-6_deepCopy_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.text
.globl _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.globl _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.type _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, @function
_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .-_Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.globl _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.type _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, @function
_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .-_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/vuongpd95/cuda-test/master/deepCopy_2/deepCopy_2.cu"
.section .rodata.str1.1
.LC2:
.string "n = %d, n_a = %d\n"
.LC3:
.string "d_b = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $240, %edi
call malloc@PLT
movq %rax, %r15
movl $0, %r14d
movq %rax, (%rsp)
movq %rax, 8(%rsp)
jmp .L22
.L43:
addl $1, %ebp
addq $40, %r12
cmpl %r13d, %ebp
je .L42
.L21:
movq %r12, %rbx
movl $10, -32(%r12)
movl $240, %edi
call malloc@PLT
movq %rax, (%r12)
movl $0, %edx
movl $0, %eax
.L20:
movq (%rbx), %rcx
leal (%rax,%rbp), %esi
movl %esi, 16(%rcx,%rdx)
addl $1, %eax
addq $24, %rdx
cmpl %eax, -32(%rbx)
jg .L20
jmp .L43
.L42:
addl $1, %r14d
addq $24, %r15
cmpl $10, %r14d
je .L44
.L22:
movq $10, (%r15)
movl $400, %edi
call malloc@PLT
movq %rax, 16(%r15)
leaq 32(%rax), %r12
movl %r14d, %ebp
leal 10(%r14), %r13d
jmp .L21
.L44:
movq (%rsp), %rbx
movq 8(%rsp), %rbp
leaq 240(%rbp), %r13
movq %rbp, %rcx
movl $0, %ebp
movl $0, %esi
jmp .L25
.L24:
addl (%rax), %ebp
addq $40, %rax
cmpq %rdx, %rax
jne .L24
.L23:
addq $24, %rcx
cmpq %r13, %rcx
je .L45
.L25:
movq (%rcx), %rdx
leal (%rsi,%rdx), %r14d
movl %r14d, %esi
testq %rdx, %rdx
je .L23
movq 16(%rcx), %rax
leaq (%rdx,%rdx,4), %rdx
leaq (%rax,%rdx,8), %rdx
jmp .L24
.L45:
movl $160, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movslq %r14d, %rax
salq $5, %rax
movq %rax, %rdi
movq %rax, 16(%rsp)
call malloc@PLT
movq %rax, %r15
movslq %ebp, %rax
leaq (%rax,%rax,2), %rax
leaq 0(,%rax,8), %rdi
movq %rdi, 32(%rsp)
call malloc@PLT
movq %rax, %r12
movq 24(%rsp), %rdx
movl $0, %r9d
movl $0, %edi
movl %r14d, 44(%rsp)
movl %ebp, %ecx
jmp .L30
.L29:
movl (%rsi), %r14d
movl %r14d, (%r8)
movl 4(%rsi), %eax
movl %eax, 4(%r8)
movl 8(%rsi), %eax
movl %eax, 8(%r8)
movl 12(%rsi), %eax
movl %eax, 12(%r8)
movl 16(%rsi), %eax
andl $536870911, %eax
movl 16(%r8), %r10d
andl $-536870912, %r10d
orl %eax, %r10d
movl %r10d, %eax
shrl $24, %eax
movl %r10d, 16(%r8)
movzbl 19(%rsi), %r10d
andl $96, %r10d
andl $-97, %eax
orl %r10d, %eax
movb %al, 19(%r8)
movzbl 19(%rsi), %r10d
andl $-128, %r10d
andl $127, %eax
orl %r10d, %eax
movb %al, 19(%r8)
movss 20(%rsi), %xmm0
movss %xmm0, 20(%r8)
movq 24(%rsi), %rax
movq %rax, 24(%r8)
testl %r14d, %r14d
jle .L27
movslq %r9d, %rax
leaq (%rax,%rax,2), %rax
leaq (%r12,%rax,8), %r10
movq 32(%rsi), %rax
movslq %r14d, %r11
leaq (%r11,%r11,2), %r11
leaq (%rax,%r11,8), %r11
movq %rdx, (%rsp)
.L28:
movq (%rax), %rdx
movq %rdx, (%r10)
movl 8(%rax), %edx
movl %edx, 8(%r10)
movl 12(%rax), %edx
movl %edx, 12(%r10)
movl 16(%rax), %edx
movl %edx, 16(%r10)
addq $24, %rax
cmpq %rax, %r11
jne .L28
movq (%rsp), %rdx
.L27:
addl %r14d, %r9d
addq $40, %rsi
cmpq %rbp, %rsi
jne .L29
movq 8(%rsp), %rax
.L26:
addl %eax, %edi
addq $24, %rbx
addq $16, %rdx
cmpq %r13, %rbx
je .L46
.L30:
movq (%rbx), %rax
movq %rax, (%rdx)
movq 8(%rbx), %rsi
movq %rsi, 8(%rdx)
testq %rax, %rax
je .L26
movslq %edi, %r8
salq $5, %r8
addq %r15, %r8
movq 16(%rbx), %rsi
leaq (%rax,%rax,4), %r10
leaq (%rsi,%r10,8), %rbp
movq %rax, 8(%rsp)
jmp .L29
.L46:
movl 44(%rsp), %r14d
movl %ecx, %ebp
leaq 56(%rsp), %rdi
movl $160, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $163, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 64(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $164, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 72(%rsp), %rdi
movq 32(%rsp), %r13
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $165, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $160, %edx
movq 24(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $167, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq 16(%rsp), %rdx
movq %r15, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $169, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $171, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl %r14d, %ecx
movl $10, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L31:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $177, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $178, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 92(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $179, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl 92(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
movq 88(%rsp), %r9
movq 80(%rsp), %r8
movq 72(%rsp), %rcx
movl %ebp, %edx
movl %r14d, %esi
movl $10, %edi
call _Z77__device_stub__Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPiiiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L31
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "deepCopy_2.hip"
.globl _Z9gpuAssert10hipError_tPKcib # -- Begin function _Z9gpuAssert10hipError_tPKcib
.p2align 4, 0x90
.type _Z9gpuAssert10hipError_tPKcib,@function
_Z9gpuAssert10hipError_tPKcib: # @_Z9gpuAssert10hipError_tPKcib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edi, %edi
jne .LBB0_1
.LBB0_2:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %r14
movl %edi, %ebx
movl %ecx, %r12d
movl %edx, %ebp
movq %rsi, %r15
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rax, %rdx
movq %r15, %rcx
movl %ebp, %r8d
xorl %eax, %eax
callq fprintf
testb %r12b, %r12b
je .LBB0_2
# %bb.3:
movl %ebx, %edi
callq exit
.Lfunc_end0:
.size _Z9gpuAssert10hipError_tPKcib, .Lfunc_end0-_Z9gpuAssert10hipError_tPKcib
.cfi_endproc
# -- End function
.globl _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi # -- Begin function _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.p2align 4, 0x90
.type _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi,@function
_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi: # @_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, .Lfunc_end1-_Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movl $240, %edi
callq malloc
movq %rax, %r13
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
# Child Loop BB2_6 Depth 3
leaq (%r15,%r15,2), %r14
movq $10, (%r13,%r14,8)
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movq %rax, 16(%r13,%r14,8)
movl %r15d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_4 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
leaq (%r14,%r14,4), %r12
movl $10, (%rbx,%r12,8)
movl $240, %edi
callq malloc
movq %rax, 32(%rbx,%r12,8)
movl $16, %ecx
movl %ebp, %edx
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_4 Depth=1
# Parent Loop BB2_5 Depth=2
# => This Inner Loop Header: Depth=3
movl %edx, (%rax,%rcx)
incl %edx
addq $24, %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=2
incq %r14
incl %ebp
cmpq $10, %r14
jne .LBB2_5
# %bb.8: # in Loop: Header=BB2_4 Depth=1
incq %r15
cmpq $10, %r15
jne .LBB2_4
# %bb.9: # %.preheader.preheader
xorl %eax, %eax
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB2_10
.p2align 4, 0x90
.LBB2_13: # %._crit_edge
# in Loop: Header=BB2_10 Depth=1
addl %ecx, %ebx
incq %rax
cmpq $10, %rax
je .LBB2_14
.LBB2_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
leaq (%rax,%rax,2), %rdx
movq (%r13,%rdx,8), %rcx
testq %rcx, %rcx
je .LBB2_13
# %bb.11: # %.lr.ph
# in Loop: Header=BB2_10 Depth=1
movq 16(%r13,%rdx,8), %rdx
movq %rcx, %rsi
.p2align 4, 0x90
.LBB2_12: # Parent Loop BB2_10 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rdx), %r12d
addq $40, %rdx
decq %rsi
jne .LBB2_12
jmp .LBB2_13
.LBB2_14:
movl $160, %edi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movl %ebx, 36(%rsp) # 4-byte Spill
movslq %ebx, %rdi
shlq $5, %rdi
movq %rdi, 80(%rsp) # 8-byte Spill
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movslq %r12d, %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdi
movq %rdi, 88(%rsp) # 8-byte Spill
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
xorl %ecx, %ecx
movl $-2147483648, %esi # imm = 0x80000000
xorl %r11d, %r11d
xorl %r9d, %r9d
movq %r13, 96(%rsp) # 8-byte Spill
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_15 Depth=1
movl %r9d, %r14d
.LBB2_22: # %._crit_edge194
# in Loop: Header=BB2_15 Depth=1
movl 40(%rsp), %r11d # 4-byte Reload
addl %r8d, %r11d
movq 104(%rsp), %rcx # 8-byte Reload
incq %rcx
movl %r14d, %r9d
cmpq $10, %rcx
movq 96(%rsp), %r13 # 8-byte Reload
je .LBB2_23
.LBB2_15: # =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
# Child Loop BB2_20 Depth 3
leaq (%rcx,%rcx,2), %rax
movq (%r13,%rax,8), %r8
movq %rcx, 104(%rsp) # 8-byte Spill
shlq $4, %rcx
movq 64(%rsp), %rdx # 8-byte Reload
movq %r8, (%rdx,%rcx)
movq 8(%r13,%rax,8), %rdi
movq %rdi, 8(%rdx,%rcx)
testq %r8, %r8
movl %r11d, 40(%rsp) # 4-byte Spill
je .LBB2_16
# %bb.17: # %.lr.ph193
# in Loop: Header=BB2_15 Depth=1
movq 16(%r13,%rax,8), %r10
movslq %r11d, %rax
shlq $5, %rax
movq 56(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax), %r11
leaq (%rcx,%rax), %rbp
addq $4, %rbp
movl 16(%rcx,%rax), %r15d
xorl %ebx, %ebx
jmp .LBB2_18
.p2align 4, 0x90
.LBB2_21: # %._crit_edge188
# in Loop: Header=BB2_18 Depth=2
addl %r9d, %r14d
incq %rbx
movl %r14d, %r9d
cmpq %r8, %rbx
je .LBB2_22
.LBB2_18: # Parent Loop BB2_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_20 Depth 3
leaq (%rbx,%rbx,4), %rdi
movl (%r10,%rdi,8), %eax
movl %eax, (%r11)
movl 4(%r10,%rdi,8), %eax
movl %eax, (%rbp)
movl 8(%r10,%rdi,8), %eax
movl %eax, 4(%rbp)
movl 12(%r10,%rdi,8), %eax
movl %eax, 8(%rbp)
movl 16(%r10,%rdi,8), %eax
movl $536870911, %ecx # imm = 0x1FFFFFFF
andl %ecx, %eax
andl $-536870912, %r15d # imm = 0xE0000000
orl %eax, %r15d
movl %r15d, 12(%rbp)
movl 16(%r10,%rdi,8), %ecx
movl $1610612736, %edx # imm = 0x60000000
andl %edx, %ecx
andl $-1610612737, %r15d # imm = 0x9FFFFFFF
orl %ecx, %r15d
movl %r15d, 12(%rbp)
movl 16(%r10,%rdi,8), %r15d
andl %esi, %r15d
orl %eax, %r15d
orl %ecx, %r15d
movl %r15d, 12(%rbp)
movss 20(%r10,%rdi,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rbp)
movq 24(%r10,%rdi,8), %rax
movq %rax, 20(%rbp)
movl (%r10,%rdi,8), %r14d
testl %r14d, %r14d
jle .LBB2_21
# %bb.19: # %.lr.ph187
# in Loop: Header=BB2_18 Depth=2
movq 32(%r10,%rdi,8), %rdi
movslq %r9d, %rax
leaq (%rax,%rax,2), %rax
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r13
leaq (,%r14,8), %rax
leaq (%rax,%rax,2), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_20: # Parent Loop BB2_15 Depth=1
# Parent Loop BB2_18 Depth=2
# => This Inner Loop Header: Depth=3
movq (%rdi,%rcx), %rdx
movq %rdx, (%r13)
movl 8(%rdi,%rcx), %edx
movl %edx, 8(%r13)
movl 12(%rdi,%rcx), %edx
movl %edx, 12(%r13)
movl 16(%rdi,%rcx), %edx
movl %edx, 16(%r13)
addq $24, %rcx
cmpq %rcx, %rax
jne .LBB2_20
jmp .LBB2_21
.LBB2_23:
leaq 16(%rsp), %rdi
movl $160, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit157
leaq 8(%rsp), %rdi
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
movl 36(%rsp), %ebx # 4-byte Reload
movq 88(%rsp), %r14 # 8-byte Reload
jne .LBB2_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit159
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_28
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit161
movq 16(%rsp), %rdi
movl $160, %edx
movq 64(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit163
movq 8(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_32
# %bb.33: # %_Z9gpuAssert10hipError_tPKcib.exit165
movq (%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_34
# %bb.35: # %_Z9gpuAssert10hipError_tPKcib.exit167
movl $.L.str.2, %edi
movl $10, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_37
# %bb.36:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq 24(%rsp), %rsi
movl $10, 52(%rsp)
movl %ebx, 48(%rsp)
movl %r12d, 44(%rsp)
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movq %rsi, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 44(%rsp), %rax
movq %rax, 208(%rsp)
leaq 184(%rsp), %rax
movq %rax, 216(%rsp)
leaq 176(%rsp), %rax
movq %rax, 224(%rsp)
leaq 168(%rsp), %rax
movq %rax, 232(%rsp)
leaq 160(%rsp), %rax
movq %rax, 240(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_37:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB2_38
# %bb.39: # %_Z9gpuAssert10hipError_tPKcib.exit169
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_40
# %bb.41: # %_Z9gpuAssert10hipError_tPKcib.exit171
movq 24(%rsp), %rsi
leaq 192(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_42
# %bb.43: # %_Z9gpuAssert10hipError_tPKcib.exit173
movl 192(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 304
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB2_2
.LBB2_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $163, %r8d
jmp .LBB2_2
.LBB2_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $164, %r8d
jmp .LBB2_2
.LBB2_28:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $165, %r8d
jmp .LBB2_2
.LBB2_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $168, %r8d
jmp .LBB2_2
.LBB2_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $170, %r8d
jmp .LBB2_2
.LBB2_34:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $172, %r8d
jmp .LBB2_2
.LBB2_38:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $177, %r8d
jmp .LBB2_2
.LBB2_40:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $178, %r8d
jmp .LBB2_2
.LBB2_42:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $179, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPUassert: %s %s %d\n"
.size .L.str, 21
.type _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi,@object # @_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.section .rodata,"a",@progbits
.globl _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.p2align 3, 0x0
_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi:
.quad _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.size _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/vuongpd95/cuda-test/master/deepCopy_2/deepCopy_2.hip"
.size .L.str.1, 110
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "n = %d, n_a = %d\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "d_b = %d\n"
.size .L.str.3, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi"
.size .L__unnamed_1, 64
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funciiiP16flat_mem_chain_vP16flat_mem_chain_tP10mem_seed_tPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //fonte: https://github.com/carloschilazo/CUDA_GA/blob/master/program.cu
#include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
using namespace std;
/* Cannot use built-in functions, need to rewrite pow function so it can run on the device, kinda reinventing the wheel over here
Im not sure if CUDA has something in its SDK, however better build it myself to avoid any overhead
0^0 even though is not defined, im treating it as 1
*/
__device__ void calculate_exponent(int base,int exponent,long &result){
result = 1L;
if(exponent==0){
return;
}
for(int counter=1;counter<=exponent;counter++){
result *= (long)base;
}
}
__global__ void evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores){
/*global position in population array index calculation */
int startingPosition = (blockIdx.y * threads_per_block * number_genes * individualsPerThread) + (threadIdx.y * number_genes * individualsPerThread);
if(startingPosition>=totalSizeOfArray){
return; //*return if thread is useless, the final block may have some threads that will not compute any data therefore we return early */
}
/*global position in scores array index calculation */
int startingPosition_scores = (blockIdx.y * threads_per_block * individualsPerThread) + (threadIdx.y * individualsPerThread);
long acumulated = 0L;
long temp = 0L;
for(int counter_individuals=0;counter_individuals<individualsPerThread;counter_individuals++){
if(startingPosition + (counter_individuals*number_genes) >= totalSizeOfArray){
return;
}
for(int counter_gene=0;counter_gene<number_genes;counter_gene++){
int base = startingPosition + (counter_individuals*number_genes) + counter_gene;
calculate_exponent(input[base],(number_genes-1)-counter_gene,temp);
acumulated += temp;
}
scores[startingPosition_scores+counter_individuals] = acumulated;
acumulated=0L;
}
}
__device__ void determine_fitness_solution(unsigned long desired_number, unsigned long actual_result, unsigned long &deviation){
if(desired_number>actual_result){
deviation = desired_number - actual_result;
}
if(actual_result>desired_number){
deviation = actual_result - desired_number;
}
if(actual_result==desired_number){
deviation = 0;
}
}
__global__ void scan_for_solution(long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error){
int starting_position_in_scores = (blockIdx.y * threads_per_block * individuals_per_thread) + (threadIdx.y * individuals_per_thread);
if(starting_position_in_scores>=number_individuals){
return; /* Return if useless thread */
}
unsigned long result;
unsigned long deviation;
for(int counter_individuals=0;counter_individuals<individuals_per_thread;counter_individuals++){
if(starting_position_in_scores+counter_individuals>=number_individuals){
return;
}
result = scores_array[starting_position_in_scores+counter_individuals];
determine_fitness_solution(desired_number,result,deviation);
if(deviation==0 || deviation<acceptable_error){
*solution_found_flag = starting_position_in_scores + counter_individuals;
}
}
}
int main(){
/* define settings */
const unsigned int number_genes = 10;
const unsigned int number_individuals = 10000000;
const unsigned int threads_per_block_evaluation = 500; //DO NOT FORGET: BLOCK IS 1 thread width, and threads_per_block height, MAX 512
const unsigned int individuals_per_thread_evaluation = 50;
/* desired algorithm result and acceptable error */
const unsigned long desired_number = 123456;
const unsigned int acceptable_error_window = 1000; /* So result can be +- acceptable_error_window */
/* allocate and randomly initialize memory for population */
int *population_array_host = new int[number_genes*number_individuals];
int *population_array_device;
srand ( time(NULL) );
for(int contador=0;contador<number_genes*number_individuals;contador++){
population_array_host[contador] = ( rand() % 10 );
}
size_t memory_for_population = number_genes*number_individuals*sizeof(int);
cudaMalloc((void **) &population_array_device, memory_for_population);
/* allocate and zeroise scores array, avoid any future issues with non initialized arrays */
long *scores_array_host = new long[number_individuals];
long *scores_array_device;
for(int contador=0;contador<number_individuals;contador++){
scores_array_host[contador] = 0L;
}
size_t memory_for_scores = number_individuals*sizeof(long);
cudaMalloc((void **) &scores_array_device, memory_for_scores);
/* allocate and initialize memory for acceptable result flag, flag indicates the element of the population which has the result */
int *solution_found_host = new int;
*solution_found_host = -1;
int *solution_found_device;
size_t memory_solution_found = sizeof(int);
cudaMalloc((void **) &solution_found_device, memory_solution_found);
/* we move data from host to device*/
cudaMemcpy(population_array_device, population_array_host, memory_for_population, cudaMemcpyHostToDevice);
cudaMemcpy(scores_array_device, scores_array_host, memory_for_scores, cudaMemcpyHostToDevice);
cudaMemcpy(solution_found_device, solution_found_host, memory_solution_found, cudaMemcpyHostToDevice);
/* we calculate dimensions for grid and blocks and create them: for evaluation */
unsigned int blocks_required_evaluation = number_individuals/(threads_per_block_evaluation *individuals_per_thread_evaluation) +
(number_individuals%(threads_per_block_evaluation *individuals_per_thread_evaluation) == 0 ? 0:1);
dim3 grid_evaluation(1,blocks_required_evaluation); /* in terms of blocks */
dim3 block_evaluation(1,threads_per_block_evaluation); /* in terms of threads*/
/* define how many elements per thread, threads and blocks should be launched to scan the score of each individual, we create dim elements accordingly*/
const unsigned int individuals_per_thread_scan_scores = 50;
const unsigned int threads_per_block_scan_scores = 511; // remember block is 1 thread width and threads_per_block_scan_scores height
const unsigned int blocks_required_scan_scores = (number_individuals/ (individuals_per_thread_scan_scores * threads_per_block_scan_scores)) +
(number_individuals%(threads_per_block_scan_scores * individuals_per_thread_scan_scores) == 0 ? 0:1);
dim3 grid_scan_scores(1,blocks_required_scan_scores); // in terms of blocks
dim3 block_scan_scores(1,threads_per_block_scan_scores); // in terms of threads
/* output parameters */
cout << "-Algorithm parameters-" << endl;
cout << "Individuals: " << number_individuals << endl;
cout << "Genes per individual: " << number_genes << endl;
cout << "Individuals computed per thread: " << individuals_per_thread_evaluation << endl;
cout << "-Computing distribution for evaluation-" << endl;
cout << "Blocks required: " << blocks_required_evaluation << endl;
cout << "Threads per block: " << threads_per_block_evaluation << endl;
cout << "Total number of threads: " << blocks_required_evaluation*threads_per_block_evaluation << endl;
cout << "-Computing distribution for scan_results-" << endl;
cout << "Individuals (scores) evaluated per thread: " << individuals_per_thread_scan_scores << endl;
cout << "Threads per block: " << threads_per_block_scan_scores << endl;
cout << "Blocks required: " << blocks_required_scan_scores << endl;
cout << endl << "Algorithm Start" << endl;
/*we launch evaluation kernel: evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores)*/
evaluate <<< grid_evaluation, block_evaluation >>> (population_array_device, number_genes*number_individuals, number_genes, individuals_per_thread_evaluation, blocks_required_evaluation, threads_per_block_evaluation, scores_array_device);
/* long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error */
scan_for_solution <<< grid_scan_scores, block_scan_scores >>> (scores_array_device, number_individuals, individuals_per_thread_scan_scores, threads_per_block_scan_scores, solution_found_device, desired_number, acceptable_error_window);
//cudaMemcpy(scores_array_host, scores_array_device, memory_for_scores, cudaMemcpyDeviceToHost);
//cudaMemcpy(population_array_host, population_array_device, memory_for_population, cudaMemcpyDeviceToHost);
cudaMemcpy(solution_found_host, solution_found_device, memory_solution_found, cudaMemcpyDeviceToHost);
cout << *solution_found_host << endl;
//cout << scores_array_host[*solution_found_host] << endl;
return 0;
} | .file "tmpxft_000386e1_00000000-6_genetic_algorithm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18calculate_exponentiiRl
.type _Z18calculate_exponentiiRl, @function
_Z18calculate_exponentiiRl:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z18calculate_exponentiiRl, .-_Z18calculate_exponentiiRl
.globl _Z26determine_fitness_solutionmmRm
.type _Z26determine_fitness_solutionmmRm, @function
_Z26determine_fitness_solutionmmRm:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z26determine_fitness_solutionmmRm, .-_Z26determine_fitness_solutionmmRm
.globl _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl
.type _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl, @function
_Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl:
.LFB3696:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 20(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8evaluatePiiiiiiPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl, .-_Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl
.globl _Z8evaluatePiiiiiiPl
.type _Z8evaluatePiiiiiiPl, @function
_Z8evaluatePiiiiiiPl:
.LFB3697:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8evaluatePiiiiiiPl, .-_Z8evaluatePiiiiiiPl
.globl _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi
.type _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi, @function
_Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi:
.LFB3698:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17scan_for_solutionPliiiPimi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi, .-_Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi
.globl _Z17scan_for_solutionPliiiPimi
.type _Z17scan_for_solutionPliiiPimi, @function
_Z17scan_for_solutionPliiiPimi:
.LFB3699:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z17scan_for_solutionPliiiPimi, .-_Z17scan_for_solutionPliiiPimi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "-Algorithm parameters-"
.LC1:
.string "Individuals: "
.LC2:
.string "Genes per individual: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Individuals computed per thread: "
.align 8
.LC4:
.string "-Computing distribution for evaluation-"
.section .rodata.str1.1
.LC5:
.string "Blocks required: "
.LC6:
.string "Threads per block: "
.LC7:
.string "Total number of threads: "
.section .rodata.str1.8
.align 8
.LC8:
.string "-Computing distribution for scan_results-"
.align 8
.LC9:
.string "Individuals (scores) evaluated per thread: "
.section .rodata.str1.1
.LC10:
.string "Algorithm Start"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $400000000, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 400000000(%r12), %rbp
.L24:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $80000000, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 80000000(%rax), %rdx
.L25:
movq $0, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L25
leaq 8(%rsp), %rdi
movl $80000000, %esi
call cudaMalloc@PLT
movl $4, %edi
call _Znwm@PLT
movq %rax, %rbp
movl $-1, (%rax)
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000000, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $400, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $500, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $392, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $511, 64(%rsp)
movl $1, 68(%rsp)
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10000000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $50, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %r12
movq %r12, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $400, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %r13
movq %r13, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $500, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $200000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $50, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $511, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $392, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq 16(%rsp)
.cfi_def_cfa_offset 144
movl $500, %r9d
movl $400, %r8d
movl $50, %ecx
movl $10, %edx
movl $100000000, %esi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L26
.L33:
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $1000
.cfi_def_cfa_offset 144
movl $123456, %r9d
movq 32(%rsp), %r8
movl $511, %ecx
movl $50, %edx
movl $10000000, %esi
movq 24(%rsp), %rdi
call _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z17scan_for_solutionPliiiPimi"
.section .rodata.str1.1
.LC12:
.string "_Z8evaluatePiiiiiiPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z17scan_for_solutionPliiiPimi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z8evaluatePiiiiiiPl(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //fonte: https://github.com/carloschilazo/CUDA_GA/blob/master/program.cu
#include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
using namespace std;
/* Cannot use built-in functions, need to rewrite pow function so it can run on the device, kinda reinventing the wheel over here
Im not sure if CUDA has something in its SDK, however better build it myself to avoid any overhead
0^0 even though is not defined, im treating it as 1
*/
__device__ void calculate_exponent(int base,int exponent,long &result){
result = 1L;
if(exponent==0){
return;
}
for(int counter=1;counter<=exponent;counter++){
result *= (long)base;
}
}
__global__ void evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores){
/*global position in population array index calculation */
int startingPosition = (blockIdx.y * threads_per_block * number_genes * individualsPerThread) + (threadIdx.y * number_genes * individualsPerThread);
if(startingPosition>=totalSizeOfArray){
return; //*return if thread is useless, the final block may have some threads that will not compute any data therefore we return early */
}
/*global position in scores array index calculation */
int startingPosition_scores = (blockIdx.y * threads_per_block * individualsPerThread) + (threadIdx.y * individualsPerThread);
long acumulated = 0L;
long temp = 0L;
for(int counter_individuals=0;counter_individuals<individualsPerThread;counter_individuals++){
if(startingPosition + (counter_individuals*number_genes) >= totalSizeOfArray){
return;
}
for(int counter_gene=0;counter_gene<number_genes;counter_gene++){
int base = startingPosition + (counter_individuals*number_genes) + counter_gene;
calculate_exponent(input[base],(number_genes-1)-counter_gene,temp);
acumulated += temp;
}
scores[startingPosition_scores+counter_individuals] = acumulated;
acumulated=0L;
}
}
__device__ void determine_fitness_solution(unsigned long desired_number, unsigned long actual_result, unsigned long &deviation){
if(desired_number>actual_result){
deviation = desired_number - actual_result;
}
if(actual_result>desired_number){
deviation = actual_result - desired_number;
}
if(actual_result==desired_number){
deviation = 0;
}
}
__global__ void scan_for_solution(long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error){
int starting_position_in_scores = (blockIdx.y * threads_per_block * individuals_per_thread) + (threadIdx.y * individuals_per_thread);
if(starting_position_in_scores>=number_individuals){
return; /* Return if useless thread */
}
unsigned long result;
unsigned long deviation;
for(int counter_individuals=0;counter_individuals<individuals_per_thread;counter_individuals++){
if(starting_position_in_scores+counter_individuals>=number_individuals){
return;
}
result = scores_array[starting_position_in_scores+counter_individuals];
determine_fitness_solution(desired_number,result,deviation);
if(deviation==0 || deviation<acceptable_error){
*solution_found_flag = starting_position_in_scores + counter_individuals;
}
}
}
int main(){
/* define settings */
const unsigned int number_genes = 10;
const unsigned int number_individuals = 10000000;
const unsigned int threads_per_block_evaluation = 500; //DO NOT FORGET: BLOCK IS 1 thread width, and threads_per_block height, MAX 512
const unsigned int individuals_per_thread_evaluation = 50;
/* desired algorithm result and acceptable error */
const unsigned long desired_number = 123456;
const unsigned int acceptable_error_window = 1000; /* So result can be +- acceptable_error_window */
/* allocate and randomly initialize memory for population */
int *population_array_host = new int[number_genes*number_individuals];
int *population_array_device;
srand ( time(NULL) );
for(int contador=0;contador<number_genes*number_individuals;contador++){
population_array_host[contador] = ( rand() % 10 );
}
size_t memory_for_population = number_genes*number_individuals*sizeof(int);
cudaMalloc((void **) &population_array_device, memory_for_population);
/* allocate and zeroise scores array, avoid any future issues with non initialized arrays */
long *scores_array_host = new long[number_individuals];
long *scores_array_device;
for(int contador=0;contador<number_individuals;contador++){
scores_array_host[contador] = 0L;
}
size_t memory_for_scores = number_individuals*sizeof(long);
cudaMalloc((void **) &scores_array_device, memory_for_scores);
/* allocate and initialize memory for acceptable result flag, flag indicates the element of the population which has the result */
int *solution_found_host = new int;
*solution_found_host = -1;
int *solution_found_device;
size_t memory_solution_found = sizeof(int);
cudaMalloc((void **) &solution_found_device, memory_solution_found);
/* we move data from host to device*/
cudaMemcpy(population_array_device, population_array_host, memory_for_population, cudaMemcpyHostToDevice);
cudaMemcpy(scores_array_device, scores_array_host, memory_for_scores, cudaMemcpyHostToDevice);
cudaMemcpy(solution_found_device, solution_found_host, memory_solution_found, cudaMemcpyHostToDevice);
/* we calculate dimensions for grid and blocks and create them: for evaluation */
unsigned int blocks_required_evaluation = number_individuals/(threads_per_block_evaluation *individuals_per_thread_evaluation) +
(number_individuals%(threads_per_block_evaluation *individuals_per_thread_evaluation) == 0 ? 0:1);
dim3 grid_evaluation(1,blocks_required_evaluation); /* in terms of blocks */
dim3 block_evaluation(1,threads_per_block_evaluation); /* in terms of threads*/
/* define how many elements per thread, threads and blocks should be launched to scan the score of each individual, we create dim elements accordingly*/
const unsigned int individuals_per_thread_scan_scores = 50;
const unsigned int threads_per_block_scan_scores = 511; // remember block is 1 thread width and threads_per_block_scan_scores height
const unsigned int blocks_required_scan_scores = (number_individuals/ (individuals_per_thread_scan_scores * threads_per_block_scan_scores)) +
(number_individuals%(threads_per_block_scan_scores * individuals_per_thread_scan_scores) == 0 ? 0:1);
dim3 grid_scan_scores(1,blocks_required_scan_scores); // in terms of blocks
dim3 block_scan_scores(1,threads_per_block_scan_scores); // in terms of threads
/* output parameters */
cout << "-Algorithm parameters-" << endl;
cout << "Individuals: " << number_individuals << endl;
cout << "Genes per individual: " << number_genes << endl;
cout << "Individuals computed per thread: " << individuals_per_thread_evaluation << endl;
cout << "-Computing distribution for evaluation-" << endl;
cout << "Blocks required: " << blocks_required_evaluation << endl;
cout << "Threads per block: " << threads_per_block_evaluation << endl;
cout << "Total number of threads: " << blocks_required_evaluation*threads_per_block_evaluation << endl;
cout << "-Computing distribution for scan_results-" << endl;
cout << "Individuals (scores) evaluated per thread: " << individuals_per_thread_scan_scores << endl;
cout << "Threads per block: " << threads_per_block_scan_scores << endl;
cout << "Blocks required: " << blocks_required_scan_scores << endl;
cout << endl << "Algorithm Start" << endl;
/*we launch evaluation kernel: evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores)*/
evaluate <<< grid_evaluation, block_evaluation >>> (population_array_device, number_genes*number_individuals, number_genes, individuals_per_thread_evaluation, blocks_required_evaluation, threads_per_block_evaluation, scores_array_device);
/* long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error */
scan_for_solution <<< grid_scan_scores, block_scan_scores >>> (scores_array_device, number_individuals, individuals_per_thread_scan_scores, threads_per_block_scan_scores, solution_found_device, desired_number, acceptable_error_window);
//cudaMemcpy(scores_array_host, scores_array_device, memory_for_scores, cudaMemcpyDeviceToHost);
//cudaMemcpy(population_array_host, population_array_device, memory_for_population, cudaMemcpyDeviceToHost);
cudaMemcpy(solution_found_host, solution_found_device, memory_solution_found, cudaMemcpyDeviceToHost);
cout << *solution_found_host << endl;
//cout << scores_array_host[*solution_found_host] << endl;
return 0;
} | //fonte: https://github.com/carloschilazo/CUDA_GA/blob/master/program.cu
#include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
using namespace std;
/* Cannot use built-in functions, need to rewrite pow function so it can run on the device, kinda reinventing the wheel over here
Im not sure if CUDA has something in its SDK, however better build it myself to avoid any overhead
0^0 even though is not defined, im treating it as 1
*/
__device__ void calculate_exponent(int base,int exponent,long &result){
result = 1L;
if(exponent==0){
return;
}
for(int counter=1;counter<=exponent;counter++){
result *= (long)base;
}
}
__global__ void evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores){
/*global position in population array index calculation */
int startingPosition = (blockIdx.y * threads_per_block * number_genes * individualsPerThread) + (threadIdx.y * number_genes * individualsPerThread);
if(startingPosition>=totalSizeOfArray){
return; //*return if thread is useless, the final block may have some threads that will not compute any data therefore we return early */
}
/*global position in scores array index calculation */
int startingPosition_scores = (blockIdx.y * threads_per_block * individualsPerThread) + (threadIdx.y * individualsPerThread);
long acumulated = 0L;
long temp = 0L;
for(int counter_individuals=0;counter_individuals<individualsPerThread;counter_individuals++){
if(startingPosition + (counter_individuals*number_genes) >= totalSizeOfArray){
return;
}
for(int counter_gene=0;counter_gene<number_genes;counter_gene++){
int base = startingPosition + (counter_individuals*number_genes) + counter_gene;
calculate_exponent(input[base],(number_genes-1)-counter_gene,temp);
acumulated += temp;
}
scores[startingPosition_scores+counter_individuals] = acumulated;
acumulated=0L;
}
}
__device__ void determine_fitness_solution(unsigned long desired_number, unsigned long actual_result, unsigned long &deviation){
if(desired_number>actual_result){
deviation = desired_number - actual_result;
}
if(actual_result>desired_number){
deviation = actual_result - desired_number;
}
if(actual_result==desired_number){
deviation = 0;
}
}
__global__ void scan_for_solution(long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error){
int starting_position_in_scores = (blockIdx.y * threads_per_block * individuals_per_thread) + (threadIdx.y * individuals_per_thread);
if(starting_position_in_scores>=number_individuals){
return; /* Return if useless thread */
}
unsigned long result;
unsigned long deviation;
for(int counter_individuals=0;counter_individuals<individuals_per_thread;counter_individuals++){
if(starting_position_in_scores+counter_individuals>=number_individuals){
return;
}
result = scores_array[starting_position_in_scores+counter_individuals];
determine_fitness_solution(desired_number,result,deviation);
if(deviation==0 || deviation<acceptable_error){
*solution_found_flag = starting_position_in_scores + counter_individuals;
}
}
}
int main(){
/* define settings */
const unsigned int number_genes = 10;
const unsigned int number_individuals = 10000000;
const unsigned int threads_per_block_evaluation = 500; //DO NOT FORGET: BLOCK IS 1 thread width, and threads_per_block height, MAX 512
const unsigned int individuals_per_thread_evaluation = 50;
/* desired algorithm result and acceptable error */
const unsigned long desired_number = 123456;
const unsigned int acceptable_error_window = 1000; /* So result can be +- acceptable_error_window */
/* allocate and randomly initialize memory for population */
int *population_array_host = new int[number_genes*number_individuals];
int *population_array_device;
srand ( time(NULL) );
for(int contador=0;contador<number_genes*number_individuals;contador++){
population_array_host[contador] = ( rand() % 10 );
}
size_t memory_for_population = number_genes*number_individuals*sizeof(int);
hipMalloc((void **) &population_array_device, memory_for_population);
/* allocate and zeroise scores array, avoid any future issues with non initialized arrays */
long *scores_array_host = new long[number_individuals];
long *scores_array_device;
for(int contador=0;contador<number_individuals;contador++){
scores_array_host[contador] = 0L;
}
size_t memory_for_scores = number_individuals*sizeof(long);
hipMalloc((void **) &scores_array_device, memory_for_scores);
/* allocate and initialize memory for acceptable result flag, flag indicates the element of the population which has the result */
int *solution_found_host = new int;
*solution_found_host = -1;
int *solution_found_device;
size_t memory_solution_found = sizeof(int);
hipMalloc((void **) &solution_found_device, memory_solution_found);
/* we move data from host to device*/
hipMemcpy(population_array_device, population_array_host, memory_for_population, hipMemcpyHostToDevice);
hipMemcpy(scores_array_device, scores_array_host, memory_for_scores, hipMemcpyHostToDevice);
hipMemcpy(solution_found_device, solution_found_host, memory_solution_found, hipMemcpyHostToDevice);
/* we calculate dimensions for grid and blocks and create them: for evaluation */
unsigned int blocks_required_evaluation = number_individuals/(threads_per_block_evaluation *individuals_per_thread_evaluation) +
(number_individuals%(threads_per_block_evaluation *individuals_per_thread_evaluation) == 0 ? 0:1);
dim3 grid_evaluation(1,blocks_required_evaluation); /* in terms of blocks */
dim3 block_evaluation(1,threads_per_block_evaluation); /* in terms of threads*/
/* define how many elements per thread, threads and blocks should be launched to scan the score of each individual, we create dim elements accordingly*/
const unsigned int individuals_per_thread_scan_scores = 50;
const unsigned int threads_per_block_scan_scores = 511; // remember block is 1 thread width and threads_per_block_scan_scores height
const unsigned int blocks_required_scan_scores = (number_individuals/ (individuals_per_thread_scan_scores * threads_per_block_scan_scores)) +
(number_individuals%(threads_per_block_scan_scores * individuals_per_thread_scan_scores) == 0 ? 0:1);
dim3 grid_scan_scores(1,blocks_required_scan_scores); // in terms of blocks
dim3 block_scan_scores(1,threads_per_block_scan_scores); // in terms of threads
/* output parameters */
cout << "-Algorithm parameters-" << endl;
cout << "Individuals: " << number_individuals << endl;
cout << "Genes per individual: " << number_genes << endl;
cout << "Individuals computed per thread: " << individuals_per_thread_evaluation << endl;
cout << "-Computing distribution for evaluation-" << endl;
cout << "Blocks required: " << blocks_required_evaluation << endl;
cout << "Threads per block: " << threads_per_block_evaluation << endl;
cout << "Total number of threads: " << blocks_required_evaluation*threads_per_block_evaluation << endl;
cout << "-Computing distribution for scan_results-" << endl;
cout << "Individuals (scores) evaluated per thread: " << individuals_per_thread_scan_scores << endl;
cout << "Threads per block: " << threads_per_block_scan_scores << endl;
cout << "Blocks required: " << blocks_required_scan_scores << endl;
cout << endl << "Algorithm Start" << endl;
/*we launch evaluation kernel: evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores)*/
evaluate <<< grid_evaluation, block_evaluation >>> (population_array_device, number_genes*number_individuals, number_genes, individuals_per_thread_evaluation, blocks_required_evaluation, threads_per_block_evaluation, scores_array_device);
/* long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error */
scan_for_solution <<< grid_scan_scores, block_scan_scores >>> (scores_array_device, number_individuals, individuals_per_thread_scan_scores, threads_per_block_scan_scores, solution_found_device, desired_number, acceptable_error_window);
//cudaMemcpy(scores_array_host, scores_array_device, memory_for_scores, cudaMemcpyDeviceToHost);
//cudaMemcpy(population_array_host, population_array_device, memory_for_population, cudaMemcpyDeviceToHost);
hipMemcpy(solution_found_host, solution_found_device, memory_solution_found, hipMemcpyDeviceToHost);
cout << *solution_found_host << endl;
//cout << scores_array_host[*solution_found_host] << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //fonte: https://github.com/carloschilazo/CUDA_GA/blob/master/program.cu
#include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
using namespace std;
/* Cannot use built-in functions, need to rewrite pow function so it can run on the device, kinda reinventing the wheel over here
Im not sure if CUDA has something in its SDK, however better build it myself to avoid any overhead
0^0 even though is not defined, im treating it as 1
*/
__device__ void calculate_exponent(int base,int exponent,long &result){
result = 1L;
if(exponent==0){
return;
}
for(int counter=1;counter<=exponent;counter++){
result *= (long)base;
}
}
__global__ void evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores){
/*global position in population array index calculation */
int startingPosition = (blockIdx.y * threads_per_block * number_genes * individualsPerThread) + (threadIdx.y * number_genes * individualsPerThread);
if(startingPosition>=totalSizeOfArray){
return; //*return if thread is useless, the final block may have some threads that will not compute any data therefore we return early */
}
/*global position in scores array index calculation */
int startingPosition_scores = (blockIdx.y * threads_per_block * individualsPerThread) + (threadIdx.y * individualsPerThread);
long acumulated = 0L;
long temp = 0L;
for(int counter_individuals=0;counter_individuals<individualsPerThread;counter_individuals++){
if(startingPosition + (counter_individuals*number_genes) >= totalSizeOfArray){
return;
}
for(int counter_gene=0;counter_gene<number_genes;counter_gene++){
int base = startingPosition + (counter_individuals*number_genes) + counter_gene;
calculate_exponent(input[base],(number_genes-1)-counter_gene,temp);
acumulated += temp;
}
scores[startingPosition_scores+counter_individuals] = acumulated;
acumulated=0L;
}
}
__device__ void determine_fitness_solution(unsigned long desired_number, unsigned long actual_result, unsigned long &deviation){
if(desired_number>actual_result){
deviation = desired_number - actual_result;
}
if(actual_result>desired_number){
deviation = actual_result - desired_number;
}
if(actual_result==desired_number){
deviation = 0;
}
}
__global__ void scan_for_solution(long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error){
int starting_position_in_scores = (blockIdx.y * threads_per_block * individuals_per_thread) + (threadIdx.y * individuals_per_thread);
if(starting_position_in_scores>=number_individuals){
return; /* Return if useless thread */
}
unsigned long result;
unsigned long deviation;
for(int counter_individuals=0;counter_individuals<individuals_per_thread;counter_individuals++){
if(starting_position_in_scores+counter_individuals>=number_individuals){
return;
}
result = scores_array[starting_position_in_scores+counter_individuals];
determine_fitness_solution(desired_number,result,deviation);
if(deviation==0 || deviation<acceptable_error){
*solution_found_flag = starting_position_in_scores + counter_individuals;
}
}
}
int main(){
/* define settings */
const unsigned int number_genes = 10;
const unsigned int number_individuals = 10000000;
const unsigned int threads_per_block_evaluation = 500; //DO NOT FORGET: BLOCK IS 1 thread width, and threads_per_block height, MAX 512
const unsigned int individuals_per_thread_evaluation = 50;
/* desired algorithm result and acceptable error */
const unsigned long desired_number = 123456;
const unsigned int acceptable_error_window = 1000; /* So result can be +- acceptable_error_window */
/* allocate and randomly initialize memory for population */
int *population_array_host = new int[number_genes*number_individuals];
int *population_array_device;
srand ( time(NULL) );
for(int contador=0;contador<number_genes*number_individuals;contador++){
population_array_host[contador] = ( rand() % 10 );
}
size_t memory_for_population = number_genes*number_individuals*sizeof(int);
hipMalloc((void **) &population_array_device, memory_for_population);
/* allocate and zeroise scores array, avoid any future issues with non initialized arrays */
long *scores_array_host = new long[number_individuals];
long *scores_array_device;
for(int contador=0;contador<number_individuals;contador++){
scores_array_host[contador] = 0L;
}
size_t memory_for_scores = number_individuals*sizeof(long);
hipMalloc((void **) &scores_array_device, memory_for_scores);
/* allocate and initialize memory for acceptable result flag, flag indicates the element of the population which has the result */
int *solution_found_host = new int;
*solution_found_host = -1;
int *solution_found_device;
size_t memory_solution_found = sizeof(int);
hipMalloc((void **) &solution_found_device, memory_solution_found);
/* we move data from host to device*/
hipMemcpy(population_array_device, population_array_host, memory_for_population, hipMemcpyHostToDevice);
hipMemcpy(scores_array_device, scores_array_host, memory_for_scores, hipMemcpyHostToDevice);
hipMemcpy(solution_found_device, solution_found_host, memory_solution_found, hipMemcpyHostToDevice);
/* we calculate dimensions for grid and blocks and create them: for evaluation */
unsigned int blocks_required_evaluation = number_individuals/(threads_per_block_evaluation *individuals_per_thread_evaluation) +
(number_individuals%(threads_per_block_evaluation *individuals_per_thread_evaluation) == 0 ? 0:1);
dim3 grid_evaluation(1,blocks_required_evaluation); /* in terms of blocks */
dim3 block_evaluation(1,threads_per_block_evaluation); /* in terms of threads*/
/* define how many elements per thread, threads and blocks should be launched to scan the score of each individual, we create dim elements accordingly*/
const unsigned int individuals_per_thread_scan_scores = 50;
const unsigned int threads_per_block_scan_scores = 511; // remember block is 1 thread width and threads_per_block_scan_scores height
const unsigned int blocks_required_scan_scores = (number_individuals/ (individuals_per_thread_scan_scores * threads_per_block_scan_scores)) +
(number_individuals%(threads_per_block_scan_scores * individuals_per_thread_scan_scores) == 0 ? 0:1);
dim3 grid_scan_scores(1,blocks_required_scan_scores); // in terms of blocks
dim3 block_scan_scores(1,threads_per_block_scan_scores); // in terms of threads
/* output parameters */
cout << "-Algorithm parameters-" << endl;
cout << "Individuals: " << number_individuals << endl;
cout << "Genes per individual: " << number_genes << endl;
cout << "Individuals computed per thread: " << individuals_per_thread_evaluation << endl;
cout << "-Computing distribution for evaluation-" << endl;
cout << "Blocks required: " << blocks_required_evaluation << endl;
cout << "Threads per block: " << threads_per_block_evaluation << endl;
cout << "Total number of threads: " << blocks_required_evaluation*threads_per_block_evaluation << endl;
cout << "-Computing distribution for scan_results-" << endl;
cout << "Individuals (scores) evaluated per thread: " << individuals_per_thread_scan_scores << endl;
cout << "Threads per block: " << threads_per_block_scan_scores << endl;
cout << "Blocks required: " << blocks_required_scan_scores << endl;
cout << endl << "Algorithm Start" << endl;
/*we launch evaluation kernel: evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores)*/
evaluate <<< grid_evaluation, block_evaluation >>> (population_array_device, number_genes*number_individuals, number_genes, individuals_per_thread_evaluation, blocks_required_evaluation, threads_per_block_evaluation, scores_array_device);
/* long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error */
scan_for_solution <<< grid_scan_scores, block_scan_scores >>> (scores_array_device, number_individuals, individuals_per_thread_scan_scores, threads_per_block_scan_scores, solution_found_device, desired_number, acceptable_error_window);
//cudaMemcpy(scores_array_host, scores_array_device, memory_for_scores, cudaMemcpyDeviceToHost);
//cudaMemcpy(population_array_host, population_array_device, memory_for_population, cudaMemcpyDeviceToHost);
hipMemcpy(solution_found_host, solution_found_device, memory_solution_found, hipMemcpyDeviceToHost);
cout << *solution_found_host << endl;
//cout << scores_array_host[*solution_found_host] << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8evaluatePiiiiiiPl
.globl _Z8evaluatePiiiiiiPl
.p2align 8
.type _Z8evaluatePiiiiiiPl,@function
_Z8evaluatePiiiiiiPl:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_mul_lo_u32 v8, v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v8, s3
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_12
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_12
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
s_cmp_gt_i32 s3, 0
s_mov_b32 s8, 0
s_cselect_b32 s7, -1, 0
s_add_i32 s9, s3, -1
s_mov_b32 s10, 0
s_branch .LBB0_5
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s10, s6
s_cselect_b32 s13, -1, 0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_and_not1_b32 s11, s11, exec_lo
s_and_b32 s13, s13, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 s11, s11, s13
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s12, exec_lo, s11
s_or_b32 s8, s12, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_12
.LBB0_5:
v_add_nc_u32_e32 v0, s10, v8
s_or_b32 s11, s11, exec_lo
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s3
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_3
s_mov_b32 s13, 0
s_mov_b32 s14, s9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
v_add_co_u32 v2, vcc_lo, v4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo
s_add_i32 s13, s13, 1
s_add_i32 s14, s14, -1
s_cmp_eq_u32 s13, s3
s_cbranch_scc1 .LBB0_3
.LBB0_9:
s_not_b32 s15, s13
v_mov_b32_e32 v4, 1
v_mov_b32_e32 v5, 0
s_add_i32 s15, s15, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s15, 1
s_cbranch_scc1 .LBB0_8
v_add_nc_u32_e32 v4, s13, v1
v_mov_b32_e32 v6, 1
v_mov_b32_e32 v7, 0
s_mov_b32 s15, s14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v7, v9
v_mul_lo_u32 v11, v6, v10
v_mad_u64_u32 v[4:5], null, v6, v9, 0
s_add_i32 s15, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s15, 0
v_add3_u32 v5, v5, v11, v7
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_cbranch_scc1 .LBB0_11
s_branch .LBB0_8
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8evaluatePiiiiiiPl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8evaluatePiiiiiiPl, .Lfunc_end0-_Z8evaluatePiiiiiiPl
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17scan_for_solutionPliiiPimi
.globl _Z17scan_for_solutionPliiiPimi
.p2align 8
.type _Z17scan_for_solutionPliiiPimi,@function
_Z17scan_for_solutionPliiiPimi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cmp_gt_i32 s3, 0
s_cselect_b32 s4, -1, 0
v_mul_lo_u32 v0, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_7
s_clause 0x2
s_load_b64 s[12:13], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x28
s_load_b128 s[4:7], s[0:1], 0x18
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s12, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
s_ashr_i32 s9, s8, 31
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s3, s3, -1
v_add_co_u32 v1, vcc_lo, v1, 8
s_cmp_eq_u32 s3, 0
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cselect_b32 s0, -1, 0
v_add_nc_u32_e32 v0, 1, v0
s_and_not1_b32 s1, s1, exec_lo
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s1, s1, s0
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s1
s_or_b32 s10, s0, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB1_7
.LBB1_4:
s_or_b32 s1, s1, exec_lo
s_mov_b32 s11, exec_lo
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB1_3
global_load_b64 v[4:5], v[1:2], off
s_waitcnt vmcnt(0)
v_sub_co_u32 v6, vcc_lo, v4, s6
v_subrev_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_sub_co_u32 v8, vcc_lo, s6, v4
v_sub_co_ci_u32_e32 v9, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_u64_e32 vcc_lo, s[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v9, v7
v_cmp_ne_u64_e32 vcc_lo, s[6:7], v[4:5]
v_dual_cndmask_b32 v5, 0, v7 :: v_dual_cndmask_b32 v4, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
v_cmp_gt_u64_e64 s0, s[8:9], v[4:5]
s_or_b32 s12, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s12
s_cbranch_execz .LBB1_2
global_store_b32 v3, v0, s[4:5]
s_branch .LBB1_2
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17scan_for_solutionPliiiPimi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17scan_for_solutionPliiiPimi, .Lfunc_end1-_Z17scan_for_solutionPliiiPimi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8evaluatePiiiiiiPl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8evaluatePiiiiiiPl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17scan_for_solutionPliiiPimi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17scan_for_solutionPliiiPimi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //fonte: https://github.com/carloschilazo/CUDA_GA/blob/master/program.cu
#include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
using namespace std;
/* Cannot use built-in functions, need to rewrite pow function so it can run on the device, kinda reinventing the wheel over here
Im not sure if CUDA has something in its SDK, however better build it myself to avoid any overhead
0^0 even though is not defined, im treating it as 1
*/
__device__ void calculate_exponent(int base,int exponent,long &result){
result = 1L;
if(exponent==0){
return;
}
for(int counter=1;counter<=exponent;counter++){
result *= (long)base;
}
}
__global__ void evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores){
/*global position in population array index calculation */
int startingPosition = (blockIdx.y * threads_per_block * number_genes * individualsPerThread) + (threadIdx.y * number_genes * individualsPerThread);
if(startingPosition>=totalSizeOfArray){
return; //*return if thread is useless, the final block may have some threads that will not compute any data therefore we return early */
}
/*global position in scores array index calculation */
int startingPosition_scores = (blockIdx.y * threads_per_block * individualsPerThread) + (threadIdx.y * individualsPerThread);
long acumulated = 0L;
long temp = 0L;
for(int counter_individuals=0;counter_individuals<individualsPerThread;counter_individuals++){
if(startingPosition + (counter_individuals*number_genes) >= totalSizeOfArray){
return;
}
for(int counter_gene=0;counter_gene<number_genes;counter_gene++){
int base = startingPosition + (counter_individuals*number_genes) + counter_gene;
calculate_exponent(input[base],(number_genes-1)-counter_gene,temp);
acumulated += temp;
}
scores[startingPosition_scores+counter_individuals] = acumulated;
acumulated=0L;
}
}
__device__ void determine_fitness_solution(unsigned long desired_number, unsigned long actual_result, unsigned long &deviation){
if(desired_number>actual_result){
deviation = desired_number - actual_result;
}
if(actual_result>desired_number){
deviation = actual_result - desired_number;
}
if(actual_result==desired_number){
deviation = 0;
}
}
__global__ void scan_for_solution(long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error){
int starting_position_in_scores = (blockIdx.y * threads_per_block * individuals_per_thread) + (threadIdx.y * individuals_per_thread);
if(starting_position_in_scores>=number_individuals){
return; /* Return if useless thread */
}
unsigned long result;
unsigned long deviation;
for(int counter_individuals=0;counter_individuals<individuals_per_thread;counter_individuals++){
if(starting_position_in_scores+counter_individuals>=number_individuals){
return;
}
result = scores_array[starting_position_in_scores+counter_individuals];
determine_fitness_solution(desired_number,result,deviation);
if(deviation==0 || deviation<acceptable_error){
*solution_found_flag = starting_position_in_scores + counter_individuals;
}
}
}
int main(){
/* define settings */
const unsigned int number_genes = 10;
const unsigned int number_individuals = 10000000;
const unsigned int threads_per_block_evaluation = 500; //DO NOT FORGET: BLOCK IS 1 thread width, and threads_per_block height, MAX 512
const unsigned int individuals_per_thread_evaluation = 50;
/* desired algorithm result and acceptable error */
const unsigned long desired_number = 123456;
const unsigned int acceptable_error_window = 1000; /* So result can be +- acceptable_error_window */
/* allocate and randomly initialize memory for population */
int *population_array_host = new int[number_genes*number_individuals];
int *population_array_device;
srand ( time(NULL) );
for(int contador=0;contador<number_genes*number_individuals;contador++){
population_array_host[contador] = ( rand() % 10 );
}
size_t memory_for_population = number_genes*number_individuals*sizeof(int);
hipMalloc((void **) &population_array_device, memory_for_population);
/* allocate and zeroise scores array, avoid any future issues with non initialized arrays */
long *scores_array_host = new long[number_individuals];
long *scores_array_device;
for(int contador=0;contador<number_individuals;contador++){
scores_array_host[contador] = 0L;
}
size_t memory_for_scores = number_individuals*sizeof(long);
hipMalloc((void **) &scores_array_device, memory_for_scores);
/* allocate and initialize memory for acceptable result flag, flag indicates the element of the population which has the result */
int *solution_found_host = new int;
*solution_found_host = -1;
int *solution_found_device;
size_t memory_solution_found = sizeof(int);
hipMalloc((void **) &solution_found_device, memory_solution_found);
/* we move data from host to device*/
hipMemcpy(population_array_device, population_array_host, memory_for_population, hipMemcpyHostToDevice);
hipMemcpy(scores_array_device, scores_array_host, memory_for_scores, hipMemcpyHostToDevice);
hipMemcpy(solution_found_device, solution_found_host, memory_solution_found, hipMemcpyHostToDevice);
/* we calculate dimensions for grid and blocks and create them: for evaluation */
unsigned int blocks_required_evaluation = number_individuals/(threads_per_block_evaluation *individuals_per_thread_evaluation) +
(number_individuals%(threads_per_block_evaluation *individuals_per_thread_evaluation) == 0 ? 0:1);
dim3 grid_evaluation(1,blocks_required_evaluation); /* in terms of blocks */
dim3 block_evaluation(1,threads_per_block_evaluation); /* in terms of threads*/
/* define how many elements per thread, threads and blocks should be launched to scan the score of each individual, we create dim elements accordingly*/
const unsigned int individuals_per_thread_scan_scores = 50;
const unsigned int threads_per_block_scan_scores = 511; // remember block is 1 thread width and threads_per_block_scan_scores height
const unsigned int blocks_required_scan_scores = (number_individuals/ (individuals_per_thread_scan_scores * threads_per_block_scan_scores)) +
(number_individuals%(threads_per_block_scan_scores * individuals_per_thread_scan_scores) == 0 ? 0:1);
dim3 grid_scan_scores(1,blocks_required_scan_scores); // in terms of blocks
dim3 block_scan_scores(1,threads_per_block_scan_scores); // in terms of threads
/* output parameters */
cout << "-Algorithm parameters-" << endl;
cout << "Individuals: " << number_individuals << endl;
cout << "Genes per individual: " << number_genes << endl;
cout << "Individuals computed per thread: " << individuals_per_thread_evaluation << endl;
cout << "-Computing distribution for evaluation-" << endl;
cout << "Blocks required: " << blocks_required_evaluation << endl;
cout << "Threads per block: " << threads_per_block_evaluation << endl;
cout << "Total number of threads: " << blocks_required_evaluation*threads_per_block_evaluation << endl;
cout << "-Computing distribution for scan_results-" << endl;
cout << "Individuals (scores) evaluated per thread: " << individuals_per_thread_scan_scores << endl;
cout << "Threads per block: " << threads_per_block_scan_scores << endl;
cout << "Blocks required: " << blocks_required_scan_scores << endl;
cout << endl << "Algorithm Start" << endl;
/*we launch evaluation kernel: evaluate(int *input, int totalSizeOfArray, int number_genes, int individualsPerThread, int number_blocks, int threads_per_block, long *scores)*/
evaluate <<< grid_evaluation, block_evaluation >>> (population_array_device, number_genes*number_individuals, number_genes, individuals_per_thread_evaluation, blocks_required_evaluation, threads_per_block_evaluation, scores_array_device);
/* long *scores_array, int number_individuals, int individuals_per_thread, int threads_per_block, int *solution_found_flag, unsigned long desired_number, int acceptable_error */
scan_for_solution <<< grid_scan_scores, block_scan_scores >>> (scores_array_device, number_individuals, individuals_per_thread_scan_scores, threads_per_block_scan_scores, solution_found_device, desired_number, acceptable_error_window);
//cudaMemcpy(scores_array_host, scores_array_device, memory_for_scores, cudaMemcpyDeviceToHost);
//cudaMemcpy(population_array_host, population_array_device, memory_for_population, cudaMemcpyDeviceToHost);
hipMemcpy(solution_found_host, solution_found_device, memory_solution_found, hipMemcpyDeviceToHost);
cout << *solution_found_host << endl;
//cout << scores_array_host[*solution_found_host] << endl;
return 0;
} | .text
.file "genetic_algorithm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__evaluatePiiiiiiPl # -- Begin function _Z23__device_stub__evaluatePiiiiiiPl
.p2align 4, 0x90
.type _Z23__device_stub__evaluatePiiiiiiPl,@function
_Z23__device_stub__evaluatePiiiiiiPl: # @_Z23__device_stub__evaluatePiiiiiiPl
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8evaluatePiiiiiiPl, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z23__device_stub__evaluatePiiiiiiPl, .Lfunc_end0-_Z23__device_stub__evaluatePiiiiiiPl
.cfi_endproc
# -- End function
.globl _Z32__device_stub__scan_for_solutionPliiiPimi # -- Begin function _Z32__device_stub__scan_for_solutionPliiiPimi
.p2align 4, 0x90
.type _Z32__device_stub__scan_for_solutionPliiiPimi,@function
_Z32__device_stub__scan_for_solutionPliiiPimi: # @_Z32__device_stub__scan_for_solutionPliiiPimi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17scan_for_solutionPliiiPimi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z32__device_stub__scan_for_solutionPliiiPimi, .Lfunc_end1-_Z32__device_stub__scan_for_solutionPliiiPimi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $176, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000000, %edi # imm = 0x17D78400
callq _Znam
movq %rax, %r14
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
cmpq $100000000, %rbx # imm = 0x5F5E100
jne .LBB2_1
# %bb.2:
leaq 104(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $80000000, %edi # imm = 0x4C4B400
callq _Znam
movq %rax, %r15
movl $80000000, %edx # imm = 0x4C4B400
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 24(%rsp), %rdi
movl $80000000, %esi # imm = 0x4C4B400
callq hipMalloc
movl $4, %edi
callq _Znwm
movq %rax, %rbx
movl $-1, (%rax)
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 104(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $80000000, %edx # imm = 0x4C4B400
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_67
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_5
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB2_6
.LBB2_5:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $10000000, %esi # imm = 0x989680
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%r14)
je .LBB2_9
# %bb.8:
movzbl 67(%r14), %ecx
jmp .LBB2_10
.LBB2_9:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i52
cmpb $0, 56(%r14)
je .LBB2_13
# %bb.12:
movzbl 67(%r14), %ecx
jmp .LBB2_14
.LBB2_13:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit55
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $50, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i57
cmpb $0, 56(%r14)
je .LBB2_17
# %bb.16:
movzbl 67(%r14), %ecx
jmp .LBB2_18
.LBB2_17:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit60
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_67
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
cmpb $0, 56(%r14)
je .LBB2_21
# %bb.20:
movzbl 67(%r14), %eax
jmp .LBB2_22
.LBB2_21:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit65
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $400, %esi # imm = 0x190
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
cmpb $0, 56(%r14)
je .LBB2_25
# %bb.24:
movzbl 67(%r14), %ecx
jmp .LBB2_26
.LBB2_25:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit70
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $500, %esi # imm = 0x1F4
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i72
cmpb $0, 56(%r14)
je .LBB2_29
# %bb.28:
movzbl 67(%r14), %ecx
jmp .LBB2_30
.LBB2_29:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit75
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $200000, %esi # imm = 0x30D40
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i77
cmpb $0, 56(%r14)
je .LBB2_33
# %bb.32:
movzbl 67(%r14), %ecx
jmp .LBB2_34
.LBB2_33:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit80
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $41, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_67
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i82
cmpb $0, 56(%r14)
je .LBB2_37
# %bb.36:
movzbl 67(%r14), %eax
jmp .LBB2_38
.LBB2_37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit85
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $43, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $50, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i87
cmpb $0, 56(%r14)
je .LBB2_41
# %bb.40:
movzbl 67(%r14), %ecx
jmp .LBB2_42
.LBB2_41:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit90
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $511, %esi # imm = 0x1FF
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i92
cmpb $0, 56(%r14)
je .LBB2_45
# %bb.44:
movzbl 67(%r14), %ecx
jmp .LBB2_46
.LBB2_45:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit95
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $392, %esi # imm = 0x188
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i97
cmpb $0, 56(%r14)
je .LBB2_49
# %bb.48:
movzbl 67(%r14), %ecx
jmp .LBB2_50
.LBB2_49:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_50: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit100
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_67
# %bb.51: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i102
cmpb $0, 56(%r14)
je .LBB2_53
# %bb.52:
movzbl 67(%r14), %eax
jmp .LBB2_54
.LBB2_53:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit105
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rax, %r14
movl $.L.str.10, %esi
movl $15, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_67
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i107
cmpb $0, 56(%r15)
je .LBB2_57
# %bb.56:
movzbl 67(%r15), %eax
jmp .LBB2_58
.LBB2_57:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_58: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit110
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $1717986918401, %rdi # imm = 0x19000000001
movabsq $2147483648001, %rdx # imm = 0x1F400000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_60
# %bb.59:
movq 104(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 96(%rsp)
movl $100000000, 32(%rsp) # imm = 0x5F5E100
movl $10, 12(%rsp)
movl $50, 8(%rsp)
movl $400, 4(%rsp) # imm = 0x190
movl $500, (%rsp) # imm = 0x1F4
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8evaluatePiiiiiiPl, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_60:
movabsq $1683627180033, %rdi # imm = 0x18800000001
movabsq $2194728288257, %rdx # imm = 0x1FF00000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_62
# %bb.61:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 96(%rsp)
movl $10000000, 12(%rsp) # imm = 0x989680
movl $50, 8(%rsp)
movl $511, 4(%rsp) # imm = 0x1FF
movq %rcx, 88(%rsp)
movq $123456, 80(%rsp) # imm = 0x1E240
movl $1000, (%rsp) # imm = 0x3E8
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17scan_for_solutionPliiiPimi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_62:
movq 16(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_67
# %bb.63: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i112
cmpb $0, 56(%rbx)
je .LBB2_65
# %bb.64:
movzbl 67(%rbx), %ecx
jmp .LBB2_66
.LBB2_65:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_66: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit115
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_67:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8evaluatePiiiiiiPl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17scan_for_solutionPliiiPimi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8evaluatePiiiiiiPl,@object # @_Z8evaluatePiiiiiiPl
.section .rodata,"a",@progbits
.globl _Z8evaluatePiiiiiiPl
.p2align 3, 0x0
_Z8evaluatePiiiiiiPl:
.quad _Z23__device_stub__evaluatePiiiiiiPl
.size _Z8evaluatePiiiiiiPl, 8
.type _Z17scan_for_solutionPliiiPimi,@object # @_Z17scan_for_solutionPliiiPimi
.globl _Z17scan_for_solutionPliiiPimi
.p2align 3, 0x0
_Z17scan_for_solutionPliiiPimi:
.quad _Z32__device_stub__scan_for_solutionPliiiPimi
.size _Z17scan_for_solutionPliiiPimi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "-Algorithm parameters-"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Individuals: "
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Genes per individual: "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Individuals computed per thread: "
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "-Computing distribution for evaluation-"
.size .L.str.4, 40
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Blocks required: "
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Threads per block: "
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Total number of threads: "
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "-Computing distribution for scan_results-"
.size .L.str.8, 42
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Individuals (scores) evaluated per thread: "
.size .L.str.9, 44
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Algorithm Start"
.size .L.str.10, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8evaluatePiiiiiiPl"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17scan_for_solutionPliiiPimi"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__evaluatePiiiiiiPl
.addrsig_sym _Z32__device_stub__scan_for_solutionPliiiPimi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8evaluatePiiiiiiPl
.addrsig_sym _Z17scan_for_solutionPliiiPimi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000386e1_00000000-6_genetic_algorithm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18calculate_exponentiiRl
.type _Z18calculate_exponentiiRl, @function
_Z18calculate_exponentiiRl:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z18calculate_exponentiiRl, .-_Z18calculate_exponentiiRl
.globl _Z26determine_fitness_solutionmmRm
.type _Z26determine_fitness_solutionmmRm, @function
_Z26determine_fitness_solutionmmRm:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z26determine_fitness_solutionmmRm, .-_Z26determine_fitness_solutionmmRm
.globl _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl
.type _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl, @function
_Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl:
.LFB3696:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 20(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8evaluatePiiiiiiPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl, .-_Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl
.globl _Z8evaluatePiiiiiiPl
.type _Z8evaluatePiiiiiiPl, @function
_Z8evaluatePiiiiiiPl:
.LFB3697:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8evaluatePiiiiiiPl, .-_Z8evaluatePiiiiiiPl
.globl _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi
.type _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi, @function
_Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi:
.LFB3698:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17scan_for_solutionPliiiPimi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi, .-_Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi
.globl _Z17scan_for_solutionPliiiPimi
.type _Z17scan_for_solutionPliiiPimi, @function
_Z17scan_for_solutionPliiiPimi:
.LFB3699:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z17scan_for_solutionPliiiPimi, .-_Z17scan_for_solutionPliiiPimi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "-Algorithm parameters-"
.LC1:
.string "Individuals: "
.LC2:
.string "Genes per individual: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Individuals computed per thread: "
.align 8
.LC4:
.string "-Computing distribution for evaluation-"
.section .rodata.str1.1
.LC5:
.string "Blocks required: "
.LC6:
.string "Threads per block: "
.LC7:
.string "Total number of threads: "
.section .rodata.str1.8
.align 8
.LC8:
.string "-Computing distribution for scan_results-"
.align 8
.LC9:
.string "Individuals (scores) evaluated per thread: "
.section .rodata.str1.1
.LC10:
.string "Algorithm Start"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $400000000, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 400000000(%r12), %rbp
.L24:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $80000000, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 80000000(%rax), %rdx
.L25:
movq $0, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L25
leaq 8(%rsp), %rdi
movl $80000000, %esi
call cudaMalloc@PLT
movl $4, %edi
call _Znwm@PLT
movq %rax, %rbp
movl $-1, (%rax)
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000000, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $400, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $500, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $392, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $511, 64(%rsp)
movl $1, 68(%rsp)
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10000000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $50, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %r12
movq %r12, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $400, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %r13
movq %r13, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $500, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $200000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $50, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $511, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $392, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq 16(%rsp)
.cfi_def_cfa_offset 144
movl $500, %r9d
movl $400, %r8d
movl $50, %ecx
movl $10, %edx
movl $100000000, %esi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z8evaluatePiiiiiiPlPiiiiiiPl
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L26
.L33:
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $1000
.cfi_def_cfa_offset 144
movl $123456, %r9d
movq 32(%rsp), %r8
movl $511, %ecx
movl $50, %edx
movl $10000000, %esi
movq 24(%rsp), %rdi
call _Z44__device_stub__Z17scan_for_solutionPliiiPimiPliiiPimi
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z17scan_for_solutionPliiiPimi"
.section .rodata.str1.1
.LC12:
.string "_Z8evaluatePiiiiiiPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z17scan_for_solutionPliiiPimi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z8evaluatePiiiiiiPl(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "genetic_algorithm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__evaluatePiiiiiiPl # -- Begin function _Z23__device_stub__evaluatePiiiiiiPl
.p2align 4, 0x90
.type _Z23__device_stub__evaluatePiiiiiiPl,@function
_Z23__device_stub__evaluatePiiiiiiPl: # @_Z23__device_stub__evaluatePiiiiiiPl
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8evaluatePiiiiiiPl, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z23__device_stub__evaluatePiiiiiiPl, .Lfunc_end0-_Z23__device_stub__evaluatePiiiiiiPl
.cfi_endproc
# -- End function
.globl _Z32__device_stub__scan_for_solutionPliiiPimi # -- Begin function _Z32__device_stub__scan_for_solutionPliiiPimi
.p2align 4, 0x90
.type _Z32__device_stub__scan_for_solutionPliiiPimi,@function
_Z32__device_stub__scan_for_solutionPliiiPimi: # @_Z32__device_stub__scan_for_solutionPliiiPimi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17scan_for_solutionPliiiPimi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z32__device_stub__scan_for_solutionPliiiPimi, .Lfunc_end1-_Z32__device_stub__scan_for_solutionPliiiPimi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $176, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000000, %edi # imm = 0x17D78400
callq _Znam
movq %rax, %r14
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
cmpq $100000000, %rbx # imm = 0x5F5E100
jne .LBB2_1
# %bb.2:
leaq 104(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $80000000, %edi # imm = 0x4C4B400
callq _Znam
movq %rax, %r15
movl $80000000, %edx # imm = 0x4C4B400
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 24(%rsp), %rdi
movl $80000000, %esi # imm = 0x4C4B400
callq hipMalloc
movl $4, %edi
callq _Znwm
movq %rax, %rbx
movl $-1, (%rax)
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 104(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $80000000, %edx # imm = 0x4C4B400
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_67
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_5
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB2_6
.LBB2_5:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $10000000, %esi # imm = 0x989680
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%r14)
je .LBB2_9
# %bb.8:
movzbl 67(%r14), %ecx
jmp .LBB2_10
.LBB2_9:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i52
cmpb $0, 56(%r14)
je .LBB2_13
# %bb.12:
movzbl 67(%r14), %ecx
jmp .LBB2_14
.LBB2_13:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit55
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $50, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i57
cmpb $0, 56(%r14)
je .LBB2_17
# %bb.16:
movzbl 67(%r14), %ecx
jmp .LBB2_18
.LBB2_17:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit60
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_67
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
cmpb $0, 56(%r14)
je .LBB2_21
# %bb.20:
movzbl 67(%r14), %eax
jmp .LBB2_22
.LBB2_21:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit65
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $400, %esi # imm = 0x190
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
cmpb $0, 56(%r14)
je .LBB2_25
# %bb.24:
movzbl 67(%r14), %ecx
jmp .LBB2_26
.LBB2_25:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit70
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $500, %esi # imm = 0x1F4
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i72
cmpb $0, 56(%r14)
je .LBB2_29
# %bb.28:
movzbl 67(%r14), %ecx
jmp .LBB2_30
.LBB2_29:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit75
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $200000, %esi # imm = 0x30D40
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i77
cmpb $0, 56(%r14)
je .LBB2_33
# %bb.32:
movzbl 67(%r14), %ecx
jmp .LBB2_34
.LBB2_33:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit80
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $41, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_67
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i82
cmpb $0, 56(%r14)
je .LBB2_37
# %bb.36:
movzbl 67(%r14), %eax
jmp .LBB2_38
.LBB2_37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit85
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $43, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $50, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i87
cmpb $0, 56(%r14)
je .LBB2_41
# %bb.40:
movzbl 67(%r14), %ecx
jmp .LBB2_42
.LBB2_41:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit90
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $511, %esi # imm = 0x1FF
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i92
cmpb $0, 56(%r14)
je .LBB2_45
# %bb.44:
movzbl 67(%r14), %ecx
jmp .LBB2_46
.LBB2_45:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit95
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $392, %esi # imm = 0x188
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_67
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i97
cmpb $0, 56(%r14)
je .LBB2_49
# %bb.48:
movzbl 67(%r14), %ecx
jmp .LBB2_50
.LBB2_49:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_50: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit100
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_67
# %bb.51: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i102
cmpb $0, 56(%r14)
je .LBB2_53
# %bb.52:
movzbl 67(%r14), %eax
jmp .LBB2_54
.LBB2_53:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_54: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit105
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rax, %r14
movl $.L.str.10, %esi
movl $15, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_67
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i107
cmpb $0, 56(%r15)
je .LBB2_57
# %bb.56:
movzbl 67(%r15), %eax
jmp .LBB2_58
.LBB2_57:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_58: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit110
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $1717986918401, %rdi # imm = 0x19000000001
movabsq $2147483648001, %rdx # imm = 0x1F400000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_60
# %bb.59:
movq 104(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 96(%rsp)
movl $100000000, 32(%rsp) # imm = 0x5F5E100
movl $10, 12(%rsp)
movl $50, 8(%rsp)
movl $400, 4(%rsp) # imm = 0x190
movl $500, (%rsp) # imm = 0x1F4
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8evaluatePiiiiiiPl, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_60:
movabsq $1683627180033, %rdi # imm = 0x18800000001
movabsq $2194728288257, %rdx # imm = 0x1FF00000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_62
# %bb.61:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 96(%rsp)
movl $10000000, 12(%rsp) # imm = 0x989680
movl $50, 8(%rsp)
movl $511, 4(%rsp) # imm = 0x1FF
movq %rcx, 88(%rsp)
movq $123456, 80(%rsp) # imm = 0x1E240
movl $1000, (%rsp) # imm = 0x3E8
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17scan_for_solutionPliiiPimi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_62:
movq 16(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_67
# %bb.63: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i112
cmpb $0, 56(%rbx)
je .LBB2_65
# %bb.64:
movzbl 67(%rbx), %ecx
jmp .LBB2_66
.LBB2_65:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_66: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit115
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_67:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8evaluatePiiiiiiPl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17scan_for_solutionPliiiPimi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8evaluatePiiiiiiPl,@object # @_Z8evaluatePiiiiiiPl
.section .rodata,"a",@progbits
.globl _Z8evaluatePiiiiiiPl
.p2align 3, 0x0
_Z8evaluatePiiiiiiPl:
.quad _Z23__device_stub__evaluatePiiiiiiPl
.size _Z8evaluatePiiiiiiPl, 8
.type _Z17scan_for_solutionPliiiPimi,@object # @_Z17scan_for_solutionPliiiPimi
.globl _Z17scan_for_solutionPliiiPimi
.p2align 3, 0x0
_Z17scan_for_solutionPliiiPimi:
.quad _Z32__device_stub__scan_for_solutionPliiiPimi
.size _Z17scan_for_solutionPliiiPimi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "-Algorithm parameters-"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Individuals: "
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Genes per individual: "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Individuals computed per thread: "
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "-Computing distribution for evaluation-"
.size .L.str.4, 40
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Blocks required: "
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Threads per block: "
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Total number of threads: "
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "-Computing distribution for scan_results-"
.size .L.str.8, 42
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Individuals (scores) evaluated per thread: "
.size .L.str.9, 44
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Algorithm Start"
.size .L.str.10, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8evaluatePiiiiiiPl"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17scan_for_solutionPliiiPimi"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__evaluatePiiiiiiPl
.addrsig_sym _Z32__device_stub__scan_for_solutionPliiiPimi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8evaluatePiiiiiiPl
.addrsig_sym _Z17scan_for_solutionPliiiPimi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ static void calc_linear_kernel_predict(int objs,int coords,double* x,int objs_train,double* x_train,double* out){
int id=blockDim.x * blockIdx.x + threadIdx.x;
int i=id/objs;
int j=id%objs;
if (i<objs_train){
double r=1.0;
for (int k=0;k<coords;k++){
r += x_train[coords*i+k] * x[coords*j+k];
}
out[id]=r;
}
} | code for sm_80
Function : _Z26calc_linear_kernel_predictiiPdiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R6, c[0x0][0x160] ; /* 0x0000580000067a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R6 ; /* 0x0000000600047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R7, R6, RZ ; /* 0x0000000607057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fca00078e00ff */
/*00f0*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0100*/ IMAD R3, R6, R3, R4 ; /* 0x0000000306037224 */
/* 0x000fca00078e0204 */
/*0110*/ ISETP.GT.U32.AND P2, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f44070 */
/*0120*/ @!P2 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x000000010303a824 */
/* 0x000fe200078e0a06 */
/*0130*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R3, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000037a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f26270 */
/*0180*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fcc0007ffe0ff */
/*0190*/ @!P1 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff029224 */
/* 0x000fe200078e0a02 */
/*01a0*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff02aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01f0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0200*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff157424 */
/* 0x000fe400078e00ff */
/*0210*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f06270 */
/*0220*/ @!P0 BRA 0xd20 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R4, R3.reuse, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x040fe20007ffe0ff */
/*0240*/ IMAD.MOV R5, RZ, RZ, -R2 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a02 */
/*0250*/ LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fe200078ec0ff */
/*0260*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0280*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff157424 */
/* 0x000fe200078e00ff */
/*0290*/ MOV R20, 0x0 ; /* 0x0000000000147802 */
/* 0x000fe20000000f00 */
/*02a0*/ IMAD R5, R5, c[0x0][0x160], R0 ; /* 0x0000580005057a24 */
/* 0x000fd400078e0200 */
/*02b0*/ @!P0 BRA 0xb90 ; /* 0x000008d000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IADD3 R4, -R3, c[0x0][0x164], RZ ; /* 0x0000590003047a10 */
/* 0x000fe20007ffe1ff */
/*02d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*02e0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*02f0*/ IMAD R6, R2, c[0x0][0x164], RZ ; /* 0x0000590002067a24 */
/* 0x000fe200078e02ff */
/*0300*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0310*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0320*/ IMAD R25, R5, c[0x0][0x164], RZ ; /* 0x0000590005197a24 */
/* 0x000fe400078e02ff */
/*0330*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff157424 */
/* 0x000fc400078e00ff */
/*0350*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fca00078e0207 */
/*0360*/ @!P0 BRA 0xa00 ; /* 0x0000069000008947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0380*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0390*/ @!P1 BRA 0x780 ; /* 0x000003e000009947 */
/* 0x000fea0003800000 */
/*03a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03b0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*03c0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x001ea2000c1e1b00 */
/*03d0*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fc6000f8e00ff */
/*03e0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fc600078e0208 */
/*0400*/ LDG.E.64 R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000f28000c1e1b00 */
/*0410*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea8000c1e1b00 */
/*0420*/ LDG.E.64 R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ee8000c1e1b00 */
/*0430*/ LDG.E.64 R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000f22000c1e1b00 */
/*0440*/ DFMA R20, R22, R10, R20 ; /* 0x0000000a1614722b */
/* 0x0060c60000000014 */
/*0450*/ LDG.E.64 R22, [R6.64+0x18] ; /* 0x0000180406167981 */
/* 0x001ea8000c1e1b00 */
/*0460*/ LDG.E.64 R10, [R8.64+0x18] ; /* 0x00001804080a7981 */
/* 0x000ea2000c1e1b00 */
/*0470*/ DFMA R16, R12, R16, R20 ; /* 0x000000100c10722b */
/* 0x0081060000000014 */
/*0480*/ LDG.E.64 R20, [R6.64+0x20] ; /* 0x0000200406147981 */
/* 0x001ee8000c1e1b00 */
/*0490*/ LDG.E.64 R12, [R8.64+0x20] ; /* 0x00002004080c7981 */
/* 0x000ee2000c1e1b00 */
/*04a0*/ DFMA R18, R14, R18, R16 ; /* 0x000000120e12722b */
/* 0x0100860000000010 */
/*04b0*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001f28000c1e1b00 */
/*04c0*/ LDG.E.64 R16, [R8.64+0x28] ; /* 0x0000280408107981 */
/* 0x000f22000c1e1b00 */
/*04d0*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0040c60000000012 */
/*04e0*/ LDG.E.64 R18, [R6.64+0x30] ; /* 0x0000300406127981 */
/* 0x001ea8000c1e1b00 */
/*04f0*/ LDG.E.64 R10, [R8.64+0x30] ; /* 0x00003004080a7981 */
/* 0x000ea2000c1e1b00 */
/*0500*/ DFMA R20, R12, R20, R22 ; /* 0x000000140c14722b */
/* 0x0081060000000016 */
/*0510*/ LDG.E.64 R22, [R6.64+0x38] ; /* 0x0000380406167981 */
/* 0x001ee8000c1e1b00 */
/*0520*/ LDG.E.64 R12, [R8.64+0x38] ; /* 0x00003804080c7981 */
/* 0x000ee2000c1e1b00 */
/*0530*/ DFMA R14, R16, R14, R20 ; /* 0x0000000e100e722b */
/* 0x0100860000000014 */
/*0540*/ LDG.E.64 R20, [R6.64+0x40] ; /* 0x0000400406147981 */
/* 0x001f28000c1e1b00 */
/*0550*/ LDG.E.64 R16, [R8.64+0x40] ; /* 0x0000400408107981 */
/* 0x000f22000c1e1b00 */
/*0560*/ DFMA R18, R10, R18, R14 ; /* 0x000000120a12722b */
/* 0x0040c6000000000e */
/*0570*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x001ea8000c1e1b00 */
/*0580*/ LDG.E.64 R10, [R8.64+0x48] ; /* 0x00004804080a7981 */
/* 0x000ea2000c1e1b00 */
/*0590*/ DFMA R22, R12, R22, R18 ; /* 0x000000160c16722b */
/* 0x0081060000000012 */
/*05a0*/ LDG.E.64 R18, [R6.64+0x50] ; /* 0x0000500406127981 */
/* 0x001ee8000c1e1b00 */
/*05b0*/ LDG.E.64 R12, [R8.64+0x50] ; /* 0x00005004080c7981 */
/* 0x000ee2000c1e1b00 */
/*05c0*/ DFMA R20, R16, R20, R22 ; /* 0x000000141014722b */
/* 0x0100860000000016 */
/*05d0*/ LDG.E.64 R22, [R6.64+0x58] ; /* 0x0000580406167981 */
/* 0x001f28000c1e1b00 */
/*05e0*/ LDG.E.64 R16, [R8.64+0x58] ; /* 0x0000580408107981 */
/* 0x000f22000c1e1b00 */
/*05f0*/ DFMA R14, R10, R14, R20 ; /* 0x0000000e0a0e722b */
/* 0x0040c60000000014 */
/*0600*/ LDG.E.64 R10, [R6.64+0x60] ; /* 0x00006004060a7981 */
/* 0x001ea8000c1e1b00 */
/*0610*/ LDG.E.64 R20, [R8.64+0x60] ; /* 0x0000600408147981 */
/* 0x000ea2000c1e1b00 */
/*0620*/ DFMA R18, R12, R18, R14 ; /* 0x000000120c12722b */
/* 0x008106000000000e */
/*0630*/ LDG.E.64 R12, [R6.64+0x68] ; /* 0x00006804060c7981 */
/* 0x001ee8000c1e1b00 */
/*0640*/ LDG.E.64 R14, [R8.64+0x68] ; /* 0x00006804080e7981 */
/* 0x000ee2000c1e1b00 */
/*0650*/ DFMA R22, R16, R22, R18 ; /* 0x000000161016722b */
/* 0x0100860000000012 */
/*0660*/ LDG.E.64 R16, [R6.64+0x70] ; /* 0x0000700406107981 */
/* 0x001f28000c1e1b00 */
/*0670*/ LDG.E.64 R18, [R8.64+0x70] ; /* 0x0000700408127981 */
/* 0x000f22000c1e1b00 */
/*0680*/ DFMA R10, R20, R10, R22 ; /* 0x0000000a140a722b */
/* 0x0040c60000000016 */
/*0690*/ LDG.E.64 R20, [R6.64+0x78] ; /* 0x0000780406147981 */
/* 0x0010a8000c1e1b00 */
/*06a0*/ LDG.E.64 R22, [R8.64+0x78] ; /* 0x0000780408167981 */
/* 0x000ea2000c1e1b00 */
/*06b0*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ DFMA R10, R14, R12, R10 ; /* 0x0000000c0e0a722b */
/* 0x008306000000000a */
/*06d0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*06e0*/ IADD3 R12, P2, R6, 0x80, RZ ; /* 0x00000080060c7810 */
/* 0x002fe20007f5e0ff */
/*06f0*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0700*/ DFMA R10, R18, R16, R10 ; /* 0x00000010120a722b */
/* 0x010ea4000000000a */
/*0710*/ IADD3.X R13, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe200017fe4ff */
/*0720*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0730*/ IADD3 R24, R24, 0x10, RZ ; /* 0x0000001018187810 */
/* 0x000fe20007ffe0ff */
/*0740*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x001fe400078e000c */
/*0750*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0760*/ DFMA R20, R22, R20, R10 ; /* 0x000000141614722b */
/* 0x004062000000000a */
/*0770*/ @P1 BRA 0x3b0 ; /* 0xfffffc3000001947 */
/* 0x000fea000383ffff */
/*0780*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0790*/ @!P1 BRA 0x9e0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*07a0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*07b0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*07c0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea6000c1e1b00 */
/*07d0*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fe200078e0208 */
/*07e0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*07f0*/ LDG.E.64 R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea8000c1e1b00 */
/*0800*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000804080a7981 */
/* 0x001ee8000c1e1b00 */
/*0810*/ LDG.E.64 R22, [R6.64+0x10] ; /* 0x0000100406167981 */
/* 0x000f28000c1e1b00 */
/*0820*/ LDG.E.64 R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000f22000c1e1b00 */
/*0830*/ DFMA R12, R18, R12, R20 ; /* 0x0000000c120c722b */
/* 0x0060c60000000014 */
/*0840*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x001ea8000c1e1b00 */
/*0850*/ LDG.E.64 R20, [R8.64+0x18] ; /* 0x0000180408147981 */
/* 0x000ea2000c1e1b00 */
/*0860*/ DFMA R16, R10, R16, R12 ; /* 0x000000100a10722b */
/* 0x008106000000000c */
/*0870*/ LDG.E.64 R10, [R6.64+0x20] ; /* 0x00002004060a7981 */
/* 0x001ee8000c1e1b00 */
/*0880*/ LDG.E.64 R12, [R8.64+0x20] ; /* 0x00002004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0890*/ DFMA R22, R14, R22, R16 ; /* 0x000000160e16722b */
/* 0x0100860000000010 */
/*08a0*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001f28000c1e1b00 */
/*08b0*/ LDG.E.64 R16, [R8.64+0x28] ; /* 0x0000280408107981 */
/* 0x000f22000c1e1b00 */
/*08c0*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x0040c60000000016 */
/*08d0*/ LDG.E.64 R20, [R6.64+0x30] ; /* 0x0000300406147981 */
/* 0x001ea8000c1e1b00 */
/*08e0*/ LDG.E.64 R22, [R8.64+0x30] ; /* 0x0000300408167981 */
/* 0x000ea2000c1e1b00 */
/*08f0*/ DFMA R12, R12, R10, R18 ; /* 0x0000000a0c0c722b */
/* 0x0081060000000012 */
/*0900*/ LDG.E.64 R10, [R6.64+0x38] ; /* 0x00003804060a7981 */
/* 0x001ee8000c1e1b00 */
/*0910*/ LDG.E.64 R18, [R8.64+0x38] ; /* 0x0000380408127981 */
/* 0x000ee2000c1e1b00 */
/*0920*/ DFMA R12, R16, R14, R12 ; /* 0x0000000e100c722b */
/* 0x010ea2000000000c */
/*0930*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0940*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0950*/ IADD3 R24, R24, 0x8, RZ ; /* 0x0000000818187810 */
/* 0x000fe40007ffe0ff */
/*0960*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0970*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0980*/ DFMA R20, R22, R20, R12 ; /* 0x000000141614722b */
/* 0x0040c4000000000c */
/*0990*/ IADD3 R12, P1, R6, 0x40, RZ ; /* 0x00000040060c7810 */
/* 0x001fca0007f3e0ff */
/*09a0*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*09b0*/ DFMA R20, R18, R10, R20 ; /* 0x0000000a1214722b */
/* 0x0080620000000014 */
/*09c0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000c */
/*09d0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000d */
/*09e0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x003fda0000705670 */
/*09f0*/ @!P0 BRA 0xb90 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0a00*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0a10*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fe2000f8e00ff */
/*0a20*/ LDG.E.64 R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea6000c1e1b00 */
/*0a30*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fe200078e0208 */
/*0a40*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee8000c1e1b00 */
/*0a50*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea8000c1e1b00 */
/*0a60*/ LDG.E.64 R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ee8000c1e1b00 */
/*0a70*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f28000c1e1b00 */
/*0a80*/ LDG.E.64 R16, [R8.64+0x10] ; /* 0x0000100408107981 */
/* 0x000f22000c1e1b00 */
/*0a90*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0aa0*/ DFMA R18, R22, R18, R20 ; /* 0x000000121612722b */
/* 0x0040c40000000014 */
/*0ab0*/ LDG.E.64 R20, [R6.64+0x18] ; /* 0x0000180406147981 */
/* 0x0010a8000c1e1b00 */
/*0ac0*/ LDG.E.64 R22, [R8.64+0x18] ; /* 0x0000180408167981 */
/* 0x000ea2000c1e1b00 */
/*0ad0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0ae0*/ DFMA R10, R12, R10, R18 ; /* 0x0000000a0c0a722b */
/* 0x0083240000000012 */
/*0af0*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x002fe20007f3e0ff */
/*0b00*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fc6000ff1e03f */
/*0b10*/ DFMA R10, R16, R14, R10 ; /* 0x0000000e100a722b */
/* 0x010ea2000000000a */
/*0b20*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*0b30*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0b40*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0b70*/ DFMA R20, R22, R20, R10 ; /* 0x000000141614722b */
/* 0x004064000000000a */
/*0b80*/ @P0 BRA 0xa00 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b90*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0ba0*/ @!P0 BRA 0xd20 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0bb0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe400078e00ff */
/*0bc0*/ IMAD R5, R5, c[0x0][0x164], R24.reuse ; /* 0x0000590005057a24 */
/* 0x100fe400078e0218 */
/*0bd0*/ IMAD R6, R2, c[0x0][0x164], R24 ; /* 0x0000590002067a24 */
/* 0x000fe400078e0218 */
/*0be0*/ IMAD.WIDE R4, R5, R7, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0207 */
/*0bf0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*0c00*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc60000000f00 */
/*0c10*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0c20*/ MOV R9, R7 ; /* 0x0000000700097202 */
/* 0x000fe20000000f00 */
/*0c30*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0006 */
/*0c40*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0008 */
/*0c50*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe20000000f00 */
/*0c60*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*0c70*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0009 */
/*0c80*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0c90*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0ca0*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0cb0*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007f3e0ff */
/*0cc0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0cd0*/ IADD3 R2, P2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe20007f5e0ff */
/*0ce0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fc600008e060b */
/*0cf0*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200017fe4ff */
/*0d00*/ DFMA R20, R4, R6, R20 ; /* 0x000000060414722b */
/* 0x00604c0000000014 */
/*0d10*/ @P0 BRA 0xc40 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0d20*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0d30*/ IMAD.WIDE R2, R0, R3, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0203 */
/*0d40*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x002fe2000c101b04 */
/*0d50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d60*/ BRA 0xd60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ static void calc_linear_kernel_predict(int objs,int coords,double* x,int objs_train,double* x_train,double* out){
int id=blockDim.x * blockIdx.x + threadIdx.x;
int i=id/objs;
int j=id%objs;
if (i<objs_train){
double r=1.0;
for (int k=0;k<coords;k++){
r += x_train[coords*i+k] * x[coords*j+k];
}
out[id]=r;
}
} | .file "tmpxft_001218cd_00000000-6_calc_linear_kernel_predict.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL26calc_linear_kernel_predictiiPdiS_S_, @function
_ZL26calc_linear_kernel_predictiiPdiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl %edi, 12(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL26calc_linear_kernel_predictiiPdiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL26calc_linear_kernel_predictiiPdiS_S_, .-_ZL26calc_linear_kernel_predictiiPdiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26calc_linear_kernel_predictiiPdiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL26calc_linear_kernel_predictiiPdiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ static void calc_linear_kernel_predict(int objs,int coords,double* x,int objs_train,double* x_train,double* out){
int id=blockDim.x * blockIdx.x + threadIdx.x;
int i=id/objs;
int j=id%objs;
if (i<objs_train){
double r=1.0;
for (int k=0;k<coords;k++){
r += x_train[coords*i+k] * x[coords*j+k];
}
out[id]=r;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void calc_linear_kernel_predict(int objs,int coords,double* x,int objs_train,double* x_train,double* out){
int id=blockDim.x * blockIdx.x + threadIdx.x;
int i=id/objs;
int j=id%objs;
if (i<objs_train){
double r=1.0;
for (int k=0;k<coords;k++){
r += x_train[coords*i+k] * x[coords*j+k];
}
out[id]=r;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void calc_linear_kernel_predict(int objs,int coords,double* x,int objs_train,double* x_train,double* out){
int id=blockDim.x * blockIdx.x + threadIdx.x;
int i=id/objs;
int j=id%objs;
if (i<objs_train){
double r=1.0;
for (int k=0;k<coords;k++){
r += x_train[coords*i+k] * x[coords*j+k];
}
out[id]=r;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL26calc_linear_kernel_predictiiPdiS_S_,"axG",@progbits,_ZL26calc_linear_kernel_predictiiPdiS_S_,comdat
.globl _ZL26calc_linear_kernel_predictiiPdiS_S_
.p2align 8
.type _ZL26calc_linear_kernel_predictiiPdiS_S_,@function
_ZL26calc_linear_kernel_predictiiPdiS_S_:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s3, s5
s_and_b32 s4, s4, 0xffff
s_xor_b32 s6, s6, s5
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s6
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
v_mul_lo_u32 v2, v0, s3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b64 s[6:7], s[0:1], 0x18
v_mul_lo_u32 v5, v0, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v1, v2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s2
v_lshlrev_b64 v[9:10], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[7:8], 3, v[2:3]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0x3ff00000
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
.LBB0_3:
global_load_b64 v[9:10], v[7:8], off
global_load_b64 v[11:12], v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[9:10], v[11:12], v[3:4]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0x3ff00000
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL26calc_linear_kernel_predictiiPdiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL26calc_linear_kernel_predictiiPdiS_S_,"axG",@progbits,_ZL26calc_linear_kernel_predictiiPdiS_S_,comdat
.Lfunc_end0:
.size _ZL26calc_linear_kernel_predictiiPdiS_S_, .Lfunc_end0-_ZL26calc_linear_kernel_predictiiPdiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL26calc_linear_kernel_predictiiPdiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL26calc_linear_kernel_predictiiPdiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void calc_linear_kernel_predict(int objs,int coords,double* x,int objs_train,double* x_train,double* out){
int id=blockDim.x * blockIdx.x + threadIdx.x;
int i=id/objs;
int j=id%objs;
if (i<objs_train){
double r=1.0;
for (int k=0;k<coords;k++){
r += x_train[coords*i+k] * x[coords*j+k];
}
out[id]=r;
}
} | .text
.file "calc_linear_kernel_predict.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26calc_linear_kernel_predictiiPdiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R6, c[0x0][0x160] ; /* 0x0000580000067a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R6 ; /* 0x0000000600047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R7, R6, RZ ; /* 0x0000000607057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fca00078e00ff */
/*00f0*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0100*/ IMAD R3, R6, R3, R4 ; /* 0x0000000306037224 */
/* 0x000fca00078e0204 */
/*0110*/ ISETP.GT.U32.AND P2, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f44070 */
/*0120*/ @!P2 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x000000010303a824 */
/* 0x000fe200078e0a06 */
/*0130*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R3, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000037a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f26270 */
/*0180*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fcc0007ffe0ff */
/*0190*/ @!P1 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff029224 */
/* 0x000fe200078e0a02 */
/*01a0*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff02aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01f0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0200*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff157424 */
/* 0x000fe400078e00ff */
/*0210*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f06270 */
/*0220*/ @!P0 BRA 0xd20 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R4, R3.reuse, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x040fe20007ffe0ff */
/*0240*/ IMAD.MOV R5, RZ, RZ, -R2 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a02 */
/*0250*/ LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fe200078ec0ff */
/*0260*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0280*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff157424 */
/* 0x000fe200078e00ff */
/*0290*/ MOV R20, 0x0 ; /* 0x0000000000147802 */
/* 0x000fe20000000f00 */
/*02a0*/ IMAD R5, R5, c[0x0][0x160], R0 ; /* 0x0000580005057a24 */
/* 0x000fd400078e0200 */
/*02b0*/ @!P0 BRA 0xb90 ; /* 0x000008d000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IADD3 R4, -R3, c[0x0][0x164], RZ ; /* 0x0000590003047a10 */
/* 0x000fe20007ffe1ff */
/*02d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*02e0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*02f0*/ IMAD R6, R2, c[0x0][0x164], RZ ; /* 0x0000590002067a24 */
/* 0x000fe200078e02ff */
/*0300*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0310*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0320*/ IMAD R25, R5, c[0x0][0x164], RZ ; /* 0x0000590005197a24 */
/* 0x000fe400078e02ff */
/*0330*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff157424 */
/* 0x000fc400078e00ff */
/*0350*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fca00078e0207 */
/*0360*/ @!P0 BRA 0xa00 ; /* 0x0000069000008947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0380*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0390*/ @!P1 BRA 0x780 ; /* 0x000003e000009947 */
/* 0x000fea0003800000 */
/*03a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03b0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*03c0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x001ea2000c1e1b00 */
/*03d0*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fc6000f8e00ff */
/*03e0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fc600078e0208 */
/*0400*/ LDG.E.64 R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000f28000c1e1b00 */
/*0410*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea8000c1e1b00 */
/*0420*/ LDG.E.64 R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ee8000c1e1b00 */
/*0430*/ LDG.E.64 R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000f22000c1e1b00 */
/*0440*/ DFMA R20, R22, R10, R20 ; /* 0x0000000a1614722b */
/* 0x0060c60000000014 */
/*0450*/ LDG.E.64 R22, [R6.64+0x18] ; /* 0x0000180406167981 */
/* 0x001ea8000c1e1b00 */
/*0460*/ LDG.E.64 R10, [R8.64+0x18] ; /* 0x00001804080a7981 */
/* 0x000ea2000c1e1b00 */
/*0470*/ DFMA R16, R12, R16, R20 ; /* 0x000000100c10722b */
/* 0x0081060000000014 */
/*0480*/ LDG.E.64 R20, [R6.64+0x20] ; /* 0x0000200406147981 */
/* 0x001ee8000c1e1b00 */
/*0490*/ LDG.E.64 R12, [R8.64+0x20] ; /* 0x00002004080c7981 */
/* 0x000ee2000c1e1b00 */
/*04a0*/ DFMA R18, R14, R18, R16 ; /* 0x000000120e12722b */
/* 0x0100860000000010 */
/*04b0*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001f28000c1e1b00 */
/*04c0*/ LDG.E.64 R16, [R8.64+0x28] ; /* 0x0000280408107981 */
/* 0x000f22000c1e1b00 */
/*04d0*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0040c60000000012 */
/*04e0*/ LDG.E.64 R18, [R6.64+0x30] ; /* 0x0000300406127981 */
/* 0x001ea8000c1e1b00 */
/*04f0*/ LDG.E.64 R10, [R8.64+0x30] ; /* 0x00003004080a7981 */
/* 0x000ea2000c1e1b00 */
/*0500*/ DFMA R20, R12, R20, R22 ; /* 0x000000140c14722b */
/* 0x0081060000000016 */
/*0510*/ LDG.E.64 R22, [R6.64+0x38] ; /* 0x0000380406167981 */
/* 0x001ee8000c1e1b00 */
/*0520*/ LDG.E.64 R12, [R8.64+0x38] ; /* 0x00003804080c7981 */
/* 0x000ee2000c1e1b00 */
/*0530*/ DFMA R14, R16, R14, R20 ; /* 0x0000000e100e722b */
/* 0x0100860000000014 */
/*0540*/ LDG.E.64 R20, [R6.64+0x40] ; /* 0x0000400406147981 */
/* 0x001f28000c1e1b00 */
/*0550*/ LDG.E.64 R16, [R8.64+0x40] ; /* 0x0000400408107981 */
/* 0x000f22000c1e1b00 */
/*0560*/ DFMA R18, R10, R18, R14 ; /* 0x000000120a12722b */
/* 0x0040c6000000000e */
/*0570*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x001ea8000c1e1b00 */
/*0580*/ LDG.E.64 R10, [R8.64+0x48] ; /* 0x00004804080a7981 */
/* 0x000ea2000c1e1b00 */
/*0590*/ DFMA R22, R12, R22, R18 ; /* 0x000000160c16722b */
/* 0x0081060000000012 */
/*05a0*/ LDG.E.64 R18, [R6.64+0x50] ; /* 0x0000500406127981 */
/* 0x001ee8000c1e1b00 */
/*05b0*/ LDG.E.64 R12, [R8.64+0x50] ; /* 0x00005004080c7981 */
/* 0x000ee2000c1e1b00 */
/*05c0*/ DFMA R20, R16, R20, R22 ; /* 0x000000141014722b */
/* 0x0100860000000016 */
/*05d0*/ LDG.E.64 R22, [R6.64+0x58] ; /* 0x0000580406167981 */
/* 0x001f28000c1e1b00 */
/*05e0*/ LDG.E.64 R16, [R8.64+0x58] ; /* 0x0000580408107981 */
/* 0x000f22000c1e1b00 */
/*05f0*/ DFMA R14, R10, R14, R20 ; /* 0x0000000e0a0e722b */
/* 0x0040c60000000014 */
/*0600*/ LDG.E.64 R10, [R6.64+0x60] ; /* 0x00006004060a7981 */
/* 0x001ea8000c1e1b00 */
/*0610*/ LDG.E.64 R20, [R8.64+0x60] ; /* 0x0000600408147981 */
/* 0x000ea2000c1e1b00 */
/*0620*/ DFMA R18, R12, R18, R14 ; /* 0x000000120c12722b */
/* 0x008106000000000e */
/*0630*/ LDG.E.64 R12, [R6.64+0x68] ; /* 0x00006804060c7981 */
/* 0x001ee8000c1e1b00 */
/*0640*/ LDG.E.64 R14, [R8.64+0x68] ; /* 0x00006804080e7981 */
/* 0x000ee2000c1e1b00 */
/*0650*/ DFMA R22, R16, R22, R18 ; /* 0x000000161016722b */
/* 0x0100860000000012 */
/*0660*/ LDG.E.64 R16, [R6.64+0x70] ; /* 0x0000700406107981 */
/* 0x001f28000c1e1b00 */
/*0670*/ LDG.E.64 R18, [R8.64+0x70] ; /* 0x0000700408127981 */
/* 0x000f22000c1e1b00 */
/*0680*/ DFMA R10, R20, R10, R22 ; /* 0x0000000a140a722b */
/* 0x0040c60000000016 */
/*0690*/ LDG.E.64 R20, [R6.64+0x78] ; /* 0x0000780406147981 */
/* 0x0010a8000c1e1b00 */
/*06a0*/ LDG.E.64 R22, [R8.64+0x78] ; /* 0x0000780408167981 */
/* 0x000ea2000c1e1b00 */
/*06b0*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ DFMA R10, R14, R12, R10 ; /* 0x0000000c0e0a722b */
/* 0x008306000000000a */
/*06d0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*06e0*/ IADD3 R12, P2, R6, 0x80, RZ ; /* 0x00000080060c7810 */
/* 0x002fe20007f5e0ff */
/*06f0*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0700*/ DFMA R10, R18, R16, R10 ; /* 0x00000010120a722b */
/* 0x010ea4000000000a */
/*0710*/ IADD3.X R13, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe200017fe4ff */
/*0720*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0730*/ IADD3 R24, R24, 0x10, RZ ; /* 0x0000001018187810 */
/* 0x000fe20007ffe0ff */
/*0740*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x001fe400078e000c */
/*0750*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0760*/ DFMA R20, R22, R20, R10 ; /* 0x000000141614722b */
/* 0x004062000000000a */
/*0770*/ @P1 BRA 0x3b0 ; /* 0xfffffc3000001947 */
/* 0x000fea000383ffff */
/*0780*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0790*/ @!P1 BRA 0x9e0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*07a0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*07b0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*07c0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea6000c1e1b00 */
/*07d0*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fe200078e0208 */
/*07e0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*07f0*/ LDG.E.64 R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea8000c1e1b00 */
/*0800*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000804080a7981 */
/* 0x001ee8000c1e1b00 */
/*0810*/ LDG.E.64 R22, [R6.64+0x10] ; /* 0x0000100406167981 */
/* 0x000f28000c1e1b00 */
/*0820*/ LDG.E.64 R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000f22000c1e1b00 */
/*0830*/ DFMA R12, R18, R12, R20 ; /* 0x0000000c120c722b */
/* 0x0060c60000000014 */
/*0840*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x001ea8000c1e1b00 */
/*0850*/ LDG.E.64 R20, [R8.64+0x18] ; /* 0x0000180408147981 */
/* 0x000ea2000c1e1b00 */
/*0860*/ DFMA R16, R10, R16, R12 ; /* 0x000000100a10722b */
/* 0x008106000000000c */
/*0870*/ LDG.E.64 R10, [R6.64+0x20] ; /* 0x00002004060a7981 */
/* 0x001ee8000c1e1b00 */
/*0880*/ LDG.E.64 R12, [R8.64+0x20] ; /* 0x00002004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0890*/ DFMA R22, R14, R22, R16 ; /* 0x000000160e16722b */
/* 0x0100860000000010 */
/*08a0*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001f28000c1e1b00 */
/*08b0*/ LDG.E.64 R16, [R8.64+0x28] ; /* 0x0000280408107981 */
/* 0x000f22000c1e1b00 */
/*08c0*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x0040c60000000016 */
/*08d0*/ LDG.E.64 R20, [R6.64+0x30] ; /* 0x0000300406147981 */
/* 0x001ea8000c1e1b00 */
/*08e0*/ LDG.E.64 R22, [R8.64+0x30] ; /* 0x0000300408167981 */
/* 0x000ea2000c1e1b00 */
/*08f0*/ DFMA R12, R12, R10, R18 ; /* 0x0000000a0c0c722b */
/* 0x0081060000000012 */
/*0900*/ LDG.E.64 R10, [R6.64+0x38] ; /* 0x00003804060a7981 */
/* 0x001ee8000c1e1b00 */
/*0910*/ LDG.E.64 R18, [R8.64+0x38] ; /* 0x0000380408127981 */
/* 0x000ee2000c1e1b00 */
/*0920*/ DFMA R12, R16, R14, R12 ; /* 0x0000000e100c722b */
/* 0x010ea2000000000c */
/*0930*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0940*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0950*/ IADD3 R24, R24, 0x8, RZ ; /* 0x0000000818187810 */
/* 0x000fe40007ffe0ff */
/*0960*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0970*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0980*/ DFMA R20, R22, R20, R12 ; /* 0x000000141614722b */
/* 0x0040c4000000000c */
/*0990*/ IADD3 R12, P1, R6, 0x40, RZ ; /* 0x00000040060c7810 */
/* 0x001fca0007f3e0ff */
/*09a0*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*09b0*/ DFMA R20, R18, R10, R20 ; /* 0x0000000a1214722b */
/* 0x0080620000000014 */
/*09c0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000c */
/*09d0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000d */
/*09e0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x003fda0000705670 */
/*09f0*/ @!P0 BRA 0xb90 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0a00*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0a10*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fe2000f8e00ff */
/*0a20*/ LDG.E.64 R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea6000c1e1b00 */
/*0a30*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fe200078e0208 */
/*0a40*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee8000c1e1b00 */
/*0a50*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea8000c1e1b00 */
/*0a60*/ LDG.E.64 R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ee8000c1e1b00 */
/*0a70*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f28000c1e1b00 */
/*0a80*/ LDG.E.64 R16, [R8.64+0x10] ; /* 0x0000100408107981 */
/* 0x000f22000c1e1b00 */
/*0a90*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0aa0*/ DFMA R18, R22, R18, R20 ; /* 0x000000121612722b */
/* 0x0040c40000000014 */
/*0ab0*/ LDG.E.64 R20, [R6.64+0x18] ; /* 0x0000180406147981 */
/* 0x0010a8000c1e1b00 */
/*0ac0*/ LDG.E.64 R22, [R8.64+0x18] ; /* 0x0000180408167981 */
/* 0x000ea2000c1e1b00 */
/*0ad0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0ae0*/ DFMA R10, R12, R10, R18 ; /* 0x0000000a0c0a722b */
/* 0x0083240000000012 */
/*0af0*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x002fe20007f3e0ff */
/*0b00*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fc6000ff1e03f */
/*0b10*/ DFMA R10, R16, R14, R10 ; /* 0x0000000e100a722b */
/* 0x010ea2000000000a */
/*0b20*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*0b30*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0b40*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0b70*/ DFMA R20, R22, R20, R10 ; /* 0x000000141614722b */
/* 0x004064000000000a */
/*0b80*/ @P0 BRA 0xa00 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b90*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0ba0*/ @!P0 BRA 0xd20 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0bb0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe400078e00ff */
/*0bc0*/ IMAD R5, R5, c[0x0][0x164], R24.reuse ; /* 0x0000590005057a24 */
/* 0x100fe400078e0218 */
/*0bd0*/ IMAD R6, R2, c[0x0][0x164], R24 ; /* 0x0000590002067a24 */
/* 0x000fe400078e0218 */
/*0be0*/ IMAD.WIDE R4, R5, R7, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0207 */
/*0bf0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*0c00*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc60000000f00 */
/*0c10*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0c20*/ MOV R9, R7 ; /* 0x0000000700097202 */
/* 0x000fe20000000f00 */
/*0c30*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0006 */
/*0c40*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0008 */
/*0c50*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe20000000f00 */
/*0c60*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*0c70*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0009 */
/*0c80*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0c90*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0ca0*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0cb0*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007f3e0ff */
/*0cc0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0cd0*/ IADD3 R2, P2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe20007f5e0ff */
/*0ce0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fc600008e060b */
/*0cf0*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200017fe4ff */
/*0d00*/ DFMA R20, R4, R6, R20 ; /* 0x000000060414722b */
/* 0x00604c0000000014 */
/*0d10*/ @P0 BRA 0xc40 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0d20*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0d30*/ IMAD.WIDE R2, R0, R3, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0203 */
/*0d40*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x002fe2000c101b04 */
/*0d50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d60*/ BRA 0xd60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL26calc_linear_kernel_predictiiPdiS_S_,"axG",@progbits,_ZL26calc_linear_kernel_predictiiPdiS_S_,comdat
.globl _ZL26calc_linear_kernel_predictiiPdiS_S_
.p2align 8
.type _ZL26calc_linear_kernel_predictiiPdiS_S_,@function
_ZL26calc_linear_kernel_predictiiPdiS_S_:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s3, s5
s_and_b32 s4, s4, 0xffff
s_xor_b32 s6, s6, s5
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s6
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
v_mul_lo_u32 v2, v0, s3
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b64 s[6:7], s[0:1], 0x18
v_mul_lo_u32 v5, v0, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v1, v2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s2
v_lshlrev_b64 v[9:10], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[7:8], 3, v[2:3]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0x3ff00000
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
.LBB0_3:
global_load_b64 v[9:10], v[7:8], off
global_load_b64 v[11:12], v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[9:10], v[11:12], v[3:4]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0x3ff00000
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL26calc_linear_kernel_predictiiPdiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL26calc_linear_kernel_predictiiPdiS_S_,"axG",@progbits,_ZL26calc_linear_kernel_predictiiPdiS_S_,comdat
.Lfunc_end0:
.size _ZL26calc_linear_kernel_predictiiPdiS_S_, .Lfunc_end0-_ZL26calc_linear_kernel_predictiiPdiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL26calc_linear_kernel_predictiiPdiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL26calc_linear_kernel_predictiiPdiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001218cd_00000000-6_calc_linear_kernel_predict.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL26calc_linear_kernel_predictiiPdiS_S_, @function
_ZL26calc_linear_kernel_predictiiPdiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl %edi, 12(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL26calc_linear_kernel_predictiiPdiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL26calc_linear_kernel_predictiiPdiS_S_, .-_ZL26calc_linear_kernel_predictiiPdiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26calc_linear_kernel_predictiiPdiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL26calc_linear_kernel_predictiiPdiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calc_linear_kernel_predict.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
/**
* CPU version of our CUDA Hello World!
*/
void cpu_helloworld()
{
printf("Hello from the CPU!\n");
}
/**
* GPU version of our CUDA Hello World!
*/
__global__ void gpu_helloworld()
{
int threadId = threadIdx.x;
printf("Hello from the GPU! My threadId is %d\n", threadId);
}
int main(int argc, char **argv)
{
dim3 grid(1); // 1 block in the grid
dim3 block(32); // 32 threads per block
// Call the CPU version
cpu_helloworld();
// Call the GPU version
gpu_helloworld<<<grid, block>>>();
////////////////
// TO-DO #1.2 ////////////////////
// Introduce your changes here! //
// synchronize the threads
cudaDeviceSynchronize();
//////////////////////////////////
return 0;
} | code for sm_80
Function : _Z14gpu_helloworldv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
/**
* CPU version of our CUDA Hello World!
*/
void cpu_helloworld()
{
printf("Hello from the CPU!\n");
}
/**
* GPU version of our CUDA Hello World!
*/
__global__ void gpu_helloworld()
{
int threadId = threadIdx.x;
printf("Hello from the GPU! My threadId is %d\n", threadId);
}
int main(int argc, char **argv)
{
dim3 grid(1); // 1 block in the grid
dim3 block(32); // 32 threads per block
// Call the CPU version
cpu_helloworld();
// Call the GPU version
gpu_helloworld<<<grid, block>>>();
////////////////
// TO-DO #1.2 ////////////////////
// Introduce your changes here! //
// synchronize the threads
cudaDeviceSynchronize();
//////////////////////////////////
return 0;
} | .file "tmpxft_00168ea2_00000000-6_lab01_ex1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello from the CPU!\n"
.text
.globl _Z14cpu_helloworldv
.type _Z14cpu_helloworldv, @function
_Z14cpu_helloworldv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z14cpu_helloworldv, .-_Z14cpu_helloworldv
.globl _Z33__device_stub__Z14gpu_helloworldvv
.type _Z33__device_stub__Z14gpu_helloworldvv, @function
_Z33__device_stub__Z14gpu_helloworldvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14gpu_helloworldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z14gpu_helloworldvv, .-_Z33__device_stub__Z14gpu_helloworldvv
.globl _Z14gpu_helloworldv
.type _Z14gpu_helloworldv, @function
_Z14gpu_helloworldv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14gpu_helloworldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14gpu_helloworldv, .-_Z14gpu_helloworldv
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call _Z14cpu_helloworldv
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _Z33__device_stub__Z14gpu_helloworldvv
jmp .L14
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14gpu_helloworldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14gpu_helloworldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
/**
* CPU version of our CUDA Hello World!
*/
void cpu_helloworld()
{
printf("Hello from the CPU!\n");
}
/**
* GPU version of our CUDA Hello World!
*/
__global__ void gpu_helloworld()
{
int threadId = threadIdx.x;
printf("Hello from the GPU! My threadId is %d\n", threadId);
}
int main(int argc, char **argv)
{
dim3 grid(1); // 1 block in the grid
dim3 block(32); // 32 threads per block
// Call the CPU version
cpu_helloworld();
// Call the GPU version
gpu_helloworld<<<grid, block>>>();
////////////////
// TO-DO #1.2 ////////////////////
// Introduce your changes here! //
// synchronize the threads
cudaDeviceSynchronize();
//////////////////////////////////
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
/**
* CPU version of our CUDA Hello World!
*/
void cpu_helloworld()
{
printf("Hello from the CPU!\n");
}
/**
* GPU version of our CUDA Hello World!
*/
__global__ void gpu_helloworld()
{
int threadId = threadIdx.x;
printf("Hello from the GPU! My threadId is %d\n", threadId);
}
int main(int argc, char **argv)
{
dim3 grid(1); // 1 block in the grid
dim3 block(32); // 32 threads per block
// Call the CPU version
cpu_helloworld();
// Call the GPU version
gpu_helloworld<<<grid, block>>>();
////////////////
// TO-DO #1.2 ////////////////////
// Introduce your changes here! //
// synchronize the threads
hipDeviceSynchronize();
//////////////////////////////////
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
/**
* CPU version of our CUDA Hello World!
*/
void cpu_helloworld()
{
printf("Hello from the CPU!\n");
}
/**
* GPU version of our CUDA Hello World!
*/
__global__ void gpu_helloworld()
{
int threadId = threadIdx.x;
printf("Hello from the GPU! My threadId is %d\n", threadId);
}
int main(int argc, char **argv)
{
dim3 grid(1); // 1 block in the grid
dim3 block(32); // 32 threads per block
// Call the CPU version
cpu_helloworld();
// Call the GPU version
gpu_helloworld<<<grid, block>>>();
////////////////
// TO-DO #1.2 ////////////////////
// Introduce your changes here! //
// synchronize the threads
hipDeviceSynchronize();
//////////////////////////////////
return 0;
} | .text
.file "lab01_ex1.hip"
.globl _Z14cpu_helloworldv # -- Begin function _Z14cpu_helloworldv
.p2align 4, 0x90
.type _Z14cpu_helloworldv,@function
_Z14cpu_helloworldv: # @_Z14cpu_helloworldv
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z14cpu_helloworldv, .Lfunc_end0-_Z14cpu_helloworldv
.cfi_endproc
# -- End function
.globl _Z29__device_stub__gpu_helloworldv # -- Begin function _Z29__device_stub__gpu_helloworldv
.p2align 4, 0x90
.type _Z29__device_stub__gpu_helloworldv,@function
_Z29__device_stub__gpu_helloworldv: # @_Z29__device_stub__gpu_helloworldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14gpu_helloworldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z29__device_stub__gpu_helloworldv, .Lfunc_end1-_Z29__device_stub__gpu_helloworldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14gpu_helloworldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14gpu_helloworldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14gpu_helloworldv,@object # @_Z14gpu_helloworldv
.section .rodata,"a",@progbits
.globl _Z14gpu_helloworldv
.p2align 3, 0x0
_Z14gpu_helloworldv:
.quad _Z29__device_stub__gpu_helloworldv
.size _Z14gpu_helloworldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14gpu_helloworldv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello from the CPU!"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__gpu_helloworldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14gpu_helloworldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00168ea2_00000000-6_lab01_ex1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello from the CPU!\n"
.text
.globl _Z14cpu_helloworldv
.type _Z14cpu_helloworldv, @function
_Z14cpu_helloworldv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z14cpu_helloworldv, .-_Z14cpu_helloworldv
.globl _Z33__device_stub__Z14gpu_helloworldvv
.type _Z33__device_stub__Z14gpu_helloworldvv, @function
_Z33__device_stub__Z14gpu_helloworldvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14gpu_helloworldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z14gpu_helloworldvv, .-_Z33__device_stub__Z14gpu_helloworldvv
.globl _Z14gpu_helloworldv
.type _Z14gpu_helloworldv, @function
_Z14gpu_helloworldv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14gpu_helloworldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14gpu_helloworldv, .-_Z14gpu_helloworldv
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call _Z14cpu_helloworldv
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _Z33__device_stub__Z14gpu_helloworldvv
jmp .L14
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14gpu_helloworldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14gpu_helloworldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab01_ex1.hip"
.globl _Z14cpu_helloworldv # -- Begin function _Z14cpu_helloworldv
.p2align 4, 0x90
.type _Z14cpu_helloworldv,@function
_Z14cpu_helloworldv: # @_Z14cpu_helloworldv
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z14cpu_helloworldv, .Lfunc_end0-_Z14cpu_helloworldv
.cfi_endproc
# -- End function
.globl _Z29__device_stub__gpu_helloworldv # -- Begin function _Z29__device_stub__gpu_helloworldv
.p2align 4, 0x90
.type _Z29__device_stub__gpu_helloworldv,@function
_Z29__device_stub__gpu_helloworldv: # @_Z29__device_stub__gpu_helloworldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14gpu_helloworldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z29__device_stub__gpu_helloworldv, .Lfunc_end1-_Z29__device_stub__gpu_helloworldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14gpu_helloworldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14gpu_helloworldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14gpu_helloworldv,@object # @_Z14gpu_helloworldv
.section .rodata,"a",@progbits
.globl _Z14gpu_helloworldv
.p2align 3, 0x0
_Z14gpu_helloworldv:
.quad _Z29__device_stub__gpu_helloworldv
.size _Z14gpu_helloworldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14gpu_helloworldv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello from the CPU!"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__gpu_helloworldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14gpu_helloworldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <iostream>
void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
// remember to edit these two parameters each time you change the block size
gridDim.x = n / (blockDim.x * 2);
gridDim.y = n / (blockDim.y * 2);
if(n % (blockDim.x*2) != 0)
gridDim.x++;
if(n % (blockDim.y*2) != 0)
gridDim.y++;
cudaSharedMemConfig shmPreference = cudaSharedMemBankSizeEightByte;
cudaDeviceSetSharedMemConfig(shmPreference);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <iostream>
void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
// remember to edit these two parameters each time you change the block size
gridDim.x = n / (blockDim.x * 2);
gridDim.y = n / (blockDim.y * 2);
if(n % (blockDim.x*2) != 0)
gridDim.x++;
if(n % (blockDim.y*2) != 0)
gridDim.y++;
cudaSharedMemConfig shmPreference = cudaSharedMemBankSizeEightByte;
cudaDeviceSetSharedMemConfig(shmPreference);
} | .file "tmpxft_0013c253_00000000-6_setGrid.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7setGridiR4dim3S0_
.type _Z7setGridiR4dim3S0_, @function
_Z7setGridiR4dim3S0_:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %r10
movq %rdx, %rsi
movl %edi, %ecx
movl (%r10), %eax
leal (%rax,%rax), %edi
movl %ecx, %eax
movl $0, %edx
divl %edi
movl %eax, %r8d
movl %eax, (%rsi)
movl 4(%r10), %eax
leal (%rax,%rax), %edi
movl %ecx, %eax
movl $0, %edx
divl %edi
movl %eax, %edi
movl %eax, 4(%rsi)
movl (%r10), %eax
leal (%rax,%rax), %r9d
movl %ecx, %eax
movl $0, %edx
divl %r9d
cmpl $1, %edx
sbbl $-1, %r8d
movl %r8d, (%rsi)
movl 4(%r10), %r8d
addl %r8d, %r8d
movl %ecx, %eax
movl $0, %edx
divl %r8d
cmpl $1, %edx
sbbl $-1, %edi
movl %edi, 4(%rsi)
movl $2, %edi
call cudaDeviceSetSharedMemConfig@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z7setGridiR4dim3S0_, .-_Z7setGridiR4dim3S0_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <iostream>
void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
// remember to edit these two parameters each time you change the block size
gridDim.x = n / (blockDim.x * 2);
gridDim.y = n / (blockDim.y * 2);
if(n % (blockDim.x*2) != 0)
gridDim.x++;
if(n % (blockDim.y*2) != 0)
gridDim.y++;
cudaSharedMemConfig shmPreference = cudaSharedMemBankSizeEightByte;
cudaDeviceSetSharedMemConfig(shmPreference);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <iostream>
void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
// remember to edit these two parameters each time you change the block size
gridDim.x = n / (blockDim.x * 2);
gridDim.y = n / (blockDim.y * 2);
if(n % (blockDim.x*2) != 0)
gridDim.x++;
if(n % (blockDim.y*2) != 0)
gridDim.y++;
hipSharedMemConfig shmPreference = hipSharedMemBankSizeEightByte;
hipDeviceSetSharedMemConfig(shmPreference);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <iostream>
void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
// remember to edit these two parameters each time you change the block size
gridDim.x = n / (blockDim.x * 2);
gridDim.y = n / (blockDim.y * 2);
if(n % (blockDim.x*2) != 0)
gridDim.x++;
if(n % (blockDim.y*2) != 0)
gridDim.y++;
hipSharedMemConfig shmPreference = hipSharedMemBankSizeEightByte;
hipDeviceSetSharedMemConfig(shmPreference);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <iostream>
void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
// remember to edit these two parameters each time you change the block size
gridDim.x = n / (blockDim.x * 2);
gridDim.y = n / (blockDim.y * 2);
if(n % (blockDim.x*2) != 0)
gridDim.x++;
if(n % (blockDim.y*2) != 0)
gridDim.y++;
hipSharedMemConfig shmPreference = hipSharedMemBankSizeEightByte;
hipDeviceSetSharedMemConfig(shmPreference);
} | .text
.file "setGrid.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7setGridiR4dim3S0_ # -- Begin function _Z7setGridiR4dim3S0_
.p2align 4, 0x90
.type _Z7setGridiR4dim3S0_,@function
_Z7setGridiR4dim3S0_: # @_Z7setGridiR4dim3S0_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movl (%rsi), %r8d
addl %r8d, %r8d
movl %edi, %eax
xorl %edx, %edx
divl %r8d
movl %eax, %r9d
movl %eax, (%rcx)
movl 4(%rsi), %r8d
addl %r8d, %r8d
movl %edi, %eax
xorl %edx, %edx
divl %r8d
movl %eax, %r8d
movl %eax, 4(%rcx)
movl (%rsi), %r10d
addl %r10d, %r10d
movl %edi, %eax
xorl %edx, %edx
divl %r10d
testl %edx, %edx
je .LBB0_2
# %bb.1:
incl %r9d
movl %r9d, (%rcx)
.LBB0_2:
movl 4(%rsi), %esi
addl %esi, %esi
movl %edi, %eax
xorl %edx, %edx
divl %esi
testl %edx, %edx
je .LBB0_4
# %bb.3:
incl %r8d
movl %r8d, 4(%rcx)
.LBB0_4:
movl $2, %edi
jmp hipDeviceSetSharedMemConfig # TAILCALL
.Lfunc_end0:
.size _Z7setGridiR4dim3S0_, .Lfunc_end0-_Z7setGridiR4dim3S0_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013c253_00000000-6_setGrid.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7setGridiR4dim3S0_
.type _Z7setGridiR4dim3S0_, @function
_Z7setGridiR4dim3S0_:
.LFB3669:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %r10
movq %rdx, %rsi
movl %edi, %ecx
movl (%r10), %eax
leal (%rax,%rax), %edi
movl %ecx, %eax
movl $0, %edx
divl %edi
movl %eax, %r8d
movl %eax, (%rsi)
movl 4(%r10), %eax
leal (%rax,%rax), %edi
movl %ecx, %eax
movl $0, %edx
divl %edi
movl %eax, %edi
movl %eax, 4(%rsi)
movl (%r10), %eax
leal (%rax,%rax), %r9d
movl %ecx, %eax
movl $0, %edx
divl %r9d
cmpl $1, %edx
sbbl $-1, %r8d
movl %r8d, (%rsi)
movl 4(%r10), %r8d
addl %r8d, %r8d
movl %ecx, %eax
movl $0, %edx
divl %r8d
cmpl $1, %edx
sbbl $-1, %edi
movl %edi, 4(%rsi)
movl $2, %edi
call cudaDeviceSetSharedMemConfig@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z7setGridiR4dim3S0_, .-_Z7setGridiR4dim3S0_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "setGrid.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7setGridiR4dim3S0_ # -- Begin function _Z7setGridiR4dim3S0_
.p2align 4, 0x90
.type _Z7setGridiR4dim3S0_,@function
_Z7setGridiR4dim3S0_: # @_Z7setGridiR4dim3S0_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movl (%rsi), %r8d
addl %r8d, %r8d
movl %edi, %eax
xorl %edx, %edx
divl %r8d
movl %eax, %r9d
movl %eax, (%rcx)
movl 4(%rsi), %r8d
addl %r8d, %r8d
movl %edi, %eax
xorl %edx, %edx
divl %r8d
movl %eax, %r8d
movl %eax, 4(%rcx)
movl (%rsi), %r10d
addl %r10d, %r10d
movl %edi, %eax
xorl %edx, %edx
divl %r10d
testl %edx, %edx
je .LBB0_2
# %bb.1:
incl %r9d
movl %r9d, (%rcx)
.LBB0_2:
movl 4(%rsi), %esi
addl %esi, %esi
movl %edi, %eax
xorl %edx, %edx
divl %esi
testl %edx, %edx
je .LBB0_4
# %bb.3:
incl %r8d
movl %r8d, 4(%rcx)
.LBB0_4:
movl $2, %edi
jmp hipDeviceSetSharedMemConfig # TAILCALL
.Lfunc_end0:
.size _Z7setGridiR4dim3S0_, .Lfunc_end0-_Z7setGridiR4dim3S0_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void scatter_kernel(int *x_coors, int *y_coors, float *pfe_output, float *scattered_feature, const int max_num_pillars_, const int grid_x_size, const int grid_y_size) {
int i_pillar = blockIdx.x;
int i_feature = threadIdx.x;
int x_ind = x_coors[i_pillar];
int y_ind = y_coors[i_pillar];
float feature = pfe_output[i_feature * max_num_pillars_ + i_pillar];
scattered_feature[i_feature * grid_y_size * grid_x_size +
y_ind * grid_x_size + x_ind] = feature;
} | code for sm_80
Function : _Z14scatter_kernelPiS_PfS0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e6e0000002100 */
/*0050*/ IMAD.WIDE R4, R6, R11, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x001fc800078e020b */
/*0060*/ IMAD.WIDE R2, R6, R11.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x080fe400078e020b */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R6, R9, c[0x0][0x180], R6 ; /* 0x0000600009067a24 */
/* 0x002fe400078e0206 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee4000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e020b */
/*00b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f22000c1e1900 */
/*00c0*/ IMAD R9, R9, c[0x0][0x188], R4 ; /* 0x0000620009097a24 */
/* 0x004fc800078e0204 */
/*00d0*/ IMAD R9, R9, c[0x0][0x184], R2 ; /* 0x0000610009097a24 */
/* 0x008fc800078e0202 */
/*00e0*/ IMAD.WIDE R8, R9, R11, c[0x0][0x178] ; /* 0x00005e0009087625 */
/* 0x000fca00078e020b */
/*00f0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x010fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void scatter_kernel(int *x_coors, int *y_coors, float *pfe_output, float *scattered_feature, const int max_num_pillars_, const int grid_x_size, const int grid_y_size) {
int i_pillar = blockIdx.x;
int i_feature = threadIdx.x;
int x_ind = x_coors[i_pillar];
int y_ind = y_coors[i_pillar];
float feature = pfe_output[i_feature * max_num_pillars_ + i_pillar];
scattered_feature[i_feature * grid_y_size * grid_x_size +
y_ind * grid_x_size + x_ind] = feature;
} | .file "tmpxft_0003b386_00000000-6_scatter_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii
.type _Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii, @function
_Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14scatter_kernelPiS_PfS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii, .-_Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii
.globl _Z14scatter_kernelPiS_PfS0_iii
.type _Z14scatter_kernelPiS_PfS0_iii, @function
_Z14scatter_kernelPiS_PfS0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14scatter_kernelPiS_PfS0_iii, .-_Z14scatter_kernelPiS_PfS0_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14scatter_kernelPiS_PfS0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14scatter_kernelPiS_PfS0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void scatter_kernel(int *x_coors, int *y_coors, float *pfe_output, float *scattered_feature, const int max_num_pillars_, const int grid_x_size, const int grid_y_size) {
int i_pillar = blockIdx.x;
int i_feature = threadIdx.x;
int x_ind = x_coors[i_pillar];
int y_ind = y_coors[i_pillar];
float feature = pfe_output[i_feature * max_num_pillars_ + i_pillar];
scattered_feature[i_feature * grid_y_size * grid_x_size +
y_ind * grid_x_size + x_ind] = feature;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scatter_kernel(int *x_coors, int *y_coors, float *pfe_output, float *scattered_feature, const int max_num_pillars_, const int grid_x_size, const int grid_y_size) {
int i_pillar = blockIdx.x;
int i_feature = threadIdx.x;
int x_ind = x_coors[i_pillar];
int y_ind = y_coors[i_pillar];
float feature = pfe_output[i_feature * max_num_pillars_ + i_pillar];
scattered_feature[i_feature * grid_y_size * grid_x_size +
y_ind * grid_x_size + x_ind] = feature;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scatter_kernel(int *x_coors, int *y_coors, float *pfe_output, float *scattered_feature, const int max_num_pillars_, const int grid_x_size, const int grid_y_size) {
int i_pillar = blockIdx.x;
int i_feature = threadIdx.x;
int x_ind = x_coors[i_pillar];
int y_ind = y_coors[i_pillar];
float feature = pfe_output[i_feature * max_num_pillars_ + i_pillar];
scattered_feature[i_feature * grid_y_size * grid_x_size +
y_ind * grid_x_size + x_ind] = feature;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14scatter_kernelPiS_PfS0_iii
.globl _Z14scatter_kernelPiS_PfS0_iii
.p2align 8
.type _Z14scatter_kernelPiS_PfS0_iii,@function
_Z14scatter_kernelPiS_PfS0_iii:
s_clause 0x2
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s14, s[0:1], 0x28
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s12, s[2:3]
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v4, v[1:2], off
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s14, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s13, s[2:3]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14scatter_kernelPiS_PfS0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14scatter_kernelPiS_PfS0_iii, .Lfunc_end0-_Z14scatter_kernelPiS_PfS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14scatter_kernelPiS_PfS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14scatter_kernelPiS_PfS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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