system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scatter_kernel(int *x_coors, int *y_coors, float *pfe_output, float *scattered_feature, const int max_num_pillars_, const int grid_x_size, const int grid_y_size) {
int i_pillar = blockIdx.x;
int i_feature = threadIdx.x;
int x_ind = x_coors[i_pillar];
int y_ind = y_coors[i_pillar];
float feature = pfe_output[i_feature * max_num_pillars_ + i_pillar];
scattered_feature[i_feature * grid_y_size * grid_x_size +
y_ind * grid_x_size + x_ind] = feature;
} | .text
.file "scatter_kernel.hip"
.globl _Z29__device_stub__scatter_kernelPiS_PfS0_iii # -- Begin function _Z29__device_stub__scatter_kernelPiS_PfS0_iii
.p2align 4, 0x90
.type _Z29__device_stub__scatter_kernelPiS_PfS0_iii,@function
_Z29__device_stub__scatter_kernelPiS_PfS0_iii: # @_Z29__device_stub__scatter_kernelPiS_PfS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14scatter_kernelPiS_PfS0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__scatter_kernelPiS_PfS0_iii, .Lfunc_end0-_Z29__device_stub__scatter_kernelPiS_PfS0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14scatter_kernelPiS_PfS0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14scatter_kernelPiS_PfS0_iii,@object # @_Z14scatter_kernelPiS_PfS0_iii
.section .rodata,"a",@progbits
.globl _Z14scatter_kernelPiS_PfS0_iii
.p2align 3, 0x0
_Z14scatter_kernelPiS_PfS0_iii:
.quad _Z29__device_stub__scatter_kernelPiS_PfS0_iii
.size _Z14scatter_kernelPiS_PfS0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14scatter_kernelPiS_PfS0_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__scatter_kernelPiS_PfS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14scatter_kernelPiS_PfS0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14scatter_kernelPiS_PfS0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e6e0000002100 */
/*0050*/ IMAD.WIDE R4, R6, R11, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x001fc800078e020b */
/*0060*/ IMAD.WIDE R2, R6, R11.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x080fe400078e020b */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R6, R9, c[0x0][0x180], R6 ; /* 0x0000600009067a24 */
/* 0x002fe400078e0206 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee4000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e020b */
/*00b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f22000c1e1900 */
/*00c0*/ IMAD R9, R9, c[0x0][0x188], R4 ; /* 0x0000620009097a24 */
/* 0x004fc800078e0204 */
/*00d0*/ IMAD R9, R9, c[0x0][0x184], R2 ; /* 0x0000610009097a24 */
/* 0x008fc800078e0202 */
/*00e0*/ IMAD.WIDE R8, R9, R11, c[0x0][0x178] ; /* 0x00005e0009087625 */
/* 0x000fca00078e020b */
/*00f0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x010fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14scatter_kernelPiS_PfS0_iii
.globl _Z14scatter_kernelPiS_PfS0_iii
.p2align 8
.type _Z14scatter_kernelPiS_PfS0_iii,@function
_Z14scatter_kernelPiS_PfS0_iii:
s_clause 0x2
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s14, s[0:1], 0x28
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s12, s[2:3]
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v4, v[1:2], off
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s14, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s13, s[2:3]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14scatter_kernelPiS_PfS0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14scatter_kernelPiS_PfS0_iii, .Lfunc_end0-_Z14scatter_kernelPiS_PfS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14scatter_kernelPiS_PfS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14scatter_kernelPiS_PfS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003b386_00000000-6_scatter_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii
.type _Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii, @function
_Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14scatter_kernelPiS_PfS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii, .-_Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii
.globl _Z14scatter_kernelPiS_PfS0_iii
.type _Z14scatter_kernelPiS_PfS0_iii, @function
_Z14scatter_kernelPiS_PfS0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z14scatter_kernelPiS_PfS0_iiiPiS_PfS0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14scatter_kernelPiS_PfS0_iii, .-_Z14scatter_kernelPiS_PfS0_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14scatter_kernelPiS_PfS0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14scatter_kernelPiS_PfS0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scatter_kernel.hip"
.globl _Z29__device_stub__scatter_kernelPiS_PfS0_iii # -- Begin function _Z29__device_stub__scatter_kernelPiS_PfS0_iii
.p2align 4, 0x90
.type _Z29__device_stub__scatter_kernelPiS_PfS0_iii,@function
_Z29__device_stub__scatter_kernelPiS_PfS0_iii: # @_Z29__device_stub__scatter_kernelPiS_PfS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14scatter_kernelPiS_PfS0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__scatter_kernelPiS_PfS0_iii, .Lfunc_end0-_Z29__device_stub__scatter_kernelPiS_PfS0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14scatter_kernelPiS_PfS0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14scatter_kernelPiS_PfS0_iii,@object # @_Z14scatter_kernelPiS_PfS0_iii
.section .rodata,"a",@progbits
.globl _Z14scatter_kernelPiS_PfS0_iii
.p2align 3, 0x0
_Z14scatter_kernelPiS_PfS0_iii:
.quad _Z29__device_stub__scatter_kernelPiS_PfS0_iii
.size _Z14scatter_kernelPiS_PfS0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14scatter_kernelPiS_PfS0_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__scatter_kernelPiS_PfS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14scatter_kernelPiS_PfS0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void blend_kernel( float *A, float *BP, float *M, float *AP, float alpha, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
// int x = id % w, y = id / w;
float weight = M[id] < 0.05f ? 0.f : alpha;
AP[dc * size + id] =
A[dc * size + id] * weight +
BP[dc * size + id] * (1.f - weight);
}
return ;
} | code for sm_80
Function : _Z12blend_kernelPfS_S_S_fiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x18c] ; /* 0x0000630000047a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R4, c[0x0][0x188], RZ ; /* 0x0000620004047a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0060*/ IMAD R3, R4, c[0x0][0x184], RZ ; /* 0x0000610004037a24 */
/* 0x000fca00078e02ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IABS R6, R4.reuse ; /* 0x0000000400067213 */
/* 0x080fe20000000000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IABS R9, R4 ; /* 0x0000000400097213 */
/* 0x000fe40000000000 */
/*00c0*/ I2F.RP R5, R6 ; /* 0x0000000600057306 */
/* 0x000e220000209400 */
/*00d0*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*00e0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f46270 */
/*00f0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fe40007ffe0ff */
/*0110*/ IADD3 R5, RZ, -R9, RZ ; /* 0x80000009ff057210 */
/* 0x000fe20007ffe0ff */
/*0120*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fc600000001ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0160*/ IMAD R7, R7, R6, RZ ; /* 0x0000000607077224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0180*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD R3, R3, R5, R8 ; /* 0x0000000503037224 */
/* 0x000fca00078e0208 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f04070 */
/*01b0*/ @!P0 IADD3 R3, R3, -R6, RZ ; /* 0x8000000603038210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*01e0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fca00078e0a06 */
/*01f0*/ @!P2 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff0303a210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R3, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff038212 */
/* 0x000fca00078e33ff */
/*0210*/ IMAD.WIDE R2, R3, R9, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fcc00078e0209 */
/*0220*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R6, R0, R9, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0209 */
/*0240*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe400078e0209 */
/*0250*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000f22000c1e1900 */
/*0270*/ FSETP.GEU.AND P0, PT, R2, 0.050000000745058059692, PT ; /* 0x3d4ccccd0200780b */
/* 0x004fc80003f0e000 */
/*0280*/ FSEL R10, RZ, c[0x0][0x180], !P0 ; /* 0x00006000ff0a7a08 */
/* 0x000fca0004000000 */
/*0290*/ FADD R8, -R10, 1 ; /* 0x3f8000000a087421 */
/* 0x000fc80000000100 */
/*02a0*/ FMUL R11, R8, R7 ; /* 0x00000007080b7220 */
/* 0x008fe40000400000 */
/*02b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e0209 */
/*02c0*/ FFMA R11, R10, R5, R11 ; /* 0x000000050a0b7223 */
/* 0x010fca000000000b */
/*02d0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void blend_kernel( float *A, float *BP, float *M, float *AP, float alpha, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
// int x = id % w, y = id / w;
float weight = M[id] < 0.05f ? 0.f : alpha;
AP[dc * size + id] =
A[dc * size + id] * weight +
BP[dc * size + id] * (1.f - weight);
}
return ;
} | .file "tmpxft_0014a23d_00000000-6_blend_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii
.type _Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii, @function
_Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12blend_kernelPfS_S_S_fiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii, .-_Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii
.globl _Z12blend_kernelPfS_S_S_fiii
.type _Z12blend_kernelPfS_S_S_fiii, @function
_Z12blend_kernelPfS_S_S_fiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12blend_kernelPfS_S_S_fiii, .-_Z12blend_kernelPfS_S_S_fiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12blend_kernelPfS_S_S_fiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12blend_kernelPfS_S_S_fiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void blend_kernel( float *A, float *BP, float *M, float *AP, float alpha, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
// int x = id % w, y = id / w;
float weight = M[id] < 0.05f ? 0.f : alpha;
AP[dc * size + id] =
A[dc * size + id] * weight +
BP[dc * size + id] * (1.f - weight);
}
return ;
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void blend_kernel( float *A, float *BP, float *M, float *AP, float alpha, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
// int x = id % w, y = id / w;
float weight = M[id] < 0.05f ? 0.f : alpha;
AP[dc * size + id] =
A[dc * size + id] * weight +
BP[dc * size + id] * (1.f - weight);
}
return ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void blend_kernel( float *A, float *BP, float *M, float *AP, float alpha, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
// int x = id % w, y = id / w;
float weight = M[id] < 0.05f ? 0.f : alpha;
AP[dc * size + id] =
A[dc * size + id] * weight +
BP[dc * size + id] * (1.f - weight);
}
return ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12blend_kernelPfS_S_S_fiii
.globl _Z12blend_kernelPfS_S_S_fiii
.p2align 8
.type _Z12blend_kernelPfS_S_S_fiii,@function
_Z12blend_kernelPfS_S_S_fiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s3, s5
s_mul_i32 s3, s2, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s2, s2, s3
s_load_b256 s[4:11], s[0:1], 0x0
s_xor_b32 s2, s2, s3
s_load_b32 s0, s[0:1], 0x20
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
v_add_nc_u32_e32 v4, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v4, v4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v0, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v4, v0
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v0
global_load_b32 v6, v[3:4], off
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(2)
v_cmp_ngt_f32_e32 vcc_lo, 0x3d4ccccd, v6
v_cndmask_b32_e64 v4, 0, s0, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, 1.0, v4
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, v2, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12blend_kernelPfS_S_S_fiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12blend_kernelPfS_S_S_fiii, .Lfunc_end0-_Z12blend_kernelPfS_S_S_fiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12blend_kernelPfS_S_S_fiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12blend_kernelPfS_S_S_fiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void blend_kernel( float *A, float *BP, float *M, float *AP, float alpha, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
// int x = id % w, y = id / w;
float weight = M[id] < 0.05f ? 0.f : alpha;
AP[dc * size + id] =
A[dc * size + id] * weight +
BP[dc * size + id] * (1.f - weight);
}
return ;
} | .text
.file "blend_kernel.hip"
.globl _Z27__device_stub__blend_kernelPfS_S_S_fiii # -- Begin function _Z27__device_stub__blend_kernelPfS_S_S_fiii
.p2align 4, 0x90
.type _Z27__device_stub__blend_kernelPfS_S_S_fiii,@function
_Z27__device_stub__blend_kernelPfS_S_S_fiii: # @_Z27__device_stub__blend_kernelPfS_S_S_fiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12blend_kernelPfS_S_S_fiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__blend_kernelPfS_S_S_fiii, .Lfunc_end0-_Z27__device_stub__blend_kernelPfS_S_S_fiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12blend_kernelPfS_S_S_fiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12blend_kernelPfS_S_S_fiii,@object # @_Z12blend_kernelPfS_S_S_fiii
.section .rodata,"a",@progbits
.globl _Z12blend_kernelPfS_S_S_fiii
.p2align 3, 0x0
_Z12blend_kernelPfS_S_S_fiii:
.quad _Z27__device_stub__blend_kernelPfS_S_S_fiii
.size _Z12blend_kernelPfS_S_S_fiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12blend_kernelPfS_S_S_fiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__blend_kernelPfS_S_S_fiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12blend_kernelPfS_S_S_fiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12blend_kernelPfS_S_S_fiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x18c] ; /* 0x0000630000047a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R4, c[0x0][0x188], RZ ; /* 0x0000620004047a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0060*/ IMAD R3, R4, c[0x0][0x184], RZ ; /* 0x0000610004037a24 */
/* 0x000fca00078e02ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IABS R6, R4.reuse ; /* 0x0000000400067213 */
/* 0x080fe20000000000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IABS R9, R4 ; /* 0x0000000400097213 */
/* 0x000fe40000000000 */
/*00c0*/ I2F.RP R5, R6 ; /* 0x0000000600057306 */
/* 0x000e220000209400 */
/*00d0*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*00e0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f46270 */
/*00f0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fe40007ffe0ff */
/*0110*/ IADD3 R5, RZ, -R9, RZ ; /* 0x80000009ff057210 */
/* 0x000fe20007ffe0ff */
/*0120*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fc600000001ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0160*/ IMAD R7, R7, R6, RZ ; /* 0x0000000607077224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0180*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD R3, R3, R5, R8 ; /* 0x0000000503037224 */
/* 0x000fca00078e0208 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f04070 */
/*01b0*/ @!P0 IADD3 R3, R3, -R6, RZ ; /* 0x8000000603038210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*01e0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fca00078e0a06 */
/*01f0*/ @!P2 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff0303a210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R3, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff038212 */
/* 0x000fca00078e33ff */
/*0210*/ IMAD.WIDE R2, R3, R9, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fcc00078e0209 */
/*0220*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R6, R0, R9, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0209 */
/*0240*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe400078e0209 */
/*0250*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000f22000c1e1900 */
/*0270*/ FSETP.GEU.AND P0, PT, R2, 0.050000000745058059692, PT ; /* 0x3d4ccccd0200780b */
/* 0x004fc80003f0e000 */
/*0280*/ FSEL R10, RZ, c[0x0][0x180], !P0 ; /* 0x00006000ff0a7a08 */
/* 0x000fca0004000000 */
/*0290*/ FADD R8, -R10, 1 ; /* 0x3f8000000a087421 */
/* 0x000fc80000000100 */
/*02a0*/ FMUL R11, R8, R7 ; /* 0x00000007080b7220 */
/* 0x008fe40000400000 */
/*02b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e0209 */
/*02c0*/ FFMA R11, R10, R5, R11 ; /* 0x000000050a0b7223 */
/* 0x010fca000000000b */
/*02d0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12blend_kernelPfS_S_S_fiii
.globl _Z12blend_kernelPfS_S_S_fiii
.p2align 8
.type _Z12blend_kernelPfS_S_S_fiii,@function
_Z12blend_kernelPfS_S_S_fiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s3, s5
s_mul_i32 s3, s2, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s2, s2, s3
s_load_b256 s[4:11], s[0:1], 0x0
s_xor_b32 s2, s2, s3
s_load_b32 s0, s[0:1], 0x20
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
v_add_nc_u32_e32 v4, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v4, v4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v0, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v4, v0
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v0
global_load_b32 v6, v[3:4], off
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(2)
v_cmp_ngt_f32_e32 vcc_lo, 0x3d4ccccd, v6
v_cndmask_b32_e64 v4, 0, s0, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, 1.0, v4
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, v2, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12blend_kernelPfS_S_S_fiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12blend_kernelPfS_S_S_fiii, .Lfunc_end0-_Z12blend_kernelPfS_S_S_fiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12blend_kernelPfS_S_S_fiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12blend_kernelPfS_S_S_fiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014a23d_00000000-6_blend_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii
.type _Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii, @function
_Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12blend_kernelPfS_S_S_fiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii, .-_Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii
.globl _Z12blend_kernelPfS_S_S_fiii
.type _Z12blend_kernelPfS_S_S_fiii, @function
_Z12blend_kernelPfS_S_S_fiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z12blend_kernelPfS_S_S_fiiiPfS_S_S_fiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12blend_kernelPfS_S_S_fiii, .-_Z12blend_kernelPfS_S_S_fiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12blend_kernelPfS_S_S_fiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12blend_kernelPfS_S_S_fiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "blend_kernel.hip"
.globl _Z27__device_stub__blend_kernelPfS_S_S_fiii # -- Begin function _Z27__device_stub__blend_kernelPfS_S_S_fiii
.p2align 4, 0x90
.type _Z27__device_stub__blend_kernelPfS_S_S_fiii,@function
_Z27__device_stub__blend_kernelPfS_S_S_fiii: # @_Z27__device_stub__blend_kernelPfS_S_S_fiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12blend_kernelPfS_S_S_fiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__blend_kernelPfS_S_S_fiii, .Lfunc_end0-_Z27__device_stub__blend_kernelPfS_S_S_fiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12blend_kernelPfS_S_S_fiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12blend_kernelPfS_S_S_fiii,@object # @_Z12blend_kernelPfS_S_S_fiii
.section .rodata,"a",@progbits
.globl _Z12blend_kernelPfS_S_S_fiii
.p2align 3, 0x0
_Z12blend_kernelPfS_S_S_fiii:
.quad _Z27__device_stub__blend_kernelPfS_S_S_fiii
.size _Z12blend_kernelPfS_S_S_fiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12blend_kernelPfS_S_S_fiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__blend_kernelPfS_S_S_fiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12blend_kernelPfS_S_S_fiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Matrix_MultiplElementWise_naiveOLD(const float * A , int Acount, int Acols, const float * B , int Bcount, int Bcols, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row,id_col;
if (id<Acount)
{
if (Acount==Bcount) // matrix .* matrix
{
out0[id] = A[id]*B[id];
}
else if (Bcols==1) // matrix .* row vector
{
id_row = id/Acols;
out0[id] = A[id]*B[id_row];
}
else // matrix .* column vector
{
id_col = id%Acols;
out0[id] = A[id]*B[id_col];
}
}
} | code for sm_80
Function : _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R7, R7, c[0x0][0xc], R0 ; /* 0x0000030007077a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x002fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0090*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fe40000011407 */
/*00c0*/ ISETP.NE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fcc0003f05270 */
/*00d0*/ IMAD.WIDE R4, R7, R0, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE R2, R7, R0, c[0x0][0x180] ; /* 0x0000600007027625 */
/* 0x000fc600078e0200 */
/*00f0*/ @!P0 BRA 0x4d0 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fca00078e00ff */
/*0110*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f05270 */
/*0120*/ IABS R6, c[0x0][0x16c] ; /* 0x00005b0000067a13 */
/* 0x000fd60000000000 */
/*0130*/ @!P0 BRA 0x2f0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0140*/ I2F.RP R10, R6 ; /* 0x00000006000a7306 */
/* 0x000e220000209400 */
/*0150*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x000fe20000000000 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0170*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fca0003f46270 */
/*0180*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0190*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*01a0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*01b0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x001fe200000001ff */
/*01c0*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a09 */
/*01d0*/ IMAD R11, R11, R6, RZ ; /* 0x000000060b0b7224 */
/* 0x000fca00078e02ff */
/*01e0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc800078e0008 */
/*01f0*/ IMAD.MOV.U32 R11, RZ, RZ, R12 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e000c */
/*0200*/ IMAD.HI.U32 R9, R9, R11, RZ ; /* 0x0000000b09097227 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*0220*/ IMAD R9, R6, R9, R11 ; /* 0x0000000906097224 */
/* 0x000fca00078e020b */
/*0230*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f04070 */
/*0240*/ @!P0 IADD3 R9, R9, -R6, RZ ; /* 0x8000000609098210 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe40003f05270 */
/*0260*/ ISETP.GT.U32.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f24070 */
/*0270*/ @!P1 IMAD.IADD R9, R9, 0x1, -R6 ; /* 0x0000000109099824 */
/* 0x000fc800078e0a06 */
/*0280*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0290*/ @!P0 LOP3.LUT R9, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff098a12 */
/* 0x000fca00078e33ff */
/*02a0*/ IMAD.WIDE R6, R9, R0, c[0x0][0x170] ; /* 0x00005c0009067625 */
/* 0x000fcc00078e0200 */
/*02b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ FMUL R9, R6, R5 ; /* 0x0000000506097220 */
/* 0x004fca0000400000 */
/*02d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ I2F.RP R10, R6 ; /* 0x00000006000a7306 */
/* 0x000e220000209400 */
/*0300*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x000fe20000000000 */
/*0310*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0320*/ LOP3.LUT R7, R7, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0007077a12 */
/* 0x000fc800078e3cff */
/*0330*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f06270 */
/*0340*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0350*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*0360*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe200078e00ff */
/*0380*/ IADD3 R11, RZ, -R9, RZ ; /* 0x80000009ff0b7210 */
/* 0x002fca0007ffe0ff */
/*0390*/ IMAD R11, R11, R6, RZ ; /* 0x000000060b0b7224 */
/* 0x000fc800078e02ff */
/*03a0*/ IMAD.HI.U32 R11, R9, R11, R8 ; /* 0x0000000b090b7227 */
/* 0x000fe200078e0008 */
/*03b0*/ MOV R9, R12 ; /* 0x0000000c00097202 */
/* 0x000fca0000000f00 */
/*03c0*/ IMAD.HI.U32 R11, R11, R9, RZ ; /* 0x000000090b0b7227 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD.MOV R10, RZ, RZ, -R11 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a0b */
/*03e0*/ IMAD R9, R6, R10, R9 ; /* 0x0000000a06097224 */
/* 0x000fca00078e0209 */
/*03f0*/ ISETP.GT.U32.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f44070 */
/*0400*/ @!P2 IADD3 R9, R9, -R6.reuse, RZ ; /* 0x800000060909a210 */
/* 0x080fe40007ffe0ff */
/*0410*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x000fe40007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe40003f26070 */
/*0430*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fd60003f45270 */
/*0440*/ @P1 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b1810 */
/* 0x000fca0007ffe0ff */
/*0450*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000b */
/*0460*/ @!P0 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07078210 */
/* 0x000fe40007ffe1ff */
/*0470*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff07aa12 */
/* 0x000fca00078e33ff */
/*0480*/ IMAD.WIDE R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fcc00078e0200 */
/*0490*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ FMUL R9, R6, R5 ; /* 0x0000000506097220 */
/* 0x004fca0000400000 */
/*04b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*04c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04d0*/ LEA R6, P0, R7.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0007067a11 */
/* 0x040fe200078010ff */
/*04e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea6000c1e1900 */
/*04f0*/ LEA.HI.X R7, R7, c[0x0][0x174], R8, 0x2, P0 ; /* 0x00005d0007077a11 */
/* 0x000fcc00000f1408 */
/*0500*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*0510*/ FMUL R9, R4, R7 ; /* 0x0000000704097220 */
/* 0x004fca0000400000 */
/*0520*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Matrix_MultiplElementWise_naiveOLD(const float * A , int Acount, int Acols, const float * B , int Bcount, int Bcols, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row,id_col;
if (id<Acount)
{
if (Acount==Bcount) // matrix .* matrix
{
out0[id] = A[id]*B[id];
}
else if (Bcols==1) // matrix .* row vector
{
id_row = id/Acols;
out0[id] = A[id]*B[id_row];
}
else // matrix .* column vector
{
id_col = id%Acols;
out0[id] = A[id]*B[id_col];
}
}
} | .file "tmpxft_000e7725_00000000-6_Matrix_MultiplElementWise_naiveOLD.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii
.type _Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii, @function
_Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii, .-_Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii
.globl _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.type _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, @function
_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, .-_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Matrix_MultiplElementWise_naiveOLD(const float * A , int Acount, int Acols, const float * B , int Bcount, int Bcols, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row,id_col;
if (id<Acount)
{
if (Acount==Bcount) // matrix .* matrix
{
out0[id] = A[id]*B[id];
}
else if (Bcols==1) // matrix .* row vector
{
id_row = id/Acols;
out0[id] = A[id]*B[id_row];
}
else // matrix .* column vector
{
id_col = id%Acols;
out0[id] = A[id]*B[id_col];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_MultiplElementWise_naiveOLD(const float * A , int Acount, int Acols, const float * B , int Bcount, int Bcols, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row,id_col;
if (id<Acount)
{
if (Acount==Bcount) // matrix .* matrix
{
out0[id] = A[id]*B[id];
}
else if (Bcols==1) // matrix .* row vector
{
id_row = id/Acols;
out0[id] = A[id]*B[id_row];
}
else // matrix .* column vector
{
id_col = id%Acols;
out0[id] = A[id]*B[id_col];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_MultiplElementWise_naiveOLD(const float * A , int Acount, int Acols, const float * B , int Bcount, int Bcols, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row,id_col;
if (id<Acount)
{
if (Acount==Bcount) // matrix .* matrix
{
out0[id] = A[id]*B[id];
}
else if (Bcols==1) // matrix .* row vector
{
id_row = id/Acols;
out0[id] = A[id]*B[id_row];
}
else // matrix .* column vector
{
id_col = id%Acols;
out0[id] = A[id]*B[id_col];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.globl _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.p2align 8
.type _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii,@function
_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_9
s_clause 0x3
s_load_b32 s9, s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s8, s9
s_mov_b32 s8, -1
s_cbranch_scc0 .LBB0_7
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[5:6], off
s_clause 0x1
s_load_b32 s8, s[0:1], 0x1c
s_load_b32 s0, s[0:1], 0xc
s_mov_b32 s1, -1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s8, 1
s_cbranch_scc0 .LBB0_4
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v7, 31, v1
s_add_i32 s8, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s8, s1
v_cvt_f32_u32_e32 v5, s1
s_sub_i32 s8, 0, s1
v_add_nc_u32_e32 v8, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
v_xor_b32_e32 v8, v8, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v5, v5
v_mul_lo_u32 v6, s8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v6
v_add_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v8, v5
v_mul_lo_u32 v5, v5, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v8, v5
v_subrev_nc_u32_e32 v6, s1, v5
v_cmp_le_u32_e32 vcc_lo, s1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s1, v5
v_cmp_le_u32_e32 vcc_lo, s1, v5
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_xor_b32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v7
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, v0, v5
global_store_b32 v[3:4], v5, off
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_6
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v7, 31, v1
s_add_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, s1
v_cvt_f32_u32_e32 v5, s0
s_sub_i32 s8, 0, s0
v_add_nc_u32_e32 v8, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
v_xor_b32_e32 v8, v8, v7
v_xor_b32_e32 v7, s1, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v5, v5
v_mul_lo_u32 v6, s8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v6
v_add_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v8, v5
v_mul_lo_u32 v6, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v8, v6
v_add_nc_u32_e32 v8, 1, v5
v_subrev_nc_u32_e32 v9, s0, v6
v_cmp_le_u32_e32 vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v6, v6, v9 :: v_dual_cndmask_b32 v5, v5, v8
v_cmp_le_u32_e32 vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, 1, v5
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v7
v_sub_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v0, v5
global_store_b32 v[3:4], v0, off
.LBB0_6:
s_mov_b32 s8, 0
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_9
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, .Lfunc_end0-_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_MultiplElementWise_naiveOLD(const float * A , int Acount, int Acols, const float * B , int Bcount, int Bcols, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row,id_col;
if (id<Acount)
{
if (Acount==Bcount) // matrix .* matrix
{
out0[id] = A[id]*B[id];
}
else if (Bcols==1) // matrix .* row vector
{
id_row = id/Acols;
out0[id] = A[id]*B[id_row];
}
else // matrix .* column vector
{
id_col = id%Acols;
out0[id] = A[id]*B[id_col];
}
}
} | .text
.file "Matrix_MultiplElementWise_naiveOLD.hip"
.globl _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii # -- Begin function _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.p2align 4, 0x90
.type _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii,@function
_Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii: # @_Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, .Lfunc_end0-_Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii,@object # @_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.section .rodata,"a",@progbits
.globl _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.p2align 3, 0x0
_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii:
.quad _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.size _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R7, R7, c[0x0][0xc], R0 ; /* 0x0000030007077a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x002fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0090*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ SHF.R.S32.HI R8, RZ, 0x1f, R7 ; /* 0x0000001fff087819 */
/* 0x000fe40000011407 */
/*00c0*/ ISETP.NE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fcc0003f05270 */
/*00d0*/ IMAD.WIDE R4, R7, R0, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE R2, R7, R0, c[0x0][0x180] ; /* 0x0000600007027625 */
/* 0x000fc600078e0200 */
/*00f0*/ @!P0 BRA 0x4d0 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fca00078e00ff */
/*0110*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f05270 */
/*0120*/ IABS R6, c[0x0][0x16c] ; /* 0x00005b0000067a13 */
/* 0x000fd60000000000 */
/*0130*/ @!P0 BRA 0x2f0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0140*/ I2F.RP R10, R6 ; /* 0x00000006000a7306 */
/* 0x000e220000209400 */
/*0150*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x000fe20000000000 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0170*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fca0003f46270 */
/*0180*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0190*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*01a0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*01b0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x001fe200000001ff */
/*01c0*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a09 */
/*01d0*/ IMAD R11, R11, R6, RZ ; /* 0x000000060b0b7224 */
/* 0x000fca00078e02ff */
/*01e0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc800078e0008 */
/*01f0*/ IMAD.MOV.U32 R11, RZ, RZ, R12 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e000c */
/*0200*/ IMAD.HI.U32 R9, R9, R11, RZ ; /* 0x0000000b09097227 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*0220*/ IMAD R9, R6, R9, R11 ; /* 0x0000000906097224 */
/* 0x000fca00078e020b */
/*0230*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f04070 */
/*0240*/ @!P0 IADD3 R9, R9, -R6, RZ ; /* 0x8000000609098210 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe40003f05270 */
/*0260*/ ISETP.GT.U32.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f24070 */
/*0270*/ @!P1 IMAD.IADD R9, R9, 0x1, -R6 ; /* 0x0000000109099824 */
/* 0x000fc800078e0a06 */
/*0280*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0290*/ @!P0 LOP3.LUT R9, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff098a12 */
/* 0x000fca00078e33ff */
/*02a0*/ IMAD.WIDE R6, R9, R0, c[0x0][0x170] ; /* 0x00005c0009067625 */
/* 0x000fcc00078e0200 */
/*02b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ FMUL R9, R6, R5 ; /* 0x0000000506097220 */
/* 0x004fca0000400000 */
/*02d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ I2F.RP R10, R6 ; /* 0x00000006000a7306 */
/* 0x000e220000209400 */
/*0300*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x000fe20000000000 */
/*0310*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0320*/ LOP3.LUT R7, R7, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0007077a12 */
/* 0x000fc800078e3cff */
/*0330*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f06270 */
/*0340*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0350*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*0360*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe200078e00ff */
/*0380*/ IADD3 R11, RZ, -R9, RZ ; /* 0x80000009ff0b7210 */
/* 0x002fca0007ffe0ff */
/*0390*/ IMAD R11, R11, R6, RZ ; /* 0x000000060b0b7224 */
/* 0x000fc800078e02ff */
/*03a0*/ IMAD.HI.U32 R11, R9, R11, R8 ; /* 0x0000000b090b7227 */
/* 0x000fe200078e0008 */
/*03b0*/ MOV R9, R12 ; /* 0x0000000c00097202 */
/* 0x000fca0000000f00 */
/*03c0*/ IMAD.HI.U32 R11, R11, R9, RZ ; /* 0x000000090b0b7227 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD.MOV R10, RZ, RZ, -R11 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a0b */
/*03e0*/ IMAD R9, R6, R10, R9 ; /* 0x0000000a06097224 */
/* 0x000fca00078e0209 */
/*03f0*/ ISETP.GT.U32.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fda0003f44070 */
/*0400*/ @!P2 IADD3 R9, R9, -R6.reuse, RZ ; /* 0x800000060909a210 */
/* 0x080fe40007ffe0ff */
/*0410*/ @!P2 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0ba810 */
/* 0x000fe40007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe40003f26070 */
/*0430*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fd60003f45270 */
/*0440*/ @P1 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b1810 */
/* 0x000fca0007ffe0ff */
/*0450*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000b */
/*0460*/ @!P0 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07078210 */
/* 0x000fe40007ffe1ff */
/*0470*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff07aa12 */
/* 0x000fca00078e33ff */
/*0480*/ IMAD.WIDE R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fcc00078e0200 */
/*0490*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ FMUL R9, R6, R5 ; /* 0x0000000506097220 */
/* 0x004fca0000400000 */
/*04b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*04c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04d0*/ LEA R6, P0, R7.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0007067a11 */
/* 0x040fe200078010ff */
/*04e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea6000c1e1900 */
/*04f0*/ LEA.HI.X R7, R7, c[0x0][0x174], R8, 0x2, P0 ; /* 0x00005d0007077a11 */
/* 0x000fcc00000f1408 */
/*0500*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*0510*/ FMUL R9, R4, R7 ; /* 0x0000000704097220 */
/* 0x004fca0000400000 */
/*0520*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.globl _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.p2align 8
.type _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii,@function
_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_9
s_clause 0x3
s_load_b32 s9, s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s8, s9
s_mov_b32 s8, -1
s_cbranch_scc0 .LBB0_7
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[5:6], off
s_clause 0x1
s_load_b32 s8, s[0:1], 0x1c
s_load_b32 s0, s[0:1], 0xc
s_mov_b32 s1, -1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s8, 1
s_cbranch_scc0 .LBB0_4
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v7, 31, v1
s_add_i32 s8, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s8, s1
v_cvt_f32_u32_e32 v5, s1
s_sub_i32 s8, 0, s1
v_add_nc_u32_e32 v8, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
v_xor_b32_e32 v8, v8, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v5, v5
v_mul_lo_u32 v6, s8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v6
v_add_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v8, v5
v_mul_lo_u32 v5, v5, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v8, v5
v_subrev_nc_u32_e32 v6, s1, v5
v_cmp_le_u32_e32 vcc_lo, s1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s1, v5
v_cmp_le_u32_e32 vcc_lo, s1, v5
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_xor_b32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v7
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, v0, v5
global_store_b32 v[3:4], v5, off
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_6
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v7, 31, v1
s_add_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, s1
v_cvt_f32_u32_e32 v5, s0
s_sub_i32 s8, 0, s0
v_add_nc_u32_e32 v8, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
v_xor_b32_e32 v8, v8, v7
v_xor_b32_e32 v7, s1, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v5, v5
v_mul_lo_u32 v6, s8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v6
v_add_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v8, v5
v_mul_lo_u32 v6, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v8, v6
v_add_nc_u32_e32 v8, 1, v5
v_subrev_nc_u32_e32 v9, s0, v6
v_cmp_le_u32_e32 vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v6, v6, v9 :: v_dual_cndmask_b32 v5, v5, v8
v_cmp_le_u32_e32 vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, 1, v5
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v7
v_sub_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v0, v5
global_store_b32 v[3:4], v0, off
.LBB0_6:
s_mov_b32 s8, 0
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_9
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, .Lfunc_end0-_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e7725_00000000-6_Matrix_MultiplElementWise_naiveOLD.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii
.type _Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii, @function
_Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii, .-_Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii
.globl _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.type _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, @function
_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z66__device_stub__Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfiiPKfiiS0_iiPfii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, .-_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix_MultiplElementWise_naiveOLD.hip"
.globl _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii # -- Begin function _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.p2align 4, 0x90
.type _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii,@function
_Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii: # @_Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, .Lfunc_end0-_Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii,@object # @_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.section .rodata,"a",@progbits
.globl _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.p2align 3, 0x0
_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii:
.quad _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.size _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z49__device_stub__Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z34Matrix_MultiplElementWise_naiveOLDPKfiiS0_iiPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#define gpuErrchk(ans) \
{ gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true) {
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %d %s %s %d\n", code, cudaGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void matrixAddKernel(float *matA, float *matB, float *matC,
int size) {
size_t indexX = blockIdx.x * blockDim.x + threadIdx.x;
size_t strideX = blockDim.x * gridDim.x;
size_t indexY = blockIdx.y * blockDim.y + threadIdx.y;
size_t strideY = blockDim.y * gridDim.y;
for (size_t i = indexX; i < size; i += strideX)
for (size_t j = indexY; j < size; j += strideY)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.B Un thread por elemento
__global__ void matrixAddKernel_B(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < size and j < size)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.C Un thread por fila
__global__ void matrixAddKernel_C(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
}
// 1.D Un thread por columna
__global__ void matrixAddKernel_D(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[j * size + i] = matA[j * size + i] + matB[j * size + i];
}
}
// 1.A
void matrixAdd(float *matA, float *matB, float *matC, int size) {
size_t sizeM = size * size * sizeof(float);
float *d_matA, *d_matB, *d_matC;
gpuErrchk(cudaMalloc(&d_matA, sizeM));
gpuErrchk(cudaMemcpy(d_matA, matA, sizeM, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&d_matB, sizeM));
gpuErrchk(cudaMemcpy(d_matB, matB, sizeM, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&d_matC, sizeM));
// Execute the kernel
// 1.B
dim3 threads(16, 16);
dim3 blocks(ceil(size / threads.x), ceil(size / threads.y));
matrixAddKernel_B<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.C
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_C<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.D
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_D<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
gpuErrchk(cudaMemcpy(matC, d_matC, sizeM, cudaMemcpyDeviceToHost));
cudaFree(d_matC);
cudaFree(d_matA);
cudaFree(d_matB);
}
int main() {
size_t size = 16;
float *matA = new float[size * size];
float *matB = new float[size * size];
float *matC = new float[size * size];
for (size_t i = 0; i < size * size; i++) {
matA[i] = 1.0;
matB[i] = 2.0;
}
matrixAdd(matA, matB, matC, size);
} | .file "tmpxft_001ab3df_00000000-6_matrixAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
.globl _Z15matrixAddKernelPfS_S_i
.type _Z15matrixAddKernelPfS_S_i, @function
_Z15matrixAddKernelPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15matrixAddKernelPfS_S_i, .-_Z15matrixAddKernelPfS_S_i
.globl _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matrixAddKernel_BPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i
.globl _Z17matrixAddKernel_BPfS_S_i
.type _Z17matrixAddKernel_BPfS_S_i, @function
_Z17matrixAddKernel_BPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z17matrixAddKernel_BPfS_S_i, .-_Z17matrixAddKernel_BPfS_S_i
.globl _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matrixAddKernel_CPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i
.globl _Z17matrixAddKernel_CPfS_S_i
.type _Z17matrixAddKernel_CPfS_S_i, @function
_Z17matrixAddKernel_CPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z17matrixAddKernel_CPfS_S_i, .-_Z17matrixAddKernel_CPfS_S_i
.globl _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matrixAddKernel_DPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i
.globl _Z17matrixAddKernel_DPfS_S_i
.type _Z17matrixAddKernel_DPfS_S_i, @function
_Z17matrixAddKernel_DPfS_S_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z17matrixAddKernel_DPfS_S_i, .-_Z17matrixAddKernel_DPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Fredy/UCSP-Paralelos/master/cuda/matrixAdd/matrixAdd.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %d %s %s %d\n"
.text
.globl _Z9matrixAddPfS_S_i
.type _Z9matrixAddPfS_S_i, @function
_Z9matrixAddPfS_S_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r15
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %ecx, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L48
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L49
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L50
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L51
movl $1, 40(%rsp)
movl %ebp, %eax
shrl $4, %eax
movl %eax, 44(%rsp)
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L41:
movl $1, 36(%rsp)
movl $1, 48(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L42:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L43:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl %eax, %r12d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $61
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L48:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $62
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L49:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $64
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L50:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $65
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L51:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $67
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L52:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i
jmp .L41
.L53:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i
jmp .L42
.L54:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i
jmp .L43
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $86
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %ebx, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L56:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9matrixAddPfS_S_i, .-_Z9matrixAddPfS_S_i
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $1024, %edi
call _Znam@PLT
movq %rax, %rbx
movl $1024, %edi
call _Znam@PLT
movq %rax, %rbp
movl $1024, %edi
call _Znam@PLT
movl $0, %edx
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L58:
movss %xmm1, (%rbx,%rdx,4)
movss %xmm0, 0(%rbp,%rdx,4)
addq $1, %rdx
cmpq $256, %rdx
jne .L58
movl $16, %ecx
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z9matrixAddPfS_S_i
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z17matrixAddKernel_DPfS_S_i"
.LC5:
.string "_Z17matrixAddKernel_CPfS_S_i"
.LC6:
.string "_Z17matrixAddKernel_BPfS_S_i"
.LC7:
.string "_Z15matrixAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrixAddKernel_DPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrixAddKernel_CPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrixAddKernel_BPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#define gpuErrchk(ans) \
{ gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true) {
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %d %s %s %d\n", code, cudaGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void matrixAddKernel(float *matA, float *matB, float *matC,
int size) {
size_t indexX = blockIdx.x * blockDim.x + threadIdx.x;
size_t strideX = blockDim.x * gridDim.x;
size_t indexY = blockIdx.y * blockDim.y + threadIdx.y;
size_t strideY = blockDim.y * gridDim.y;
for (size_t i = indexX; i < size; i += strideX)
for (size_t j = indexY; j < size; j += strideY)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.B Un thread por elemento
__global__ void matrixAddKernel_B(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < size and j < size)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.C Un thread por fila
__global__ void matrixAddKernel_C(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
}
// 1.D Un thread por columna
__global__ void matrixAddKernel_D(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[j * size + i] = matA[j * size + i] + matB[j * size + i];
}
}
// 1.A
void matrixAdd(float *matA, float *matB, float *matC, int size) {
size_t sizeM = size * size * sizeof(float);
float *d_matA, *d_matB, *d_matC;
gpuErrchk(cudaMalloc(&d_matA, sizeM));
gpuErrchk(cudaMemcpy(d_matA, matA, sizeM, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&d_matB, sizeM));
gpuErrchk(cudaMemcpy(d_matB, matB, sizeM, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&d_matC, sizeM));
// Execute the kernel
// 1.B
dim3 threads(16, 16);
dim3 blocks(ceil(size / threads.x), ceil(size / threads.y));
matrixAddKernel_B<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.C
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_C<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.D
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_D<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
gpuErrchk(cudaMemcpy(matC, d_matC, sizeM, cudaMemcpyDeviceToHost));
cudaFree(d_matC);
cudaFree(d_matA);
cudaFree(d_matB);
}
int main() {
size_t size = 16;
float *matA = new float[size * size];
float *matB = new float[size * size];
float *matC = new float[size * size];
for (size_t i = 0; i < size * size; i++) {
matA[i] = 1.0;
matB[i] = 2.0;
}
matrixAdd(matA, matB, matC, size);
} | #include <hip/hip_runtime.h>
#include <cstdio>
#define gpuErrchk(ans) \
{ gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %d %s %s %d\n", code, hipGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void matrixAddKernel(float *matA, float *matB, float *matC,
int size) {
size_t indexX = blockIdx.x * blockDim.x + threadIdx.x;
size_t strideX = blockDim.x * gridDim.x;
size_t indexY = blockIdx.y * blockDim.y + threadIdx.y;
size_t strideY = blockDim.y * gridDim.y;
for (size_t i = indexX; i < size; i += strideX)
for (size_t j = indexY; j < size; j += strideY)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.B Un thread por elemento
__global__ void matrixAddKernel_B(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < size and j < size)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.C Un thread por fila
__global__ void matrixAddKernel_C(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
}
// 1.D Un thread por columna
__global__ void matrixAddKernel_D(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[j * size + i] = matA[j * size + i] + matB[j * size + i];
}
}
// 1.A
void matrixAdd(float *matA, float *matB, float *matC, int size) {
size_t sizeM = size * size * sizeof(float);
float *d_matA, *d_matB, *d_matC;
gpuErrchk(hipMalloc(&d_matA, sizeM));
gpuErrchk(hipMemcpy(d_matA, matA, sizeM, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&d_matB, sizeM));
gpuErrchk(hipMemcpy(d_matB, matB, sizeM, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&d_matC, sizeM));
// Execute the kernel
// 1.B
dim3 threads(16, 16);
dim3 blocks(ceil(size / threads.x), ceil(size / threads.y));
matrixAddKernel_B<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.C
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_C<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.D
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_D<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
gpuErrchk(hipMemcpy(matC, d_matC, sizeM, hipMemcpyDeviceToHost));
hipFree(d_matC);
hipFree(d_matA);
hipFree(d_matB);
}
int main() {
size_t size = 16;
float *matA = new float[size * size];
float *matB = new float[size * size];
float *matC = new float[size * size];
for (size_t i = 0; i < size * size; i++) {
matA[i] = 1.0;
matB[i] = 2.0;
}
matrixAdd(matA, matB, matC, size);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#define gpuErrchk(ans) \
{ gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %d %s %s %d\n", code, hipGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void matrixAddKernel(float *matA, float *matB, float *matC,
int size) {
size_t indexX = blockIdx.x * blockDim.x + threadIdx.x;
size_t strideX = blockDim.x * gridDim.x;
size_t indexY = blockIdx.y * blockDim.y + threadIdx.y;
size_t strideY = blockDim.y * gridDim.y;
for (size_t i = indexX; i < size; i += strideX)
for (size_t j = indexY; j < size; j += strideY)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.B Un thread por elemento
__global__ void matrixAddKernel_B(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < size and j < size)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.C Un thread por fila
__global__ void matrixAddKernel_C(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
}
// 1.D Un thread por columna
__global__ void matrixAddKernel_D(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[j * size + i] = matA[j * size + i] + matB[j * size + i];
}
}
// 1.A
void matrixAdd(float *matA, float *matB, float *matC, int size) {
size_t sizeM = size * size * sizeof(float);
float *d_matA, *d_matB, *d_matC;
gpuErrchk(hipMalloc(&d_matA, sizeM));
gpuErrchk(hipMemcpy(d_matA, matA, sizeM, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&d_matB, sizeM));
gpuErrchk(hipMemcpy(d_matB, matB, sizeM, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&d_matC, sizeM));
// Execute the kernel
// 1.B
dim3 threads(16, 16);
dim3 blocks(ceil(size / threads.x), ceil(size / threads.y));
matrixAddKernel_B<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.C
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_C<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.D
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_D<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
gpuErrchk(hipMemcpy(matC, d_matC, sizeM, hipMemcpyDeviceToHost));
hipFree(d_matC);
hipFree(d_matA);
hipFree(d_matB);
}
int main() {
size_t size = 16;
float *matA = new float[size * size];
float *matB = new float[size * size];
float *matC = new float[size * size];
for (size_t i = 0; i < size * size; i++) {
matA[i] = 1.0;
matB[i] = 2.0;
}
matrixAdd(matA, matB, matC, size);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixAddKernelPfS_S_i
.globl _Z15matrixAddKernelPfS_S_i
.p2align 8
.type _Z15matrixAddKernelPfS_S_i,@function
_Z15matrixAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x2c
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s6, v[3:4]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_6
s_load_b32 s7, s[4:5], 0xc
v_bfe_u32 v0, v0, 10, 10
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[16:17], s[0:1], 0x10
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s7, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s7, v[0:1]
v_mov_b32_e32 v4, 0
s_load_b64 s[14:15], s[4:5], 0x0
s_mov_b32 s5, s12
v_mad_u64_u32 v[5:6], null, s2, v1, v[3:4]
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v6
v_mad_u64_u32 v[6:7], null, s3, v1, v[0:1]
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s14, s6
s_mul_i32 s4, s15, s7
s_mul_i32 s0, s3, s13
s_mul_hi_u32 s1, s2, s13
s_mul_i32 s6, s2, s13
s_add_i32 s7, s1, s0
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_lshl_b64 s[6:7], s[6:7], 2
s_mov_b32 s14, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s8, v5
v_add_co_ci_u32_e64 v7, s0, s9, v6, s0
v_add_co_u32 v8, s0, s10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s11, v6, s0
v_add_co_u32 v10, s0, s16, v5
v_add_co_ci_u32_e64 v11, s0, s17, v6, s0
s_lshl_b64 s[8:9], s[4:5], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s15
v_add_co_u32 v1, s0, v1, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s12, v2, s0
v_add_co_u32 v0, s0, v0, s6
v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
v_add_co_u32 v8, s0, v8, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s7, v9, s0
v_cmp_le_u64_e64 s0, s[2:3], v[1:2]
v_add_co_u32 v10, s1, v10, s6
v_add_co_ci_u32_e64 v11, s1, s7, v11, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s14, s0, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s15, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_mov_b64 s[10:11], 0
s_mov_b32 s16, 0
.p2align 6
.LBB0_5:
v_add_co_u32 v12, s0, v0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s11, v7, s0
v_add_co_u32 v14, s0, v8, s10
v_add_co_ci_u32_e64 v15, s0, s11, v9, s0
v_add_co_u32 v5, s0, v5, s4
global_load_b32 v16, v[12:13], off
global_load_b32 v14, v[14:15], off
v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
v_add_co_u32 v12, s0, v10, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v13, s0, s11, v11, s0
v_cmp_le_u64_e64 s1, s[2:3], v[5:6]
s_add_u32 s10, s10, s8
s_addc_u32 s11, s11, s9
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s16, s1, s16
s_waitcnt vmcnt(0)
v_add_f32_e32 v14, v16, v14
global_store_b32 v[12:13], v14, off
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixAddKernelPfS_S_i, .Lfunc_end0-_Z15matrixAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17matrixAddKernel_BPfS_S_i
.globl _Z17matrixAddKernel_BPfS_S_i
.p2align 8
.type _Z17matrixAddKernel_BPfS_S_i,@function
_Z17matrixAddKernel_BPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matrixAddKernel_BPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17matrixAddKernel_BPfS_S_i, .Lfunc_end1-_Z17matrixAddKernel_BPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17matrixAddKernel_CPfS_S_i
.globl _Z17matrixAddKernel_CPfS_S_i
.p2align 8
.type _Z17matrixAddKernel_CPfS_S_i,@function
_Z17matrixAddKernel_CPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB2_4
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB2_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.p2align 6
.LBB2_3:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc1 .LBB2_3
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matrixAddKernel_CPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17matrixAddKernel_CPfS_S_i, .Lfunc_end2-_Z17matrixAddKernel_CPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17matrixAddKernel_DPfS_S_i
.globl _Z17matrixAddKernel_DPfS_S_i
.p2align 8
.type _Z17matrixAddKernel_DPfS_S_i,@function
_Z17matrixAddKernel_DPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB3_4
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB3_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[8:9], s[2:3], 2
v_lshlrev_b64 v[0:1], 2, v[1:2]
.p2align 6
.LBB3_3:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_add_u32 s2, s2, -1
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v6, v4
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB3_3
.LBB3_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matrixAddKernel_DPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z17matrixAddKernel_DPfS_S_i, .Lfunc_end3-_Z17matrixAddKernel_DPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z15matrixAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matrixAddKernel_BPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matrixAddKernel_BPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matrixAddKernel_CPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matrixAddKernel_CPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matrixAddKernel_DPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matrixAddKernel_DPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#define gpuErrchk(ans) \
{ gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %d %s %s %d\n", code, hipGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void matrixAddKernel(float *matA, float *matB, float *matC,
int size) {
size_t indexX = blockIdx.x * blockDim.x + threadIdx.x;
size_t strideX = blockDim.x * gridDim.x;
size_t indexY = blockIdx.y * blockDim.y + threadIdx.y;
size_t strideY = blockDim.y * gridDim.y;
for (size_t i = indexX; i < size; i += strideX)
for (size_t j = indexY; j < size; j += strideY)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.B Un thread por elemento
__global__ void matrixAddKernel_B(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < size and j < size)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
// 1.C Un thread por fila
__global__ void matrixAddKernel_C(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[i * size + j] = matA[i * size + j] + matB[i * size + j];
}
}
// 1.D Un thread por columna
__global__ void matrixAddKernel_D(float *matA, float *matB, float *matC,
int size) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size) {
for (size_t j = 0; j < size; j++)
matC[j * size + i] = matA[j * size + i] + matB[j * size + i];
}
}
// 1.A
void matrixAdd(float *matA, float *matB, float *matC, int size) {
size_t sizeM = size * size * sizeof(float);
float *d_matA, *d_matB, *d_matC;
gpuErrchk(hipMalloc(&d_matA, sizeM));
gpuErrchk(hipMemcpy(d_matA, matA, sizeM, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&d_matB, sizeM));
gpuErrchk(hipMemcpy(d_matB, matB, sizeM, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&d_matC, sizeM));
// Execute the kernel
// 1.B
dim3 threads(16, 16);
dim3 blocks(ceil(size / threads.x), ceil(size / threads.y));
matrixAddKernel_B<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.C
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_C<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
// 1.D
threads = dim3(16);
blocks = dim3(ceil(size / threads.x));
matrixAddKernel_D<<<blocks, threads>>>(d_matA, d_matB, d_matC, size);
gpuErrchk(hipMemcpy(matC, d_matC, sizeM, hipMemcpyDeviceToHost));
hipFree(d_matC);
hipFree(d_matA);
hipFree(d_matB);
}
int main() {
size_t size = 16;
float *matA = new float[size * size];
float *matB = new float[size * size];
float *matC = new float[size * size];
for (size_t i = 0; i < size * size; i++) {
matA[i] = 1.0;
matB[i] = 2.0;
}
matrixAdd(matA, matB, matC, size);
} | .text
.file "matrixAdd.hip"
.globl _Z30__device_stub__matrixAddKernelPfS_S_i # -- Begin function _Z30__device_stub__matrixAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddKernelPfS_S_i,@function
_Z30__device_stub__matrixAddKernelPfS_S_i: # @_Z30__device_stub__matrixAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixAddKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__matrixAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__matrixAddKernel_BPfS_S_i # -- Begin function _Z32__device_stub__matrixAddKernel_BPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matrixAddKernel_BPfS_S_i,@function
_Z32__device_stub__matrixAddKernel_BPfS_S_i: # @_Z32__device_stub__matrixAddKernel_BPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matrixAddKernel_BPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z32__device_stub__matrixAddKernel_BPfS_S_i, .Lfunc_end1-_Z32__device_stub__matrixAddKernel_BPfS_S_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__matrixAddKernel_CPfS_S_i # -- Begin function _Z32__device_stub__matrixAddKernel_CPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matrixAddKernel_CPfS_S_i,@function
_Z32__device_stub__matrixAddKernel_CPfS_S_i: # @_Z32__device_stub__matrixAddKernel_CPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matrixAddKernel_CPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z32__device_stub__matrixAddKernel_CPfS_S_i, .Lfunc_end2-_Z32__device_stub__matrixAddKernel_CPfS_S_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__matrixAddKernel_DPfS_S_i # -- Begin function _Z32__device_stub__matrixAddKernel_DPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matrixAddKernel_DPfS_S_i,@function
_Z32__device_stub__matrixAddKernel_DPfS_S_i: # @_Z32__device_stub__matrixAddKernel_DPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matrixAddKernel_DPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z32__device_stub__matrixAddKernel_DPfS_S_i, .Lfunc_end3-_Z32__device_stub__matrixAddKernel_DPfS_S_i
.cfi_endproc
# -- End function
.globl _Z9matrixAddPfS_S_i # -- Begin function _Z9matrixAddPfS_S_i
.p2align 4, 0x90
.type _Z9matrixAddPfS_S_i,@function
_Z9matrixAddPfS_S_i: # @_Z9matrixAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, %r14d
imull %r14d, %r14d
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit42
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit44
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit46
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit48
movabsq $4294967296, %r15 # imm = 0x100000000
movl %ebp, %r12d
shrl $4, %r12d
leaq 1(%r15), %rdi
imulq %r12, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17matrixAddKernel_BPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13:
orq %r15, %r12
addq $16, %r15
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_15
# %bb.14:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17matrixAddKernel_CPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_15:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17matrixAddKernel_DPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_17:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit62
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $63, %r9d
jmp .LBB4_2
.LBB4_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $64, %r9d
jmp .LBB4_2
.LBB4_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $66, %r9d
jmp .LBB4_2
.LBB4_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $67, %r9d
jmp .LBB4_2
.LBB4_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $69, %r9d
jmp .LBB4_2
.LBB4_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $88, %r9d
.LBB4_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end4:
.size _Z9matrixAddPfS_S_i, .Lfunc_end4-_Z9matrixAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $1024, %edi # imm = 0x400
callq _Znam
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq _Znam
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq _Znam
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB5_1
# %bb.2:
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
movl $16, %ecx
callq _Z9matrixAddPfS_S_i
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrixAddKernel_BPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrixAddKernel_CPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrixAddKernel_DPfS_S_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixAddKernelPfS_S_i,@object # @_Z15matrixAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrixAddKernelPfS_S_i
.p2align 3, 0x0
_Z15matrixAddKernelPfS_S_i:
.quad _Z30__device_stub__matrixAddKernelPfS_S_i
.size _Z15matrixAddKernelPfS_S_i, 8
.type _Z17matrixAddKernel_BPfS_S_i,@object # @_Z17matrixAddKernel_BPfS_S_i
.globl _Z17matrixAddKernel_BPfS_S_i
.p2align 3, 0x0
_Z17matrixAddKernel_BPfS_S_i:
.quad _Z32__device_stub__matrixAddKernel_BPfS_S_i
.size _Z17matrixAddKernel_BPfS_S_i, 8
.type _Z17matrixAddKernel_CPfS_S_i,@object # @_Z17matrixAddKernel_CPfS_S_i
.globl _Z17matrixAddKernel_CPfS_S_i
.p2align 3, 0x0
_Z17matrixAddKernel_CPfS_S_i:
.quad _Z32__device_stub__matrixAddKernel_CPfS_S_i
.size _Z17matrixAddKernel_CPfS_S_i, 8
.type _Z17matrixAddKernel_DPfS_S_i,@object # @_Z17matrixAddKernel_DPfS_S_i
.globl _Z17matrixAddKernel_DPfS_S_i
.p2align 3, 0x0
_Z17matrixAddKernel_DPfS_S_i:
.quad _Z32__device_stub__matrixAddKernel_DPfS_S_i
.size _Z17matrixAddKernel_DPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Fredy/UCSP-Paralelos/master/cuda/matrixAdd/matrixAdd.hip"
.size .L.str, 114
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %d %s %s %d\n"
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixAddKernelPfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17matrixAddKernel_BPfS_S_i"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17matrixAddKernel_CPfS_S_i"
.size .L__unnamed_3, 29
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z17matrixAddKernel_DPfS_S_i"
.size .L__unnamed_4, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixAddKernelPfS_S_i
.addrsig_sym _Z32__device_stub__matrixAddKernel_BPfS_S_i
.addrsig_sym _Z32__device_stub__matrixAddKernel_CPfS_S_i
.addrsig_sym _Z32__device_stub__matrixAddKernel_DPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixAddKernelPfS_S_i
.addrsig_sym _Z17matrixAddKernel_BPfS_S_i
.addrsig_sym _Z17matrixAddKernel_CPfS_S_i
.addrsig_sym _Z17matrixAddKernel_DPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ab3df_00000000-6_matrixAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
.globl _Z15matrixAddKernelPfS_S_i
.type _Z15matrixAddKernelPfS_S_i, @function
_Z15matrixAddKernelPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15matrixAddKernelPfS_S_i, .-_Z15matrixAddKernelPfS_S_i
.globl _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matrixAddKernel_BPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i
.globl _Z17matrixAddKernel_BPfS_S_i
.type _Z17matrixAddKernel_BPfS_S_i, @function
_Z17matrixAddKernel_BPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z17matrixAddKernel_BPfS_S_i, .-_Z17matrixAddKernel_BPfS_S_i
.globl _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matrixAddKernel_CPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i
.globl _Z17matrixAddKernel_CPfS_S_i
.type _Z17matrixAddKernel_CPfS_S_i, @function
_Z17matrixAddKernel_CPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z17matrixAddKernel_CPfS_S_i, .-_Z17matrixAddKernel_CPfS_S_i
.globl _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matrixAddKernel_DPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i
.globl _Z17matrixAddKernel_DPfS_S_i
.type _Z17matrixAddKernel_DPfS_S_i, @function
_Z17matrixAddKernel_DPfS_S_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z17matrixAddKernel_DPfS_S_i, .-_Z17matrixAddKernel_DPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Fredy/UCSP-Paralelos/master/cuda/matrixAdd/matrixAdd.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %d %s %s %d\n"
.text
.globl _Z9matrixAddPfS_S_i
.type _Z9matrixAddPfS_S_i, @function
_Z9matrixAddPfS_S_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r15
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %ecx, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L48
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L49
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L50
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L51
movl $1, 40(%rsp)
movl %ebp, %eax
shrl $4, %eax
movl %eax, 44(%rsp)
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L41:
movl $1, 36(%rsp)
movl $1, 48(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L42:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L43:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl %eax, %r12d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $61
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L48:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $62
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L49:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $64
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L50:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $65
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L51:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $67
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %r12d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L52:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17matrixAddKernel_BPfS_S_iPfS_S_i
jmp .L41
.L53:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17matrixAddKernel_CPfS_S_iPfS_S_i
jmp .L42
.L54:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17matrixAddKernel_DPfS_S_iPfS_S_i
jmp .L43
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 136
pushq $86
.cfi_def_cfa_offset 144
leaq .LC0(%rip), %r9
movl %ebx, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L56:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9matrixAddPfS_S_i, .-_Z9matrixAddPfS_S_i
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $1024, %edi
call _Znam@PLT
movq %rax, %rbx
movl $1024, %edi
call _Znam@PLT
movq %rax, %rbp
movl $1024, %edi
call _Znam@PLT
movl $0, %edx
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L58:
movss %xmm1, (%rbx,%rdx,4)
movss %xmm0, 0(%rbp,%rdx,4)
addq $1, %rdx
cmpq $256, %rdx
jne .L58
movl $16, %ecx
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z9matrixAddPfS_S_i
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z17matrixAddKernel_DPfS_S_i"
.LC5:
.string "_Z17matrixAddKernel_CPfS_S_i"
.LC6:
.string "_Z17matrixAddKernel_BPfS_S_i"
.LC7:
.string "_Z15matrixAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrixAddKernel_DPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrixAddKernel_CPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrixAddKernel_BPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixAdd.hip"
.globl _Z30__device_stub__matrixAddKernelPfS_S_i # -- Begin function _Z30__device_stub__matrixAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddKernelPfS_S_i,@function
_Z30__device_stub__matrixAddKernelPfS_S_i: # @_Z30__device_stub__matrixAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixAddKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__matrixAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__matrixAddKernel_BPfS_S_i # -- Begin function _Z32__device_stub__matrixAddKernel_BPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matrixAddKernel_BPfS_S_i,@function
_Z32__device_stub__matrixAddKernel_BPfS_S_i: # @_Z32__device_stub__matrixAddKernel_BPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matrixAddKernel_BPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z32__device_stub__matrixAddKernel_BPfS_S_i, .Lfunc_end1-_Z32__device_stub__matrixAddKernel_BPfS_S_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__matrixAddKernel_CPfS_S_i # -- Begin function _Z32__device_stub__matrixAddKernel_CPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matrixAddKernel_CPfS_S_i,@function
_Z32__device_stub__matrixAddKernel_CPfS_S_i: # @_Z32__device_stub__matrixAddKernel_CPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matrixAddKernel_CPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z32__device_stub__matrixAddKernel_CPfS_S_i, .Lfunc_end2-_Z32__device_stub__matrixAddKernel_CPfS_S_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__matrixAddKernel_DPfS_S_i # -- Begin function _Z32__device_stub__matrixAddKernel_DPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__matrixAddKernel_DPfS_S_i,@function
_Z32__device_stub__matrixAddKernel_DPfS_S_i: # @_Z32__device_stub__matrixAddKernel_DPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matrixAddKernel_DPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z32__device_stub__matrixAddKernel_DPfS_S_i, .Lfunc_end3-_Z32__device_stub__matrixAddKernel_DPfS_S_i
.cfi_endproc
# -- End function
.globl _Z9matrixAddPfS_S_i # -- Begin function _Z9matrixAddPfS_S_i
.p2align 4, 0x90
.type _Z9matrixAddPfS_S_i,@function
_Z9matrixAddPfS_S_i: # @_Z9matrixAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, %r14d
imull %r14d, %r14d
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit42
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit44
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit46
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit48
movabsq $4294967296, %r15 # imm = 0x100000000
movl %ebp, %r12d
shrl $4, %r12d
leaq 1(%r15), %rdi
imulq %r12, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17matrixAddKernel_BPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13:
orq %r15, %r12
addq $16, %r15
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_15
# %bb.14:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17matrixAddKernel_CPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_15:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17matrixAddKernel_DPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_17:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit62
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $63, %r9d
jmp .LBB4_2
.LBB4_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $64, %r9d
jmp .LBB4_2
.LBB4_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $66, %r9d
jmp .LBB4_2
.LBB4_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $67, %r9d
jmp .LBB4_2
.LBB4_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $69, %r9d
jmp .LBB4_2
.LBB4_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %r8d
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
movl $88, %r9d
.LBB4_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end4:
.size _Z9matrixAddPfS_S_i, .Lfunc_end4-_Z9matrixAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $1024, %edi # imm = 0x400
callq _Znam
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq _Znam
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq _Znam
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB5_1
# %bb.2:
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
movl $16, %ecx
callq _Z9matrixAddPfS_S_i
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrixAddKernel_BPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrixAddKernel_CPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrixAddKernel_DPfS_S_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixAddKernelPfS_S_i,@object # @_Z15matrixAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrixAddKernelPfS_S_i
.p2align 3, 0x0
_Z15matrixAddKernelPfS_S_i:
.quad _Z30__device_stub__matrixAddKernelPfS_S_i
.size _Z15matrixAddKernelPfS_S_i, 8
.type _Z17matrixAddKernel_BPfS_S_i,@object # @_Z17matrixAddKernel_BPfS_S_i
.globl _Z17matrixAddKernel_BPfS_S_i
.p2align 3, 0x0
_Z17matrixAddKernel_BPfS_S_i:
.quad _Z32__device_stub__matrixAddKernel_BPfS_S_i
.size _Z17matrixAddKernel_BPfS_S_i, 8
.type _Z17matrixAddKernel_CPfS_S_i,@object # @_Z17matrixAddKernel_CPfS_S_i
.globl _Z17matrixAddKernel_CPfS_S_i
.p2align 3, 0x0
_Z17matrixAddKernel_CPfS_S_i:
.quad _Z32__device_stub__matrixAddKernel_CPfS_S_i
.size _Z17matrixAddKernel_CPfS_S_i, 8
.type _Z17matrixAddKernel_DPfS_S_i,@object # @_Z17matrixAddKernel_DPfS_S_i
.globl _Z17matrixAddKernel_DPfS_S_i
.p2align 3, 0x0
_Z17matrixAddKernel_DPfS_S_i:
.quad _Z32__device_stub__matrixAddKernel_DPfS_S_i
.size _Z17matrixAddKernel_DPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Fredy/UCSP-Paralelos/master/cuda/matrixAdd/matrixAdd.hip"
.size .L.str, 114
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %d %s %s %d\n"
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixAddKernelPfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17matrixAddKernel_BPfS_S_i"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17matrixAddKernel_CPfS_S_i"
.size .L__unnamed_3, 29
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z17matrixAddKernel_DPfS_S_i"
.size .L__unnamed_4, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixAddKernelPfS_S_i
.addrsig_sym _Z32__device_stub__matrixAddKernel_BPfS_S_i
.addrsig_sym _Z32__device_stub__matrixAddKernel_CPfS_S_i
.addrsig_sym _Z32__device_stub__matrixAddKernel_DPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixAddKernelPfS_S_i
.addrsig_sym _Z17matrixAddKernel_BPfS_S_i
.addrsig_sym _Z17matrixAddKernel_CPfS_S_i
.addrsig_sym _Z17matrixAddKernel_DPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | # include <stdio.h>
# include <stdint.h>
# include "cuda_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
cudaSetDevice(1);
measure_global();
cudaDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 20*256*1024;
// N = 96*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
cudaDeviceReset();
cudaError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != cudaSuccess) {
printf("Error 1.0 is %s\n", cudaGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// // 16MB*33
// for (i=0; i<33; i++){
// h_a[i * 1024 * 256 * 16*2] = (i+1)*256*1024*16*2;
// h_a[i * 1024 * 256 * 16*2+1] = (1+i) * 1024 * 256 * 16*2+1;
// }
// // 1MB*63
// for (i=0; i<63 ; i++){
// h_a[(528*2+i)*256*1024] = (528*2+1+i)*256*1024;
// }
// h_a[528*2*256*1024+1] = 528*2*256*1024+2;
// h_a[528*2*256*1024+2] = 528*2*256*1024+3;
// h_a[528*2*256*1024+3] = 528*2*256*1024+1;
// h_a[591*256*1024 ] = 1;
// for (i=0; i<iterations*160; i++){
// h_a[i ] = (i+1);
// // h_a[i * 16+1] = (1+i) * 16+1;
// }
for (i=0; i<N ; i++){
h_a[i] = (i+1024*16)%N;
}
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
if (error_id != cudaSuccess) {
printf("Error 1.1 is %s\n", cudaGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *duration;
error_id = cudaMalloc ((void **) &duration, sizeof(unsigned int)*160*2);
if (error_id != cudaSuccess) {
printf("Error 1.2 is %s\n", cudaGetErrorString(error_id));
}
unsigned int *d_index;
error_id = cudaMalloc( (void **) &d_index, sizeof(unsigned int)*160*2 );
if (error_id != cudaSuccess) {
printf("Error 1.3 is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
cudaThreadSynchronize ();
error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
printf("Error kernel is %s\n", cudaGetErrorString(error_id));
}
/* copy results from GPU to CPU */
cudaThreadSynchronize ();
error_id = cudaMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160*2, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) {
printf("Error 2.0 is %s\n", cudaGetErrorString(error_id));
}
error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160*2, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) {
printf("Error 2.1 is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize ();
for(i=0;i<iterations*160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
cudaFree(d_a);
cudaFree(d_index);
cudaFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
cudaDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[2*160];
__shared__ unsigned int s_index[2*160];
int k;
int temp;
for(k=0; k<iterations*160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
for (k = 0; k < array_length; k++){
temp += my_array[k];
}
index[2*160] = temp;
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<iterations*160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} | .file "tmpxft_001994dd_00000000-6_global_latency.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
.type _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_, @function
_Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14global_latencyPjiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_, .-_Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
.globl _Z14global_latencyPjiiS_S_
.type _Z14global_latencyPjiiS_S_, @function
_Z14global_latencyPjiiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14global_latencyPjiiS_S_, .-_Z14global_latencyPjiiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error 1.0 is %s\n"
.LC1:
.string "Error 1.1 is %s\n"
.LC2:
.string "Error 1.2 is %s\n"
.LC3:
.string "Error 1.3 is %s\n"
.LC4:
.string "Error kernel is %s\n"
.LC5:
.string "Error 2.0 is %s\n"
.LC6:
.string "Error 2.1 is %s\n"
.LC7:
.string "%d\t %d\n"
.text
.globl _Z25parametric_measure_globalii
.type _Z25parametric_measure_globalii, @function
_Z25parametric_measure_globalii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaDeviceReset@PLT
leal 2(%rbx), %r12d
movslq %r12d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
.L12:
testl %ebx, %ebx
jle .L13
movq %rbp, %rax
movslq %ebx, %rsi
leaq -8(%rbp,%r12), %rdx
.L14:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
movl $0, %ecx
.L15:
leal 16384(%rcx), %eax
cltd
idivl %ebx
movl %edx, 0(%rbp,%rcx,4)
addq $1, %rcx
cmpq %rsi, %rcx
jne .L15
.L13:
leaq -8(%r12), %rdx
movl $0, -8(%rbp,%r12)
movl $0, -4(%rbp,%r12)
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L31
.L16:
movl $1280, %edi
call malloc@PLT
movq %rax, %r14
movl $1280, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $1280, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
.L17:
leaq 24(%rsp), %rdi
movl $1280, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
.L18:
call cudaThreadSynchronize@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L19:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
.L20:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $1280, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
.L21:
movl $2, %ecx
movl $1280, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
.L22:
call cudaThreadSynchronize@PLT
leal 0(%r13,%r13,4), %r15d
sall $5, %r15d
testl %r13d, %r13d
jle .L23
movl $0, %ebx
leaq .LC7(%rip), %r13
.L24:
movl (%r12,%rbx,4), %ecx
movl (%r14,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, %r15d
jg .L24
.L23:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L34:
movq 24(%rsp), %r8
movq 16(%rsp), %rcx
movl %r13d, %edx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
jmp .L19
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z25parametric_measure_globalii, .-_Z25parametric_measure_globalii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n"
.align 8
.LC10:
.string "===============================================\n\n"
.text
.globl _Z14measure_globalv
.type _Z14measure_globalv, @function
_Z14measure_globalv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %esi
movl $5242880, %edi
call _Z25parametric_measure_globalii
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z14measure_globalv, .-_Z14measure_globalv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call cudaSetDevice@PLT
call _Z14measure_globalv
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z14global_latencyPjiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z14global_latencyPjiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1077149696
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | # include <stdio.h>
# include <stdint.h>
# include "cuda_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
cudaSetDevice(1);
measure_global();
cudaDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 20*256*1024;
// N = 96*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
cudaDeviceReset();
cudaError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != cudaSuccess) {
printf("Error 1.0 is %s\n", cudaGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// // 16MB*33
// for (i=0; i<33; i++){
// h_a[i * 1024 * 256 * 16*2] = (i+1)*256*1024*16*2;
// h_a[i * 1024 * 256 * 16*2+1] = (1+i) * 1024 * 256 * 16*2+1;
// }
// // 1MB*63
// for (i=0; i<63 ; i++){
// h_a[(528*2+i)*256*1024] = (528*2+1+i)*256*1024;
// }
// h_a[528*2*256*1024+1] = 528*2*256*1024+2;
// h_a[528*2*256*1024+2] = 528*2*256*1024+3;
// h_a[528*2*256*1024+3] = 528*2*256*1024+1;
// h_a[591*256*1024 ] = 1;
// for (i=0; i<iterations*160; i++){
// h_a[i ] = (i+1);
// // h_a[i * 16+1] = (1+i) * 16+1;
// }
for (i=0; i<N ; i++){
h_a[i] = (i+1024*16)%N;
}
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned int) * N, cudaMemcpyHostToDevice);
if (error_id != cudaSuccess) {
printf("Error 1.1 is %s\n", cudaGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *duration;
error_id = cudaMalloc ((void **) &duration, sizeof(unsigned int)*160*2);
if (error_id != cudaSuccess) {
printf("Error 1.2 is %s\n", cudaGetErrorString(error_id));
}
unsigned int *d_index;
error_id = cudaMalloc( (void **) &d_index, sizeof(unsigned int)*160*2 );
if (error_id != cudaSuccess) {
printf("Error 1.3 is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
cudaThreadSynchronize ();
error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
printf("Error kernel is %s\n", cudaGetErrorString(error_id));
}
/* copy results from GPU to CPU */
cudaThreadSynchronize ();
error_id = cudaMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160*2, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) {
printf("Error 2.0 is %s\n", cudaGetErrorString(error_id));
}
error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160*2, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) {
printf("Error 2.1 is %s\n", cudaGetErrorString(error_id));
}
cudaThreadSynchronize ();
for(i=0;i<iterations*160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
cudaFree(d_a);
cudaFree(d_index);
cudaFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
cudaDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[2*160];
__shared__ unsigned int s_index[2*160];
int k;
int temp;
for(k=0; k<iterations*160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
for (k = 0; k < array_length; k++){
temp += my_array[k];
}
index[2*160] = temp;
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<iterations*160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} | # include <stdio.h>
# include <stdint.h>
# include "hip/hip_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
hipSetDevice(1);
measure_global();
hipDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 20*256*1024;
// N = 96*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
hipDeviceReset();
hipError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = hipMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != hipSuccess) {
printf("Error 1.0 is %s\n", hipGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// // 16MB*33
// for (i=0; i<33; i++){
// h_a[i * 1024 * 256 * 16*2] = (i+1)*256*1024*16*2;
// h_a[i * 1024 * 256 * 16*2+1] = (1+i) * 1024 * 256 * 16*2+1;
// }
// // 1MB*63
// for (i=0; i<63 ; i++){
// h_a[(528*2+i)*256*1024] = (528*2+1+i)*256*1024;
// }
// h_a[528*2*256*1024+1] = 528*2*256*1024+2;
// h_a[528*2*256*1024+2] = 528*2*256*1024+3;
// h_a[528*2*256*1024+3] = 528*2*256*1024+1;
// h_a[591*256*1024 ] = 1;
// for (i=0; i<iterations*160; i++){
// h_a[i ] = (i+1);
// // h_a[i * 16+1] = (1+i) * 16+1;
// }
for (i=0; i<N ; i++){
h_a[i] = (i+1024*16)%N;
}
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = hipMemcpy(d_a, h_a, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
if (error_id != hipSuccess) {
printf("Error 1.1 is %s\n", hipGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *duration;
error_id = hipMalloc ((void **) &duration, sizeof(unsigned int)*160*2);
if (error_id != hipSuccess) {
printf("Error 1.2 is %s\n", hipGetErrorString(error_id));
}
unsigned int *d_index;
error_id = hipMalloc( (void **) &d_index, sizeof(unsigned int)*160*2 );
if (error_id != hipSuccess) {
printf("Error 1.3 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
hipDeviceSynchronize ();
error_id = hipGetLastError();
if (error_id != hipSuccess) {
printf("Error kernel is %s\n", hipGetErrorString(error_id));
}
/* copy results from GPU to CPU */
hipDeviceSynchronize ();
error_id = hipMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160*2, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.0 is %s\n", hipGetErrorString(error_id));
}
error_id = hipMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160*2, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.1 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
for(i=0;i<iterations*160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
hipFree(d_a);
hipFree(d_index);
hipFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
hipDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[2*160];
__shared__ unsigned int s_index[2*160];
int k;
int temp;
for(k=0; k<iterations*160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
for (k = 0; k < array_length; k++){
temp += my_array[k];
}
index[2*160] = temp;
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<iterations*160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | # include <stdio.h>
# include <stdint.h>
# include "hip/hip_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
hipSetDevice(1);
measure_global();
hipDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 20*256*1024;
// N = 96*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
hipDeviceReset();
hipError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = hipMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != hipSuccess) {
printf("Error 1.0 is %s\n", hipGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// // 16MB*33
// for (i=0; i<33; i++){
// h_a[i * 1024 * 256 * 16*2] = (i+1)*256*1024*16*2;
// h_a[i * 1024 * 256 * 16*2+1] = (1+i) * 1024 * 256 * 16*2+1;
// }
// // 1MB*63
// for (i=0; i<63 ; i++){
// h_a[(528*2+i)*256*1024] = (528*2+1+i)*256*1024;
// }
// h_a[528*2*256*1024+1] = 528*2*256*1024+2;
// h_a[528*2*256*1024+2] = 528*2*256*1024+3;
// h_a[528*2*256*1024+3] = 528*2*256*1024+1;
// h_a[591*256*1024 ] = 1;
// for (i=0; i<iterations*160; i++){
// h_a[i ] = (i+1);
// // h_a[i * 16+1] = (1+i) * 16+1;
// }
for (i=0; i<N ; i++){
h_a[i] = (i+1024*16)%N;
}
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = hipMemcpy(d_a, h_a, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
if (error_id != hipSuccess) {
printf("Error 1.1 is %s\n", hipGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *duration;
error_id = hipMalloc ((void **) &duration, sizeof(unsigned int)*160*2);
if (error_id != hipSuccess) {
printf("Error 1.2 is %s\n", hipGetErrorString(error_id));
}
unsigned int *d_index;
error_id = hipMalloc( (void **) &d_index, sizeof(unsigned int)*160*2 );
if (error_id != hipSuccess) {
printf("Error 1.3 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
hipDeviceSynchronize ();
error_id = hipGetLastError();
if (error_id != hipSuccess) {
printf("Error kernel is %s\n", hipGetErrorString(error_id));
}
/* copy results from GPU to CPU */
hipDeviceSynchronize ();
error_id = hipMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160*2, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.0 is %s\n", hipGetErrorString(error_id));
}
error_id = hipMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160*2, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.1 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
for(i=0;i<iterations*160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
hipFree(d_a);
hipFree(d_index);
hipFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
hipDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[2*160];
__shared__ unsigned int s_index[2*160];
int k;
int temp;
for(k=0; k<iterations*160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
for (k = 0; k < array_length; k++){
temp += my_array[k];
}
index[2*160] = temp;
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<iterations*160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14global_latencyPjiiS_S_
.globl _Z14global_latencyPjiiS_S_
.p2align 8
.type _Z14global_latencyPjiiS_S_,@function
_Z14global_latencyPjiiS_S_:
s_load_b32 s9, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 1
s_mul_i32 s8, s9, 0xa0
s_cbranch_scc1 .LBB0_3
v_mov_b32_e32 v0, 0
s_max_i32 s2, s8, 1
s_mov_b32 s3, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s3
s_add_i32 s2, s2, -1
s_add_i32 s3, s3, 4
s_cmp_eq_u32 s2, 0
ds_store_2addr_stride64_b32 v1, v0, v0 offset1:5
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_6
s_mov_b64 s[2:3], s[4:5]
s_mov_b32 s10, s6
.LBB0_5:
s_load_b32 s11, s[2:3], 0x0
s_add_i32 s10, s10, -1
s_waitcnt lgkmcnt(0)
s_add_i32 s7, s11, s7
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s10, 0
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_7
.LBB0_6:
.LBB0_7:
s_load_b64 s[2:3], s[0:1], 0x18
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s7
s_cmp_lt_i32 s9, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[2:3] offset:1280
s_cbranch_scc1 .LBB0_10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_max_i32 s7, s8, 1
s_mov_b32 s10, 0
.p2align 6
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_getreg_b32 s11, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_add_i32 s7, s7, -1
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
v_mov_b32_e32 v2, s10
s_add_i32 s10, s10, 4
s_waitcnt vmcnt(0)
ds_store_b32 v2, v0
s_getreg_b32 s12, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s11, s12, s11
s_cmp_lg_u32 s7, 0
v_mov_b32_e32 v3, s11
ds_store_b32 v2, v3 offset:1280
s_cbranch_scc1 .LBB0_9
.LBB0_10:
v_mov_b32_e32 v1, 0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[6:7], s[6:7], 2
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_cmp_lt_i32 s9, 1
global_store_b32 v1, v0, s[4:5]
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[4:5] offset:4
s_cbranch_scc1 .LBB0_13
s_load_b64 s[0:1], s[0:1], 0x10
s_max_i32 s4, s8, 1
s_mov_b32 s5, 0
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v0, s5
s_add_i32 s4, s4, -1
ds_load_2addr_stride64_b32 v[2:3], v0 offset1:5
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v1, v2, s[2:3]
global_store_b32 v1, v3, s[0:1]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_add_i32 s5, s5, 4
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_12
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14global_latencyPjiiS_S_
.amdhsa_group_segment_fixed_size 2560
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 13
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14global_latencyPjiiS_S_, .Lfunc_end0-_Z14global_latencyPjiiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2560
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14global_latencyPjiiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 15
.sgpr_spill_count: 0
.symbol: _Z14global_latencyPjiiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | # include <stdio.h>
# include <stdint.h>
# include "hip/hip_runtime.h"
//compile nvcc *.cu -o test
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index);
void parametric_measure_global(int N, int iterations);
void measure_global();
int main(){
hipSetDevice(1);
measure_global();
hipDeviceReset();
return 0;
}
void measure_global() {
int N, iterations;
//stride in element
iterations = 1;
N = 20*256*1024;
// N = 96*1024;
printf("\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n", sizeof(unsigned int)*(float)N/1024/1024);
parametric_measure_global(N, iterations);
printf("===============================================\n\n");
}
void parametric_measure_global(int N, int iterations) {
hipDeviceReset();
hipError_t error_id;
int i;
unsigned int * h_a;
/* allocate arrays on CPU */
h_a = (unsigned int *)malloc(sizeof(unsigned int) * (N+2));
unsigned int * d_a;
/* allocate arrays on GPU */
error_id = hipMalloc ((void **) &d_a, sizeof(unsigned int) * (N+2));
if (error_id != hipSuccess) {
printf("Error 1.0 is %s\n", hipGetErrorString(error_id));
}
/* initialize array elements*/
for (i=0; i<N; i++)
h_a[i] = 0;
// // 16MB*33
// for (i=0; i<33; i++){
// h_a[i * 1024 * 256 * 16*2] = (i+1)*256*1024*16*2;
// h_a[i * 1024 * 256 * 16*2+1] = (1+i) * 1024 * 256 * 16*2+1;
// }
// // 1MB*63
// for (i=0; i<63 ; i++){
// h_a[(528*2+i)*256*1024] = (528*2+1+i)*256*1024;
// }
// h_a[528*2*256*1024+1] = 528*2*256*1024+2;
// h_a[528*2*256*1024+2] = 528*2*256*1024+3;
// h_a[528*2*256*1024+3] = 528*2*256*1024+1;
// h_a[591*256*1024 ] = 1;
// for (i=0; i<iterations*160; i++){
// h_a[i ] = (i+1);
// // h_a[i * 16+1] = (1+i) * 16+1;
// }
for (i=0; i<N ; i++){
h_a[i] = (i+1024*16)%N;
}
h_a[N] = 0;
h_a[N+1] = 0;
/* copy array elements from CPU to GPU */
error_id = hipMemcpy(d_a, h_a, sizeof(unsigned int) * N, hipMemcpyHostToDevice);
if (error_id != hipSuccess) {
printf("Error 1.1 is %s\n", hipGetErrorString(error_id));
}
unsigned int *h_index = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *h_timeinfo = (unsigned int *)malloc(sizeof(unsigned int)*160*2);
unsigned int *duration;
error_id = hipMalloc ((void **) &duration, sizeof(unsigned int)*160*2);
if (error_id != hipSuccess) {
printf("Error 1.2 is %s\n", hipGetErrorString(error_id));
}
unsigned int *d_index;
error_id = hipMalloc( (void **) &d_index, sizeof(unsigned int)*160*2 );
if (error_id != hipSuccess) {
printf("Error 1.3 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
/* launch kernel*/
dim3 Db = dim3(1);
dim3 Dg = dim3(1,1,1);
global_latency <<<Dg, Db>>>(d_a, N, iterations, duration, d_index);
hipDeviceSynchronize ();
error_id = hipGetLastError();
if (error_id != hipSuccess) {
printf("Error kernel is %s\n", hipGetErrorString(error_id));
}
/* copy results from GPU to CPU */
hipDeviceSynchronize ();
error_id = hipMemcpy((void *)h_timeinfo, (void *)duration, sizeof(unsigned int)*160*2, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.0 is %s\n", hipGetErrorString(error_id));
}
error_id = hipMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned int)*160*2, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) {
printf("Error 2.1 is %s\n", hipGetErrorString(error_id));
}
hipDeviceSynchronize ();
for(i=0;i<iterations*160;i++)
printf("%d\t %d\n", h_index[i], h_timeinfo[i]);
/* free memory on GPU */
hipFree(d_a);
hipFree(d_index);
hipFree(duration);
/*free memory on CPU */
free(h_a);
free(h_index);
free(h_timeinfo);
hipDeviceReset();
}
__global__ void global_latency (unsigned int * my_array, int array_length, int iterations, unsigned int * duration, unsigned int *index) {
unsigned int start_time, end_time;
unsigned int j = 0;
__shared__ unsigned int s_tvalue[2*160];
__shared__ unsigned int s_index[2*160];
int k;
int temp;
for(k=0; k<iterations*160; k++){
s_index[k] = 0;
s_tvalue[k] = 0;
}
//first round
for (k = 0; k < array_length; k++){
temp += my_array[k];
}
index[2*160] = temp;
//second round
for (k = 0; k < iterations*160; k++) {
start_time = clock();
j = my_array[j];
s_index[k]= j;
end_time = clock();
s_tvalue[k] = end_time-start_time;
}
my_array[array_length] = j;
my_array[array_length+1] = my_array[j];
for(k=0; k<iterations*160; k++){
index[k]= s_index[k];
duration[k] = s_tvalue[k];
}
} | .text
.file "global_latency.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x4034000000000000 # double 20
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1, %edi
callq hipSetDevice
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movl $5242880, %edi # imm = 0x500000
movl $1, %esi
callq _Z25parametric_measure_globalii
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14measure_globalv
.LCPI1_0:
.quad 0x4034000000000000 # double 20
.text
.globl _Z14measure_globalv
.p2align 4, 0x90
.type _Z14measure_globalv,@function
_Z14measure_globalv: # @_Z14measure_globalv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movl $5242880, %edi # imm = 0x500000
movl $1, %esi
callq _Z25parametric_measure_globalii
movl $.Lstr, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z14measure_globalv, .Lfunc_end1-_Z14measure_globalv
.cfi_endproc
# -- End function
.globl _Z25parametric_measure_globalii # -- Begin function _Z25parametric_measure_globalii
.p2align 4, 0x90
.type _Z25parametric_measure_globalii,@function
_Z25parametric_measure_globalii: # @_Z25parametric_measure_globalii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movl %edi, %ebp
callq hipDeviceReset
movslq %ebp, %r15
leaq 8(,%r15,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_2:
movl %ebp, %r12d
testl %ebp, %ebp
jle .LBB2_4
# %bb.3: # %.lr.ph.preheader
leaq (,%r12,4), %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_4: # %.preheader
testl %ebp, %ebp
jle .LBB2_7
# %bb.5: # %.lr.ph72.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph72
# =>This Inner Loop Header: Depth=1
leal 16384(%rcx), %eax
xorl %edx, %edx
divl %ebp
movl %edx, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %r12
jne .LBB2_6
.LBB2_7: # %._crit_edge
movq $0, (%rbx,%r15,4)
movq 24(%rsp), %rdi
shlq $2, %r15
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_9
# %bb.8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_9:
movl $1280, %edi # imm = 0x500
callq malloc
movq %rax, %r15
movl $1280, %edi # imm = 0x500
callq malloc
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $1280, %esi # imm = 0x500
callq hipMalloc
testl %eax, %eax
je .LBB2_11
# %bb.10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_11:
leaq 8(%rsp), %rdi
movl $1280, %esi # imm = 0x500
callq hipMalloc
testl %eax, %eax
je .LBB2_13
# %bb.12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_13:
callq hipDeviceSynchronize
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movl %ebp, 36(%rsp)
movl %r14d, 32(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14global_latencyPjiiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB2_17
# %bb.16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_17:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $1280, %edx # imm = 0x500
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_19
# %bb.18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_19:
movq 8(%rsp), %rsi
movl $1280, %edx # imm = 0x500
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_21
# %bb.20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_21:
callq hipDeviceSynchronize
testl %r14d, %r14d
jle .LBB2_24
# %bb.22: # %.lr.ph75.preheader
shll $5, %r14d
leal (%r14,%r14,4), %eax
cmpl $2, %eax
movl $1, %r14d
cmovgel %eax, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_23: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl (%r12,%r13,4), %edx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB2_23
.LBB2_24: # %._crit_edge76
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
callq hipDeviceReset
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z25parametric_measure_globalii, .Lfunc_end2-_Z25parametric_measure_globalii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__global_latencyPjiiS_S_ # -- Begin function _Z29__device_stub__global_latencyPjiiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__global_latencyPjiiS_S_,@function
_Z29__device_stub__global_latencyPjiiS_S_: # @_Z29__device_stub__global_latencyPjiiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14global_latencyPjiiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z29__device_stub__global_latencyPjiiS_S_, .Lfunc_end3-_Z29__device_stub__global_latencyPjiiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14global_latencyPjiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n"
.size .L.str, 65
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error 1.0 is %s\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error 1.1 is %s\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error 1.2 is %s\n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error 1.3 is %s\n"
.size .L.str.5, 17
.type _Z14global_latencyPjiiS_S_,@object # @_Z14global_latencyPjiiS_S_
.section .rodata,"a",@progbits
.globl _Z14global_latencyPjiiS_S_
.p2align 3, 0x0
_Z14global_latencyPjiiS_S_:
.quad _Z29__device_stub__global_latencyPjiiS_S_
.size _Z14global_latencyPjiiS_S_, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Error kernel is %s\n"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error 2.0 is %s\n"
.size .L.str.7, 17
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error 2.1 is %s\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d\t %d\n"
.size .L.str.9, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14global_latencyPjiiS_S_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "===============================================\n"
.size .Lstr, 49
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__global_latencyPjiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14global_latencyPjiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001994dd_00000000-6_global_latency.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
.type _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_, @function
_Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14global_latencyPjiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_, .-_Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
.globl _Z14global_latencyPjiiS_S_
.type _Z14global_latencyPjiiS_S_, @function
_Z14global_latencyPjiiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14global_latencyPjiiS_S_, .-_Z14global_latencyPjiiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error 1.0 is %s\n"
.LC1:
.string "Error 1.1 is %s\n"
.LC2:
.string "Error 1.2 is %s\n"
.LC3:
.string "Error 1.3 is %s\n"
.LC4:
.string "Error kernel is %s\n"
.LC5:
.string "Error 2.0 is %s\n"
.LC6:
.string "Error 2.1 is %s\n"
.LC7:
.string "%d\t %d\n"
.text
.globl _Z25parametric_measure_globalii
.type _Z25parametric_measure_globalii, @function
_Z25parametric_measure_globalii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaDeviceReset@PLT
leal 2(%rbx), %r12d
movslq %r12d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
.L12:
testl %ebx, %ebx
jle .L13
movq %rbp, %rax
movslq %ebx, %rsi
leaq -8(%rbp,%r12), %rdx
.L14:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
movl $0, %ecx
.L15:
leal 16384(%rcx), %eax
cltd
idivl %ebx
movl %edx, 0(%rbp,%rcx,4)
addq $1, %rcx
cmpq %rsi, %rcx
jne .L15
.L13:
leaq -8(%r12), %rdx
movl $0, -8(%rbp,%r12)
movl $0, -4(%rbp,%r12)
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L31
.L16:
movl $1280, %edi
call malloc@PLT
movq %rax, %r14
movl $1280, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $1280, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
.L17:
leaq 24(%rsp), %rdi
movl $1280, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
.L18:
call cudaThreadSynchronize@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L19:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
.L20:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $1280, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
.L21:
movl $2, %ecx
movl $1280, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
.L22:
call cudaThreadSynchronize@PLT
leal 0(%r13,%r13,4), %r15d
sall $5, %r15d
testl %r13d, %r13d
jle .L23
movl $0, %ebx
leaq .LC7(%rip), %r13
.L24:
movl (%r12,%rbx,4), %ecx
movl (%r14,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, %r15d
jg .L24
.L23:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L34:
movq 24(%rsp), %r8
movq 16(%rsp), %rcx
movl %r13d, %edx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z14global_latencyPjiiS_S_PjiiS_S_
jmp .L19
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z25parametric_measure_globalii, .-_Z25parametric_measure_globalii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n"
.align 8
.LC10:
.string "===============================================\n\n"
.text
.globl _Z14measure_globalv
.type _Z14measure_globalv, @function
_Z14measure_globalv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %esi
movl $5242880, %edi
call _Z25parametric_measure_globalii
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z14measure_globalv, .-_Z14measure_globalv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call cudaSetDevice@PLT
call _Z14measure_globalv
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z14global_latencyPjiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z14global_latencyPjiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1077149696
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "global_latency.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x4034000000000000 # double 20
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1, %edi
callq hipSetDevice
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movl $5242880, %edi # imm = 0x500000
movl $1, %esi
callq _Z25parametric_measure_globalii
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14measure_globalv
.LCPI1_0:
.quad 0x4034000000000000 # double 20
.text
.globl _Z14measure_globalv
.p2align 4, 0x90
.type _Z14measure_globalv,@function
_Z14measure_globalv: # @_Z14measure_globalv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movl $5242880, %edi # imm = 0x500000
movl $1, %esi
callq _Z25parametric_measure_globalii
movl $.Lstr, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z14measure_globalv, .Lfunc_end1-_Z14measure_globalv
.cfi_endproc
# -- End function
.globl _Z25parametric_measure_globalii # -- Begin function _Z25parametric_measure_globalii
.p2align 4, 0x90
.type _Z25parametric_measure_globalii,@function
_Z25parametric_measure_globalii: # @_Z25parametric_measure_globalii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movl %edi, %ebp
callq hipDeviceReset
movslq %ebp, %r15
leaq 8(,%r15,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_2:
movl %ebp, %r12d
testl %ebp, %ebp
jle .LBB2_4
# %bb.3: # %.lr.ph.preheader
leaq (,%r12,4), %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_4: # %.preheader
testl %ebp, %ebp
jle .LBB2_7
# %bb.5: # %.lr.ph72.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph72
# =>This Inner Loop Header: Depth=1
leal 16384(%rcx), %eax
xorl %edx, %edx
divl %ebp
movl %edx, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %r12
jne .LBB2_6
.LBB2_7: # %._crit_edge
movq $0, (%rbx,%r15,4)
movq 24(%rsp), %rdi
shlq $2, %r15
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_9
# %bb.8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_9:
movl $1280, %edi # imm = 0x500
callq malloc
movq %rax, %r15
movl $1280, %edi # imm = 0x500
callq malloc
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $1280, %esi # imm = 0x500
callq hipMalloc
testl %eax, %eax
je .LBB2_11
# %bb.10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_11:
leaq 8(%rsp), %rdi
movl $1280, %esi # imm = 0x500
callq hipMalloc
testl %eax, %eax
je .LBB2_13
# %bb.12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_13:
callq hipDeviceSynchronize
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movl %ebp, 36(%rsp)
movl %r14d, 32(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14global_latencyPjiiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB2_17
# %bb.16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_17:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $1280, %edx # imm = 0x500
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_19
# %bb.18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_19:
movq 8(%rsp), %rsi
movl $1280, %edx # imm = 0x500
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_21
# %bb.20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_21:
callq hipDeviceSynchronize
testl %r14d, %r14d
jle .LBB2_24
# %bb.22: # %.lr.ph75.preheader
shll $5, %r14d
leal (%r14,%r14,4), %eax
cmpl $2, %eax
movl $1, %r14d
cmovgel %eax, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_23: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl (%r12,%r13,4), %edx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB2_23
.LBB2_24: # %._crit_edge76
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
callq hipDeviceReset
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z25parametric_measure_globalii, .Lfunc_end2-_Z25parametric_measure_globalii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__global_latencyPjiiS_S_ # -- Begin function _Z29__device_stub__global_latencyPjiiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__global_latencyPjiiS_S_,@function
_Z29__device_stub__global_latencyPjiiS_S_: # @_Z29__device_stub__global_latencyPjiiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14global_latencyPjiiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z29__device_stub__global_latencyPjiiS_S_, .Lfunc_end3-_Z29__device_stub__global_latencyPjiiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14global_latencyPjiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n=====%10.4f MB array, Fermi pattern read, read 160 element====\n"
.size .L.str, 65
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error 1.0 is %s\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error 1.1 is %s\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error 1.2 is %s\n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error 1.3 is %s\n"
.size .L.str.5, 17
.type _Z14global_latencyPjiiS_S_,@object # @_Z14global_latencyPjiiS_S_
.section .rodata,"a",@progbits
.globl _Z14global_latencyPjiiS_S_
.p2align 3, 0x0
_Z14global_latencyPjiiS_S_:
.quad _Z29__device_stub__global_latencyPjiiS_S_
.size _Z14global_latencyPjiiS_S_, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Error kernel is %s\n"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error 2.0 is %s\n"
.size .L.str.7, 17
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error 2.1 is %s\n"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d\t %d\n"
.size .L.str.9, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14global_latencyPjiiS_S_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "===============================================\n"
.size .Lstr, 49
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__global_latencyPjiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14global_latencyPjiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void float_to_color(uchar4 * pixels, float* in){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float num = in[offset];
pixels[offset].x = (int)(num*255);
pixels[offset].y = (int)(0);
pixels[offset].z = (int)((MAX_TEMP-num) * 255);
pixels[offset].w = 255;
} | code for sm_80
Function : _Z14float_to_colorP6uchar4Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fce00078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 1.5199184417724609375e-05 ; /* 0x000000ffff097435 */
/* 0x000fe200000001ff */
/*00d0*/ FMUL R6, R2.reuse, 255 ; /* 0x437f000002067820 */
/* 0x044fe40000400000 */
/*00e0*/ FADD R4, -R2, 1 ; /* 0x3f80000002047421 */
/* 0x000fc80000000100 */
/*00f0*/ FMUL R7, R4, 255 ; /* 0x437f000004077820 */
/* 0x000fe20000400000 */
/*0100*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*0110*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e62000020f100 */
/*0120*/ PRMT R4, RZ, 0x7604, R6 ; /* 0x00007604ff047816 */
/* 0x001fc80000000006 */
/*0130*/ PRMT R8, R7, 0x7054, R4 ; /* 0x0000705407087816 */
/* 0x002fe20000000004 */
/*0140*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0205 */
/*0150*/ PRMT R9, R9, 0x654, R8 ; /* 0x0000065409097816 */
/* 0x000fca0000000008 */
/*0160*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void float_to_color(uchar4 * pixels, float* in){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float num = in[offset];
pixels[offset].x = (int)(num*255);
pixels[offset].y = (int)(0);
pixels[offset].z = (int)((MAX_TEMP-num) * 255);
pixels[offset].w = 255;
} | .file "tmpxft_00084e5c_00000000-6_float_to_color.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf
.type _Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf, @function
_Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14float_to_colorP6uchar4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf, .-_Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf
.globl _Z14float_to_colorP6uchar4Pf
.type _Z14float_to_colorP6uchar4Pf, @function
_Z14float_to_colorP6uchar4Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14float_to_colorP6uchar4Pf, .-_Z14float_to_colorP6uchar4Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14float_to_colorP6uchar4Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14float_to_colorP6uchar4Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void float_to_color(uchar4 * pixels, float* in){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float num = in[offset];
pixels[offset].x = (int)(num*255);
pixels[offset].y = (int)(0);
pixels[offset].z = (int)((MAX_TEMP-num) * 255);
pixels[offset].w = 255;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void float_to_color(uchar4 * pixels, float* in){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float num = in[offset];
pixels[offset].x = (int)(num*255);
pixels[offset].y = (int)(0);
pixels[offset].z = (int)((MAX_TEMP-num) * 255);
pixels[offset].w = 255;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void float_to_color(uchar4 * pixels, float* in){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float num = in[offset];
pixels[offset].x = (int)(num*255);
pixels[offset].y = (int)(0);
pixels[offset].z = (int)((MAX_TEMP-num) * 255);
pixels[offset].w = 255;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.globl _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.p2align 8
.type _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf,@function
_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v5, 0xff
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, s2, s[14:15]
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v4, 0
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v2, 0x437f0000, v2 :: v_dual_mul_f32 v3, 0x437f0000, v3
v_cvt_i32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2)
v_cvt_i32_f32_e32 v3, v3
s_clause 0x3
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v4, off offset:1
global_store_b8 v[0:1], v3, off offset:2
global_store_b8 v[0:1], v5, off offset:3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf, .Lfunc_end0-_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void float_to_color(uchar4 * pixels, float* in){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y * blockDim.x * gridDim.x;
float num = in[offset];
pixels[offset].x = (int)(num*255);
pixels[offset].y = (int)(0);
pixels[offset].z = (int)((MAX_TEMP-num) * 255);
pixels[offset].w = 255;
} | .text
.file "float_to_color.hip"
.globl _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf # -- Begin function _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.p2align 4, 0x90
.type _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf,@function
_Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf: # @_Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf, .Lfunc_end0-_Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf,@object # @_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.section .rodata,"a",@progbits
.globl _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.p2align 3, 0x0
_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf:
.quad _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.size _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14float_to_colorP6uchar4Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fce00078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 1.5199184417724609375e-05 ; /* 0x000000ffff097435 */
/* 0x000fe200000001ff */
/*00d0*/ FMUL R6, R2.reuse, 255 ; /* 0x437f000002067820 */
/* 0x044fe40000400000 */
/*00e0*/ FADD R4, -R2, 1 ; /* 0x3f80000002047421 */
/* 0x000fc80000000100 */
/*00f0*/ FMUL R7, R4, 255 ; /* 0x437f000004077820 */
/* 0x000fe20000400000 */
/*0100*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e30000020f100 */
/*0110*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e62000020f100 */
/*0120*/ PRMT R4, RZ, 0x7604, R6 ; /* 0x00007604ff047816 */
/* 0x001fc80000000006 */
/*0130*/ PRMT R8, R7, 0x7054, R4 ; /* 0x0000705407087816 */
/* 0x002fe20000000004 */
/*0140*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0205 */
/*0150*/ PRMT R9, R9, 0x654, R8 ; /* 0x0000065409097816 */
/* 0x000fca0000000008 */
/*0160*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.globl _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.p2align 8
.type _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf,@function
_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v5, 0xff
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, s2, s[14:15]
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v4, 0
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v2, 0x437f0000, v2 :: v_dual_mul_f32 v3, 0x437f0000, v3
v_cvt_i32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2)
v_cvt_i32_f32_e32 v3, v3
s_clause 0x3
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v4, off offset:1
global_store_b8 v[0:1], v3, off offset:2
global_store_b8 v[0:1], v5, off offset:3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf, .Lfunc_end0-_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00084e5c_00000000-6_float_to_color.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf
.type _Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf, @function
_Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14float_to_colorP6uchar4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf, .-_Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf
.globl _Z14float_to_colorP6uchar4Pf
.type _Z14float_to_colorP6uchar4Pf, @function
_Z14float_to_colorP6uchar4Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z14float_to_colorP6uchar4PfP6uchar4Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14float_to_colorP6uchar4Pf, .-_Z14float_to_colorP6uchar4Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14float_to_colorP6uchar4Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14float_to_colorP6uchar4Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "float_to_color.hip"
.globl _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf # -- Begin function _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.p2align 4, 0x90
.type _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf,@function
_Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf: # @_Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf, .Lfunc_end0-_Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf,@object # @_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.section .rodata,"a",@progbits
.globl _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.p2align 3, 0x0
_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf:
.quad _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.size _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14float_to_colorP15HIP_vector_typeIhLj4EEPf"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__float_to_colorP15HIP_vector_typeIhLj4EEPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14float_to_colorP15HIP_vector_typeIhLj4EEPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
/* Thread block size = number of threads of a block*/
/* Notice: in this example, the input data size = BLOCK_SIZE */
/* (different with the CUDA Reduction assigment) */
#define BLOCK_SIZE 16
__global__ void work_efficient_scan(const float* input, float* output, int size)
{
/*Declare the shared memory*/
__shared__ float XY[BLOCK_SIZE];
/**/
unsigned int t = threadIdx.x;
/*load data from global memory to shared memory*/
XY[t] = input[t];
/*****************************************************************/
/* YOUR TODO-1 STARTS HERE */
/* Implement the Reduction step, */
/* (the final results is kept in the last element */
/*****************************************************************/
for(int stride = 1;stride<blockDim.x;stride*=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index < blockDim.x) XY[index]+=XY[index-stride];
}
/*************************************************************/
/* YOUR TODO-1 ENDS HERE */
/*************************************************************/
/*************************************************************/
/* YOUR TODO-2 STARTS HERE */
/* Implement the "post scan" step */
/* to finish the inclusive scan */
/*************************************************************/
for(int stride=size/4;stride>0;stride/=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index+stride < blockDim.x) XY[index+stride] += XY[index];
}
/*************************************************************/
/* YOUR TODO-2 ENDS HERE */
/*************************************************************/
__syncthreads();
/* write the final output to global memory */
output[t] = XY[t];
}
/**/
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/**/
float* h_input, *h_output;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
/* read the value of size from stdin*/
scanf("%d", &size);
/* Allocate host memory */
h_input = (float*) malloc(sizeof(float)*size);
h_output = (float*) malloc(sizeof(float)*size);
/* read input from stdin */
for(i=0;i<size*size;++i){ scanf("%f", &h_input[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
float* d_input, *d_output;
cudaMalloc(&d_input,sizeof(float)*size);
cudaMalloc(&d_output,sizeof(float)*size);
cudaEventRecord(start,0);
/***********************************/
/* copy input data to device */
/***********************************/
cudaMemcpy(d_input, h_input, size*sizeof(float), cudaMemcpyHostToDevice);
/*************************************/
/* call kernel */
/* 1 block, BLOCK_SIZE threads */
/*************************************/
work_efficient_scan<<<1,BLOCK_SIZE>>>(d_input, d_output,size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_output, d_output, sizeof(float)*size, cudaMemcpyDeviceToHost);
/**/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/*******************************************/
/* Print the final scan result */
/*******************************************/
printf("The final inclusive scan result:\n");
for(int i=0;i<size;++i)printf("%4.1f ",h_output[i]);
/* free device memory */
cudaFree(d_input);
cudaFree(d_output);
/* free host memory */
free(h_input);
free(h_output);
/**/
return 0;
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | code for sm_80
Function : _Z19work_efficient_scanPKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fcc00078e0002 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff007435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fca00078e00ff */
/*0080*/ ISETP.LE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f03270 */
/*0090*/ ISETP.LE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fe20003f23070 */
/*00a0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041d80000004800 */
/*00b0*/ @!P1 BRA 0x190 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*00c0*/ LEA R0, R7, 0x2, 0x1 ; /* 0x0000000207007811 */
/* 0x000fe200078e08ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fc600078e00ff */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ IMAD R6, R0, R3, -0x1 ; /* 0xffffffff00067424 */
/* 0x000fca00078e0203 */
/*0100*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f26070 */
/*0110*/ @!P1 IADD3 R2, R6, -R3, RZ ; /* 0x8000000306029210 */
/* 0x001fe20007ffe0ff */
/*0120*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x000fe200078e00ff */
/*0130*/ @!P1 LDS R4, [R6.X4] ; /* 0x0000000006049984 */
/* 0x000fe80000004800 */
/*0140*/ @!P1 LDS R5, [R2.X4] ; /* 0x0000000002059984 */
/* 0x000e240000004800 */
/*0150*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0160*/ @!P1 STS [R6.X4], R4 ; /* 0x0000000406009388 */
/* 0x0001e20000004800 */
/*0170*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x0], PT ; /* 0x0000000003007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @!P1 BRA 0xe0 ; /* 0xffffff5000009947 */
/* 0x001fea000383ffff */
/*0190*/ @!P0 BRA 0x2b0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*01b0*/ LEA R9, R7, 0x2, 0x1 ; /* 0x0000000207097811 */
/* 0x000fe200078e08ff */
/*01c0*/ USHF.R.U32.HI UR4, URZ, 0x2, UR4 ; /* 0x000000023f047899 */
/* 0x000fcc0008011604 */
/*01d0*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fc8000f8e00ff */
/*01e0*/ IMAD R5, R9, R0.reuse, -0x1 ; /* 0xffffffff09057424 */
/* 0x080fe200078e0200 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0200*/ IADD3 R2, R5, R0, RZ ; /* 0x0000000005027210 */
/* 0x001fc80007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x0], PT ; /* 0x0000000002007a0c */
/* 0x000fda0003f06070 */
/*0220*/ @!P0 IMAD.SHL.U32 R3, R5, 0x4, RZ ; /* 0x0000000405038824 */
/* 0x000fe400078e00ff */
/*0230*/ @!P0 LDS R5, [R5.X4] ; /* 0x0000000005058984 */
/* 0x000fe60000004800 */
/*0240*/ @!P0 LEA R3, R0, R3, 0x2 ; /* 0x0000000300038211 */
/* 0x000fe400078e10ff */
/*0250*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc60000011600 */
/*0260*/ @!P0 LDS R2, [R3] ; /* 0x0000000003028984 */
/* 0x000e240000000800 */
/*0270*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*0280*/ @!P0 STS [R3], R2 ; /* 0x0000000203008388 */
/* 0x0001e20000000800 */
/*0290*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*02a0*/ @P0 BRA 0x1e0 ; /* 0xffffff3000000947 */
/* 0x001fea000383ffff */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ LEA R2, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x001fc800078010ff */
/*02d0*/ LEA.HI.X R3, R7, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fe200000f14ff */
/*02e0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*02f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
/* Thread block size = number of threads of a block*/
/* Notice: in this example, the input data size = BLOCK_SIZE */
/* (different with the CUDA Reduction assigment) */
#define BLOCK_SIZE 16
__global__ void work_efficient_scan(const float* input, float* output, int size)
{
/*Declare the shared memory*/
__shared__ float XY[BLOCK_SIZE];
/**/
unsigned int t = threadIdx.x;
/*load data from global memory to shared memory*/
XY[t] = input[t];
/*****************************************************************/
/* YOUR TODO-1 STARTS HERE */
/* Implement the Reduction step, */
/* (the final results is kept in the last element */
/*****************************************************************/
for(int stride = 1;stride<blockDim.x;stride*=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index < blockDim.x) XY[index]+=XY[index-stride];
}
/*************************************************************/
/* YOUR TODO-1 ENDS HERE */
/*************************************************************/
/*************************************************************/
/* YOUR TODO-2 STARTS HERE */
/* Implement the "post scan" step */
/* to finish the inclusive scan */
/*************************************************************/
for(int stride=size/4;stride>0;stride/=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index+stride < blockDim.x) XY[index+stride] += XY[index];
}
/*************************************************************/
/* YOUR TODO-2 ENDS HERE */
/*************************************************************/
__syncthreads();
/* write the final output to global memory */
output[t] = XY[t];
}
/**/
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/**/
float* h_input, *h_output;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
/* read the value of size from stdin*/
scanf("%d", &size);
/* Allocate host memory */
h_input = (float*) malloc(sizeof(float)*size);
h_output = (float*) malloc(sizeof(float)*size);
/* read input from stdin */
for(i=0;i<size*size;++i){ scanf("%f", &h_input[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
float* d_input, *d_output;
cudaMalloc(&d_input,sizeof(float)*size);
cudaMalloc(&d_output,sizeof(float)*size);
cudaEventRecord(start,0);
/***********************************/
/* copy input data to device */
/***********************************/
cudaMemcpy(d_input, h_input, size*sizeof(float), cudaMemcpyHostToDevice);
/*************************************/
/* call kernel */
/* 1 block, BLOCK_SIZE threads */
/*************************************/
work_efficient_scan<<<1,BLOCK_SIZE>>>(d_input, d_output,size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_output, d_output, sizeof(float)*size, cudaMemcpyDeviceToHost);
/**/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/*******************************************/
/* Print the final scan result */
/*******************************************/
printf("The final inclusive scan result:\n");
for(int i=0;i<size;++i)printf("%4.1f ",h_output[i]);
/* free device memory */
cudaFree(d_input);
cudaFree(d_output);
/* free host memory */
free(h_input);
free(h_output);
/**/
return 0;
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .file "tmpxft_000ffcf2_00000000-6_cudaScan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi
.type _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi, @function
_Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19work_efficient_scanPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi, .-_Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi
.globl _Z19work_efficient_scanPKfPfi
.type _Z19work_efficient_scanPKfPfi, @function
_Z19work_efficient_scanPKfPfi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19work_efficient_scanPKfPfi, .-_Z19work_efficient_scanPKfPfi
.section .rodata.str1.1
.LC1:
.string "%d"
.LC2:
.string "%f"
.LC3:
.string "Kernel Invoking"
.LC4:
.string "Elapsed time = %f (s)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "The final inclusive scan result:\n"
.section .rodata.str1.1
.LC6:
.string "%4.1f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, 12(%rsp)
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %ebx
movslq %ebx, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
movl %ebx, %eax
imull %ebx, %eax
testl %eax, %eax
jle .L16
movq %r12, %r14
movl $0, %r13d
leaq .LC2(%rip), %r15
.L17:
movq %r14, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %r13d
movl 12(%rsp), %ebx
addq $4, %r14
movl %ebx, %eax
imull %ebx, %eax
cmpl %r13d, %eax
jg .L17
.L16:
movslq %ebx, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L18:
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKc
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L19
movl $0, %ebx
leaq .LC6(%rip), %r13
.L20:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 12(%rsp)
jg .L20
.L19:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl 12(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z19work_efficient_scanPKfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19work_efficient_scanPKfPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
/* Thread block size = number of threads of a block*/
/* Notice: in this example, the input data size = BLOCK_SIZE */
/* (different with the CUDA Reduction assigment) */
#define BLOCK_SIZE 16
__global__ void work_efficient_scan(const float* input, float* output, int size)
{
/*Declare the shared memory*/
__shared__ float XY[BLOCK_SIZE];
/**/
unsigned int t = threadIdx.x;
/*load data from global memory to shared memory*/
XY[t] = input[t];
/*****************************************************************/
/* YOUR TODO-1 STARTS HERE */
/* Implement the Reduction step, */
/* (the final results is kept in the last element */
/*****************************************************************/
for(int stride = 1;stride<blockDim.x;stride*=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index < blockDim.x) XY[index]+=XY[index-stride];
}
/*************************************************************/
/* YOUR TODO-1 ENDS HERE */
/*************************************************************/
/*************************************************************/
/* YOUR TODO-2 STARTS HERE */
/* Implement the "post scan" step */
/* to finish the inclusive scan */
/*************************************************************/
for(int stride=size/4;stride>0;stride/=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index+stride < blockDim.x) XY[index+stride] += XY[index];
}
/*************************************************************/
/* YOUR TODO-2 ENDS HERE */
/*************************************************************/
__syncthreads();
/* write the final output to global memory */
output[t] = XY[t];
}
/**/
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/**/
float* h_input, *h_output;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
/* read the value of size from stdin*/
scanf("%d", &size);
/* Allocate host memory */
h_input = (float*) malloc(sizeof(float)*size);
h_output = (float*) malloc(sizeof(float)*size);
/* read input from stdin */
for(i=0;i<size*size;++i){ scanf("%f", &h_input[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
float* d_input, *d_output;
cudaMalloc(&d_input,sizeof(float)*size);
cudaMalloc(&d_output,sizeof(float)*size);
cudaEventRecord(start,0);
/***********************************/
/* copy input data to device */
/***********************************/
cudaMemcpy(d_input, h_input, size*sizeof(float), cudaMemcpyHostToDevice);
/*************************************/
/* call kernel */
/* 1 block, BLOCK_SIZE threads */
/*************************************/
work_efficient_scan<<<1,BLOCK_SIZE>>>(d_input, d_output,size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_output, d_output, sizeof(float)*size, cudaMemcpyDeviceToHost);
/**/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/*******************************************/
/* Print the final scan result */
/*******************************************/
printf("The final inclusive scan result:\n");
for(int i=0;i<size;++i)printf("%4.1f ",h_output[i]);
/* free device memory */
cudaFree(d_input);
cudaFree(d_output);
/* free host memory */
free(h_input);
free(h_output);
/**/
return 0;
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | #include <stdio.h>
#include <hip/hip_runtime.h>
/* Thread block size = number of threads of a block*/
/* Notice: in this example, the input data size = BLOCK_SIZE */
/* (different with the CUDA Reduction assigment) */
#define BLOCK_SIZE 16
__global__ void work_efficient_scan(const float* input, float* output, int size)
{
/*Declare the shared memory*/
__shared__ float XY[BLOCK_SIZE];
/**/
unsigned int t = threadIdx.x;
/*load data from global memory to shared memory*/
XY[t] = input[t];
/*****************************************************************/
/* YOUR TODO-1 STARTS HERE */
/* Implement the Reduction step, */
/* (the final results is kept in the last element */
/*****************************************************************/
for(int stride = 1;stride<blockDim.x;stride*=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index < blockDim.x) XY[index]+=XY[index-stride];
}
/*************************************************************/
/* YOUR TODO-1 ENDS HERE */
/*************************************************************/
/*************************************************************/
/* YOUR TODO-2 STARTS HERE */
/* Implement the "post scan" step */
/* to finish the inclusive scan */
/*************************************************************/
for(int stride=size/4;stride>0;stride/=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index+stride < blockDim.x) XY[index+stride] += XY[index];
}
/*************************************************************/
/* YOUR TODO-2 ENDS HERE */
/*************************************************************/
__syncthreads();
/* write the final output to global memory */
output[t] = XY[t];
}
/**/
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/**/
float* h_input, *h_output;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
/* read the value of size from stdin*/
scanf("%d", &size);
/* Allocate host memory */
h_input = (float*) malloc(sizeof(float)*size);
h_output = (float*) malloc(sizeof(float)*size);
/* read input from stdin */
for(i=0;i<size*size;++i){ scanf("%f", &h_input[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
float* d_input, *d_output;
hipMalloc(&d_input,sizeof(float)*size);
hipMalloc(&d_output,sizeof(float)*size);
hipEventRecord(start,0);
/***********************************/
/* copy input data to device */
/***********************************/
hipMemcpy(d_input, h_input, size*sizeof(float), hipMemcpyHostToDevice);
/*************************************/
/* call kernel */
/* 1 block, BLOCK_SIZE threads */
/*************************************/
work_efficient_scan<<<1,BLOCK_SIZE>>>(d_input, d_output,size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_output, d_output, sizeof(float)*size, hipMemcpyDeviceToHost);
/**/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
/*******************************************/
/* Print the final scan result */
/*******************************************/
printf("The final inclusive scan result:\n");
for(int i=0;i<size;++i)printf("%4.1f ",h_output[i]);
/* free device memory */
hipFree(d_input);
hipFree(d_output);
/* free host memory */
free(h_input);
free(h_output);
/**/
return 0;
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/* Thread block size = number of threads of a block*/
/* Notice: in this example, the input data size = BLOCK_SIZE */
/* (different with the CUDA Reduction assigment) */
#define BLOCK_SIZE 16
__global__ void work_efficient_scan(const float* input, float* output, int size)
{
/*Declare the shared memory*/
__shared__ float XY[BLOCK_SIZE];
/**/
unsigned int t = threadIdx.x;
/*load data from global memory to shared memory*/
XY[t] = input[t];
/*****************************************************************/
/* YOUR TODO-1 STARTS HERE */
/* Implement the Reduction step, */
/* (the final results is kept in the last element */
/*****************************************************************/
for(int stride = 1;stride<blockDim.x;stride*=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index < blockDim.x) XY[index]+=XY[index-stride];
}
/*************************************************************/
/* YOUR TODO-1 ENDS HERE */
/*************************************************************/
/*************************************************************/
/* YOUR TODO-2 STARTS HERE */
/* Implement the "post scan" step */
/* to finish the inclusive scan */
/*************************************************************/
for(int stride=size/4;stride>0;stride/=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index+stride < blockDim.x) XY[index+stride] += XY[index];
}
/*************************************************************/
/* YOUR TODO-2 ENDS HERE */
/*************************************************************/
__syncthreads();
/* write the final output to global memory */
output[t] = XY[t];
}
/**/
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/**/
float* h_input, *h_output;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
/* read the value of size from stdin*/
scanf("%d", &size);
/* Allocate host memory */
h_input = (float*) malloc(sizeof(float)*size);
h_output = (float*) malloc(sizeof(float)*size);
/* read input from stdin */
for(i=0;i<size*size;++i){ scanf("%f", &h_input[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
float* d_input, *d_output;
hipMalloc(&d_input,sizeof(float)*size);
hipMalloc(&d_output,sizeof(float)*size);
hipEventRecord(start,0);
/***********************************/
/* copy input data to device */
/***********************************/
hipMemcpy(d_input, h_input, size*sizeof(float), hipMemcpyHostToDevice);
/*************************************/
/* call kernel */
/* 1 block, BLOCK_SIZE threads */
/*************************************/
work_efficient_scan<<<1,BLOCK_SIZE>>>(d_input, d_output,size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_output, d_output, sizeof(float)*size, hipMemcpyDeviceToHost);
/**/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
/*******************************************/
/* Print the final scan result */
/*******************************************/
printf("The final inclusive scan result:\n");
for(int i=0;i<size;++i)printf("%4.1f ",h_output[i]);
/* free device memory */
hipFree(d_input);
hipFree(d_output);
/* free host memory */
free(h_input);
free(h_output);
/**/
return 0;
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19work_efficient_scanPKfPfi
.globl _Z19work_efficient_scanPKfPfi
.p2align 8
.type _Z19work_efficient_scanPKfPfi,@function
_Z19work_efficient_scanPKfPfi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v3, s[2:3]
s_and_b32 s2, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s2, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
s_cbranch_scc1 .LBB0_5
v_lshl_add_u32 v4, v0, 1, 2
s_mov_b32 s3, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s3, s2
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s3, -1
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_2
v_subrev_nc_u32_e32 v2, s3, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v2, 2, v2
ds_load_b32 v2, v2
ds_load_b32 v5, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 4
s_cbranch_scc1 .LBB0_10
v_lshl_add_u32 v4, v0, 1, 2
s_lshr_b32 s3, s3, 2
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_10
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s3, -1
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v2, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB0_7
v_lshlrev_b32_e32 v1, 2, v1
v_lshlrev_b32_e32 v2, 2, v2
ds_load_b32 v1, v1
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v5
ds_store_b32 v2, v1
s_branch .LBB0_7
.LBB0_10:
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v3
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19work_efficient_scanPKfPfi
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19work_efficient_scanPKfPfi, .Lfunc_end0-_Z19work_efficient_scanPKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19work_efficient_scanPKfPfi
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z19work_efficient_scanPKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/* Thread block size = number of threads of a block*/
/* Notice: in this example, the input data size = BLOCK_SIZE */
/* (different with the CUDA Reduction assigment) */
#define BLOCK_SIZE 16
__global__ void work_efficient_scan(const float* input, float* output, int size)
{
/*Declare the shared memory*/
__shared__ float XY[BLOCK_SIZE];
/**/
unsigned int t = threadIdx.x;
/*load data from global memory to shared memory*/
XY[t] = input[t];
/*****************************************************************/
/* YOUR TODO-1 STARTS HERE */
/* Implement the Reduction step, */
/* (the final results is kept in the last element */
/*****************************************************************/
for(int stride = 1;stride<blockDim.x;stride*=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index < blockDim.x) XY[index]+=XY[index-stride];
}
/*************************************************************/
/* YOUR TODO-1 ENDS HERE */
/*************************************************************/
/*************************************************************/
/* YOUR TODO-2 STARTS HERE */
/* Implement the "post scan" step */
/* to finish the inclusive scan */
/*************************************************************/
for(int stride=size/4;stride>0;stride/=2)
{
__syncthreads();
int index = (t+1)*stride*2-1;
if(index+stride < blockDim.x) XY[index+stride] += XY[index];
}
/*************************************************************/
/* YOUR TODO-2 ENDS HERE */
/*************************************************************/
__syncthreads();
/* write the final output to global memory */
output[t] = XY[t];
}
/**/
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/**/
float* h_input, *h_output;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
/* read the value of size from stdin*/
scanf("%d", &size);
/* Allocate host memory */
h_input = (float*) malloc(sizeof(float)*size);
h_output = (float*) malloc(sizeof(float)*size);
/* read input from stdin */
for(i=0;i<size*size;++i){ scanf("%f", &h_input[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
float* d_input, *d_output;
hipMalloc(&d_input,sizeof(float)*size);
hipMalloc(&d_output,sizeof(float)*size);
hipEventRecord(start,0);
/***********************************/
/* copy input data to device */
/***********************************/
hipMemcpy(d_input, h_input, size*sizeof(float), hipMemcpyHostToDevice);
/*************************************/
/* call kernel */
/* 1 block, BLOCK_SIZE threads */
/*************************************/
work_efficient_scan<<<1,BLOCK_SIZE>>>(d_input, d_output,size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_output, d_output, sizeof(float)*size, hipMemcpyDeviceToHost);
/**/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
/*******************************************/
/* Print the final scan result */
/*******************************************/
printf("The final inclusive scan result:\n");
for(int i=0;i<size;++i)printf("%4.1f ",h_output[i]);
/* free device memory */
hipFree(d_input);
hipFree(d_output);
/* free host memory */
free(h_input);
free(h_output);
/**/
return 0;
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.file "cudaScan.hip"
.globl _Z34__device_stub__work_efficient_scanPKfPfi # -- Begin function _Z34__device_stub__work_efficient_scanPKfPfi
.p2align 4, 0x90
.type _Z34__device_stub__work_efficient_scanPKfPfi,@function
_Z34__device_stub__work_efficient_scanPKfPfi: # @_Z34__device_stub__work_efficient_scanPKfPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19work_efficient_scanPKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__work_efficient_scanPKfPfi, .Lfunc_end0-_Z34__device_stub__work_efficient_scanPKfPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r12
leaq (,%r12,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
testq %r12, %r12
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %rbx, %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movl 4(%rsp), %r12d
movl %r12d, %eax
imull %eax, %eax
addq $4, %r15
cmpq %rax, %r13
jb .LBB1_2
.LBB1_3: # %._crit_edge
movslq %r12d, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %edx, 44(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19work_efficient_scanPKfPfi, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_10
# %bb.6: # %_Z14checkCUDAErrorPKc.exit
movq 16(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq stderr(%rip), %rdi
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_9
# %bb.7: # %.lr.ph19.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph19
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r15
movslq 4(%rsp), %rax
cmpq %rax, %r15
jl .LBB1_8
.LBB1_9: # %._crit_edge20
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB2_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14checkCUDAErrorPKc, .Lfunc_end2-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19work_efficient_scanPKfPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19work_efficient_scanPKfPfi,@object # @_Z19work_efficient_scanPKfPfi
.section .rodata,"a",@progbits
.globl _Z19work_efficient_scanPKfPfi
.p2align 3, 0x0
_Z19work_efficient_scanPKfPfi:
.quad _Z34__device_stub__work_efficient_scanPKfPfi
.size _Z19work_efficient_scanPKfPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel Invoking"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Elapsed time = %f (s)\n"
.size .L.str.3, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%4.1f "
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.6, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19work_efficient_scanPKfPfi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The final inclusive scan result:"
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__work_efficient_scanPKfPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19work_efficient_scanPKfPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19work_efficient_scanPKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fcc00078e0002 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff007435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fca00078e00ff */
/*0080*/ ISETP.LE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f03270 */
/*0090*/ ISETP.LE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fe20003f23070 */
/*00a0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041d80000004800 */
/*00b0*/ @!P1 BRA 0x190 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*00c0*/ LEA R0, R7, 0x2, 0x1 ; /* 0x0000000207007811 */
/* 0x000fe200078e08ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fc600078e00ff */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00f0*/ IMAD R6, R0, R3, -0x1 ; /* 0xffffffff00067424 */
/* 0x000fca00078e0203 */
/*0100*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f26070 */
/*0110*/ @!P1 IADD3 R2, R6, -R3, RZ ; /* 0x8000000306029210 */
/* 0x001fe20007ffe0ff */
/*0120*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x000fe200078e00ff */
/*0130*/ @!P1 LDS R4, [R6.X4] ; /* 0x0000000006049984 */
/* 0x000fe80000004800 */
/*0140*/ @!P1 LDS R5, [R2.X4] ; /* 0x0000000002059984 */
/* 0x000e240000004800 */
/*0150*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0160*/ @!P1 STS [R6.X4], R4 ; /* 0x0000000406009388 */
/* 0x0001e20000004800 */
/*0170*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x0], PT ; /* 0x0000000003007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @!P1 BRA 0xe0 ; /* 0xffffff5000009947 */
/* 0x001fea000383ffff */
/*0190*/ @!P0 BRA 0x2b0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*01b0*/ LEA R9, R7, 0x2, 0x1 ; /* 0x0000000207097811 */
/* 0x000fe200078e08ff */
/*01c0*/ USHF.R.U32.HI UR4, URZ, 0x2, UR4 ; /* 0x000000023f047899 */
/* 0x000fcc0008011604 */
/*01d0*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fc8000f8e00ff */
/*01e0*/ IMAD R5, R9, R0.reuse, -0x1 ; /* 0xffffffff09057424 */
/* 0x080fe200078e0200 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0200*/ IADD3 R2, R5, R0, RZ ; /* 0x0000000005027210 */
/* 0x001fc80007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x0], PT ; /* 0x0000000002007a0c */
/* 0x000fda0003f06070 */
/*0220*/ @!P0 IMAD.SHL.U32 R3, R5, 0x4, RZ ; /* 0x0000000405038824 */
/* 0x000fe400078e00ff */
/*0230*/ @!P0 LDS R5, [R5.X4] ; /* 0x0000000005058984 */
/* 0x000fe60000004800 */
/*0240*/ @!P0 LEA R3, R0, R3, 0x2 ; /* 0x0000000300038211 */
/* 0x000fe400078e10ff */
/*0250*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc60000011600 */
/*0260*/ @!P0 LDS R2, [R3] ; /* 0x0000000003028984 */
/* 0x000e240000000800 */
/*0270*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*0280*/ @!P0 STS [R3], R2 ; /* 0x0000000203008388 */
/* 0x0001e20000000800 */
/*0290*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*02a0*/ @P0 BRA 0x1e0 ; /* 0xffffff3000000947 */
/* 0x001fea000383ffff */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ LEA R2, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x001fc800078010ff */
/*02d0*/ LEA.HI.X R3, R7, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fe200000f14ff */
/*02e0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*02f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19work_efficient_scanPKfPfi
.globl _Z19work_efficient_scanPKfPfi
.p2align 8
.type _Z19work_efficient_scanPKfPfi,@function
_Z19work_efficient_scanPKfPfi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v3, s[2:3]
s_and_b32 s2, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s2, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
s_cbranch_scc1 .LBB0_5
v_lshl_add_u32 v4, v0, 1, 2
s_mov_b32 s3, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s3, s2
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s3, -1
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_2
v_subrev_nc_u32_e32 v2, s3, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v2, 2, v2
ds_load_b32 v2, v2
ds_load_b32 v5, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 4
s_cbranch_scc1 .LBB0_10
v_lshl_add_u32 v4, v0, 1, 2
s_lshr_b32 s3, s3, 2
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_10
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s3, -1
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v2, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB0_7
v_lshlrev_b32_e32 v1, 2, v1
v_lshlrev_b32_e32 v2, 2, v2
ds_load_b32 v1, v1
ds_load_b32 v5, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v5
ds_store_b32 v2, v1
s_branch .LBB0_7
.LBB0_10:
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v3
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19work_efficient_scanPKfPfi
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19work_efficient_scanPKfPfi, .Lfunc_end0-_Z19work_efficient_scanPKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19work_efficient_scanPKfPfi
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z19work_efficient_scanPKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ffcf2_00000000-6_cudaScan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi
.type _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi, @function
_Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19work_efficient_scanPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi, .-_Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi
.globl _Z19work_efficient_scanPKfPfi
.type _Z19work_efficient_scanPKfPfi, @function
_Z19work_efficient_scanPKfPfi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19work_efficient_scanPKfPfi, .-_Z19work_efficient_scanPKfPfi
.section .rodata.str1.1
.LC1:
.string "%d"
.LC2:
.string "%f"
.LC3:
.string "Kernel Invoking"
.LC4:
.string "Elapsed time = %f (s)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "The final inclusive scan result:\n"
.section .rodata.str1.1
.LC6:
.string "%4.1f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, 12(%rsp)
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %ebx
movslq %ebx, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
movl %ebx, %eax
imull %ebx, %eax
testl %eax, %eax
jle .L16
movq %r12, %r14
movl $0, %r13d
leaq .LC2(%rip), %r15
.L17:
movq %r14, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %r13d
movl 12(%rsp), %ebx
addq $4, %r14
movl %ebx, %eax
imull %ebx, %eax
cmpl %r13d, %eax
jg .L17
.L16:
movslq %ebx, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L18:
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKc
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L19
movl $0, %ebx
leaq .LC6(%rip), %r13
.L20:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 12(%rsp)
jg .L20
.L19:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl 12(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z43__device_stub__Z19work_efficient_scanPKfPfiPKfPfi
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z19work_efficient_scanPKfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19work_efficient_scanPKfPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaScan.hip"
.globl _Z34__device_stub__work_efficient_scanPKfPfi # -- Begin function _Z34__device_stub__work_efficient_scanPKfPfi
.p2align 4, 0x90
.type _Z34__device_stub__work_efficient_scanPKfPfi,@function
_Z34__device_stub__work_efficient_scanPKfPfi: # @_Z34__device_stub__work_efficient_scanPKfPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19work_efficient_scanPKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__work_efficient_scanPKfPfi, .Lfunc_end0-_Z34__device_stub__work_efficient_scanPKfPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r12
leaq (,%r12,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
testq %r12, %r12
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %rbx, %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movl 4(%rsp), %r12d
movl %r12d, %eax
imull %eax, %eax
addq $4, %r15
cmpq %rax, %r13
jb .LBB1_2
.LBB1_3: # %._crit_edge
movslq %r12d, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %edx, 44(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19work_efficient_scanPKfPfi, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_10
# %bb.6: # %_Z14checkCUDAErrorPKc.exit
movq 16(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq stderr(%rip), %rdi
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_9
# %bb.7: # %.lr.ph19.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # %.lr.ph19
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r15
movslq 4(%rsp), %rax
cmpq %rax, %r15
jl .LBB1_8
.LBB1_9: # %._crit_edge20
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB2_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14checkCUDAErrorPKc, .Lfunc_end2-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19work_efficient_scanPKfPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19work_efficient_scanPKfPfi,@object # @_Z19work_efficient_scanPKfPfi
.section .rodata,"a",@progbits
.globl _Z19work_efficient_scanPKfPfi
.p2align 3, 0x0
_Z19work_efficient_scanPKfPfi:
.quad _Z34__device_stub__work_efficient_scanPKfPfi
.size _Z19work_efficient_scanPKfPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel Invoking"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Elapsed time = %f (s)\n"
.size .L.str.3, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%4.1f "
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.6, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19work_efficient_scanPKfPfi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The final inclusive scan result:"
.size .Lstr, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__work_efficient_scanPKfPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19work_efficient_scanPKfPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void init(int n, float *x, float *y) {
int lane_id = threadIdx.x & 31;
size_t warp_id = (threadIdx.x + blockIdx.x * blockDim.x) >> 5;
size_t warps_per_grid = (blockDim.x * gridDim.x) >> 5;
size_t warp_total = ((sizeof(float)*n) + STRIDE_64K-1) / STRIDE_64K;
if(blockIdx.x==0 && threadIdx.x==0) {
//printf("\n TId[%d] ", threadIdx.x);
//printf(" WId[%u] ", warp_id);
//printf(" LId[%u] ", lane_id);
//printf(" WperG[%u] ", warps_per_grid);
//printf(" wTot[%u] ", warp_total);
//printf(" rep[%d] ", STRIDE_64K/sizeof(float)/32);
}
for(; warp_id < warp_total; warp_id += warps_per_grid) {
#pragma unroll
for(int rep = 0; rep < STRIDE_64K/sizeof(float)/32; rep++) {
size_t ind = warp_id * STRIDE_64K/sizeof(float) + rep * 32 + lane_id;
if (ind < n) {
x[ind] = 1.0f;
//if(blockIdx.x==0 && threadIdx.x==0) {
// printf(" \nind[%d] ", ind);
//}
y[ind] = 2.0f;
}
}
}
} | .file "tmpxft_00156cb7_00000000-6_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4initiPfS_iPfS_
.type _Z26__device_stub__Z4initiPfS_iPfS_, @function
_Z26__device_stub__Z4initiPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4initiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4initiPfS_iPfS_, .-_Z26__device_stub__Z4initiPfS_iPfS_
.globl _Z4initiPfS_
.type _Z4initiPfS_, @function
_Z4initiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4initiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4initiPfS_, .-_Z4initiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4initiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void init(int n, float *x, float *y) {
int lane_id = threadIdx.x & 31;
size_t warp_id = (threadIdx.x + blockIdx.x * blockDim.x) >> 5;
size_t warps_per_grid = (blockDim.x * gridDim.x) >> 5;
size_t warp_total = ((sizeof(float)*n) + STRIDE_64K-1) / STRIDE_64K;
if(blockIdx.x==0 && threadIdx.x==0) {
//printf("\n TId[%d] ", threadIdx.x);
//printf(" WId[%u] ", warp_id);
//printf(" LId[%u] ", lane_id);
//printf(" WperG[%u] ", warps_per_grid);
//printf(" wTot[%u] ", warp_total);
//printf(" rep[%d] ", STRIDE_64K/sizeof(float)/32);
}
for(; warp_id < warp_total; warp_id += warps_per_grid) {
#pragma unroll
for(int rep = 0; rep < STRIDE_64K/sizeof(float)/32; rep++) {
size_t ind = warp_id * STRIDE_64K/sizeof(float) + rep * 32 + lane_id;
if (ind < n) {
x[ind] = 1.0f;
//if(blockIdx.x==0 && threadIdx.x==0) {
// printf(" \nind[%d] ", ind);
//}
y[ind] = 2.0f;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init(int n, float *x, float *y) {
int lane_id = threadIdx.x & 31;
size_t warp_id = (threadIdx.x + blockIdx.x * blockDim.x) >> 5;
size_t warps_per_grid = (blockDim.x * gridDim.x) >> 5;
size_t warp_total = ((sizeof(float)*n) + STRIDE_64K-1) / STRIDE_64K;
if(blockIdx.x==0 && threadIdx.x==0) {
//printf("\n TId[%d] ", threadIdx.x);
//printf(" WId[%u] ", warp_id);
//printf(" LId[%u] ", lane_id);
//printf(" WperG[%u] ", warps_per_grid);
//printf(" wTot[%u] ", warp_total);
//printf(" rep[%d] ", STRIDE_64K/sizeof(float)/32);
}
for(; warp_id < warp_total; warp_id += warps_per_grid) {
#pragma unroll
for(int rep = 0; rep < STRIDE_64K/sizeof(float)/32; rep++) {
size_t ind = warp_id * STRIDE_64K/sizeof(float) + rep * 32 + lane_id;
if (ind < n) {
x[ind] = 1.0f;
//if(blockIdx.x==0 && threadIdx.x==0) {
// printf(" \nind[%d] ", ind);
//}
y[ind] = 2.0f;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init(int n, float *x, float *y) {
int lane_id = threadIdx.x & 31;
size_t warp_id = (threadIdx.x + blockIdx.x * blockDim.x) >> 5;
size_t warps_per_grid = (blockDim.x * gridDim.x) >> 5;
size_t warp_total = ((sizeof(float)*n) + STRIDE_64K-1) / STRIDE_64K;
if(blockIdx.x==0 && threadIdx.x==0) {
//printf("\n TId[%d] ", threadIdx.x);
//printf(" WId[%u] ", warp_id);
//printf(" LId[%u] ", lane_id);
//printf(" WperG[%u] ", warps_per_grid);
//printf(" wTot[%u] ", warp_total);
//printf(" rep[%d] ", STRIDE_64K/sizeof(float)/32);
}
for(; warp_id < warp_total; warp_id += warps_per_grid) {
#pragma unroll
for(int rep = 0; rep < STRIDE_64K/sizeof(float)/32; rep++) {
size_t ind = warp_id * STRIDE_64K/sizeof(float) + rep * 32 + lane_id;
if (ind < n) {
x[ind] = 1.0f;
//if(blockIdx.x==0 && threadIdx.x==0) {
// printf(" \nind[%d] ", ind);
//}
y[ind] = 2.0f;
}
}
}
} | .text
.file "init.hip"
.globl _Z19__device_stub__initiPfS_ # -- Begin function _Z19__device_stub__initiPfS_
.p2align 4, 0x90
.type _Z19__device_stub__initiPfS_,@function
_Z19__device_stub__initiPfS_: # @_Z19__device_stub__initiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4initiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__initiPfS_, .Lfunc_end0-_Z19__device_stub__initiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initiPfS_,@object # @_Z4initiPfS_
.section .rodata,"a",@progbits
.globl _Z4initiPfS_
.p2align 3, 0x0
_Z4initiPfS_:
.quad _Z19__device_stub__initiPfS_
.size _Z4initiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4initiPfS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00156cb7_00000000-6_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4initiPfS_iPfS_
.type _Z26__device_stub__Z4initiPfS_iPfS_, @function
_Z26__device_stub__Z4initiPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4initiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4initiPfS_iPfS_, .-_Z26__device_stub__Z4initiPfS_iPfS_
.globl _Z4initiPfS_
.type _Z4initiPfS_, @function
_Z4initiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4initiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4initiPfS_, .-_Z4initiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4initiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "init.hip"
.globl _Z19__device_stub__initiPfS_ # -- Begin function _Z19__device_stub__initiPfS_
.p2align 4, 0x90
.type _Z19__device_stub__initiPfS_,@function
_Z19__device_stub__initiPfS_: # @_Z19__device_stub__initiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4initiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__initiPfS_, .Lfunc_end0-_Z19__device_stub__initiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initiPfS_,@object # @_Z4initiPfS_
.section .rodata,"a",@progbits
.globl _Z4initiPfS_
.p2align 3, 0x0
_Z4initiPfS_:
.quad _Z19__device_stub__initiPfS_
.size _Z4initiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4initiPfS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__
void dummy() {}
extern "C"
__global__
void vecSub(int *l, int *r, int *p, size_t N, size_t iter) {
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
for (size_t i = 0; i < iter; ++i) {
if (idx < N) {
p[idx] = l[idx] - r[idx];
}
}
} | code for sm_80
Function : vecSub
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fc60003f05070 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f05300 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fe400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ IADD3 R2, P1, R8, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x000fe20007f3e0ff */
/*00b0*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00c0*/ SHF.R.U32.HI R7, RZ, 0x1e, R0 ; /* 0x0000001eff077819 */
/* 0x000fe40000011600 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00e0*/ IADD3.X R3, R3, -0x1, RZ, P1, !PT ; /* 0xffffffff03037810 */
/* 0x000fc40000ffe4ff */
/*00f0*/ IADD3 R2, P3, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006027a10 */
/* 0x040fe40007f7e0ff */
/*0100*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*0110*/ IADD3 R4, P2, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f5e0ff */
/*0120*/ IADD3 R6, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe40007f3e0ff */
/*0130*/ IADD3.X R3, R7.reuse, c[0x0][0x164], RZ, P3, !PT ; /* 0x0000590007037a10 */
/* 0x040fe40001ffe4ff */
/*0140*/ IADD3.X R5, R7, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0007057a10 */
/* 0x000fc400017fe4ff */
/*0150*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe40000ffe4ff */
/*0160*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*0170*/ @!P0 BRA 0xbc0 ; /* 0x00000a4000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R9, P0, R8, -c[0x0][0x180], RZ ; /* 0x8000600008097a10 */
/* 0x000fca0007f1e0ff */
/*0190*/ IMAD.X R10, RZ, RZ, ~c[0x0][0x184], P0 ; /* 0x80006100ff0a7624 */
/* 0x000fca00000e06ff */
/*01a0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*01b0*/ @P0 BRA 0xa50 ; /* 0x0000089000000947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R11, P0, RZ, -R9, RZ ; /* 0x80000009ff0b7210 */
/* 0x000fc80007f1e0ff */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f24070 */
/*01e0*/ IMAD.X R11, RZ, RZ, ~R10, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e0e0a */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0200*/ ISETP.GT.AND.EX P1, PT, R11, RZ, PT, P1 ; /* 0x000000ff0b00720c */
/* 0x000fda0003f24310 */
/*0210*/ @!P1 BRA 0x730 ; /* 0x0000051000009947 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.GE.U32.AND P1, PT, R0.reuse, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x040fe40003f26070 */
/*0230*/ ISETP.GE.U32.AND P2, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f46070 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0250*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P1 ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f26110 */
/*0260*/ ISETP.GE.U32.AND.EX P2, PT, RZ, c[0x0][0x17c], PT, P2 ; /* 0x00005f00ff007a0c */
/* 0x000fd60003f46120 */
/*0270*/ @!P1 LDG.E R11, [R2.64] ; /* 0x00000004020b9981 */
/* 0x001ea8000c1e1900 */
/*0280*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea4000c1e1900 */
/*0290*/ @!P1 IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b9824 */
/* 0x004fca00078e0a0c */
/*02a0*/ @!P1 STG.E [R6.64], R11 ; /* 0x0000000b06009986 */
/* 0x0001e8000c101904 */
/*02b0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ @!P1 LDG.E R13, [R2.64] ; /* 0x00000004020d9981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ @!P1 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d9824 */
/* 0x004fca00078e0a0c */
/*02e0*/ @!P1 STG.E [R6.64], R13 ; /* 0x0000000d06009986 */
/* 0x0001e8000c101904 */
/*02f0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0300*/ @!P1 LDG.E R15, [R2.64] ; /* 0x00000004020f9981 */
/* 0x000ea4000c1e1900 */
/*0310*/ @!P1 IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f9824 */
/* 0x004fca00078e0a0c */
/*0320*/ @!P1 STG.E [R6.64], R15 ; /* 0x0000000f06009986 */
/* 0x0001e8000c101904 */
/*0330*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0340*/ @!P1 LDG.E R17, [R2.64] ; /* 0x0000000402119981 */
/* 0x000ea2000c1e1900 */
/*0350*/ BSSY B0, 0x4b0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0360*/ @!P1 IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111119824 */
/* 0x004fca00078e0a0c */
/*0370*/ @!P1 STG.E [R6.64], R17 ; /* 0x0000001106009986 */
/* 0x0001e2000c101904 */
/*0380*/ PLOP3.LUT P1, PT, P2, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda000172f070 */
/*0390*/ @P1 BRA 0x4a0 ; /* 0x0000010000001947 */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x001ea8000c1e1900 */
/*03b0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b7824 */
/* 0x004fca00078e0a0c */
/*03d0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*03e0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0400*/ IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d7824 */
/* 0x004fca00078e0a0c */
/*0410*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0420*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*0440*/ IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f7824 */
/* 0x004fca00078e0a0c */
/*0450*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0460*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea4000c1e1900 */
/*0480*/ IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111117824 */
/* 0x004fca00078e0a0c */
/*0490*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e4000c101904 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*04b0*/ BSSY B0, 0x5e0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*04c0*/ @P1 BRA 0x5d0 ; /* 0x0000010000001947 */
/* 0x000fea0003800000 */
/*04d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b7824 */
/* 0x004fca00078e0a0c */
/*0500*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0510*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0520*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0530*/ IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d7824 */
/* 0x004fca00078e0a0c */
/*0540*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0550*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*0570*/ IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f7824 */
/* 0x004fca00078e0a0c */
/*0580*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0590*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea4000c1e1900 */
/*05b0*/ IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111117824 */
/* 0x004fca00078e0a0c */
/*05c0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e4000c101904 */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05e0*/ @!P1 LDG.E R11, [R2.64] ; /* 0x00000004020b9981 */
/* 0x001ea8000c1e1900 */
/*05f0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea4000c1e1900 */
/*0600*/ @!P1 IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b9824 */
/* 0x004fca00078e0a0c */
/*0610*/ @!P1 STG.E [R6.64], R11 ; /* 0x0000000b06009986 */
/* 0x0001e8000c101904 */
/*0620*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0630*/ @!P1 LDG.E R13, [R2.64] ; /* 0x00000004020d9981 */
/* 0x000ea4000c1e1900 */
/*0640*/ @!P1 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d9824 */
/* 0x004fca00078e0a0c */
/*0650*/ @!P1 STG.E [R6.64], R13 ; /* 0x0000000d06009986 */
/* 0x0001e8000c101904 */
/*0660*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0670*/ @!P1 LDG.E R15, [R2.64] ; /* 0x00000004020f9981 */
/* 0x000ea4000c1e1900 */
/*0680*/ @!P1 IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f9824 */
/* 0x004fca00078e0a0c */
/*0690*/ @!P1 STG.E [R6.64], R15 ; /* 0x0000000f06009986 */
/* 0x0001e8000c101904 */
/*06a0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ @!P1 LDG.E R17, [R2.64] ; /* 0x0000000402119981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IADD3 R9, P3, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fca0007f7e0ff */
/*06d0*/ IMAD.X R10, RZ, RZ, R10, P3 ; /* 0x000000ffff0a7224 */
/* 0x000fe200018e060a */
/*06e0*/ ISETP.GE.U32.AND P3, PT, R9, -0xc, PT ; /* 0xfffffff40900780c */
/* 0x000fc80003f66070 */
/*06f0*/ ISETP.GE.AND.EX P3, PT, R10, -0x1, PT, P3 ; /* 0xffffffff0a00780c */
/* 0x000fe20003f66330 */
/*0700*/ @!P1 IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111119824 */
/* 0x004fca00078e0a0c */
/*0710*/ @!P1 STG.E [R6.64], R17 ; /* 0x0000001106009986 */
/* 0x0001ee000c101904 */
/*0720*/ @!P3 BRA 0x270 ; /* 0xfffffb400000b947 */
/* 0x000fea000383ffff */
/*0730*/ IADD3 R11, P2, RZ, -R9, RZ ; /* 0x80000009ff0b7210 */
/* 0x001fc80007f5e0ff */
/*0740*/ ISETP.GT.U32.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fe20003f24070 */
/*0750*/ IMAD.X R11, RZ, RZ, ~R10, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fca00010e0e0a */
/*0760*/ ISETP.GT.AND.EX P1, PT, R11, RZ, PT, P1 ; /* 0x000000ff0b00720c */
/* 0x000fda0003f24310 */
/*0770*/ @!P1 BRA 0xa20 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0790*/ BSSY B0, 0x8d0 ; /* 0x0000013000007945 */
/* 0x000fe60003800000 */
/*07a0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*07b0*/ @P0 BRA 0x8c0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b7824 */
/* 0x004fca00078e0a0c */
/*07f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0800*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0820*/ IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d7824 */
/* 0x004fca00078e0a0c */
/*0830*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*0860*/ IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f7824 */
/* 0x004fca00078e0a0c */
/*0870*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0880*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111117824 */
/* 0x004fca00078e0a0c */
/*08b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e4000c101904 */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x001ea8000c1e1900 */
/*08e0*/ @!P0 LDG.E R12, [R4.64] ; /* 0x00000004040c8981 */
/* 0x000ea4000c1e1900 */
/*08f0*/ @!P0 IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b8824 */
/* 0x004fca00078e0a0c */
/*0900*/ @!P0 STG.E [R6.64], R11 ; /* 0x0000000b06008986 */
/* 0x0001e8000c101904 */
/*0910*/ @!P0 LDG.E R12, [R4.64] ; /* 0x00000004040c8981 */
/* 0x000ea8000c1e1900 */
/*0920*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000004020d8981 */
/* 0x000ea4000c1e1900 */
/*0930*/ @!P0 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d8824 */
/* 0x004fca00078e0a0c */
/*0940*/ @!P0 STG.E [R6.64], R13 ; /* 0x0000000d06008986 */
/* 0x0001e8000c101904 */
/*0950*/ @!P0 LDG.E R12, [R4.64] ; /* 0x00000004040c8981 */
/* 0x000ea8000c1e1900 */
/*0960*/ @!P0 LDG.E R15, [R2.64] ; /* 0x00000004020f8981 */
/* 0x000ea4000c1e1900 */
/*0970*/ @!P0 IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f8824 */
/* 0x004fca00078e0a0c */
/*0980*/ @!P0 STG.E [R6.64], R15 ; /* 0x0000000f06008986 */
/* 0x0001e8000c101904 */
/*0990*/ @!P0 LDG.E R12, [R4.64] ; /* 0x00000004040c8981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ @!P0 LDG.E R17, [R2.64] ; /* 0x0000000402118981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc80007f3e0ff */
/*09c0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f5e0ff */
/*09d0*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e060a */
/*09e0*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400010e060a */
/*09f0*/ @!P0 IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111118824 */
/* 0x004fca00078e0a0c */
/*0a00*/ @!P0 STG.E [R6.64], R17 ; /* 0x0000001106008986 */
/* 0x0001e2000c101904 */
/*0a10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*0a20*/ ISETP.NE.U32.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f25070 */
/*0a30*/ ISETP.NE.OR.EX P0, PT, R10, RZ, P0, P1 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705710 */
/*0a40*/ @!P0 BRA 0xbc0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0a60*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f26100 */
/*0a70*/ @!P1 LDG.E R11, [R2.64] ; /* 0x00000004020b9981 */
/* 0x001ea8000c1e1900 */
/*0a80*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea4000c1e1900 */
/*0a90*/ @!P1 IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b9824 */
/* 0x004fca00078e0a0c */
/*0aa0*/ @!P1 STG.E [R6.64], R11 ; /* 0x0000000b06009986 */
/* 0x0001e8000c101904 */
/*0ab0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0ac0*/ @!P1 LDG.E R13, [R2.64] ; /* 0x00000004020d9981 */
/* 0x000ea4000c1e1900 */
/*0ad0*/ @!P1 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d9824 */
/* 0x004fca00078e0a0c */
/*0ae0*/ @!P1 STG.E [R6.64], R13 ; /* 0x0000000d06009986 */
/* 0x0001e8000c101904 */
/*0af0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0b00*/ @!P1 LDG.E R15, [R2.64] ; /* 0x00000004020f9981 */
/* 0x000ea4000c1e1900 */
/*0b10*/ @!P1 IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f9824 */
/* 0x004fca00078e0a0c */
/*0b20*/ @!P1 STG.E [R6.64], R15 ; /* 0x0000000f06009986 */
/* 0x0001e8000c101904 */
/*0b30*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0b40*/ @!P1 LDG.E R17, [R2.64] ; /* 0x0000000402119981 */
/* 0x000ea2000c1e1900 */
/*0b50*/ IADD3 R9, P0, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fca0007f1e0ff */
/*0b60*/ IMAD.X R10, RZ, RZ, R10, P0 ; /* 0x000000ffff0a7224 */
/* 0x000fe200000e060a */
/*0b70*/ ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f05070 */
/*0b80*/ ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05300 */
/*0b90*/ @!P1 IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111119824 */
/* 0x004fca00078e0a0c */
/*0ba0*/ @!P1 STG.E [R6.64], R17 ; /* 0x0000001106009986 */
/* 0x0001ee000c101904 */
/*0bb0*/ @P0 BRA 0xa70 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*0bd0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0be0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0bf0*/ IADD3 R8, P1, RZ, -R8, RZ ; /* 0x80000008ff087210 */
/* 0x000fe40007f3e0ff */
/*0c00*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc60003f06070 */
/*0c10*/ IMAD.X R10, RZ, RZ, -0x1, P1 ; /* 0xffffffffff0a7424 */
/* 0x000fe200008e06ff */
/*0c20*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0c30*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea8000c1e1900 */
/*0c40*/ @!P0 LDG.E R9, [R4.64] ; /* 0x0000000404098981 */
/* 0x002ea2000c1e1900 */
/*0c50*/ IADD3 R8, P1, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fca0007f3e0ff */
/*0c60*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*0c70*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f25070 */
/*0c80*/ ISETP.NE.AND.EX P1, PT, R10, RZ, PT, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25310 */
/*0c90*/ @!P0 IMAD.IADD R9, R0, 0x1, -R9 ; /* 0x0000000100098824 */
/* 0x004fca00078e0a09 */
/*0ca0*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0003ee000c101904 */
/*0cb0*/ @P1 BRA 0xc30 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*0cc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : dummy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__
void dummy() {}
extern "C"
__global__
void vecSub(int *l, int *r, int *p, size_t N, size_t iter) {
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
for (size_t i = 0; i < iter; ++i) {
if (idx < N) {
p[idx] = l[idx] - r[idx];
}
}
} | .file "tmpxft_0013eb8d_00000000-6_vecSub.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5dummyvv
.type _Z23__device_stub__Z5dummyvv, @function
_Z23__device_stub__Z5dummyvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq dummy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z5dummyvv, .-_Z23__device_stub__Z5dummyvv
.globl dummy
.type dummy, @function
dummy:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5dummyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size dummy, .-dummy
.globl _Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm
.type _Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm, @function
_Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq vecSub(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm, .-_Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm
.globl vecSub
.type vecSub, @function
vecSub:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size vecSub, .-vecSub
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vecSub"
.LC1:
.string "dummy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vecSub(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq dummy(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__
void dummy() {}
extern "C"
__global__
void vecSub(int *l, int *r, int *p, size_t N, size_t iter) {
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
for (size_t i = 0; i < iter; ++i) {
if (idx < N) {
p[idx] = l[idx] - r[idx];
}
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__
void dummy() {}
extern "C"
__global__
void vecSub(int *l, int *r, int *p, size_t N, size_t iter) {
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
for (size_t i = 0; i < iter; ++i) {
if (idx < N) {
p[idx] = l[idx] - r[idx];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void dummy() {}
extern "C"
__global__
void vecSub(int *l, int *r, int *p, size_t N, size_t iter) {
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
for (size_t i = 0; i < iter; ++i) {
if (idx < N) {
p[idx] = l[idx] - r[idx];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected dummy
.globl dummy
.p2align 8
.type dummy,@function
dummy:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel dummy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size dummy, .Lfunc_end0-dummy
.section .AMDGPU.csdata,"",@progbits
.text
.protected vecSub
.globl vecSub
.p2align 8
.type vecSub,@function
vecSub:
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc1 .LBB1_5
s_clause 0x1
s_load_b32 s12, s[0:1], 0x34
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s12, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s4, v4
v_add_co_ci_u32_e64 v1, s0, s5, v5, s0
v_add_co_u32 v2, s0, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s7, v5, s0
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc1 .LBB1_5
.LBB1_3:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_2
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
s_branch .LBB1_2
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vecSub
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size vecSub, .Lfunc_end1-vecSub
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: dummy
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: dummy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vecSub
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vecSub.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void dummy() {}
extern "C"
__global__
void vecSub(int *l, int *r, int *p, size_t N, size_t iter) {
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
for (size_t i = 0; i < iter; ++i) {
if (idx < N) {
p[idx] = l[idx] - r[idx];
}
}
} | .text
.file "vecSub.hip"
.globl __device_stub__dummy # -- Begin function __device_stub__dummy
.p2align 4, 0x90
.type __device_stub__dummy,@function
__device_stub__dummy: # @__device_stub__dummy
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $dummy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size __device_stub__dummy, .Lfunc_end0-__device_stub__dummy
.cfi_endproc
# -- End function
.globl __device_stub__vecSub # -- Begin function __device_stub__vecSub
.p2align 4, 0x90
.type __device_stub__vecSub,@function
__device_stub__vecSub: # @__device_stub__vecSub
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $vecSub, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size __device_stub__vecSub, .Lfunc_end1-__device_stub__vecSub
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $dummy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vecSub, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type dummy,@object # @dummy
.section .rodata,"a",@progbits
.globl dummy
.p2align 3, 0x0
dummy:
.quad __device_stub__dummy
.size dummy, 8
.type vecSub,@object # @vecSub
.globl vecSub
.p2align 3, 0x0
vecSub:
.quad __device_stub__vecSub
.size vecSub, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "dummy"
.size .L__unnamed_1, 6
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "vecSub"
.size .L__unnamed_2, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__dummy
.addrsig_sym __device_stub__vecSub
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dummy
.addrsig_sym vecSub
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : vecSub
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fc60003f05070 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f05300 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fe400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ IADD3 R2, P1, R8, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x000fe20007f3e0ff */
/*00b0*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00c0*/ SHF.R.U32.HI R7, RZ, 0x1e, R0 ; /* 0x0000001eff077819 */
/* 0x000fe40000011600 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00e0*/ IADD3.X R3, R3, -0x1, RZ, P1, !PT ; /* 0xffffffff03037810 */
/* 0x000fc40000ffe4ff */
/*00f0*/ IADD3 R2, P3, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006027a10 */
/* 0x040fe40007f7e0ff */
/*0100*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*0110*/ IADD3 R4, P2, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f5e0ff */
/*0120*/ IADD3 R6, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe40007f3e0ff */
/*0130*/ IADD3.X R3, R7.reuse, c[0x0][0x164], RZ, P3, !PT ; /* 0x0000590007037a10 */
/* 0x040fe40001ffe4ff */
/*0140*/ IADD3.X R5, R7, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0007057a10 */
/* 0x000fc400017fe4ff */
/*0150*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe40000ffe4ff */
/*0160*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*0170*/ @!P0 BRA 0xbc0 ; /* 0x00000a4000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R9, P0, R8, -c[0x0][0x180], RZ ; /* 0x8000600008097a10 */
/* 0x000fca0007f1e0ff */
/*0190*/ IMAD.X R10, RZ, RZ, ~c[0x0][0x184], P0 ; /* 0x80006100ff0a7624 */
/* 0x000fca00000e06ff */
/*01a0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*01b0*/ @P0 BRA 0xa50 ; /* 0x0000089000000947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R11, P0, RZ, -R9, RZ ; /* 0x80000009ff0b7210 */
/* 0x000fc80007f1e0ff */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f24070 */
/*01e0*/ IMAD.X R11, RZ, RZ, ~R10, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e0e0a */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0200*/ ISETP.GT.AND.EX P1, PT, R11, RZ, PT, P1 ; /* 0x000000ff0b00720c */
/* 0x000fda0003f24310 */
/*0210*/ @!P1 BRA 0x730 ; /* 0x0000051000009947 */
/* 0x000fea0003800000 */
/*0220*/ ISETP.GE.U32.AND P1, PT, R0.reuse, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x040fe40003f26070 */
/*0230*/ ISETP.GE.U32.AND P2, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f46070 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0250*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P1 ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f26110 */
/*0260*/ ISETP.GE.U32.AND.EX P2, PT, RZ, c[0x0][0x17c], PT, P2 ; /* 0x00005f00ff007a0c */
/* 0x000fd60003f46120 */
/*0270*/ @!P1 LDG.E R11, [R2.64] ; /* 0x00000004020b9981 */
/* 0x001ea8000c1e1900 */
/*0280*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea4000c1e1900 */
/*0290*/ @!P1 IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b9824 */
/* 0x004fca00078e0a0c */
/*02a0*/ @!P1 STG.E [R6.64], R11 ; /* 0x0000000b06009986 */
/* 0x0001e8000c101904 */
/*02b0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ @!P1 LDG.E R13, [R2.64] ; /* 0x00000004020d9981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ @!P1 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d9824 */
/* 0x004fca00078e0a0c */
/*02e0*/ @!P1 STG.E [R6.64], R13 ; /* 0x0000000d06009986 */
/* 0x0001e8000c101904 */
/*02f0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0300*/ @!P1 LDG.E R15, [R2.64] ; /* 0x00000004020f9981 */
/* 0x000ea4000c1e1900 */
/*0310*/ @!P1 IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f9824 */
/* 0x004fca00078e0a0c */
/*0320*/ @!P1 STG.E [R6.64], R15 ; /* 0x0000000f06009986 */
/* 0x0001e8000c101904 */
/*0330*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0340*/ @!P1 LDG.E R17, [R2.64] ; /* 0x0000000402119981 */
/* 0x000ea2000c1e1900 */
/*0350*/ BSSY B0, 0x4b0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0360*/ @!P1 IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111119824 */
/* 0x004fca00078e0a0c */
/*0370*/ @!P1 STG.E [R6.64], R17 ; /* 0x0000001106009986 */
/* 0x0001e2000c101904 */
/*0380*/ PLOP3.LUT P1, PT, P2, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda000172f070 */
/*0390*/ @P1 BRA 0x4a0 ; /* 0x0000010000001947 */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x001ea8000c1e1900 */
/*03b0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b7824 */
/* 0x004fca00078e0a0c */
/*03d0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*03e0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0400*/ IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d7824 */
/* 0x004fca00078e0a0c */
/*0410*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0420*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*0440*/ IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f7824 */
/* 0x004fca00078e0a0c */
/*0450*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0460*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea4000c1e1900 */
/*0480*/ IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111117824 */
/* 0x004fca00078e0a0c */
/*0490*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e4000c101904 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*04b0*/ BSSY B0, 0x5e0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*04c0*/ @P1 BRA 0x5d0 ; /* 0x0000010000001947 */
/* 0x000fea0003800000 */
/*04d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b7824 */
/* 0x004fca00078e0a0c */
/*0500*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0510*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0520*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0530*/ IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d7824 */
/* 0x004fca00078e0a0c */
/*0540*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0550*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*0570*/ IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f7824 */
/* 0x004fca00078e0a0c */
/*0580*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0590*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea4000c1e1900 */
/*05b0*/ IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111117824 */
/* 0x004fca00078e0a0c */
/*05c0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e4000c101904 */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05e0*/ @!P1 LDG.E R11, [R2.64] ; /* 0x00000004020b9981 */
/* 0x001ea8000c1e1900 */
/*05f0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea4000c1e1900 */
/*0600*/ @!P1 IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b9824 */
/* 0x004fca00078e0a0c */
/*0610*/ @!P1 STG.E [R6.64], R11 ; /* 0x0000000b06009986 */
/* 0x0001e8000c101904 */
/*0620*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0630*/ @!P1 LDG.E R13, [R2.64] ; /* 0x00000004020d9981 */
/* 0x000ea4000c1e1900 */
/*0640*/ @!P1 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d9824 */
/* 0x004fca00078e0a0c */
/*0650*/ @!P1 STG.E [R6.64], R13 ; /* 0x0000000d06009986 */
/* 0x0001e8000c101904 */
/*0660*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0670*/ @!P1 LDG.E R15, [R2.64] ; /* 0x00000004020f9981 */
/* 0x000ea4000c1e1900 */
/*0680*/ @!P1 IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f9824 */
/* 0x004fca00078e0a0c */
/*0690*/ @!P1 STG.E [R6.64], R15 ; /* 0x0000000f06009986 */
/* 0x0001e8000c101904 */
/*06a0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ @!P1 LDG.E R17, [R2.64] ; /* 0x0000000402119981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IADD3 R9, P3, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fca0007f7e0ff */
/*06d0*/ IMAD.X R10, RZ, RZ, R10, P3 ; /* 0x000000ffff0a7224 */
/* 0x000fe200018e060a */
/*06e0*/ ISETP.GE.U32.AND P3, PT, R9, -0xc, PT ; /* 0xfffffff40900780c */
/* 0x000fc80003f66070 */
/*06f0*/ ISETP.GE.AND.EX P3, PT, R10, -0x1, PT, P3 ; /* 0xffffffff0a00780c */
/* 0x000fe20003f66330 */
/*0700*/ @!P1 IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111119824 */
/* 0x004fca00078e0a0c */
/*0710*/ @!P1 STG.E [R6.64], R17 ; /* 0x0000001106009986 */
/* 0x0001ee000c101904 */
/*0720*/ @!P3 BRA 0x270 ; /* 0xfffffb400000b947 */
/* 0x000fea000383ffff */
/*0730*/ IADD3 R11, P2, RZ, -R9, RZ ; /* 0x80000009ff0b7210 */
/* 0x001fc80007f5e0ff */
/*0740*/ ISETP.GT.U32.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fe20003f24070 */
/*0750*/ IMAD.X R11, RZ, RZ, ~R10, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fca00010e0e0a */
/*0760*/ ISETP.GT.AND.EX P1, PT, R11, RZ, PT, P1 ; /* 0x000000ff0b00720c */
/* 0x000fda0003f24310 */
/*0770*/ @!P1 BRA 0xa20 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0790*/ BSSY B0, 0x8d0 ; /* 0x0000013000007945 */
/* 0x000fe60003800000 */
/*07a0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*07b0*/ @P0 BRA 0x8c0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b7824 */
/* 0x004fca00078e0a0c */
/*07f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0800*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0820*/ IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d7824 */
/* 0x004fca00078e0a0c */
/*0830*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*0860*/ IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f7824 */
/* 0x004fca00078e0a0c */
/*0870*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0880*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111117824 */
/* 0x004fca00078e0a0c */
/*08b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e4000c101904 */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ @!P0 LDG.E R11, [R2.64] ; /* 0x00000004020b8981 */
/* 0x001ea8000c1e1900 */
/*08e0*/ @!P0 LDG.E R12, [R4.64] ; /* 0x00000004040c8981 */
/* 0x000ea4000c1e1900 */
/*08f0*/ @!P0 IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b8824 */
/* 0x004fca00078e0a0c */
/*0900*/ @!P0 STG.E [R6.64], R11 ; /* 0x0000000b06008986 */
/* 0x0001e8000c101904 */
/*0910*/ @!P0 LDG.E R12, [R4.64] ; /* 0x00000004040c8981 */
/* 0x000ea8000c1e1900 */
/*0920*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000004020d8981 */
/* 0x000ea4000c1e1900 */
/*0930*/ @!P0 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d8824 */
/* 0x004fca00078e0a0c */
/*0940*/ @!P0 STG.E [R6.64], R13 ; /* 0x0000000d06008986 */
/* 0x0001e8000c101904 */
/*0950*/ @!P0 LDG.E R12, [R4.64] ; /* 0x00000004040c8981 */
/* 0x000ea8000c1e1900 */
/*0960*/ @!P0 LDG.E R15, [R2.64] ; /* 0x00000004020f8981 */
/* 0x000ea4000c1e1900 */
/*0970*/ @!P0 IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f8824 */
/* 0x004fca00078e0a0c */
/*0980*/ @!P0 STG.E [R6.64], R15 ; /* 0x0000000f06008986 */
/* 0x0001e8000c101904 */
/*0990*/ @!P0 LDG.E R12, [R4.64] ; /* 0x00000004040c8981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ @!P0 LDG.E R17, [R2.64] ; /* 0x0000000402118981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc80007f3e0ff */
/*09c0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f5e0ff */
/*09d0*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e060a */
/*09e0*/ IMAD.X R10, RZ, RZ, R10, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400010e060a */
/*09f0*/ @!P0 IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111118824 */
/* 0x004fca00078e0a0c */
/*0a00*/ @!P0 STG.E [R6.64], R17 ; /* 0x0000001106008986 */
/* 0x0001e2000c101904 */
/*0a10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*0a20*/ ISETP.NE.U32.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f25070 */
/*0a30*/ ISETP.NE.OR.EX P0, PT, R10, RZ, P0, P1 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705710 */
/*0a40*/ @!P0 BRA 0xbc0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0a60*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f26100 */
/*0a70*/ @!P1 LDG.E R11, [R2.64] ; /* 0x00000004020b9981 */
/* 0x001ea8000c1e1900 */
/*0a80*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea4000c1e1900 */
/*0a90*/ @!P1 IMAD.IADD R11, R11, 0x1, -R12 ; /* 0x000000010b0b9824 */
/* 0x004fca00078e0a0c */
/*0aa0*/ @!P1 STG.E [R6.64], R11 ; /* 0x0000000b06009986 */
/* 0x0001e8000c101904 */
/*0ab0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0ac0*/ @!P1 LDG.E R13, [R2.64] ; /* 0x00000004020d9981 */
/* 0x000ea4000c1e1900 */
/*0ad0*/ @!P1 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0d9824 */
/* 0x004fca00078e0a0c */
/*0ae0*/ @!P1 STG.E [R6.64], R13 ; /* 0x0000000d06009986 */
/* 0x0001e8000c101904 */
/*0af0*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0b00*/ @!P1 LDG.E R15, [R2.64] ; /* 0x00000004020f9981 */
/* 0x000ea4000c1e1900 */
/*0b10*/ @!P1 IMAD.IADD R15, R15, 0x1, -R12 ; /* 0x000000010f0f9824 */
/* 0x004fca00078e0a0c */
/*0b20*/ @!P1 STG.E [R6.64], R15 ; /* 0x0000000f06009986 */
/* 0x0001e8000c101904 */
/*0b30*/ @!P1 LDG.E R12, [R4.64] ; /* 0x00000004040c9981 */
/* 0x000ea8000c1e1900 */
/*0b40*/ @!P1 LDG.E R17, [R2.64] ; /* 0x0000000402119981 */
/* 0x000ea2000c1e1900 */
/*0b50*/ IADD3 R9, P0, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fca0007f1e0ff */
/*0b60*/ IMAD.X R10, RZ, RZ, R10, P0 ; /* 0x000000ffff0a7224 */
/* 0x000fe200000e060a */
/*0b70*/ ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f05070 */
/*0b80*/ ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05300 */
/*0b90*/ @!P1 IMAD.IADD R17, R17, 0x1, -R12 ; /* 0x0000000111119824 */
/* 0x004fca00078e0a0c */
/*0ba0*/ @!P1 STG.E [R6.64], R17 ; /* 0x0000001106009986 */
/* 0x0001ee000c101904 */
/*0bb0*/ @P0 BRA 0xa70 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*0bd0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0be0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0bf0*/ IADD3 R8, P1, RZ, -R8, RZ ; /* 0x80000008ff087210 */
/* 0x000fe40007f3e0ff */
/*0c00*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc60003f06070 */
/*0c10*/ IMAD.X R10, RZ, RZ, -0x1, P1 ; /* 0xffffffffff0a7424 */
/* 0x000fe200008e06ff */
/*0c20*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0c30*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea8000c1e1900 */
/*0c40*/ @!P0 LDG.E R9, [R4.64] ; /* 0x0000000404098981 */
/* 0x002ea2000c1e1900 */
/*0c50*/ IADD3 R8, P1, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fca0007f3e0ff */
/*0c60*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*0c70*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f25070 */
/*0c80*/ ISETP.NE.AND.EX P1, PT, R10, RZ, PT, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25310 */
/*0c90*/ @!P0 IMAD.IADD R9, R0, 0x1, -R9 ; /* 0x0000000100098824 */
/* 0x004fca00078e0a09 */
/*0ca0*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0003ee000c101904 */
/*0cb0*/ @P1 BRA 0xc30 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*0cc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : dummy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected dummy
.globl dummy
.p2align 8
.type dummy,@function
dummy:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel dummy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size dummy, .Lfunc_end0-dummy
.section .AMDGPU.csdata,"",@progbits
.text
.protected vecSub
.globl vecSub
.p2align 8
.type vecSub,@function
vecSub:
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc1 .LBB1_5
s_clause 0x1
s_load_b32 s12, s[0:1], 0x34
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s12, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s4, v4
v_add_co_ci_u32_e64 v1, s0, s5, v5, s0
v_add_co_u32 v2, s0, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s7, v5, s0
v_add_co_u32 v4, s0, s8, v4
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc1 .LBB1_5
.LBB1_3:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_2
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
s_branch .LBB1_2
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vecSub
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size vecSub, .Lfunc_end1-vecSub
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: dummy
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: dummy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vecSub
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vecSub.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013eb8d_00000000-6_vecSub.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5dummyvv
.type _Z23__device_stub__Z5dummyvv, @function
_Z23__device_stub__Z5dummyvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq dummy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z5dummyvv, .-_Z23__device_stub__Z5dummyvv
.globl dummy
.type dummy, @function
dummy:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5dummyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size dummy, .-dummy
.globl _Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm
.type _Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm, @function
_Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq vecSub(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm, .-_Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm
.globl vecSub
.type vecSub, @function
vecSub:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6vecSubPiS_S_mmPiS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size vecSub, .-vecSub
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vecSub"
.LC1:
.string "dummy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vecSub(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq dummy(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecSub.hip"
.globl __device_stub__dummy # -- Begin function __device_stub__dummy
.p2align 4, 0x90
.type __device_stub__dummy,@function
__device_stub__dummy: # @__device_stub__dummy
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $dummy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size __device_stub__dummy, .Lfunc_end0-__device_stub__dummy
.cfi_endproc
# -- End function
.globl __device_stub__vecSub # -- Begin function __device_stub__vecSub
.p2align 4, 0x90
.type __device_stub__vecSub,@function
__device_stub__vecSub: # @__device_stub__vecSub
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $vecSub, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size __device_stub__vecSub, .Lfunc_end1-__device_stub__vecSub
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $dummy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vecSub, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type dummy,@object # @dummy
.section .rodata,"a",@progbits
.globl dummy
.p2align 3, 0x0
dummy:
.quad __device_stub__dummy
.size dummy, 8
.type vecSub,@object # @vecSub
.globl vecSub
.p2align 3, 0x0
vecSub:
.quad __device_stub__vecSub
.size vecSub, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "dummy"
.size .L__unnamed_1, 6
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "vecSub"
.size .L__unnamed_2, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__dummy
.addrsig_sym __device_stub__vecSub
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dummy
.addrsig_sym vecSub
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void __fillToInds3D(double A, double *B, int ldb, int rdb, int *I, int nrows, int *J, int ncols, int *K, int nk) {
int ii = threadIdx.x + blockDim.x * blockIdx.x;
int jj = threadIdx.y + blockDim.y * blockIdx.y;
int kk = threadIdx.z + blockDim.z * blockIdx.z;
int i, j, k, mapi, mapj, mapk;
for (k = kk; k < nk; k += blockDim.z * gridDim.z) {
mapk = k;
if (K != NULL) mapk = K[k];
for (j = jj; j < ncols; j += blockDim.y * gridDim.y) {
mapj = j;
if (J != NULL) mapj = J[j];
if (I != NULL) {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = I[i];
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
} else {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = i;
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
}
}
}
} | code for sm_80
Function : _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Z ; /* 0x0000000000037919 */
/* 0x000e280000002700 */
/*0020*/ S2R R0, SR_TID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002300 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e680000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000ea80000002600 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000ee20000002200 */
/*0060*/ IMAD R3, R3, c[0x0][0x8], R0 ; /* 0x0000020003037a24 */
/* 0x001fc600078e0200 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0080*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x1a0], PT ; /* 0x0000680003007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x198], PT ; /* 0x00006600ff007a0c */
/* 0x00efe20003f05070 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0205 */
/*00d0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x19c], PT, P0 ; /* 0x00006700ff007a0c */
/* 0x000fe20003f05300 */
/*00e0*/ IMAD R2, R2, c[0x0][0x4], R7 ; /* 0x0000010002027a24 */
/* 0x000fd800078e0207 */
/*00f0*/ @!P0 BRA 0x7f0 ; /* 0x000006f000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe20003f06270 */
/*0110*/ BSSY B0, 0x7a0 ; /* 0x0000068000007945 */
/* 0x000fd80003800000 */
/*0120*/ @P0 BRA 0x790 ; /* 0x0000066000000947 */
/* 0x001fea0003800000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.WIDE R4, R3, R4, c[0x0][0x198] ; /* 0x0000660003047625 */
/* 0x000fcc00078e0204 */
/*0150*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000162000c1e1900 */
/*0160*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fc80003f05070 */
/*0170*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fda0003f05300 */
/*0180*/ @!P0 BRA 0x480 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0190*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x001fe40000000f00 */
/*01a0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x4 ; /* 0x00000004ff0e7424 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.WIDE R6, R5, R14, c[0x0][0x188] ; /* 0x0000620005067625 */
/* 0x021fcc00078e020e */
/*01c0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x020162000c1e1900 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05070 */
/*01e0*/ BSSY B1, 0x460 ; /* 0x0000027000017945 */
/* 0x000fe20003800000 */
/*01f0*/ MOV R8, c[0x0][0x4] ; /* 0x0000010000087a02 */
/* 0x000fe40000000f00 */
/*0200*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fc60003f05300 */
/*0210*/ IMAD R5, R8, c[0x0][0x10], R5 ; /* 0x0000040008057a24 */
/* 0x000fca00078e0205 */
/*0220*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x190], PT ; /* 0x0000640005007a0c */
/* 0x000fca0003f26270 */
/*0230*/ @!P0 BRA 0x370 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fe20003f06270 */
/*0250*/ BSSY B2, 0x360 ; /* 0x0000010000027945 */
/* 0x000fd80003800000 */
/*0260*/ @P0 BRA 0x350 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD R15, R4, c[0x0][0x174], R7 ; /* 0x00005d00040f7a24 */
/* 0x020fe400078e0207 */
/*0280*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fc800078e0000 */
/*0290*/ IMAD.WIDE R6, R12, R14, c[0x0][0x178] ; /* 0x00005e000c067625 */
/* 0x000fcc00078e020e */
/*02a0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fe200000001ff */
/*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*02d0*/ MOV R11, c[0x0][0x164] ; /* 0x00005900000b7a02 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD R12, R13, c[0x0][0xc], R12 ; /* 0x000003000d0c7a24 */
/* 0x000fca00078e020c */
/*0300*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x180], PT ; /* 0x000060000c007a0c */
/* 0x000fe20003f06270 */
/*0310*/ IMAD R8, R15, c[0x0][0x170], R6 ; /* 0x00005c000f087a24 */
/* 0x004fc800078e0206 */
/*0320*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*0330*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e6000c101b04 */
/*0340*/ @!P0 BRA 0x290 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0350*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x450 ; /* 0x000000e000007947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fda0003f06270 */
/*0380*/ @P0 BRA 0x450 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD R11, R4, c[0x0][0x174], R7 ; /* 0x00005d00040b7a24 */
/* 0x020fe200078e0207 */
/*03a0*/ MOV R10, R0 ; /* 0x00000000000a7202 */
/* 0x000fe20000000f00 */
/*03b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; /* 0x00000008ff0d7424 */
/* 0x000fe200078e00ff */
/*03c0*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fe20000000f00 */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*03e0*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe40000000f00 */
/*03f0*/ IMAD R6, R11, c[0x0][0x170], R10.reuse ; /* 0x00005c000b067a24 */
/* 0x101fe400078e020a */
/*0400*/ IMAD R10, R15, c[0x0][0xc], R10 ; /* 0x000003000f0a7a24 */
/* 0x000fe400078e020a */
/*0410*/ IMAD.WIDE R6, R6, R13, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e020d */
/*0420*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x180], PT ; /* 0x000060000a007a0c */
/* 0x000fe40003f06270 */
/*0430*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001f6000c101b04 */
/*0440*/ @!P0 BRA 0x3f0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0450*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0460*/ @!P1 BRA 0x1a0 ; /* 0xfffffd3000009947 */
/* 0x000fea000383ffff */
/*0470*/ BRA 0x790 ; /* 0x0000031000007947 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x001fc80003f05070 */
/*0490*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*04a0*/ @!P0 BRA 0x640 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0002 */
/*04c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ BSSY B1, 0x600 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*04e0*/ MOV R14, c[0x0][0x4] ; /* 0x00000100000e7a02 */
/* 0x000fd60000000f00 */
/*04f0*/ @P0 BRA 0x5f0 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0500*/ IMAD R13, R4, c[0x0][0x174], R5 ; /* 0x00005d00040d7a24 */
/* 0x020fe400078e0205 */
/*0510*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0000 */
/*0520*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*0530*/ IMAD.WIDE R6, R12, R7, c[0x0][0x178] ; /* 0x00005e000c067625 */
/* 0x000fcc00078e0207 */
/*0540*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x001fe200078e00ff */
/*0560*/ MOV R10, c[0x0][0x160] ; /* 0x00005800000a7a02 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0b7624 */
/* 0x000fe200078e00ff */
/*0580*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fca0000000f00 */
/*0590*/ IMAD R12, R15, c[0x0][0xc], R12 ; /* 0x000003000f0c7a24 */
/* 0x000fca00078e020c */
/*05a0*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x180], PT ; /* 0x000060000c007a0c */
/* 0x000fe20003f06270 */
/*05b0*/ IMAD R8, R13, c[0x0][0x170], R6 ; /* 0x00005c000d087a24 */
/* 0x004fc800078e0206 */
/*05c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*05d0*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e6000c101b04 */
/*05e0*/ @!P0 BRA 0x520 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*05f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0600*/ IMAD R5, R14, c[0x0][0x10], R5 ; /* 0x000004000e057a24 */
/* 0x000fca00078e0205 */
/*0610*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x190], PT ; /* 0x0000640005007a0c */
/* 0x000fda0003f06270 */
/*0620*/ @!P0 BRA 0x4c0 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*0630*/ BRA 0x790 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0002 */
/*0650*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0660*/ BSSY B1, 0x760 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0670*/ MOV R12, c[0x0][0x4] ; /* 0x00000100000c7a02 */
/* 0x000fd60000000f00 */
/*0680*/ @P0 BRA 0x750 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0690*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fe200000001ff */
/*06a0*/ IMAD R11, R4, c[0x0][0x174], R5 ; /* 0x00005d00040b7a24 */
/* 0x020fe200078e0205 */
/*06b0*/ MOV R8, c[0x0][0x160] ; /* 0x0000580000087a02 */
/* 0x000fe20000000f00 */
/*06c0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0000 */
/*06d0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe400078e00ff */
/*06f0*/ IMAD R6, R11, c[0x0][0x170], R10.reuse ; /* 0x00005c000b067a24 */
/* 0x101fe400078e020a */
/*0700*/ IMAD R10, R15, c[0x0][0xc], R10 ; /* 0x000003000f0a7a24 */
/* 0x000fe400078e020a */
/*0710*/ IMAD.WIDE R6, R6, R13, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e020d */
/*0720*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x180], PT ; /* 0x000060000a007a0c */
/* 0x000fe40003f06270 */
/*0730*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001f6000c101b04 */
/*0740*/ @!P0 BRA 0x6f0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0750*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0760*/ IMAD R5, R12, c[0x0][0x10], R5 ; /* 0x000004000c057a24 */
/* 0x000fca00078e0205 */
/*0770*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x190], PT ; /* 0x0000640005007a0c */
/* 0x000fda0003f06270 */
/*0780*/ @!P0 BRA 0x650 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0790*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07a0*/ MOV R4, c[0x0][0x8] ; /* 0x0000020000047a02 */
/* 0x020fca0000000f00 */
/*07b0*/ IMAD R3, R4, c[0x0][0x14], R3 ; /* 0x0000050004037a24 */
/* 0x000fca00078e0203 */
/*07c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x1a0], PT ; /* 0x0000680003007a0c */
/* 0x000fda0003f06270 */
/*07d0*/ @!P0 BRA 0x100 ; /* 0xfffff92000008947 */
/* 0x000fea000383ffff */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe20003f06270 */
/*0800*/ BSSY B0, 0xe60 ; /* 0x0000065000007945 */
/* 0x000fd80003800000 */
/*0810*/ @P0 BRA 0xe50 ; /* 0x0000063000000947 */
/* 0x020fea0003800000 */
/*0820*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fc80003f05070 */
/*0830*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fda0003f05300 */
/*0840*/ @!P0 BRA 0xb40 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0860*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fd400000001ff */
/*0870*/ IMAD.WIDE R6, R4, R12, c[0x0][0x188] ; /* 0x0000620004067625 */
/* 0x021fcc00078e020c */
/*0880*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000162000c1e1900 */
/*0890*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05070 */
/*08a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff057624 */
/* 0x000fe200078e00ff */
/*08b0*/ BSSY B1, 0xb20 ; /* 0x0000026000017945 */
/* 0x000fe40003800000 */
/*08c0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05300 */
/*08d0*/ IMAD R4, R5, c[0x0][0x10], R4 ; /* 0x0000040005047a24 */
/* 0x000fca00078e0204 */
/*08e0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x190], PT ; /* 0x0000640004007a0c */
/* 0x000fce0003f26270 */
/*08f0*/ @!P0 BRA 0xa30 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0900*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fe20003f06270 */
/*0910*/ BSSY B2, 0xa20 ; /* 0x0000010000027945 */
/* 0x000fd80003800000 */
/*0920*/ @P0 BRA 0xa10 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD R13, R3, c[0x0][0x174], R6 ; /* 0x00005d00030d7a24 */
/* 0x020fe200078e0206 */
/*0940*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fca0000000f00 */
/*0950*/ IMAD.WIDE R6, R5, R12, c[0x0][0x178] ; /* 0x00005e0005067625 */
/* 0x000fcc00078e020c */
/*0960*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0970*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fe200000001ff */
/*0980*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*0990*/ MOV R11, c[0x0][0x164] ; /* 0x00005900000b7a02 */
/* 0x000fe40000000f00 */
/*09a0*/ MOV R14, c[0x0][0x0] ; /* 0x00000000000e7a02 */
/* 0x000fca0000000f00 */
/*09b0*/ IMAD R5, R14, c[0x0][0xc], R5 ; /* 0x000003000e057a24 */
/* 0x000fca00078e0205 */
/*09c0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe20003f06270 */
/*09d0*/ IMAD R8, R13, c[0x0][0x170], R6 ; /* 0x00005c000d087a24 */
/* 0x004fc800078e0206 */
/*09e0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*09f0*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e6000c101b04 */
/*0a00*/ @!P0 BRA 0x950 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0a10*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xb10 ; /* 0x000000e000007947 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fda0003f06270 */
/*0a40*/ @P0 BRA 0xb10 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0a50*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0a60*/ IMAD R10, R3, c[0x0][0x174], R6 ; /* 0x00005d00030a7a24 */
/* 0x020fe200078e0206 */
/*0a70*/ MOV R12, c[0x0][0x0] ; /* 0x00000000000c7a02 */
/* 0x000fe20000000f00 */
/*0a80*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0000 */
/*0a90*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0aa0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe400078e00ff */
/*0ab0*/ IMAD R6, R10, c[0x0][0x170], R5.reuse ; /* 0x00005c000a067a24 */
/* 0x101fe400078e0205 */
/*0ac0*/ IMAD R5, R12, c[0x0][0xc], R5 ; /* 0x000003000c057a24 */
/* 0x000fe400078e0205 */
/*0ad0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e020b */
/*0ae0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe40003f06270 */
/*0af0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001f6000c101b04 */
/*0b00*/ @!P0 BRA 0xab0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0b10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b20*/ @!P1 BRA 0x860 ; /* 0xfffffd3000009947 */
/* 0x000fea000383ffff */
/*0b30*/ BRA 0xe50 ; /* 0x0000031000007947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fc80003f05070 */
/*0b50*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*0b60*/ @!P0 BRA 0xd00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0b70*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fe40000000f00 */
/*0b80*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0b90*/ BSSY B1, 0xcc0 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*0ba0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fd600078e00ff */
/*0bb0*/ @P0 BRA 0xcb0 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0bc0*/ IMAD R13, R3, c[0x0][0x174], R10 ; /* 0x00005d00030d7a24 */
/* 0x000fe200078e020a */
/*0bd0*/ MOV R11, R0 ; /* 0x00000000000b7202 */
/* 0x000fe40000000f00 */
/*0be0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fd400000001ff */
/*0bf0*/ IMAD.WIDE R4, R11, R4, c[0x0][0x178] ; /* 0x00005e000b047625 */
/* 0x000fcc00078e0204 */
/*0c00*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0c10*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x001fe200078e00ff */
/*0c20*/ MOV R8, c[0x0][0x160] ; /* 0x0000580000087a02 */
/* 0x000fe20000000f00 */
/*0c30*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0c7624 */
/* 0x000fe200078e00ff */
/*0c40*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fc60000000f00 */
/*0c50*/ IMAD R11, R12, c[0x0][0xc], R11 ; /* 0x000003000c0b7a24 */
/* 0x000fca00078e020b */
/*0c60*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fe20003f06270 */
/*0c70*/ IMAD R6, R13, c[0x0][0x170], R4 ; /* 0x00005c000d067a24 */
/* 0x004fc800078e0204 */
/*0c80*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e0207 */
/*0c90*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001e6000c101b04 */
/*0ca0*/ @!P0 BRA 0xbe0 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0cb0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cc0*/ IMAD R10, R15, c[0x0][0x10], R10 ; /* 0x000004000f0a7a24 */
/* 0x000fca00078e020a */
/*0cd0*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x190], PT ; /* 0x000064000a007a0c */
/* 0x000fda0003f06270 */
/*0ce0*/ @!P0 BRA 0xb80 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*0cf0*/ BRA 0xe50 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0d00*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fe40000000f00 */
/*0d10*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0d20*/ BSSY B1, 0xe20 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0d30*/ MOV R13, c[0x0][0x4] ; /* 0x00000100000d7a02 */
/* 0x000fd60000000f00 */
/*0d40*/ @P0 BRA 0xe10 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0d50*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0d60*/ IMAD R10, R3, c[0x0][0x174], R8 ; /* 0x00005d00030a7a24 */
/* 0x000fe200078e0208 */
/*0d70*/ MOV R12, c[0x0][0x0] ; /* 0x00000000000c7a02 */
/* 0x000fe20000000f00 */
/*0d80*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0000 */
/*0d90*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fe20000000f00 */
/*0da0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe400078e00ff */
/*0db0*/ IMAD R4, R10, c[0x0][0x170], R9.reuse ; /* 0x00005c000a047a24 */
/* 0x101fe400078e0209 */
/*0dc0*/ IMAD R9, R12, c[0x0][0xc], R9 ; /* 0x000003000c097a24 */
/* 0x000fe400078e0209 */
/*0dd0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e020b */
/*0de0*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x180], PT ; /* 0x0000600009007a0c */
/* 0x000fe40003f06270 */
/*0df0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0001f6000c101b04 */
/*0e00*/ @!P0 BRA 0xdb0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0e10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0e20*/ IMAD R8, R13, c[0x0][0x10], R8 ; /* 0x000004000d087a24 */
/* 0x000fca00078e0208 */
/*0e30*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x190], PT ; /* 0x0000640008007a0c */
/* 0x000fda0003f06270 */
/*0e40*/ @!P0 BRA 0xd10 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0e50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e60*/ MOV R4, c[0x0][0x8] ; /* 0x0000020000047a02 */
/* 0x001fca0000000f00 */
/*0e70*/ IMAD R3, R4, c[0x0][0x14], R3 ; /* 0x0000050004037a24 */
/* 0x000fca00078e0203 */
/*0e80*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x1a0], PT ; /* 0x0000680003007a0c */
/* 0x000fda0003f06270 */
/*0e90*/ @!P0 BRA 0x7f0 ; /* 0xfffff95000008947 */
/* 0x000fea000383ffff */
/*0ea0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0eb0*/ BRA 0xeb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void __fillToInds3D(double A, double *B, int ldb, int rdb, int *I, int nrows, int *J, int ncols, int *K, int nk) {
int ii = threadIdx.x + blockDim.x * blockIdx.x;
int jj = threadIdx.y + blockDim.y * blockIdx.y;
int kk = threadIdx.z + blockDim.z * blockIdx.z;
int i, j, k, mapi, mapj, mapk;
for (k = kk; k < nk; k += blockDim.z * gridDim.z) {
mapk = k;
if (K != NULL) mapk = K[k];
for (j = jj; j < ncols; j += blockDim.y * gridDim.y) {
mapj = j;
if (J != NULL) mapj = J[j];
if (I != NULL) {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = I[i];
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
} else {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = i;
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
}
}
}
} | .file "tmpxft_0019a03d_00000000-6___fillToInds3D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i
.type _Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i, @function
_Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movsd %xmm0, 56(%rsp)
movq %rdi, 48(%rsp)
movl %esi, 44(%rsp)
movl %edx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14__fillToInds3DdPdiiPiiS0_iS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i, .-_Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i
.globl _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.type _Z14__fillToInds3DdPdiiPiiS0_iS0_i, @function
_Z14__fillToInds3DdPdiiPiiS0_iS0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14__fillToInds3DdPdiiPiiS0_iS0_i, .-_Z14__fillToInds3DdPdiiPiiS0_iS0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14__fillToInds3DdPdiiPiiS0_iS0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14__fillToInds3DdPdiiPiiS0_iS0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void __fillToInds3D(double A, double *B, int ldb, int rdb, int *I, int nrows, int *J, int ncols, int *K, int nk) {
int ii = threadIdx.x + blockDim.x * blockIdx.x;
int jj = threadIdx.y + blockDim.y * blockIdx.y;
int kk = threadIdx.z + blockDim.z * blockIdx.z;
int i, j, k, mapi, mapj, mapk;
for (k = kk; k < nk; k += blockDim.z * gridDim.z) {
mapk = k;
if (K != NULL) mapk = K[k];
for (j = jj; j < ncols; j += blockDim.y * gridDim.y) {
mapj = j;
if (J != NULL) mapj = J[j];
if (I != NULL) {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = I[i];
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
} else {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = i;
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __fillToInds3D(double A, double *B, int ldb, int rdb, int *I, int nrows, int *J, int ncols, int *K, int nk) {
int ii = threadIdx.x + blockDim.x * blockIdx.x;
int jj = threadIdx.y + blockDim.y * blockIdx.y;
int kk = threadIdx.z + blockDim.z * blockIdx.z;
int i, j, k, mapi, mapj, mapk;
for (k = kk; k < nk; k += blockDim.z * gridDim.z) {
mapk = k;
if (K != NULL) mapk = K[k];
for (j = jj; j < ncols; j += blockDim.y * gridDim.y) {
mapj = j;
if (J != NULL) mapj = J[j];
if (I != NULL) {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = I[i];
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
} else {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = i;
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __fillToInds3D(double A, double *B, int ldb, int rdb, int *I, int nrows, int *J, int ncols, int *K, int nk) {
int ii = threadIdx.x + blockDim.x * blockIdx.x;
int jj = threadIdx.y + blockDim.y * blockIdx.y;
int kk = threadIdx.z + blockDim.z * blockIdx.z;
int i, j, k, mapi, mapj, mapk;
for (k = kk; k < nk; k += blockDim.z * gridDim.z) {
mapk = k;
if (K != NULL) mapk = K[k];
for (j = jj; j < ncols; j += blockDim.y * gridDim.y) {
mapj = j;
if (J != NULL) mapj = J[j];
if (I != NULL) {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = I[i];
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
} else {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = i;
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.globl _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.p2align 8
.type _Z14__fillToInds3DdPdiiPiiS0_iS0_i,@function
_Z14__fillToInds3DdPdiiPiiS0_iS0_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x58
s_load_b32 s12, s[0:1], 0x40
v_bfe_u32 v3, v0, 20, 10
s_add_u32 s2, s0, 0x48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s23, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s23, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_20
s_load_b128 s[24:27], s[2:3], 0x0
s_clause 0x4
s_load_b64 s[16:17], s[0:1], 0x38
s_load_b64 s[18:19], s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x30
s_load_b32 s15, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s27, 0xffff
s_lshr_b32 s2, s27, 16
v_mad_u64_u32 v[3:4], null, s13, s0, v[2:3]
v_mad_u64_u32 v[4:5], null, s14, s2, v[0:1]
s_cmp_lg_u64 s[16:17], 0
s_mul_i32 s13, s24, s0
s_cselect_b32 s14, -1, 0
s_cmp_lg_u64 s[18:19], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s1, s15, v3
s_cselect_b32 s20, -1, 0
v_cmp_gt_i32_e64 s0, s3, v4
s_cmp_lg_u64 s[10:11], 0
s_mul_i32 s22, s25, s2
s_cselect_b32 s21, -1, 0
s_mul_i32 s23, s26, s23
s_mov_b32 s24, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s25
v_add_nc_u32_e32 v1, s23, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s24, vcc_lo, s24
s_and_not1_b32 exec_lo, exec_lo, s24
s_cbranch_execz .LBB0_20
.LBB0_3:
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, v1
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s16, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
global_load_b32 v0, v[5:6], off
.LBB0_5:
s_and_saveexec_b32 s25, s0
s_cbranch_execz .LBB0_2
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v0, s9
v_mov_b32_e32 v5, v4
s_mov_b32 s26, 0
s_branch .LBB0_9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s27
.LBB0_8:
v_add_nc_u32_e32 v5, s22, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v5
s_or_b32 s26, vcc_lo, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_2
.LBB0_9:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v5
s_and_not1_b32 vcc_lo, exec_lo, s20
s_cbranch_vccnz .LBB0_11
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s18, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s19, v7, vcc_lo
global_load_b32 v2, v[6:7], off
.LBB0_11:
s_and_not1_b32 vcc_lo, exec_lo, s21
s_cbranch_vccnz .LBB0_16
s_and_saveexec_b32 s27, s1
s_cbranch_execz .LBB0_15
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v2, v0
s_mov_b32 s28, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v8, v6, s8
v_mov_b32_e32 v6, v3
.p2align 6
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_dual_mov_b32 v12, s5 :: v_dual_mov_b32 v11, s4
v_lshlrev_b64 v[9:10], 2, v[6:7]
v_add_nc_u32_e32 v6, s13, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s15, v6
global_load_b32 v7, v[9:10], off
s_or_b32 s28, vcc_lo, s28
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v9, v7, v8
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v9, s2, s6, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s2, s7, v10, s2
global_store_b64 v[9:10], v[11:12], off
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execnz .LBB0_14
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s27
s_cbranch_execnz .LBB0_8
s_branch .LBB0_17
.LBB0_16:
.LBB0_17:
s_and_saveexec_b32 s27, s1
s_cbranch_execz .LBB0_7
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v0
v_mov_b32_e32 v6, v3
s_mov_b32 s28, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s8
.p2align 6
.LBB0_19:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v10, s5 :: v_dual_add_nc_u32 v7, v2, v6
v_dual_mov_b32 v9, s4 :: v_dual_add_nc_u32 v6, s13, v6
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s15, v6
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_or_b32 s28, vcc_lo, s28
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s2, s6, v7
v_add_co_ci_u32_e64 v8, s2, s7, v8, s2
global_store_b64 v[7:8], v[9:10], off
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execnz .LBB0_19
s_branch .LBB0_7
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 29
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14__fillToInds3DdPdiiPiiS0_iS0_i, .Lfunc_end0-_Z14__fillToInds3DdPdiiPiiS0_iS0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.private_segment_fixed_size: 0
.sgpr_count: 31
.sgpr_spill_count: 0
.symbol: _Z14__fillToInds3DdPdiiPiiS0_iS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __fillToInds3D(double A, double *B, int ldb, int rdb, int *I, int nrows, int *J, int ncols, int *K, int nk) {
int ii = threadIdx.x + blockDim.x * blockIdx.x;
int jj = threadIdx.y + blockDim.y * blockIdx.y;
int kk = threadIdx.z + blockDim.z * blockIdx.z;
int i, j, k, mapi, mapj, mapk;
for (k = kk; k < nk; k += blockDim.z * gridDim.z) {
mapk = k;
if (K != NULL) mapk = K[k];
for (j = jj; j < ncols; j += blockDim.y * gridDim.y) {
mapj = j;
if (J != NULL) mapj = J[j];
if (I != NULL) {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = I[i];
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
} else {
for (i = ii; i < nrows; i += blockDim.x * gridDim.x) {
mapi = i;
B[mapi + ldb * (mapj + rdb * mapk)] = A;
}
}
}
}
} | .text
.file "__fillToInds3D.hip"
.globl _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i # -- Begin function _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.p2align 4, 0x90
.type _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i,@function
_Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i: # @_Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movsd %xmm0, 88(%rsp)
movq %rdi, 80(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 192(%rsp), %rax
movq %rax, 152(%rsp)
leaq 200(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14__fillToInds3DdPdiiPiiS0_iS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i, .Lfunc_end0-_Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14__fillToInds3DdPdiiPiiS0_iS0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14__fillToInds3DdPdiiPiiS0_iS0_i,@object # @_Z14__fillToInds3DdPdiiPiiS0_iS0_i
.section .rodata,"a",@progbits
.globl _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.p2align 3, 0x0
_Z14__fillToInds3DdPdiiPiiS0_iS0_i:
.quad _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.size _Z14__fillToInds3DdPdiiPiiS0_iS0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14__fillToInds3DdPdiiPiiS0_iS0_i"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Z ; /* 0x0000000000037919 */
/* 0x000e280000002700 */
/*0020*/ S2R R0, SR_TID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002300 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e680000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000ea80000002600 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000ee20000002200 */
/*0060*/ IMAD R3, R3, c[0x0][0x8], R0 ; /* 0x0000020003037a24 */
/* 0x001fc600078e0200 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0080*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x1a0], PT ; /* 0x0000680003007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x198], PT ; /* 0x00006600ff007a0c */
/* 0x00efe20003f05070 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0205 */
/*00d0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x19c], PT, P0 ; /* 0x00006700ff007a0c */
/* 0x000fe20003f05300 */
/*00e0*/ IMAD R2, R2, c[0x0][0x4], R7 ; /* 0x0000010002027a24 */
/* 0x000fd800078e0207 */
/*00f0*/ @!P0 BRA 0x7f0 ; /* 0x000006f000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe20003f06270 */
/*0110*/ BSSY B0, 0x7a0 ; /* 0x0000068000007945 */
/* 0x000fd80003800000 */
/*0120*/ @P0 BRA 0x790 ; /* 0x0000066000000947 */
/* 0x001fea0003800000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.WIDE R4, R3, R4, c[0x0][0x198] ; /* 0x0000660003047625 */
/* 0x000fcc00078e0204 */
/*0150*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000162000c1e1900 */
/*0160*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fc80003f05070 */
/*0170*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fda0003f05300 */
/*0180*/ @!P0 BRA 0x480 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0190*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x001fe40000000f00 */
/*01a0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x4 ; /* 0x00000004ff0e7424 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.WIDE R6, R5, R14, c[0x0][0x188] ; /* 0x0000620005067625 */
/* 0x021fcc00078e020e */
/*01c0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x020162000c1e1900 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05070 */
/*01e0*/ BSSY B1, 0x460 ; /* 0x0000027000017945 */
/* 0x000fe20003800000 */
/*01f0*/ MOV R8, c[0x0][0x4] ; /* 0x0000010000087a02 */
/* 0x000fe40000000f00 */
/*0200*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fc60003f05300 */
/*0210*/ IMAD R5, R8, c[0x0][0x10], R5 ; /* 0x0000040008057a24 */
/* 0x000fca00078e0205 */
/*0220*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x190], PT ; /* 0x0000640005007a0c */
/* 0x000fca0003f26270 */
/*0230*/ @!P0 BRA 0x370 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fe20003f06270 */
/*0250*/ BSSY B2, 0x360 ; /* 0x0000010000027945 */
/* 0x000fd80003800000 */
/*0260*/ @P0 BRA 0x350 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD R15, R4, c[0x0][0x174], R7 ; /* 0x00005d00040f7a24 */
/* 0x020fe400078e0207 */
/*0280*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fc800078e0000 */
/*0290*/ IMAD.WIDE R6, R12, R14, c[0x0][0x178] ; /* 0x00005e000c067625 */
/* 0x000fcc00078e020e */
/*02a0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fe200000001ff */
/*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*02d0*/ MOV R11, c[0x0][0x164] ; /* 0x00005900000b7a02 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD R12, R13, c[0x0][0xc], R12 ; /* 0x000003000d0c7a24 */
/* 0x000fca00078e020c */
/*0300*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x180], PT ; /* 0x000060000c007a0c */
/* 0x000fe20003f06270 */
/*0310*/ IMAD R8, R15, c[0x0][0x170], R6 ; /* 0x00005c000f087a24 */
/* 0x004fc800078e0206 */
/*0320*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*0330*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e6000c101b04 */
/*0340*/ @!P0 BRA 0x290 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0350*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x450 ; /* 0x000000e000007947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fda0003f06270 */
/*0380*/ @P0 BRA 0x450 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD R11, R4, c[0x0][0x174], R7 ; /* 0x00005d00040b7a24 */
/* 0x020fe200078e0207 */
/*03a0*/ MOV R10, R0 ; /* 0x00000000000a7202 */
/* 0x000fe20000000f00 */
/*03b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; /* 0x00000008ff0d7424 */
/* 0x000fe200078e00ff */
/*03c0*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fe20000000f00 */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*03e0*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe40000000f00 */
/*03f0*/ IMAD R6, R11, c[0x0][0x170], R10.reuse ; /* 0x00005c000b067a24 */
/* 0x101fe400078e020a */
/*0400*/ IMAD R10, R15, c[0x0][0xc], R10 ; /* 0x000003000f0a7a24 */
/* 0x000fe400078e020a */
/*0410*/ IMAD.WIDE R6, R6, R13, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e020d */
/*0420*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x180], PT ; /* 0x000060000a007a0c */
/* 0x000fe40003f06270 */
/*0430*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001f6000c101b04 */
/*0440*/ @!P0 BRA 0x3f0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0450*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0460*/ @!P1 BRA 0x1a0 ; /* 0xfffffd3000009947 */
/* 0x000fea000383ffff */
/*0470*/ BRA 0x790 ; /* 0x0000031000007947 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x001fc80003f05070 */
/*0490*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*04a0*/ @!P0 BRA 0x640 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0002 */
/*04c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ BSSY B1, 0x600 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*04e0*/ MOV R14, c[0x0][0x4] ; /* 0x00000100000e7a02 */
/* 0x000fd60000000f00 */
/*04f0*/ @P0 BRA 0x5f0 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0500*/ IMAD R13, R4, c[0x0][0x174], R5 ; /* 0x00005d00040d7a24 */
/* 0x020fe400078e0205 */
/*0510*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0000 */
/*0520*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*0530*/ IMAD.WIDE R6, R12, R7, c[0x0][0x178] ; /* 0x00005e000c067625 */
/* 0x000fcc00078e0207 */
/*0540*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x001fe200078e00ff */
/*0560*/ MOV R10, c[0x0][0x160] ; /* 0x00005800000a7a02 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0b7624 */
/* 0x000fe200078e00ff */
/*0580*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fca0000000f00 */
/*0590*/ IMAD R12, R15, c[0x0][0xc], R12 ; /* 0x000003000f0c7a24 */
/* 0x000fca00078e020c */
/*05a0*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x180], PT ; /* 0x000060000c007a0c */
/* 0x000fe20003f06270 */
/*05b0*/ IMAD R8, R13, c[0x0][0x170], R6 ; /* 0x00005c000d087a24 */
/* 0x004fc800078e0206 */
/*05c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*05d0*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e6000c101b04 */
/*05e0*/ @!P0 BRA 0x520 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*05f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0600*/ IMAD R5, R14, c[0x0][0x10], R5 ; /* 0x000004000e057a24 */
/* 0x000fca00078e0205 */
/*0610*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x190], PT ; /* 0x0000640005007a0c */
/* 0x000fda0003f06270 */
/*0620*/ @!P0 BRA 0x4c0 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*0630*/ BRA 0x790 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0002 */
/*0650*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0660*/ BSSY B1, 0x760 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0670*/ MOV R12, c[0x0][0x4] ; /* 0x00000100000c7a02 */
/* 0x000fd60000000f00 */
/*0680*/ @P0 BRA 0x750 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0690*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fe200000001ff */
/*06a0*/ IMAD R11, R4, c[0x0][0x174], R5 ; /* 0x00005d00040b7a24 */
/* 0x020fe200078e0205 */
/*06b0*/ MOV R8, c[0x0][0x160] ; /* 0x0000580000087a02 */
/* 0x000fe20000000f00 */
/*06c0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0000 */
/*06d0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe400078e00ff */
/*06f0*/ IMAD R6, R11, c[0x0][0x170], R10.reuse ; /* 0x00005c000b067a24 */
/* 0x101fe400078e020a */
/*0700*/ IMAD R10, R15, c[0x0][0xc], R10 ; /* 0x000003000f0a7a24 */
/* 0x000fe400078e020a */
/*0710*/ IMAD.WIDE R6, R6, R13, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e020d */
/*0720*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x180], PT ; /* 0x000060000a007a0c */
/* 0x000fe40003f06270 */
/*0730*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001f6000c101b04 */
/*0740*/ @!P0 BRA 0x6f0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0750*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0760*/ IMAD R5, R12, c[0x0][0x10], R5 ; /* 0x000004000c057a24 */
/* 0x000fca00078e0205 */
/*0770*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x190], PT ; /* 0x0000640005007a0c */
/* 0x000fda0003f06270 */
/*0780*/ @!P0 BRA 0x650 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0790*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07a0*/ MOV R4, c[0x0][0x8] ; /* 0x0000020000047a02 */
/* 0x020fca0000000f00 */
/*07b0*/ IMAD R3, R4, c[0x0][0x14], R3 ; /* 0x0000050004037a24 */
/* 0x000fca00078e0203 */
/*07c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x1a0], PT ; /* 0x0000680003007a0c */
/* 0x000fda0003f06270 */
/*07d0*/ @!P0 BRA 0x100 ; /* 0xfffff92000008947 */
/* 0x000fea000383ffff */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe20003f06270 */
/*0800*/ BSSY B0, 0xe60 ; /* 0x0000065000007945 */
/* 0x000fd80003800000 */
/*0810*/ @P0 BRA 0xe50 ; /* 0x0000063000000947 */
/* 0x020fea0003800000 */
/*0820*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fc80003f05070 */
/*0830*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fda0003f05300 */
/*0840*/ @!P0 BRA 0xb40 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0860*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fd400000001ff */
/*0870*/ IMAD.WIDE R6, R4, R12, c[0x0][0x188] ; /* 0x0000620004067625 */
/* 0x021fcc00078e020c */
/*0880*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000162000c1e1900 */
/*0890*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05070 */
/*08a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff057624 */
/* 0x000fe200078e00ff */
/*08b0*/ BSSY B1, 0xb20 ; /* 0x0000026000017945 */
/* 0x000fe40003800000 */
/*08c0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05300 */
/*08d0*/ IMAD R4, R5, c[0x0][0x10], R4 ; /* 0x0000040005047a24 */
/* 0x000fca00078e0204 */
/*08e0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x190], PT ; /* 0x0000640004007a0c */
/* 0x000fce0003f26270 */
/*08f0*/ @!P0 BRA 0xa30 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0900*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fe20003f06270 */
/*0910*/ BSSY B2, 0xa20 ; /* 0x0000010000027945 */
/* 0x000fd80003800000 */
/*0920*/ @P0 BRA 0xa10 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD R13, R3, c[0x0][0x174], R6 ; /* 0x00005d00030d7a24 */
/* 0x020fe200078e0206 */
/*0940*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fca0000000f00 */
/*0950*/ IMAD.WIDE R6, R5, R12, c[0x0][0x178] ; /* 0x00005e0005067625 */
/* 0x000fcc00078e020c */
/*0960*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0970*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fe200000001ff */
/*0980*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*0990*/ MOV R11, c[0x0][0x164] ; /* 0x00005900000b7a02 */
/* 0x000fe40000000f00 */
/*09a0*/ MOV R14, c[0x0][0x0] ; /* 0x00000000000e7a02 */
/* 0x000fca0000000f00 */
/*09b0*/ IMAD R5, R14, c[0x0][0xc], R5 ; /* 0x000003000e057a24 */
/* 0x000fca00078e0205 */
/*09c0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe20003f06270 */
/*09d0*/ IMAD R8, R13, c[0x0][0x170], R6 ; /* 0x00005c000d087a24 */
/* 0x004fc800078e0206 */
/*09e0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*09f0*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e6000c101b04 */
/*0a00*/ @!P0 BRA 0x950 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0a10*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xb10 ; /* 0x000000e000007947 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x001fda0003f06270 */
/*0a40*/ @P0 BRA 0xb10 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0a50*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0a60*/ IMAD R10, R3, c[0x0][0x174], R6 ; /* 0x00005d00030a7a24 */
/* 0x020fe200078e0206 */
/*0a70*/ MOV R12, c[0x0][0x0] ; /* 0x00000000000c7a02 */
/* 0x000fe20000000f00 */
/*0a80*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0000 */
/*0a90*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0aa0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe400078e00ff */
/*0ab0*/ IMAD R6, R10, c[0x0][0x170], R5.reuse ; /* 0x00005c000a067a24 */
/* 0x101fe400078e0205 */
/*0ac0*/ IMAD R5, R12, c[0x0][0xc], R5 ; /* 0x000003000c057a24 */
/* 0x000fe400078e0205 */
/*0ad0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e020b */
/*0ae0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe40003f06270 */
/*0af0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001f6000c101b04 */
/*0b00*/ @!P0 BRA 0xab0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0b10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b20*/ @!P1 BRA 0x860 ; /* 0xfffffd3000009947 */
/* 0x000fea000383ffff */
/*0b30*/ BRA 0xe50 ; /* 0x0000031000007947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fc80003f05070 */
/*0b50*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*0b60*/ @!P0 BRA 0xd00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0b70*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fe40000000f00 */
/*0b80*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0b90*/ BSSY B1, 0xcc0 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*0ba0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fd600078e00ff */
/*0bb0*/ @P0 BRA 0xcb0 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0bc0*/ IMAD R13, R3, c[0x0][0x174], R10 ; /* 0x00005d00030d7a24 */
/* 0x000fe200078e020a */
/*0bd0*/ MOV R11, R0 ; /* 0x00000000000b7202 */
/* 0x000fe40000000f00 */
/*0be0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fd400000001ff */
/*0bf0*/ IMAD.WIDE R4, R11, R4, c[0x0][0x178] ; /* 0x00005e000b047625 */
/* 0x000fcc00078e0204 */
/*0c00*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0c10*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x001fe200078e00ff */
/*0c20*/ MOV R8, c[0x0][0x160] ; /* 0x0000580000087a02 */
/* 0x000fe20000000f00 */
/*0c30*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0c7624 */
/* 0x000fe200078e00ff */
/*0c40*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fc60000000f00 */
/*0c50*/ IMAD R11, R12, c[0x0][0xc], R11 ; /* 0x000003000c0b7a24 */
/* 0x000fca00078e020b */
/*0c60*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fe20003f06270 */
/*0c70*/ IMAD R6, R13, c[0x0][0x170], R4 ; /* 0x00005c000d067a24 */
/* 0x004fc800078e0204 */
/*0c80*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e0207 */
/*0c90*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001e6000c101b04 */
/*0ca0*/ @!P0 BRA 0xbe0 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0cb0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cc0*/ IMAD R10, R15, c[0x0][0x10], R10 ; /* 0x000004000f0a7a24 */
/* 0x000fca00078e020a */
/*0cd0*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x190], PT ; /* 0x000064000a007a0c */
/* 0x000fda0003f06270 */
/*0ce0*/ @!P0 BRA 0xb80 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*0cf0*/ BRA 0xe50 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0d00*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fe40000000f00 */
/*0d10*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0d20*/ BSSY B1, 0xe20 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0d30*/ MOV R13, c[0x0][0x4] ; /* 0x00000100000d7a02 */
/* 0x000fd60000000f00 */
/*0d40*/ @P0 BRA 0xe10 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0d50*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0d60*/ IMAD R10, R3, c[0x0][0x174], R8 ; /* 0x00005d00030a7a24 */
/* 0x000fe200078e0208 */
/*0d70*/ MOV R12, c[0x0][0x0] ; /* 0x00000000000c7a02 */
/* 0x000fe20000000f00 */
/*0d80*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0000 */
/*0d90*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fe20000000f00 */
/*0da0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe400078e00ff */
/*0db0*/ IMAD R4, R10, c[0x0][0x170], R9.reuse ; /* 0x00005c000a047a24 */
/* 0x101fe400078e0209 */
/*0dc0*/ IMAD R9, R12, c[0x0][0xc], R9 ; /* 0x000003000c097a24 */
/* 0x000fe400078e0209 */
/*0dd0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e020b */
/*0de0*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x180], PT ; /* 0x0000600009007a0c */
/* 0x000fe40003f06270 */
/*0df0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0001f6000c101b04 */
/*0e00*/ @!P0 BRA 0xdb0 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0e10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0e20*/ IMAD R8, R13, c[0x0][0x10], R8 ; /* 0x000004000d087a24 */
/* 0x000fca00078e0208 */
/*0e30*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x190], PT ; /* 0x0000640008007a0c */
/* 0x000fda0003f06270 */
/*0e40*/ @!P0 BRA 0xd10 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0e50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e60*/ MOV R4, c[0x0][0x8] ; /* 0x0000020000047a02 */
/* 0x001fca0000000f00 */
/*0e70*/ IMAD R3, R4, c[0x0][0x14], R3 ; /* 0x0000050004037a24 */
/* 0x000fca00078e0203 */
/*0e80*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x1a0], PT ; /* 0x0000680003007a0c */
/* 0x000fda0003f06270 */
/*0e90*/ @!P0 BRA 0x7f0 ; /* 0xfffff95000008947 */
/* 0x000fea000383ffff */
/*0ea0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0eb0*/ BRA 0xeb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.globl _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.p2align 8
.type _Z14__fillToInds3DdPdiiPiiS0_iS0_i,@function
_Z14__fillToInds3DdPdiiPiiS0_iS0_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x58
s_load_b32 s12, s[0:1], 0x40
v_bfe_u32 v3, v0, 20, 10
s_add_u32 s2, s0, 0x48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s23, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s23, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_20
s_load_b128 s[24:27], s[2:3], 0x0
s_clause 0x4
s_load_b64 s[16:17], s[0:1], 0x38
s_load_b64 s[18:19], s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x30
s_load_b32 s15, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s27, 0xffff
s_lshr_b32 s2, s27, 16
v_mad_u64_u32 v[3:4], null, s13, s0, v[2:3]
v_mad_u64_u32 v[4:5], null, s14, s2, v[0:1]
s_cmp_lg_u64 s[16:17], 0
s_mul_i32 s13, s24, s0
s_cselect_b32 s14, -1, 0
s_cmp_lg_u64 s[18:19], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s1, s15, v3
s_cselect_b32 s20, -1, 0
v_cmp_gt_i32_e64 s0, s3, v4
s_cmp_lg_u64 s[10:11], 0
s_mul_i32 s22, s25, s2
s_cselect_b32 s21, -1, 0
s_mul_i32 s23, s26, s23
s_mov_b32 s24, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s25
v_add_nc_u32_e32 v1, s23, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s24, vcc_lo, s24
s_and_not1_b32 exec_lo, exec_lo, s24
s_cbranch_execz .LBB0_20
.LBB0_3:
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, v1
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s16, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
global_load_b32 v0, v[5:6], off
.LBB0_5:
s_and_saveexec_b32 s25, s0
s_cbranch_execz .LBB0_2
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v0, s9
v_mov_b32_e32 v5, v4
s_mov_b32 s26, 0
s_branch .LBB0_9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s27
.LBB0_8:
v_add_nc_u32_e32 v5, s22, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v5
s_or_b32 s26, vcc_lo, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_2
.LBB0_9:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v5
s_and_not1_b32 vcc_lo, exec_lo, s20
s_cbranch_vccnz .LBB0_11
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s18, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s19, v7, vcc_lo
global_load_b32 v2, v[6:7], off
.LBB0_11:
s_and_not1_b32 vcc_lo, exec_lo, s21
s_cbranch_vccnz .LBB0_16
s_and_saveexec_b32 s27, s1
s_cbranch_execz .LBB0_15
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v2, v0
s_mov_b32 s28, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v8, v6, s8
v_mov_b32_e32 v6, v3
.p2align 6
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_dual_mov_b32 v12, s5 :: v_dual_mov_b32 v11, s4
v_lshlrev_b64 v[9:10], 2, v[6:7]
v_add_nc_u32_e32 v6, s13, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s15, v6
global_load_b32 v7, v[9:10], off
s_or_b32 s28, vcc_lo, s28
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v9, v7, v8
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v9, s2, s6, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s2, s7, v10, s2
global_store_b64 v[9:10], v[11:12], off
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execnz .LBB0_14
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s27
s_cbranch_execnz .LBB0_8
s_branch .LBB0_17
.LBB0_16:
.LBB0_17:
s_and_saveexec_b32 s27, s1
s_cbranch_execz .LBB0_7
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v0
v_mov_b32_e32 v6, v3
s_mov_b32 s28, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s8
.p2align 6
.LBB0_19:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v10, s5 :: v_dual_add_nc_u32 v7, v2, v6
v_dual_mov_b32 v9, s4 :: v_dual_add_nc_u32 v6, s13, v6
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s15, v6
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_or_b32 s28, vcc_lo, s28
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s2, s6, v7
v_add_co_ci_u32_e64 v8, s2, s7, v8, s2
global_store_b64 v[7:8], v[9:10], off
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execnz .LBB0_19
s_branch .LBB0_7
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 29
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14__fillToInds3DdPdiiPiiS0_iS0_i, .Lfunc_end0-_Z14__fillToInds3DdPdiiPiiS0_iS0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.private_segment_fixed_size: 0
.sgpr_count: 31
.sgpr_spill_count: 0
.symbol: _Z14__fillToInds3DdPdiiPiiS0_iS0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019a03d_00000000-6___fillToInds3D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i
.type _Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i, @function
_Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movsd %xmm0, 56(%rsp)
movq %rdi, 48(%rsp)
movl %esi, 44(%rsp)
movl %edx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14__fillToInds3DdPdiiPiiS0_iS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i, .-_Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i
.globl _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.type _Z14__fillToInds3DdPdiiPiiS0_iS0_i, @function
_Z14__fillToInds3DdPdiiPiiS0_iS0_i:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z14__fillToInds3DdPdiiPiiS0_iS0_idPdiiPiiS0_iS0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14__fillToInds3DdPdiiPiiS0_iS0_i, .-_Z14__fillToInds3DdPdiiPiiS0_iS0_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14__fillToInds3DdPdiiPiiS0_iS0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14__fillToInds3DdPdiiPiiS0_iS0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "__fillToInds3D.hip"
.globl _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i # -- Begin function _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.p2align 4, 0x90
.type _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i,@function
_Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i: # @_Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movsd %xmm0, 88(%rsp)
movq %rdi, 80(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 192(%rsp), %rax
movq %rax, 152(%rsp)
leaq 200(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14__fillToInds3DdPdiiPiiS0_iS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i, .Lfunc_end0-_Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14__fillToInds3DdPdiiPiiS0_iS0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14__fillToInds3DdPdiiPiiS0_iS0_i,@object # @_Z14__fillToInds3DdPdiiPiiS0_iS0_i
.section .rodata,"a",@progbits
.globl _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.p2align 3, 0x0
_Z14__fillToInds3DdPdiiPiiS0_iS0_i:
.quad _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.size _Z14__fillToInds3DdPdiiPiiS0_iS0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14__fillToInds3DdPdiiPiiS0_iS0_i"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub____fillToInds3DdPdiiPiiS0_iS0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14__fillToInds3DdPdiiPiiS0_iS0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void update_population_metadata( unsigned int * pop , unsigned int rows , unsigned int cols , unsigned int * free , unsigned int * lost , unsigned int * fixed ) {
unsigned int tid = threadIdx.y * blockDim.x + threadIdx.x;
__shared__ unsigned int sPop[ MAX_THREADS ];
__shared__ unsigned int sMeta[ MAX_THREADS ];
bool is_fixed_thread = ((threadIdx.y & 1) == 0);
unsigned int eoffset = tid + ((is_fixed_thread) ? blockDim.x : -blockDim.x);
sMeta[ tid ] = ((is_fixed_thread) ? -1 : 0);
__syncthreads();
unsigned int b_offset = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int offset = threadIdx.y * cols + b_offset;
unsigned int mat_size = rows * cols;
unsigned int i = 0;
// scan population
while( i < rows ) {
sPop[ tid ] = ((offset < mat_size) ? pop[offset] : 0 );
__syncthreads();
unsigned int d = sPop[tid], e = sPop[eoffset];
__syncthreads();
unsigned int res = sMeta[ tid ];
if( offset < mat_size ) {
// should only fail when rows is NOT a multiple of THREAD_ROWS
if( is_fixed_thread ) {
res &= (d & e);
} else {
res |= (d | e);
}
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i += blockDim.y;
offset += blockDim.y * cols;
}
// reduce the fixed and lost lists
i = 4;
while( i <= 32 ) {
unsigned int masked = (threadIdx.y & (i - 1));
unsigned int t = ((tid + (i / 2) * blockDim.x) & (MAX_THREADS - 1));
// how will branches execute?
// assuming that threads are grouped into warps according to their threadIdx.x coordinate
// all threads in a warp should execute same logic
//
unsigned int res = sMeta[tid], v = sMeta[t];
__syncthreads();
if( masked == 0 ) {
res &= v;
} else if( masked == 1 ) {
res |= v;
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i <<= 1;
}
// use a single warp to write shared data back to global memory
if( threadIdx.y == 0 ) {
unsigned int fxd = sMeta[ threadIdx.x ];
unsigned int lst = (~sMeta[ blockDim.x + threadIdx.x ]);
free[ b_offset ] = (fxd | lst);
fixed[ b_offset ] = fxd;
lost[ b_offset ] = lst;
}
__syncthreads();
} | code for sm_80
Function : _Z26update_population_metadataPjjjS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0020*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f25270 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2 ; /* 0x00000002ff047424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e680000002100 */
/*0060*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000ea20000002500 */
/*0070*/ LOP3.LUT P0, RZ, R5.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105ff7812 */
/* 0x041fe2000780c0ff */
/*0080*/ IMAD R3, R5, c[0x0][0x0], R2 ; /* 0x0000000005037a24 */
/* 0x002fc600078e0202 */
/*0090*/ SEL R6, RZ, 0xffffffff, P0 ; /* 0xffffffffff067807 */
/* 0x000fe20000000000 */
/*00a0*/ IMAD R7, R4, c[0x0][0x0], R3 ; /* 0x0000000004077a24 */
/* 0x000fc800078e0203 */
/*00b0*/ STS [R3.X4+0x1000], R6 ; /* 0x0010000603007388 */
/* 0x0001e20000004800 */
/*00c0*/ IMAD R0, R9, c[0x0][0x0], R2 ; /* 0x0000000009007a24 */
/* 0x004fe400078e0202 */
/*00d0*/ IMAD.SHL.U32 R8, R7, 0x4, RZ ; /* 0x0000000407087824 */
/* 0x000fca00078e00ff */
/*00e0*/ LOP3.LUT R17, R8, 0xffc, RZ, 0xc0, !PT ; /* 0x00000ffc08117812 */
/* 0x000fe200078ec0ff */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ @!P1 BRA 0x310 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV R9, RZ, RZ, -c[0x0][0x0] ; /* 0x80000000ff097624 */
/* 0x001fe200078e02ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IMAD.SHL.U32 R6, R3, 0x4, RZ ; /* 0x0000000403067824 */
/* 0x000fe200078e00ff */
/*0140*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0150*/ IMAD R10, R5, c[0x0][0x16c], R0 ; /* 0x00005b00050a7a24 */
/* 0x000fe200078e0200 */
/*0160*/ SEL R9, R9, c[0x0][0x0], P0 ; /* 0x0000000009097a07 */
/* 0x000fe20000000000 */
/*0170*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R6, R9, 0x4, R6 ; /* 0x0000000409067824 */
/* 0x000fe400078e0206 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R10, UR4, PT ; /* 0x000000040a007c0c */
/* 0x000fe2000bf26070 */
/*01a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fd800078e00ff */
/*01b0*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff099424 */
/* 0x000fc800078e00ff */
/*01c0*/ @!P1 IMAD.WIDE.U32 R8, R10, R9, c[0x0][0x160] ; /* 0x000058000a089625 */
/* 0x000fca00078e0009 */
/*01d0*/ @!P1 LDG.E R12, [R8.64] ; /* 0x00000006080c9981 */
/* 0x0000a2000c1e1900 */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R10, UR4, PT ; /* 0x000000040a007c0c */
/* 0x000fe4000bf26070 */
/*01f0*/ IADD3 R11, R11, c[0x0][0x4], RZ ; /* 0x000001000b0b7a10 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x001fc800078e00ff */
/*0210*/ IMAD R10, R9, c[0x0][0x4], R10 ; /* 0x00000100090a7a24 */
/* 0x000fe200078e020a */
/*0220*/ STS [R3.X4], R12 ; /* 0x0000000c03007388 */
/* 0x004fe80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ LDS R13, [R3.X4] ; /* 0x00000000030d7984 */
/* 0x000fe80000004800 */
/*0250*/ LDS R14, [R6] ; /* 0x00000000060e7984 */
/* 0x000e280000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R15, [R3.X4+0x1000] ; /* 0x00100000030f7984 */
/* 0x000e620000004800 */
/*0280*/ LOP3.LUT R16, R14, R13, RZ, 0xfc, !PT ; /* 0x0000000d0e107212 */
/* 0x001fc400078efcff */
/*0290*/ LOP3.LUT R14, R15, R14, R13, 0x80, !PT ; /* 0x0000000e0f0e7212 */
/* 0x002fe400078e800d */
/*02a0*/ @P0 LOP3.LUT R14, R16, R15, RZ, 0xfc, !PT ; /* 0x0000000f100e0212 */
/* 0x000fc800078efcff */
/*02b0*/ SEL R14, R14, R15, !P1 ; /* 0x0000000f0e0e7207 */
/* 0x000fe20004800000 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.GE.U32.AND P1, PT, R11, c[0x0][0x168], PT ; /* 0x00005a000b007a0c */
/* 0x000fca0003f26070 */
/*02e0*/ STS [R3.X4+0x1000], R14 ; /* 0x0010000e03007388 */
/* 0x0001e80000004800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ @!P1 BRA 0x190 ; /* 0xfffffe8000009947 */
/* 0x001fea000383ffff */
/*0310*/ LDS R17, [R17+0x1000] ; /* 0x0010000011117984 */
/* 0x001e220000000800 */
/*0320*/ LOP3.LUT P0, RZ, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305ff7812 */
/* 0x040fe2000780c0ff */
/*0330*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe200078e00ff */
/*0340*/ LOP3.LUT R6, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x000fe200078ec0ff */
/*0350*/ LDS R8, [R3.X4+0x1000] ; /* 0x0010000003087984 */
/* 0x000e620000004800 */
/*0360*/ BSSY B0, 0x790 ; /* 0x0000042000007945 */
/* 0x000fe60003800000 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f25270 */
/*03a0*/ IMAD R6, R4, c[0x0][0x0], R7 ; /* 0x0000000004067a24 */
/* 0x000fc800078e0207 */
/*03b0*/ IMAD.SHL.U32 R9, R6, 0x4, RZ ; /* 0x0000000406097824 */
/* 0x000fe200078e00ff */
/*03c0*/ SEL R7, R17, RZ, !P1 ; /* 0x000000ff11077207 */
/* 0x001fc80004800000 */
/*03d0*/ LOP3.LUT R9, R9, 0xffc, RZ, 0xc0, !PT ; /* 0x00000ffc09097812 */
/* 0x000fe400078ec0ff */
/*03e0*/ LOP3.LUT R4, R17, R8.reuse, RZ, 0xc0, !PT ; /* 0x0000000811047212 */
/* 0x082fe400078ec0ff */
/*03f0*/ @P0 LOP3.LUT R4, R7, R8, RZ, 0xfc, !PT ; /* 0x0000000807040212 */
/* 0x000fe200078efcff */
/*0400*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0410*/ LOP3.LUT P0, R10, R5, 0x7, RZ, 0xc0, !PT ; /* 0x00000007050a7812 */
/* 0x000fc8000780c0ff */
/*0420*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f25270 */
/*0430*/ IMAD R10, R7, c[0x0][0x0], R6 ; /* 0x00000000070a7a24 */
/* 0x000fe200078e0206 */
/*0440*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x000fe60000004800 */
/*0450*/ IMAD.SHL.U32 R12, R10, 0x4, RZ ; /* 0x000000040a0c7824 */
/* 0x000fe200078e00ff */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0470*/ IMAD R10, R13, 0x8, R10 ; /* 0x000000080d0a7824 */
/* 0x000fc600078e020a */
/*0480*/ LOP3.LUT R12, R12, 0xffc, RZ, 0xc0, !PT ; /* 0x00000ffc0c0c7812 */
/* 0x000fe200078ec0ff */
/*0490*/ IMAD.SHL.U32 R10, R10, 0x4, RZ ; /* 0x000000040a0a7824 */
/* 0x000fca00078e00ff */
/*04a0*/ LOP3.LUT R10, R10, 0xffc, RZ, 0xc0, !PT ; /* 0x00000ffc0a0a7812 */
/* 0x000fe200078ec0ff */
/*04b0*/ LDS R9, [R9+0x1000] ; /* 0x0010000009097984 */
/* 0x000e280000000800 */
/*04c0*/ LDS R8, [R3.X4+0x1000] ; /* 0x0010000003087984 */
/* 0x000e620000004800 */
/*04d0*/ SEL R11, R9.reuse, RZ, !P1 ; /* 0x000000ff090b7207 */
/* 0x041fe40004800000 */
/*04e0*/ LOP3.LUT R6, R9, R8.reuse, RZ, 0xc0, !PT ; /* 0x0000000809067212 */
/* 0x082fe200078ec0ff */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0500*/ @P0 LOP3.LUT R6, R11, R8, RZ, 0xfc, !PT ; /* 0x000000080b060212 */
/* 0x000fca00078efcff */
/*0510*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0520*/ LOP3.LUT P0, R8, R5, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f05087812 */
/* 0x000fc8000780c0ff */
/*0530*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f25270 */
/*0540*/ STS [R3.X4+0x1000], R6 ; /* 0x0010000603007388 */
/* 0x000fe80000004800 */
/*0550*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0560*/ LDS R9, [R12+0x1000] ; /* 0x001000000c097984 */
/* 0x000e280000000800 */
/*0570*/ LDS R4, [R3.X4+0x1000] ; /* 0x0010000003047984 */
/* 0x000e620000004800 */
/*0580*/ SEL R11, R9, RZ, !P1 ; /* 0x000000ff090b7207 */
/* 0x001fc40004800000 */
/*0590*/ LOP3.LUT R8, R9, R4.reuse, RZ, 0xc0, !PT ; /* 0x0000000409087212 */
/* 0x082fe200078ec0ff */
/*05a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05b0*/ @P0 LOP3.LUT R8, R11, R4, RZ, 0xfc, !PT ; /* 0x000000040b080212 */
/* 0x000fca00078efcff */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05d0*/ LOP3.LUT P0, R6, R5, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f05067812 */
/* 0x000fc8000780c0ff */
/*05e0*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f25270 */
/*05f0*/ STS [R3.X4+0x1000], R8 ; /* 0x0010000803007388 */
/* 0x000fe80000004800 */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ LDS R9, [R10+0x1000] ; /* 0x001000000a097984 */
/* 0x000e280000000800 */
/*0620*/ LDS R4, [R3.X4+0x1000] ; /* 0x0010000003047984 */
/* 0x000e620000004800 */
/*0630*/ SEL R11, R9, RZ, !P1 ; /* 0x000000ff090b7207 */
/* 0x001fc60004800000 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0660*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f25270 */
/*0670*/ LOP3.LUT R6, R9, R4.reuse, RZ, 0xc0, !PT ; /* 0x0000000409067212 */
/* 0x082fe400078ec0ff */
/*0680*/ @P0 LOP3.LUT R6, R11, R4, RZ, 0xfc, !PT ; /* 0x000000040b060212 */
/* 0x000fca00078efcff */
/*0690*/ STS [R3.X4+0x1000], R6 ; /* 0x0010000603007388 */
/* 0x0001e80000004800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ @P1 BRA 0x780 ; /* 0x000000c000001947 */
/* 0x000fea0003800000 */
/*06c0*/ LEA R3, R2, 0x1000, 0x2 ; /* 0x0000100002037811 */
/* 0x001fe200078e10ff */
/*06d0*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0007 */
/*06e0*/ LDS R2, [R2.X4+0x1000] ; /* 0x0010000002027984 */
/* 0x000fe60000004800 */
/*06f0*/ IMAD R3, R13, 0x4, R3 ; /* 0x000000040d037824 */
/* 0x000fc400078e0203 */
/*0700*/ IMAD.WIDE.U32 R8, R0, R7, c[0x0][0x180] ; /* 0x0000600000087625 */
/* 0x000fc800078e0007 */
/*0710*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e220000000800 */
/*0720*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0007 */
/*0730*/ LOP3.LUT R13, R2, R3.reuse, RZ, 0xf3, !PT ; /* 0x00000003020d7212 */
/* 0x081fe400078ef3ff */
/*0740*/ LOP3.LUT R11, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff0b7212 */
/* 0x000fc600078e33ff */
/*0750*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e8000c101906 */
/*0760*/ STG.E [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0001e8000c101906 */
/*0770*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e4000c101906 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0790*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void update_population_metadata( unsigned int * pop , unsigned int rows , unsigned int cols , unsigned int * free , unsigned int * lost , unsigned int * fixed ) {
unsigned int tid = threadIdx.y * blockDim.x + threadIdx.x;
__shared__ unsigned int sPop[ MAX_THREADS ];
__shared__ unsigned int sMeta[ MAX_THREADS ];
bool is_fixed_thread = ((threadIdx.y & 1) == 0);
unsigned int eoffset = tid + ((is_fixed_thread) ? blockDim.x : -blockDim.x);
sMeta[ tid ] = ((is_fixed_thread) ? -1 : 0);
__syncthreads();
unsigned int b_offset = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int offset = threadIdx.y * cols + b_offset;
unsigned int mat_size = rows * cols;
unsigned int i = 0;
// scan population
while( i < rows ) {
sPop[ tid ] = ((offset < mat_size) ? pop[offset] : 0 );
__syncthreads();
unsigned int d = sPop[tid], e = sPop[eoffset];
__syncthreads();
unsigned int res = sMeta[ tid ];
if( offset < mat_size ) {
// should only fail when rows is NOT a multiple of THREAD_ROWS
if( is_fixed_thread ) {
res &= (d & e);
} else {
res |= (d | e);
}
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i += blockDim.y;
offset += blockDim.y * cols;
}
// reduce the fixed and lost lists
i = 4;
while( i <= 32 ) {
unsigned int masked = (threadIdx.y & (i - 1));
unsigned int t = ((tid + (i / 2) * blockDim.x) & (MAX_THREADS - 1));
// how will branches execute?
// assuming that threads are grouped into warps according to their threadIdx.x coordinate
// all threads in a warp should execute same logic
//
unsigned int res = sMeta[tid], v = sMeta[t];
__syncthreads();
if( masked == 0 ) {
res &= v;
} else if( masked == 1 ) {
res |= v;
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i <<= 1;
}
// use a single warp to write shared data back to global memory
if( threadIdx.y == 0 ) {
unsigned int fxd = sMeta[ threadIdx.x ];
unsigned int lst = (~sMeta[ blockDim.x + threadIdx.x ]);
free[ b_offset ] = (fxd | lst);
fixed[ b_offset ] = fxd;
lost[ b_offset ] = lst;
}
__syncthreads();
} | .file "tmpxft_000d7e07_00000000-6_update_population_metadata.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_
.type _Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_, @function
_Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26update_population_metadataPjjjS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_, .-_Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_
.globl _Z26update_population_metadataPjjjS_S_S_
.type _Z26update_population_metadataPjjjS_S_S_, @function
_Z26update_population_metadataPjjjS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26update_population_metadataPjjjS_S_S_, .-_Z26update_population_metadataPjjjS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26update_population_metadataPjjjS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26update_population_metadataPjjjS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void update_population_metadata( unsigned int * pop , unsigned int rows , unsigned int cols , unsigned int * free , unsigned int * lost , unsigned int * fixed ) {
unsigned int tid = threadIdx.y * blockDim.x + threadIdx.x;
__shared__ unsigned int sPop[ MAX_THREADS ];
__shared__ unsigned int sMeta[ MAX_THREADS ];
bool is_fixed_thread = ((threadIdx.y & 1) == 0);
unsigned int eoffset = tid + ((is_fixed_thread) ? blockDim.x : -blockDim.x);
sMeta[ tid ] = ((is_fixed_thread) ? -1 : 0);
__syncthreads();
unsigned int b_offset = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int offset = threadIdx.y * cols + b_offset;
unsigned int mat_size = rows * cols;
unsigned int i = 0;
// scan population
while( i < rows ) {
sPop[ tid ] = ((offset < mat_size) ? pop[offset] : 0 );
__syncthreads();
unsigned int d = sPop[tid], e = sPop[eoffset];
__syncthreads();
unsigned int res = sMeta[ tid ];
if( offset < mat_size ) {
// should only fail when rows is NOT a multiple of THREAD_ROWS
if( is_fixed_thread ) {
res &= (d & e);
} else {
res |= (d | e);
}
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i += blockDim.y;
offset += blockDim.y * cols;
}
// reduce the fixed and lost lists
i = 4;
while( i <= 32 ) {
unsigned int masked = (threadIdx.y & (i - 1));
unsigned int t = ((tid + (i / 2) * blockDim.x) & (MAX_THREADS - 1));
// how will branches execute?
// assuming that threads are grouped into warps according to their threadIdx.x coordinate
// all threads in a warp should execute same logic
//
unsigned int res = sMeta[tid], v = sMeta[t];
__syncthreads();
if( masked == 0 ) {
res &= v;
} else if( masked == 1 ) {
res |= v;
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i <<= 1;
}
// use a single warp to write shared data back to global memory
if( threadIdx.y == 0 ) {
unsigned int fxd = sMeta[ threadIdx.x ];
unsigned int lst = (~sMeta[ blockDim.x + threadIdx.x ]);
free[ b_offset ] = (fxd | lst);
fixed[ b_offset ] = fxd;
lost[ b_offset ] = lst;
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_population_metadata( unsigned int * pop , unsigned int rows , unsigned int cols , unsigned int * free , unsigned int * lost , unsigned int * fixed ) {
unsigned int tid = threadIdx.y * blockDim.x + threadIdx.x;
__shared__ unsigned int sPop[ MAX_THREADS ];
__shared__ unsigned int sMeta[ MAX_THREADS ];
bool is_fixed_thread = ((threadIdx.y & 1) == 0);
unsigned int eoffset = tid + ((is_fixed_thread) ? blockDim.x : -blockDim.x);
sMeta[ tid ] = ((is_fixed_thread) ? -1 : 0);
__syncthreads();
unsigned int b_offset = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int offset = threadIdx.y * cols + b_offset;
unsigned int mat_size = rows * cols;
unsigned int i = 0;
// scan population
while( i < rows ) {
sPop[ tid ] = ((offset < mat_size) ? pop[offset] : 0 );
__syncthreads();
unsigned int d = sPop[tid], e = sPop[eoffset];
__syncthreads();
unsigned int res = sMeta[ tid ];
if( offset < mat_size ) {
// should only fail when rows is NOT a multiple of THREAD_ROWS
if( is_fixed_thread ) {
res &= (d & e);
} else {
res |= (d | e);
}
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i += blockDim.y;
offset += blockDim.y * cols;
}
// reduce the fixed and lost lists
i = 4;
while( i <= 32 ) {
unsigned int masked = (threadIdx.y & (i - 1));
unsigned int t = ((tid + (i / 2) * blockDim.x) & (MAX_THREADS - 1));
// how will branches execute?
// assuming that threads are grouped into warps according to their threadIdx.x coordinate
// all threads in a warp should execute same logic
//
unsigned int res = sMeta[tid], v = sMeta[t];
__syncthreads();
if( masked == 0 ) {
res &= v;
} else if( masked == 1 ) {
res |= v;
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i <<= 1;
}
// use a single warp to write shared data back to global memory
if( threadIdx.y == 0 ) {
unsigned int fxd = sMeta[ threadIdx.x ];
unsigned int lst = (~sMeta[ blockDim.x + threadIdx.x ]);
free[ b_offset ] = (fxd | lst);
fixed[ b_offset ] = fxd;
lost[ b_offset ] = lst;
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_population_metadata( unsigned int * pop , unsigned int rows , unsigned int cols , unsigned int * free , unsigned int * lost , unsigned int * fixed ) {
unsigned int tid = threadIdx.y * blockDim.x + threadIdx.x;
__shared__ unsigned int sPop[ MAX_THREADS ];
__shared__ unsigned int sMeta[ MAX_THREADS ];
bool is_fixed_thread = ((threadIdx.y & 1) == 0);
unsigned int eoffset = tid + ((is_fixed_thread) ? blockDim.x : -blockDim.x);
sMeta[ tid ] = ((is_fixed_thread) ? -1 : 0);
__syncthreads();
unsigned int b_offset = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int offset = threadIdx.y * cols + b_offset;
unsigned int mat_size = rows * cols;
unsigned int i = 0;
// scan population
while( i < rows ) {
sPop[ tid ] = ((offset < mat_size) ? pop[offset] : 0 );
__syncthreads();
unsigned int d = sPop[tid], e = sPop[eoffset];
__syncthreads();
unsigned int res = sMeta[ tid ];
if( offset < mat_size ) {
// should only fail when rows is NOT a multiple of THREAD_ROWS
if( is_fixed_thread ) {
res &= (d & e);
} else {
res |= (d | e);
}
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i += blockDim.y;
offset += blockDim.y * cols;
}
// reduce the fixed and lost lists
i = 4;
while( i <= 32 ) {
unsigned int masked = (threadIdx.y & (i - 1));
unsigned int t = ((tid + (i / 2) * blockDim.x) & (MAX_THREADS - 1));
// how will branches execute?
// assuming that threads are grouped into warps according to their threadIdx.x coordinate
// all threads in a warp should execute same logic
//
unsigned int res = sMeta[tid], v = sMeta[t];
__syncthreads();
if( masked == 0 ) {
res &= v;
} else if( masked == 1 ) {
res |= v;
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i <<= 1;
}
// use a single warp to write shared data back to global memory
if( threadIdx.y == 0 ) {
unsigned int fxd = sMeta[ threadIdx.x ];
unsigned int lst = (~sMeta[ blockDim.x + threadIdx.x ]);
free[ b_offset ] = (fxd | lst);
fixed[ b_offset ] = fxd;
lost[ b_offset ] = lst;
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26update_population_metadataPjjjS_S_S_
.globl _Z26update_population_metadataPjjjS_S_S_
.p2align 8
.type _Z26update_population_metadataPjjjS_S_S_,@function
_Z26update_population_metadataPjjjS_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s7, s[0:1], 0x8
v_bfe_u32 v7, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
v_bfe_u32 v2, v0, 10, 1
v_and_b32_e32 v0, 0x400, v0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
v_cmp_eq_u32_e64 s2, 0, v2
v_mad_u32_u24 v4, v7, s6, v1
v_mad_u64_u32 v[2:3], null, s15, s6, v[1:2]
s_cmp_eq_u32 s7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0, -1, s2
v_lshlrev_b32_e32 v8, 2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, 0x1000, v8
ds_store_b32 v8, v5 offset:4096
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
s_load_b32 s3, s[0:1], 0xc
s_load_b32 s9, s[4:5], 0xc
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, s6
s_sub_i32 s10, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v3, s10, v3, s2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v7, s3, v[2:3]
v_mov_b32_e32 v6, 0
v_add_lshl_u32 v3, v4, v3, 2
s_lshr_b32 s9, s9, 16
s_mul_i32 s10, s3, s7
s_mul_i32 s11, s9, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v5, s11, v5
s_add_i32 s8, s8, s9
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s8, s7
s_barrier
buffer_gl0_inv
ds_store_b32 v0, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_11
.LBB0_4:
v_cmp_gt_u32_e64 s2, s10, v5
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s12, s2
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s3, s4, v9
v_add_co_ci_u32_e64 v10, s3, s5, v10, s3
global_load_b32 v9, v[9:10], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s12
s_waitcnt vmcnt(0)
ds_store_b32 v8, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v11, v8
ds_load_b32 v10, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v9, v0
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_9
s_waitcnt lgkmcnt(0)
v_or3_b32 v9, v10, v11, v9
.LBB0_9:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_2
v_and_b32_e32 v10, v10, v11
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v9, v10, v9
s_branch .LBB0_2
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, 4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_13
.p2align 6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_lshl_b32 s3, s2, 1
s_cmp_lt_u32 s2, 17
s_mov_b32 s2, s3
s_barrier
buffer_gl0_inv
ds_store_b32 v0, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_19
.LBB0_13:
s_lshr_b32 s3, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s3, s6, v[4:5]
s_add_i32 s3, s2, -1
v_and_b32_e32 v6, s3, v7
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v3, 0x3ff, v5
v_lshlrev_b32_e32 v5, 2, v3
ds_load_b32 v3, v0
ds_load_b32 v5, v5 offset:4096
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_lt_i32_e32 0, v6
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_17
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 1, v6
v_or_b32_e32 v3, v5, v3
s_or_b32 exec_lo, exec_lo, s4
.LBB0_17:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_12
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v3, v5, v3
s_branch .LBB0_12
.LBB0_19:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v7
s_cbranch_execz .LBB0_21
v_add_lshl_u32 v0, v1, s6, 2
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v1
s_load_b64 s[0:1], s[0:1], 0x20
v_mov_b32_e32 v3, 0
ds_load_b32 v4, v0 offset:4096
ds_load_b32 v6, v1 offset:4096
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_not_b32_e32 v7, v4
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_or_b32_e32 v8, v6, v7
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[2:3], v8, off
global_store_b32 v[4:5], v6, off
global_store_b32 v[0:1], v7, off
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26update_population_metadataPjjjS_S_S_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26update_population_metadataPjjjS_S_S_, .Lfunc_end0-_Z26update_population_metadataPjjjS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26update_population_metadataPjjjS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26update_population_metadataPjjjS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_population_metadata( unsigned int * pop , unsigned int rows , unsigned int cols , unsigned int * free , unsigned int * lost , unsigned int * fixed ) {
unsigned int tid = threadIdx.y * blockDim.x + threadIdx.x;
__shared__ unsigned int sPop[ MAX_THREADS ];
__shared__ unsigned int sMeta[ MAX_THREADS ];
bool is_fixed_thread = ((threadIdx.y & 1) == 0);
unsigned int eoffset = tid + ((is_fixed_thread) ? blockDim.x : -blockDim.x);
sMeta[ tid ] = ((is_fixed_thread) ? -1 : 0);
__syncthreads();
unsigned int b_offset = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int offset = threadIdx.y * cols + b_offset;
unsigned int mat_size = rows * cols;
unsigned int i = 0;
// scan population
while( i < rows ) {
sPop[ tid ] = ((offset < mat_size) ? pop[offset] : 0 );
__syncthreads();
unsigned int d = sPop[tid], e = sPop[eoffset];
__syncthreads();
unsigned int res = sMeta[ tid ];
if( offset < mat_size ) {
// should only fail when rows is NOT a multiple of THREAD_ROWS
if( is_fixed_thread ) {
res &= (d & e);
} else {
res |= (d | e);
}
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i += blockDim.y;
offset += blockDim.y * cols;
}
// reduce the fixed and lost lists
i = 4;
while( i <= 32 ) {
unsigned int masked = (threadIdx.y & (i - 1));
unsigned int t = ((tid + (i / 2) * blockDim.x) & (MAX_THREADS - 1));
// how will branches execute?
// assuming that threads are grouped into warps according to their threadIdx.x coordinate
// all threads in a warp should execute same logic
//
unsigned int res = sMeta[tid], v = sMeta[t];
__syncthreads();
if( masked == 0 ) {
res &= v;
} else if( masked == 1 ) {
res |= v;
}
__syncthreads();
sMeta[ tid ] = res;
__syncthreads();
i <<= 1;
}
// use a single warp to write shared data back to global memory
if( threadIdx.y == 0 ) {
unsigned int fxd = sMeta[ threadIdx.x ];
unsigned int lst = (~sMeta[ blockDim.x + threadIdx.x ]);
free[ b_offset ] = (fxd | lst);
fixed[ b_offset ] = fxd;
lost[ b_offset ] = lst;
}
__syncthreads();
} | .text
.file "update_population_metadata.hip"
.globl _Z41__device_stub__update_population_metadataPjjjS_S_S_ # -- Begin function _Z41__device_stub__update_population_metadataPjjjS_S_S_
.p2align 4, 0x90
.type _Z41__device_stub__update_population_metadataPjjjS_S_S_,@function
_Z41__device_stub__update_population_metadataPjjjS_S_S_: # @_Z41__device_stub__update_population_metadataPjjjS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26update_population_metadataPjjjS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__update_population_metadataPjjjS_S_S_, .Lfunc_end0-_Z41__device_stub__update_population_metadataPjjjS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26update_population_metadataPjjjS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26update_population_metadataPjjjS_S_S_,@object # @_Z26update_population_metadataPjjjS_S_S_
.section .rodata,"a",@progbits
.globl _Z26update_population_metadataPjjjS_S_S_
.p2align 3, 0x0
_Z26update_population_metadataPjjjS_S_S_:
.quad _Z41__device_stub__update_population_metadataPjjjS_S_S_
.size _Z26update_population_metadataPjjjS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26update_population_metadataPjjjS_S_S_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__update_population_metadataPjjjS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26update_population_metadataPjjjS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26update_population_metadataPjjjS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0020*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f25270 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2 ; /* 0x00000002ff047424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e680000002100 */
/*0060*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000ea20000002500 */
/*0070*/ LOP3.LUT P0, RZ, R5.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105ff7812 */
/* 0x041fe2000780c0ff */
/*0080*/ IMAD R3, R5, c[0x0][0x0], R2 ; /* 0x0000000005037a24 */
/* 0x002fc600078e0202 */
/*0090*/ SEL R6, RZ, 0xffffffff, P0 ; /* 0xffffffffff067807 */
/* 0x000fe20000000000 */
/*00a0*/ IMAD R7, R4, c[0x0][0x0], R3 ; /* 0x0000000004077a24 */
/* 0x000fc800078e0203 */
/*00b0*/ STS [R3.X4+0x1000], R6 ; /* 0x0010000603007388 */
/* 0x0001e20000004800 */
/*00c0*/ IMAD R0, R9, c[0x0][0x0], R2 ; /* 0x0000000009007a24 */
/* 0x004fe400078e0202 */
/*00d0*/ IMAD.SHL.U32 R8, R7, 0x4, RZ ; /* 0x0000000407087824 */
/* 0x000fca00078e00ff */
/*00e0*/ LOP3.LUT R17, R8, 0xffc, RZ, 0xc0, !PT ; /* 0x00000ffc08117812 */
/* 0x000fe200078ec0ff */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ @!P1 BRA 0x310 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV R9, RZ, RZ, -c[0x0][0x0] ; /* 0x80000000ff097624 */
/* 0x001fe200078e02ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IMAD.SHL.U32 R6, R3, 0x4, RZ ; /* 0x0000000403067824 */
/* 0x000fe200078e00ff */
/*0140*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0150*/ IMAD R10, R5, c[0x0][0x16c], R0 ; /* 0x00005b00050a7a24 */
/* 0x000fe200078e0200 */
/*0160*/ SEL R9, R9, c[0x0][0x0], P0 ; /* 0x0000000009097a07 */
/* 0x000fe20000000000 */
/*0170*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R6, R9, 0x4, R6 ; /* 0x0000000409067824 */
/* 0x000fe400078e0206 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R10, UR4, PT ; /* 0x000000040a007c0c */
/* 0x000fe2000bf26070 */
/*01a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fd800078e00ff */
/*01b0*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff099424 */
/* 0x000fc800078e00ff */
/*01c0*/ @!P1 IMAD.WIDE.U32 R8, R10, R9, c[0x0][0x160] ; /* 0x000058000a089625 */
/* 0x000fca00078e0009 */
/*01d0*/ @!P1 LDG.E R12, [R8.64] ; /* 0x00000006080c9981 */
/* 0x0000a2000c1e1900 */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R10, UR4, PT ; /* 0x000000040a007c0c */
/* 0x000fe4000bf26070 */
/*01f0*/ IADD3 R11, R11, c[0x0][0x4], RZ ; /* 0x000001000b0b7a10 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x001fc800078e00ff */
/*0210*/ IMAD R10, R9, c[0x0][0x4], R10 ; /* 0x00000100090a7a24 */
/* 0x000fe200078e020a */
/*0220*/ STS [R3.X4], R12 ; /* 0x0000000c03007388 */
/* 0x004fe80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ LDS R13, [R3.X4] ; /* 0x00000000030d7984 */
/* 0x000fe80000004800 */
/*0250*/ LDS R14, [R6] ; /* 0x00000000060e7984 */
/* 0x000e280000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R15, [R3.X4+0x1000] ; /* 0x00100000030f7984 */
/* 0x000e620000004800 */
/*0280*/ LOP3.LUT R16, R14, R13, RZ, 0xfc, !PT ; /* 0x0000000d0e107212 */
/* 0x001fc400078efcff */
/*0290*/ LOP3.LUT R14, R15, R14, R13, 0x80, !PT ; /* 0x0000000e0f0e7212 */
/* 0x002fe400078e800d */
/*02a0*/ @P0 LOP3.LUT R14, R16, R15, RZ, 0xfc, !PT ; /* 0x0000000f100e0212 */
/* 0x000fc800078efcff */
/*02b0*/ SEL R14, R14, R15, !P1 ; /* 0x0000000f0e0e7207 */
/* 0x000fe20004800000 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.GE.U32.AND P1, PT, R11, c[0x0][0x168], PT ; /* 0x00005a000b007a0c */
/* 0x000fca0003f26070 */
/*02e0*/ STS [R3.X4+0x1000], R14 ; /* 0x0010000e03007388 */
/* 0x0001e80000004800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ @!P1 BRA 0x190 ; /* 0xfffffe8000009947 */
/* 0x001fea000383ffff */
/*0310*/ LDS R17, [R17+0x1000] ; /* 0x0010000011117984 */
/* 0x001e220000000800 */
/*0320*/ LOP3.LUT P0, RZ, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305ff7812 */
/* 0x040fe2000780c0ff */
/*0330*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe200078e00ff */
/*0340*/ LOP3.LUT R6, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305067812 */
/* 0x000fe200078ec0ff */
/*0350*/ LDS R8, [R3.X4+0x1000] ; /* 0x0010000003087984 */
/* 0x000e620000004800 */
/*0360*/ BSSY B0, 0x790 ; /* 0x0000042000007945 */
/* 0x000fe60003800000 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f25270 */
/*03a0*/ IMAD R6, R4, c[0x0][0x0], R7 ; /* 0x0000000004067a24 */
/* 0x000fc800078e0207 */
/*03b0*/ IMAD.SHL.U32 R9, R6, 0x4, RZ ; /* 0x0000000406097824 */
/* 0x000fe200078e00ff */
/*03c0*/ SEL R7, R17, RZ, !P1 ; /* 0x000000ff11077207 */
/* 0x001fc80004800000 */
/*03d0*/ LOP3.LUT R9, R9, 0xffc, RZ, 0xc0, !PT ; /* 0x00000ffc09097812 */
/* 0x000fe400078ec0ff */
/*03e0*/ LOP3.LUT R4, R17, R8.reuse, RZ, 0xc0, !PT ; /* 0x0000000811047212 */
/* 0x082fe400078ec0ff */
/*03f0*/ @P0 LOP3.LUT R4, R7, R8, RZ, 0xfc, !PT ; /* 0x0000000807040212 */
/* 0x000fe200078efcff */
/*0400*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0410*/ LOP3.LUT P0, R10, R5, 0x7, RZ, 0xc0, !PT ; /* 0x00000007050a7812 */
/* 0x000fc8000780c0ff */
/*0420*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f25270 */
/*0430*/ IMAD R10, R7, c[0x0][0x0], R6 ; /* 0x00000000070a7a24 */
/* 0x000fe200078e0206 */
/*0440*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x000fe60000004800 */
/*0450*/ IMAD.SHL.U32 R12, R10, 0x4, RZ ; /* 0x000000040a0c7824 */
/* 0x000fe200078e00ff */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0470*/ IMAD R10, R13, 0x8, R10 ; /* 0x000000080d0a7824 */
/* 0x000fc600078e020a */
/*0480*/ LOP3.LUT R12, R12, 0xffc, RZ, 0xc0, !PT ; /* 0x00000ffc0c0c7812 */
/* 0x000fe200078ec0ff */
/*0490*/ IMAD.SHL.U32 R10, R10, 0x4, RZ ; /* 0x000000040a0a7824 */
/* 0x000fca00078e00ff */
/*04a0*/ LOP3.LUT R10, R10, 0xffc, RZ, 0xc0, !PT ; /* 0x00000ffc0a0a7812 */
/* 0x000fe200078ec0ff */
/*04b0*/ LDS R9, [R9+0x1000] ; /* 0x0010000009097984 */
/* 0x000e280000000800 */
/*04c0*/ LDS R8, [R3.X4+0x1000] ; /* 0x0010000003087984 */
/* 0x000e620000004800 */
/*04d0*/ SEL R11, R9.reuse, RZ, !P1 ; /* 0x000000ff090b7207 */
/* 0x041fe40004800000 */
/*04e0*/ LOP3.LUT R6, R9, R8.reuse, RZ, 0xc0, !PT ; /* 0x0000000809067212 */
/* 0x082fe200078ec0ff */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0500*/ @P0 LOP3.LUT R6, R11, R8, RZ, 0xfc, !PT ; /* 0x000000080b060212 */
/* 0x000fca00078efcff */
/*0510*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0520*/ LOP3.LUT P0, R8, R5, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f05087812 */
/* 0x000fc8000780c0ff */
/*0530*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f25270 */
/*0540*/ STS [R3.X4+0x1000], R6 ; /* 0x0010000603007388 */
/* 0x000fe80000004800 */
/*0550*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0560*/ LDS R9, [R12+0x1000] ; /* 0x001000000c097984 */
/* 0x000e280000000800 */
/*0570*/ LDS R4, [R3.X4+0x1000] ; /* 0x0010000003047984 */
/* 0x000e620000004800 */
/*0580*/ SEL R11, R9, RZ, !P1 ; /* 0x000000ff090b7207 */
/* 0x001fc40004800000 */
/*0590*/ LOP3.LUT R8, R9, R4.reuse, RZ, 0xc0, !PT ; /* 0x0000000409087212 */
/* 0x082fe200078ec0ff */
/*05a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05b0*/ @P0 LOP3.LUT R8, R11, R4, RZ, 0xfc, !PT ; /* 0x000000040b080212 */
/* 0x000fca00078efcff */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05d0*/ LOP3.LUT P0, R6, R5, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f05067812 */
/* 0x000fc8000780c0ff */
/*05e0*/ ISETP.NE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f25270 */
/*05f0*/ STS [R3.X4+0x1000], R8 ; /* 0x0010000803007388 */
/* 0x000fe80000004800 */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ LDS R9, [R10+0x1000] ; /* 0x001000000a097984 */
/* 0x000e280000000800 */
/*0620*/ LDS R4, [R3.X4+0x1000] ; /* 0x0010000003047984 */
/* 0x000e620000004800 */
/*0630*/ SEL R11, R9, RZ, !P1 ; /* 0x000000ff090b7207 */
/* 0x001fc60004800000 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0660*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f25270 */
/*0670*/ LOP3.LUT R6, R9, R4.reuse, RZ, 0xc0, !PT ; /* 0x0000000409067212 */
/* 0x082fe400078ec0ff */
/*0680*/ @P0 LOP3.LUT R6, R11, R4, RZ, 0xfc, !PT ; /* 0x000000040b060212 */
/* 0x000fca00078efcff */
/*0690*/ STS [R3.X4+0x1000], R6 ; /* 0x0010000603007388 */
/* 0x0001e80000004800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ @P1 BRA 0x780 ; /* 0x000000c000001947 */
/* 0x000fea0003800000 */
/*06c0*/ LEA R3, R2, 0x1000, 0x2 ; /* 0x0000100002037811 */
/* 0x001fe200078e10ff */
/*06d0*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0007 */
/*06e0*/ LDS R2, [R2.X4+0x1000] ; /* 0x0010000002027984 */
/* 0x000fe60000004800 */
/*06f0*/ IMAD R3, R13, 0x4, R3 ; /* 0x000000040d037824 */
/* 0x000fc400078e0203 */
/*0700*/ IMAD.WIDE.U32 R8, R0, R7, c[0x0][0x180] ; /* 0x0000600000087625 */
/* 0x000fc800078e0007 */
/*0710*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e220000000800 */
/*0720*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0007 */
/*0730*/ LOP3.LUT R13, R2, R3.reuse, RZ, 0xf3, !PT ; /* 0x00000003020d7212 */
/* 0x081fe400078ef3ff */
/*0740*/ LOP3.LUT R11, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff0b7212 */
/* 0x000fc600078e33ff */
/*0750*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e8000c101906 */
/*0760*/ STG.E [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0001e8000c101906 */
/*0770*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e4000c101906 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0790*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26update_population_metadataPjjjS_S_S_
.globl _Z26update_population_metadataPjjjS_S_S_
.p2align 8
.type _Z26update_population_metadataPjjjS_S_S_,@function
_Z26update_population_metadataPjjjS_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s7, s[0:1], 0x8
v_bfe_u32 v7, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
v_bfe_u32 v2, v0, 10, 1
v_and_b32_e32 v0, 0x400, v0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
v_cmp_eq_u32_e64 s2, 0, v2
v_mad_u32_u24 v4, v7, s6, v1
v_mad_u64_u32 v[2:3], null, s15, s6, v[1:2]
s_cmp_eq_u32 s7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0, -1, s2
v_lshlrev_b32_e32 v8, 2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, 0x1000, v8
ds_store_b32 v8, v5 offset:4096
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
s_load_b32 s3, s[0:1], 0xc
s_load_b32 s9, s[4:5], 0xc
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, s6
s_sub_i32 s10, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v3, s10, v3, s2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v7, s3, v[2:3]
v_mov_b32_e32 v6, 0
v_add_lshl_u32 v3, v4, v3, 2
s_lshr_b32 s9, s9, 16
s_mul_i32 s10, s3, s7
s_mul_i32 s11, s9, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v5, s11, v5
s_add_i32 s8, s8, s9
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s8, s7
s_barrier
buffer_gl0_inv
ds_store_b32 v0, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_11
.LBB0_4:
v_cmp_gt_u32_e64 s2, s10, v5
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s12, s2
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s3, s4, v9
v_add_co_ci_u32_e64 v10, s3, s5, v10, s3
global_load_b32 v9, v[9:10], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s12
s_waitcnt vmcnt(0)
ds_store_b32 v8, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v11, v8
ds_load_b32 v10, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v9, v0
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_9
s_waitcnt lgkmcnt(0)
v_or3_b32 v9, v10, v11, v9
.LBB0_9:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_2
v_and_b32_e32 v10, v10, v11
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v9, v10, v9
s_branch .LBB0_2
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, 4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_13
.p2align 6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_lshl_b32 s3, s2, 1
s_cmp_lt_u32 s2, 17
s_mov_b32 s2, s3
s_barrier
buffer_gl0_inv
ds_store_b32 v0, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_19
.LBB0_13:
s_lshr_b32 s3, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s3, s6, v[4:5]
s_add_i32 s3, s2, -1
v_and_b32_e32 v6, s3, v7
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v3, 0x3ff, v5
v_lshlrev_b32_e32 v5, 2, v3
ds_load_b32 v3, v0
ds_load_b32 v5, v5 offset:4096
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_lt_i32_e32 0, v6
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_17
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 1, v6
v_or_b32_e32 v3, v5, v3
s_or_b32 exec_lo, exec_lo, s4
.LBB0_17:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_12
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v3, v5, v3
s_branch .LBB0_12
.LBB0_19:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v7
s_cbranch_execz .LBB0_21
v_add_lshl_u32 v0, v1, s6, 2
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v1
s_load_b64 s[0:1], s[0:1], 0x20
v_mov_b32_e32 v3, 0
ds_load_b32 v4, v0 offset:4096
ds_load_b32 v6, v1 offset:4096
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_not_b32_e32 v7, v4
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_or_b32_e32 v8, v6, v7
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[2:3], v8, off
global_store_b32 v[4:5], v6, off
global_store_b32 v[0:1], v7, off
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26update_population_metadataPjjjS_S_S_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26update_population_metadataPjjjS_S_S_, .Lfunc_end0-_Z26update_population_metadataPjjjS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26update_population_metadataPjjjS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26update_population_metadataPjjjS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d7e07_00000000-6_update_population_metadata.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_
.type _Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_, @function
_Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26update_population_metadataPjjjS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_, .-_Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_
.globl _Z26update_population_metadataPjjjS_S_S_
.type _Z26update_population_metadataPjjjS_S_S_, @function
_Z26update_population_metadataPjjjS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z26update_population_metadataPjjjS_S_S_PjjjS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26update_population_metadataPjjjS_S_S_, .-_Z26update_population_metadataPjjjS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26update_population_metadataPjjjS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26update_population_metadataPjjjS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update_population_metadata.hip"
.globl _Z41__device_stub__update_population_metadataPjjjS_S_S_ # -- Begin function _Z41__device_stub__update_population_metadataPjjjS_S_S_
.p2align 4, 0x90
.type _Z41__device_stub__update_population_metadataPjjjS_S_S_,@function
_Z41__device_stub__update_population_metadataPjjjS_S_S_: # @_Z41__device_stub__update_population_metadataPjjjS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26update_population_metadataPjjjS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__update_population_metadataPjjjS_S_S_, .Lfunc_end0-_Z41__device_stub__update_population_metadataPjjjS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26update_population_metadataPjjjS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26update_population_metadataPjjjS_S_S_,@object # @_Z26update_population_metadataPjjjS_S_S_
.section .rodata,"a",@progbits
.globl _Z26update_population_metadataPjjjS_S_S_
.p2align 3, 0x0
_Z26update_population_metadataPjjjS_S_S_:
.quad _Z41__device_stub__update_population_metadataPjjjS_S_S_
.size _Z26update_population_metadataPjjjS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26update_population_metadataPjjjS_S_S_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__update_population_metadataPjjjS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26update_population_metadataPjjjS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
//Code written by Alan Fleming
//CONSTANTS
#define MATRIXSIZE 2048
#define BLOCKSIZE 1024
//Code to prefix sum using the cpu
void prefixSumCPU(int* x, int* y, int N){
y[0] = x[0];
for(int i = 1; i < N; i++){
y[i] = y[i-1] + x[i];
}
}
__global__ void parallelPrefixSum(int* x, int* y, int inputSize) {
//allocate shared memory for block
__shared__ int scan_array[2*BLOCKSIZE];
//initialize shared memory
unsigned int start = 2 * blockIdx.x * blockDim.x;
scan_array[threadIdx.x] = x[start + threadIdx.x];
scan_array[blockDim.x + threadIdx.x] = x[start + blockDim.x + threadIdx.x];
__syncthreads();
//Reduction step
for(int stride = 1; stride <= BLOCKSIZE; stride *= 2){
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index < 2 * BLOCKSIZE) {
scan_array[index] += scan_array[index - stride];
}
__syncthreads();
}
//Post Scan
for(int stride = BLOCKSIZE/2; stride > 0; stride /= 2) {
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index + stride < 2*BLOCKSIZE) {
scan_array[index + stride] += scan_array[index];
}
__syncthreads();
}
//Output array
y[start + threadIdx.x] = scan_array[threadIdx.x];
y[start + blockDim.x + threadIdx.x] = scan_array[blockDim.x + threadIdx.x];
}
int main() {
int *a = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for array
int *cpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for cpu output array
int *gpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for gpu output array
//initialize array
int init = 1325;
for(int i=0; i<MATRIXSIZE;i++){
init = 3125 * init % 6553;
a[i] = (init - 1000) % 97;
gpuResult[i] = 0;
}
//Test CPU reduction
//Get start time
clock_t t1 = clock();
//Calculate reduction
prefixSumCPU(a, cpuResult, MATRIXSIZE);
//Get stop time
clock_t t2 = clock();
//Calculate runtime
float cpuTime= (float(t2-t1)/CLOCKS_PER_SEC*1000);
//Allocate memory on GPU compution. dev_b is used to store the results of the first pass of reduction
int *dev_a, *dev_b;
cudaMalloc((void **)(&dev_a), MATRIXSIZE *sizeof(int));
cudaMalloc((void **)(&dev_b), MATRIXSIZE *sizeof(int));
//copy memory to gpu
cudaMemcpy(dev_a,a, MATRIXSIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,gpuResult, MATRIXSIZE * sizeof(int), cudaMemcpyHostToDevice);
//calculate dimentions for gpu
dim3 dimBlock(BLOCKSIZE);
dim3 dimGrid(ceil(double(MATRIXSIZE)/dimBlock.x/2));
//Set up cuda events for recording runtime
cudaEvent_t start,stop;
float gpuTime;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//calculate prefix sum
parallelPrefixSum<<<dimGrid, dimBlock>>>(dev_a, dev_b, MATRIXSIZE);
//calculate runtime
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&gpuTime,start,stop);
//destroy cuda events
cudaEventDestroy(start);
cudaEventDestroy(stop);
//copy sum from gpu
cudaMemcpy(gpuResult, dev_b, MATRIXSIZE * sizeof(int), cudaMemcpyDeviceToHost);
//print speedup
printf("CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)gpuTime, double(cpuTime / gpuTime));
//verify results
bool valid = true;
for(int i = 0; i < MATRIXSIZE; i++) {
if(cpuResult[i] != gpuResult[i]) {
valid = false;
break;
}
}
if(valid) {
printf("TEST PASSED\n");
} else {
printf("TEST FAILED\n");
}
//free memory
free(a);
free(cpuResult);
free(gpuResult);
cudaFree(dev_a);
cudaFree(dev_b);
return 0;
} | code for sm_80
Function : _Z17parallelPrefixSumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x001fc800078e00ff */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fc800078e0203 */
/*0070*/ IMAD.WIDE.U32 R6, R2.reuse, R13, c[0x0][0x160] ; /* 0x0000580002067625 */
/* 0x040fe200078e000d */
/*0080*/ IADD3 R0, R2, c[0x0][0x0], RZ ; /* 0x0000000002007a10 */
/* 0x000fc80007ffe0ff */
/*0090*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R8, R0, R13, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fcc00078e000d */
/*00b0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ SHF.L.U32 R11, R3, 0x2, RZ ; /* 0x00000002030b7819 */
/* 0x000fca00000006ff */
/*00d0*/ IMAD R4, R13, c[0x0][0x0], R11 ; /* 0x000000000d047a24 */
/* 0x000fe400078e020b */
/*00e0*/ IMAD.SHL.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057824 */
/* 0x000fca00078e00ff */
/*00f0*/ ISETP.GT.AND P0, PT, R5, 0x7fe, PT ; /* 0x000007fe0500780c */
/* 0x000fe40003f04270 */
/*0100*/ IADD3 R14, R11, 0x3, RZ ; /* 0x000000030b0e7810 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GT.AND P1, PT, R14, 0x7ff, PT ; /* 0x000007ff0e00780c */
/* 0x000fe40003f24270 */
/*0120*/ IADD3 R6, R5, 0x2, RZ ; /* 0x0000000205067810 */
/* 0x001fca0007ffe0ff */
/*0130*/ IMAD.SHL.U32 R7, R6, 0x2, RZ ; /* 0x0000000206077824 */
/* 0x000fe200078e00ff */
/*0140*/ STS [R3.X4], R10 ; /* 0x0000000a03007388 */
/* 0x004fe80000004800 */
/*0150*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x008fe80000000800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P0 LDS.64 R12, [R3.X8] ; /* 0x00000000030c8984 */
/* 0x000e240000008a00 */
/*0180*/ @!P0 IMAD.IADD R12, R12, 0x1, R13 ; /* 0x000000010c0c8824 */
/* 0x001fca00078e020d */
/*0190*/ @!P0 STS [R3.X8+0x4], R12 ; /* 0x0000040c03008388 */
/* 0x000fe80000008800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ @!P1 LDS R8, [R6.X8+-0xc] ; /* 0xfffff40006089984 */
/* 0x000fe80000008800 */
/*01c0*/ @!P1 LDS R11, [R6.X8+-0x4] ; /* 0xfffffc00060b9984 */
/* 0x000e220000008800 */
/*01d0*/ IMAD.IADD R9, R7, 0x1, R14 ; /* 0x0000000107097824 */
/* 0x000fca00078e020e */
/*01e0*/ ISETP.GT.AND P0, PT, R9, 0x7ff, PT ; /* 0x000007ff0900780c */
/* 0x000fe20003f04270 */
/*01f0*/ @!P1 IMAD.IADD R11, R8, 0x1, R11 ; /* 0x00000001080b9824 */
/* 0x001fca00078e020b */
/*0200*/ @!P1 STS [R6.X8+-0x4], R11 ; /* 0xfffffc0b06009388 */
/* 0x000fe80000008800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0220*/ @!P0 LDS R10, [R6.X16+-0x14] ; /* 0xffffec00060a8984 */
/* 0x000fe8000000c800 */
/*0230*/ @!P0 LDS R13, [R6.X16+-0x4] ; /* 0xfffffc00060d8984 */
/* 0x000e22000000c800 */
/*0240*/ SHF.L.U32 R8, R6, 0x2, RZ ; /* 0x0000000206087819 */
/* 0x000fca00000006ff */
/*0250*/ IMAD.IADD R15, R9, 0x1, R8 ; /* 0x00000001090f7824 */
/* 0x000fca00078e0208 */
/*0260*/ ISETP.GT.AND P1, PT, R15, 0x7ff, PT ; /* 0x000007ff0f00780c */
/* 0x000fe20003f24270 */
/*0270*/ IMAD.SHL.U32 R9, R6, 0x20, RZ ; /* 0x0000002006097824 */
/* 0x000fe400078e00ff */
/*0280*/ @!P0 IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d8824 */
/* 0x001fca00078e020d */
/*0290*/ @!P0 STS [R6.X16+-0x4], R13 ; /* 0xfffffc0d06008388 */
/* 0x000fe8000000c800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ @!P1 LDS R11, [R9+-0x24] ; /* 0xffffdc00090b9984 */
/* 0x000fe80000000800 */
/*02c0*/ @!P1 LDS R12, [R9+-0x4] ; /* 0xfffffc00090c9984 */
/* 0x000e220000000800 */
/*02d0*/ IMAD.SHL.U32 R10, R6, 0x8, RZ ; /* 0x00000008060a7824 */
/* 0x000fca00078e00ff */
/*02e0*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x000fc80007ffe0ff */
/*02f0*/ ISETP.GT.AND P0, PT, R15, 0x7ff, PT ; /* 0x000007ff0f00780c */
/* 0x000fe20003f04270 */
/*0300*/ @!P1 IMAD.IADD R14, R11, 0x1, R12 ; /* 0x000000010b0e9824 */
/* 0x001fca00078e020c */
/*0310*/ @!P1 STS [R9+-0x4], R14 ; /* 0xfffffc0e09009388 */
/* 0x000fe20000000800 */
/*0320*/ IMAD.SHL.U32 R11, R6, 0x40, RZ ; /* 0x00000040060b7824 */
/* 0x000fc600078e00ff */
/*0330*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0340*/ @!P0 LDS R13, [R11+-0x44] ; /* 0xffffbc000b0d8984 */
/* 0x000fe80000000800 */
/*0350*/ @!P0 LDS R16, [R11+-0x4] ; /* 0xfffffc000b108984 */
/* 0x000e220000000800 */
/*0360*/ IMAD.SHL.U32 R12, R6, 0x10, RZ ; /* 0x00000010060c7824 */
/* 0x000fc800078e00ff */
/*0370*/ IMAD.IADD R18, R12, 0x1, R15 ; /* 0x000000010c127824 */
/* 0x000fca00078e020f */
/*0380*/ ISETP.GT.AND P1, PT, R18, 0x7ff, PT ; /* 0x000007ff1200780c */
/* 0x000fe40003f24270 */
/*0390*/ @!P0 IADD3 R16, R13, R16, RZ ; /* 0x000000100d108210 */
/* 0x001fca0007ffe0ff */
/*03a0*/ @!P0 STS [R11+-0x4], R16 ; /* 0xfffffc100b008388 */
/* 0x000fe20000000800 */
/*03b0*/ IMAD.SHL.U32 R13, R6, 0x80, RZ ; /* 0x00000080060d7824 */
/* 0x000fc600078e00ff */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ @!P1 LDS R14, [R13+-0x84] ; /* 0xffff7c000d0e9984 */
/* 0x000fe80000000800 */
/*03e0*/ @!P1 LDS R15, [R13+-0x4] ; /* 0xfffffc000d0f9984 */
/* 0x000e220000000800 */
/*03f0*/ IMAD.IADD R18, R9, 0x1, R18 ; /* 0x0000000109127824 */
/* 0x000fca00078e0212 */
/*0400*/ ISETP.GT.AND P0, PT, R18, 0x7ff, PT ; /* 0x000007ff1200780c */
/* 0x000fe20003f04270 */
/*0410*/ @!P1 IMAD.IADD R18, R14, 0x1, R15 ; /* 0x000000010e129824 */
/* 0x001fca00078e020f */
/*0420*/ @!P1 STS [R13+-0x4], R18 ; /* 0xfffffc120d009388 */
/* 0x000fe20000000800 */
/*0430*/ IMAD.SHL.U32 R14, R6, 0x100, RZ ; /* 0x00000100060e7824 */
/* 0x000fc600078e00ff */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0450*/ @!P0 LDS R15, [R14+-0x104] ; /* 0xfffefc000e0f8984 */
/* 0x000fe80000000800 */
/*0460*/ @!P0 LDS R16, [R14+-0x4] ; /* 0xfffffc000e108984 */
/* 0x000e220000000800 */
/*0470*/ IADD3 R17, R13, -0x1, RZ ; /* 0xffffffff0d117810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.GT.AND P1, PT, R17, 0x7ff, PT ; /* 0x000007ff1100780c */
/* 0x000fe40003f24270 */
/*0490*/ @!P0 IADD3 R17, R15, R16, RZ ; /* 0x000000100f118210 */
/* 0x001fca0007ffe0ff */
/*04a0*/ @!P0 STS [R14+-0x4], R17 ; /* 0xfffffc110e008388 */
/* 0x000fe20000000800 */
/*04b0*/ IMAD.SHL.U32 R15, R6, 0x200, RZ ; /* 0x00000200060f7824 */
/* 0x000fc600078e00ff */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ @!P1 LDS R16, [R15+-0x204] ; /* 0xfffdfc000f109984 */
/* 0x000fe80000000800 */
/*04e0*/ @!P1 LDS R19, [R15+-0x4] ; /* 0xfffffc000f139984 */
/* 0x000e220000000800 */
/*04f0*/ IADD3 R18, R14, -0x1, RZ ; /* 0xffffffff0e127810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.GT.AND P0, PT, R18, 0x7ff, PT ; /* 0x000007ff1200780c */
/* 0x000fe20003f04270 */
/*0510*/ @!P1 IMAD.IADD R18, R16, 0x1, R19 ; /* 0x0000000110129824 */
/* 0x001fca00078e0213 */
/*0520*/ @!P1 STS [R15+-0x4], R18 ; /* 0xfffffc120f009388 */
/* 0x000fe20000000800 */
/*0530*/ IMAD.SHL.U32 R16, R6, 0x400, RZ ; /* 0x0000040006107824 */
/* 0x000fc600078e00ff */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @!P0 LDS R19, [R16+-0x404] ; /* 0xfffbfc0010138984 */
/* 0x000fe80000000800 */
/*0560*/ @!P0 LDS R20, [R16+-0x4] ; /* 0xfffffc0010148984 */
/* 0x000e220000000800 */
/*0570*/ IADD3 R17, R15, -0x1, RZ ; /* 0xffffffff0f117810 */
/* 0x000fc80007ffe0ff */
/*0580*/ ISETP.GT.AND P1, PT, R17, 0x7ff, PT ; /* 0x000007ff1100780c */
/* 0x000fe20003f24270 */
/*0590*/ IMAD.SHL.U32 R17, R6, 0x800, RZ ; /* 0x0000080006117824 */
/* 0x000fe200078e00ff */
/*05a0*/ @!P0 IADD3 R19, R19, R20, RZ ; /* 0x0000001413138210 */
/* 0x001fca0007ffe0ff */
/*05b0*/ @!P0 STS [R16+-0x4], R19 ; /* 0xfffffc1310008388 */
/* 0x000fe80000000800 */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05d0*/ @!P1 LDS R20, [R17+-0x804] ; /* 0xfff7fc0011149984 */
/* 0x000fe80000000800 */
/*05e0*/ @!P1 LDS R21, [R17+-0x4] ; /* 0xfffffc0011159984 */
/* 0x000e220000000800 */
/*05f0*/ IADD3 R18, R16, -0x1, RZ ; /* 0xffffffff10127810 */
/* 0x000fc80007ffe0ff */
/*0600*/ ISETP.GT.AND P0, PT, R18, 0x7ff, PT ; /* 0x000007ff1200780c */
/* 0x000fe20003f04270 */
/*0610*/ IMAD.SHL.U32 R22, R5, 0x1000, RZ ; /* 0x0000100005167824 */
/* 0x000fe400078e00ff */
/*0620*/ @!P1 IMAD.IADD R20, R20, 0x1, R21 ; /* 0x0000000114149824 */
/* 0x001fca00078e0215 */
/*0630*/ @!P1 STS [R17+-0x4], R20 ; /* 0xfffffc1411009388 */
/* 0x000fe80000000800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ @!P0 LDS R5, [R22+0x1ffc] ; /* 0x001ffc0016058984 */
/* 0x000fe80000000800 */
/*0660*/ @!P0 LDS R18, [R22+0xffc] ; /* 0x000ffc0016128984 */
/* 0x000e220000000800 */
/*0670*/ ISETP.GT.AND P1, PT, R15, 0x600, PT ; /* 0x000006000f00780c */
/* 0x000fc40003f24270 */
/*0680*/ @!P0 IADD3 R5, R5, R18, RZ ; /* 0x0000001205058210 */
/* 0x001fca0007ffe0ff */
/*0690*/ @!P0 STS [R22+0x1ffc], R5 ; /* 0x001ffc0516008388 */
/* 0x000fe80000000800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ @!P1 LDS R18, [R17+0x7fc] ; /* 0x0007fc0011129984 */
/* 0x000fe80000000800 */
/*06c0*/ @!P1 LDS R19, [R17+-0x4] ; /* 0xfffffc0011139984 */
/* 0x000e220000000800 */
/*06d0*/ ISETP.GT.AND P0, PT, R14, 0x700, PT ; /* 0x000007000e00780c */
/* 0x000fe20003f04270 */
/*06e0*/ @!P1 IMAD.IADD R18, R18, 0x1, R19 ; /* 0x0000000112129824 */
/* 0x001fca00078e0213 */
/*06f0*/ @!P1 STS [R17+0x7fc], R18 ; /* 0x0007fc1211009388 */
/* 0x000fe80000000800 */
/*0700*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0710*/ @!P0 LDS R19, [R16+0x3fc] ; /* 0x0003fc0010138984 */
/* 0x000fe80000000800 */
/*0720*/ @!P0 LDS R20, [R16+-0x4] ; /* 0xfffffc0010148984 */
/* 0x000e220000000800 */
/*0730*/ ISETP.GT.AND P1, PT, R13, 0x780, PT ; /* 0x000007800d00780c */
/* 0x000fe20003f24270 */
/*0740*/ @!P0 IMAD.IADD R19, R19, 0x1, R20 ; /* 0x0000000113138824 */
/* 0x001fca00078e0214 */
/*0750*/ @!P0 STS [R16+0x3fc], R19 ; /* 0x0003fc1310008388 */
/* 0x000fe80000000800 */
/*0760*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0770*/ @!P1 LDS R5, [R15+0x1fc] ; /* 0x0001fc000f059984 */
/* 0x000fe80000000800 */
/*0780*/ @!P1 LDS R20, [R15+-0x4] ; /* 0xfffffc000f149984 */
/* 0x000e220000000800 */
/*0790*/ ISETP.GT.AND P0, PT, R11, 0x7c0, PT ; /* 0x000007c00b00780c */
/* 0x000fe20003f04270 */
/*07a0*/ @!P1 IMAD.IADD R20, R5, 0x1, R20 ; /* 0x0000000105149824 */
/* 0x001fca00078e0214 */
/*07b0*/ @!P1 STS [R15+0x1fc], R20 ; /* 0x0001fc140f009388 */
/* 0x000fe80000000800 */
/*07c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07d0*/ @!P0 LDS R5, [R14+0xfc] ; /* 0x0000fc000e058984 */
/* 0x000fe80000000800 */
/*07e0*/ @!P0 LDS R18, [R14+-0x4] ; /* 0xfffffc000e128984 */
/* 0x000e220000000800 */
/*07f0*/ ISETP.GT.AND P1, PT, R9, 0x7e0, PT ; /* 0x000007e00900780c */
/* 0x000fc40003f24270 */
/*0800*/ @!P0 IADD3 R5, R5, R18, RZ ; /* 0x0000001205058210 */
/* 0x001fca0007ffe0ff */
/*0810*/ @!P0 STS [R14+0xfc], R5 ; /* 0x0000fc050e008388 */
/* 0x000fe80000000800 */
/*0820*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0830*/ @!P1 LDS R16, [R13+0x7c] ; /* 0x00007c000d109984 */
/* 0x000fe80000000800 */
/*0840*/ @!P1 LDS R17, [R13+-0x4] ; /* 0xfffffc000d119984 */
/* 0x000e220000000800 */
/*0850*/ ISETP.GT.AND P0, PT, R12, 0x7f0, PT ; /* 0x000007f00c00780c */
/* 0x000fe20003f04270 */
/*0860*/ @!P1 IMAD.IADD R16, R16, 0x1, R17 ; /* 0x0000000110109824 */
/* 0x001fca00078e0211 */
/*0870*/ @!P1 STS [R13+0x7c], R16 ; /* 0x00007c100d009388 */
/* 0x000fe80000000800 */
/*0880*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0890*/ @!P0 LDS R12, [R11+0x3c] ; /* 0x00003c000b0c8984 */
/* 0x000fe80000000800 */
/*08a0*/ @!P0 LDS R15, [R11+-0x4] ; /* 0xfffffc000b0f8984 */
/* 0x000e220000000800 */
/*08b0*/ ISETP.GT.AND P1, PT, R10, 0x7f8, PT ; /* 0x000007f80a00780c */
/* 0x000fe20003f24270 */
/*08c0*/ @!P0 IMAD.IADD R12, R12, 0x1, R15 ; /* 0x000000010c0c8824 */
/* 0x001fca00078e020f */
/*08d0*/ @!P0 STS [R11+0x3c], R12 ; /* 0x00003c0c0b008388 */
/* 0x000fe80000000800 */
/*08e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08f0*/ @!P1 LDS R5, [R9+0x1c] ; /* 0x00001c0009059984 */
/* 0x000fe80000000800 */
/*0900*/ @!P1 LDS R10, [R9+-0x4] ; /* 0xfffffc00090a9984 */
/* 0x000e220000000800 */
/*0910*/ ISETP.GT.AND P0, PT, R8, 0x7fc, PT ; /* 0x000007fc0800780c */
/* 0x000fe20003f04270 */
/*0920*/ @!P1 IMAD.IADD R10, R5, 0x1, R10 ; /* 0x00000001050a9824 */
/* 0x001fca00078e020a */
/*0930*/ @!P1 STS [R9+0x1c], R10 ; /* 0x00001c0a09009388 */
/* 0x000fe80000000800 */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ @!P0 LDS R5, [R6.X16+0xc] ; /* 0x00000c0006058984 */
/* 0x000fe8000000c800 */
/*0960*/ @!P0 LDS R8, [R6.X16+-0x4] ; /* 0xfffffc0006088984 */
/* 0x000e22000000c800 */
/*0970*/ ISETP.GT.AND P1, PT, R7, 0x7fe, PT ; /* 0x000007fe0700780c */
/* 0x000fc40003f24270 */
/*0980*/ @!P0 IADD3 R5, R5, R8, RZ ; /* 0x0000000805058210 */
/* 0x001fca0007ffe0ff */
/*0990*/ @!P0 STS [R6.X16+0xc], R5 ; /* 0x00000c0506008388 */
/* 0x000fe8000000c800 */
/*09a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09b0*/ @!P1 LDS R7, [R6.X8+0x4] ; /* 0x0000040006079984 */
/* 0x000fe80000008800 */
/*09c0*/ @!P1 LDS R8, [R6.X8+-0x4] ; /* 0xfffffc0006089984 */
/* 0x000e220000008800 */
/*09d0*/ ISETP.GT.AND P0, PT, R6, 0x7ff, PT ; /* 0x000007ff0600780c */
/* 0x000fe20003f04270 */
/*09e0*/ @!P1 IMAD.IADD R7, R7, 0x1, R8 ; /* 0x0000000107079824 */
/* 0x001fca00078e0208 */
/*09f0*/ @!P1 STS [R6.X8+0x4], R7 ; /* 0x0000040706009388 */
/* 0x000fe80000008800 */
/*0a00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a10*/ @!P0 LDS R8, [R3.X8+0x8] ; /* 0x0000080003088984 */
/* 0x000fe80000008800 */
/*0a20*/ @!P0 LDS R9, [R3.X8+0x4] ; /* 0x0000040003098984 */
/* 0x000e240000008800 */
/*0a30*/ @!P0 IMAD.IADD R12, R8, 0x1, R9 ; /* 0x00000001080c8824 */
/* 0x001fca00078e0209 */
/*0a40*/ @!P0 STS [R3.X8+0x8], R12 ; /* 0x0000080c03008388 */
/* 0x000fe80000008800 */
/*0a50*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a60*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000e280000004800 */
/*0a70*/ LDS R13, [R4] ; /* 0x00000000040d7984 */
/* 0x000e620000000800 */
/*0a80*/ LEA R8, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002087a11 */
/* 0x000fc400078010ff */
/*0a90*/ LEA R10, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a00000a7a11 */
/* 0x000fe400078210ff */
/*0aa0*/ LEA.HI.X R9, R2, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0002097a11 */
/* 0x000fe400000f14ff */
/*0ab0*/ LEA.HI.X R11, R0, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b00000b7a11 */
/* 0x000fc600008f14ff */
/*0ac0*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x001fe8000c101904 */
/*0ad0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x002fe2000c101904 */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
//Code written by Alan Fleming
//CONSTANTS
#define MATRIXSIZE 2048
#define BLOCKSIZE 1024
//Code to prefix sum using the cpu
void prefixSumCPU(int* x, int* y, int N){
y[0] = x[0];
for(int i = 1; i < N; i++){
y[i] = y[i-1] + x[i];
}
}
__global__ void parallelPrefixSum(int* x, int* y, int inputSize) {
//allocate shared memory for block
__shared__ int scan_array[2*BLOCKSIZE];
//initialize shared memory
unsigned int start = 2 * blockIdx.x * blockDim.x;
scan_array[threadIdx.x] = x[start + threadIdx.x];
scan_array[blockDim.x + threadIdx.x] = x[start + blockDim.x + threadIdx.x];
__syncthreads();
//Reduction step
for(int stride = 1; stride <= BLOCKSIZE; stride *= 2){
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index < 2 * BLOCKSIZE) {
scan_array[index] += scan_array[index - stride];
}
__syncthreads();
}
//Post Scan
for(int stride = BLOCKSIZE/2; stride > 0; stride /= 2) {
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index + stride < 2*BLOCKSIZE) {
scan_array[index + stride] += scan_array[index];
}
__syncthreads();
}
//Output array
y[start + threadIdx.x] = scan_array[threadIdx.x];
y[start + blockDim.x + threadIdx.x] = scan_array[blockDim.x + threadIdx.x];
}
int main() {
int *a = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for array
int *cpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for cpu output array
int *gpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for gpu output array
//initialize array
int init = 1325;
for(int i=0; i<MATRIXSIZE;i++){
init = 3125 * init % 6553;
a[i] = (init - 1000) % 97;
gpuResult[i] = 0;
}
//Test CPU reduction
//Get start time
clock_t t1 = clock();
//Calculate reduction
prefixSumCPU(a, cpuResult, MATRIXSIZE);
//Get stop time
clock_t t2 = clock();
//Calculate runtime
float cpuTime= (float(t2-t1)/CLOCKS_PER_SEC*1000);
//Allocate memory on GPU compution. dev_b is used to store the results of the first pass of reduction
int *dev_a, *dev_b;
cudaMalloc((void **)(&dev_a), MATRIXSIZE *sizeof(int));
cudaMalloc((void **)(&dev_b), MATRIXSIZE *sizeof(int));
//copy memory to gpu
cudaMemcpy(dev_a,a, MATRIXSIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,gpuResult, MATRIXSIZE * sizeof(int), cudaMemcpyHostToDevice);
//calculate dimentions for gpu
dim3 dimBlock(BLOCKSIZE);
dim3 dimGrid(ceil(double(MATRIXSIZE)/dimBlock.x/2));
//Set up cuda events for recording runtime
cudaEvent_t start,stop;
float gpuTime;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//calculate prefix sum
parallelPrefixSum<<<dimGrid, dimBlock>>>(dev_a, dev_b, MATRIXSIZE);
//calculate runtime
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&gpuTime,start,stop);
//destroy cuda events
cudaEventDestroy(start);
cudaEventDestroy(stop);
//copy sum from gpu
cudaMemcpy(gpuResult, dev_b, MATRIXSIZE * sizeof(int), cudaMemcpyDeviceToHost);
//print speedup
printf("CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)gpuTime, double(cpuTime / gpuTime));
//verify results
bool valid = true;
for(int i = 0; i < MATRIXSIZE; i++) {
if(cpuResult[i] != gpuResult[i]) {
valid = false;
break;
}
}
if(valid) {
printf("TEST PASSED\n");
} else {
printf("TEST FAILED\n");
}
//free memory
free(a);
free(cpuResult);
free(gpuResult);
cudaFree(dev_a);
cudaFree(dev_b);
return 0;
} | .file "tmpxft_0008e098_00000000-6_flemingPrefixSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12prefixSumCPUPiS_i
.type _Z12prefixSumCPUPiS_i, @function
_Z12prefixSumCPUPiS_i:
.LFB2057:
.cfi_startproc
endbr64
movl (%rdi), %eax
movl %eax, (%rsi)
cmpl $1, %edx
jle .L3
movl %edx, %edx
movl $1, %eax
.L5:
movl (%rdi,%rax,4), %ecx
addl -4(%rsi,%rax,4), %ecx
movl %ecx, (%rsi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z12prefixSumCPUPiS_i, .-_Z12prefixSumCPUPiS_i
.globl _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i
.type _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i, @function
_Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17parallelPrefixSumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i, .-_Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i
.globl _Z17parallelPrefixSumPiS_i
.type _Z17parallelPrefixSumPiS_i, @function
_Z17parallelPrefixSumPiS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17parallelPrefixSumPiS_i, .-_Z17parallelPrefixSumPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "TEST PASSED\n"
.LC4:
.string "TEST FAILED\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
movl $8192, %edi
call malloc@PLT
movq %rax, %r12
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %ecx
movl $1325, %eax
.L16:
imull $3125, %eax, %edx
movslq %edx, %rax
imulq $-1610366953, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $12, %eax
movl %edx, %esi
sarl $31, %esi
subl %esi, %eax
imull $6553, %eax, %esi
movl %edx, %eax
subl %esi, %eax
leal -1000(%rax), %esi
movslq %esi, %rdx
imulq $354224107, %rdx, %rdx
sarq $35, %rdx
movl %esi, %edi
sarl $31, %edi
subl %edi, %edx
imull $97, %edx, %edx
subl %edx, %esi
movl %esi, 0(%rbp,%rcx)
movl $0, (%rbx,%rcx)
addq $4, %rcx
cmpq $8192, %rcx
jne .L16
call clock@PLT
movq %rax, %r13
movl $2048, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z12prefixSumCPUPiS_i
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 12(%rsp)
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 64(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $8192, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movss 28(%rsp), %xmm1
movss 12(%rsp), %xmm3
movaps %xmm3, %xmm2
divss %xmm1, %xmm2
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $0, %eax
.L19:
movl (%rbx,%rax), %ecx
cmpl %ecx, (%r12,%rax)
jne .L18
addq $4, %rax
cmpq $8192, %rax
jne .L19
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $2048, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i
jmp .L17
.L18:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z17parallelPrefixSumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17parallelPrefixSumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1232348160
.align 4
.LC1:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
//Code written by Alan Fleming
//CONSTANTS
#define MATRIXSIZE 2048
#define BLOCKSIZE 1024
//Code to prefix sum using the cpu
void prefixSumCPU(int* x, int* y, int N){
y[0] = x[0];
for(int i = 1; i < N; i++){
y[i] = y[i-1] + x[i];
}
}
__global__ void parallelPrefixSum(int* x, int* y, int inputSize) {
//allocate shared memory for block
__shared__ int scan_array[2*BLOCKSIZE];
//initialize shared memory
unsigned int start = 2 * blockIdx.x * blockDim.x;
scan_array[threadIdx.x] = x[start + threadIdx.x];
scan_array[blockDim.x + threadIdx.x] = x[start + blockDim.x + threadIdx.x];
__syncthreads();
//Reduction step
for(int stride = 1; stride <= BLOCKSIZE; stride *= 2){
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index < 2 * BLOCKSIZE) {
scan_array[index] += scan_array[index - stride];
}
__syncthreads();
}
//Post Scan
for(int stride = BLOCKSIZE/2; stride > 0; stride /= 2) {
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index + stride < 2*BLOCKSIZE) {
scan_array[index + stride] += scan_array[index];
}
__syncthreads();
}
//Output array
y[start + threadIdx.x] = scan_array[threadIdx.x];
y[start + blockDim.x + threadIdx.x] = scan_array[blockDim.x + threadIdx.x];
}
int main() {
int *a = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for array
int *cpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for cpu output array
int *gpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for gpu output array
//initialize array
int init = 1325;
for(int i=0; i<MATRIXSIZE;i++){
init = 3125 * init % 6553;
a[i] = (init - 1000) % 97;
gpuResult[i] = 0;
}
//Test CPU reduction
//Get start time
clock_t t1 = clock();
//Calculate reduction
prefixSumCPU(a, cpuResult, MATRIXSIZE);
//Get stop time
clock_t t2 = clock();
//Calculate runtime
float cpuTime= (float(t2-t1)/CLOCKS_PER_SEC*1000);
//Allocate memory on GPU compution. dev_b is used to store the results of the first pass of reduction
int *dev_a, *dev_b;
cudaMalloc((void **)(&dev_a), MATRIXSIZE *sizeof(int));
cudaMalloc((void **)(&dev_b), MATRIXSIZE *sizeof(int));
//copy memory to gpu
cudaMemcpy(dev_a,a, MATRIXSIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,gpuResult, MATRIXSIZE * sizeof(int), cudaMemcpyHostToDevice);
//calculate dimentions for gpu
dim3 dimBlock(BLOCKSIZE);
dim3 dimGrid(ceil(double(MATRIXSIZE)/dimBlock.x/2));
//Set up cuda events for recording runtime
cudaEvent_t start,stop;
float gpuTime;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//calculate prefix sum
parallelPrefixSum<<<dimGrid, dimBlock>>>(dev_a, dev_b, MATRIXSIZE);
//calculate runtime
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&gpuTime,start,stop);
//destroy cuda events
cudaEventDestroy(start);
cudaEventDestroy(stop);
//copy sum from gpu
cudaMemcpy(gpuResult, dev_b, MATRIXSIZE * sizeof(int), cudaMemcpyDeviceToHost);
//print speedup
printf("CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)gpuTime, double(cpuTime / gpuTime));
//verify results
bool valid = true;
for(int i = 0; i < MATRIXSIZE; i++) {
if(cpuResult[i] != gpuResult[i]) {
valid = false;
break;
}
}
if(valid) {
printf("TEST PASSED\n");
} else {
printf("TEST FAILED\n");
}
//free memory
free(a);
free(cpuResult);
free(gpuResult);
cudaFree(dev_a);
cudaFree(dev_b);
return 0;
} | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
//Code written by Alan Fleming
//CONSTANTS
#define MATRIXSIZE 2048
#define BLOCKSIZE 1024
//Code to prefix sum using the cpu
void prefixSumCPU(int* x, int* y, int N){
y[0] = x[0];
for(int i = 1; i < N; i++){
y[i] = y[i-1] + x[i];
}
}
__global__ void parallelPrefixSum(int* x, int* y, int inputSize) {
//allocate shared memory for block
__shared__ int scan_array[2*BLOCKSIZE];
//initialize shared memory
unsigned int start = 2 * blockIdx.x * blockDim.x;
scan_array[threadIdx.x] = x[start + threadIdx.x];
scan_array[blockDim.x + threadIdx.x] = x[start + blockDim.x + threadIdx.x];
__syncthreads();
//Reduction step
for(int stride = 1; stride <= BLOCKSIZE; stride *= 2){
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index < 2 * BLOCKSIZE) {
scan_array[index] += scan_array[index - stride];
}
__syncthreads();
}
//Post Scan
for(int stride = BLOCKSIZE/2; stride > 0; stride /= 2) {
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index + stride < 2*BLOCKSIZE) {
scan_array[index + stride] += scan_array[index];
}
__syncthreads();
}
//Output array
y[start + threadIdx.x] = scan_array[threadIdx.x];
y[start + blockDim.x + threadIdx.x] = scan_array[blockDim.x + threadIdx.x];
}
int main() {
int *a = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for array
int *cpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for cpu output array
int *gpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for gpu output array
//initialize array
int init = 1325;
for(int i=0; i<MATRIXSIZE;i++){
init = 3125 * init % 6553;
a[i] = (init - 1000) % 97;
gpuResult[i] = 0;
}
//Test CPU reduction
//Get start time
clock_t t1 = clock();
//Calculate reduction
prefixSumCPU(a, cpuResult, MATRIXSIZE);
//Get stop time
clock_t t2 = clock();
//Calculate runtime
float cpuTime= (float(t2-t1)/CLOCKS_PER_SEC*1000);
//Allocate memory on GPU compution. dev_b is used to store the results of the first pass of reduction
int *dev_a, *dev_b;
hipMalloc((void **)(&dev_a), MATRIXSIZE *sizeof(int));
hipMalloc((void **)(&dev_b), MATRIXSIZE *sizeof(int));
//copy memory to gpu
hipMemcpy(dev_a,a, MATRIXSIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b,gpuResult, MATRIXSIZE * sizeof(int), hipMemcpyHostToDevice);
//calculate dimentions for gpu
dim3 dimBlock(BLOCKSIZE);
dim3 dimGrid(ceil(double(MATRIXSIZE)/dimBlock.x/2));
//Set up cuda events for recording runtime
hipEvent_t start,stop;
float gpuTime;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//calculate prefix sum
parallelPrefixSum<<<dimGrid, dimBlock>>>(dev_a, dev_b, MATRIXSIZE);
//calculate runtime
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&gpuTime,start,stop);
//destroy cuda events
hipEventDestroy(start);
hipEventDestroy(stop);
//copy sum from gpu
hipMemcpy(gpuResult, dev_b, MATRIXSIZE * sizeof(int), hipMemcpyDeviceToHost);
//print speedup
printf("CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)gpuTime, double(cpuTime / gpuTime));
//verify results
bool valid = true;
for(int i = 0; i < MATRIXSIZE; i++) {
if(cpuResult[i] != gpuResult[i]) {
valid = false;
break;
}
}
if(valid) {
printf("TEST PASSED\n");
} else {
printf("TEST FAILED\n");
}
//free memory
free(a);
free(cpuResult);
free(gpuResult);
hipFree(dev_a);
hipFree(dev_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
//Code written by Alan Fleming
//CONSTANTS
#define MATRIXSIZE 2048
#define BLOCKSIZE 1024
//Code to prefix sum using the cpu
void prefixSumCPU(int* x, int* y, int N){
y[0] = x[0];
for(int i = 1; i < N; i++){
y[i] = y[i-1] + x[i];
}
}
__global__ void parallelPrefixSum(int* x, int* y, int inputSize) {
//allocate shared memory for block
__shared__ int scan_array[2*BLOCKSIZE];
//initialize shared memory
unsigned int start = 2 * blockIdx.x * blockDim.x;
scan_array[threadIdx.x] = x[start + threadIdx.x];
scan_array[blockDim.x + threadIdx.x] = x[start + blockDim.x + threadIdx.x];
__syncthreads();
//Reduction step
for(int stride = 1; stride <= BLOCKSIZE; stride *= 2){
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index < 2 * BLOCKSIZE) {
scan_array[index] += scan_array[index - stride];
}
__syncthreads();
}
//Post Scan
for(int stride = BLOCKSIZE/2; stride > 0; stride /= 2) {
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index + stride < 2*BLOCKSIZE) {
scan_array[index + stride] += scan_array[index];
}
__syncthreads();
}
//Output array
y[start + threadIdx.x] = scan_array[threadIdx.x];
y[start + blockDim.x + threadIdx.x] = scan_array[blockDim.x + threadIdx.x];
}
int main() {
int *a = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for array
int *cpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for cpu output array
int *gpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for gpu output array
//initialize array
int init = 1325;
for(int i=0; i<MATRIXSIZE;i++){
init = 3125 * init % 6553;
a[i] = (init - 1000) % 97;
gpuResult[i] = 0;
}
//Test CPU reduction
//Get start time
clock_t t1 = clock();
//Calculate reduction
prefixSumCPU(a, cpuResult, MATRIXSIZE);
//Get stop time
clock_t t2 = clock();
//Calculate runtime
float cpuTime= (float(t2-t1)/CLOCKS_PER_SEC*1000);
//Allocate memory on GPU compution. dev_b is used to store the results of the first pass of reduction
int *dev_a, *dev_b;
hipMalloc((void **)(&dev_a), MATRIXSIZE *sizeof(int));
hipMalloc((void **)(&dev_b), MATRIXSIZE *sizeof(int));
//copy memory to gpu
hipMemcpy(dev_a,a, MATRIXSIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b,gpuResult, MATRIXSIZE * sizeof(int), hipMemcpyHostToDevice);
//calculate dimentions for gpu
dim3 dimBlock(BLOCKSIZE);
dim3 dimGrid(ceil(double(MATRIXSIZE)/dimBlock.x/2));
//Set up cuda events for recording runtime
hipEvent_t start,stop;
float gpuTime;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//calculate prefix sum
parallelPrefixSum<<<dimGrid, dimBlock>>>(dev_a, dev_b, MATRIXSIZE);
//calculate runtime
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&gpuTime,start,stop);
//destroy cuda events
hipEventDestroy(start);
hipEventDestroy(stop);
//copy sum from gpu
hipMemcpy(gpuResult, dev_b, MATRIXSIZE * sizeof(int), hipMemcpyDeviceToHost);
//print speedup
printf("CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)gpuTime, double(cpuTime / gpuTime));
//verify results
bool valid = true;
for(int i = 0; i < MATRIXSIZE; i++) {
if(cpuResult[i] != gpuResult[i]) {
valid = false;
break;
}
}
if(valid) {
printf("TEST PASSED\n");
} else {
printf("TEST FAILED\n");
}
//free memory
free(a);
free(cpuResult);
free(gpuResult);
hipFree(dev_a);
hipFree(dev_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17parallelPrefixSumPiS_i
.globl _Z17parallelPrefixSumPiS_i
.p2align 8
.type _Z17parallelPrefixSumPiS_i,@function
_Z17parallelPrefixSumPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, s4, v0
s_mul_i32 s15, s15, s4
s_lshl_b32 s5, s15, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v1, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s5, v9
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_clause 0x1
global_load_b32 v10, v[5:6], off
global_load_b32 v8, v[7:8], off
v_lshlrev_b32_e32 v6, 2, v0
v_lshlrev_b32_e32 v5, 2, v9
v_add_nc_u32_e32 v7, 1, v0
s_mov_b32 s2, 1
s_waitcnt vmcnt(1)
ds_store_b32 v6, v10
s_waitcnt vmcnt(0)
ds_store_b32 v5, v8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s3
s_lshl_b32 s3, s2, 1
s_cmpk_gt_u32 s2, 0x200
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_2:
v_mul_lo_u32 v8, s2, v7
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x401, v8
s_cbranch_execz .LBB0_1
v_lshl_add_u32 v8, v8, 1, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s2, v8
v_lshlrev_b32_e32 v8, 2, v8
v_lshlrev_b32_e32 v9, 2, v9
ds_load_b32 v9, v9
ds_load_b32 v10, v8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v9, v10, v9
ds_store_b32 v8, v9
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_lshl_add_u32 v0, v0, 1, 2
s_movk_i32 s2, 0x200
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u32_u24 v8, v0, s2, -1
s_mov_b32 s3, exec_lo
v_add_nc_u32_e32 v7, s2, v8
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x800, v7
s_cbranch_execz .LBB0_5
v_lshlrev_b32_e32 v8, 2, v8
v_lshlrev_b32_e32 v7, 2, v7
ds_load_b32 v8, v8
ds_load_b32 v9, v7
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v8, v9, v8
ds_store_b32 v7, v8
s_branch .LBB0_5
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v6, v6
ds_load_b32 v5, v5
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17parallelPrefixSumPiS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17parallelPrefixSumPiS_i, .Lfunc_end0-_Z17parallelPrefixSumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17parallelPrefixSumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17parallelPrefixSumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
//Code written by Alan Fleming
//CONSTANTS
#define MATRIXSIZE 2048
#define BLOCKSIZE 1024
//Code to prefix sum using the cpu
void prefixSumCPU(int* x, int* y, int N){
y[0] = x[0];
for(int i = 1; i < N; i++){
y[i] = y[i-1] + x[i];
}
}
__global__ void parallelPrefixSum(int* x, int* y, int inputSize) {
//allocate shared memory for block
__shared__ int scan_array[2*BLOCKSIZE];
//initialize shared memory
unsigned int start = 2 * blockIdx.x * blockDim.x;
scan_array[threadIdx.x] = x[start + threadIdx.x];
scan_array[blockDim.x + threadIdx.x] = x[start + blockDim.x + threadIdx.x];
__syncthreads();
//Reduction step
for(int stride = 1; stride <= BLOCKSIZE; stride *= 2){
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index < 2 * BLOCKSIZE) {
scan_array[index] += scan_array[index - stride];
}
__syncthreads();
}
//Post Scan
for(int stride = BLOCKSIZE/2; stride > 0; stride /= 2) {
int index = (threadIdx.x + 1) * stride * 2 - 1;
if(index + stride < 2*BLOCKSIZE) {
scan_array[index + stride] += scan_array[index];
}
__syncthreads();
}
//Output array
y[start + threadIdx.x] = scan_array[threadIdx.x];
y[start + blockDim.x + threadIdx.x] = scan_array[blockDim.x + threadIdx.x];
}
int main() {
int *a = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for array
int *cpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for cpu output array
int *gpuResult = (int *)malloc(sizeof(int) * MATRIXSIZE); //allocate space for gpu output array
//initialize array
int init = 1325;
for(int i=0; i<MATRIXSIZE;i++){
init = 3125 * init % 6553;
a[i] = (init - 1000) % 97;
gpuResult[i] = 0;
}
//Test CPU reduction
//Get start time
clock_t t1 = clock();
//Calculate reduction
prefixSumCPU(a, cpuResult, MATRIXSIZE);
//Get stop time
clock_t t2 = clock();
//Calculate runtime
float cpuTime= (float(t2-t1)/CLOCKS_PER_SEC*1000);
//Allocate memory on GPU compution. dev_b is used to store the results of the first pass of reduction
int *dev_a, *dev_b;
hipMalloc((void **)(&dev_a), MATRIXSIZE *sizeof(int));
hipMalloc((void **)(&dev_b), MATRIXSIZE *sizeof(int));
//copy memory to gpu
hipMemcpy(dev_a,a, MATRIXSIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b,gpuResult, MATRIXSIZE * sizeof(int), hipMemcpyHostToDevice);
//calculate dimentions for gpu
dim3 dimBlock(BLOCKSIZE);
dim3 dimGrid(ceil(double(MATRIXSIZE)/dimBlock.x/2));
//Set up cuda events for recording runtime
hipEvent_t start,stop;
float gpuTime;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//calculate prefix sum
parallelPrefixSum<<<dimGrid, dimBlock>>>(dev_a, dev_b, MATRIXSIZE);
//calculate runtime
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&gpuTime,start,stop);
//destroy cuda events
hipEventDestroy(start);
hipEventDestroy(stop);
//copy sum from gpu
hipMemcpy(gpuResult, dev_b, MATRIXSIZE * sizeof(int), hipMemcpyDeviceToHost);
//print speedup
printf("CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)gpuTime, double(cpuTime / gpuTime));
//verify results
bool valid = true;
for(int i = 0; i < MATRIXSIZE; i++) {
if(cpuResult[i] != gpuResult[i]) {
valid = false;
break;
}
}
if(valid) {
printf("TEST PASSED\n");
} else {
printf("TEST FAILED\n");
}
//free memory
free(a);
free(cpuResult);
free(gpuResult);
hipFree(dev_a);
hipFree(dev_b);
return 0;
} | .text
.file "flemingPrefixSum.hip"
.globl _Z12prefixSumCPUPiS_i # -- Begin function _Z12prefixSumCPUPiS_i
.p2align 4, 0x90
.type _Z12prefixSumCPUPiS_i,@function
_Z12prefixSumCPUPiS_i: # @_Z12prefixSumCPUPiS_i
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
movl %eax, (%rsi)
cmpl $2, %edx
jl .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
movl (%rsi), %ecx
movl $1, %edx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rdx,4), %ecx
movl %ecx, (%rsi,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z12prefixSumCPUPiS_i, .Lfunc_end0-_Z12prefixSumCPUPiS_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__parallelPrefixSumPiS_i # -- Begin function _Z32__device_stub__parallelPrefixSumPiS_i
.p2align 4, 0x90
.type _Z32__device_stub__parallelPrefixSumPiS_i,@function
_Z32__device_stub__parallelPrefixSumPiS_i: # @_Z32__device_stub__parallelPrefixSumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17parallelPrefixSumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z32__device_stub__parallelPrefixSumPiS_i, .Lfunc_end1-_Z32__device_stub__parallelPrefixSumPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x49742400 # float 1.0E+6
.LCPI2_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1325, %ecx # imm = 0x52D
movl $2684600343, %eax # imm = 0xA003C017
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
imull $3125, %ecx, %edx # imm = 0xC35
movq %rdx, %rcx
imulq %rax, %rcx
shrq $44, %rcx
imull $6553, %ecx, %esi # imm = 0x1999
movl %edx, %ecx
subl %esi, %ecx
negl %esi
addl %esi, %edx
addl $-1000, %edx # imm = 0xFC18
movslq %edx, %rdx
imulq $354224107, %rdx, %rsi # imm = 0x151D07EB
movq %rsi, %rdi
shrq $63, %rdi
sarq $35, %rsi
addl %edi, %esi
imull $97, %esi, %esi
subl %esi, %edx
movl %edx, (%rbx,%r12,4)
incq %r12
cmpq $2048, %r12 # imm = 0x800
jne .LBB2_1
# %bb.2:
callq clock
movq %rax, %r12
movl (%rbx), %eax
movl %eax, (%r14)
movl $1, %ecx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %eax
movl %eax, (%r14,%rcx,4)
incq %rcx
cmpq $2048, %rcx # imm = 0x800
jne .LBB2_3
# %bb.4: # %_Z12prefixSumCPUPiS_i.exit
callq clock
subq %r12, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI2_0(%rip), %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, 40(%rsp) # 4-byte Spill
leaq 32(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 32(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl $2048, 44(%rsp) # imm = 0x800
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17parallelPrefixSumPiS_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 40(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
movss 48(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm1
divss %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtss2sd %xmm3, %xmm2
movl $.L.str, %edi
movb $3, %al
callq printf
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %eax
cmpl (%r15,%r12,4), %eax
jne .LBB2_10
# %bb.8: # in Loop: Header=BB2_7 Depth=1
incq %r12
cmpq $2048, %r12 # imm = 0x800
jne .LBB2_7
# %bb.9:
movl $.Lstr.1, %edi
jmp .LBB2_11
.LBB2_10:
movl $.Lstr, %edi
.LBB2_11: # %.critedge
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17parallelPrefixSumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17parallelPrefixSumPiS_i,@object # @_Z17parallelPrefixSumPiS_i
.section .rodata,"a",@progbits
.globl _Z17parallelPrefixSumPiS_i
.p2align 3, 0x0
_Z17parallelPrefixSumPiS_i:
.quad _Z32__device_stub__parallelPrefixSumPiS_i
.size _Z17parallelPrefixSumPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
.size .L.str, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17parallelPrefixSumPiS_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST FAILED"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "TEST PASSED"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__parallelPrefixSumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17parallelPrefixSumPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17parallelPrefixSumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x001fc800078e00ff */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fc800078e0203 */
/*0070*/ IMAD.WIDE.U32 R6, R2.reuse, R13, c[0x0][0x160] ; /* 0x0000580002067625 */
/* 0x040fe200078e000d */
/*0080*/ IADD3 R0, R2, c[0x0][0x0], RZ ; /* 0x0000000002007a10 */
/* 0x000fc80007ffe0ff */
/*0090*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R8, R0, R13, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fcc00078e000d */
/*00b0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ SHF.L.U32 R11, R3, 0x2, RZ ; /* 0x00000002030b7819 */
/* 0x000fca00000006ff */
/*00d0*/ IMAD R4, R13, c[0x0][0x0], R11 ; /* 0x000000000d047a24 */
/* 0x000fe400078e020b */
/*00e0*/ IMAD.SHL.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057824 */
/* 0x000fca00078e00ff */
/*00f0*/ ISETP.GT.AND P0, PT, R5, 0x7fe, PT ; /* 0x000007fe0500780c */
/* 0x000fe40003f04270 */
/*0100*/ IADD3 R14, R11, 0x3, RZ ; /* 0x000000030b0e7810 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GT.AND P1, PT, R14, 0x7ff, PT ; /* 0x000007ff0e00780c */
/* 0x000fe40003f24270 */
/*0120*/ IADD3 R6, R5, 0x2, RZ ; /* 0x0000000205067810 */
/* 0x001fca0007ffe0ff */
/*0130*/ IMAD.SHL.U32 R7, R6, 0x2, RZ ; /* 0x0000000206077824 */
/* 0x000fe200078e00ff */
/*0140*/ STS [R3.X4], R10 ; /* 0x0000000a03007388 */
/* 0x004fe80000004800 */
/*0150*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x008fe80000000800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P0 LDS.64 R12, [R3.X8] ; /* 0x00000000030c8984 */
/* 0x000e240000008a00 */
/*0180*/ @!P0 IMAD.IADD R12, R12, 0x1, R13 ; /* 0x000000010c0c8824 */
/* 0x001fca00078e020d */
/*0190*/ @!P0 STS [R3.X8+0x4], R12 ; /* 0x0000040c03008388 */
/* 0x000fe80000008800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ @!P1 LDS R8, [R6.X8+-0xc] ; /* 0xfffff40006089984 */
/* 0x000fe80000008800 */
/*01c0*/ @!P1 LDS R11, [R6.X8+-0x4] ; /* 0xfffffc00060b9984 */
/* 0x000e220000008800 */
/*01d0*/ IMAD.IADD R9, R7, 0x1, R14 ; /* 0x0000000107097824 */
/* 0x000fca00078e020e */
/*01e0*/ ISETP.GT.AND P0, PT, R9, 0x7ff, PT ; /* 0x000007ff0900780c */
/* 0x000fe20003f04270 */
/*01f0*/ @!P1 IMAD.IADD R11, R8, 0x1, R11 ; /* 0x00000001080b9824 */
/* 0x001fca00078e020b */
/*0200*/ @!P1 STS [R6.X8+-0x4], R11 ; /* 0xfffffc0b06009388 */
/* 0x000fe80000008800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0220*/ @!P0 LDS R10, [R6.X16+-0x14] ; /* 0xffffec00060a8984 */
/* 0x000fe8000000c800 */
/*0230*/ @!P0 LDS R13, [R6.X16+-0x4] ; /* 0xfffffc00060d8984 */
/* 0x000e22000000c800 */
/*0240*/ SHF.L.U32 R8, R6, 0x2, RZ ; /* 0x0000000206087819 */
/* 0x000fca00000006ff */
/*0250*/ IMAD.IADD R15, R9, 0x1, R8 ; /* 0x00000001090f7824 */
/* 0x000fca00078e0208 */
/*0260*/ ISETP.GT.AND P1, PT, R15, 0x7ff, PT ; /* 0x000007ff0f00780c */
/* 0x000fe20003f24270 */
/*0270*/ IMAD.SHL.U32 R9, R6, 0x20, RZ ; /* 0x0000002006097824 */
/* 0x000fe400078e00ff */
/*0280*/ @!P0 IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d8824 */
/* 0x001fca00078e020d */
/*0290*/ @!P0 STS [R6.X16+-0x4], R13 ; /* 0xfffffc0d06008388 */
/* 0x000fe8000000c800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ @!P1 LDS R11, [R9+-0x24] ; /* 0xffffdc00090b9984 */
/* 0x000fe80000000800 */
/*02c0*/ @!P1 LDS R12, [R9+-0x4] ; /* 0xfffffc00090c9984 */
/* 0x000e220000000800 */
/*02d0*/ IMAD.SHL.U32 R10, R6, 0x8, RZ ; /* 0x00000008060a7824 */
/* 0x000fca00078e00ff */
/*02e0*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x000fc80007ffe0ff */
/*02f0*/ ISETP.GT.AND P0, PT, R15, 0x7ff, PT ; /* 0x000007ff0f00780c */
/* 0x000fe20003f04270 */
/*0300*/ @!P1 IMAD.IADD R14, R11, 0x1, R12 ; /* 0x000000010b0e9824 */
/* 0x001fca00078e020c */
/*0310*/ @!P1 STS [R9+-0x4], R14 ; /* 0xfffffc0e09009388 */
/* 0x000fe20000000800 */
/*0320*/ IMAD.SHL.U32 R11, R6, 0x40, RZ ; /* 0x00000040060b7824 */
/* 0x000fc600078e00ff */
/*0330*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0340*/ @!P0 LDS R13, [R11+-0x44] ; /* 0xffffbc000b0d8984 */
/* 0x000fe80000000800 */
/*0350*/ @!P0 LDS R16, [R11+-0x4] ; /* 0xfffffc000b108984 */
/* 0x000e220000000800 */
/*0360*/ IMAD.SHL.U32 R12, R6, 0x10, RZ ; /* 0x00000010060c7824 */
/* 0x000fc800078e00ff */
/*0370*/ IMAD.IADD R18, R12, 0x1, R15 ; /* 0x000000010c127824 */
/* 0x000fca00078e020f */
/*0380*/ ISETP.GT.AND P1, PT, R18, 0x7ff, PT ; /* 0x000007ff1200780c */
/* 0x000fe40003f24270 */
/*0390*/ @!P0 IADD3 R16, R13, R16, RZ ; /* 0x000000100d108210 */
/* 0x001fca0007ffe0ff */
/*03a0*/ @!P0 STS [R11+-0x4], R16 ; /* 0xfffffc100b008388 */
/* 0x000fe20000000800 */
/*03b0*/ IMAD.SHL.U32 R13, R6, 0x80, RZ ; /* 0x00000080060d7824 */
/* 0x000fc600078e00ff */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ @!P1 LDS R14, [R13+-0x84] ; /* 0xffff7c000d0e9984 */
/* 0x000fe80000000800 */
/*03e0*/ @!P1 LDS R15, [R13+-0x4] ; /* 0xfffffc000d0f9984 */
/* 0x000e220000000800 */
/*03f0*/ IMAD.IADD R18, R9, 0x1, R18 ; /* 0x0000000109127824 */
/* 0x000fca00078e0212 */
/*0400*/ ISETP.GT.AND P0, PT, R18, 0x7ff, PT ; /* 0x000007ff1200780c */
/* 0x000fe20003f04270 */
/*0410*/ @!P1 IMAD.IADD R18, R14, 0x1, R15 ; /* 0x000000010e129824 */
/* 0x001fca00078e020f */
/*0420*/ @!P1 STS [R13+-0x4], R18 ; /* 0xfffffc120d009388 */
/* 0x000fe20000000800 */
/*0430*/ IMAD.SHL.U32 R14, R6, 0x100, RZ ; /* 0x00000100060e7824 */
/* 0x000fc600078e00ff */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0450*/ @!P0 LDS R15, [R14+-0x104] ; /* 0xfffefc000e0f8984 */
/* 0x000fe80000000800 */
/*0460*/ @!P0 LDS R16, [R14+-0x4] ; /* 0xfffffc000e108984 */
/* 0x000e220000000800 */
/*0470*/ IADD3 R17, R13, -0x1, RZ ; /* 0xffffffff0d117810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.GT.AND P1, PT, R17, 0x7ff, PT ; /* 0x000007ff1100780c */
/* 0x000fe40003f24270 */
/*0490*/ @!P0 IADD3 R17, R15, R16, RZ ; /* 0x000000100f118210 */
/* 0x001fca0007ffe0ff */
/*04a0*/ @!P0 STS [R14+-0x4], R17 ; /* 0xfffffc110e008388 */
/* 0x000fe20000000800 */
/*04b0*/ IMAD.SHL.U32 R15, R6, 0x200, RZ ; /* 0x00000200060f7824 */
/* 0x000fc600078e00ff */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ @!P1 LDS R16, [R15+-0x204] ; /* 0xfffdfc000f109984 */
/* 0x000fe80000000800 */
/*04e0*/ @!P1 LDS R19, [R15+-0x4] ; /* 0xfffffc000f139984 */
/* 0x000e220000000800 */
/*04f0*/ IADD3 R18, R14, -0x1, RZ ; /* 0xffffffff0e127810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.GT.AND P0, PT, R18, 0x7ff, PT ; /* 0x000007ff1200780c */
/* 0x000fe20003f04270 */
/*0510*/ @!P1 IMAD.IADD R18, R16, 0x1, R19 ; /* 0x0000000110129824 */
/* 0x001fca00078e0213 */
/*0520*/ @!P1 STS [R15+-0x4], R18 ; /* 0xfffffc120f009388 */
/* 0x000fe20000000800 */
/*0530*/ IMAD.SHL.U32 R16, R6, 0x400, RZ ; /* 0x0000040006107824 */
/* 0x000fc600078e00ff */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @!P0 LDS R19, [R16+-0x404] ; /* 0xfffbfc0010138984 */
/* 0x000fe80000000800 */
/*0560*/ @!P0 LDS R20, [R16+-0x4] ; /* 0xfffffc0010148984 */
/* 0x000e220000000800 */
/*0570*/ IADD3 R17, R15, -0x1, RZ ; /* 0xffffffff0f117810 */
/* 0x000fc80007ffe0ff */
/*0580*/ ISETP.GT.AND P1, PT, R17, 0x7ff, PT ; /* 0x000007ff1100780c */
/* 0x000fe20003f24270 */
/*0590*/ IMAD.SHL.U32 R17, R6, 0x800, RZ ; /* 0x0000080006117824 */
/* 0x000fe200078e00ff */
/*05a0*/ @!P0 IADD3 R19, R19, R20, RZ ; /* 0x0000001413138210 */
/* 0x001fca0007ffe0ff */
/*05b0*/ @!P0 STS [R16+-0x4], R19 ; /* 0xfffffc1310008388 */
/* 0x000fe80000000800 */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05d0*/ @!P1 LDS R20, [R17+-0x804] ; /* 0xfff7fc0011149984 */
/* 0x000fe80000000800 */
/*05e0*/ @!P1 LDS R21, [R17+-0x4] ; /* 0xfffffc0011159984 */
/* 0x000e220000000800 */
/*05f0*/ IADD3 R18, R16, -0x1, RZ ; /* 0xffffffff10127810 */
/* 0x000fc80007ffe0ff */
/*0600*/ ISETP.GT.AND P0, PT, R18, 0x7ff, PT ; /* 0x000007ff1200780c */
/* 0x000fe20003f04270 */
/*0610*/ IMAD.SHL.U32 R22, R5, 0x1000, RZ ; /* 0x0000100005167824 */
/* 0x000fe400078e00ff */
/*0620*/ @!P1 IMAD.IADD R20, R20, 0x1, R21 ; /* 0x0000000114149824 */
/* 0x001fca00078e0215 */
/*0630*/ @!P1 STS [R17+-0x4], R20 ; /* 0xfffffc1411009388 */
/* 0x000fe80000000800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ @!P0 LDS R5, [R22+0x1ffc] ; /* 0x001ffc0016058984 */
/* 0x000fe80000000800 */
/*0660*/ @!P0 LDS R18, [R22+0xffc] ; /* 0x000ffc0016128984 */
/* 0x000e220000000800 */
/*0670*/ ISETP.GT.AND P1, PT, R15, 0x600, PT ; /* 0x000006000f00780c */
/* 0x000fc40003f24270 */
/*0680*/ @!P0 IADD3 R5, R5, R18, RZ ; /* 0x0000001205058210 */
/* 0x001fca0007ffe0ff */
/*0690*/ @!P0 STS [R22+0x1ffc], R5 ; /* 0x001ffc0516008388 */
/* 0x000fe80000000800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ @!P1 LDS R18, [R17+0x7fc] ; /* 0x0007fc0011129984 */
/* 0x000fe80000000800 */
/*06c0*/ @!P1 LDS R19, [R17+-0x4] ; /* 0xfffffc0011139984 */
/* 0x000e220000000800 */
/*06d0*/ ISETP.GT.AND P0, PT, R14, 0x700, PT ; /* 0x000007000e00780c */
/* 0x000fe20003f04270 */
/*06e0*/ @!P1 IMAD.IADD R18, R18, 0x1, R19 ; /* 0x0000000112129824 */
/* 0x001fca00078e0213 */
/*06f0*/ @!P1 STS [R17+0x7fc], R18 ; /* 0x0007fc1211009388 */
/* 0x000fe80000000800 */
/*0700*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0710*/ @!P0 LDS R19, [R16+0x3fc] ; /* 0x0003fc0010138984 */
/* 0x000fe80000000800 */
/*0720*/ @!P0 LDS R20, [R16+-0x4] ; /* 0xfffffc0010148984 */
/* 0x000e220000000800 */
/*0730*/ ISETP.GT.AND P1, PT, R13, 0x780, PT ; /* 0x000007800d00780c */
/* 0x000fe20003f24270 */
/*0740*/ @!P0 IMAD.IADD R19, R19, 0x1, R20 ; /* 0x0000000113138824 */
/* 0x001fca00078e0214 */
/*0750*/ @!P0 STS [R16+0x3fc], R19 ; /* 0x0003fc1310008388 */
/* 0x000fe80000000800 */
/*0760*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0770*/ @!P1 LDS R5, [R15+0x1fc] ; /* 0x0001fc000f059984 */
/* 0x000fe80000000800 */
/*0780*/ @!P1 LDS R20, [R15+-0x4] ; /* 0xfffffc000f149984 */
/* 0x000e220000000800 */
/*0790*/ ISETP.GT.AND P0, PT, R11, 0x7c0, PT ; /* 0x000007c00b00780c */
/* 0x000fe20003f04270 */
/*07a0*/ @!P1 IMAD.IADD R20, R5, 0x1, R20 ; /* 0x0000000105149824 */
/* 0x001fca00078e0214 */
/*07b0*/ @!P1 STS [R15+0x1fc], R20 ; /* 0x0001fc140f009388 */
/* 0x000fe80000000800 */
/*07c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07d0*/ @!P0 LDS R5, [R14+0xfc] ; /* 0x0000fc000e058984 */
/* 0x000fe80000000800 */
/*07e0*/ @!P0 LDS R18, [R14+-0x4] ; /* 0xfffffc000e128984 */
/* 0x000e220000000800 */
/*07f0*/ ISETP.GT.AND P1, PT, R9, 0x7e0, PT ; /* 0x000007e00900780c */
/* 0x000fc40003f24270 */
/*0800*/ @!P0 IADD3 R5, R5, R18, RZ ; /* 0x0000001205058210 */
/* 0x001fca0007ffe0ff */
/*0810*/ @!P0 STS [R14+0xfc], R5 ; /* 0x0000fc050e008388 */
/* 0x000fe80000000800 */
/*0820*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0830*/ @!P1 LDS R16, [R13+0x7c] ; /* 0x00007c000d109984 */
/* 0x000fe80000000800 */
/*0840*/ @!P1 LDS R17, [R13+-0x4] ; /* 0xfffffc000d119984 */
/* 0x000e220000000800 */
/*0850*/ ISETP.GT.AND P0, PT, R12, 0x7f0, PT ; /* 0x000007f00c00780c */
/* 0x000fe20003f04270 */
/*0860*/ @!P1 IMAD.IADD R16, R16, 0x1, R17 ; /* 0x0000000110109824 */
/* 0x001fca00078e0211 */
/*0870*/ @!P1 STS [R13+0x7c], R16 ; /* 0x00007c100d009388 */
/* 0x000fe80000000800 */
/*0880*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0890*/ @!P0 LDS R12, [R11+0x3c] ; /* 0x00003c000b0c8984 */
/* 0x000fe80000000800 */
/*08a0*/ @!P0 LDS R15, [R11+-0x4] ; /* 0xfffffc000b0f8984 */
/* 0x000e220000000800 */
/*08b0*/ ISETP.GT.AND P1, PT, R10, 0x7f8, PT ; /* 0x000007f80a00780c */
/* 0x000fe20003f24270 */
/*08c0*/ @!P0 IMAD.IADD R12, R12, 0x1, R15 ; /* 0x000000010c0c8824 */
/* 0x001fca00078e020f */
/*08d0*/ @!P0 STS [R11+0x3c], R12 ; /* 0x00003c0c0b008388 */
/* 0x000fe80000000800 */
/*08e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08f0*/ @!P1 LDS R5, [R9+0x1c] ; /* 0x00001c0009059984 */
/* 0x000fe80000000800 */
/*0900*/ @!P1 LDS R10, [R9+-0x4] ; /* 0xfffffc00090a9984 */
/* 0x000e220000000800 */
/*0910*/ ISETP.GT.AND P0, PT, R8, 0x7fc, PT ; /* 0x000007fc0800780c */
/* 0x000fe20003f04270 */
/*0920*/ @!P1 IMAD.IADD R10, R5, 0x1, R10 ; /* 0x00000001050a9824 */
/* 0x001fca00078e020a */
/*0930*/ @!P1 STS [R9+0x1c], R10 ; /* 0x00001c0a09009388 */
/* 0x000fe80000000800 */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ @!P0 LDS R5, [R6.X16+0xc] ; /* 0x00000c0006058984 */
/* 0x000fe8000000c800 */
/*0960*/ @!P0 LDS R8, [R6.X16+-0x4] ; /* 0xfffffc0006088984 */
/* 0x000e22000000c800 */
/*0970*/ ISETP.GT.AND P1, PT, R7, 0x7fe, PT ; /* 0x000007fe0700780c */
/* 0x000fc40003f24270 */
/*0980*/ @!P0 IADD3 R5, R5, R8, RZ ; /* 0x0000000805058210 */
/* 0x001fca0007ffe0ff */
/*0990*/ @!P0 STS [R6.X16+0xc], R5 ; /* 0x00000c0506008388 */
/* 0x000fe8000000c800 */
/*09a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09b0*/ @!P1 LDS R7, [R6.X8+0x4] ; /* 0x0000040006079984 */
/* 0x000fe80000008800 */
/*09c0*/ @!P1 LDS R8, [R6.X8+-0x4] ; /* 0xfffffc0006089984 */
/* 0x000e220000008800 */
/*09d0*/ ISETP.GT.AND P0, PT, R6, 0x7ff, PT ; /* 0x000007ff0600780c */
/* 0x000fe20003f04270 */
/*09e0*/ @!P1 IMAD.IADD R7, R7, 0x1, R8 ; /* 0x0000000107079824 */
/* 0x001fca00078e0208 */
/*09f0*/ @!P1 STS [R6.X8+0x4], R7 ; /* 0x0000040706009388 */
/* 0x000fe80000008800 */
/*0a00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a10*/ @!P0 LDS R8, [R3.X8+0x8] ; /* 0x0000080003088984 */
/* 0x000fe80000008800 */
/*0a20*/ @!P0 LDS R9, [R3.X8+0x4] ; /* 0x0000040003098984 */
/* 0x000e240000008800 */
/*0a30*/ @!P0 IMAD.IADD R12, R8, 0x1, R9 ; /* 0x00000001080c8824 */
/* 0x001fca00078e0209 */
/*0a40*/ @!P0 STS [R3.X8+0x8], R12 ; /* 0x0000080c03008388 */
/* 0x000fe80000008800 */
/*0a50*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a60*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000e280000004800 */
/*0a70*/ LDS R13, [R4] ; /* 0x00000000040d7984 */
/* 0x000e620000000800 */
/*0a80*/ LEA R8, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002087a11 */
/* 0x000fc400078010ff */
/*0a90*/ LEA R10, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a00000a7a11 */
/* 0x000fe400078210ff */
/*0aa0*/ LEA.HI.X R9, R2, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0002097a11 */
/* 0x000fe400000f14ff */
/*0ab0*/ LEA.HI.X R11, R0, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b00000b7a11 */
/* 0x000fc600008f14ff */
/*0ac0*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x001fe8000c101904 */
/*0ad0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x002fe2000c101904 */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17parallelPrefixSumPiS_i
.globl _Z17parallelPrefixSumPiS_i
.p2align 8
.type _Z17parallelPrefixSumPiS_i,@function
_Z17parallelPrefixSumPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, s4, v0
s_mul_i32 s15, s15, s4
s_lshl_b32 s5, s15, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v1, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s5, v9
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_clause 0x1
global_load_b32 v10, v[5:6], off
global_load_b32 v8, v[7:8], off
v_lshlrev_b32_e32 v6, 2, v0
v_lshlrev_b32_e32 v5, 2, v9
v_add_nc_u32_e32 v7, 1, v0
s_mov_b32 s2, 1
s_waitcnt vmcnt(1)
ds_store_b32 v6, v10
s_waitcnt vmcnt(0)
ds_store_b32 v5, v8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s3
s_lshl_b32 s3, s2, 1
s_cmpk_gt_u32 s2, 0x200
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_2:
v_mul_lo_u32 v8, s2, v7
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x401, v8
s_cbranch_execz .LBB0_1
v_lshl_add_u32 v8, v8, 1, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s2, v8
v_lshlrev_b32_e32 v8, 2, v8
v_lshlrev_b32_e32 v9, 2, v9
ds_load_b32 v9, v9
ds_load_b32 v10, v8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v9, v10, v9
ds_store_b32 v8, v9
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_lshl_add_u32 v0, v0, 1, 2
s_movk_i32 s2, 0x200
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u32_u24 v8, v0, s2, -1
s_mov_b32 s3, exec_lo
v_add_nc_u32_e32 v7, s2, v8
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x800, v7
s_cbranch_execz .LBB0_5
v_lshlrev_b32_e32 v8, 2, v8
v_lshlrev_b32_e32 v7, 2, v7
ds_load_b32 v8, v8
ds_load_b32 v9, v7
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v8, v9, v8
ds_store_b32 v7, v8
s_branch .LBB0_5
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v6, v6
ds_load_b32 v5, v5
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17parallelPrefixSumPiS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17parallelPrefixSumPiS_i, .Lfunc_end0-_Z17parallelPrefixSumPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17parallelPrefixSumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17parallelPrefixSumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008e098_00000000-6_flemingPrefixSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12prefixSumCPUPiS_i
.type _Z12prefixSumCPUPiS_i, @function
_Z12prefixSumCPUPiS_i:
.LFB2057:
.cfi_startproc
endbr64
movl (%rdi), %eax
movl %eax, (%rsi)
cmpl $1, %edx
jle .L3
movl %edx, %edx
movl $1, %eax
.L5:
movl (%rdi,%rax,4), %ecx
addl -4(%rsi,%rax,4), %ecx
movl %ecx, (%rsi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z12prefixSumCPUPiS_i, .-_Z12prefixSumCPUPiS_i
.globl _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i
.type _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i, @function
_Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17parallelPrefixSumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i, .-_Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i
.globl _Z17parallelPrefixSumPiS_i
.type _Z17parallelPrefixSumPiS_i, @function
_Z17parallelPrefixSumPiS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17parallelPrefixSumPiS_i, .-_Z17parallelPrefixSumPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "TEST PASSED\n"
.LC4:
.string "TEST FAILED\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
movl $8192, %edi
call malloc@PLT
movq %rax, %r12
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %ecx
movl $1325, %eax
.L16:
imull $3125, %eax, %edx
movslq %edx, %rax
imulq $-1610366953, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $12, %eax
movl %edx, %esi
sarl $31, %esi
subl %esi, %eax
imull $6553, %eax, %esi
movl %edx, %eax
subl %esi, %eax
leal -1000(%rax), %esi
movslq %esi, %rdx
imulq $354224107, %rdx, %rdx
sarq $35, %rdx
movl %esi, %edi
sarl $31, %edi
subl %edi, %edx
imull $97, %edx, %edx
subl %edx, %esi
movl %esi, 0(%rbp,%rcx)
movl $0, (%rbx,%rcx)
addq $4, %rcx
cmpq $8192, %rcx
jne .L16
call clock@PLT
movq %rax, %r13
movl $2048, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z12prefixSumCPUPiS_i
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 12(%rsp)
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 64(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $8192, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movss 28(%rsp), %xmm1
movss 12(%rsp), %xmm3
movaps %xmm3, %xmm2
divss %xmm1, %xmm2
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $0, %eax
.L19:
movl (%rbx,%rax), %ecx
cmpl %ecx, (%r12,%rax)
jne .L18
addq $4, %rax
cmpq $8192, %rax
jne .L19
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $2048, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z40__device_stub__Z17parallelPrefixSumPiS_iPiS_i
jmp .L17
.L18:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z17parallelPrefixSumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17parallelPrefixSumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1232348160
.align 4
.LC1:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "flemingPrefixSum.hip"
.globl _Z12prefixSumCPUPiS_i # -- Begin function _Z12prefixSumCPUPiS_i
.p2align 4, 0x90
.type _Z12prefixSumCPUPiS_i,@function
_Z12prefixSumCPUPiS_i: # @_Z12prefixSumCPUPiS_i
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
movl %eax, (%rsi)
cmpl $2, %edx
jl .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
movl (%rsi), %ecx
movl $1, %edx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rdx,4), %ecx
movl %ecx, (%rsi,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z12prefixSumCPUPiS_i, .Lfunc_end0-_Z12prefixSumCPUPiS_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__parallelPrefixSumPiS_i # -- Begin function _Z32__device_stub__parallelPrefixSumPiS_i
.p2align 4, 0x90
.type _Z32__device_stub__parallelPrefixSumPiS_i,@function
_Z32__device_stub__parallelPrefixSumPiS_i: # @_Z32__device_stub__parallelPrefixSumPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17parallelPrefixSumPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z32__device_stub__parallelPrefixSumPiS_i, .Lfunc_end1-_Z32__device_stub__parallelPrefixSumPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x49742400 # float 1.0E+6
.LCPI2_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1325, %ecx # imm = 0x52D
movl $2684600343, %eax # imm = 0xA003C017
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
imull $3125, %ecx, %edx # imm = 0xC35
movq %rdx, %rcx
imulq %rax, %rcx
shrq $44, %rcx
imull $6553, %ecx, %esi # imm = 0x1999
movl %edx, %ecx
subl %esi, %ecx
negl %esi
addl %esi, %edx
addl $-1000, %edx # imm = 0xFC18
movslq %edx, %rdx
imulq $354224107, %rdx, %rsi # imm = 0x151D07EB
movq %rsi, %rdi
shrq $63, %rdi
sarq $35, %rsi
addl %edi, %esi
imull $97, %esi, %esi
subl %esi, %edx
movl %edx, (%rbx,%r12,4)
incq %r12
cmpq $2048, %r12 # imm = 0x800
jne .LBB2_1
# %bb.2:
callq clock
movq %rax, %r12
movl (%rbx), %eax
movl %eax, (%r14)
movl $1, %ecx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %eax
movl %eax, (%r14,%rcx,4)
incq %rcx
cmpq $2048, %rcx # imm = 0x800
jne .LBB2_3
# %bb.4: # %_Z12prefixSumCPUPiS_i.exit
callq clock
subq %r12, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI2_0(%rip), %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, 40(%rsp) # 4-byte Spill
leaq 32(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 32(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl $2048, 44(%rsp) # imm = 0x800
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17parallelPrefixSumPiS_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 40(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
movss 48(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm1
divss %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtss2sd %xmm3, %xmm2
movl $.L.str, %edi
movb $3, %al
callq printf
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %eax
cmpl (%r15,%r12,4), %eax
jne .LBB2_10
# %bb.8: # in Loop: Header=BB2_7 Depth=1
incq %r12
cmpq $2048, %r12 # imm = 0x800
jne .LBB2_7
# %bb.9:
movl $.Lstr.1, %edi
jmp .LBB2_11
.LBB2_10:
movl $.Lstr, %edi
.LBB2_11: # %.critedge
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17parallelPrefixSumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17parallelPrefixSumPiS_i,@object # @_Z17parallelPrefixSumPiS_i
.section .rodata,"a",@progbits
.globl _Z17parallelPrefixSumPiS_i
.p2align 3, 0x0
_Z17parallelPrefixSumPiS_i:
.quad _Z32__device_stub__parallelPrefixSumPiS_i
.size _Z17parallelPrefixSumPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
.size .L.str, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17parallelPrefixSumPiS_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST FAILED"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "TEST PASSED"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__parallelPrefixSumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17parallelPrefixSumPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
//extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
}
int main() {
const int N = 1<<20;
float *x, *y, *z, *dx, *dy, *dz;
//printf("hello world\n");
cudaMalloc((void**)&dx, N*sizeof(float));
cudaMalloc((void**)&dy, N*sizeof(float));
cudaMalloc((void**)&dz, N*sizeof(float));
// init array x, y
for (int i=0; i<N; i++) {
x[i] = 2.3f*i;
y[i] = 4.1f*i;
}
cudaMemcpy(dx, x, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dy, y, N*sizeof(float), cudaMemcpyHostToDevice);
runKernel(N, dx, dy, dz);
cudaMemcpy(z, dz, N*sizeof(float), cudaMemcpyDeviceToHost);
//printf("hello world\n");
cudaFree(dx);
cudaFree(dy);
cudaFree(dz);
//printf("hello world\n");
free(x);
free(y);
free(z);
//printf("hello world\n");
return 0;
} | code for sm_80
Function : _Z21cudaMultVectorsKerneliPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
//extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
}
int main() {
const int N = 1<<20;
float *x, *y, *z, *dx, *dy, *dz;
//printf("hello world\n");
cudaMalloc((void**)&dx, N*sizeof(float));
cudaMalloc((void**)&dy, N*sizeof(float));
cudaMalloc((void**)&dz, N*sizeof(float));
// init array x, y
for (int i=0; i<N; i++) {
x[i] = 2.3f*i;
y[i] = 4.1f*i;
}
cudaMemcpy(dx, x, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dy, y, N*sizeof(float), cudaMemcpyHostToDevice);
runKernel(N, dx, dy, dz);
cudaMemcpy(z, dz, N*sizeof(float), cudaMemcpyDeviceToHost);
//printf("hello world\n");
cudaFree(dx);
cudaFree(dy);
cudaFree(dz);
//printf("hello world\n");
free(x);
free(y);
free(z);
//printf("hello world\n");
return 0;
} | .file "tmpxft_00008fd0_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
.type _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_, @function
_Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21cudaMultVectorsKerneliPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_, .-_Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
.globl _Z21cudaMultVectorsKerneliPfS_S_
.type _Z21cudaMultVectorsKerneliPfS_S_, @function
_Z21cudaMultVectorsKerneliPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z21cudaMultVectorsKerneliPfS_S_, .-_Z21cudaMultVectorsKerneliPfS_S_
.globl _Z9runKerneliPfS_S_
.type _Z9runKerneliPfS_S_, @function
_Z9runKerneliPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movl $512, 20(%rsp)
movl $1, 24(%rsp)
leal 1022(%rdi), %eax
movl %edi, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z9runKerneliPfS_S_, .-_Z9runKerneliPfS_S_
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
.L16:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm2, %xmm0
movss %xmm0, 0(,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L16
movl $1, %ecx
movl $4194304, %edx
movl $0, %r12d
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movl $0, %ebp
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1048576, %edi
call _Z9runKerneliPfS_S_
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movl $0, %ebx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z21cudaMultVectorsKerneliPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21cudaMultVectorsKerneliPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1075000115
.align 4
.LC1:
.long 1082340147
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
//extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
}
int main() {
const int N = 1<<20;
float *x, *y, *z, *dx, *dy, *dz;
//printf("hello world\n");
cudaMalloc((void**)&dx, N*sizeof(float));
cudaMalloc((void**)&dy, N*sizeof(float));
cudaMalloc((void**)&dz, N*sizeof(float));
// init array x, y
for (int i=0; i<N; i++) {
x[i] = 2.3f*i;
y[i] = 4.1f*i;
}
cudaMemcpy(dx, x, N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dy, y, N*sizeof(float), cudaMemcpyHostToDevice);
runKernel(N, dx, dy, dz);
cudaMemcpy(z, dz, N*sizeof(float), cudaMemcpyDeviceToHost);
//printf("hello world\n");
cudaFree(dx);
cudaFree(dy);
cudaFree(dz);
//printf("hello world\n");
free(x);
free(y);
free(z);
//printf("hello world\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
//extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
}
int main() {
const int N = 1<<20;
float *x, *y, *z, *dx, *dy, *dz;
//printf("hello world\n");
hipMalloc((void**)&dx, N*sizeof(float));
hipMalloc((void**)&dy, N*sizeof(float));
hipMalloc((void**)&dz, N*sizeof(float));
// init array x, y
for (int i=0; i<N; i++) {
x[i] = 2.3f*i;
y[i] = 4.1f*i;
}
hipMemcpy(dx, x, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dy, y, N*sizeof(float), hipMemcpyHostToDevice);
runKernel(N, dx, dy, dz);
hipMemcpy(z, dz, N*sizeof(float), hipMemcpyDeviceToHost);
//printf("hello world\n");
hipFree(dx);
hipFree(dy);
hipFree(dz);
//printf("hello world\n");
free(x);
free(y);
free(z);
//printf("hello world\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
//extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
}
int main() {
const int N = 1<<20;
float *x, *y, *z, *dx, *dy, *dz;
//printf("hello world\n");
hipMalloc((void**)&dx, N*sizeof(float));
hipMalloc((void**)&dy, N*sizeof(float));
hipMalloc((void**)&dz, N*sizeof(float));
// init array x, y
for (int i=0; i<N; i++) {
x[i] = 2.3f*i;
y[i] = 4.1f*i;
}
hipMemcpy(dx, x, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dy, y, N*sizeof(float), hipMemcpyHostToDevice);
runKernel(N, dx, dy, dz);
hipMemcpy(z, dz, N*sizeof(float), hipMemcpyDeviceToHost);
//printf("hello world\n");
hipFree(dx);
hipFree(dy);
hipFree(dz);
//printf("hello world\n");
free(x);
free(y);
free(z);
//printf("hello world\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21cudaMultVectorsKerneliPfS_S_
.globl _Z21cudaMultVectorsKerneliPfS_S_
.p2align 8
.type _Z21cudaMultVectorsKerneliPfS_S_,@function
_Z21cudaMultVectorsKerneliPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21cudaMultVectorsKerneliPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21cudaMultVectorsKerneliPfS_S_, .Lfunc_end0-_Z21cudaMultVectorsKerneliPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21cudaMultVectorsKerneliPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21cudaMultVectorsKerneliPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
//extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
}
int main() {
const int N = 1<<20;
float *x, *y, *z, *dx, *dy, *dz;
//printf("hello world\n");
hipMalloc((void**)&dx, N*sizeof(float));
hipMalloc((void**)&dy, N*sizeof(float));
hipMalloc((void**)&dz, N*sizeof(float));
// init array x, y
for (int i=0; i<N; i++) {
x[i] = 2.3f*i;
y[i] = 4.1f*i;
}
hipMemcpy(dx, x, N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dy, y, N*sizeof(float), hipMemcpyHostToDevice);
runKernel(N, dx, dy, dz);
hipMemcpy(z, dz, N*sizeof(float), hipMemcpyDeviceToHost);
//printf("hello world\n");
hipFree(dx);
hipFree(dy);
hipFree(dz);
//printf("hello world\n");
free(x);
free(y);
free(z);
//printf("hello world\n");
return 0;
} | .text
.file "main.hip"
.globl _Z36__device_stub__cudaMultVectorsKerneliPfS_S_ # -- Begin function _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.p2align 4, 0x90
.type _Z36__device_stub__cudaMultVectorsKerneliPfS_S_,@function
_Z36__device_stub__cudaMultVectorsKerneliPfS_S_: # @_Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21cudaMultVectorsKerneliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__cudaMultVectorsKerneliPfS_S_, .Lfunc_end0-_Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.cfi_endproc
# -- End function
.globl _Z9runKerneliPfS_S_ # -- Begin function _Z9runKerneliPfS_S_
.p2align 4, 0x90
.type _Z9runKerneliPfS_S_,@function
_Z9runKerneliPfS_S_: # @_Z9runKerneliPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movl %edi, %r12d
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl %r12d, 4(%rsp)
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21cudaMultVectorsKerneliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9runKerneliPfS_S_, .Lfunc_end1-_Z9runKerneliPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21cudaMultVectorsKerneliPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21cudaMultVectorsKerneliPfS_S_,@object # @_Z21cudaMultVectorsKerneliPfS_S_
.section .rodata,"a",@progbits
.globl _Z21cudaMultVectorsKerneliPfS_S_
.p2align 3, 0x0
_Z21cudaMultVectorsKerneliPfS_S_:
.quad _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.size _Z21cudaMultVectorsKerneliPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21cudaMultVectorsKerneliPfS_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21cudaMultVectorsKerneliPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21cudaMultVectorsKerneliPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21cudaMultVectorsKerneliPfS_S_
.globl _Z21cudaMultVectorsKerneliPfS_S_
.p2align 8
.type _Z21cudaMultVectorsKerneliPfS_S_,@function
_Z21cudaMultVectorsKerneliPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21cudaMultVectorsKerneliPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21cudaMultVectorsKerneliPfS_S_, .Lfunc_end0-_Z21cudaMultVectorsKerneliPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21cudaMultVectorsKerneliPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21cudaMultVectorsKerneliPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00008fd0_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
.type _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_, @function
_Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21cudaMultVectorsKerneliPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_, .-_Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
.globl _Z21cudaMultVectorsKerneliPfS_S_
.type _Z21cudaMultVectorsKerneliPfS_S_, @function
_Z21cudaMultVectorsKerneliPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z21cudaMultVectorsKerneliPfS_S_, .-_Z21cudaMultVectorsKerneliPfS_S_
.globl _Z9runKerneliPfS_S_
.type _Z9runKerneliPfS_S_, @function
_Z9runKerneliPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movl $512, 20(%rsp)
movl $1, 24(%rsp)
leal 1022(%rdi), %eax
movl %edi, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z9runKerneliPfS_S_, .-_Z9runKerneliPfS_S_
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
.L16:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm2, %xmm0
movss %xmm0, 0(,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L16
movl $1, %ecx
movl $4194304, %edx
movl $0, %r12d
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movl $0, %ebp
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1048576, %edi
call _Z9runKerneliPfS_S_
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movl $0, %ebx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z21cudaMultVectorsKerneliPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21cudaMultVectorsKerneliPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1075000115
.align 4
.LC1:
.long 1082340147
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z36__device_stub__cudaMultVectorsKerneliPfS_S_ # -- Begin function _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.p2align 4, 0x90
.type _Z36__device_stub__cudaMultVectorsKerneliPfS_S_,@function
_Z36__device_stub__cudaMultVectorsKerneliPfS_S_: # @_Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21cudaMultVectorsKerneliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__cudaMultVectorsKerneliPfS_S_, .Lfunc_end0-_Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.cfi_endproc
# -- End function
.globl _Z9runKerneliPfS_S_ # -- Begin function _Z9runKerneliPfS_S_
.p2align 4, 0x90
.type _Z9runKerneliPfS_S_,@function
_Z9runKerneliPfS_S_: # @_Z9runKerneliPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movl %edi, %r12d
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl %r12d, 4(%rsp)
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21cudaMultVectorsKerneliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9runKerneliPfS_S_, .Lfunc_end1-_Z9runKerneliPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21cudaMultVectorsKerneliPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21cudaMultVectorsKerneliPfS_S_,@object # @_Z21cudaMultVectorsKerneliPfS_S_
.section .rodata,"a",@progbits
.globl _Z21cudaMultVectorsKerneliPfS_S_
.p2align 3, 0x0
_Z21cudaMultVectorsKerneliPfS_S_:
.quad _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.size _Z21cudaMultVectorsKerneliPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21cudaMultVectorsKerneliPfS_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21cudaMultVectorsKerneliPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#include<time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
//*******************kernel********************
__global__ void kernel (int *B_d,float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int offset=idx + idy*blockDim.x*gridDim.x;
int id=offset;
int i;
float X=0.f,Xprom=0.f,Y=0.f;
int dimy=1388,tam_imag=1388*1040,msk=3;
var_d[id]=0;
if(offset<tam_imag){
int dimy_B=dimy+2;
offset+=2*idy;
int id_p=offset+(dimy+msk);
int M_d[9];
M_d[0]=B_d[offset];
M_d[1]=B_d[offset+1];
M_d[2]=B_d[offset+2];
M_d[3]=B_d[id_p-1];
M_d[4]=B_d[id_p];
M_d[5]=B_d[id_p+1];
M_d[6]=B_d[(id_p-1)+dimy_B];
M_d[7]=B_d[id_p+dimy_B];
M_d[8]=B_d[(id_p+1)+dimy_B];
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************funcion main**********************
int main(int argc,char* argv[]){
//***************declaracion de variables**************
int i,j,m,cont,tam_B, init,fin;
init=atoi(argv[1]);
fin=atoi(argv[2]);
tam_B=(dimx+2)*(dimy+2);
FILE *arch, *matrizG;
int **A;
int B[dimx+2][dimy+2];
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *B_d, *B_h;
float *var_d,*var_h;
int d;
for(d=init;d<=fin;d++){
//*******************declaracion de variables***************
printf("d=%d \n", d);
B_h=(int *)malloc(sizeof(int)*tam_B);
cudaMalloc((void**)&B_d, tam_B*sizeof(int));
var_h=(float *)malloc(sizeof(float)*tam_imag);
cudaMalloc((void**)&var_d,tam_imag*sizeof(float));
A=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++)
A[i]=(int*)malloc(sizeof(int)*dimy);
//*****************calculo matriz B****************
char ruta1[]="MiTesis/";
sprintf(ruta1, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(ruta1,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizG, "%d", &A[i][j]);
}
}
fclose(matrizG);
cont=0;
for(i=0;i<dimx+2;i++){
//printf("\n");
for(j=0;j<dimy+2;j++){
B[i][j]=((i==0 || j==0 || i==dimx+1 || j==dimy+1) ? 0:A[i-1][j-1]);
B_h[cont]=B[i][j];
cont++;
}
}
//******************llamado de kernel*******************
dim3 Grid(347,20);
dim3 Block(13,16);
cudaMemcpy(B_d,B_h,sizeof(int)*tam_B,cudaMemcpyHostToDevice);
kernel<<<Grid,Block>>>(B_d,var_d);
cudaMemcpy(var_h,var_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
//****************almacenamiento matriz de varianza**************
char rutaV[]="VARIANZAS/";
sprintf(rutaV, "%s%d", rutaV,d);
arch=fopen(rutaV,"w+");
for(m=0;m<tam_imag;m++){
if(m%dimy==0 && m!=0){
fprintf(arch,"\n");
}
fprintf(arch,"%f ",var_h[m]); // "%.2f " - Imprimiria 2 decimales
}
fclose(arch);
free(B_h);
free(var_h);
free(A);
cudaFree(var_d);
cudaFree(B_d);
}
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
return 0;
}//FIN funcion main() | code for sm_80
Function : _Z6kernelPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R2, R0, c[0x0][0xc], R5 ; /* 0x0000030000027a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R5, R2, c[0x0][0x0], R7 ; /* 0x0000000002057a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R5.reuse, R13, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x040fe200078e020d */
/*00b0*/ ISETP.GT.AND P0, PT, R5, 0x1606bf, PT ; /* 0x001606bf0500780c */
/* 0x000fc80003f04270 */
/*00c0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f2000c101904 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ LEA R12, R0, R5, 0x1 ; /* 0x00000005000c7211 */
/* 0x000fca00078e08ff */
/*00f0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e020d */
/*0100*/ LDG.E R0, [R12.64] ; /* 0x000000040c007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R5, [R12.64+0x4] ; /* 0x000004040c057981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R4, [R12.64+0x8] ; /* 0x000008040c047981 */
/* 0x000f28000c1e1900 */
/*0130*/ LDG.E R6, [R12.64+0x15b8] ; /* 0x0015b8040c067981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R7, [R12.64+0x15bc] ; /* 0x0015bc040c077981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R8, [R12.64+0x15c0] ; /* 0x0015c0040c087981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R9, [R12.64+0x2b70] ; /* 0x002b70040c097981 */
/* 0x000368000c1e1900 */
/*0170*/ LDG.E R10, [R12.64+0x2b74] ; /* 0x002b74040c0a7981 */
/* 0x000368000c1e1900 */
/*0180*/ LDG.E R15, [R12.64+0x2b78] ; /* 0x002b78040c0f7981 */
/* 0x000362000c1e1900 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, 0x3de38e39 ; /* 0x3de38e39ff107424 */
/* 0x000fe200078e00ff */
/*01a0*/ BSSY B0, 0x390 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*01b0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x004ff00000201400 */
/*01c0*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x008eb00000201400 */
/*01d0*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x010ef00000201400 */
/*01e0*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x020e620000201400 */
/*01f0*/ FADD R11, R0, R5 ; /* 0x00000005000b7221 */
/* 0x004fce0000000000 */
/*0200*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000ea20000201400 */
/*0210*/ FADD R11, R11, R4 ; /* 0x000000040b0b7221 */
/* 0x008fce0000000000 */
/*0220*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000ee20000201400 */
/*0230*/ FADD R12, R11, R6 ; /* 0x000000060b0c7221 */
/* 0x002fce0000000000 */
/*0240*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000e620000201400 */
/*0250*/ FADD R13, R12, R7 ; /* 0x000000070c0d7221 */
/* 0x004fe20000000000 */
/*0260*/ HFMA2.MMA R12, -RZ, RZ, 2.53125, 0 ; /* 0x41100000ff0c7435 */
/* 0x000fcc00000001ff */
/*0270*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000ea20000201400 */
/*0280*/ FADD R14, R13, R8 ; /* 0x000000080d0e7221 */
/* 0x008fce0000000000 */
/*0290*/ I2F R11, R15 ; /* 0x0000000f000b7306 */
/* 0x000ee20000201400 */
/*02a0*/ FADD R13, R14, R9 ; /* 0x000000090e0d7221 */
/* 0x002fc80000000000 */
/*02b0*/ FADD R14, R13, R10 ; /* 0x0000000a0d0e7221 */
/* 0x004fe40000000000 */
/*02c0*/ FFMA R13, R16, -R12, 1 ; /* 0x3f800000100d7423 */
/* 0x000fc8000000080c */
/*02d0*/ FFMA R13, R13, R16, 0.11111111193895339966 ; /* 0x3de38e390d0d7423 */
/* 0x000fe40000000010 */
/*02e0*/ FADD R14, R14, R11 ; /* 0x0000000b0e0e7221 */
/* 0x008fc80000000000 */
/*02f0*/ FCHK P0, R14, 9 ; /* 0x411000000e007902 */
/* 0x000e620000000000 */
/*0300*/ FFMA R15, R14, R13, RZ ; /* 0x0000000d0e0f7223 */
/* 0x000fc800000000ff */
/*0310*/ FFMA R16, R15, -9, R14 ; /* 0xc11000000f107823 */
/* 0x000fc8000000000e */
/*0320*/ FFMA R13, R13, R16, R15 ; /* 0x000000100d0d7223 */
/* 0x000fe2000000000f */
/*0330*/ @!P0 BRA 0x380 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0340*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000e */
/*0350*/ MOV R14, 0x370 ; /* 0x00000370000e7802 */
/* 0x000fe40000000f00 */
/*0360*/ CALL.REL.NOINC 0x5b0 ; /* 0x0000024000007944 */
/* 0x001fea0003c00000 */
/*0370*/ MOV R13, R12 ; /* 0x0000000c000d7202 */
/* 0x001fe40000000f00 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ FADD R0, -R0, R13.reuse ; /* 0x0000000d00007221 */
/* 0x100fe20000000100 */
/*03a0*/ HFMA2.MMA R12, -RZ, RZ, 2.53125, 0 ; /* 0x41100000ff0c7435 */
/* 0x000fe200000001ff */
/*03b0*/ FADD R5, -R5, R13.reuse ; /* 0x0000000d05057221 */
/* 0x100fe20000000100 */
/*03c0*/ BSSY B0, 0x590 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*03d0*/ FFMA R0, R0, R0, RZ ; /* 0x0000000000007223 */
/* 0x000fe400000000ff */
/*03e0*/ FADD R15, -R4, R13 ; /* 0x0000000d040f7221 */
/* 0x000fe40000000100 */
/*03f0*/ FFMA R0, R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fc40000000000 */
/*0400*/ FADD R5, -R6, R13.reuse ; /* 0x0000000d06057221 */
/* 0x100fe40000000100 */
/*0410*/ FFMA R0, R15, R15, R0 ; /* 0x0000000f0f007223 */
/* 0x000fe40000000000 */
/*0420*/ FADD R7, -R7, R13.reuse ; /* 0x0000000d07077221 */
/* 0x100fe40000000100 */
/*0430*/ FFMA R0, R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fe40000000000 */
/*0440*/ FADD R5, -R8, R13 ; /* 0x0000000d08057221 */
/* 0x000fe40000000100 */
/*0450*/ FFMA R0, R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x000fc40000000000 */
/*0460*/ FADD R9, -R9, R13.reuse ; /* 0x0000000d09097221 */
/* 0x100fe40000000100 */
/*0470*/ FFMA R0, R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fe40000000000 */
/*0480*/ FADD R5, -R10, R13.reuse ; /* 0x0000000d0a057221 */
/* 0x100fe40000000100 */
/*0490*/ FFMA R0, R9, R9, R0 ; /* 0x0000000909007223 */
/* 0x000fe40000000000 */
/*04a0*/ FADD R11, -R11, R13 ; /* 0x0000000d0b0b7221 */
/* 0x000fe40000000100 */
/*04b0*/ FFMA R0, R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fc40000000000 */
/*04c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3de38e39 ; /* 0x3de38e39ff077424 */
/* 0x000fe400078e00ff */
/*04d0*/ FFMA R16, R11, R11, R0 ; /* 0x0000000b0b107223 */
/* 0x000fe40000000000 */
/*04e0*/ FFMA R4, R7, -R12, 1 ; /* 0x3f80000007047423 */
/* 0x000fe4000000080c */
/*04f0*/ FCHK P0, R16, 9 ; /* 0x4110000010007902 */
/* 0x000e640000000000 */
/*0500*/ FFMA R7, R4, R7, 0.11111111193895339966 ; /* 0x3de38e3904077423 */
/* 0x000fc80000000007 */
/*0510*/ FFMA R0, R7, R16, RZ ; /* 0x0000001007007223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R5, R0, -9, R16 ; /* 0xc110000000057823 */
/* 0x000fc80000000010 */
/*0530*/ FFMA R5, R7, R5, R0 ; /* 0x0000000507057223 */
/* 0x000fe20000000000 */
/*0540*/ @!P0 BRA 0x580 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0550*/ MOV R14, 0x570 ; /* 0x00000570000e7802 */
/* 0x000fe40000000f00 */
/*0560*/ CALL.REL.NOINC 0x5b0 ; /* 0x0000004000007944 */
/* 0x001fea0003c00000 */
/*0570*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x001fe400078e000c */
/*0580*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0590*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ SHF.R.U32.HI R13, RZ, 0x17, R12 ; /* 0x00000017ff0d7819 */
/* 0x000fe2000001160c */
/*05c0*/ BSSY B1, 0xbf0 ; /* 0x0000062000017945 */
/* 0x000fe20003800000 */
/*05d0*/ SHF.R.U32.HI R15, RZ, 0x17, R16 ; /* 0x00000017ff0f7819 */
/* 0x000fe40000011610 */
/*05e0*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fe400078ec0ff */
/*05f0*/ LOP3.LUT R18, R15, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0f127812 */
/* 0x000fe400078ec0ff */
/*0600*/ IADD3 R17, R13, -0x1, RZ ; /* 0xffffffff0d117810 */
/* 0x000fc40007ffe0ff */
/*0610*/ IADD3 R19, R18, -0x1, RZ ; /* 0xffffffff12137810 */
/* 0x000fe40007ffe0ff */
/*0620*/ ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ; /* 0x000000fd1100780c */
/* 0x000fc80003f04070 */
/*0630*/ ISETP.GT.U32.OR P0, PT, R19, 0xfd, P0 ; /* 0x000000fd1300780c */
/* 0x000fda0000704470 */
/*0640*/ @!P0 MOV R15, RZ ; /* 0x000000ff000f8202 */
/* 0x000fe20000000f00 */
/*0650*/ @!P0 BRA 0x7d0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0660*/ FSETP.GTU.FTZ.AND P0, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fe40003f1c200 */
/*0670*/ FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fc80003f3c200 */
/*0680*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0690*/ @P0 BRA 0xbd0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*06a0*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R16, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c810 */
/*06b0*/ @!P0 BRA 0xbb0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FSETP.NEU.FTZ.AND P2, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fe40003f5d200 */
/*06d0*/ FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3d200 */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fd60003f1d200 */
/*06f0*/ @!P1 BRA !P2, 0xbb0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0700*/ LOP3.LUT P2, RZ, R16, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff10ff7812 */
/* 0x000fc8000784c0ff */
/*0710*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0720*/ @P1 BRA 0xb90 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*0740*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0750*/ @P0 BRA 0xb60 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0760*/ ISETP.GE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe40003f06270 */
/*0770*/ ISETP.GE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f26270 */
/*0780*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e00ff */
/*0790*/ @!P0 MOV R15, 0xffffffc0 ; /* 0xffffffc0000f8802 */
/* 0x000fe20000000f00 */
/*07a0*/ @!P0 FFMA R16, R16, 1.84467440737095516160e+19, RZ ; /* 0x5f80000010108823 */
/* 0x000fe400000000ff */
/*07b0*/ @!P1 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c0c9823 */
/* 0x000fe200000000ff */
/*07c0*/ @!P1 IADD3 R15, R15, 0x40, RZ ; /* 0x000000400f0f9810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ LEA R17, R13, 0xc0800000, 0x17 ; /* 0xc08000000d117811 */
/* 0x000fe200078eb8ff */
/*07e0*/ BSSY B2, 0xb50 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*07f0*/ IADD3 R18, R18, -0x7f, RZ ; /* 0xffffff8112127810 */
/* 0x000fc60007ffe0ff */
/*0800*/ IMAD.IADD R19, R12, 0x1, -R17 ; /* 0x000000010c137824 */
/* 0x000fe400078e0a11 */
/*0810*/ IMAD R12, R18.reuse, -0x800000, R16 ; /* 0xff800000120c7824 */
/* 0x040fe200078e0210 */
/*0820*/ IADD3 R18, R18, 0x7f, -R13 ; /* 0x0000007f12127810 */
/* 0x000fe20007ffe80d */
/*0830*/ MUFU.RCP R17, R19 ; /* 0x0000001300117308 */
/* 0x000e220000001000 */
/*0840*/ FADD.FTZ R20, -R19, -RZ ; /* 0x800000ff13147221 */
/* 0x000fe40000010100 */
/*0850*/ IADD3 R18, R18, R15, RZ ; /* 0x0000000f12127210 */
/* 0x000fe40007ffe0ff */
/*0860*/ FFMA R22, R17, R20, 1 ; /* 0x3f80000011167423 */
/* 0x001fc80000000014 */
/*0870*/ FFMA R16, R17, R22, R17 ; /* 0x0000001611107223 */
/* 0x000fc80000000011 */
/*0880*/ FFMA R17, R12, R16, RZ ; /* 0x000000100c117223 */
/* 0x000fc800000000ff */
/*0890*/ FFMA R21, R20, R17, R12 ; /* 0x0000001114157223 */
/* 0x000fc8000000000c */
/*08a0*/ FFMA R17, R16, R21, R17 ; /* 0x0000001510117223 */
/* 0x000fc80000000011 */
/*08b0*/ FFMA R20, R20, R17, R12 ; /* 0x0000001114147223 */
/* 0x000fc8000000000c */
/*08c0*/ FFMA R12, R16, R20, R17 ; /* 0x00000014100c7223 */
/* 0x000fca0000000011 */
/*08d0*/ SHF.R.U32.HI R13, RZ, 0x17, R12 ; /* 0x00000017ff0d7819 */
/* 0x000fc8000001160c */
/*08e0*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fca00078ec0ff */
/*08f0*/ IMAD.IADD R19, R13, 0x1, R18 ; /* 0x000000010d137824 */
/* 0x000fca00078e0212 */
/*0900*/ IADD3 R13, R19, -0x1, RZ ; /* 0xffffffff130d7810 */
/* 0x000fc80007ffe0ff */
/*0910*/ ISETP.GE.U32.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f06070 */
/*0920*/ @!P0 BRA 0xb30 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GT.AND P0, PT, R19, 0xfe, PT ; /* 0x000000fe1300780c */
/* 0x000fda0003f04270 */
/*0940*/ @P0 BRA 0xb00 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fda0003f06270 */
/*0960*/ @P0 BRA 0xb40 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0970*/ ISETP.GE.AND P0, PT, R19, -0x18, PT ; /* 0xffffffe81300780c */
/* 0x000fe40003f06270 */
/*0980*/ LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000c0c7812 */
/* 0x000fd600078ec0ff */
/*0990*/ @!P0 BRA 0xb40 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*09a0*/ FFMA.RZ R13, R16.reuse, R20.reuse, R17.reuse ; /* 0x00000014100d7223 */
/* 0x1c0fe2000000c011 */
/*09b0*/ IADD3 R18, R19.reuse, 0x20, RZ ; /* 0x0000002013127810 */
/* 0x040fe40007ffe0ff */
/*09c0*/ ISETP.NE.AND P2, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe40003f45270 */
/*09d0*/ LOP3.LUT R15, R13, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0d0f7812 */
/* 0x000fe200078ec0ff */
/*09e0*/ FFMA.RP R13, R16.reuse, R20.reuse, R17.reuse ; /* 0x00000014100d7223 */
/* 0x1c0fe20000008011 */
/*09f0*/ ISETP.NE.AND P1, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003f25270 */
/*0a00*/ FFMA.RM R16, R16, R20, R17 ; /* 0x0000001410107223 */
/* 0x000fe20000004011 */
/*0a10*/ LOP3.LUT R15, R15, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000f0f7812 */
/* 0x000fe400078efcff */
/*0a20*/ IADD3 R17, -R19, RZ, RZ ; /* 0x000000ff13117210 */
/* 0x000fc40007ffe1ff */
/*0a30*/ SHF.L.U32 R18, R15, R18, RZ ; /* 0x000000120f127219 */
/* 0x000fe400000006ff */
/*0a40*/ FSETP.NEU.FTZ.AND P0, PT, R13, R16, PT ; /* 0x000000100d00720b */
/* 0x000fe40003f1d000 */
/*0a50*/ SEL R16, R17, RZ, P2 ; /* 0x000000ff11107207 */
/* 0x000fe40001000000 */
/*0a60*/ ISETP.NE.AND P1, PT, R18, RZ, P1 ; /* 0x000000ff1200720c */
/* 0x000fe40000f25270 */
/*0a70*/ SHF.R.U32.HI R16, RZ, R16, R15 ; /* 0x00000010ff107219 */
/* 0x000fe4000001160f */
/*0a80*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0a90*/ SHF.R.U32.HI R18, RZ, 0x1, R16 ; /* 0x00000001ff127819 */
/* 0x000fe40000011610 */
/*0aa0*/ SEL R13, RZ, 0x1, !P0 ; /* 0x00000001ff0d7807 */
/* 0x000fc80004000000 */
/*0ab0*/ LOP3.LUT R13, R13, 0x1, R18, 0xf8, !PT ; /* 0x000000010d0d7812 */
/* 0x000fc800078ef812 */
/*0ac0*/ LOP3.LUT R13, R13, R16, RZ, 0xc0, !PT ; /* 0x000000100d0d7212 */
/* 0x000fca00078ec0ff */
/*0ad0*/ IMAD.IADD R13, R18, 0x1, R13 ; /* 0x00000001120d7824 */
/* 0x000fca00078e020d */
/*0ae0*/ LOP3.LUT R12, R13, R12, RZ, 0xfc, !PT ; /* 0x0000000c0d0c7212 */
/* 0x000fe200078efcff */
/*0af0*/ BRA 0xb40 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0b00*/ LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000c0c7812 */
/* 0x000fc800078ec0ff */
/*0b10*/ LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000c0c7812 */
/* 0x000fe200078efcff */
/*0b20*/ BRA 0xb40 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b30*/ LEA R12, R18, R12, 0x17 ; /* 0x0000000c120c7211 */
/* 0x000fe400078eb8ff */
/*0b40*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b50*/ BRA 0xbe0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b60*/ LOP3.LUT R12, R12, 0x80000000, R16, 0x48, !PT ; /* 0x800000000c0c7812 */
/* 0x000fc800078e4810 */
/*0b70*/ LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000c0c7812 */
/* 0x000fe200078efcff */
/*0b80*/ BRA 0xbe0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b90*/ LOP3.LUT R12, R12, 0x80000000, R16, 0x48, !PT ; /* 0x800000000c0c7812 */
/* 0x000fe200078e4810 */
/*0ba0*/ BRA 0xbe0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ MUFU.RSQ R12, -QNAN ; /* 0xffc00000000c7908 */
/* 0x000e220000001400 */
/*0bc0*/ BRA 0xbe0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ FADD.FTZ R12, R16, R12 ; /* 0x0000000c100c7221 */
/* 0x000fe40000010000 */
/*0be0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bf0*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fcc00000001ff */
/*0c00*/ RET.REL.NODEC R14 0x0 ; /* 0xfffff3f00e007950 */
/* 0x000fea0003c3ffff */
/*0c10*/ BRA 0xc10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#include<time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
//*******************kernel********************
__global__ void kernel (int *B_d,float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int offset=idx + idy*blockDim.x*gridDim.x;
int id=offset;
int i;
float X=0.f,Xprom=0.f,Y=0.f;
int dimy=1388,tam_imag=1388*1040,msk=3;
var_d[id]=0;
if(offset<tam_imag){
int dimy_B=dimy+2;
offset+=2*idy;
int id_p=offset+(dimy+msk);
int M_d[9];
M_d[0]=B_d[offset];
M_d[1]=B_d[offset+1];
M_d[2]=B_d[offset+2];
M_d[3]=B_d[id_p-1];
M_d[4]=B_d[id_p];
M_d[5]=B_d[id_p+1];
M_d[6]=B_d[(id_p-1)+dimy_B];
M_d[7]=B_d[id_p+dimy_B];
M_d[8]=B_d[(id_p+1)+dimy_B];
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************funcion main**********************
int main(int argc,char* argv[]){
//***************declaracion de variables**************
int i,j,m,cont,tam_B, init,fin;
init=atoi(argv[1]);
fin=atoi(argv[2]);
tam_B=(dimx+2)*(dimy+2);
FILE *arch, *matrizG;
int **A;
int B[dimx+2][dimy+2];
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *B_d, *B_h;
float *var_d,*var_h;
int d;
for(d=init;d<=fin;d++){
//*******************declaracion de variables***************
printf("d=%d \n", d);
B_h=(int *)malloc(sizeof(int)*tam_B);
cudaMalloc((void**)&B_d, tam_B*sizeof(int));
var_h=(float *)malloc(sizeof(float)*tam_imag);
cudaMalloc((void**)&var_d,tam_imag*sizeof(float));
A=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++)
A[i]=(int*)malloc(sizeof(int)*dimy);
//*****************calculo matriz B****************
char ruta1[]="MiTesis/";
sprintf(ruta1, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(ruta1,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizG, "%d", &A[i][j]);
}
}
fclose(matrizG);
cont=0;
for(i=0;i<dimx+2;i++){
//printf("\n");
for(j=0;j<dimy+2;j++){
B[i][j]=((i==0 || j==0 || i==dimx+1 || j==dimy+1) ? 0:A[i-1][j-1]);
B_h[cont]=B[i][j];
cont++;
}
}
//******************llamado de kernel*******************
dim3 Grid(347,20);
dim3 Block(13,16);
cudaMemcpy(B_d,B_h,sizeof(int)*tam_B,cudaMemcpyHostToDevice);
kernel<<<Grid,Block>>>(B_d,var_d);
cudaMemcpy(var_h,var_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
//****************almacenamiento matriz de varianza**************
char rutaV[]="VARIANZAS/";
sprintf(rutaV, "%s%d", rutaV,d);
arch=fopen(rutaV,"w+");
for(m=0;m<tam_imag;m++){
if(m%dimy==0 && m!=0){
fprintf(arch,"\n");
}
fprintf(arch,"%f ",var_h[m]); // "%.2f " - Imprimiria 2 decimales
}
fclose(arch);
free(B_h);
free(var_h);
free(A);
cudaFree(var_d);
cudaFree(B_d);
}
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
return 0;
}//FIN funcion main() | .file "tmpxft_0012ffa5_00000000-6_1_varianza.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPiPfPiPf
.type _Z27__device_stub__Z6kernelPiPfPiPf, @function
_Z27__device_stub__Z6kernelPiPfPiPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPiPfPiPf, .-_Z27__device_stub__Z6kernelPiPfPiPf
.globl _Z6kernelPiPf
.type _Z6kernelPiPf, @function
_Z6kernelPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPiPf, .-_Z6kernelPiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "d=%d \n"
.LC1:
.string "RGB/"
.LC2:
.string "%s%d%s"
.LC3:
.string "/G"
.LC4:
.string "r+"
.LC5:
.string "%d"
.LC6:
.string "%s%d"
.LC7:
.string "w+"
.LC8:
.string "\n"
.LC9:
.string "%f "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "\ntiempo de procesamiento de varianzas: %6.3fs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $152, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, -140(%rbp)
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, -144(%rbp)
movl dimy(%rip), %eax
leal 2(%rax), %edx
movslq %edx, %rdx
leaq 0(,%rdx,4), %rax
movq %rax, -136(%rbp)
movl dimx(%rip), %eax
addl $2, %eax
cltq
imulq %rdx, %rax
salq $2, %rax
movq %rax, -168(%rbp)
leaq 15(%rax), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L12:
cmpq %rcx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L14
orq $0, -8(%rsp,%rdx)
.L14:
movq %rsp, -184(%rbp)
call clock@PLT
movq %rax, %r14
cmpl %ebx, %r12d
jl .L15
movq %rax, -192(%rbp)
jmp .L32
.L20:
movq (%r12), %rax
leaq (%rax,%rbx,4), %rdx
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
cmpl %ebx, dimy(%rip)
jg .L20
.L21:
addl $1, %r15d
addq $8, %r12
cmpl %r15d, dimx(%rip)
jle .L42
.L19:
movl $0, %ebx
cmpl $0, dimy(%rip)
jg .L20
jmp .L21
.L42:
movq -176(%rbp), %r15
.L18:
movq %r13, %rdi
call fclose@PLT
movl dimx(%rip), %eax
movl %eax, %r10d
addl $1, %r10d
js .L22
movl dimy(%rip), %r9d
leal 1(%r9), %r11d
movq -184(%rbp), %rdi
leal 2(%rax), %r12d
movl $0, %esi
movl $0, %ebx
addl $2, %r9d
movq -152(%rbp), %rcx
jmp .L23
.L35:
movl $0, %r13d
.L24:
movl %r13d, 4(%rdi,%rdx)
movl %r13d, 4(%r8,%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %eax, %r9d
je .L46
.L25:
testl %esi, %esi
setne %r14b
cmpl %r10d, %esi
setne %r13b
andl %r14d, %r13d
testl %eax, %eax
setne %r14b
testb %r14b, %r13b
je .L35
cmpl %eax, %r11d
je .L35
movq -8(%r15,%rsi,8), %r13
movl 0(%r13,%rdx), %r13d
jmp .L24
.L46:
leal 1(%r11,%rbx), %ebx
.L27:
addq $1, %rsi
movq -136(%rbp), %rax
addq %rax, %rdi
cmpq %rsi, %r12
je .L22
.L23:
testl %r11d, %r11d
js .L27
movslq %ebx, %rax
leaq (%rcx,%rax,4), %r8
movq $-4, %rdx
movl $0, %eax
jmp .L25
.L22:
movl $347, -100(%rbp)
movl $20, -96(%rbp)
movl $1, -92(%rbp)
movl $13, -88(%rbp)
movl $16, -84(%rbp)
movl $1, -80(%rbp)
movl $1, %ecx
movq -168(%rbp), %rdx
movq -152(%rbp), %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl -80(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -88(%rbp), %rdx
movq -100(%rbp), %rdi
movl -92(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L28:
movslq tam_imag(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq -112(%rbp), %rsi
movq -160(%rbp), %rdi
call cudaMemcpy@PLT
movabsq $4709162402679243094, %rax
movq %rax, -67(%rbp)
movl $3101505, -60(%rbp)
leaq -67(%rbp), %rbx
movl -140(%rbp), %r9d
movq %rbx, %r8
leaq .LC6(%rip), %rcx
movl $11, %edx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, tam_imag(%rip)
jle .L29
movl $0, %ebx
leaq .LC8(%rip), %r14
leaq .LC9(%rip), %r13
movq %r15, -176(%rbp)
movq -160(%rbp), %r15
jmp .L31
.L47:
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z27__device_stub__Z6kernelPiPfPiPf
jmp .L28
.L30:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, tam_imag(%rip)
jle .L48
.L31:
movl %ebx, %eax
cltd
idivl dimy(%rip)
testl %edx, %edx
jne .L30
testl %ebx, %ebx
je .L30
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L30
.L48:
movq -176(%rbp), %r15
.L29:
movq %r12, %rdi
call fclose@PLT
movq -152(%rbp), %rdi
call free@PLT
movq -160(%rbp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
addl $1, -140(%rbp)
movl -140(%rbp), %eax
movl -144(%rbp), %ecx
cmpl %ecx, %eax
jg .L49
.L32:
movl -140(%rbp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -168(%rbp), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, -152(%rbp)
leaq -120(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, -160(%rbp)
leaq -112(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl dimx(%rip), %ebx
movslq %ebx, %r12
leaq 0(,%r12,4), %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L16
movq %rax, %rbx
leaq (%rax,%r12,8), %r12
.L17:
movslq dimy(%rip), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L17
.L16:
movabsq $3419192486446524749, %rax
movq %rax, -76(%rbp)
movb $0, -68(%rbp)
leaq -76(%rbp), %rbx
subq $8, %rsp
leaq .LC3(%rip), %rax
pushq %rax
movl -140(%rbp), %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rcx
movl $9, %edx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $16, %rsp
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r13
cmpl $0, dimx(%rip)
jle .L18
movq %r15, %r12
movl $0, %eax
leaq .LC5(%rip), %r14
movq %r15, -176(%rbp)
movl %eax, %r15d
jmp .L19
.L49:
movq -192(%rbp), %r14
.L15:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r14, %xmm1
subss %xmm1, %xmm0
divss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L50:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z6kernelPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tam_imag
.data
.align 4
.type tam_imag, @object
.size tam_imag, 4
tam_imag:
.long 1443520
.globl dimy
.align 4
.type dimy, @object
.size dimy, 4
dimy:
.long 1388
.globl dimx
.align 4
.type dimx, @object
.size dimx, 4
dimx:
.long 1040
.globl msk
.align 4
.type msk, @object
.size msk, 4
msk:
.long 3
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#include<time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
//*******************kernel********************
__global__ void kernel (int *B_d,float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int offset=idx + idy*blockDim.x*gridDim.x;
int id=offset;
int i;
float X=0.f,Xprom=0.f,Y=0.f;
int dimy=1388,tam_imag=1388*1040,msk=3;
var_d[id]=0;
if(offset<tam_imag){
int dimy_B=dimy+2;
offset+=2*idy;
int id_p=offset+(dimy+msk);
int M_d[9];
M_d[0]=B_d[offset];
M_d[1]=B_d[offset+1];
M_d[2]=B_d[offset+2];
M_d[3]=B_d[id_p-1];
M_d[4]=B_d[id_p];
M_d[5]=B_d[id_p+1];
M_d[6]=B_d[(id_p-1)+dimy_B];
M_d[7]=B_d[id_p+dimy_B];
M_d[8]=B_d[(id_p+1)+dimy_B];
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************funcion main**********************
int main(int argc,char* argv[]){
//***************declaracion de variables**************
int i,j,m,cont,tam_B, init,fin;
init=atoi(argv[1]);
fin=atoi(argv[2]);
tam_B=(dimx+2)*(dimy+2);
FILE *arch, *matrizG;
int **A;
int B[dimx+2][dimy+2];
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *B_d, *B_h;
float *var_d,*var_h;
int d;
for(d=init;d<=fin;d++){
//*******************declaracion de variables***************
printf("d=%d \n", d);
B_h=(int *)malloc(sizeof(int)*tam_B);
cudaMalloc((void**)&B_d, tam_B*sizeof(int));
var_h=(float *)malloc(sizeof(float)*tam_imag);
cudaMalloc((void**)&var_d,tam_imag*sizeof(float));
A=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++)
A[i]=(int*)malloc(sizeof(int)*dimy);
//*****************calculo matriz B****************
char ruta1[]="MiTesis/";
sprintf(ruta1, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(ruta1,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizG, "%d", &A[i][j]);
}
}
fclose(matrizG);
cont=0;
for(i=0;i<dimx+2;i++){
//printf("\n");
for(j=0;j<dimy+2;j++){
B[i][j]=((i==0 || j==0 || i==dimx+1 || j==dimy+1) ? 0:A[i-1][j-1]);
B_h[cont]=B[i][j];
cont++;
}
}
//******************llamado de kernel*******************
dim3 Grid(347,20);
dim3 Block(13,16);
cudaMemcpy(B_d,B_h,sizeof(int)*tam_B,cudaMemcpyHostToDevice);
kernel<<<Grid,Block>>>(B_d,var_d);
cudaMemcpy(var_h,var_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
//****************almacenamiento matriz de varianza**************
char rutaV[]="VARIANZAS/";
sprintf(rutaV, "%s%d", rutaV,d);
arch=fopen(rutaV,"w+");
for(m=0;m<tam_imag;m++){
if(m%dimy==0 && m!=0){
fprintf(arch,"\n");
}
fprintf(arch,"%f ",var_h[m]); // "%.2f " - Imprimiria 2 decimales
}
fclose(arch);
free(B_h);
free(var_h);
free(A);
cudaFree(var_d);
cudaFree(B_d);
}
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
return 0;
}//FIN funcion main() | #include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include<time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
//*******************kernel********************
__global__ void kernel (int *B_d,float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int offset=idx + idy*blockDim.x*gridDim.x;
int id=offset;
int i;
float X=0.f,Xprom=0.f,Y=0.f;
int dimy=1388,tam_imag=1388*1040,msk=3;
var_d[id]=0;
if(offset<tam_imag){
int dimy_B=dimy+2;
offset+=2*idy;
int id_p=offset+(dimy+msk);
int M_d[9];
M_d[0]=B_d[offset];
M_d[1]=B_d[offset+1];
M_d[2]=B_d[offset+2];
M_d[3]=B_d[id_p-1];
M_d[4]=B_d[id_p];
M_d[5]=B_d[id_p+1];
M_d[6]=B_d[(id_p-1)+dimy_B];
M_d[7]=B_d[id_p+dimy_B];
M_d[8]=B_d[(id_p+1)+dimy_B];
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************funcion main**********************
int main(int argc,char* argv[]){
//***************declaracion de variables**************
int i,j,m,cont,tam_B, init,fin;
init=atoi(argv[1]);
fin=atoi(argv[2]);
tam_B=(dimx+2)*(dimy+2);
FILE *arch, *matrizG;
int **A;
int B[dimx+2][dimy+2];
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *B_d, *B_h;
float *var_d,*var_h;
int d;
for(d=init;d<=fin;d++){
//*******************declaracion de variables***************
printf("d=%d \n", d);
B_h=(int *)malloc(sizeof(int)*tam_B);
hipMalloc((void**)&B_d, tam_B*sizeof(int));
var_h=(float *)malloc(sizeof(float)*tam_imag);
hipMalloc((void**)&var_d,tam_imag*sizeof(float));
A=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++)
A[i]=(int*)malloc(sizeof(int)*dimy);
//*****************calculo matriz B****************
char ruta1[]="MiTesis/";
sprintf(ruta1, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(ruta1,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizG, "%d", &A[i][j]);
}
}
fclose(matrizG);
cont=0;
for(i=0;i<dimx+2;i++){
//printf("\n");
for(j=0;j<dimy+2;j++){
B[i][j]=((i==0 || j==0 || i==dimx+1 || j==dimy+1) ? 0:A[i-1][j-1]);
B_h[cont]=B[i][j];
cont++;
}
}
//******************llamado de kernel*******************
dim3 Grid(347,20);
dim3 Block(13,16);
hipMemcpy(B_d,B_h,sizeof(int)*tam_B,hipMemcpyHostToDevice);
kernel<<<Grid,Block>>>(B_d,var_d);
hipMemcpy(var_h,var_d,sizeof(float)*tam_imag,hipMemcpyDeviceToHost);
//****************almacenamiento matriz de varianza**************
char rutaV[]="VARIANZAS/";
sprintf(rutaV, "%s%d", rutaV,d);
arch=fopen(rutaV,"w+");
for(m=0;m<tam_imag;m++){
if(m%dimy==0 && m!=0){
fprintf(arch,"\n");
}
fprintf(arch,"%f ",var_h[m]); // "%.2f " - Imprimiria 2 decimales
}
fclose(arch);
free(B_h);
free(var_h);
free(A);
hipFree(var_d);
hipFree(B_d);
}
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
return 0;
}//FIN funcion main() |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include<time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
//*******************kernel********************
__global__ void kernel (int *B_d,float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int offset=idx + idy*blockDim.x*gridDim.x;
int id=offset;
int i;
float X=0.f,Xprom=0.f,Y=0.f;
int dimy=1388,tam_imag=1388*1040,msk=3;
var_d[id]=0;
if(offset<tam_imag){
int dimy_B=dimy+2;
offset+=2*idy;
int id_p=offset+(dimy+msk);
int M_d[9];
M_d[0]=B_d[offset];
M_d[1]=B_d[offset+1];
M_d[2]=B_d[offset+2];
M_d[3]=B_d[id_p-1];
M_d[4]=B_d[id_p];
M_d[5]=B_d[id_p+1];
M_d[6]=B_d[(id_p-1)+dimy_B];
M_d[7]=B_d[id_p+dimy_B];
M_d[8]=B_d[(id_p+1)+dimy_B];
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************funcion main**********************
int main(int argc,char* argv[]){
//***************declaracion de variables**************
int i,j,m,cont,tam_B, init,fin;
init=atoi(argv[1]);
fin=atoi(argv[2]);
tam_B=(dimx+2)*(dimy+2);
FILE *arch, *matrizG;
int **A;
int B[dimx+2][dimy+2];
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *B_d, *B_h;
float *var_d,*var_h;
int d;
for(d=init;d<=fin;d++){
//*******************declaracion de variables***************
printf("d=%d \n", d);
B_h=(int *)malloc(sizeof(int)*tam_B);
hipMalloc((void**)&B_d, tam_B*sizeof(int));
var_h=(float *)malloc(sizeof(float)*tam_imag);
hipMalloc((void**)&var_d,tam_imag*sizeof(float));
A=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++)
A[i]=(int*)malloc(sizeof(int)*dimy);
//*****************calculo matriz B****************
char ruta1[]="MiTesis/";
sprintf(ruta1, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(ruta1,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizG, "%d", &A[i][j]);
}
}
fclose(matrizG);
cont=0;
for(i=0;i<dimx+2;i++){
//printf("\n");
for(j=0;j<dimy+2;j++){
B[i][j]=((i==0 || j==0 || i==dimx+1 || j==dimy+1) ? 0:A[i-1][j-1]);
B_h[cont]=B[i][j];
cont++;
}
}
//******************llamado de kernel*******************
dim3 Grid(347,20);
dim3 Block(13,16);
hipMemcpy(B_d,B_h,sizeof(int)*tam_B,hipMemcpyHostToDevice);
kernel<<<Grid,Block>>>(B_d,var_d);
hipMemcpy(var_h,var_d,sizeof(float)*tam_imag,hipMemcpyDeviceToHost);
//****************almacenamiento matriz de varianza**************
char rutaV[]="VARIANZAS/";
sprintf(rutaV, "%s%d", rutaV,d);
arch=fopen(rutaV,"w+");
for(m=0;m<tam_imag;m++){
if(m%dimy==0 && m!=0){
fprintf(arch,"\n");
}
fprintf(arch,"%f ",var_h[m]); // "%.2f " - Imprimiria 2 decimales
}
fclose(arch);
free(B_h);
free(var_h);
free(A);
hipFree(var_d);
hipFree(B_d);
}
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
return 0;
}//FIN funcion main() | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiPf
.globl _Z6kernelPiPf
.p2align 8
.type _Z6kernelPiPf,@function
_Z6kernelPiPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
v_dual_mov_b32 v11, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v1, s2, s[14:15]
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v4, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_store_b32 v[9:10], v11, off
v_cmpx_gt_i32_e32 0x1606c0, v2
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v0, v1, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b64 s[0:1], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, 0x1000, v0
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x2000, v0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
s_clause 0x2
global_load_b96 v[0:2], v[0:1], off
global_load_b96 v[3:5], v[3:4], off offset:1464
global_load_b96 v[6:8], v[6:7], off offset:2928
.LBB0_2:
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
s_waitcnt vmcnt(0)
v_movrels_b32_e32 v12, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v12, v12
v_add_f32_e32 v11, v11, v12
s_cbranch_scc1 .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v12, null, 0x41100000, 0x41100000, v11
v_div_scale_f32 v15, vcc_lo, v11, 0x41100000, v11
s_mov_b64 s[0:1], 0
v_rcp_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v12, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v12, v14, v15
v_fmac_f32_e32 v14, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v12, v14, v15
v_div_fmas_f32 v12, v12, v13, v14
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v12, v12, 0x41100000, v11
v_mov_b32_e32 v11, 0
.LBB0_4:
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
v_movrels_b32_e32 v13, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v13, v13
v_sub_f32_e32 v13, v12, v13
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v13
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v0, null, 0x41100000, 0x41100000, v11
v_rcp_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v1, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v2, v1
v_div_scale_f32 v2, vcc_lo, v11, 0x41100000, v11
v_mul_f32_e32 v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v0, v3, v2
v_fmac_f32_e32 v3, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v0, v3, v2
v_div_fmas_f32 v0, v0, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v0, 0x41100000, v11
global_store_b32 v[9:10], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiPf, .Lfunc_end0-_Z6kernelPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include<time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
//*******************kernel********************
__global__ void kernel (int *B_d,float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int offset=idx + idy*blockDim.x*gridDim.x;
int id=offset;
int i;
float X=0.f,Xprom=0.f,Y=0.f;
int dimy=1388,tam_imag=1388*1040,msk=3;
var_d[id]=0;
if(offset<tam_imag){
int dimy_B=dimy+2;
offset+=2*idy;
int id_p=offset+(dimy+msk);
int M_d[9];
M_d[0]=B_d[offset];
M_d[1]=B_d[offset+1];
M_d[2]=B_d[offset+2];
M_d[3]=B_d[id_p-1];
M_d[4]=B_d[id_p];
M_d[5]=B_d[id_p+1];
M_d[6]=B_d[(id_p-1)+dimy_B];
M_d[7]=B_d[id_p+dimy_B];
M_d[8]=B_d[(id_p+1)+dimy_B];
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************funcion main**********************
int main(int argc,char* argv[]){
//***************declaracion de variables**************
int i,j,m,cont,tam_B, init,fin;
init=atoi(argv[1]);
fin=atoi(argv[2]);
tam_B=(dimx+2)*(dimy+2);
FILE *arch, *matrizG;
int **A;
int B[dimx+2][dimy+2];
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *B_d, *B_h;
float *var_d,*var_h;
int d;
for(d=init;d<=fin;d++){
//*******************declaracion de variables***************
printf("d=%d \n", d);
B_h=(int *)malloc(sizeof(int)*tam_B);
hipMalloc((void**)&B_d, tam_B*sizeof(int));
var_h=(float *)malloc(sizeof(float)*tam_imag);
hipMalloc((void**)&var_d,tam_imag*sizeof(float));
A=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++)
A[i]=(int*)malloc(sizeof(int)*dimy);
//*****************calculo matriz B****************
char ruta1[]="MiTesis/";
sprintf(ruta1, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(ruta1,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizG, "%d", &A[i][j]);
}
}
fclose(matrizG);
cont=0;
for(i=0;i<dimx+2;i++){
//printf("\n");
for(j=0;j<dimy+2;j++){
B[i][j]=((i==0 || j==0 || i==dimx+1 || j==dimy+1) ? 0:A[i-1][j-1]);
B_h[cont]=B[i][j];
cont++;
}
}
//******************llamado de kernel*******************
dim3 Grid(347,20);
dim3 Block(13,16);
hipMemcpy(B_d,B_h,sizeof(int)*tam_B,hipMemcpyHostToDevice);
kernel<<<Grid,Block>>>(B_d,var_d);
hipMemcpy(var_h,var_d,sizeof(float)*tam_imag,hipMemcpyDeviceToHost);
//****************almacenamiento matriz de varianza**************
char rutaV[]="VARIANZAS/";
sprintf(rutaV, "%s%d", rutaV,d);
arch=fopen(rutaV,"w+");
for(m=0;m<tam_imag;m++){
if(m%dimy==0 && m!=0){
fprintf(arch,"\n");
}
fprintf(arch,"%f ",var_h[m]); // "%.2f " - Imprimiria 2 decimales
}
fclose(arch);
free(B_h);
free(var_h);
free(A);
hipFree(var_d);
hipFree(B_d);
}
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
return 0;
}//FIN funcion main() | .text
.file "1_varianza.hip"
.globl _Z21__device_stub__kernelPiPf # -- Begin function _Z21__device_stub__kernelPiPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiPf,@function
_Z21__device_stub__kernelPiPf: # @_Z21__device_stub__kernelPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiPf, .Lfunc_end0-_Z21__device_stub__kernelPiPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq dimx(%rip), %r15
movslq dimy(%rip), %rbx
callq clock
movq %rax, 64(%rsp) # 8-byte Spill
movq %r14, 72(%rsp) # 8-byte Spill
cmpl %r14d, %ebp
jle .LBB1_1
.LBB1_32: # %._crit_edge103
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
cvtsi2ssq 64(%rsp), %xmm1 # 8-byte Folded Reload
subss %xmm1, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1: # %.lr.ph102
.cfi_def_cfa_offset 208
addq $2, %rbx
addq $2, %r15
imulq %rbx, %r15
shlq $2, %r15
movq %r15, 32(%rsp) # 8-byte Spill
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_31: # %._crit_edge98
# in Loop: Header=BB1_2 Depth=1
movq %r13, %rdi
callq fclose
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
leal 1(%rbp), %eax
cmpl 72(%rsp), %ebp # 4-byte Folded Reload
movl %eax, %ebp
je .LBB1_32
.LBB1_2: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_7 Depth 2
# Child Loop BB1_9 Depth 3
# Child Loop BB1_13 Depth 2
# Child Loop BB1_15 Depth 3
# Child Loop BB1_27 Depth 2
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq tam_imag(%rip), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movslq dimx(%rip), %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, %r14
testq %rbx, %rbx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebx, %ebx
movslq dimy(%rip), %r12
shlq $2, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
callq malloc
movq %rax, (%r14,%r13,8)
incq %r13
cmpq %r13, %rbx
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movabsq $3419192486446524749, %rax # imm = 0x2F7369736554694D
movq %rax, 55(%rsp)
movb $0, 63(%rsp)
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.3, %r8d
leaq 55(%rsp), %rbx
movq %rbx, %rdi
movq %rbp, 80(%rsp) # 8-byte Spill
movl %ebp, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r13
cmpl $0, dimx(%rip)
jle .LBB1_11
# %bb.6: # %.preheader81.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %ebx, %ebx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %._crit_edge85
# in Loop: Header=BB1_7 Depth=2
incq %rbx
movslq dimx(%rip), %rax
cmpq %rax, %rbx
jge .LBB1_11
.LBB1_7: # %.preheader81
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
cmpl $0, dimy(%rip)
jle .LBB1_10
# %bb.8: # %.lr.ph84
# in Loop: Header=BB1_7 Depth=2
movq (%r14,%rbx,8), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_7 Depth=2
# => This Inner Loop Header: Depth=3
movl $.L.str.5, %esi
movq %r13, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq dimy(%rip), %rax
addq $4, %r12
cmpq %rax, %rbp
jl .LBB1_9
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_11: # %._crit_edge87
# in Loop: Header=BB1_2 Depth=1
movq %r13, %rdi
callq fclose
movl dimx(%rip), %eax
cmpl $-1, %eax
movq 80(%rsp), %rbp # 8-byte Reload
movq 40(%rsp), %rsi # 8-byte Reload
jl .LBB1_23
# %bb.12: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl dimy(%rip), %ecx
leal 1(%rax), %edx
leal 1(%rcx), %r12d
leal 2(%rcx), %edi
addl $2, %eax
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_21: # %._crit_edge91.loopexit
# in Loop: Header=BB1_13 Depth=2
addl %r10d, %r9d
.LBB1_22: # %._crit_edge91
# in Loop: Header=BB1_13 Depth=2
incq %r8
cmpq %rax, %r8
je .LBB1_23
.LBB1_13: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_15 Depth 3
cmpl $-1, %ecx
jl .LBB1_22
# %bb.14: # %.lr.ph90
# in Loop: Header=BB1_13 Depth=2
movslq %r9d, %r10
leaq (%rsi,%r10,4), %r11
xorl %r10d, %r10d
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_15 Depth=3
movl %ebx, (%r11,%r10,4)
incq %r10
cmpq %r10, %rdi
je .LBB1_21
.LBB1_15: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_13 Depth=2
# => This Inner Loop Header: Depth=3
xorl %ebx, %ebx
testq %r8, %r8
je .LBB1_20
# %bb.16: # in Loop: Header=BB1_15 Depth=3
testq %r10, %r10
je .LBB1_20
# %bb.17: # in Loop: Header=BB1_15 Depth=3
cmpq %rdx, %r8
je .LBB1_20
# %bb.18: # in Loop: Header=BB1_15 Depth=3
cmpq %r10, %r12
je .LBB1_20
# %bb.19: # in Loop: Header=BB1_15 Depth=3
movq -8(%r14,%r8,8), %rbx
movl -4(%rbx,%r10,4), %ebx
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_23: # %._crit_edge94
# in Loop: Header=BB1_2 Depth=1
movq 8(%rsp), %rdi
movq 32(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movabsq $85899346267, %rdi # imm = 0x140000015B
movl $1, %esi
movabsq $68719476749, %rdx # imm = 0x100000000D
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_25
# %bb.24: # in Loop: Header=BB1_2 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 16(%rsp)
leaq 136(%rsp), %rax
movq %rax, 24(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z6kernelPiPf, %edi
leaq 16(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_25: # in Loop: Header=BB1_2 Depth=1
movq (%rsp), %rsi
movslq tam_imag(%rip), %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movabsq $4709162402679243094, %rax # imm = 0x415A4E4149524156
movq %rax, 16(%rsp)
movw $12115, 24(%rsp) # imm = 0x2F53
movb $0, 26(%rsp)
movl $.L.str.6, %esi
leaq 16(%rsp), %rbx
movq %rbx, %rdi
movq %rbx, %rdx
movl %ebp, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.7, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r13
cmpl $0, tam_imag(%rip)
jle .LBB1_31
# %bb.26: # %.lr.ph97.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r12d, %r12d
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_30: # in Loop: Header=BB1_27 Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %esi
movq %r13, %rdi
movb $1, %al
callq fprintf
incq %r12
movslq tam_imag(%rip), %rax
cmpq %rax, %r12
jge .LBB1_31
.LBB1_27: # %.lr.ph97
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r12d, %eax
cltd
idivl dimy(%rip)
testq %r12, %r12
je .LBB1_30
# %bb.28: # %.lr.ph97
# in Loop: Header=BB1_27 Depth=2
testl %edx, %edx
jne .LBB1_30
# %bb.29: # in Loop: Header=BB1_27 Depth=2
movl $10, %edi
movq %r13, %rsi
callq fputc@PLT
jmp .LBB1_30
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type msk,@object # @msk
.data
.globl msk
.p2align 2, 0x0
msk:
.long 3 # 0x3
.size msk, 4
.type dimx,@object # @dimx
.globl dimx
.p2align 2, 0x0
dimx:
.long 1040 # 0x410
.size dimx, 4
.type dimy,@object # @dimy
.globl dimy
.p2align 2, 0x0
dimy:
.long 1388 # 0x56c
.size dimy, 4
.type tam_imag,@object # @tam_imag
.globl tam_imag
.p2align 2, 0x0
tam_imag:
.long 1443520 # 0x1606c0
.size tam_imag, 4
.type _Z6kernelPiPf,@object # @_Z6kernelPiPf
.section .rodata,"a",@progbits
.globl _Z6kernelPiPf
.p2align 3, 0x0
_Z6kernelPiPf:
.quad _Z21__device_stub__kernelPiPf
.size _Z6kernelPiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "d=%d \n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s%d%s"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "RGB/"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/G"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r+"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s%d"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "w+"
.size .L.str.7, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%f "
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\ntiempo de procesamiento de varianzas: %6.3fs\n"
.size .L.str.10, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R2, R0, c[0x0][0xc], R5 ; /* 0x0000030000027a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R5, R2, c[0x0][0x0], R7 ; /* 0x0000000002057a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R5.reuse, R13, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x040fe200078e020d */
/*00b0*/ ISETP.GT.AND P0, PT, R5, 0x1606bf, PT ; /* 0x001606bf0500780c */
/* 0x000fc80003f04270 */
/*00c0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f2000c101904 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ LEA R12, R0, R5, 0x1 ; /* 0x00000005000c7211 */
/* 0x000fca00078e08ff */
/*00f0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e020d */
/*0100*/ LDG.E R0, [R12.64] ; /* 0x000000040c007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R5, [R12.64+0x4] ; /* 0x000004040c057981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R4, [R12.64+0x8] ; /* 0x000008040c047981 */
/* 0x000f28000c1e1900 */
/*0130*/ LDG.E R6, [R12.64+0x15b8] ; /* 0x0015b8040c067981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R7, [R12.64+0x15bc] ; /* 0x0015bc040c077981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R8, [R12.64+0x15c0] ; /* 0x0015c0040c087981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R9, [R12.64+0x2b70] ; /* 0x002b70040c097981 */
/* 0x000368000c1e1900 */
/*0170*/ LDG.E R10, [R12.64+0x2b74] ; /* 0x002b74040c0a7981 */
/* 0x000368000c1e1900 */
/*0180*/ LDG.E R15, [R12.64+0x2b78] ; /* 0x002b78040c0f7981 */
/* 0x000362000c1e1900 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, 0x3de38e39 ; /* 0x3de38e39ff107424 */
/* 0x000fe200078e00ff */
/*01a0*/ BSSY B0, 0x390 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*01b0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x004ff00000201400 */
/*01c0*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x008eb00000201400 */
/*01d0*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x010ef00000201400 */
/*01e0*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x020e620000201400 */
/*01f0*/ FADD R11, R0, R5 ; /* 0x00000005000b7221 */
/* 0x004fce0000000000 */
/*0200*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000ea20000201400 */
/*0210*/ FADD R11, R11, R4 ; /* 0x000000040b0b7221 */
/* 0x008fce0000000000 */
/*0220*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000ee20000201400 */
/*0230*/ FADD R12, R11, R6 ; /* 0x000000060b0c7221 */
/* 0x002fce0000000000 */
/*0240*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000e620000201400 */
/*0250*/ FADD R13, R12, R7 ; /* 0x000000070c0d7221 */
/* 0x004fe20000000000 */
/*0260*/ HFMA2.MMA R12, -RZ, RZ, 2.53125, 0 ; /* 0x41100000ff0c7435 */
/* 0x000fcc00000001ff */
/*0270*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000ea20000201400 */
/*0280*/ FADD R14, R13, R8 ; /* 0x000000080d0e7221 */
/* 0x008fce0000000000 */
/*0290*/ I2F R11, R15 ; /* 0x0000000f000b7306 */
/* 0x000ee20000201400 */
/*02a0*/ FADD R13, R14, R9 ; /* 0x000000090e0d7221 */
/* 0x002fc80000000000 */
/*02b0*/ FADD R14, R13, R10 ; /* 0x0000000a0d0e7221 */
/* 0x004fe40000000000 */
/*02c0*/ FFMA R13, R16, -R12, 1 ; /* 0x3f800000100d7423 */
/* 0x000fc8000000080c */
/*02d0*/ FFMA R13, R13, R16, 0.11111111193895339966 ; /* 0x3de38e390d0d7423 */
/* 0x000fe40000000010 */
/*02e0*/ FADD R14, R14, R11 ; /* 0x0000000b0e0e7221 */
/* 0x008fc80000000000 */
/*02f0*/ FCHK P0, R14, 9 ; /* 0x411000000e007902 */
/* 0x000e620000000000 */
/*0300*/ FFMA R15, R14, R13, RZ ; /* 0x0000000d0e0f7223 */
/* 0x000fc800000000ff */
/*0310*/ FFMA R16, R15, -9, R14 ; /* 0xc11000000f107823 */
/* 0x000fc8000000000e */
/*0320*/ FFMA R13, R13, R16, R15 ; /* 0x000000100d0d7223 */
/* 0x000fe2000000000f */
/*0330*/ @!P0 BRA 0x380 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0340*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000e */
/*0350*/ MOV R14, 0x370 ; /* 0x00000370000e7802 */
/* 0x000fe40000000f00 */
/*0360*/ CALL.REL.NOINC 0x5b0 ; /* 0x0000024000007944 */
/* 0x001fea0003c00000 */
/*0370*/ MOV R13, R12 ; /* 0x0000000c000d7202 */
/* 0x001fe40000000f00 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ FADD R0, -R0, R13.reuse ; /* 0x0000000d00007221 */
/* 0x100fe20000000100 */
/*03a0*/ HFMA2.MMA R12, -RZ, RZ, 2.53125, 0 ; /* 0x41100000ff0c7435 */
/* 0x000fe200000001ff */
/*03b0*/ FADD R5, -R5, R13.reuse ; /* 0x0000000d05057221 */
/* 0x100fe20000000100 */
/*03c0*/ BSSY B0, 0x590 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*03d0*/ FFMA R0, R0, R0, RZ ; /* 0x0000000000007223 */
/* 0x000fe400000000ff */
/*03e0*/ FADD R15, -R4, R13 ; /* 0x0000000d040f7221 */
/* 0x000fe40000000100 */
/*03f0*/ FFMA R0, R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fc40000000000 */
/*0400*/ FADD R5, -R6, R13.reuse ; /* 0x0000000d06057221 */
/* 0x100fe40000000100 */
/*0410*/ FFMA R0, R15, R15, R0 ; /* 0x0000000f0f007223 */
/* 0x000fe40000000000 */
/*0420*/ FADD R7, -R7, R13.reuse ; /* 0x0000000d07077221 */
/* 0x100fe40000000100 */
/*0430*/ FFMA R0, R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fe40000000000 */
/*0440*/ FADD R5, -R8, R13 ; /* 0x0000000d08057221 */
/* 0x000fe40000000100 */
/*0450*/ FFMA R0, R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x000fc40000000000 */
/*0460*/ FADD R9, -R9, R13.reuse ; /* 0x0000000d09097221 */
/* 0x100fe40000000100 */
/*0470*/ FFMA R0, R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fe40000000000 */
/*0480*/ FADD R5, -R10, R13.reuse ; /* 0x0000000d0a057221 */
/* 0x100fe40000000100 */
/*0490*/ FFMA R0, R9, R9, R0 ; /* 0x0000000909007223 */
/* 0x000fe40000000000 */
/*04a0*/ FADD R11, -R11, R13 ; /* 0x0000000d0b0b7221 */
/* 0x000fe40000000100 */
/*04b0*/ FFMA R0, R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x000fc40000000000 */
/*04c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3de38e39 ; /* 0x3de38e39ff077424 */
/* 0x000fe400078e00ff */
/*04d0*/ FFMA R16, R11, R11, R0 ; /* 0x0000000b0b107223 */
/* 0x000fe40000000000 */
/*04e0*/ FFMA R4, R7, -R12, 1 ; /* 0x3f80000007047423 */
/* 0x000fe4000000080c */
/*04f0*/ FCHK P0, R16, 9 ; /* 0x4110000010007902 */
/* 0x000e640000000000 */
/*0500*/ FFMA R7, R4, R7, 0.11111111193895339966 ; /* 0x3de38e3904077423 */
/* 0x000fc80000000007 */
/*0510*/ FFMA R0, R7, R16, RZ ; /* 0x0000001007007223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R5, R0, -9, R16 ; /* 0xc110000000057823 */
/* 0x000fc80000000010 */
/*0530*/ FFMA R5, R7, R5, R0 ; /* 0x0000000507057223 */
/* 0x000fe20000000000 */
/*0540*/ @!P0 BRA 0x580 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0550*/ MOV R14, 0x570 ; /* 0x00000570000e7802 */
/* 0x000fe40000000f00 */
/*0560*/ CALL.REL.NOINC 0x5b0 ; /* 0x0000004000007944 */
/* 0x001fea0003c00000 */
/*0570*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x001fe400078e000c */
/*0580*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0590*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ SHF.R.U32.HI R13, RZ, 0x17, R12 ; /* 0x00000017ff0d7819 */
/* 0x000fe2000001160c */
/*05c0*/ BSSY B1, 0xbf0 ; /* 0x0000062000017945 */
/* 0x000fe20003800000 */
/*05d0*/ SHF.R.U32.HI R15, RZ, 0x17, R16 ; /* 0x00000017ff0f7819 */
/* 0x000fe40000011610 */
/*05e0*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fe400078ec0ff */
/*05f0*/ LOP3.LUT R18, R15, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0f127812 */
/* 0x000fe400078ec0ff */
/*0600*/ IADD3 R17, R13, -0x1, RZ ; /* 0xffffffff0d117810 */
/* 0x000fc40007ffe0ff */
/*0610*/ IADD3 R19, R18, -0x1, RZ ; /* 0xffffffff12137810 */
/* 0x000fe40007ffe0ff */
/*0620*/ ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ; /* 0x000000fd1100780c */
/* 0x000fc80003f04070 */
/*0630*/ ISETP.GT.U32.OR P0, PT, R19, 0xfd, P0 ; /* 0x000000fd1300780c */
/* 0x000fda0000704470 */
/*0640*/ @!P0 MOV R15, RZ ; /* 0x000000ff000f8202 */
/* 0x000fe20000000f00 */
/*0650*/ @!P0 BRA 0x7d0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0660*/ FSETP.GTU.FTZ.AND P0, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fe40003f1c200 */
/*0670*/ FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fc80003f3c200 */
/*0680*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0690*/ @P0 BRA 0xbd0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*06a0*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R16, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c810 */
/*06b0*/ @!P0 BRA 0xbb0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FSETP.NEU.FTZ.AND P2, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fe40003f5d200 */
/*06d0*/ FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3d200 */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fd60003f1d200 */
/*06f0*/ @!P1 BRA !P2, 0xbb0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0700*/ LOP3.LUT P2, RZ, R16, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff10ff7812 */
/* 0x000fc8000784c0ff */
/*0710*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0720*/ @P1 BRA 0xb90 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*0740*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0750*/ @P0 BRA 0xb60 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0760*/ ISETP.GE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe40003f06270 */
/*0770*/ ISETP.GE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f26270 */
/*0780*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e00ff */
/*0790*/ @!P0 MOV R15, 0xffffffc0 ; /* 0xffffffc0000f8802 */
/* 0x000fe20000000f00 */
/*07a0*/ @!P0 FFMA R16, R16, 1.84467440737095516160e+19, RZ ; /* 0x5f80000010108823 */
/* 0x000fe400000000ff */
/*07b0*/ @!P1 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c0c9823 */
/* 0x000fe200000000ff */
/*07c0*/ @!P1 IADD3 R15, R15, 0x40, RZ ; /* 0x000000400f0f9810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ LEA R17, R13, 0xc0800000, 0x17 ; /* 0xc08000000d117811 */
/* 0x000fe200078eb8ff */
/*07e0*/ BSSY B2, 0xb50 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*07f0*/ IADD3 R18, R18, -0x7f, RZ ; /* 0xffffff8112127810 */
/* 0x000fc60007ffe0ff */
/*0800*/ IMAD.IADD R19, R12, 0x1, -R17 ; /* 0x000000010c137824 */
/* 0x000fe400078e0a11 */
/*0810*/ IMAD R12, R18.reuse, -0x800000, R16 ; /* 0xff800000120c7824 */
/* 0x040fe200078e0210 */
/*0820*/ IADD3 R18, R18, 0x7f, -R13 ; /* 0x0000007f12127810 */
/* 0x000fe20007ffe80d */
/*0830*/ MUFU.RCP R17, R19 ; /* 0x0000001300117308 */
/* 0x000e220000001000 */
/*0840*/ FADD.FTZ R20, -R19, -RZ ; /* 0x800000ff13147221 */
/* 0x000fe40000010100 */
/*0850*/ IADD3 R18, R18, R15, RZ ; /* 0x0000000f12127210 */
/* 0x000fe40007ffe0ff */
/*0860*/ FFMA R22, R17, R20, 1 ; /* 0x3f80000011167423 */
/* 0x001fc80000000014 */
/*0870*/ FFMA R16, R17, R22, R17 ; /* 0x0000001611107223 */
/* 0x000fc80000000011 */
/*0880*/ FFMA R17, R12, R16, RZ ; /* 0x000000100c117223 */
/* 0x000fc800000000ff */
/*0890*/ FFMA R21, R20, R17, R12 ; /* 0x0000001114157223 */
/* 0x000fc8000000000c */
/*08a0*/ FFMA R17, R16, R21, R17 ; /* 0x0000001510117223 */
/* 0x000fc80000000011 */
/*08b0*/ FFMA R20, R20, R17, R12 ; /* 0x0000001114147223 */
/* 0x000fc8000000000c */
/*08c0*/ FFMA R12, R16, R20, R17 ; /* 0x00000014100c7223 */
/* 0x000fca0000000011 */
/*08d0*/ SHF.R.U32.HI R13, RZ, 0x17, R12 ; /* 0x00000017ff0d7819 */
/* 0x000fc8000001160c */
/*08e0*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fca00078ec0ff */
/*08f0*/ IMAD.IADD R19, R13, 0x1, R18 ; /* 0x000000010d137824 */
/* 0x000fca00078e0212 */
/*0900*/ IADD3 R13, R19, -0x1, RZ ; /* 0xffffffff130d7810 */
/* 0x000fc80007ffe0ff */
/*0910*/ ISETP.GE.U32.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f06070 */
/*0920*/ @!P0 BRA 0xb30 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GT.AND P0, PT, R19, 0xfe, PT ; /* 0x000000fe1300780c */
/* 0x000fda0003f04270 */
/*0940*/ @P0 BRA 0xb00 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fda0003f06270 */
/*0960*/ @P0 BRA 0xb40 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0970*/ ISETP.GE.AND P0, PT, R19, -0x18, PT ; /* 0xffffffe81300780c */
/* 0x000fe40003f06270 */
/*0980*/ LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000c0c7812 */
/* 0x000fd600078ec0ff */
/*0990*/ @!P0 BRA 0xb40 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*09a0*/ FFMA.RZ R13, R16.reuse, R20.reuse, R17.reuse ; /* 0x00000014100d7223 */
/* 0x1c0fe2000000c011 */
/*09b0*/ IADD3 R18, R19.reuse, 0x20, RZ ; /* 0x0000002013127810 */
/* 0x040fe40007ffe0ff */
/*09c0*/ ISETP.NE.AND P2, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe40003f45270 */
/*09d0*/ LOP3.LUT R15, R13, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0d0f7812 */
/* 0x000fe200078ec0ff */
/*09e0*/ FFMA.RP R13, R16.reuse, R20.reuse, R17.reuse ; /* 0x00000014100d7223 */
/* 0x1c0fe20000008011 */
/*09f0*/ ISETP.NE.AND P1, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003f25270 */
/*0a00*/ FFMA.RM R16, R16, R20, R17 ; /* 0x0000001410107223 */
/* 0x000fe20000004011 */
/*0a10*/ LOP3.LUT R15, R15, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000f0f7812 */
/* 0x000fe400078efcff */
/*0a20*/ IADD3 R17, -R19, RZ, RZ ; /* 0x000000ff13117210 */
/* 0x000fc40007ffe1ff */
/*0a30*/ SHF.L.U32 R18, R15, R18, RZ ; /* 0x000000120f127219 */
/* 0x000fe400000006ff */
/*0a40*/ FSETP.NEU.FTZ.AND P0, PT, R13, R16, PT ; /* 0x000000100d00720b */
/* 0x000fe40003f1d000 */
/*0a50*/ SEL R16, R17, RZ, P2 ; /* 0x000000ff11107207 */
/* 0x000fe40001000000 */
/*0a60*/ ISETP.NE.AND P1, PT, R18, RZ, P1 ; /* 0x000000ff1200720c */
/* 0x000fe40000f25270 */
/*0a70*/ SHF.R.U32.HI R16, RZ, R16, R15 ; /* 0x00000010ff107219 */
/* 0x000fe4000001160f */
/*0a80*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0a90*/ SHF.R.U32.HI R18, RZ, 0x1, R16 ; /* 0x00000001ff127819 */
/* 0x000fe40000011610 */
/*0aa0*/ SEL R13, RZ, 0x1, !P0 ; /* 0x00000001ff0d7807 */
/* 0x000fc80004000000 */
/*0ab0*/ LOP3.LUT R13, R13, 0x1, R18, 0xf8, !PT ; /* 0x000000010d0d7812 */
/* 0x000fc800078ef812 */
/*0ac0*/ LOP3.LUT R13, R13, R16, RZ, 0xc0, !PT ; /* 0x000000100d0d7212 */
/* 0x000fca00078ec0ff */
/*0ad0*/ IMAD.IADD R13, R18, 0x1, R13 ; /* 0x00000001120d7824 */
/* 0x000fca00078e020d */
/*0ae0*/ LOP3.LUT R12, R13, R12, RZ, 0xfc, !PT ; /* 0x0000000c0d0c7212 */
/* 0x000fe200078efcff */
/*0af0*/ BRA 0xb40 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0b00*/ LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000c0c7812 */
/* 0x000fc800078ec0ff */
/*0b10*/ LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000c0c7812 */
/* 0x000fe200078efcff */
/*0b20*/ BRA 0xb40 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b30*/ LEA R12, R18, R12, 0x17 ; /* 0x0000000c120c7211 */
/* 0x000fe400078eb8ff */
/*0b40*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b50*/ BRA 0xbe0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b60*/ LOP3.LUT R12, R12, 0x80000000, R16, 0x48, !PT ; /* 0x800000000c0c7812 */
/* 0x000fc800078e4810 */
/*0b70*/ LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000c0c7812 */
/* 0x000fe200078efcff */
/*0b80*/ BRA 0xbe0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b90*/ LOP3.LUT R12, R12, 0x80000000, R16, 0x48, !PT ; /* 0x800000000c0c7812 */
/* 0x000fe200078e4810 */
/*0ba0*/ BRA 0xbe0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ MUFU.RSQ R12, -QNAN ; /* 0xffc00000000c7908 */
/* 0x000e220000001400 */
/*0bc0*/ BRA 0xbe0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ FADD.FTZ R12, R16, R12 ; /* 0x0000000c100c7221 */
/* 0x000fe40000010000 */
/*0be0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bf0*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fcc00000001ff */
/*0c00*/ RET.REL.NODEC R14 0x0 ; /* 0xfffff3f00e007950 */
/* 0x000fea0003c3ffff */
/*0c10*/ BRA 0xc10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiPf
.globl _Z6kernelPiPf
.p2align 8
.type _Z6kernelPiPf,@function
_Z6kernelPiPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
v_dual_mov_b32 v11, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v1, s2, s[14:15]
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v4, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_store_b32 v[9:10], v11, off
v_cmpx_gt_i32_e32 0x1606c0, v2
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v0, v1, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b64 s[0:1], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, 0x1000, v0
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, 0x2000, v0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
s_clause 0x2
global_load_b96 v[0:2], v[0:1], off
global_load_b96 v[3:5], v[3:4], off offset:1464
global_load_b96 v[6:8], v[6:7], off offset:2928
.LBB0_2:
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
s_waitcnt vmcnt(0)
v_movrels_b32_e32 v12, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v12, v12
v_add_f32_e32 v11, v11, v12
s_cbranch_scc1 .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v12, null, 0x41100000, 0x41100000, v11
v_div_scale_f32 v15, vcc_lo, v11, 0x41100000, v11
s_mov_b64 s[0:1], 0
v_rcp_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v12, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v12, v14, v15
v_fmac_f32_e32 v14, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v12, v14, v15
v_div_fmas_f32 v12, v12, v13, v14
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v12, v12, 0x41100000, v11
v_mov_b32_e32 v11, 0
.LBB0_4:
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
v_movrels_b32_e32 v13, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v13, v13
v_sub_f32_e32 v13, v12, v13
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v13
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v0, null, 0x41100000, 0x41100000, v11
v_rcp_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v1, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v2, v1
v_div_scale_f32 v2, vcc_lo, v11, 0x41100000, v11
v_mul_f32_e32 v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v0, v3, v2
v_fmac_f32_e32 v3, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v0, v3, v2
v_div_fmas_f32 v0, v0, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v0, 0x41100000, v11
global_store_b32 v[9:10], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiPf, .Lfunc_end0-_Z6kernelPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012ffa5_00000000-6_1_varianza.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPiPfPiPf
.type _Z27__device_stub__Z6kernelPiPfPiPf, @function
_Z27__device_stub__Z6kernelPiPfPiPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPiPfPiPf, .-_Z27__device_stub__Z6kernelPiPfPiPf
.globl _Z6kernelPiPf
.type _Z6kernelPiPf, @function
_Z6kernelPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPiPf, .-_Z6kernelPiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "d=%d \n"
.LC1:
.string "RGB/"
.LC2:
.string "%s%d%s"
.LC3:
.string "/G"
.LC4:
.string "r+"
.LC5:
.string "%d"
.LC6:
.string "%s%d"
.LC7:
.string "w+"
.LC8:
.string "\n"
.LC9:
.string "%f "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "\ntiempo de procesamiento de varianzas: %6.3fs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $152, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, -140(%rbp)
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, -144(%rbp)
movl dimy(%rip), %eax
leal 2(%rax), %edx
movslq %edx, %rdx
leaq 0(,%rdx,4), %rax
movq %rax, -136(%rbp)
movl dimx(%rip), %eax
addl $2, %eax
cltq
imulq %rdx, %rax
salq $2, %rax
movq %rax, -168(%rbp)
leaq 15(%rax), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L12:
cmpq %rcx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L14
orq $0, -8(%rsp,%rdx)
.L14:
movq %rsp, -184(%rbp)
call clock@PLT
movq %rax, %r14
cmpl %ebx, %r12d
jl .L15
movq %rax, -192(%rbp)
jmp .L32
.L20:
movq (%r12), %rax
leaq (%rax,%rbx,4), %rdx
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
cmpl %ebx, dimy(%rip)
jg .L20
.L21:
addl $1, %r15d
addq $8, %r12
cmpl %r15d, dimx(%rip)
jle .L42
.L19:
movl $0, %ebx
cmpl $0, dimy(%rip)
jg .L20
jmp .L21
.L42:
movq -176(%rbp), %r15
.L18:
movq %r13, %rdi
call fclose@PLT
movl dimx(%rip), %eax
movl %eax, %r10d
addl $1, %r10d
js .L22
movl dimy(%rip), %r9d
leal 1(%r9), %r11d
movq -184(%rbp), %rdi
leal 2(%rax), %r12d
movl $0, %esi
movl $0, %ebx
addl $2, %r9d
movq -152(%rbp), %rcx
jmp .L23
.L35:
movl $0, %r13d
.L24:
movl %r13d, 4(%rdi,%rdx)
movl %r13d, 4(%r8,%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %eax, %r9d
je .L46
.L25:
testl %esi, %esi
setne %r14b
cmpl %r10d, %esi
setne %r13b
andl %r14d, %r13d
testl %eax, %eax
setne %r14b
testb %r14b, %r13b
je .L35
cmpl %eax, %r11d
je .L35
movq -8(%r15,%rsi,8), %r13
movl 0(%r13,%rdx), %r13d
jmp .L24
.L46:
leal 1(%r11,%rbx), %ebx
.L27:
addq $1, %rsi
movq -136(%rbp), %rax
addq %rax, %rdi
cmpq %rsi, %r12
je .L22
.L23:
testl %r11d, %r11d
js .L27
movslq %ebx, %rax
leaq (%rcx,%rax,4), %r8
movq $-4, %rdx
movl $0, %eax
jmp .L25
.L22:
movl $347, -100(%rbp)
movl $20, -96(%rbp)
movl $1, -92(%rbp)
movl $13, -88(%rbp)
movl $16, -84(%rbp)
movl $1, -80(%rbp)
movl $1, %ecx
movq -168(%rbp), %rdx
movq -152(%rbp), %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl -80(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -88(%rbp), %rdx
movq -100(%rbp), %rdi
movl -92(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L28:
movslq tam_imag(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq -112(%rbp), %rsi
movq -160(%rbp), %rdi
call cudaMemcpy@PLT
movabsq $4709162402679243094, %rax
movq %rax, -67(%rbp)
movl $3101505, -60(%rbp)
leaq -67(%rbp), %rbx
movl -140(%rbp), %r9d
movq %rbx, %r8
leaq .LC6(%rip), %rcx
movl $11, %edx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, tam_imag(%rip)
jle .L29
movl $0, %ebx
leaq .LC8(%rip), %r14
leaq .LC9(%rip), %r13
movq %r15, -176(%rbp)
movq -160(%rbp), %r15
jmp .L31
.L47:
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z27__device_stub__Z6kernelPiPfPiPf
jmp .L28
.L30:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, tam_imag(%rip)
jle .L48
.L31:
movl %ebx, %eax
cltd
idivl dimy(%rip)
testl %edx, %edx
jne .L30
testl %ebx, %ebx
je .L30
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L30
.L48:
movq -176(%rbp), %r15
.L29:
movq %r12, %rdi
call fclose@PLT
movq -152(%rbp), %rdi
call free@PLT
movq -160(%rbp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
addl $1, -140(%rbp)
movl -140(%rbp), %eax
movl -144(%rbp), %ecx
cmpl %ecx, %eax
jg .L49
.L32:
movl -140(%rbp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -168(%rbp), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, -152(%rbp)
leaq -120(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, -160(%rbp)
leaq -112(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl dimx(%rip), %ebx
movslq %ebx, %r12
leaq 0(,%r12,4), %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L16
movq %rax, %rbx
leaq (%rax,%r12,8), %r12
.L17:
movslq dimy(%rip), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L17
.L16:
movabsq $3419192486446524749, %rax
movq %rax, -76(%rbp)
movb $0, -68(%rbp)
leaq -76(%rbp), %rbx
subq $8, %rsp
leaq .LC3(%rip), %rax
pushq %rax
movl -140(%rbp), %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rcx
movl $9, %edx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $16, %rsp
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r13
cmpl $0, dimx(%rip)
jle .L18
movq %r15, %r12
movl $0, %eax
leaq .LC5(%rip), %r14
movq %r15, -176(%rbp)
movl %eax, %r15d
jmp .L19
.L49:
movq -192(%rbp), %r14
.L15:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r14, %xmm1
subss %xmm1, %xmm0
divss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L50:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z6kernelPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tam_imag
.data
.align 4
.type tam_imag, @object
.size tam_imag, 4
tam_imag:
.long 1443520
.globl dimy
.align 4
.type dimy, @object
.size dimy, 4
dimy:
.long 1388
.globl dimx
.align 4
.type dimx, @object
.size dimx, 4
dimx:
.long 1040
.globl msk
.align 4
.type msk, @object
.size msk, 4
msk:
.long 3
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1_varianza.hip"
.globl _Z21__device_stub__kernelPiPf # -- Begin function _Z21__device_stub__kernelPiPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiPf,@function
_Z21__device_stub__kernelPiPf: # @_Z21__device_stub__kernelPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiPf, .Lfunc_end0-_Z21__device_stub__kernelPiPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq dimx(%rip), %r15
movslq dimy(%rip), %rbx
callq clock
movq %rax, 64(%rsp) # 8-byte Spill
movq %r14, 72(%rsp) # 8-byte Spill
cmpl %r14d, %ebp
jle .LBB1_1
.LBB1_32: # %._crit_edge103
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
cvtsi2ssq 64(%rsp), %xmm1 # 8-byte Folded Reload
subss %xmm1, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1: # %.lr.ph102
.cfi_def_cfa_offset 208
addq $2, %rbx
addq $2, %r15
imulq %rbx, %r15
shlq $2, %r15
movq %r15, 32(%rsp) # 8-byte Spill
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_31: # %._crit_edge98
# in Loop: Header=BB1_2 Depth=1
movq %r13, %rdi
callq fclose
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
leal 1(%rbp), %eax
cmpl 72(%rsp), %ebp # 4-byte Folded Reload
movl %eax, %ebp
je .LBB1_32
.LBB1_2: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_7 Depth 2
# Child Loop BB1_9 Depth 3
# Child Loop BB1_13 Depth 2
# Child Loop BB1_15 Depth 3
# Child Loop BB1_27 Depth 2
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq tam_imag(%rip), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movslq dimx(%rip), %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, %r14
testq %rbx, %rbx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebx, %ebx
movslq dimy(%rip), %r12
shlq $2, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
callq malloc
movq %rax, (%r14,%r13,8)
incq %r13
cmpq %r13, %rbx
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movabsq $3419192486446524749, %rax # imm = 0x2F7369736554694D
movq %rax, 55(%rsp)
movb $0, 63(%rsp)
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.3, %r8d
leaq 55(%rsp), %rbx
movq %rbx, %rdi
movq %rbp, 80(%rsp) # 8-byte Spill
movl %ebp, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r13
cmpl $0, dimx(%rip)
jle .LBB1_11
# %bb.6: # %.preheader81.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %ebx, %ebx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %._crit_edge85
# in Loop: Header=BB1_7 Depth=2
incq %rbx
movslq dimx(%rip), %rax
cmpq %rax, %rbx
jge .LBB1_11
.LBB1_7: # %.preheader81
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
cmpl $0, dimy(%rip)
jle .LBB1_10
# %bb.8: # %.lr.ph84
# in Loop: Header=BB1_7 Depth=2
movq (%r14,%rbx,8), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_7 Depth=2
# => This Inner Loop Header: Depth=3
movl $.L.str.5, %esi
movq %r13, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq dimy(%rip), %rax
addq $4, %r12
cmpq %rax, %rbp
jl .LBB1_9
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_11: # %._crit_edge87
# in Loop: Header=BB1_2 Depth=1
movq %r13, %rdi
callq fclose
movl dimx(%rip), %eax
cmpl $-1, %eax
movq 80(%rsp), %rbp # 8-byte Reload
movq 40(%rsp), %rsi # 8-byte Reload
jl .LBB1_23
# %bb.12: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl dimy(%rip), %ecx
leal 1(%rax), %edx
leal 1(%rcx), %r12d
leal 2(%rcx), %edi
addl $2, %eax
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_21: # %._crit_edge91.loopexit
# in Loop: Header=BB1_13 Depth=2
addl %r10d, %r9d
.LBB1_22: # %._crit_edge91
# in Loop: Header=BB1_13 Depth=2
incq %r8
cmpq %rax, %r8
je .LBB1_23
.LBB1_13: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_15 Depth 3
cmpl $-1, %ecx
jl .LBB1_22
# %bb.14: # %.lr.ph90
# in Loop: Header=BB1_13 Depth=2
movslq %r9d, %r10
leaq (%rsi,%r10,4), %r11
xorl %r10d, %r10d
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_15 Depth=3
movl %ebx, (%r11,%r10,4)
incq %r10
cmpq %r10, %rdi
je .LBB1_21
.LBB1_15: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_13 Depth=2
# => This Inner Loop Header: Depth=3
xorl %ebx, %ebx
testq %r8, %r8
je .LBB1_20
# %bb.16: # in Loop: Header=BB1_15 Depth=3
testq %r10, %r10
je .LBB1_20
# %bb.17: # in Loop: Header=BB1_15 Depth=3
cmpq %rdx, %r8
je .LBB1_20
# %bb.18: # in Loop: Header=BB1_15 Depth=3
cmpq %r10, %r12
je .LBB1_20
# %bb.19: # in Loop: Header=BB1_15 Depth=3
movq -8(%r14,%r8,8), %rbx
movl -4(%rbx,%r10,4), %ebx
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_23: # %._crit_edge94
# in Loop: Header=BB1_2 Depth=1
movq 8(%rsp), %rdi
movq 32(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movabsq $85899346267, %rdi # imm = 0x140000015B
movl $1, %esi
movabsq $68719476749, %rdx # imm = 0x100000000D
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_25
# %bb.24: # in Loop: Header=BB1_2 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 16(%rsp)
leaq 136(%rsp), %rax
movq %rax, 24(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z6kernelPiPf, %edi
leaq 16(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_25: # in Loop: Header=BB1_2 Depth=1
movq (%rsp), %rsi
movslq tam_imag(%rip), %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movabsq $4709162402679243094, %rax # imm = 0x415A4E4149524156
movq %rax, 16(%rsp)
movw $12115, 24(%rsp) # imm = 0x2F53
movb $0, 26(%rsp)
movl $.L.str.6, %esi
leaq 16(%rsp), %rbx
movq %rbx, %rdi
movq %rbx, %rdx
movl %ebp, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.7, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r13
cmpl $0, tam_imag(%rip)
jle .LBB1_31
# %bb.26: # %.lr.ph97.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r12d, %r12d
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_30: # in Loop: Header=BB1_27 Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %esi
movq %r13, %rdi
movb $1, %al
callq fprintf
incq %r12
movslq tam_imag(%rip), %rax
cmpq %rax, %r12
jge .LBB1_31
.LBB1_27: # %.lr.ph97
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r12d, %eax
cltd
idivl dimy(%rip)
testq %r12, %r12
je .LBB1_30
# %bb.28: # %.lr.ph97
# in Loop: Header=BB1_27 Depth=2
testl %edx, %edx
jne .LBB1_30
# %bb.29: # in Loop: Header=BB1_27 Depth=2
movl $10, %edi
movq %r13, %rsi
callq fputc@PLT
jmp .LBB1_30
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type msk,@object # @msk
.data
.globl msk
.p2align 2, 0x0
msk:
.long 3 # 0x3
.size msk, 4
.type dimx,@object # @dimx
.globl dimx
.p2align 2, 0x0
dimx:
.long 1040 # 0x410
.size dimx, 4
.type dimy,@object # @dimy
.globl dimy
.p2align 2, 0x0
dimy:
.long 1388 # 0x56c
.size dimy, 4
.type tam_imag,@object # @tam_imag
.globl tam_imag
.p2align 2, 0x0
tam_imag:
.long 1443520 # 0x1606c0
.size tam_imag, 4
.type _Z6kernelPiPf,@object # @_Z6kernelPiPf
.section .rodata,"a",@progbits
.globl _Z6kernelPiPf
.p2align 3, 0x0
_Z6kernelPiPf:
.quad _Z21__device_stub__kernelPiPf
.size _Z6kernelPiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "d=%d \n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s%d%s"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "RGB/"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/G"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r+"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s%d"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "w+"
.size .L.str.7, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%f "
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\ntiempo de procesamiento de varianzas: %6.3fs\n"
.size .L.str.10, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct CudaMatrixStruct {
double *data;
int height, width;
} CudaMatrix;
__global__ void CudaPrintMatrix(CudaMatrix *A){
printf("Elementos de CudaMatrix:\n");
for(int i = 0; i < A->height * A->width ; i++)
printf("%d: %.3lf\n", i, A->data[i]);
printf("CudaMatrix->height: %d CudaMatrix->width: %d\n", A->height, A->width);
}
void CudaCreateMatrix(CudaMatrix *&AA,int hei,int wid){
double *d;// = new double[hei*wid];
d = (double *)malloc( hei * wid * sizeof(double) );
for(int i = 0 ; i < hei * wid ; i++)
d[i] = i + 1.0;
double *data;
cudaMalloc( (void **) &data, sizeof(double) * hei * wid );
cudaMemcpy( data , d , sizeof(double) * hei * wid , cudaMemcpyHostToDevice );
CudaMatrix *A = new CudaMatrix();
A->width = wid;
A->height = hei;
cudaMalloc((void **)&AA, sizeof(CudaMatrix));
cudaMemcpy(AA, A, sizeof(CudaMatrix), cudaMemcpyHostToDevice);
cudaMemcpy(&(AA->data), &data, sizeof(double *), cudaMemcpyHostToDevice);
CudaPrintMatrix<<<1, 1>>>(AA);
//cudaFree(AA);
//cudaFree(data);
}
int main() {
CudaMatrix *devGr;
int side = 1;
CudaCreateMatrix( devGr , 2 * side + 1 , 2 * side + 1 );
//CudaPrintMatrix<<<1,1>>>(devGr);//IMPRIME LA MATRICES CREADA
cudaFree(devGr);
} | code for sm_80
Function : _Z15CudaPrintMatrixP16CudaMatrixStruct
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*0060*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0070*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fcc0000000a00 */
/*0080*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*0090*/ MOV R11, 0x100 ; /* 0x00000100000b7802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R20, 0x80 ; /* 0x0000008000147802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*00c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*00d0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00e0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00f0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fcc00078e00ff */
/*0130*/ LDG.E.64 R8, [R8.64+0x8] ; /* 0x0000082408087981 */
/* 0x000ea2000c1e1b00 */
/*0140*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000ff1e03f */
/*0150*/ IADD3 R18, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001127a10 */
/* 0x000fc60007f3e0ff */
/*0160*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0170*/ IMAD.U32 R16, RZ, RZ, UR4 ; /* 0x00000004ff107e24 */
/* 0x000fe4000f8e00ff */
/*0180*/ IMAD.X R2, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff027624 */
/* 0x000fe400008e06ff */
/*0190*/ IMAD.U32 R17, RZ, RZ, UR5 ; /* 0x00000005ff117e24 */
/* 0x000fe4000f8e00ff */
/*01a0*/ IMAD R0, R8, R9, RZ ; /* 0x0000000908007224 */
/* 0x004fca00078e02ff */
/*01b0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*01c0*/ @!P0 BRA 0x3c0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*01d0*/ BSSY B6, 0x3c0 ; /* 0x000001e000067945 */
/* 0x000fe20003800000 */
/*01e0*/ CS2R R22, SRZ ; /* 0x0000000000167805 */
/* 0x000fe2000001ff00 */
/*01f0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc600078e00ff */
/*0200*/ LDG.E.64 R4, [R16.64+-0x8] ; /* 0xfffff82410047981 */
/* 0x000ea4000c1e1b00 */
/*0210*/ IADD3 R10, P0, R4, R19, RZ ; /* 0x00000013040a7210 */
/* 0x004fca0007f1e0ff */
/*0220*/ IMAD.X R11, R5, 0x1, R23, P0 ; /* 0x00000001050b7824 */
/* 0x000fcc00000e0617 */
/*0230*/ LD.E.64 R10, [R10.64] ; /* 0x000000240a0a7980 */
/* 0x000ea2000c101b00 */
/*0240*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0260*/ STL [R1], R22 ; /* 0x0000001601007387 */
/* 0x0001e20000100800 */
/*0270*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0280*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*02b0*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0041e80000100a00 */
/*02c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe20000000000 */
/*02d0*/ MOV R3, 0x340 ; /* 0x0000034000037802 */
/* 0x000fc40000000f00 */
/*02e0*/ MOV R20, 0x2c0 ; /* 0x000002c000147802 */
/* 0x000fe40000000f00 */
/*02f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0300*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0310*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0320*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0330*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0340*/ LDG.E.64 R8, [R16.64] ; /* 0x0000002410087981 */
/* 0x000ea2000c1e1b00 */
/*0350*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IADD3 R19, P1, R19, 0x8, RZ ; /* 0x0000000813137810 */
/* 0x000fca0007f3e0ff */
/*0370*/ IMAD.X R23, RZ, RZ, R23, P1 ; /* 0x000000ffff177224 */
/* 0x000fe400008e0617 */
/*0380*/ IMAD R3, R8, R9, RZ ; /* 0x0000000908037224 */
/* 0x004fca00078e02ff */
/*0390*/ ISETP.GE.AND P0, PT, R22, R3, PT ; /* 0x000000031600720c */
/* 0x000fda0003f06270 */
/*03a0*/ @!P0 BRA 0x200 ; /* 0xfffffe5000008947 */
/* 0x000fea000383ffff */
/*03b0*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*03c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*03d0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100a00 */
/*03e0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*03f0*/ LDC.64 R10, c[0x4][R0] ; /* 0x01000000000a7b82 */
/* 0x0000620000000a00 */
/*0400*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0410*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe400078e00ff */
/*0420*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fc600078e00ff */
/*0430*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x000fe20000000000 */
/*0440*/ MOV R9, 0x4b0 ; /* 0x000004b000097802 */
/* 0x001fc40000000f00 */
/*0450*/ MOV R20, 0x430 ; /* 0x0000043000147802 */
/* 0x000fe40000000f00 */
/*0460*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0470*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0480*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0490*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*04a0*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x002fea0003c00000 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct CudaMatrixStruct {
double *data;
int height, width;
} CudaMatrix;
__global__ void CudaPrintMatrix(CudaMatrix *A){
printf("Elementos de CudaMatrix:\n");
for(int i = 0; i < A->height * A->width ; i++)
printf("%d: %.3lf\n", i, A->data[i]);
printf("CudaMatrix->height: %d CudaMatrix->width: %d\n", A->height, A->width);
}
void CudaCreateMatrix(CudaMatrix *&AA,int hei,int wid){
double *d;// = new double[hei*wid];
d = (double *)malloc( hei * wid * sizeof(double) );
for(int i = 0 ; i < hei * wid ; i++)
d[i] = i + 1.0;
double *data;
cudaMalloc( (void **) &data, sizeof(double) * hei * wid );
cudaMemcpy( data , d , sizeof(double) * hei * wid , cudaMemcpyHostToDevice );
CudaMatrix *A = new CudaMatrix();
A->width = wid;
A->height = hei;
cudaMalloc((void **)&AA, sizeof(CudaMatrix));
cudaMemcpy(AA, A, sizeof(CudaMatrix), cudaMemcpyHostToDevice);
cudaMemcpy(&(AA->data), &data, sizeof(double *), cudaMemcpyHostToDevice);
CudaPrintMatrix<<<1, 1>>>(AA);
//cudaFree(AA);
//cudaFree(data);
}
int main() {
CudaMatrix *devGr;
int side = 1;
CudaCreateMatrix( devGr , 2 * side + 1 , 2 * side + 1 );
//CudaPrintMatrix<<<1,1>>>(devGr);//IMPRIME LA MATRICES CREADA
cudaFree(devGr);
} | .file "tmpxft_000ea7cf_00000000-6_copy2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10863:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct
.type _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct, @function
_Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct:
.LFB10885:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15CudaPrintMatrixP16CudaMatrixStruct(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10885:
.size _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct, .-_Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct
.globl _Z15CudaPrintMatrixP16CudaMatrixStruct
.type _Z15CudaPrintMatrixP16CudaMatrixStruct, @function
_Z15CudaPrintMatrixP16CudaMatrixStruct:
.LFB10886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _Z15CudaPrintMatrixP16CudaMatrixStruct, .-_Z15CudaPrintMatrixP16CudaMatrixStruct
.globl _Z16CudaCreateMatrixRP16CudaMatrixStructii
.type _Z16CudaCreateMatrixRP16CudaMatrixStructii, @function
_Z16CudaCreateMatrixRP16CudaMatrixStructii:
.LFB10859:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movl %esi, %r13d
movl %edx, %r14d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %r15d
imull %edx, %r15d
movslq %r15d, %rbp
leaq 0(,%rbp,8), %rdi
call malloc@PLT
movq %rax, %rbx
testl %r15d, %r15d
jle .L12
movl $0, %eax
movsd .LC0(%rip), %xmm1
.L13:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq %rax, %rbp
jne .L13
.L12:
movslq %r13d, %r15
movslq %r14d, %rax
imulq %rax, %r15
salq $3, %r15
leaq 8(%rsp), %rbp
movq %r15, %rsi
movq %rbp, %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, %edi
call _Znwm@PLT
movq %rax, %rbx
movq $0, (%rax)
movl %r14d, 12(%rax)
movl %r13d, 8(%rax)
movl $16, %esi
movq %r12, %rdi
call cudaMalloc@PLT
movq (%r12), %rdi
movl $1, %ecx
movl $16, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
movq (%r12), %rdi
movl $1, %ecx
movl $8, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L11:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq (%r12), %rdi
call _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct
jmp .L11
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10859:
.size _Z16CudaCreateMatrixRP16CudaMatrixStructii, .-_Z16CudaCreateMatrixRP16CudaMatrixStructii
.globl main
.type main, @function
main:
.LFB10860:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $3, %edx
movl $3, %esi
call _Z16CudaCreateMatrixRP16CudaMatrixStructii
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10860:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z15CudaPrintMatrixP16CudaMatrixStruct"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10888:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15CudaPrintMatrixP16CudaMatrixStruct(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10888:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct CudaMatrixStruct {
double *data;
int height, width;
} CudaMatrix;
__global__ void CudaPrintMatrix(CudaMatrix *A){
printf("Elementos de CudaMatrix:\n");
for(int i = 0; i < A->height * A->width ; i++)
printf("%d: %.3lf\n", i, A->data[i]);
printf("CudaMatrix->height: %d CudaMatrix->width: %d\n", A->height, A->width);
}
void CudaCreateMatrix(CudaMatrix *&AA,int hei,int wid){
double *d;// = new double[hei*wid];
d = (double *)malloc( hei * wid * sizeof(double) );
for(int i = 0 ; i < hei * wid ; i++)
d[i] = i + 1.0;
double *data;
cudaMalloc( (void **) &data, sizeof(double) * hei * wid );
cudaMemcpy( data , d , sizeof(double) * hei * wid , cudaMemcpyHostToDevice );
CudaMatrix *A = new CudaMatrix();
A->width = wid;
A->height = hei;
cudaMalloc((void **)&AA, sizeof(CudaMatrix));
cudaMemcpy(AA, A, sizeof(CudaMatrix), cudaMemcpyHostToDevice);
cudaMemcpy(&(AA->data), &data, sizeof(double *), cudaMemcpyHostToDevice);
CudaPrintMatrix<<<1, 1>>>(AA);
//cudaFree(AA);
//cudaFree(data);
}
int main() {
CudaMatrix *devGr;
int side = 1;
CudaCreateMatrix( devGr , 2 * side + 1 , 2 * side + 1 );
//CudaPrintMatrix<<<1,1>>>(devGr);//IMPRIME LA MATRICES CREADA
cudaFree(devGr);
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct CudaMatrixStruct {
double *data;
int height, width;
} CudaMatrix;
__global__ void CudaPrintMatrix(CudaMatrix *A){
printf("Elementos de CudaMatrix:\n");
for(int i = 0; i < A->height * A->width ; i++)
printf("%d: %.3lf\n", i, A->data[i]);
printf("CudaMatrix->height: %d CudaMatrix->width: %d\n", A->height, A->width);
}
void CudaCreateMatrix(CudaMatrix *&AA,int hei,int wid){
double *d;// = new double[hei*wid];
d = (double *)malloc( hei * wid * sizeof(double) );
for(int i = 0 ; i < hei * wid ; i++)
d[i] = i + 1.0;
double *data;
hipMalloc( (void **) &data, sizeof(double) * hei * wid );
hipMemcpy( data , d , sizeof(double) * hei * wid , hipMemcpyHostToDevice );
CudaMatrix *A = new CudaMatrix();
A->width = wid;
A->height = hei;
hipMalloc((void **)&AA, sizeof(CudaMatrix));
hipMemcpy(AA, A, sizeof(CudaMatrix), hipMemcpyHostToDevice);
hipMemcpy(&(AA->data), &data, sizeof(double *), hipMemcpyHostToDevice);
CudaPrintMatrix<<<1, 1>>>(AA);
//cudaFree(AA);
//cudaFree(data);
}
int main() {
CudaMatrix *devGr;
int side = 1;
CudaCreateMatrix( devGr , 2 * side + 1 , 2 * side + 1 );
//CudaPrintMatrix<<<1,1>>>(devGr);//IMPRIME LA MATRICES CREADA
hipFree(devGr);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
typedef struct CudaMatrixStruct {
double *data;
int height, width;
} CudaMatrix;
__global__ void CudaPrintMatrix(CudaMatrix *A){
printf("Elementos de CudaMatrix:\n");
for(int i = 0; i < A->height * A->width ; i++)
printf("%d: %.3lf\n", i, A->data[i]);
printf("CudaMatrix->height: %d CudaMatrix->width: %d\n", A->height, A->width);
}
void CudaCreateMatrix(CudaMatrix *&AA,int hei,int wid){
double *d;// = new double[hei*wid];
d = (double *)malloc( hei * wid * sizeof(double) );
for(int i = 0 ; i < hei * wid ; i++)
d[i] = i + 1.0;
double *data;
hipMalloc( (void **) &data, sizeof(double) * hei * wid );
hipMemcpy( data , d , sizeof(double) * hei * wid , hipMemcpyHostToDevice );
CudaMatrix *A = new CudaMatrix();
A->width = wid;
A->height = hei;
hipMalloc((void **)&AA, sizeof(CudaMatrix));
hipMemcpy(AA, A, sizeof(CudaMatrix), hipMemcpyHostToDevice);
hipMemcpy(&(AA->data), &data, sizeof(double *), hipMemcpyHostToDevice);
CudaPrintMatrix<<<1, 1>>>(AA);
//cudaFree(AA);
//cudaFree(data);
}
int main() {
CudaMatrix *devGr;
int side = 1;
CudaCreateMatrix( devGr , 2 * side + 1 , 2 * side + 1 );
//CudaPrintMatrix<<<1,1>>>(devGr);//IMPRIME LA MATRICES CREADA
hipFree(devGr);
} | .text
.file "copy2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct # -- Begin function _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.p2align 4, 0x90
.type _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct,@function
_Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct: # @_Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15CudaPrintMatrixP16CudaMatrixStruct, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct, .Lfunc_end0-_Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16CudaCreateMatrixRP16CudaMatrixStructii
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z16CudaCreateMatrixRP16CudaMatrixStructii
.p2align 4, 0x90
.type _Z16CudaCreateMatrixRP16CudaMatrixStructii,@function
_Z16CudaCreateMatrixRP16CudaMatrixStructii: # @_Z16CudaCreateMatrixRP16CudaMatrixStructii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r14d
movq %rdi, %rbx
movl %edx, %r12d
imull %esi, %r12d
movslq %r12d, %r13
leaq (,%r13,8), %rdi
callq malloc
movq %rax, %r15
testl %r13d, %r13d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%r15,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
movslq %r14d, %r13
movslq %ebp, %rbp
movq %r13, %r12
imulq %rbp, %r12
shlq $3, %r12
leaq 8(%rsp), %r14
movq %r14, %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $16, %edi
callq _Znwm
movq %rax, %r15
xorpd %xmm0, %xmm0
movapd %xmm0, (%rax)
movl %ebp, 12(%rax)
movl %r13d, 8(%rax)
movl $16, %esi
movq %rbx, %rdi
callq hipMalloc
movq (%rbx), %rdi
movl $16, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rbx), %rdi
movl $8, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq (%rbx), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15CudaPrintMatrixP16CudaMatrixStruct, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16CudaCreateMatrixRP16CudaMatrixStructii, .Lfunc_end1-_Z16CudaCreateMatrixRP16CudaMatrixStructii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $3, %esi
movl $3, %edx
callq _Z16CudaCreateMatrixRP16CudaMatrixStructii
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15CudaPrintMatrixP16CudaMatrixStruct, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15CudaPrintMatrixP16CudaMatrixStruct,@object # @_Z15CudaPrintMatrixP16CudaMatrixStruct
.section .rodata,"a",@progbits
.globl _Z15CudaPrintMatrixP16CudaMatrixStruct
.p2align 3, 0x0
_Z15CudaPrintMatrixP16CudaMatrixStruct:
.quad _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.size _Z15CudaPrintMatrixP16CudaMatrixStruct, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15CudaPrintMatrixP16CudaMatrixStruct"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15CudaPrintMatrixP16CudaMatrixStruct
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ea7cf_00000000-6_copy2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10863:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct
.type _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct, @function
_Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct:
.LFB10885:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15CudaPrintMatrixP16CudaMatrixStruct(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10885:
.size _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct, .-_Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct
.globl _Z15CudaPrintMatrixP16CudaMatrixStruct
.type _Z15CudaPrintMatrixP16CudaMatrixStruct, @function
_Z15CudaPrintMatrixP16CudaMatrixStruct:
.LFB10886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _Z15CudaPrintMatrixP16CudaMatrixStruct, .-_Z15CudaPrintMatrixP16CudaMatrixStruct
.globl _Z16CudaCreateMatrixRP16CudaMatrixStructii
.type _Z16CudaCreateMatrixRP16CudaMatrixStructii, @function
_Z16CudaCreateMatrixRP16CudaMatrixStructii:
.LFB10859:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movl %esi, %r13d
movl %edx, %r14d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %r15d
imull %edx, %r15d
movslq %r15d, %rbp
leaq 0(,%rbp,8), %rdi
call malloc@PLT
movq %rax, %rbx
testl %r15d, %r15d
jle .L12
movl $0, %eax
movsd .LC0(%rip), %xmm1
.L13:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq %rax, %rbp
jne .L13
.L12:
movslq %r13d, %r15
movslq %r14d, %rax
imulq %rax, %r15
salq $3, %r15
leaq 8(%rsp), %rbp
movq %r15, %rsi
movq %rbp, %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, %edi
call _Znwm@PLT
movq %rax, %rbx
movq $0, (%rax)
movl %r14d, 12(%rax)
movl %r13d, 8(%rax)
movl $16, %esi
movq %r12, %rdi
call cudaMalloc@PLT
movq (%r12), %rdi
movl $1, %ecx
movl $16, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
movq (%r12), %rdi
movl $1, %ecx
movl $8, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L11:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq (%r12), %rdi
call _Z52__device_stub__Z15CudaPrintMatrixP16CudaMatrixStructP16CudaMatrixStruct
jmp .L11
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10859:
.size _Z16CudaCreateMatrixRP16CudaMatrixStructii, .-_Z16CudaCreateMatrixRP16CudaMatrixStructii
.globl main
.type main, @function
main:
.LFB10860:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $3, %edx
movl $3, %esi
call _Z16CudaCreateMatrixRP16CudaMatrixStructii
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10860:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z15CudaPrintMatrixP16CudaMatrixStruct"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10888:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15CudaPrintMatrixP16CudaMatrixStruct(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10888:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copy2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct # -- Begin function _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.p2align 4, 0x90
.type _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct,@function
_Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct: # @_Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15CudaPrintMatrixP16CudaMatrixStruct, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct, .Lfunc_end0-_Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16CudaCreateMatrixRP16CudaMatrixStructii
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z16CudaCreateMatrixRP16CudaMatrixStructii
.p2align 4, 0x90
.type _Z16CudaCreateMatrixRP16CudaMatrixStructii,@function
_Z16CudaCreateMatrixRP16CudaMatrixStructii: # @_Z16CudaCreateMatrixRP16CudaMatrixStructii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r14d
movq %rdi, %rbx
movl %edx, %r12d
imull %esi, %r12d
movslq %r12d, %r13
leaq (,%r13,8), %rdi
callq malloc
movq %rax, %r15
testl %r13d, %r13d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %r12d, %eax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%r15,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
movslq %r14d, %r13
movslq %ebp, %rbp
movq %r13, %r12
imulq %rbp, %r12
shlq $3, %r12
leaq 8(%rsp), %r14
movq %r14, %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $16, %edi
callq _Znwm
movq %rax, %r15
xorpd %xmm0, %xmm0
movapd %xmm0, (%rax)
movl %ebp, 12(%rax)
movl %r13d, 8(%rax)
movl $16, %esi
movq %rbx, %rdi
callq hipMalloc
movq (%rbx), %rdi
movl $16, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rbx), %rdi
movl $8, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq (%rbx), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15CudaPrintMatrixP16CudaMatrixStruct, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16CudaCreateMatrixRP16CudaMatrixStructii, .Lfunc_end1-_Z16CudaCreateMatrixRP16CudaMatrixStructii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $3, %esi
movl $3, %edx
callq _Z16CudaCreateMatrixRP16CudaMatrixStructii
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15CudaPrintMatrixP16CudaMatrixStruct, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15CudaPrintMatrixP16CudaMatrixStruct,@object # @_Z15CudaPrintMatrixP16CudaMatrixStruct
.section .rodata,"a",@progbits
.globl _Z15CudaPrintMatrixP16CudaMatrixStruct
.p2align 3, 0x0
_Z15CudaPrintMatrixP16CudaMatrixStruct:
.quad _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.size _Z15CudaPrintMatrixP16CudaMatrixStruct, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15CudaPrintMatrixP16CudaMatrixStruct"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__CudaPrintMatrixP16CudaMatrixStruct
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15CudaPrintMatrixP16CudaMatrixStruct
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <time.h>
#include <stdio.h>
#define gpuErrchck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
__global__ void gpu_loop(int n, int *n_ret_device)
{
int bsize = blockDim.x;
int tid = threadIdx.x;
int i;
for(i = tid*(n/bsize) ; i < (tid+1)*(n/bsize) ; ++i)
n_ret_device[i] = i;
}
void cpu_loop(int n, int *n_ret_host)
{
int i;
for(i=0;i<n;++i)
n_ret_host[i] = i;
}
int main()
{
int N = 10000000;
int *n_ret_host = new int[N];
int *n_ret_device = NULL;
gpuErrchck( cudaMalloc((void**)&n_ret_device,N*sizeof(int)) );
clock_t start, end;
double cpu_time_used;
start = clock();
gpu_loop<<< 1,5 >>>(N,n_ret_device);
gpuErrchck( cudaMemcpy((void*)n_ret_host, (void*)n_ret_device, N*sizeof(int), cudaMemcpyDeviceToHost) );
gpuErrchck( cudaDeviceSynchronize() );
end = clock();
cout<<n_ret_host[1]<<endl;
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
start = clock();
cpu_loop(N,n_ret_host);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
delete[] n_ret_host;
cudaFree((void*)n_ret_device);
return 0;
} | code for sm_80
Function : _Z8gpu_loopiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x0] ; /* 0x0000000000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*0050*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fcc000f8e3c3f */
/*0060*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0070*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00d0*/ IABS R4, c[0x0][0x160] ; /* 0x0000580000047a13 */
/* 0x000fc60000000000 */
/*00e0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00f0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0110*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0120*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*0130*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a05 */
/*0140*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe40003f45270 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0170*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e360000002100 */
/*0180*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0190*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01a0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fca00078e33ff */
/*01b0*/ IMAD R5, R3, R5, RZ ; /* 0x0000000503057224 */
/* 0x001fc800078e02ff */
/*01c0*/ IMAD.IADD R0, R3, 0x1, R5 ; /* 0x0000000103007824 */
/* 0x000fca00078e0205 */
/*01d0*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06270 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ LOP3.LUT P1, R4, R3.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x040fe2000782c0ff */
/*0200*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0210*/ IADD3 R2, R3, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x000fc80007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fce0003f06070 */
/*0230*/ @!P1 BRA 0x2d0 ; /* 0x0000009000009947 */
/* 0x000fec0003800000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.WIDE R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0202 */
/*0260*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e6000c101904 */
/*0280*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0290*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f5e0ff */
/*02a0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fcc00010e0603 */
/*02c0*/ @P1 BRA 0x260 ; /* 0xffffff9000001947 */
/* 0x000fea000383ffff */
/*02d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe200078e0a05 */
/*02f0*/ BSSY B0, 0x600 ; /* 0x0000030000007945 */
/* 0x000fe20003800000 */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0310*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0320*/ IMAD.WIDE R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fca00078e0202 */
/*0330*/ IADD3 R2, P0, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f1e0ff */
/*0340*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0360*/ @!P1 BRA 0x5f0 ; /* 0x0000028000009947 */
/* 0x000fee0003800000 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0380*/ IADD3 R6, R0, -0xc, RZ ; /* 0xfffffff400067810 */
/* 0x000fc60007ffe0ff */
/*0390*/ IADD3 R25, R5.reuse, 0x1, RZ ; /* 0x0000000105197810 */
/* 0x040fe20007ffe0ff */
/*03a0*/ STG.E [R2.64+-0x8], R5 ; /* 0xfffff80502007986 */
/* 0x000fe2000c101904 */
/*03b0*/ IADD3 R7, R5.reuse, 0x2, RZ ; /* 0x0000000205077810 */
/* 0x040fe40007ffe0ff */
/*03c0*/ IADD3 R9, R5.reuse, 0x3, RZ ; /* 0x0000000305097810 */
/* 0x040fe20007ffe0ff */
/*03d0*/ STG.E [R2.64+-0x4], R25 ; /* 0xfffffc1902007986 */
/* 0x0001e2000c101904 */
/*03e0*/ IADD3 R11, R5, 0x4, RZ ; /* 0x00000004050b7810 */
/* 0x000fc40007ffe0ff */
/*03f0*/ IADD3 R13, R5.reuse, 0x5, RZ ; /* 0x00000005050d7810 */
/* 0x040fe20007ffe0ff */
/*0400*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e2000c101904 */
/*0410*/ IADD3 R15, R5.reuse, 0x6, RZ ; /* 0x00000006050f7810 */
/* 0x040fe40007ffe0ff */
/*0420*/ IADD3 R17, R5.reuse, 0x7, RZ ; /* 0x0000000705117810 */
/* 0x040fe20007ffe0ff */
/*0430*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x0005e2000c101904 */
/*0440*/ IADD3 R19, R5.reuse, 0x8, RZ ; /* 0x0000000805137810 */
/* 0x040fe40007ffe0ff */
/*0450*/ IADD3 R21, R5.reuse, 0x9, RZ ; /* 0x0000000905157810 */
/* 0x040fe20007ffe0ff */
/*0460*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x0007e2000c101904 */
/*0470*/ IADD3 R23, R5, 0xa, RZ ; /* 0x0000000a05177810 */
/* 0x000fc40007ffe0ff */
/*0480*/ IADD3 R25, R5.reuse, 0xf, RZ ; /* 0x0000000f05197810 */
/* 0x041fe20007ffe0ff */
/*0490*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0001e2000c101904 */
/*04a0*/ IADD3 R7, R5.reuse, 0xb, RZ ; /* 0x0000000b05077810 */
/* 0x042fe40007ffe0ff */
/*04b0*/ IADD3 R4, P2, R2, 0x40, RZ ; /* 0x0000004002047810 */
/* 0x000fe20007f5e0ff */
/*04c0*/ STG.E [R2.64+0x10], R15 ; /* 0x0000100f02007986 */
/* 0x0003e2000c101904 */
/*04d0*/ IADD3 R9, R5.reuse, 0xc, RZ ; /* 0x0000000c05097810 */
/* 0x044fe40007ffe0ff */
/*04e0*/ IADD3 R11, R5.reuse, 0xd, RZ ; /* 0x0000000d050b7810 */
/* 0x048fe20007ffe0ff */
/*04f0*/ STG.E [R2.64+0x14], R17 ; /* 0x0000141102007986 */
/* 0x000fe2000c101904 */
/*0500*/ IADD3 R13, R5, 0xe, RZ ; /* 0x0000000e050d7810 */
/* 0x001fc60007ffe0ff */
/*0510*/ STG.E [R2.64+0x18], R19 ; /* 0x0000181302007986 */
/* 0x000fe2000c101904 */
/*0520*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*0530*/ IMAD.X R15, RZ, RZ, R3, P2 ; /* 0x000000ffff0f7224 */
/* 0x002fe400010e0603 */
/*0540*/ STG.E [R2.64+0x1c], R21 ; /* 0x00001c1502007986 */
/* 0x000fe2000c101904 */
/*0550*/ ISETP.GE.AND P1, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x000fc60003f26270 */
/*0560*/ STG.E [R2.64+0x20], R23 ; /* 0x0000201702007986 */
/* 0x000fe8000c101904 */
/*0570*/ STG.E [R2.64+0x24], R7 ; /* 0x0000240702007986 */
/* 0x000fe8000c101904 */
/*0580*/ STG.E [R2.64+0x28], R9 ; /* 0x0000280902007986 */
/* 0x000fe8000c101904 */
/*0590*/ STG.E [R2.64+0x2c], R11 ; /* 0x00002c0b02007986 */
/* 0x000fe8000c101904 */
/*05a0*/ STG.E [R2.64+0x30], R13 ; /* 0x0000300d02007986 */
/* 0x000fe8000c101904 */
/*05b0*/ STG.E [R2.64+0x34], R25 ; /* 0x0000341902007986 */
/* 0x0001e4000c101904 */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0004 */
/*05d0*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*05e0*/ @!P1 BRA 0x390 ; /* 0xfffffda000009947 */
/* 0x000fea000383ffff */
/*05f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0600*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe200078e0a05 */
/*0610*/ BSSY B0, 0x7a0 ; /* 0x0000018000007945 */
/* 0x000fe80003800000 */
/*0620*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0630*/ @!P1 BRA 0x790 ; /* 0x0000015000009947 */
/* 0x000fea0003800000 */
/*0640*/ IADD3 R7, R5.reuse, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x040fe20007ffe0ff */
/*0650*/ STG.E [R2.64+-0x8], R5 ; /* 0xfffff80502007986 */
/* 0x000fe2000c101904 */
/*0660*/ IADD3 R4, P1, R2, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x000fe40007f3e0ff */
/*0670*/ IADD3 R9, R5.reuse, 0x2, RZ ; /* 0x0000000205097810 */
/* 0x040fe20007ffe0ff */
/*0680*/ STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702007986 */
/* 0x0001e2000c101904 */
/*0690*/ IADD3 R11, R5.reuse, 0x3, RZ ; /* 0x00000003050b7810 */
/* 0x040fe40007ffe0ff */
/*06a0*/ IADD3 R13, R5.reuse, 0x4, RZ ; /* 0x00000004050d7810 */
/* 0x040fe20007ffe0ff */
/*06b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*06c0*/ IADD3 R15, R5, 0x5, RZ ; /* 0x00000005050f7810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ IADD3 R17, R5.reuse, 0x6, RZ ; /* 0x0000000605117810 */
/* 0x040fe20007ffe0ff */
/*06e0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x000fe2000c101904 */
/*06f0*/ IADD3 R19, R5.reuse, 0x7, RZ ; /* 0x0000000705137810 */
/* 0x040fe40007ffe0ff */
/*0700*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0710*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x001fe200008e0603 */
/*0720*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x000fe2000c101904 */
/*0730*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fc60007ffe0ff */
/*0740*/ STG.E [R2.64+0xc], R15 ; /* 0x00000c0f02007986 */
/* 0x000fe8000c101904 */
/*0750*/ STG.E [R2.64+0x10], R17 ; /* 0x0000101102007986 */
/* 0x000fe8000c101904 */
/*0760*/ STG.E [R2.64+0x14], R19 ; /* 0x0000141302007986 */
/* 0x0001e4000c101904 */
/*0770*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0004 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0790*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.LT.OR P0, PT, R5, R0, P0 ; /* 0x000000000500720c */
/* 0x000fda0000701670 */
/*07b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07c0*/ IADD3 R7, R5.reuse, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x040fe20007ffe0ff */
/*07d0*/ STG.E [R2.64+-0x8], R5 ; /* 0xfffff80502007986 */
/* 0x000fe2000c101904 */
/*07e0*/ IADD3 R9, R5.reuse, 0x2, RZ ; /* 0x0000000205097810 */
/* 0x040fe40007ffe0ff */
/*07f0*/ IADD3 R11, R5, 0x3, RZ ; /* 0x00000003050b7810 */
/* 0x000fe20007ffe0ff */
/*0800*/ STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702007986 */
/* 0x000fe8000c101904 */
/*0810*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0820*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <time.h>
#include <stdio.h>
#define gpuErrchck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
__global__ void gpu_loop(int n, int *n_ret_device)
{
int bsize = blockDim.x;
int tid = threadIdx.x;
int i;
for(i = tid*(n/bsize) ; i < (tid+1)*(n/bsize) ; ++i)
n_ret_device[i] = i;
}
void cpu_loop(int n, int *n_ret_host)
{
int i;
for(i=0;i<n;++i)
n_ret_host[i] = i;
}
int main()
{
int N = 10000000;
int *n_ret_host = new int[N];
int *n_ret_device = NULL;
gpuErrchck( cudaMalloc((void**)&n_ret_device,N*sizeof(int)) );
clock_t start, end;
double cpu_time_used;
start = clock();
gpu_loop<<< 1,5 >>>(N,n_ret_device);
gpuErrchck( cudaMemcpy((void*)n_ret_host, (void*)n_ret_device, N*sizeof(int), cudaMemcpyDeviceToHost) );
gpuErrchck( cudaDeviceSynchronize() );
end = clock();
cout<<n_ret_host[1]<<endl;
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
start = clock();
cpu_loop(N,n_ret_host);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
delete[] n_ret_host;
cudaFree((void*)n_ret_device);
return 0;
} | .file "tmpxft_00008e63_00000000-6_trial.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z8cpu_loopiPi
.type _Z8cpu_loopiPi, @function
_Z8cpu_loopiPi:
.LFB3670:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L11
movslq %edi, %rdi
movl $0, %eax
.L13:
movl %eax, (%rsi,%rax,4)
addq $1, %rax
cmpq %rdi, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE3670:
.size _Z8cpu_loopiPi, .-_Z8cpu_loopiPi
.globl _Z28__device_stub__Z8gpu_loopiPiiPi
.type _Z28__device_stub__Z8gpu_loopiPiiPi, @function
_Z28__device_stub__Z8gpu_loopiPiiPi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_loopiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z28__device_stub__Z8gpu_loopiPiiPi, .-_Z28__device_stub__Z8gpu_loopiPiiPi
.globl _Z8gpu_loopiPi
.type _Z8gpu_loopiPi, @function
_Z8gpu_loopiPi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8gpu_loopiPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8gpu_loopiPi, .-_Z8gpu_loopiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/elektronicaIITH/cuda_sessions/master/trial.cu"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $40000000, %edi
call _Znam@PLT
movq %rax, %rbx
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $42, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
call clock@PLT
movq %rax, %r13
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
movl $2, %ecx
movl $40000000, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $49, %edx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $50, %edx
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call clock@PLT
movq %rax, %rbp
movl 4(%rbx), %esi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
subq %r13, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC2(%rip), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %rbp
movq %rbx, %rsi
movl $10000000, %edi
call _Z8cpu_loopiPi
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 8(%rsp), %rsi
movl $10000000, %edi
call _Z28__device_stub__Z8gpu_loopiPiiPi
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z8gpu_loopiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_loopiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <time.h>
#include <stdio.h>
#define gpuErrchck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
__global__ void gpu_loop(int n, int *n_ret_device)
{
int bsize = blockDim.x;
int tid = threadIdx.x;
int i;
for(i = tid*(n/bsize) ; i < (tid+1)*(n/bsize) ; ++i)
n_ret_device[i] = i;
}
void cpu_loop(int n, int *n_ret_host)
{
int i;
for(i=0;i<n;++i)
n_ret_host[i] = i;
}
int main()
{
int N = 10000000;
int *n_ret_host = new int[N];
int *n_ret_device = NULL;
gpuErrchck( cudaMalloc((void**)&n_ret_device,N*sizeof(int)) );
clock_t start, end;
double cpu_time_used;
start = clock();
gpu_loop<<< 1,5 >>>(N,n_ret_device);
gpuErrchck( cudaMemcpy((void*)n_ret_host, (void*)n_ret_device, N*sizeof(int), cudaMemcpyDeviceToHost) );
gpuErrchck( cudaDeviceSynchronize() );
end = clock();
cout<<n_ret_host[1]<<endl;
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
start = clock();
cpu_loop(N,n_ret_host);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
delete[] n_ret_host;
cudaFree((void*)n_ret_device);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <time.h>
#include <stdio.h>
#define gpuErrchck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
__global__ void gpu_loop(int n, int *n_ret_device)
{
int bsize = blockDim.x;
int tid = threadIdx.x;
int i;
for(i = tid*(n/bsize) ; i < (tid+1)*(n/bsize) ; ++i)
n_ret_device[i] = i;
}
void cpu_loop(int n, int *n_ret_host)
{
int i;
for(i=0;i<n;++i)
n_ret_host[i] = i;
}
int main()
{
int N = 10000000;
int *n_ret_host = new int[N];
int *n_ret_device = NULL;
gpuErrchck( hipMalloc((void**)&n_ret_device,N*sizeof(int)) );
clock_t start, end;
double cpu_time_used;
start = clock();
gpu_loop<<< 1,5 >>>(N,n_ret_device);
gpuErrchck( hipMemcpy((void*)n_ret_host, (void*)n_ret_device, N*sizeof(int), hipMemcpyDeviceToHost) );
gpuErrchck( hipDeviceSynchronize() );
end = clock();
cout<<n_ret_host[1]<<endl;
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
start = clock();
cpu_loop(N,n_ret_host);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
delete[] n_ret_host;
hipFree((void*)n_ret_device);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <time.h>
#include <stdio.h>
#define gpuErrchck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
__global__ void gpu_loop(int n, int *n_ret_device)
{
int bsize = blockDim.x;
int tid = threadIdx.x;
int i;
for(i = tid*(n/bsize) ; i < (tid+1)*(n/bsize) ; ++i)
n_ret_device[i] = i;
}
void cpu_loop(int n, int *n_ret_host)
{
int i;
for(i=0;i<n;++i)
n_ret_host[i] = i;
}
int main()
{
int N = 10000000;
int *n_ret_host = new int[N];
int *n_ret_device = NULL;
gpuErrchck( hipMalloc((void**)&n_ret_device,N*sizeof(int)) );
clock_t start, end;
double cpu_time_used;
start = clock();
gpu_loop<<< 1,5 >>>(N,n_ret_device);
gpuErrchck( hipMemcpy((void*)n_ret_host, (void*)n_ret_device, N*sizeof(int), hipMemcpyDeviceToHost) );
gpuErrchck( hipDeviceSynchronize() );
end = clock();
cout<<n_ret_host[1]<<endl;
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
start = clock();
cpu_loop(N,n_ret_host);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
delete[] n_ret_host;
hipFree((void*)n_ret_device);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_loopiPi
.globl _Z8gpu_loopiPi
.p2align 8
.type _Z8gpu_loopiPi,@function
_Z8gpu_loopiPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s6, s3, 31
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s5, 0, s2
s_add_i32 s3, s3, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s6
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s5, s4
s_mul_hi_u32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s5
s_mul_hi_u32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s4, s2
s_sub_i32 s3, s3, s5
s_add_i32 s5, s4, 1
s_sub_i32 s7, s3, s2
s_cmp_ge_u32 s3, s2
s_cselect_b32 s4, s5, s4
s_cselect_b32 s3, s7, s3
s_add_i32 s5, s4, 1
s_cmp_ge_u32 s3, s2
s_mov_b32 s3, exec_lo
s_cselect_b32 s2, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s6
s_sub_i32 s2, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, s2, v0
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v0, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
.LBB0_2:
global_store_b32 v[1:2], v0, off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_nc_u32_e32 v0, 1, v0
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_loopiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpu_loopiPi, .Lfunc_end0-_Z8gpu_loopiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpu_loopiPi
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8gpu_loopiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <time.h>
#include <stdio.h>
#define gpuErrchck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
__global__ void gpu_loop(int n, int *n_ret_device)
{
int bsize = blockDim.x;
int tid = threadIdx.x;
int i;
for(i = tid*(n/bsize) ; i < (tid+1)*(n/bsize) ; ++i)
n_ret_device[i] = i;
}
void cpu_loop(int n, int *n_ret_host)
{
int i;
for(i=0;i<n;++i)
n_ret_host[i] = i;
}
int main()
{
int N = 10000000;
int *n_ret_host = new int[N];
int *n_ret_device = NULL;
gpuErrchck( hipMalloc((void**)&n_ret_device,N*sizeof(int)) );
clock_t start, end;
double cpu_time_used;
start = clock();
gpu_loop<<< 1,5 >>>(N,n_ret_device);
gpuErrchck( hipMemcpy((void*)n_ret_host, (void*)n_ret_device, N*sizeof(int), hipMemcpyDeviceToHost) );
gpuErrchck( hipDeviceSynchronize() );
end = clock();
cout<<n_ret_host[1]<<endl;
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
start = clock();
cpu_loop(N,n_ret_host);
end = clock();
cpu_time_used = ((double) (end - start)) / CLOCKS_PER_SEC;
cout<<cpu_time_used<<endl;
delete[] n_ret_host;
hipFree((void*)n_ret_device);
return 0;
} | .text
.file "trial.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__gpu_loopiPi # -- Begin function _Z23__device_stub__gpu_loopiPi
.p2align 4, 0x90
.type _Z23__device_stub__gpu_loopiPi,@function
_Z23__device_stub__gpu_loopiPi: # @_Z23__device_stub__gpu_loopiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpu_loopiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_loopiPi, .Lfunc_end0-_Z23__device_stub__gpu_loopiPi
.cfi_endproc
# -- End function
.globl _Z8cpu_loopiPi # -- Begin function _Z8cpu_loopiPi
.p2align 4, 0x90
.type _Z8cpu_loopiPi,@function
_Z8cpu_loopiPi: # @_Z8cpu_loopiPi
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z8cpu_loopiPi, .Lfunc_end1-_Z8cpu_loopiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $40000000, %edi # imm = 0x2625A00
callq _Znam
movq %rax, %rbx
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
callq clock
movq %rax, %r14
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 8(%rsp), %rax
movl $10000000, 20(%rsp) # imm = 0x989680
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8gpu_loopiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 8(%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit17
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit19
callq clock
movq %rax, %r15
movl 4(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_24
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_12
# %bb.11:
movzbl 67(%r12), %ecx
jmp .LBB2_13
.LBB2_12:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
subq %r14, %r15
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_24
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%r14)
je .LBB2_16
# %bb.15:
movzbl 67(%r14), %ecx
jmp .LBB2_17
.LBB2_16:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
callq clock
movq %rax, %r14
.p2align 4, 0x90
.LBB2_18: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %r15d, (%rbx,%r15,4)
incq %r15
cmpq $10000000, %r15 # imm = 0x989680
jne .LBB2_18
# %bb.19: # %_Z8cpu_loopiPi.exit
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%r14)
je .LBB2_22
# %bb.21:
movzbl 67(%r14), %ecx
jmp .LBB2_23
.LBB2_22:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.LBB2_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $44, %r8d
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $51, %r8d
jmp .LBB2_2
.LBB2_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $52, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_loopiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8gpu_loopiPi,@object # @_Z8gpu_loopiPi
.section .rodata,"a",@progbits
.globl _Z8gpu_loopiPi
.p2align 3, 0x0
_Z8gpu_loopiPi:
.quad _Z23__device_stub__gpu_loopiPi
.size _Z8gpu_loopiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/elektronicaIITH/cuda_sessions/master/trial.hip"
.size .L.str, 104
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpu_loopiPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_loopiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_loopiPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8gpu_loopiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x0] ; /* 0x0000000000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*0050*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fcc000f8e3c3f */
/*0060*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0070*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00d0*/ IABS R4, c[0x0][0x160] ; /* 0x0000580000047a13 */
/* 0x000fc60000000000 */
/*00e0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00f0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0110*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*0120*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*0130*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a05 */
/*0140*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe40003f45270 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0170*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e360000002100 */
/*0180*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0190*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01a0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fca00078e33ff */
/*01b0*/ IMAD R5, R3, R5, RZ ; /* 0x0000000503057224 */
/* 0x001fc800078e02ff */
/*01c0*/ IMAD.IADD R0, R3, 0x1, R5 ; /* 0x0000000103007824 */
/* 0x000fca00078e0205 */
/*01d0*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06270 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ LOP3.LUT P1, R4, R3.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x040fe2000782c0ff */
/*0200*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0210*/ IADD3 R2, R3, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x000fc80007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fce0003f06070 */
/*0230*/ @!P1 BRA 0x2d0 ; /* 0x0000009000009947 */
/* 0x000fec0003800000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.WIDE R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0202 */
/*0260*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e6000c101904 */
/*0280*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0290*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f5e0ff */
/*02a0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fcc00010e0603 */
/*02c0*/ @P1 BRA 0x260 ; /* 0xffffff9000001947 */
/* 0x000fea000383ffff */
/*02d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe200078e0a05 */
/*02f0*/ BSSY B0, 0x600 ; /* 0x0000030000007945 */
/* 0x000fe20003800000 */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0310*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0320*/ IMAD.WIDE R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fca00078e0202 */
/*0330*/ IADD3 R2, P0, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f1e0ff */
/*0340*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0360*/ @!P1 BRA 0x5f0 ; /* 0x0000028000009947 */
/* 0x000fee0003800000 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0380*/ IADD3 R6, R0, -0xc, RZ ; /* 0xfffffff400067810 */
/* 0x000fc60007ffe0ff */
/*0390*/ IADD3 R25, R5.reuse, 0x1, RZ ; /* 0x0000000105197810 */
/* 0x040fe20007ffe0ff */
/*03a0*/ STG.E [R2.64+-0x8], R5 ; /* 0xfffff80502007986 */
/* 0x000fe2000c101904 */
/*03b0*/ IADD3 R7, R5.reuse, 0x2, RZ ; /* 0x0000000205077810 */
/* 0x040fe40007ffe0ff */
/*03c0*/ IADD3 R9, R5.reuse, 0x3, RZ ; /* 0x0000000305097810 */
/* 0x040fe20007ffe0ff */
/*03d0*/ STG.E [R2.64+-0x4], R25 ; /* 0xfffffc1902007986 */
/* 0x0001e2000c101904 */
/*03e0*/ IADD3 R11, R5, 0x4, RZ ; /* 0x00000004050b7810 */
/* 0x000fc40007ffe0ff */
/*03f0*/ IADD3 R13, R5.reuse, 0x5, RZ ; /* 0x00000005050d7810 */
/* 0x040fe20007ffe0ff */
/*0400*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e2000c101904 */
/*0410*/ IADD3 R15, R5.reuse, 0x6, RZ ; /* 0x00000006050f7810 */
/* 0x040fe40007ffe0ff */
/*0420*/ IADD3 R17, R5.reuse, 0x7, RZ ; /* 0x0000000705117810 */
/* 0x040fe20007ffe0ff */
/*0430*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x0005e2000c101904 */
/*0440*/ IADD3 R19, R5.reuse, 0x8, RZ ; /* 0x0000000805137810 */
/* 0x040fe40007ffe0ff */
/*0450*/ IADD3 R21, R5.reuse, 0x9, RZ ; /* 0x0000000905157810 */
/* 0x040fe20007ffe0ff */
/*0460*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x0007e2000c101904 */
/*0470*/ IADD3 R23, R5, 0xa, RZ ; /* 0x0000000a05177810 */
/* 0x000fc40007ffe0ff */
/*0480*/ IADD3 R25, R5.reuse, 0xf, RZ ; /* 0x0000000f05197810 */
/* 0x041fe20007ffe0ff */
/*0490*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0001e2000c101904 */
/*04a0*/ IADD3 R7, R5.reuse, 0xb, RZ ; /* 0x0000000b05077810 */
/* 0x042fe40007ffe0ff */
/*04b0*/ IADD3 R4, P2, R2, 0x40, RZ ; /* 0x0000004002047810 */
/* 0x000fe20007f5e0ff */
/*04c0*/ STG.E [R2.64+0x10], R15 ; /* 0x0000100f02007986 */
/* 0x0003e2000c101904 */
/*04d0*/ IADD3 R9, R5.reuse, 0xc, RZ ; /* 0x0000000c05097810 */
/* 0x044fe40007ffe0ff */
/*04e0*/ IADD3 R11, R5.reuse, 0xd, RZ ; /* 0x0000000d050b7810 */
/* 0x048fe20007ffe0ff */
/*04f0*/ STG.E [R2.64+0x14], R17 ; /* 0x0000141102007986 */
/* 0x000fe2000c101904 */
/*0500*/ IADD3 R13, R5, 0xe, RZ ; /* 0x0000000e050d7810 */
/* 0x001fc60007ffe0ff */
/*0510*/ STG.E [R2.64+0x18], R19 ; /* 0x0000181302007986 */
/* 0x000fe2000c101904 */
/*0520*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*0530*/ IMAD.X R15, RZ, RZ, R3, P2 ; /* 0x000000ffff0f7224 */
/* 0x002fe400010e0603 */
/*0540*/ STG.E [R2.64+0x1c], R21 ; /* 0x00001c1502007986 */
/* 0x000fe2000c101904 */
/*0550*/ ISETP.GE.AND P1, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x000fc60003f26270 */
/*0560*/ STG.E [R2.64+0x20], R23 ; /* 0x0000201702007986 */
/* 0x000fe8000c101904 */
/*0570*/ STG.E [R2.64+0x24], R7 ; /* 0x0000240702007986 */
/* 0x000fe8000c101904 */
/*0580*/ STG.E [R2.64+0x28], R9 ; /* 0x0000280902007986 */
/* 0x000fe8000c101904 */
/*0590*/ STG.E [R2.64+0x2c], R11 ; /* 0x00002c0b02007986 */
/* 0x000fe8000c101904 */
/*05a0*/ STG.E [R2.64+0x30], R13 ; /* 0x0000300d02007986 */
/* 0x000fe8000c101904 */
/*05b0*/ STG.E [R2.64+0x34], R25 ; /* 0x0000341902007986 */
/* 0x0001e4000c101904 */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0004 */
/*05d0*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*05e0*/ @!P1 BRA 0x390 ; /* 0xfffffda000009947 */
/* 0x000fea000383ffff */
/*05f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0600*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe200078e0a05 */
/*0610*/ BSSY B0, 0x7a0 ; /* 0x0000018000007945 */
/* 0x000fe80003800000 */
/*0620*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0630*/ @!P1 BRA 0x790 ; /* 0x0000015000009947 */
/* 0x000fea0003800000 */
/*0640*/ IADD3 R7, R5.reuse, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x040fe20007ffe0ff */
/*0650*/ STG.E [R2.64+-0x8], R5 ; /* 0xfffff80502007986 */
/* 0x000fe2000c101904 */
/*0660*/ IADD3 R4, P1, R2, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x000fe40007f3e0ff */
/*0670*/ IADD3 R9, R5.reuse, 0x2, RZ ; /* 0x0000000205097810 */
/* 0x040fe20007ffe0ff */
/*0680*/ STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702007986 */
/* 0x0001e2000c101904 */
/*0690*/ IADD3 R11, R5.reuse, 0x3, RZ ; /* 0x00000003050b7810 */
/* 0x040fe40007ffe0ff */
/*06a0*/ IADD3 R13, R5.reuse, 0x4, RZ ; /* 0x00000004050d7810 */
/* 0x040fe20007ffe0ff */
/*06b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*06c0*/ IADD3 R15, R5, 0x5, RZ ; /* 0x00000005050f7810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ IADD3 R17, R5.reuse, 0x6, RZ ; /* 0x0000000605117810 */
/* 0x040fe20007ffe0ff */
/*06e0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x000fe2000c101904 */
/*06f0*/ IADD3 R19, R5.reuse, 0x7, RZ ; /* 0x0000000705137810 */
/* 0x040fe40007ffe0ff */
/*0700*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0710*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x001fe200008e0603 */
/*0720*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x000fe2000c101904 */
/*0730*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fc60007ffe0ff */
/*0740*/ STG.E [R2.64+0xc], R15 ; /* 0x00000c0f02007986 */
/* 0x000fe8000c101904 */
/*0750*/ STG.E [R2.64+0x10], R17 ; /* 0x0000101102007986 */
/* 0x000fe8000c101904 */
/*0760*/ STG.E [R2.64+0x14], R19 ; /* 0x0000141302007986 */
/* 0x0001e4000c101904 */
/*0770*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0004 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0790*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.LT.OR P0, PT, R5, R0, P0 ; /* 0x000000000500720c */
/* 0x000fda0000701670 */
/*07b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07c0*/ IADD3 R7, R5.reuse, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x040fe20007ffe0ff */
/*07d0*/ STG.E [R2.64+-0x8], R5 ; /* 0xfffff80502007986 */
/* 0x000fe2000c101904 */
/*07e0*/ IADD3 R9, R5.reuse, 0x2, RZ ; /* 0x0000000205097810 */
/* 0x040fe40007ffe0ff */
/*07f0*/ IADD3 R11, R5, 0x3, RZ ; /* 0x00000003050b7810 */
/* 0x000fe20007ffe0ff */
/*0800*/ STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702007986 */
/* 0x000fe8000c101904 */
/*0810*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0820*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_loopiPi
.globl _Z8gpu_loopiPi
.p2align 8
.type _Z8gpu_loopiPi,@function
_Z8gpu_loopiPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s6, s3, 31
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s5, 0, s2
s_add_i32 s3, s3, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s6
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s5, s4
s_mul_hi_u32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s5
s_mul_hi_u32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s4, s2
s_sub_i32 s3, s3, s5
s_add_i32 s5, s4, 1
s_sub_i32 s7, s3, s2
s_cmp_ge_u32 s3, s2
s_cselect_b32 s4, s5, s4
s_cselect_b32 s3, s7, s3
s_add_i32 s5, s4, 1
s_cmp_ge_u32 s3, s2
s_mov_b32 s3, exec_lo
s_cselect_b32 s2, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s6
s_sub_i32 s2, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, s2, v0
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v0, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
.LBB0_2:
global_store_b32 v[1:2], v0, off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_nc_u32_e32 v0, 1, v0
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_loopiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpu_loopiPi, .Lfunc_end0-_Z8gpu_loopiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpu_loopiPi
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8gpu_loopiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00008e63_00000000-6_trial.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z8cpu_loopiPi
.type _Z8cpu_loopiPi, @function
_Z8cpu_loopiPi:
.LFB3670:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L11
movslq %edi, %rdi
movl $0, %eax
.L13:
movl %eax, (%rsi,%rax,4)
addq $1, %rax
cmpq %rdi, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE3670:
.size _Z8cpu_loopiPi, .-_Z8cpu_loopiPi
.globl _Z28__device_stub__Z8gpu_loopiPiiPi
.type _Z28__device_stub__Z8gpu_loopiPiiPi, @function
_Z28__device_stub__Z8gpu_loopiPiiPi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_loopiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z28__device_stub__Z8gpu_loopiPiiPi, .-_Z28__device_stub__Z8gpu_loopiPiiPi
.globl _Z8gpu_loopiPi
.type _Z8gpu_loopiPi, @function
_Z8gpu_loopiPi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8gpu_loopiPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8gpu_loopiPi, .-_Z8gpu_loopiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/elektronicaIITH/cuda_sessions/master/trial.cu"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $40000000, %edi
call _Znam@PLT
movq %rax, %rbx
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $42, %edx
leaq .LC1(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
call clock@PLT
movq %rax, %r13
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
movl $2, %ecx
movl $40000000, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $49, %edx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $50, %edx
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call clock@PLT
movq %rax, %rbp
movl 4(%rbx), %esi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
subq %r13, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC2(%rip), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %rbp
movq %rbx, %rsi
movl $10000000, %edi
call _Z8cpu_loopiPi
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 8(%rsp), %rsi
movl $10000000, %edi
call _Z28__device_stub__Z8gpu_loopiPiiPi
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z8gpu_loopiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_loopiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "trial.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__gpu_loopiPi # -- Begin function _Z23__device_stub__gpu_loopiPi
.p2align 4, 0x90
.type _Z23__device_stub__gpu_loopiPi,@function
_Z23__device_stub__gpu_loopiPi: # @_Z23__device_stub__gpu_loopiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpu_loopiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_loopiPi, .Lfunc_end0-_Z23__device_stub__gpu_loopiPi
.cfi_endproc
# -- End function
.globl _Z8cpu_loopiPi # -- Begin function _Z8cpu_loopiPi
.p2align 4, 0x90
.type _Z8cpu_loopiPi,@function
_Z8cpu_loopiPi: # @_Z8cpu_loopiPi
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z8cpu_loopiPi, .Lfunc_end1-_Z8cpu_loopiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $40000000, %edi # imm = 0x2625A00
callq _Znam
movq %rax, %rbx
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
callq clock
movq %rax, %r14
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 8(%rsp), %rax
movl $10000000, 20(%rsp) # imm = 0x989680
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8gpu_loopiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 8(%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit17
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit19
callq clock
movq %rax, %r15
movl 4(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_24
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_12
# %bb.11:
movzbl 67(%r12), %ecx
jmp .LBB2_13
.LBB2_12:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
subq %r14, %r15
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_24
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%r14)
je .LBB2_16
# %bb.15:
movzbl 67(%r14), %ecx
jmp .LBB2_17
.LBB2_16:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
callq clock
movq %rax, %r14
.p2align 4, 0x90
.LBB2_18: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %r15d, (%rbx,%r15,4)
incq %r15
cmpq $10000000, %r15 # imm = 0x989680
jne .LBB2_18
# %bb.19: # %_Z8cpu_loopiPi.exit
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%r14)
je .LBB2_22
# %bb.21:
movzbl 67(%r14), %ecx
jmp .LBB2_23
.LBB2_22:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.LBB2_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $44, %r8d
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $51, %r8d
jmp .LBB2_2
.LBB2_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $52, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_loopiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8gpu_loopiPi,@object # @_Z8gpu_loopiPi
.section .rodata,"a",@progbits
.globl _Z8gpu_loopiPi
.p2align 3, 0x0
_Z8gpu_loopiPi:
.quad _Z23__device_stub__gpu_loopiPi
.size _Z8gpu_loopiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/elektronicaIITH/cuda_sessions/master/trial.hip"
.size .L.str, 104
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpu_loopiPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_loopiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_loopiPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/**
* Given a input tensor x with shape (N, C, D), compute x.mean(2).mean(0)
* This function is useful in batch normalization.
* Refer to https://people.maths.ox.ac.uk/gilesm/cuda/prac4/reduction.pdf.
* But the unrolling warps seems to be not working correctly for now.
*/
const int N = 256;
const int C = 1024;
const int D = 28*28;
__global__ void reduce0(const float* in, float* out) {
__shared__ float buffer[CUDA_NUM_THREADS];
const unsigned int tid = threadIdx.x;
const unsigned int c = blockIdx.x;
// load and accumulate data to buffer
buffer[tid] = 0;
for (int i = tid; i < N * D; i += blockDim.x) {
const unsigned int n = i / D;
const unsigned int d = i % D;
const unsigned int index = n * C * D + c * D + d;
buffer[tid] += in[index];
}
__syncthreads();
// do tree reduction in buffer
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) { // <-- bad: divergent branching
buffer[tid] += buffer[tid + s];
}
__syncthreads();
}
if (tid == 0) out[c] = buffer[0] / (N * D);
} | code for sm_80
Function : _Z7reduce0PKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1c0 ; /* 0x0000018000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0011e20000004800 */
/*0060*/ ISETP.GE.AND P0, PT, R2.reuse, 0x31000, PT ; /* 0x000310000200780c */
/* 0x040fe20003f06270 */
/*0070*/ IMAD.SHL.U32 R3, R2, 0x4, RZ ; /* 0x0000000402037824 */
/* 0x000fd800078e00ff */
/*0080*/ @P0 BRA 0x1b0 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0090*/ BSSY B1, 0x1a0 ; /* 0x0000010000017945 */
/* 0x003fe20003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0002 */
/*00c0*/ IMAD.HI R4, R6, 0x5397829d, RZ ; /* 0x5397829d06047827 */
/* 0x000fca00078e02ff */
/*00d0*/ SHF.R.U32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011604 */
/*00e0*/ LEA.HI.SX32 R5, R4, R5, 0x18 ; /* 0x0000000504057211 */
/* 0x000fca00078fc2ff */
/*00f0*/ IMAD R9, R5, -0x310, R6 ; /* 0xfffffcf005097824 */
/* 0x000fc800078e0206 */
/*0100*/ IMAD R4, R0, 0x310, R9 ; /* 0x0000031000047824 */
/* 0x000fe400078e0209 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD R4, R5, 0xc4000, R4 ; /* 0x000c400005047824 */
/* 0x000fc800078e0204 */
/*0130*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0009 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R6, R6, c[0x0][0x0], RZ ; /* 0x0000000006067a10 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.AND P0, PT, R6, 0x31000, PT ; /* 0x000310000600780c */
/* 0x000fe20003f06270 */
/*0170*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x004fd80000000000 */
/*0180*/ @!P0 BRA 0xc0 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01a0*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x0001e40000004800 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe200078e00ff */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f05270 */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fda0003f26070 */
/*0200*/ @!P1 BRA 0x3e0 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.SHL.U32 R8, R6, 0x2, RZ ; /* 0x0000000206087824 */
/* 0x000fc800078e00ff */
/*0230*/ I2F.U32.RP R7, R8 ; /* 0x0000000800077306 */
/* 0x000e220000209000 */
/*0240*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a08 */
/*0250*/ ISETP.NE.U32.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fcc0003f45070 */
/*0260*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0270*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fcc0007ffe0ff */
/*0280*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*02a0*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*02b0*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*02c0*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*02e0*/ IMAD R5, R8, R5, R2 ; /* 0x0000000508057224 */
/* 0x000fca00078e0202 */
/*02f0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*0300*/ @P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105051824 */
/* 0x000fca00078e0a08 */
/*0310*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*0320*/ @P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105051824 */
/* 0x000fe200078e0a08 */
/*0330*/ @!P2 LOP3.LUT R5, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff05a212 */
/* 0x000fc800078e33ff */
/*0340*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0350*/ @!P1 IMAD R4, R6, 0x4, R3 ; /* 0x0000000406049824 */
/* 0x000fe200078e0203 */
/*0360*/ @!P1 LDS R5, [R2.X4] ; /* 0x0000000002059984 */
/* 0x000fe20000004800 */
/*0370*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fc80000000f00 */
/*0380*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*0390*/ @!P1 FADD R5, R5, R4 ; /* 0x0000000405059221 */
/* 0x001fca0000000000 */
/*03a0*/ @!P1 STS [R2.X4], R5 ; /* 0x0000000502009388 */
/* 0x0001e80000004800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fda0003f26070 */
/*03d0*/ @!P1 BRA 0x220 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*03e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03f0*/ LDS R3, [RZ] ; /* 0x00000000ff037984 */
/* 0x000e220000000800 */
/*0400*/ IMAD.MOV.U32 R5, RZ, RZ, 0x36a72f05 ; /* 0x36a72f05ff057424 */
/* 0x000fe400078e00ff */
/*0410*/ IMAD.MOV.U32 R2, RZ, RZ, 0x48440000 ; /* 0x48440000ff027424 */
/* 0x000fc800078e00ff */
/*0420*/ FFMA R2, R5, -R2, 1 ; /* 0x3f80000005027423 */
/* 0x000fc80000000802 */
/*0430*/ FFMA R2, R2, R5, 4.9824616326077375561e-06 ; /* 0x36a72f0502027423 */
/* 0x000fe20000000005 */
/*0440*/ FCHK P0, R3, 200704 ; /* 0x4844000003007902 */
/* 0x001e260000000000 */
/*0450*/ FFMA R4, R3, R2, RZ ; /* 0x0000000203047223 */
/* 0x000fc800000000ff */
/*0460*/ FFMA R5, R4, -200704, R3 ; /* 0xc844000004057823 */
/* 0x000fc80000000003 */
/*0470*/ FFMA R5, R2, R5, R4 ; /* 0x0000000502057223 */
/* 0x000fe20000000004 */
/*0480*/ @!P0 BRA 0x4b0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0490*/ MOV R2, 0x4b0 ; /* 0x000004b000027802 */
/* 0x000fe40000000f00 */
/*04a0*/ CALL.REL.NOINC 0x4f0 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*04b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*04c0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*04d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ SHF.R.U32.HI R4, RZ, 0x17, R3.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011603 */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0003 */
/*0510*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fc800078ec0ff */
/*0520*/ IADD3 R7, R4, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x000fc80007ffe0ff */
/*0530*/ ISETP.GT.U32.OR P0, PT, R7, 0xfd, !PT ; /* 0x000000fd0700780c */
/* 0x000fda0007f04470 */
/*0540*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0550*/ @!P0 BRA 0x650 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0560*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0570*/ @P0 BRA 0xa20 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*0580*/ IMAD.MOV.U32 R6, RZ, RZ, 0x48440000 ; /* 0x48440000ff067424 */
/* 0x000fca00078e00ff */
/*0590*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*05a0*/ @!P0 BRA 0xa00 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*05b0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*05c0*/ @!P0 BRA 0x9e0 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*05d0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1d200 */
/*05e0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*05f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0600*/ @P0 BRA 0x9b0 ; /* 0x000003a000000947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*0620*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe200078e00ff */
/*0630*/ @!P0 MOV R6, 0xffffffc0 ; /* 0xffffffc000068802 */
/* 0x000fe20000000f00 */
/*0640*/ @!P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003058823 */
/* 0x000fe400000000ff */
/*0650*/ UMOV UR4, 0x48440000 ; /* 0x4844000000047882 */
/* 0x000fe20000000000 */
/*0660*/ IADD3 R4, R4, -0x7f, RZ ; /* 0xffffff8104047810 */
/* 0x000fe20007ffe0ff */
/*0670*/ UIADD3 UR4, UR4, -0x8800000, URZ ; /* 0xf780000004047890 */
/* 0x000fc6000fffe03f */
/*0680*/ IADD3 R6, R6, -0x11, R4 ; /* 0xffffffef06067810 */
/* 0x000fe20007ffe004 */
/*0690*/ IMAD R5, R4, -0x800000, R5 ; /* 0xff80000004057824 */
/* 0x000fe400078e0205 */
/*06a0*/ FADD.FTZ R8, -RZ, -UR4 ; /* 0x80000004ff087e21 */
/* 0x000fc60008010100 */
/*06b0*/ MUFU.RCP R3, UR4 ; /* 0x0000000400037d08 */
/* 0x000e240008001000 */
/*06c0*/ FFMA R10, R3, R8, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000008 */
/*06d0*/ FFMA R10, R3, R10, R3 ; /* 0x0000000a030a7223 */
/* 0x000fc80000000003 */
/*06e0*/ FFMA R3, R5, R10, RZ ; /* 0x0000000a05037223 */
/* 0x000fc800000000ff */
/*06f0*/ FFMA R7, R8, R3, R5 ; /* 0x0000000308077223 */
/* 0x000fc80000000005 */
/*0700*/ FFMA R7, R10, R7, R3 ; /* 0x000000070a077223 */
/* 0x000fc80000000003 */
/*0710*/ FFMA R8, R8, R7, R5 ; /* 0x0000000708087223 */
/* 0x000fc80000000005 */
/*0720*/ FFMA R5, R10, R8, R7 ; /* 0x000000080a057223 */
/* 0x000fca0000000007 */
/*0730*/ SHF.R.U32.HI R3, RZ, 0x17, R5 ; /* 0x00000017ff037819 */
/* 0x000fc80000011605 */
/*0740*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*0750*/ IMAD.IADD R9, R3, 0x1, R6 ; /* 0x0000000103097824 */
/* 0x000fca00078e0206 */
/*0760*/ IADD3 R3, R9, -0x1, RZ ; /* 0xffffffff09037810 */
/* 0x000fc80007ffe0ff */
/*0770*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*0780*/ @!P0 BRA 0x990 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0790*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*07a0*/ @P0 BRA 0x960 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*07b0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*07c0*/ @P0 BRA 0xa30 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*07d0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*07e0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*07f0*/ @!P0 BRA 0xa30 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0800*/ FFMA.RZ R3, R10.reuse, R8.reuse, R7 ; /* 0x000000080a037223 */
/* 0x0c0fe2000000c007 */
/*0810*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0820*/ IMAD.MOV R6, RZ, RZ, -R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a09 */
/*0830*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0840*/ LOP3.LUT R4, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03047812 */
/* 0x000fe200078ec0ff */
/*0850*/ FFMA.RP R3, R10.reuse, R8.reuse, R7.reuse ; /* 0x000000080a037223 */
/* 0x1c0fe40000008007 */
/*0860*/ FFMA.RM R10, R10, R8, R7 ; /* 0x000000080a0a7223 */
/* 0x000fe20000004007 */
/*0870*/ IADD3 R7, R9, 0x20, RZ ; /* 0x0000002009077810 */
/* 0x000fe40007ffe0ff */
/*0880*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fc400078efcff */
/*0890*/ FSETP.NEU.FTZ.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720b */
/* 0x000fe40003f1d000 */
/*08a0*/ SHF.L.U32 R7, R4, R7, RZ ; /* 0x0000000704077219 */
/* 0x000fe400000006ff */
/*08b0*/ SEL R3, R6, RZ, P2 ; /* 0x000000ff06037207 */
/* 0x000fe40001000000 */
/*08c0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*08d0*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fe40000011604 */
/*08e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*08f0*/ SHF.R.U32.HI R7, RZ, 0x1, R3 ; /* 0x00000001ff077819 */
/* 0x000fe40000011603 */
/*0900*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0910*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0920*/ LOP3.LUT R4, R4, R3, RZ, 0xc0, !PT ; /* 0x0000000304047212 */
/* 0x000fca00078ec0ff */
/*0930*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0940*/ LOP3.LUT R5, R4, R5, RZ, 0xfc, !PT ; /* 0x0000000504057212 */
/* 0x000fe200078efcff */
/*0950*/ BRA 0xa30 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0960*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0970*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0980*/ BRA 0xa30 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0990*/ IMAD R5, R6, 0x800000, R5 ; /* 0x0080000006057824 */
/* 0x000fe200078e0205 */
/*09a0*/ BRA 0xa30 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*09b0*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fc800078e4805 */
/*09c0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*09d0*/ BRA 0xa30 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078e4805 */
/*09f0*/ BRA 0xa30 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a00*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0a10*/ BRA 0xa30 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a20*/ FADD.FTZ R5, R3, 200704 ; /* 0x4844000003057421 */
/* 0x000fe40000010000 */
/*0a30*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0a40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff5b002007950 */
/* 0x000fea0003c3ffff */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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