system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019eaa9_00000000-6_cumulative_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cumulative_sum.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
int main()
{
cudaDeviceProp prop;
int count;
cudaGetDeviceCount(&count);
for(int i=0;i<count;++i)
{
cudaGetDeviceProperties(&prop,i);
printf( "--- General Information for device %d ---\n", i );
printf( "Name:%s\n", prop.name );
printf( "Compute capability:%d.%d\n", prop.major, prop.minor );
printf( "Clock rate:%d\n", prop.clockRate );
printf( "Device copy overlap:" );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execution timeout :" );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "--- Memory Information for device %d ---\n", i );
printf( "Total global mem:%ld\n", prop.totalGlobalMem );
printf( "Total constant Mem:%ld\n", prop.totalConstMem );
printf( "Max mem pitch:%ld\n", prop.memPitch );
printf( "Texture Alignment:%ld\n", prop.textureAlignment );
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
int main()
{
cudaDeviceProp prop;
int count;
cudaGetDeviceCount(&count);
for(int i=0;i<count;++i)
{
cudaGetDeviceProperties(&prop,i);
printf( "--- General Information for device %d ---\n", i );
printf( "Name:%s\n", prop.name );
printf( "Compute capability:%d.%d\n", prop.major, prop.minor );
printf( "Clock rate:%d\n", prop.clockRate );
printf( "Device copy overlap:" );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execution timeout :" );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "--- Memory Information for device %d ---\n", i );
printf( "Total global mem:%ld\n", prop.totalGlobalMem );
printf( "Total constant Mem:%ld\n", prop.totalConstMem );
printf( "Max mem pitch:%ld\n", prop.memPitch );
printf( "Texture Alignment:%ld\n", prop.textureAlignment );
}
} | .file "tmpxft_000b79d8_00000000-6_device-query.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "--- General Information for device %d ---\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Name:%s\n"
.LC2:
.string "Compute capability:%d.%d\n"
.LC3:
.string "Clock rate:%d\n"
.LC4:
.string "Device copy overlap:"
.LC5:
.string "Enabled\n"
.LC6:
.string "Disabled\n"
.LC7:
.string "Kernel execution timeout :"
.section .rodata.str1.8
.align 8
.LC8:
.string "--- Memory Information for device %d ---\n"
.section .rodata.str1.1
.LC9:
.string "Total global mem:%ld\n"
.LC10:
.string "Total constant Mem:%ld\n"
.LC11:
.string "Max mem pitch:%ld\n"
.LC12:
.string "Texture Alignment:%ld\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r12
jmp .L9
.L5:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L7:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L8:
movl %ebx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L4
.L9:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
je .L5
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 408(%rsp)
je .L7
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L13
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
int main()
{
cudaDeviceProp prop;
int count;
cudaGetDeviceCount(&count);
for(int i=0;i<count;++i)
{
cudaGetDeviceProperties(&prop,i);
printf( "--- General Information for device %d ---\n", i );
printf( "Name:%s\n", prop.name );
printf( "Compute capability:%d.%d\n", prop.major, prop.minor );
printf( "Clock rate:%d\n", prop.clockRate );
printf( "Device copy overlap:" );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execution timeout :" );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "--- Memory Information for device %d ---\n", i );
printf( "Total global mem:%ld\n", prop.totalGlobalMem );
printf( "Total constant Mem:%ld\n", prop.totalConstMem );
printf( "Max mem pitch:%ld\n", prop.memPitch );
printf( "Texture Alignment:%ld\n", prop.textureAlignment );
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main()
{
hipDeviceProp_t prop;
int count;
hipGetDeviceCount(&count);
for(int i=0;i<count;++i)
{
hipGetDeviceProperties(&prop,i);
printf( "--- General Information for device %d ---\n", i );
printf( "Name:%s\n", prop.name );
printf( "Compute capability:%d.%d\n", prop.major, prop.minor );
printf( "Clock rate:%d\n", prop.clockRate );
printf( "Device copy overlap:" );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execution timeout :" );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "--- Memory Information for device %d ---\n", i );
printf( "Total global mem:%ld\n", prop.totalGlobalMem );
printf( "Total constant Mem:%ld\n", prop.totalConstMem );
printf( "Max mem pitch:%ld\n", prop.memPitch );
printf( "Texture Alignment:%ld\n", prop.textureAlignment );
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main()
{
hipDeviceProp_t prop;
int count;
hipGetDeviceCount(&count);
for(int i=0;i<count;++i)
{
hipGetDeviceProperties(&prop,i);
printf( "--- General Information for device %d ---\n", i );
printf( "Name:%s\n", prop.name );
printf( "Compute capability:%d.%d\n", prop.major, prop.minor );
printf( "Clock rate:%d\n", prop.clockRate );
printf( "Device copy overlap:" );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execution timeout :" );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "--- Memory Information for device %d ---\n", i );
printf( "Total global mem:%ld\n", prop.totalGlobalMem );
printf( "Total constant Mem:%ld\n", prop.totalConstMem );
printf( "Max mem pitch:%ld\n", prop.memPitch );
printf( "Texture Alignment:%ld\n", prop.textureAlignment );
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main()
{
hipDeviceProp_t prop;
int count;
hipGetDeviceCount(&count);
for(int i=0;i<count;++i)
{
hipGetDeviceProperties(&prop,i);
printf( "--- General Information for device %d ---\n", i );
printf( "Name:%s\n", prop.name );
printf( "Compute capability:%d.%d\n", prop.major, prop.minor );
printf( "Clock rate:%d\n", prop.clockRate );
printf( "Device copy overlap:" );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execution timeout :" );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "--- Memory Information for device %d ---\n", i );
printf( "Total global mem:%ld\n", prop.totalGlobalMem );
printf( "Total constant Mem:%ld\n", prop.totalConstMem );
printf( "Max mem pitch:%ld\n", prop.memPitch );
printf( "Texture Alignment:%ld\n", prop.textureAlignment );
}
} | .text
.file "device-query.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 16(%rsp), %rbx
movl $.Lstr.2, %r14d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl 380(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 364(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $0, 400(%rsp)
movl $.Lstr.3, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
cmpl $0, 408(%rsp)
movl $.Lstr.3, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.8, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "--- General Information for device %d ---\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Name:%s\n"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute capability:%d.%d\n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Clock rate:%d\n"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device copy overlap:"
.size .L.str.4, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Kernel execution timeout :"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "--- Memory Information for device %d ---\n"
.size .L.str.8, 42
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Total global mem:%ld\n"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Total constant Mem:%ld\n"
.size .L.str.10, 24
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Max mem pitch:%ld\n"
.size .L.str.11, 19
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Texture Alignment:%ld\n"
.size .L.str.12, 23
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.2,@object # @str.2
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
.asciz "Disabled"
.size .Lstr.2, 9
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Enabled"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b79d8_00000000-6_device-query.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "--- General Information for device %d ---\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Name:%s\n"
.LC2:
.string "Compute capability:%d.%d\n"
.LC3:
.string "Clock rate:%d\n"
.LC4:
.string "Device copy overlap:"
.LC5:
.string "Enabled\n"
.LC6:
.string "Disabled\n"
.LC7:
.string "Kernel execution timeout :"
.section .rodata.str1.8
.align 8
.LC8:
.string "--- Memory Information for device %d ---\n"
.section .rodata.str1.1
.LC9:
.string "Total global mem:%ld\n"
.LC10:
.string "Total constant Mem:%ld\n"
.LC11:
.string "Max mem pitch:%ld\n"
.LC12:
.string "Texture Alignment:%ld\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r12
jmp .L9
.L5:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L7:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L8:
movl %ebx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L4
.L9:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
je .L5
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 408(%rsp)
je .L7
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L13
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "device-query.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 16(%rsp), %rbx
movl $.Lstr.2, %r14d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl 380(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 364(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $0, 400(%rsp)
movl $.Lstr.3, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
cmpl $0, 408(%rsp)
movl $.Lstr.3, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.8, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "--- General Information for device %d ---\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Name:%s\n"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute capability:%d.%d\n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Clock rate:%d\n"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device copy overlap:"
.size .L.str.4, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Kernel execution timeout :"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "--- Memory Information for device %d ---\n"
.size .L.str.8, 42
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Total global mem:%ld\n"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Total constant Mem:%ld\n"
.size .L.str.10, 24
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Max mem pitch:%ld\n"
.size .L.str.11, 19
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Texture Alignment:%ld\n"
.size .L.str.12, 23
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.2,@object # @str.2
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
.asciz "Disabled"
.size .Lstr.2, 9
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Enabled"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "conv2d-bias-add-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DBiasAddGrad::Conv2DBiasAddGrad(Op* dz)
: Op("conv2d_bias_add_grad",
Shape({dz->shape_get()[3]}),
{dz})
{}
void Conv2DBiasAddGrad::compile()
{
auto& g = Graph::instance();
auto& cz = g.compiled(preds()[0]);
Shape out_shape({cz.out_shape[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int size[4] = {
cz.out_shape[0], cz.out_shape[1],
cz.out_shape[2], cz.out_shape[3]
};
auto out_node = rt::Node::op_mat_sum_cols(cz.out_data, out_data,
size[0] * size[1] * size[2], size[3],
{cz.out_node});
//auto out_node = rt::Node::op_conv2d_bias_add_grad(cz.out_data, size, out_data,
//{cz.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "conv2d-bias-add-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DBiasAddGrad::Conv2DBiasAddGrad(Op* dz)
: Op("conv2d_bias_add_grad",
Shape({dz->shape_get()[3]}),
{dz})
{}
void Conv2DBiasAddGrad::compile()
{
auto& g = Graph::instance();
auto& cz = g.compiled(preds()[0]);
Shape out_shape({cz.out_shape[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int size[4] = {
cz.out_shape[0], cz.out_shape[1],
cz.out_shape[2], cz.out_shape[3]
};
auto out_node = rt::Node::op_mat_sum_cols(cz.out_data, out_data,
size[0] * size[1] * size[2], size[3],
{cz.out_node});
//auto out_node = rt::Node::op_conv2d_bias_add_grad(cz.out_data, size, out_data,
//{cz.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .file "tmpxft_001379ee_00000000-6_conv2d-bias-add-grad.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4620:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4620:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops17Conv2DBiasAddGradD2Ev,"axG",@progbits,_ZN3ops17Conv2DBiasAddGradD5Ev,comdat
.align 2
.weak _ZN3ops17Conv2DBiasAddGradD2Ev
.type _ZN3ops17Conv2DBiasAddGradD2Ev, @function
_ZN3ops17Conv2DBiasAddGradD2Ev:
.LFB5662:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5662:
.size _ZN3ops17Conv2DBiasAddGradD2Ev, .-_ZN3ops17Conv2DBiasAddGradD2Ev
.weak _ZN3ops17Conv2DBiasAddGradD1Ev
.set _ZN3ops17Conv2DBiasAddGradD1Ev,_ZN3ops17Conv2DBiasAddGradD2Ev
.section .text._ZN3ops17Conv2DBiasAddGradD0Ev,"axG",@progbits,_ZN3ops17Conv2DBiasAddGradD5Ev,comdat
.align 2
.weak _ZN3ops17Conv2DBiasAddGradD0Ev
.type _ZN3ops17Conv2DBiasAddGradD0Ev, @function
_ZN3ops17Conv2DBiasAddGradD0Ev:
.LFB5664:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5664:
.size _ZN3ops17Conv2DBiasAddGradD0Ev, .-_ZN3ops17Conv2DBiasAddGradD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4643:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4947:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4947:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4959:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4959:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4993:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE4993:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5173:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L38
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L38:
ret
.cfi_endproc
.LFE5173:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt12_Vector_baseIiSaIiEED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIiSaIiEED2Ev
.type _ZNSt12_Vector_baseIiSaIiEED2Ev, @function
_ZNSt12_Vector_baseIiSaIiEED2Ev:
.LFB5207:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L44
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L44:
ret
.cfi_endproc
.LFE5207:
.size _ZNSt12_Vector_baseIiSaIiEED2Ev, .-_ZNSt12_Vector_baseIiSaIiEED2Ev
.weak _ZNSt12_Vector_baseIiSaIiEED1Ev
.set _ZNSt12_Vector_baseIiSaIiEED1Ev,_ZNSt12_Vector_baseIiSaIiEED2Ev
.text
.align 2
.globl _ZN3ops17Conv2DBiasAddGrad7compileEv
.type _ZN3ops17Conv2DBiasAddGrad7compileEv, @function
_ZN3ops17Conv2DBiasAddGrad7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r15
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB0:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %r14
leaq -80(%rbp), %rdi
movq %r15, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE0:
movq -80(%rbp), %rax
movq (%rax), %rsi
movq %r14, %rdi
.LEHB1:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE1:
movq %rax, -152(%rbp)
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L48
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L48:
movq -152(%rbp), %rax
leaq 64(%rax), %r12
movl $3, %esi
movq %r12, %rdi
.LEHB2:
call _ZNK3ops5ShapeixEm@PLT
.LEHE2:
movl %eax, %ebx
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $4, %edi
.LEHB3:
call _Znwm@PLT
.LEHE3:
movq %rax, -80(%rbp)
leaq 4(%rax), %rdx
movq %rdx, -64(%rbp)
movl %ebx, (%rax)
movq %rdx, -72(%rbp)
leaq -80(%rbp), %rsi
leaq -144(%rbp), %rdi
.LEHB4:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE4:
jmp .L89
.L80:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIiSaIiEED2Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
movq %rbx, %rdi
.LEHB5:
call _Unwind_Resume@PLT
.LEHE5:
.L89:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L52
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L52:
leaq -144(%rbp), %rdi
.LEHB6:
call _ZNK3ops5Shape5totalEv@PLT
movslq %eax, %rdi
call _Z12tensor_allocm@PLT
movq %rax, %r13
movl $0, %esi
movq %r12, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, %ebx
movl $1, %esi
movq %r12, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -156(%rbp)
movl $2, %esi
movq %r12, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -160(%rbp)
movl $3, %esi
movq %r12, %rdi
call _ZNK3ops5ShapeixEm@PLT
.LEHE6:
movl %eax, -164(%rbp)
movq -152(%rbp), %rcx
movq 56(%rcx), %r12
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB7:
call _Znwm@PLT
.LEHE7:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r12, (%rax)
movq %rdx, -72(%rbp)
movslq -164(%rbp), %rcx
movl -156(%rbp), %edx
imull %edx, %ebx
movl -160(%rbp), %edx
imull %edx, %ebx
movslq %ebx, %rdx
movq -152(%rbp), %rax
movq 88(%rax), %rdi
leaq -80(%rbp), %r8
movq %r13, %rsi
.LEHB8:
call _ZN2rt4Node15op_mat_sum_colsEPKfPfmmRKSt6vectorIPS0_SaIS5_EE@PLT
.LEHE8:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L56
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L56:
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB9:
call _Znwm@PLT
.LEHE9:
jmp .L90
.L81:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L55:
leaq -144(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L73
call __stack_chk_fail@PLT
.L90:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r13, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB10:
call _Znwm@PLT
.LEHE10:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r13
leaq -144(%rbp), %r9
movq %rbx, %r8
movq %r15, %rsi
movq %r14, %rdi
.LEHB11:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE11:
jmp .L91
.L82:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L55
call _ZdlPvm@PLT
jmp .L55
.L91:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L63
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L63:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L64
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L64:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L47
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L47:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L92
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L83:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L62:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L55
call _ZdlPvm@PLT
jmp .L55
.L75:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
.LEHB12:
call _Unwind_Resume@PLT
.L76:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L69
call __stack_chk_fail@PLT
.L69:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L78:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L55
.L79:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L62
.L77:
endbr64
movq %rax, %rbx
jmp .L55
.L73:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE12:
.L92:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB0-.LFB4617
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4617
.uleb128 .LEHE1-.LEHB1
.uleb128 .L75-.LFB4617
.uleb128 0
.uleb128 .LEHB2-.LFB4617
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4617
.uleb128 .LEHE3-.LEHB3
.uleb128 .L80-.LFB4617
.uleb128 0
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 .L76-.LFB4617
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 .L77-.LFB4617
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L81-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 .L78-.LFB4617
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L82-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 .L83-.LFB4617
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 .L79-.LFB4617
.uleb128 0
.uleb128 .LEHB12-.LFB4617
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops17Conv2DBiasAddGrad7compileEv, .-_ZN3ops17Conv2DBiasAddGrad7compileEv
.align 2
.globl _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.type _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE, @function
_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $8, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
movq %rax, 80(%rsp)
leaq 8(%rax), %rdx
movq %rdx, 96(%rsp)
movq %rbp, (%rax)
movq %rdx, 88(%rsp)
movq %rbp, %rdi
.LEHB14:
call _ZNK3ops2Op9shape_getEv@PLT
movq %rax, %rdi
movl $3, %esi
call _ZNK3ops5ShapeixEm@PLT
.LEHE14:
jmp .L121
.L115:
endbr64
movq %rax, %rbx
movq 80(%rsp), %rdi
movq 96(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L97
call _ZdlPvm@PLT
.L97:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 184(%rsp), %rax
subq %fs:40, %rax
je .L109
call __stack_chk_fail@PLT
.L121:
movl %eax, %ebp
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movl $4, %edi
.LEHB15:
call _Znwm@PLT
.LEHE15:
movq %rax, 48(%rsp)
leaq 4(%rax), %rdx
movq %rdx, 64(%rsp)
movl %ebp, (%rax)
movq %rdx, 56(%rsp)
leaq 48(%rsp), %rsi
leaq 16(%rsp), %rdi
.LEHB16:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE16:
jmp .L122
.L116:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt12_Vector_baseIiSaIiEED2Ev
.L100:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L97
.L122:
leaq 144(%rsp), %rdi
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movq $20, 8(%rsp)
leaq 8(%rsp), %rsi
movl $0, %edx
.LEHB17:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE17:
movq %rax, 144(%rsp)
movq 8(%rsp), %rdx
movq %rdx, 160(%rsp)
movabsq $7088494506402541411, %rsi
movabsq $6873729300650221929, %rdi
movq %rsi, (%rax)
movq %rdi, 8(%rax)
movl $1684107879, 16(%rax)
movq %rdx, 152(%rsp)
movq 144(%rsp), %rax
movb $0, (%rax,%rdx)
leaq 80(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 144(%rsp), %rsi
leaq 112(%rsp), %r8
movq %rbx, %rdi
.LEHB18:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE18:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L101
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L101:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .L102
movq 32(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L102:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .L103
movq 64(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L103:
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .L104
movq 96(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L104:
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .L105
movq 128(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L105:
leaq 16+_ZTVN3ops17Conv2DBiasAddGradE(%rip), %rax
movq %rax, (%rbx)
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L123
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L114:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L107:
leaq 16(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L108:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
jmp .L100
.L113:
endbr64
movq %rax, %rbx
jmp .L107
.L112:
endbr64
movq %rax, %rbx
jmp .L108
.L111:
endbr64
movq %rax, %rbx
jmp .L100
.L109:
movq %rbx, %rdi
.LEHB19:
call _Unwind_Resume@PLT
.LEHE19:
.L123:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.section .gcc_except_table
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB13-.LFB4615
.uleb128 .LEHE13-.LEHB13
.uleb128 .L115-.LFB4615
.uleb128 0
.uleb128 .LEHB14-.LFB4615
.uleb128 .LEHE14-.LEHB14
.uleb128 .L111-.LFB4615
.uleb128 0
.uleb128 .LEHB15-.LFB4615
.uleb128 .LEHE15-.LEHB15
.uleb128 .L116-.LFB4615
.uleb128 0
.uleb128 .LEHB16-.LFB4615
.uleb128 .LEHE16-.LEHB16
.uleb128 .L112-.LFB4615
.uleb128 0
.uleb128 .LEHB17-.LFB4615
.uleb128 .LEHE17-.LEHB17
.uleb128 .L113-.LFB4615
.uleb128 0
.uleb128 .LEHB18-.LFB4615
.uleb128 .LEHE18-.LEHB18
.uleb128 .L114-.LFB4615
.uleb128 0
.uleb128 .LEHB19-.LFB4615
.uleb128 .LEHE19-.LEHB19
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE, .-_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.globl _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE
.set _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE,_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.weak _ZTSN3ops17Conv2DBiasAddGradE
.section .rodata._ZTSN3ops17Conv2DBiasAddGradE,"aG",@progbits,_ZTSN3ops17Conv2DBiasAddGradE,comdat
.align 16
.type _ZTSN3ops17Conv2DBiasAddGradE, @object
.size _ZTSN3ops17Conv2DBiasAddGradE, 26
_ZTSN3ops17Conv2DBiasAddGradE:
.string "N3ops17Conv2DBiasAddGradE"
.weak _ZTIN3ops17Conv2DBiasAddGradE
.section .data.rel.ro._ZTIN3ops17Conv2DBiasAddGradE,"awG",@progbits,_ZTIN3ops17Conv2DBiasAddGradE,comdat
.align 8
.type _ZTIN3ops17Conv2DBiasAddGradE, @object
.size _ZTIN3ops17Conv2DBiasAddGradE, 24
_ZTIN3ops17Conv2DBiasAddGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops17Conv2DBiasAddGradE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops17Conv2DBiasAddGradE
.section .data.rel.ro._ZTVN3ops17Conv2DBiasAddGradE,"awG",@progbits,_ZTVN3ops17Conv2DBiasAddGradE,comdat
.align 8
.type _ZTVN3ops17Conv2DBiasAddGradE, @object
.size _ZTVN3ops17Conv2DBiasAddGradE, 48
_ZTVN3ops17Conv2DBiasAddGradE:
.quad 0
.quad _ZTIN3ops17Conv2DBiasAddGradE
.quad _ZN3ops17Conv2DBiasAddGradD1Ev
.quad _ZN3ops17Conv2DBiasAddGradD0Ev
.quad _ZN3ops17Conv2DBiasAddGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "conv2d-bias-add-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DBiasAddGrad::Conv2DBiasAddGrad(Op* dz)
: Op("conv2d_bias_add_grad",
Shape({dz->shape_get()[3]}),
{dz})
{}
void Conv2DBiasAddGrad::compile()
{
auto& g = Graph::instance();
auto& cz = g.compiled(preds()[0]);
Shape out_shape({cz.out_shape[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int size[4] = {
cz.out_shape[0], cz.out_shape[1],
cz.out_shape[2], cz.out_shape[3]
};
auto out_node = rt::Node::op_mat_sum_cols(cz.out_data, out_data,
size[0] * size[1] * size[2], size[3],
{cz.out_node});
//auto out_node = rt::Node::op_conv2d_bias_add_grad(cz.out_data, size, out_data,
//{cz.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | #include <hip/hip_runtime.h>
#include "conv2d-bias-add-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DBiasAddGrad::Conv2DBiasAddGrad(Op* dz)
: Op("conv2d_bias_add_grad",
Shape({dz->shape_get()[3]}),
{dz})
{}
void Conv2DBiasAddGrad::compile()
{
auto& g = Graph::instance();
auto& cz = g.compiled(preds()[0]);
Shape out_shape({cz.out_shape[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int size[4] = {
cz.out_shape[0], cz.out_shape[1],
cz.out_shape[2], cz.out_shape[3]
};
auto out_node = rt::Node::op_mat_sum_cols(cz.out_data, out_data,
size[0] * size[1] * size[2], size[3],
{cz.out_node});
//auto out_node = rt::Node::op_conv2d_bias_add_grad(cz.out_data, size, out_data,
//{cz.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "conv2d-bias-add-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DBiasAddGrad::Conv2DBiasAddGrad(Op* dz)
: Op("conv2d_bias_add_grad",
Shape({dz->shape_get()[3]}),
{dz})
{}
void Conv2DBiasAddGrad::compile()
{
auto& g = Graph::instance();
auto& cz = g.compiled(preds()[0]);
Shape out_shape({cz.out_shape[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int size[4] = {
cz.out_shape[0], cz.out_shape[1],
cz.out_shape[2], cz.out_shape[3]
};
auto out_node = rt::Node::op_mat_sum_cols(cz.out_data, out_data,
size[0] * size[1] * size[2], size[3],
{cz.out_node});
//auto out_node = rt::Node::op_conv2d_bias_add_grad(cz.out_data, size, out_data,
//{cz.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "conv2d-bias-add-grad.hh"
#include "graph.hh"
#include "../runtime/graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
Conv2DBiasAddGrad::Conv2DBiasAddGrad(Op* dz)
: Op("conv2d_bias_add_grad",
Shape({dz->shape_get()[3]}),
{dz})
{}
void Conv2DBiasAddGrad::compile()
{
auto& g = Graph::instance();
auto& cz = g.compiled(preds()[0]);
Shape out_shape({cz.out_shape[3]});
dbl_t* out_data = tensor_alloc(out_shape.total());
int size[4] = {
cz.out_shape[0], cz.out_shape[1],
cz.out_shape[2], cz.out_shape[3]
};
auto out_node = rt::Node::op_mat_sum_cols(cz.out_data, out_data,
size[0] * size[1] * size[2], size[3],
{cz.out_node});
//auto out_node = rt::Node::op_conv2d_bias_add_grad(cz.out_data, size, out_data,
//{cz.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .text
.file "conv2d-bias-add-grad.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.p2align 4, 0x90
.type _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE,@function
_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE: # @_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %rbx
leaq 80(%rsp), %r15
movq %r15, 64(%rsp)
movl $21, %edi
callq _Znwm
movq %rax, 64(%rsp)
movq $20, 80(%rsp)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movl $1684107879, 16(%rax) # imm = 0x64617267
movq $20, 72(%rsp)
movb $0, 20(%rax)
.Ltmp0:
movq %r14, %rdi
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
.Ltmp2:
movl $3, %esi
movq %rax, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp3:
# %bb.2:
movl %eax, %ebp
xorps %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
.Ltmp5:
movl $4, %edi
callq _Znwm
.Ltmp6:
# %bb.3: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit
movq %rax, 32(%rsp)
movq %rax, %rcx
addq $4, %rcx
movq %rcx, 48(%rsp)
movl %ebp, (%rax)
movq %rcx, 40(%rsp)
.Ltmp8:
leaq 128(%rsp), %rdi
leaq 32(%rsp), %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp9:
# %bb.4:
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp11:
movl $8, %edi
callq _Znwm
.Ltmp12:
# %bb.5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 16(%rsp)
movq %r14, (%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 96(%rsp)
movq $0, 112(%rsp)
.Ltmp14:
leaq 64(%rsp), %rsi
leaq 128(%rsp), %rdx
movq %rsp, %rcx
leaq 96(%rsp), %r8
movq %rbx, %rdi
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp15:
# %bb.6:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_8
# %bb.7:
callq _ZdlPv
.LBB0_8: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_10
# %bb.9:
callq _ZdlPv
.LBB0_10: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit24
movq 128(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_12
# %bb.11:
callq _ZdlPv
.LBB0_12: # %_ZN3ops5ShapeD2Ev.exit
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
.LBB0_14: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq 64(%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_16
# %bb.15: # %.critedge.i.i
callq _ZdlPv
.LBB0_16: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops17Conv2DBiasAddGradE+16, (%rbx)
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_17:
.cfi_def_cfa_offset 192
.Ltmp16:
movq %rax, %rbx
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_20
# %bb.18:
callq _ZdlPv
jmp .LBB0_20
.LBB0_19:
.Ltmp13:
movq %rax, %rbx
.LBB0_20: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit29
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_22
# %bb.21: # %.body19.sink.split
callq _ZdlPv
.LBB0_22: # %.body19
movq 128(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_27
# %bb.23:
callq _ZdlPv
jmp .LBB0_27
.LBB0_24:
.Ltmp10:
jmp .LBB0_26
.LBB0_25:
.Ltmp7:
.LBB0_26: # %_ZN3ops5ShapeD2Ev.exit34
movq %rax, %rbx
.LBB0_27: # %_ZN3ops5ShapeD2Ev.exit34
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_30
# %bb.28:
callq _ZdlPv
jmp .LBB0_30
.LBB0_29:
.Ltmp4:
movq %rax, %rbx
.LBB0_30: # %.body
movq 64(%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_32
# %bb.31: # %.critedge.i.i38
callq _ZdlPv
.LBB0_32: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit40
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE, .Lfunc_end0-_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end0-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops17Conv2DBiasAddGrad7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops17Conv2DBiasAddGrad7compileEv
.p2align 4, 0x90
.type _ZN3ops17Conv2DBiasAddGrad7compileEv,@function
_ZN3ops17Conv2DBiasAddGrad7compileEv: # @_ZN3ops17Conv2DBiasAddGrad7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq _ZN3ops5Graph8instanceEv
movq %rax, %r14
leaq 112(%rsp), %rdi
movq %rbx, 144(%rsp) # 8-byte Spill
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
movq 112(%rsp), %rax
movq (%rax), %rsi
.Ltmp17:
movq %r14, 136(%rsp) # 8-byte Spill
movq %r14, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp18:
# %bb.1:
movq %rax, %r12
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
leaq 64(%r12), %r13
movl $3, %esi
movq %r13, %rdi
callq _ZNK3ops5ShapeixEm
movl %eax, %ebx
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp20:
movl $4, %edi
callq _Znwm
.Ltmp21:
# %bb.4: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit
movq %rax, 16(%rsp)
movq %rax, %rcx
addq $4, %rcx
movq %rcx, 32(%rsp)
movl %ebx, (%rax)
movq %rcx, 24(%rsp)
.Ltmp23:
leaq 112(%rsp), %rdi
leaq 16(%rsp), %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp24:
# %bb.5:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_7
# %bb.6:
callq _ZdlPv
.LBB1_7: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.Ltmp26:
leaq 112(%rsp), %rdi
callq _ZNK3ops5Shape5totalEv
.Ltmp27:
# %bb.8:
movslq %eax, %rdi
.Ltmp28:
callq _Z12tensor_allocm
.Ltmp29:
# %bb.9:
.Ltmp31:
movq %rax, %r15
movq %r13, %rdi
xorl %esi, %esi
callq _ZNK3ops5ShapeixEm
movl %eax, 44(%rsp) # 4-byte Spill
.Ltmp32:
# %bb.10:
.Ltmp33:
movl $1, %esi
movq %r13, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp34:
# %bb.11:
.Ltmp35:
movl %eax, %ebx
movl $2, %esi
movq %r13, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp36:
# %bb.12:
.Ltmp37:
movl %eax, %r14d
movl $3, %esi
movq %r13, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp38:
# %bb.13:
movl %eax, %ebp
movq 88(%r12), %r13
movq 56(%r12), %r12
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp40:
movl $8, %edi
callq _Znwm
.Ltmp41:
# %bb.14: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, 16(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 32(%rsp)
movq %r12, (%rax)
movq %rcx, 24(%rsp)
movslq %ebp, %rcx
imull 44(%rsp), %ebx # 4-byte Folded Reload
imull %r14d, %ebx
movslq %ebx, %rdx
.Ltmp43:
leaq 16(%rsp), %r8
movq %r13, %rdi
movq %r15, %rsi
callq _ZN2rt4Node15op_mat_sum_colsEPKfPfmmRKSt6vectorIPS0_SaIS5_EE
.Ltmp44:
# %bb.15:
movq %rax, %r12
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_17
# %bb.16:
callq _ZdlPv
.LBB1_17: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movq $0, 96(%rsp)
.Ltmp46:
movl $8, %edi
callq _Znwm
.Ltmp47:
# %bb.18: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit54
movq %rax, 80(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 96(%rsp)
movq %r12, (%rax)
movq %rcx, 88(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp49:
movl $8, %edi
callq _Znwm
.Ltmp50:
# %bb.19: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 48(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 64(%rsp)
movq %r15, (%rax)
movq %rcx, 56(%rsp)
.Ltmp52:
movq %r15, (%rsp)
leaq 80(%rsp), %rdx
leaq 48(%rsp), %rcx
leaq 112(%rsp), %r9
movq 136(%rsp), %rdi # 8-byte Reload
movq 144(%rsp), %rsi # 8-byte Reload
movq %r12, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp53:
# %bb.20:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_22
# %bb.21:
callq _ZdlPv
.LBB1_22: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_24
# %bb.23:
callq _ZdlPv
.LBB1_24: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit62
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_26
# %bb.25:
callq _ZdlPv
.LBB1_26: # %_ZN3ops5ShapeD2Ev.exit
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 208
.Ltmp54:
jmp .LBB1_29
.LBB1_28:
.Ltmp51:
.LBB1_29:
movq %rax, %rbx
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_32
# %bb.30: # %.body56.sink.split
callq _ZdlPv
jmp .LBB1_32
.LBB1_31:
.Ltmp48:
movq %rax, %rbx
.LBB1_32: # %.body56
movq 80(%rsp), %rdi
jmp .LBB1_36
.LBB1_33:
.Ltmp45:
jmp .LBB1_35
.LBB1_34:
.Ltmp42:
.LBB1_35:
movq %rax, %rbx
movq 16(%rsp), %rdi
.LBB1_36: # %.body56
testq %rdi, %rdi
je .LBB1_45
# %bb.37:
callq _ZdlPv
jmp .LBB1_45
.LBB1_38:
.Ltmp25:
jmp .LBB1_40
.LBB1_39:
.Ltmp22:
.LBB1_40:
movq %rax, %rbx
movq 16(%rsp), %rdi
jmp .LBB1_46
.LBB1_41:
.Ltmp19:
jmp .LBB1_44
.LBB1_42:
.Ltmp30:
jmp .LBB1_44
.LBB1_43:
.Ltmp39:
.LBB1_44: # %.body52
movq %rax, %rbx
.LBB1_45: # %.body52
movq 112(%rsp), %rdi
.LBB1_46: # %.body52
testq %rdi, %rdi
je .LBB1_48
# %bb.47:
callq _ZdlPv
.LBB1_48:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops17Conv2DBiasAddGrad7compileEv, .Lfunc_end1-_ZN3ops17Conv2DBiasAddGrad7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp17-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp17
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin1 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp20-.Ltmp18 # Call between .Ltmp18 and .Ltmp20
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin1 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin1 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp29-.Ltmp26 # Call between .Ltmp26 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin1 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp38-.Ltmp31 # Call between .Ltmp31 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin1 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin1 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44
.uleb128 .Ltmp45-.Lfunc_begin1 # jumps to .Ltmp45
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp47-.Ltmp46 # Call between .Ltmp46 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin1 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp50-.Ltmp49 # Call between .Ltmp49 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin1 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53
.uleb128 .Ltmp54-.Lfunc_begin1 # jumps to .Ltmp54
.byte 0 # On action: cleanup
.uleb128 .Ltmp53-.Lfunc_begin1 # >> Call Site 13 <<
.uleb128 .Lfunc_end1-.Ltmp53 # Call between .Ltmp53 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops17Conv2DBiasAddGradD0Ev,"axG",@progbits,_ZN3ops17Conv2DBiasAddGradD0Ev,comdat
.weak _ZN3ops17Conv2DBiasAddGradD0Ev # -- Begin function _ZN3ops17Conv2DBiasAddGradD0Ev
.p2align 4, 0x90
.type _ZN3ops17Conv2DBiasAddGradD0Ev,@function
_ZN3ops17Conv2DBiasAddGradD0Ev: # @_ZN3ops17Conv2DBiasAddGradD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops17Conv2DBiasAddGradD0Ev, .Lfunc_end3-_ZN3ops17Conv2DBiasAddGradD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "conv2d_bias_add_grad"
.size .L.str, 21
.type _ZTVN3ops17Conv2DBiasAddGradE,@object # @_ZTVN3ops17Conv2DBiasAddGradE
.section .rodata,"a",@progbits
.globl _ZTVN3ops17Conv2DBiasAddGradE
.p2align 3, 0x0
_ZTVN3ops17Conv2DBiasAddGradE:
.quad 0
.quad _ZTIN3ops17Conv2DBiasAddGradE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops17Conv2DBiasAddGradD0Ev
.quad _ZN3ops17Conv2DBiasAddGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops17Conv2DBiasAddGradE, 48
.type _ZTSN3ops17Conv2DBiasAddGradE,@object # @_ZTSN3ops17Conv2DBiasAddGradE
.globl _ZTSN3ops17Conv2DBiasAddGradE
_ZTSN3ops17Conv2DBiasAddGradE:
.asciz "N3ops17Conv2DBiasAddGradE"
.size _ZTSN3ops17Conv2DBiasAddGradE, 26
.type _ZTIN3ops17Conv2DBiasAddGradE,@object # @_ZTIN3ops17Conv2DBiasAddGradE
.globl _ZTIN3ops17Conv2DBiasAddGradE
.p2align 3, 0x0
_ZTIN3ops17Conv2DBiasAddGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops17Conv2DBiasAddGradE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops17Conv2DBiasAddGradE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE
.type _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE,@function
.set _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE, _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops17Conv2DBiasAddGradE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops17Conv2DBiasAddGradE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001379ee_00000000-6_conv2d-bias-add-grad.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4620:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4620:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops17Conv2DBiasAddGradD2Ev,"axG",@progbits,_ZN3ops17Conv2DBiasAddGradD5Ev,comdat
.align 2
.weak _ZN3ops17Conv2DBiasAddGradD2Ev
.type _ZN3ops17Conv2DBiasAddGradD2Ev, @function
_ZN3ops17Conv2DBiasAddGradD2Ev:
.LFB5662:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5662:
.size _ZN3ops17Conv2DBiasAddGradD2Ev, .-_ZN3ops17Conv2DBiasAddGradD2Ev
.weak _ZN3ops17Conv2DBiasAddGradD1Ev
.set _ZN3ops17Conv2DBiasAddGradD1Ev,_ZN3ops17Conv2DBiasAddGradD2Ev
.section .text._ZN3ops17Conv2DBiasAddGradD0Ev,"axG",@progbits,_ZN3ops17Conv2DBiasAddGradD5Ev,comdat
.align 2
.weak _ZN3ops17Conv2DBiasAddGradD0Ev
.type _ZN3ops17Conv2DBiasAddGradD0Ev, @function
_ZN3ops17Conv2DBiasAddGradD0Ev:
.LFB5664:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5664:
.size _ZN3ops17Conv2DBiasAddGradD0Ev, .-_ZN3ops17Conv2DBiasAddGradD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4643:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4947:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4947:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4959:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4959:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4993:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE4993:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5173:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L38
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L38:
ret
.cfi_endproc
.LFE5173:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt12_Vector_baseIiSaIiEED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIiSaIiEED2Ev
.type _ZNSt12_Vector_baseIiSaIiEED2Ev, @function
_ZNSt12_Vector_baseIiSaIiEED2Ev:
.LFB5207:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L44
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L44:
ret
.cfi_endproc
.LFE5207:
.size _ZNSt12_Vector_baseIiSaIiEED2Ev, .-_ZNSt12_Vector_baseIiSaIiEED2Ev
.weak _ZNSt12_Vector_baseIiSaIiEED1Ev
.set _ZNSt12_Vector_baseIiSaIiEED1Ev,_ZNSt12_Vector_baseIiSaIiEED2Ev
.text
.align 2
.globl _ZN3ops17Conv2DBiasAddGrad7compileEv
.type _ZN3ops17Conv2DBiasAddGrad7compileEv, @function
_ZN3ops17Conv2DBiasAddGrad7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r15
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB0:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %r14
leaq -80(%rbp), %rdi
movq %r15, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE0:
movq -80(%rbp), %rax
movq (%rax), %rsi
movq %r14, %rdi
.LEHB1:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE1:
movq %rax, -152(%rbp)
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L48
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L48:
movq -152(%rbp), %rax
leaq 64(%rax), %r12
movl $3, %esi
movq %r12, %rdi
.LEHB2:
call _ZNK3ops5ShapeixEm@PLT
.LEHE2:
movl %eax, %ebx
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $4, %edi
.LEHB3:
call _Znwm@PLT
.LEHE3:
movq %rax, -80(%rbp)
leaq 4(%rax), %rdx
movq %rdx, -64(%rbp)
movl %ebx, (%rax)
movq %rdx, -72(%rbp)
leaq -80(%rbp), %rsi
leaq -144(%rbp), %rdi
.LEHB4:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE4:
jmp .L89
.L80:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIiSaIiEED2Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
movq %rbx, %rdi
.LEHB5:
call _Unwind_Resume@PLT
.LEHE5:
.L89:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L52
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L52:
leaq -144(%rbp), %rdi
.LEHB6:
call _ZNK3ops5Shape5totalEv@PLT
movslq %eax, %rdi
call _Z12tensor_allocm@PLT
movq %rax, %r13
movl $0, %esi
movq %r12, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, %ebx
movl $1, %esi
movq %r12, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -156(%rbp)
movl $2, %esi
movq %r12, %rdi
call _ZNK3ops5ShapeixEm@PLT
movl %eax, -160(%rbp)
movl $3, %esi
movq %r12, %rdi
call _ZNK3ops5ShapeixEm@PLT
.LEHE6:
movl %eax, -164(%rbp)
movq -152(%rbp), %rcx
movq 56(%rcx), %r12
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB7:
call _Znwm@PLT
.LEHE7:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r12, (%rax)
movq %rdx, -72(%rbp)
movslq -164(%rbp), %rcx
movl -156(%rbp), %edx
imull %edx, %ebx
movl -160(%rbp), %edx
imull %edx, %ebx
movslq %ebx, %rdx
movq -152(%rbp), %rax
movq 88(%rax), %rdi
leaq -80(%rbp), %r8
movq %r13, %rsi
.LEHB8:
call _ZN2rt4Node15op_mat_sum_colsEPKfPfmmRKSt6vectorIPS0_SaIS5_EE@PLT
.LEHE8:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L56
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L56:
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB9:
call _Znwm@PLT
.LEHE9:
jmp .L90
.L81:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L55:
leaq -144(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L73
call __stack_chk_fail@PLT
.L90:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r13, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB10:
call _Znwm@PLT
.LEHE10:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r13
leaq -144(%rbp), %r9
movq %rbx, %r8
movq %r15, %rsi
movq %r14, %rdi
.LEHB11:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE11:
jmp .L91
.L82:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L55
call _ZdlPvm@PLT
jmp .L55
.L91:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L63
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L63:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L64
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L64:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L47
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L47:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L92
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L83:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L62:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L55
call _ZdlPvm@PLT
jmp .L55
.L75:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
.LEHB12:
call _Unwind_Resume@PLT
.L76:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L69
call __stack_chk_fail@PLT
.L69:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L78:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L55
.L79:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L62
.L77:
endbr64
movq %rax, %rbx
jmp .L55
.L73:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE12:
.L92:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB0-.LFB4617
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4617
.uleb128 .LEHE1-.LEHB1
.uleb128 .L75-.LFB4617
.uleb128 0
.uleb128 .LEHB2-.LFB4617
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4617
.uleb128 .LEHE3-.LEHB3
.uleb128 .L80-.LFB4617
.uleb128 0
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 .L76-.LFB4617
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 .L77-.LFB4617
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L81-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 .L78-.LFB4617
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L82-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 .L83-.LFB4617
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 .L79-.LFB4617
.uleb128 0
.uleb128 .LEHB12-.LFB4617
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops17Conv2DBiasAddGrad7compileEv, .-_ZN3ops17Conv2DBiasAddGrad7compileEv
.align 2
.globl _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.type _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE, @function
_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $8, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
movq %rax, 80(%rsp)
leaq 8(%rax), %rdx
movq %rdx, 96(%rsp)
movq %rbp, (%rax)
movq %rdx, 88(%rsp)
movq %rbp, %rdi
.LEHB14:
call _ZNK3ops2Op9shape_getEv@PLT
movq %rax, %rdi
movl $3, %esi
call _ZNK3ops5ShapeixEm@PLT
.LEHE14:
jmp .L121
.L115:
endbr64
movq %rax, %rbx
movq 80(%rsp), %rdi
movq 96(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L97
call _ZdlPvm@PLT
.L97:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 184(%rsp), %rax
subq %fs:40, %rax
je .L109
call __stack_chk_fail@PLT
.L121:
movl %eax, %ebp
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movl $4, %edi
.LEHB15:
call _Znwm@PLT
.LEHE15:
movq %rax, 48(%rsp)
leaq 4(%rax), %rdx
movq %rdx, 64(%rsp)
movl %ebp, (%rax)
movq %rdx, 56(%rsp)
leaq 48(%rsp), %rsi
leaq 16(%rsp), %rdi
.LEHB16:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE16:
jmp .L122
.L116:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt12_Vector_baseIiSaIiEED2Ev
.L100:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L97
.L122:
leaq 144(%rsp), %rdi
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movq $20, 8(%rsp)
leaq 8(%rsp), %rsi
movl $0, %edx
.LEHB17:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE17:
movq %rax, 144(%rsp)
movq 8(%rsp), %rdx
movq %rdx, 160(%rsp)
movabsq $7088494506402541411, %rsi
movabsq $6873729300650221929, %rdi
movq %rsi, (%rax)
movq %rdi, 8(%rax)
movl $1684107879, 16(%rax)
movq %rdx, 152(%rsp)
movq 144(%rsp), %rax
movb $0, (%rax,%rdx)
leaq 80(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 144(%rsp), %rsi
leaq 112(%rsp), %r8
movq %rbx, %rdi
.LEHB18:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE18:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L101
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L101:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .L102
movq 32(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L102:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .L103
movq 64(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L103:
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .L104
movq 96(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L104:
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .L105
movq 128(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L105:
leaq 16+_ZTVN3ops17Conv2DBiasAddGradE(%rip), %rax
movq %rax, (%rbx)
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L123
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L114:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L107:
leaq 16(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L108:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
jmp .L100
.L113:
endbr64
movq %rax, %rbx
jmp .L107
.L112:
endbr64
movq %rax, %rbx
jmp .L108
.L111:
endbr64
movq %rax, %rbx
jmp .L100
.L109:
movq %rbx, %rdi
.LEHB19:
call _Unwind_Resume@PLT
.LEHE19:
.L123:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.section .gcc_except_table
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB13-.LFB4615
.uleb128 .LEHE13-.LEHB13
.uleb128 .L115-.LFB4615
.uleb128 0
.uleb128 .LEHB14-.LFB4615
.uleb128 .LEHE14-.LEHB14
.uleb128 .L111-.LFB4615
.uleb128 0
.uleb128 .LEHB15-.LFB4615
.uleb128 .LEHE15-.LEHB15
.uleb128 .L116-.LFB4615
.uleb128 0
.uleb128 .LEHB16-.LFB4615
.uleb128 .LEHE16-.LEHB16
.uleb128 .L112-.LFB4615
.uleb128 0
.uleb128 .LEHB17-.LFB4615
.uleb128 .LEHE17-.LEHB17
.uleb128 .L113-.LFB4615
.uleb128 0
.uleb128 .LEHB18-.LFB4615
.uleb128 .LEHE18-.LEHB18
.uleb128 .L114-.LFB4615
.uleb128 0
.uleb128 .LEHB19-.LFB4615
.uleb128 .LEHE19-.LEHB19
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE, .-_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.globl _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE
.set _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE,_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.weak _ZTSN3ops17Conv2DBiasAddGradE
.section .rodata._ZTSN3ops17Conv2DBiasAddGradE,"aG",@progbits,_ZTSN3ops17Conv2DBiasAddGradE,comdat
.align 16
.type _ZTSN3ops17Conv2DBiasAddGradE, @object
.size _ZTSN3ops17Conv2DBiasAddGradE, 26
_ZTSN3ops17Conv2DBiasAddGradE:
.string "N3ops17Conv2DBiasAddGradE"
.weak _ZTIN3ops17Conv2DBiasAddGradE
.section .data.rel.ro._ZTIN3ops17Conv2DBiasAddGradE,"awG",@progbits,_ZTIN3ops17Conv2DBiasAddGradE,comdat
.align 8
.type _ZTIN3ops17Conv2DBiasAddGradE, @object
.size _ZTIN3ops17Conv2DBiasAddGradE, 24
_ZTIN3ops17Conv2DBiasAddGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops17Conv2DBiasAddGradE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops17Conv2DBiasAddGradE
.section .data.rel.ro._ZTVN3ops17Conv2DBiasAddGradE,"awG",@progbits,_ZTVN3ops17Conv2DBiasAddGradE,comdat
.align 8
.type _ZTVN3ops17Conv2DBiasAddGradE, @object
.size _ZTVN3ops17Conv2DBiasAddGradE, 48
_ZTVN3ops17Conv2DBiasAddGradE:
.quad 0
.quad _ZTIN3ops17Conv2DBiasAddGradE
.quad _ZN3ops17Conv2DBiasAddGradD1Ev
.quad _ZN3ops17Conv2DBiasAddGradD0Ev
.quad _ZN3ops17Conv2DBiasAddGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "conv2d-bias-add-grad.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.p2align 4, 0x90
.type _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE,@function
_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE: # @_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %rbx
leaq 80(%rsp), %r15
movq %r15, 64(%rsp)
movl $21, %edi
callq _Znwm
movq %rax, 64(%rsp)
movq $20, 80(%rsp)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movl $1684107879, 16(%rax) # imm = 0x64617267
movq $20, 72(%rsp)
movb $0, 20(%rax)
.Ltmp0:
movq %r14, %rdi
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
.Ltmp2:
movl $3, %esi
movq %rax, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp3:
# %bb.2:
movl %eax, %ebp
xorps %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
.Ltmp5:
movl $4, %edi
callq _Znwm
.Ltmp6:
# %bb.3: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit
movq %rax, 32(%rsp)
movq %rax, %rcx
addq $4, %rcx
movq %rcx, 48(%rsp)
movl %ebp, (%rax)
movq %rcx, 40(%rsp)
.Ltmp8:
leaq 128(%rsp), %rdi
leaq 32(%rsp), %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp9:
# %bb.4:
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp11:
movl $8, %edi
callq _Znwm
.Ltmp12:
# %bb.5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 16(%rsp)
movq %r14, (%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 96(%rsp)
movq $0, 112(%rsp)
.Ltmp14:
leaq 64(%rsp), %rsi
leaq 128(%rsp), %rdx
movq %rsp, %rcx
leaq 96(%rsp), %r8
movq %rbx, %rdi
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp15:
# %bb.6:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_8
# %bb.7:
callq _ZdlPv
.LBB0_8: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_10
# %bb.9:
callq _ZdlPv
.LBB0_10: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit24
movq 128(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_12
# %bb.11:
callq _ZdlPv
.LBB0_12: # %_ZN3ops5ShapeD2Ev.exit
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
.LBB0_14: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq 64(%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_16
# %bb.15: # %.critedge.i.i
callq _ZdlPv
.LBB0_16: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops17Conv2DBiasAddGradE+16, (%rbx)
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_17:
.cfi_def_cfa_offset 192
.Ltmp16:
movq %rax, %rbx
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_20
# %bb.18:
callq _ZdlPv
jmp .LBB0_20
.LBB0_19:
.Ltmp13:
movq %rax, %rbx
.LBB0_20: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit29
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_22
# %bb.21: # %.body19.sink.split
callq _ZdlPv
.LBB0_22: # %.body19
movq 128(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_27
# %bb.23:
callq _ZdlPv
jmp .LBB0_27
.LBB0_24:
.Ltmp10:
jmp .LBB0_26
.LBB0_25:
.Ltmp7:
.LBB0_26: # %_ZN3ops5ShapeD2Ev.exit34
movq %rax, %rbx
.LBB0_27: # %_ZN3ops5ShapeD2Ev.exit34
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_30
# %bb.28:
callq _ZdlPv
jmp .LBB0_30
.LBB0_29:
.Ltmp4:
movq %rax, %rbx
.LBB0_30: # %.body
movq 64(%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_32
# %bb.31: # %.critedge.i.i38
callq _ZdlPv
.LBB0_32: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit40
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE, .Lfunc_end0-_ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end0-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops17Conv2DBiasAddGrad7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops17Conv2DBiasAddGrad7compileEv
.p2align 4, 0x90
.type _ZN3ops17Conv2DBiasAddGrad7compileEv,@function
_ZN3ops17Conv2DBiasAddGrad7compileEv: # @_ZN3ops17Conv2DBiasAddGrad7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq _ZN3ops5Graph8instanceEv
movq %rax, %r14
leaq 112(%rsp), %rdi
movq %rbx, 144(%rsp) # 8-byte Spill
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
movq 112(%rsp), %rax
movq (%rax), %rsi
.Ltmp17:
movq %r14, 136(%rsp) # 8-byte Spill
movq %r14, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp18:
# %bb.1:
movq %rax, %r12
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
leaq 64(%r12), %r13
movl $3, %esi
movq %r13, %rdi
callq _ZNK3ops5ShapeixEm
movl %eax, %ebx
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp20:
movl $4, %edi
callq _Znwm
.Ltmp21:
# %bb.4: # %_ZNSt6vectorIiSaIiEEC2ESt16initializer_listIiERKS0_.exit
movq %rax, 16(%rsp)
movq %rax, %rcx
addq $4, %rcx
movq %rcx, 32(%rsp)
movl %ebx, (%rax)
movq %rcx, 24(%rsp)
.Ltmp23:
leaq 112(%rsp), %rdi
leaq 16(%rsp), %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp24:
# %bb.5:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_7
# %bb.6:
callq _ZdlPv
.LBB1_7: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.Ltmp26:
leaq 112(%rsp), %rdi
callq _ZNK3ops5Shape5totalEv
.Ltmp27:
# %bb.8:
movslq %eax, %rdi
.Ltmp28:
callq _Z12tensor_allocm
.Ltmp29:
# %bb.9:
.Ltmp31:
movq %rax, %r15
movq %r13, %rdi
xorl %esi, %esi
callq _ZNK3ops5ShapeixEm
movl %eax, 44(%rsp) # 4-byte Spill
.Ltmp32:
# %bb.10:
.Ltmp33:
movl $1, %esi
movq %r13, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp34:
# %bb.11:
.Ltmp35:
movl %eax, %ebx
movl $2, %esi
movq %r13, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp36:
# %bb.12:
.Ltmp37:
movl %eax, %r14d
movl $3, %esi
movq %r13, %rdi
callq _ZNK3ops5ShapeixEm
.Ltmp38:
# %bb.13:
movl %eax, %ebp
movq 88(%r12), %r13
movq 56(%r12), %r12
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp40:
movl $8, %edi
callq _Znwm
.Ltmp41:
# %bb.14: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, 16(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 32(%rsp)
movq %r12, (%rax)
movq %rcx, 24(%rsp)
movslq %ebp, %rcx
imull 44(%rsp), %ebx # 4-byte Folded Reload
imull %r14d, %ebx
movslq %ebx, %rdx
.Ltmp43:
leaq 16(%rsp), %r8
movq %r13, %rdi
movq %r15, %rsi
callq _ZN2rt4Node15op_mat_sum_colsEPKfPfmmRKSt6vectorIPS0_SaIS5_EE
.Ltmp44:
# %bb.15:
movq %rax, %r12
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_17
# %bb.16:
callq _ZdlPv
.LBB1_17: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movq $0, 96(%rsp)
.Ltmp46:
movl $8, %edi
callq _Znwm
.Ltmp47:
# %bb.18: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit54
movq %rax, 80(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 96(%rsp)
movq %r12, (%rax)
movq %rcx, 88(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp49:
movl $8, %edi
callq _Znwm
.Ltmp50:
# %bb.19: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 48(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 64(%rsp)
movq %r15, (%rax)
movq %rcx, 56(%rsp)
.Ltmp52:
movq %r15, (%rsp)
leaq 80(%rsp), %rdx
leaq 48(%rsp), %rcx
leaq 112(%rsp), %r9
movq 136(%rsp), %rdi # 8-byte Reload
movq 144(%rsp), %rsi # 8-byte Reload
movq %r12, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp53:
# %bb.20:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_22
# %bb.21:
callq _ZdlPv
.LBB1_22: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_24
# %bb.23:
callq _ZdlPv
.LBB1_24: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit62
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_26
# %bb.25:
callq _ZdlPv
.LBB1_26: # %_ZN3ops5ShapeD2Ev.exit
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 208
.Ltmp54:
jmp .LBB1_29
.LBB1_28:
.Ltmp51:
.LBB1_29:
movq %rax, %rbx
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_32
# %bb.30: # %.body56.sink.split
callq _ZdlPv
jmp .LBB1_32
.LBB1_31:
.Ltmp48:
movq %rax, %rbx
.LBB1_32: # %.body56
movq 80(%rsp), %rdi
jmp .LBB1_36
.LBB1_33:
.Ltmp45:
jmp .LBB1_35
.LBB1_34:
.Ltmp42:
.LBB1_35:
movq %rax, %rbx
movq 16(%rsp), %rdi
.LBB1_36: # %.body56
testq %rdi, %rdi
je .LBB1_45
# %bb.37:
callq _ZdlPv
jmp .LBB1_45
.LBB1_38:
.Ltmp25:
jmp .LBB1_40
.LBB1_39:
.Ltmp22:
.LBB1_40:
movq %rax, %rbx
movq 16(%rsp), %rdi
jmp .LBB1_46
.LBB1_41:
.Ltmp19:
jmp .LBB1_44
.LBB1_42:
.Ltmp30:
jmp .LBB1_44
.LBB1_43:
.Ltmp39:
.LBB1_44: # %.body52
movq %rax, %rbx
.LBB1_45: # %.body52
movq 112(%rsp), %rdi
.LBB1_46: # %.body52
testq %rdi, %rdi
je .LBB1_48
# %bb.47:
callq _ZdlPv
.LBB1_48:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops17Conv2DBiasAddGrad7compileEv, .Lfunc_end1-_ZN3ops17Conv2DBiasAddGrad7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp17-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp17
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin1 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp20-.Ltmp18 # Call between .Ltmp18 and .Ltmp20
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin1 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin1 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp29-.Ltmp26 # Call between .Ltmp26 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin1 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp38-.Ltmp31 # Call between .Ltmp31 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin1 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin1 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44
.uleb128 .Ltmp45-.Lfunc_begin1 # jumps to .Ltmp45
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp47-.Ltmp46 # Call between .Ltmp46 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin1 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp50-.Ltmp49 # Call between .Ltmp49 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin1 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53
.uleb128 .Ltmp54-.Lfunc_begin1 # jumps to .Ltmp54
.byte 0 # On action: cleanup
.uleb128 .Ltmp53-.Lfunc_begin1 # >> Call Site 13 <<
.uleb128 .Lfunc_end1-.Ltmp53 # Call between .Ltmp53 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops17Conv2DBiasAddGradD0Ev,"axG",@progbits,_ZN3ops17Conv2DBiasAddGradD0Ev,comdat
.weak _ZN3ops17Conv2DBiasAddGradD0Ev # -- Begin function _ZN3ops17Conv2DBiasAddGradD0Ev
.p2align 4, 0x90
.type _ZN3ops17Conv2DBiasAddGradD0Ev,@function
_ZN3ops17Conv2DBiasAddGradD0Ev: # @_ZN3ops17Conv2DBiasAddGradD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops17Conv2DBiasAddGradD0Ev, .Lfunc_end3-_ZN3ops17Conv2DBiasAddGradD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "conv2d_bias_add_grad"
.size .L.str, 21
.type _ZTVN3ops17Conv2DBiasAddGradE,@object # @_ZTVN3ops17Conv2DBiasAddGradE
.section .rodata,"a",@progbits
.globl _ZTVN3ops17Conv2DBiasAddGradE
.p2align 3, 0x0
_ZTVN3ops17Conv2DBiasAddGradE:
.quad 0
.quad _ZTIN3ops17Conv2DBiasAddGradE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops17Conv2DBiasAddGradD0Ev
.quad _ZN3ops17Conv2DBiasAddGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops17Conv2DBiasAddGradE, 48
.type _ZTSN3ops17Conv2DBiasAddGradE,@object # @_ZTSN3ops17Conv2DBiasAddGradE
.globl _ZTSN3ops17Conv2DBiasAddGradE
_ZTSN3ops17Conv2DBiasAddGradE:
.asciz "N3ops17Conv2DBiasAddGradE"
.size _ZTSN3ops17Conv2DBiasAddGradE, 26
.type _ZTIN3ops17Conv2DBiasAddGradE,@object # @_ZTIN3ops17Conv2DBiasAddGradE
.globl _ZTIN3ops17Conv2DBiasAddGradE
.p2align 3, 0x0
_ZTIN3ops17Conv2DBiasAddGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops17Conv2DBiasAddGradE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops17Conv2DBiasAddGradE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE
.type _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE,@function
.set _ZN3ops17Conv2DBiasAddGradC1EPNS_2OpE, _ZN3ops17Conv2DBiasAddGradC2EPNS_2OpE
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops17Conv2DBiasAddGradE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops17Conv2DBiasAddGradE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ float rowcol_dot(float *matrix_a, float *matrix_b, int row, int col, int N)
{
float val = 0;
for (int k=0; k < N; k++)
{
val += matrix_a[ row*N + k ] * matrix_b[ col + k*N];
}
return(val);
}
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x*blockDim.x + threadIdx.x;
int col = blockIdx.y*blockDim.y + threadIdx.y;
output_matrix[col + row*N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
} | code for sm_80
Function : _Z15matrix_mult_kerPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ float rowcol_dot(float *matrix_a, float *matrix_b, int row, int col, int N)
{
float val = 0;
for (int k=0; k < N; k++)
{
val += matrix_a[ row*N + k ] * matrix_b[ col + k*N];
}
return(val);
}
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x*blockDim.x + threadIdx.x;
int col = blockIdx.y*blockDim.y + threadIdx.y;
output_matrix[col + row*N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
} | .file "tmpxft_00094762_00000000-6_matrix_mult_ker.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10rowcol_dotPfS_iii
.type _Z10rowcol_dotPfS_iii, @function
_Z10rowcol_dotPfS_iii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10rowcol_dotPfS_iii, .-_Z10rowcol_dotPfS_iii
.globl _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrix_mult_kerPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
.globl _Z15matrix_mult_kerPfS_S_i
.type _Z15matrix_mult_kerPfS_S_i, @function
_Z15matrix_mult_kerPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15matrix_mult_kerPfS_S_i, .-_Z15matrix_mult_kerPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrix_mult_kerPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrix_mult_kerPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ float rowcol_dot(float *matrix_a, float *matrix_b, int row, int col, int N)
{
float val = 0;
for (int k=0; k < N; k++)
{
val += matrix_a[ row*N + k ] * matrix_b[ col + k*N];
}
return(val);
}
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x*blockDim.x + threadIdx.x;
int col = blockIdx.y*blockDim.y + threadIdx.y;
output_matrix[col + row*N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float rowcol_dot(float *matrix_a, float *matrix_b, int row, int col, int N)
{
float val = 0;
for (int k=0; k < N; k++)
{
val += matrix_a[ row*N + k ] * matrix_b[ col + k*N];
}
return(val);
}
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x*blockDim.x + threadIdx.x;
int col = blockIdx.y*blockDim.y + threadIdx.y;
output_matrix[col + row*N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float rowcol_dot(float *matrix_a, float *matrix_b, int row, int col, int N)
{
float val = 0;
for (int k=0; k < N; k++)
{
val += matrix_a[ row*N + k ] * matrix_b[ col + k*N];
}
return(val);
}
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x*blockDim.x + threadIdx.x;
int col = blockIdx.y*blockDim.y + threadIdx.y;
output_matrix[col + row*N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrix_mult_kerPfS_S_i
.globl _Z15matrix_mult_kerPfS_S_i
.p2align 8
.type _Z15matrix_mult_kerPfS_S_i,@function
_Z15matrix_mult_kerPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrix_mult_kerPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrix_mult_kerPfS_S_i, .Lfunc_end0-_Z15matrix_mult_kerPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrix_mult_kerPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrix_mult_kerPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float rowcol_dot(float *matrix_a, float *matrix_b, int row, int col, int N)
{
float val = 0;
for (int k=0; k < N; k++)
{
val += matrix_a[ row*N + k ] * matrix_b[ col + k*N];
}
return(val);
}
__global__ void matrix_mult_ker(float * matrix_a, float * matrix_b, float * output_matrix, int N)
{
int row = blockIdx.x*blockDim.x + threadIdx.x;
int col = blockIdx.y*blockDim.y + threadIdx.y;
output_matrix[col + row*N] = rowcol_dot(matrix_a, matrix_b, row, col, N);
} | .text
.file "matrix_mult_ker.hip"
.globl _Z30__device_stub__matrix_mult_kerPfS_S_i # -- Begin function _Z30__device_stub__matrix_mult_kerPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrix_mult_kerPfS_S_i,@function
_Z30__device_stub__matrix_mult_kerPfS_S_i: # @_Z30__device_stub__matrix_mult_kerPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrix_mult_kerPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrix_mult_kerPfS_S_i, .Lfunc_end0-_Z30__device_stub__matrix_mult_kerPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrix_mult_kerPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrix_mult_kerPfS_S_i,@object # @_Z15matrix_mult_kerPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrix_mult_kerPfS_S_i
.p2align 3, 0x0
_Z15matrix_mult_kerPfS_S_i:
.quad _Z30__device_stub__matrix_mult_kerPfS_S_i
.size _Z15matrix_mult_kerPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrix_mult_kerPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrix_mult_kerPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrix_mult_kerPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15matrix_mult_kerPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbf0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xad0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fcc00078e0219 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0250*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0270*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0290*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*02a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02b0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02f0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*0300*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0310*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0320*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0340*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0350*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0370*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0380*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03a0*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03b0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03e0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03f0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0410*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0420*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0430*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0460*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0470*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04b0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0500*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0510*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0520*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0540*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0550*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0560*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0580*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05b0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05e0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0630*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0640*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0650*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0660*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06b0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06f0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0700*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0710*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0730*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08a0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08b0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08c0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*08d0*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08e0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08f0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0900*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0910*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0960*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0990*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*09a0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09d0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a80*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a90*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0aa0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ab0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbf0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b00*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b30*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b40*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b50*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b60*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b70*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bd0*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0be0*/ @P0 BRA 0xb50 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrix_mult_kerPfS_S_i
.globl _Z15matrix_mult_kerPfS_S_i
.p2align 8
.type _Z15matrix_mult_kerPfS_S_i,@function
_Z15matrix_mult_kerPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrix_mult_kerPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrix_mult_kerPfS_S_i, .Lfunc_end0-_Z15matrix_mult_kerPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrix_mult_kerPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrix_mult_kerPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00094762_00000000-6_matrix_mult_ker.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10rowcol_dotPfS_iii
.type _Z10rowcol_dotPfS_iii, @function
_Z10rowcol_dotPfS_iii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10rowcol_dotPfS_iii, .-_Z10rowcol_dotPfS_iii
.globl _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrix_mult_kerPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
.globl _Z15matrix_mult_kerPfS_S_i
.type _Z15matrix_mult_kerPfS_S_i, @function
_Z15matrix_mult_kerPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrix_mult_kerPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15matrix_mult_kerPfS_S_i, .-_Z15matrix_mult_kerPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrix_mult_kerPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrix_mult_kerPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mult_ker.hip"
.globl _Z30__device_stub__matrix_mult_kerPfS_S_i # -- Begin function _Z30__device_stub__matrix_mult_kerPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrix_mult_kerPfS_S_i,@function
_Z30__device_stub__matrix_mult_kerPfS_S_i: # @_Z30__device_stub__matrix_mult_kerPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrix_mult_kerPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__matrix_mult_kerPfS_S_i, .Lfunc_end0-_Z30__device_stub__matrix_mult_kerPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrix_mult_kerPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrix_mult_kerPfS_S_i,@object # @_Z15matrix_mult_kerPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrix_mult_kerPfS_S_i
.p2align 3, 0x0
_Z15matrix_mult_kerPfS_S_i:
.quad _Z30__device_stub__matrix_mult_kerPfS_S_i
.size _Z15matrix_mult_kerPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrix_mult_kerPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrix_mult_kerPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrix_mult_kerPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float* var_6,float* var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float* var_14,float var_15) {
if (comp > +1.5118E34f * ceilf((var_4 + var_5))) {
for (int i=0; i < var_1; ++i) {
float tmp_1 = -1.3065E-36f;
float tmp_2 = +1.2489E3f;
comp += tmp_2 - tmp_1 * -1.6165E-36f + -1.1804E-44f;
for (int i=0; i < var_2; ++i) {
var_6[i] = (var_8 * (-0.0f - sinhf(cosf(-0.0f * (var_9 * var_10 * var_11)))));
var_7[i] = -1.4603E36f;
comp = var_7[i] / var_6[i] - (+1.8357E-37f + var_12 * var_13);
comp = -1.6243E25f - -1.1032E36f / +1.0991E10f;
}
for (int i=0; i < var_3; ++i) {
var_14[i] = +1.7771E-12f;
comp = var_14[i] - sqrtf(+1.4712E35f / +1.3325E-41f + -1.2108E-37f / (var_15 - acosf(ldexpf(sinf(+1.8169E-43f), 2))));
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float* tmp_7 = initPointer( atof(argv[7]) );
float* tmp_8 = initPointer( atof(argv[8]) );
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float* tmp_15 = initPointer( atof(argv[15]) );
float tmp_16 = atof(argv[16]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_001299a2_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f
.type _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f, @function
_Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 76(%rsp)
movl %edi, 72(%rsp)
movl %esi, 68(%rsp)
movl %edx, 64(%rsp)
movss %xmm1, 60(%rsp)
movss %xmm2, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movss %xmm3, 36(%rsp)
movss %xmm4, 32(%rsp)
movss %xmm5, 28(%rsp)
movss %xmm6, 24(%rsp)
movss %xmm7, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 68(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 60(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 40(%rsp), %rax
movq %rax, 200(%rsp)
leaq 36(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 28(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 20(%rsp), %rax
movq %rax, 240(%rsp)
leaq 304(%rsp), %rax
movq %rax, 248(%rsp)
leaq 8(%rsp), %rax
movq %rax, 256(%rsp)
leaq 312(%rsp), %rax
movq %rax, 264(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 312
pushq 88(%rsp)
.cfi_def_cfa_offset 320
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z7computefiiiffPfS_ffffffS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f, .-_Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f
.globl _Z7computefiiiffPfS_ffffffS_f
.type _Z7computefiiiffPfS_ffffffS_f, @function
_Z7computefiiiffPfS_ffffffS_f:
.LFB2084:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss 40(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 32(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiiffPfS_ffffffS_f, .-_Z7computefiiiffPfS_ffffffS_f
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 80(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r15
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 88(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss 8(%rsp), %xmm1
leaq -16(%rsp), %rsp
.cfi_def_cfa_offset 208
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 32(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r15, %r9
pxor %xmm7, %xmm7
cvtsd2ss 40(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 48(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 56(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 64(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 72(%rsp), %xmm3
movq %r14, %r8
movq %r13, %rcx
pxor %xmm2, %xmm2
cvtsd2ss 80(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movl %r12d, %edx
movl %ebp, %esi
movl 96(%rsp), %edi
call _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefiiiffPfS_ffffffS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiiffPfS_ffffffS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float* var_6,float* var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float* var_14,float var_15) {
if (comp > +1.5118E34f * ceilf((var_4 + var_5))) {
for (int i=0; i < var_1; ++i) {
float tmp_1 = -1.3065E-36f;
float tmp_2 = +1.2489E3f;
comp += tmp_2 - tmp_1 * -1.6165E-36f + -1.1804E-44f;
for (int i=0; i < var_2; ++i) {
var_6[i] = (var_8 * (-0.0f - sinhf(cosf(-0.0f * (var_9 * var_10 * var_11)))));
var_7[i] = -1.4603E36f;
comp = var_7[i] / var_6[i] - (+1.8357E-37f + var_12 * var_13);
comp = -1.6243E25f - -1.1032E36f / +1.0991E10f;
}
for (int i=0; i < var_3; ++i) {
var_14[i] = +1.7771E-12f;
comp = var_14[i] - sqrtf(+1.4712E35f / +1.3325E-41f + -1.2108E-37f / (var_15 - acosf(ldexpf(sinf(+1.8169E-43f), 2))));
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float* tmp_7 = initPointer( atof(argv[7]) );
float* tmp_8 = initPointer( atof(argv[8]) );
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float* tmp_15 = initPointer( atof(argv[15]) );
float tmp_16 = atof(argv[16]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float* var_6,float* var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float* var_14,float var_15) {
if (comp > +1.5118E34f * ceilf((var_4 + var_5))) {
for (int i=0; i < var_1; ++i) {
float tmp_1 = -1.3065E-36f;
float tmp_2 = +1.2489E3f;
comp += tmp_2 - tmp_1 * -1.6165E-36f + -1.1804E-44f;
for (int i=0; i < var_2; ++i) {
var_6[i] = (var_8 * (-0.0f - sinhf(cosf(-0.0f * (var_9 * var_10 * var_11)))));
var_7[i] = -1.4603E36f;
comp = var_7[i] / var_6[i] - (+1.8357E-37f + var_12 * var_13);
comp = -1.6243E25f - -1.1032E36f / +1.0991E10f;
}
for (int i=0; i < var_3; ++i) {
var_14[i] = +1.7771E-12f;
comp = var_14[i] - sqrtf(+1.4712E35f / +1.3325E-41f + -1.2108E-37f / (var_15 - acosf(ldexpf(sinf(+1.8169E-43f), 2))));
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float* tmp_7 = initPointer( atof(argv[7]) );
float* tmp_8 = initPointer( atof(argv[8]) );
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float* tmp_15 = initPointer( atof(argv[15]) );
float tmp_16 = atof(argv[16]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float* var_6,float* var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float* var_14,float var_15) {
if (comp > +1.5118E34f * ceilf((var_4 + var_5))) {
for (int i=0; i < var_1; ++i) {
float tmp_1 = -1.3065E-36f;
float tmp_2 = +1.2489E3f;
comp += tmp_2 - tmp_1 * -1.6165E-36f + -1.1804E-44f;
for (int i=0; i < var_2; ++i) {
var_6[i] = (var_8 * (-0.0f - sinhf(cosf(-0.0f * (var_9 * var_10 * var_11)))));
var_7[i] = -1.4603E36f;
comp = var_7[i] / var_6[i] - (+1.8357E-37f + var_12 * var_13);
comp = -1.6243E25f - -1.1032E36f / +1.0991E10f;
}
for (int i=0; i < var_3; ++i) {
var_14[i] = +1.7771E-12f;
comp = var_14[i] - sqrtf(+1.4712E35f / +1.3325E-41f + -1.2108E-37f / (var_15 - acosf(ldexpf(sinf(+1.8169E-43f), 2))));
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float* tmp_7 = initPointer( atof(argv[7]) );
float* tmp_8 = initPointer( atof(argv[8]) );
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float* tmp_15 = initPointer( atof(argv[15]) );
float tmp_16 = atof(argv[16]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiiiffPfS_ffffffS_f # -- Begin function _Z22__device_stub__computefiiiffPfS_ffffffS_f
.p2align 4, 0x90
.type _Z22__device_stub__computefiiiffPfS_ffffffS_f,@function
_Z22__device_stub__computefiiiffPfS_ffffffS_f: # @_Z22__device_stub__computefiiiffPfS_ffffffS_f
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 52(%rsp)
movl %edi, 48(%rsp)
movl %esi, 44(%rsp)
movl %edx, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movq %rcx, 120(%rsp)
movq %r8, 112(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %r9, 104(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 12(%rsp), %rax
movq %rax, 224(%rsp)
leaq 272(%rsp), %rax
movq %rax, 232(%rsp)
leaq 104(%rsp), %rax
movq %rax, 240(%rsp)
leaq 280(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7computefiiiffPfS_ffffffS_f, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiiffPfS_ffffffS_f, .Lfunc_end0-_Z22__device_stub__computefiiiffPfS_ffffffS_f
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq 8(%rsi), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 136(%rsp) # 8-byte Spill
movq 24(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 128(%rsp) # 8-byte Spill
movq 32(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 40(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 48(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 56(%r12), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 64(%r12), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbp
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit36
movq 72(%r12), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 88(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 96(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 104(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 112(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 120(%r12), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $10, %r14
jne .LBB2_5
# %bb.6: # %_Z11initPointerf.exit40
movq 128(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, (%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 80(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 88(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 96(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 104(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 112(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 120(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 144(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movss %xmm9, 60(%rsp)
movq 136(%rsp), %rax # 8-byte Reload
movl %eax, 56(%rsp)
movq 128(%rsp), %rax # 8-byte Reload
movl %eax, 52(%rsp)
movl %r15d, 48(%rsp)
movss %xmm8, 44(%rsp)
movss %xmm7, 40(%rsp)
movq %r13, 216(%rsp)
movq %rbp, 208(%rsp)
movss %xmm6, 36(%rsp)
movss %xmm5, 32(%rsp)
movss %xmm4, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rbx, 200(%rsp)
movss %xmm0, 12(%rsp)
leaq 60(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 52(%rsp), %rax
movq %rax, 240(%rsp)
leaq 48(%rsp), %rax
movq %rax, 248(%rsp)
leaq 44(%rsp), %rax
movq %rax, 256(%rsp)
leaq 40(%rsp), %rax
movq %rax, 264(%rsp)
leaq 216(%rsp), %rax
movq %rax, 272(%rsp)
leaq 208(%rsp), %rax
movq %rax, 280(%rsp)
leaq 36(%rsp), %rax
movq %rax, 288(%rsp)
leaq 32(%rsp), %rax
movq %rax, 296(%rsp)
leaq 28(%rsp), %rax
movq %rax, 304(%rsp)
leaq 24(%rsp), %rax
movq %rax, 312(%rsp)
leaq 20(%rsp), %rax
movq %rax, 320(%rsp)
leaq 16(%rsp), %rax
movq %rax, 328(%rsp)
leaq 200(%rsp), %rax
movq %rax, 336(%rsp)
leaq 12(%rsp), %rax
movq %rax, 344(%rsp)
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z7computefiiiffPfS_ffffffS_f, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiiffPfS_ffffffS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiiffPfS_ffffffS_f,@object # @_Z7computefiiiffPfS_ffffffS_f
.section .rodata,"a",@progbits
.globl _Z7computefiiiffPfS_ffffffS_f
.p2align 3, 0x0
_Z7computefiiiffPfS_ffffffS_f:
.quad _Z22__device_stub__computefiiiffPfS_ffffffS_f
.size _Z7computefiiiffPfS_ffffffS_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiiffPfS_ffffffS_f"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiiffPfS_ffffffS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiiffPfS_ffffffS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001299a2_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f
.type _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f, @function
_Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 76(%rsp)
movl %edi, 72(%rsp)
movl %esi, 68(%rsp)
movl %edx, 64(%rsp)
movss %xmm1, 60(%rsp)
movss %xmm2, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movss %xmm3, 36(%rsp)
movss %xmm4, 32(%rsp)
movss %xmm5, 28(%rsp)
movss %xmm6, 24(%rsp)
movss %xmm7, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 68(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 60(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 40(%rsp), %rax
movq %rax, 200(%rsp)
leaq 36(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 28(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 20(%rsp), %rax
movq %rax, 240(%rsp)
leaq 304(%rsp), %rax
movq %rax, 248(%rsp)
leaq 8(%rsp), %rax
movq %rax, 256(%rsp)
leaq 312(%rsp), %rax
movq %rax, 264(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 312
pushq 88(%rsp)
.cfi_def_cfa_offset 320
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z7computefiiiffPfS_ffffffS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f, .-_Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f
.globl _Z7computefiiiffPfS_ffffffS_f
.type _Z7computefiiiffPfS_ffffffS_f, @function
_Z7computefiiiffPfS_ffffffS_f:
.LFB2084:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss 40(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 32(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiiffPfS_ffffffS_f, .-_Z7computefiiiffPfS_ffffffS_f
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 80(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r15
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 88(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss 8(%rsp), %xmm1
leaq -16(%rsp), %rsp
.cfi_def_cfa_offset 208
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 32(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r15, %r9
pxor %xmm7, %xmm7
cvtsd2ss 40(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 48(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 56(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 64(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 72(%rsp), %xmm3
movq %r14, %r8
movq %r13, %rcx
pxor %xmm2, %xmm2
cvtsd2ss 80(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movl %r12d, %edx
movl %ebp, %esi
movl 96(%rsp), %edi
call _Z43__device_stub__Z7computefiiiffPfS_ffffffS_ffiiiffPfS_ffffffS_f
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefiiiffPfS_ffffffS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiiffPfS_ffffffS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiiiffPfS_ffffffS_f # -- Begin function _Z22__device_stub__computefiiiffPfS_ffffffS_f
.p2align 4, 0x90
.type _Z22__device_stub__computefiiiffPfS_ffffffS_f,@function
_Z22__device_stub__computefiiiffPfS_ffffffS_f: # @_Z22__device_stub__computefiiiffPfS_ffffffS_f
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 52(%rsp)
movl %edi, 48(%rsp)
movl %esi, 44(%rsp)
movl %edx, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movq %rcx, 120(%rsp)
movq %r8, 112(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %r9, 104(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 12(%rsp), %rax
movq %rax, 224(%rsp)
leaq 272(%rsp), %rax
movq %rax, 232(%rsp)
leaq 104(%rsp), %rax
movq %rax, 240(%rsp)
leaq 280(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7computefiiiffPfS_ffffffS_f, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiiffPfS_ffffffS_f, .Lfunc_end0-_Z22__device_stub__computefiiiffPfS_ffffffS_f
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq 8(%rsi), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 136(%rsp) # 8-byte Spill
movq 24(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 128(%rsp) # 8-byte Spill
movq 32(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 40(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 48(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 56(%r12), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 64(%r12), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbp
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit36
movq 72(%r12), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 88(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 96(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 104(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 112(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 120(%r12), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $10, %r14
jne .LBB2_5
# %bb.6: # %_Z11initPointerf.exit40
movq 128(%r12), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, (%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 80(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 88(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 96(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 104(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 112(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 120(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 144(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movss %xmm9, 60(%rsp)
movq 136(%rsp), %rax # 8-byte Reload
movl %eax, 56(%rsp)
movq 128(%rsp), %rax # 8-byte Reload
movl %eax, 52(%rsp)
movl %r15d, 48(%rsp)
movss %xmm8, 44(%rsp)
movss %xmm7, 40(%rsp)
movq %r13, 216(%rsp)
movq %rbp, 208(%rsp)
movss %xmm6, 36(%rsp)
movss %xmm5, 32(%rsp)
movss %xmm4, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rbx, 200(%rsp)
movss %xmm0, 12(%rsp)
leaq 60(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 52(%rsp), %rax
movq %rax, 240(%rsp)
leaq 48(%rsp), %rax
movq %rax, 248(%rsp)
leaq 44(%rsp), %rax
movq %rax, 256(%rsp)
leaq 40(%rsp), %rax
movq %rax, 264(%rsp)
leaq 216(%rsp), %rax
movq %rax, 272(%rsp)
leaq 208(%rsp), %rax
movq %rax, 280(%rsp)
leaq 36(%rsp), %rax
movq %rax, 288(%rsp)
leaq 32(%rsp), %rax
movq %rax, 296(%rsp)
leaq 28(%rsp), %rax
movq %rax, 304(%rsp)
leaq 24(%rsp), %rax
movq %rax, 312(%rsp)
leaq 20(%rsp), %rax
movq %rax, 320(%rsp)
leaq 16(%rsp), %rax
movq %rax, 328(%rsp)
leaq 200(%rsp), %rax
movq %rax, 336(%rsp)
leaq 12(%rsp), %rax
movq %rax, 344(%rsp)
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z7computefiiiffPfS_ffffffS_f, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiiffPfS_ffffffS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiiffPfS_ffffffS_f,@object # @_Z7computefiiiffPfS_ffffffS_f
.section .rodata,"a",@progbits
.globl _Z7computefiiiffPfS_ffffffS_f
.p2align 3, 0x0
_Z7computefiiiffPfS_ffffffS_f:
.quad _Z22__device_stub__computefiiiffPfS_ffffffS_f
.size _Z7computefiiiffPfS_ffffffS_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiiffPfS_ffffffS_f"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiiffPfS_ffffffS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiiffPfS_ffffffS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void polynomial_expansion (float* poly, int degree, int n, float* array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if( index < n )
{
float out = 0.0;
float xtothepowerof = 1.0;
for ( int x = 0; x <= degree; ++x)
{
out += xtothepowerof * poly[x];
xtothepowerof *= array[index];
}
array[index] = out;
}
} | code for sm_80
Function : _Z20polynomial_expansionPfiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f03270 */
/*0070*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe400078e0208 */
/*00a0*/ @!P0 BRA 0xa30 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R9, c[0x0][0x168] ; /* 0x00005a0000097a02 */
/* 0x000fe20000000f00 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1900 */
/*00d0*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R9.reuse, 0x3, PT ; /* 0x000000030900780c */
/* 0x040fe40003f06070 */
/*00f0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0100*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0120*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fca00078ec0ff */
/*0130*/ @!P0 BRA 0x8d0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R10, -R9, c[0x0][0x168], RZ ; /* 0x00005a00090a7a10 */
/* 0x001fe20007ffe1ff */
/*0150*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0160*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fe20000000f00 */
/*0170*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0180*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fe40003f04270 */
/*0190*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fd20000000f00 */
/*01b0*/ @!P0 BRA 0x790 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x570 ; /* 0x0000037000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R26, [R4.64+0x4] ; /* 0x00000404041a7981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R24, [R4.64+0x8] ; /* 0x0000080404187981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000128000c1e1900 */
/*0250*/ LDG.E R22, [R4.64+0x10] ; /* 0x0000100404167981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R21, [R4.64+0x14] ; /* 0x0000140404157981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R20, [R4.64+0x18] ; /* 0x0000180404147981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R19, [R4.64+0x1c] ; /* 0x00001c0404137981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000128000c1e1900 */
/*02a0*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R15, [R4.64+0x2c] ; /* 0x00002c04040f7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x000128000c1e1900 */
/*02e0*/ LDG.E R13, [R4.64+0x34] ; /* 0x00003404040d7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000122000c1e1900 */
/*0300*/ FMUL R27, R0, R6 ; /* 0x00000006001b7220 */
/* 0x020fc40000400000 */
/*0310*/ FFMA R25, R25, R6, R7 ; /* 0x0000000619197223 */
/* 0x004fe40000000007 */
/*0320*/ LDG.E R7, [R4.64+0x3c] ; /* 0x00003c0404077981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*0340*/ FFMA R25, R26, R27.reuse, R25 ; /* 0x0000001b1a197223 */
/* 0x088fe20000000019 */
/*0350*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*0360*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fe20000400000 */
/*0370*/ ISETP.GT.AND P1, PT, R10, 0xb, PT ; /* 0x0000000b0a00780c */
/* 0x000fc60003f24270 */
/*0380*/ FFMA R24, R27, R24, R25 ; /* 0x000000181b187223 */
/* 0x010fe40000000019 */
/*0390*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fe20000400000 */
/*03a0*/ IADD3 R4, P2, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fc60007f5e0ff */
/*03b0*/ FFMA R23, R27, R23, R24 ; /* 0x000000171b177223 */
/* 0x000fe20000000018 */
/*03c0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*03d0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*03e0*/ FFMA R22, R27, R22, R23 ; /* 0x000000161b167223 */
/* 0x000fe40000000017 */
/*03f0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0400*/ FFMA R21, R21, R27.reuse, R22 ; /* 0x0000001b15157223 */
/* 0x080fe40000000016 */
/*0410*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0420*/ FFMA R20, R27, R20, R21 ; /* 0x000000141b147223 */
/* 0x000fe40000000015 */
/*0430*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0440*/ FFMA R19, R27, R19, R20 ; /* 0x000000131b137223 */
/* 0x000fe40000000014 */
/*0450*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0460*/ FFMA R18, R27, R18, R19 ; /* 0x000000121b127223 */
/* 0x000fe40000000013 */
/*0470*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0480*/ FFMA R17, R17, R27.reuse, R18 ; /* 0x0000001b11117223 */
/* 0x080fe40000000012 */
/*0490*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04a0*/ FFMA R16, R27, R16, R17 ; /* 0x000000101b107223 */
/* 0x000fe40000000011 */
/*04b0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04c0*/ FFMA R15, R27, R15, R16 ; /* 0x0000000f1b0f7223 */
/* 0x000fe40000000010 */
/*04d0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04e0*/ FFMA R14, R27, R14, R15 ; /* 0x0000000e1b0e7223 */
/* 0x000fe4000000000f */
/*04f0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0500*/ FFMA R13, R13, R27.reuse, R14 ; /* 0x0000001b0d0d7223 */
/* 0x080fe4000000000e */
/*0510*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0520*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x000fe4000000000d */
/*0530*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0540*/ FMUL R6, R0, R27 ; /* 0x0000001b00067220 */
/* 0x000fe40000400000 */
/*0550*/ FFMA R7, R27, R7, R12 ; /* 0x000000071b077223 */
/* 0x004fe2000000000c */
/*0560*/ @P1 BRA 0x210 ; /* 0xfffffca000001947 */
/* 0x000fea000383ffff */
/*0570*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fc80007ffe0ff */
/*0580*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*0590*/ @!P1 BRA 0x770 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*05a0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x0000a8000c1e1900 */
/*05b0*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x0000e8000c1e1900 */
/*05c0*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000128000c1e1900 */
/*05d0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000128000c1e1900 */
/*05e0*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000128000c1e1900 */
/*05f0*/ LDG.E R19, [R4.64+0x14] ; /* 0x0000140404137981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000128000c1e1900 */
/*0610*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000122000c1e1900 */
/*0620*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0630*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*0640*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*0650*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fc80007f3e0ff */
/*0660*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0670*/ FFMA R14, R6, R14, R7 ; /* 0x0000000e060e7223 */
/* 0x004fe40000000007 */
/*0680*/ FMUL R7, R0, R6 ; /* 0x0000000600077220 */
/* 0x020fc80000400000 */
/*0690*/ FFMA R14, R15, R7.reuse, R14 ; /* 0x000000070f0e7223 */
/* 0x088fe4000000000e */
/*06a0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06b0*/ FFMA R14, R7, R16, R14 ; /* 0x00000010070e7223 */
/* 0x010fe4000000000e */
/*06c0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06d0*/ FFMA R14, R7, R17, R14 ; /* 0x00000011070e7223 */
/* 0x000fe4000000000e */
/*06e0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06f0*/ FFMA R14, R7, R18, R14 ; /* 0x00000012070e7223 */
/* 0x000fe4000000000e */
/*0700*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*0710*/ FFMA R19, R19, R7.reuse, R14 ; /* 0x0000000713137223 */
/* 0x080fe4000000000e */
/*0720*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*0730*/ FFMA R12, R7, R12, R19 ; /* 0x0000000c070c7223 */
/* 0x000fe40000000013 */
/*0740*/ FMUL R15, R0, R7 ; /* 0x00000007000f7220 */
/* 0x000fc80000400000 */
/*0750*/ FFMA R7, R15, R13, R12 ; /* 0x0000000d0f077223 */
/* 0x000fe4000000000c */
/*0760*/ FMUL R6, R0, R15 ; /* 0x0000000f00067220 */
/* 0x000fe40000400000 */
/*0770*/ ISETP.NE.OR P0, PT, R10, -0x1, P0 ; /* 0xffffffff0a00780c */
/* 0x000fda0000705670 */
/*0780*/ @!P0 BRA 0x8d0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000122000c1e1900 */
/*07d0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc40007ffe0ff */
/*07e0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ ISETP.NE.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fe20003f05270 */
/*0800*/ FFMA R12, R12, R6.reuse, R7 ; /* 0x000000060c0c7223 */
/* 0x084fe40000000007 */
/*0810*/ FMUL R7, R0, R6 ; /* 0x0000000600077220 */
/* 0x020fc80000400000 */
/*0820*/ FFMA R12, R13, R7.reuse, R12 ; /* 0x000000070d0c7223 */
/* 0x088fe2000000000c */
/*0830*/ IADD3 R13, P1, R4, 0x10, RZ ; /* 0x00000010040d7810 */
/* 0x000fe20007f3e0ff */
/*0840*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc60000400000 */
/*0850*/ IADD3.X R14, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0e7210 */
/* 0x000fe20000ffe4ff */
/*0860*/ FFMA R12, R15, R7, R12 ; /* 0x000000070f0c7223 */
/* 0x010fe2000000000c */
/*0870*/ MOV R4, R13 ; /* 0x0000000d00047202 */
/* 0x001fe20000000f00 */
/*0880*/ FMUL R15, R0, R7 ; /* 0x00000007000f7220 */
/* 0x000fe20000400000 */
/*0890*/ MOV R5, R14 ; /* 0x0000000e00057202 */
/* 0x000fc60000000f00 */
/*08a0*/ FFMA R7, R17, R15.reuse, R12 ; /* 0x0000000f11077223 */
/* 0x080fe4000000000c */
/*08b0*/ FMUL R6, R0, R15 ; /* 0x0000000f00067220 */
/* 0x000fe20000400000 */
/*08c0*/ @P0 BRA 0x790 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*08d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fda0003f05270 */
/*08e0*/ @!P0 BRA 0xa40 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD.WIDE R4, R11, R8, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fca00078e0208 */
/*0900*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R10, P1, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fe40007f3e0ff */
/*0930*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0940*/ IADD3.X R12, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0c7210 */
/* 0x000fe20000ffe4ff */
/*0950*/ FFMA R7, R8, R6, R7 ; /* 0x0000000608077223 */
/* 0x004fd40000000007 */
/*0960*/ @!P0 BRA 0xa40 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0970*/ FMUL R11, R0, R6 ; /* 0x00000006000b7220 */
/* 0x020fe40000400000 */
/*0980*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0990*/ MOV R5, R12 ; /* 0x0000000c00057202 */
/* 0x000fca0000000f00 */
/*09a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*09d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*09e0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*09f0*/ FFMA R7, R4, R11.reuse, R7 ; /* 0x0000000b04077223 */
/* 0x084fe40000000007 */
/*0a00*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x000fd00000400000 */
/*0a10*/ @P0 BRA 0x980 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0a20*/ BRA 0xa40 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a30*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fca0000000f00 */
/*0a40*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void polynomial_expansion (float* poly, int degree, int n, float* array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if( index < n )
{
float out = 0.0;
float xtothepowerof = 1.0;
for ( int x = 0; x <= degree; ++x)
{
out += xtothepowerof * poly[x];
xtothepowerof *= array[index];
}
array[index] = out;
}
} | .file "tmpxft_0002b37d_00000000-6_polynomial_expansion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
.type _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_, @function
_Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20polynomial_expansionPfiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_, .-_Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
.globl _Z20polynomial_expansionPfiiS_
.type _Z20polynomial_expansionPfiiS_, @function
_Z20polynomial_expansionPfiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20polynomial_expansionPfiiS_, .-_Z20polynomial_expansionPfiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20polynomial_expansionPfiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20polynomial_expansionPfiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void polynomial_expansion (float* poly, int degree, int n, float* array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if( index < n )
{
float out = 0.0;
float xtothepowerof = 1.0;
for ( int x = 0; x <= degree; ++x)
{
out += xtothepowerof * poly[x];
xtothepowerof *= array[index];
}
array[index] = out;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void polynomial_expansion (float* poly, int degree, int n, float* array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if( index < n )
{
float out = 0.0;
float xtothepowerof = 1.0;
for ( int x = 0; x <= degree; ++x)
{
out += xtothepowerof * poly[x];
xtothepowerof *= array[index];
}
array[index] = out;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void polynomial_expansion (float* poly, int degree, int n, float* array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if( index < n )
{
float out = 0.0;
float xtothepowerof = 1.0;
for ( int x = 0; x <= degree; ++x)
{
out += xtothepowerof * poly[x];
xtothepowerof *= array[index];
}
array[index] = out;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20polynomial_expansionPfiiS_
.globl _Z20polynomial_expansionPfiiS_
.p2align 8
.type _Z20polynomial_expansionPfiiS_,@function
_Z20polynomial_expansionPfiiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 0
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_add_i32 s4, s4, 1
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_mov_b32_e32 v4, 1.0
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[0:1], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v4, v3
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20polynomial_expansionPfiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20polynomial_expansionPfiiS_, .Lfunc_end0-_Z20polynomial_expansionPfiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20polynomial_expansionPfiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20polynomial_expansionPfiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void polynomial_expansion (float* poly, int degree, int n, float* array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if( index < n )
{
float out = 0.0;
float xtothepowerof = 1.0;
for ( int x = 0; x <= degree; ++x)
{
out += xtothepowerof * poly[x];
xtothepowerof *= array[index];
}
array[index] = out;
}
} | .text
.file "polynomial_expansion.hip"
.globl _Z35__device_stub__polynomial_expansionPfiiS_ # -- Begin function _Z35__device_stub__polynomial_expansionPfiiS_
.p2align 4, 0x90
.type _Z35__device_stub__polynomial_expansionPfiiS_,@function
_Z35__device_stub__polynomial_expansionPfiiS_: # @_Z35__device_stub__polynomial_expansionPfiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20polynomial_expansionPfiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__polynomial_expansionPfiiS_, .Lfunc_end0-_Z35__device_stub__polynomial_expansionPfiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20polynomial_expansionPfiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20polynomial_expansionPfiiS_,@object # @_Z20polynomial_expansionPfiiS_
.section .rodata,"a",@progbits
.globl _Z20polynomial_expansionPfiiS_
.p2align 3, 0x0
_Z20polynomial_expansionPfiiS_:
.quad _Z35__device_stub__polynomial_expansionPfiiS_
.size _Z20polynomial_expansionPfiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20polynomial_expansionPfiiS_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__polynomial_expansionPfiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20polynomial_expansionPfiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20polynomial_expansionPfiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f03270 */
/*0070*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0090*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe400078e0208 */
/*00a0*/ @!P0 BRA 0xa30 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R9, c[0x0][0x168] ; /* 0x00005a0000097a02 */
/* 0x000fe20000000f00 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1900 */
/*00d0*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R9.reuse, 0x3, PT ; /* 0x000000030900780c */
/* 0x040fe40003f06070 */
/*00f0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0100*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0120*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fca00078ec0ff */
/*0130*/ @!P0 BRA 0x8d0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R10, -R9, c[0x0][0x168], RZ ; /* 0x00005a00090a7a10 */
/* 0x001fe20007ffe1ff */
/*0150*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0160*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fe20000000f00 */
/*0170*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0180*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fe40003f04270 */
/*0190*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fd20000000f00 */
/*01b0*/ @!P0 BRA 0x790 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fda0003f24270 */
/*01f0*/ @!P1 BRA 0x570 ; /* 0x0000037000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R26, [R4.64+0x4] ; /* 0x00000404041a7981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R24, [R4.64+0x8] ; /* 0x0000080404187981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000128000c1e1900 */
/*0250*/ LDG.E R22, [R4.64+0x10] ; /* 0x0000100404167981 */
/* 0x000128000c1e1900 */
/*0260*/ LDG.E R21, [R4.64+0x14] ; /* 0x0000140404157981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R20, [R4.64+0x18] ; /* 0x0000180404147981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R19, [R4.64+0x1c] ; /* 0x00001c0404137981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000128000c1e1900 */
/*02a0*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R15, [R4.64+0x2c] ; /* 0x00002c04040f7981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R14, [R4.64+0x30] ; /* 0x00003004040e7981 */
/* 0x000128000c1e1900 */
/*02e0*/ LDG.E R13, [R4.64+0x34] ; /* 0x00003404040d7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x000122000c1e1900 */
/*0300*/ FMUL R27, R0, R6 ; /* 0x00000006001b7220 */
/* 0x020fc40000400000 */
/*0310*/ FFMA R25, R25, R6, R7 ; /* 0x0000000619197223 */
/* 0x004fe40000000007 */
/*0320*/ LDG.E R7, [R4.64+0x3c] ; /* 0x00003c0404077981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*0340*/ FFMA R25, R26, R27.reuse, R25 ; /* 0x0000001b1a197223 */
/* 0x088fe20000000019 */
/*0350*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*0360*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fe20000400000 */
/*0370*/ ISETP.GT.AND P1, PT, R10, 0xb, PT ; /* 0x0000000b0a00780c */
/* 0x000fc60003f24270 */
/*0380*/ FFMA R24, R27, R24, R25 ; /* 0x000000181b187223 */
/* 0x010fe40000000019 */
/*0390*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fe20000400000 */
/*03a0*/ IADD3 R4, P2, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fc60007f5e0ff */
/*03b0*/ FFMA R23, R27, R23, R24 ; /* 0x000000171b177223 */
/* 0x000fe20000000018 */
/*03c0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*03d0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*03e0*/ FFMA R22, R27, R22, R23 ; /* 0x000000161b167223 */
/* 0x000fe40000000017 */
/*03f0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0400*/ FFMA R21, R21, R27.reuse, R22 ; /* 0x0000001b15157223 */
/* 0x080fe40000000016 */
/*0410*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0420*/ FFMA R20, R27, R20, R21 ; /* 0x000000141b147223 */
/* 0x000fe40000000015 */
/*0430*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0440*/ FFMA R19, R27, R19, R20 ; /* 0x000000131b137223 */
/* 0x000fe40000000014 */
/*0450*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0460*/ FFMA R18, R27, R18, R19 ; /* 0x000000121b127223 */
/* 0x000fe40000000013 */
/*0470*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0480*/ FFMA R17, R17, R27.reuse, R18 ; /* 0x0000001b11117223 */
/* 0x080fe40000000012 */
/*0490*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04a0*/ FFMA R16, R27, R16, R17 ; /* 0x000000101b107223 */
/* 0x000fe40000000011 */
/*04b0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04c0*/ FFMA R15, R27, R15, R16 ; /* 0x0000000f1b0f7223 */
/* 0x000fe40000000010 */
/*04d0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*04e0*/ FFMA R14, R27, R14, R15 ; /* 0x0000000e1b0e7223 */
/* 0x000fe4000000000f */
/*04f0*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0500*/ FFMA R13, R13, R27.reuse, R14 ; /* 0x0000001b0d0d7223 */
/* 0x080fe4000000000e */
/*0510*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0520*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x000fe4000000000d */
/*0530*/ FMUL R27, R0, R27 ; /* 0x0000001b001b7220 */
/* 0x000fc80000400000 */
/*0540*/ FMUL R6, R0, R27 ; /* 0x0000001b00067220 */
/* 0x000fe40000400000 */
/*0550*/ FFMA R7, R27, R7, R12 ; /* 0x000000071b077223 */
/* 0x004fe2000000000c */
/*0560*/ @P1 BRA 0x210 ; /* 0xfffffca000001947 */
/* 0x000fea000383ffff */
/*0570*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fc80007ffe0ff */
/*0580*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*0590*/ @!P1 BRA 0x770 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*05a0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x0000a8000c1e1900 */
/*05b0*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x0000e8000c1e1900 */
/*05c0*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000128000c1e1900 */
/*05d0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000128000c1e1900 */
/*05e0*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000128000c1e1900 */
/*05f0*/ LDG.E R19, [R4.64+0x14] ; /* 0x0000140404137981 */
/* 0x000128000c1e1900 */
/*0600*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000128000c1e1900 */
/*0610*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000122000c1e1900 */
/*0620*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0630*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*0640*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*0650*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fc80007f3e0ff */
/*0660*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0670*/ FFMA R14, R6, R14, R7 ; /* 0x0000000e060e7223 */
/* 0x004fe40000000007 */
/*0680*/ FMUL R7, R0, R6 ; /* 0x0000000600077220 */
/* 0x020fc80000400000 */
/*0690*/ FFMA R14, R15, R7.reuse, R14 ; /* 0x000000070f0e7223 */
/* 0x088fe4000000000e */
/*06a0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06b0*/ FFMA R14, R7, R16, R14 ; /* 0x00000010070e7223 */
/* 0x010fe4000000000e */
/*06c0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06d0*/ FFMA R14, R7, R17, R14 ; /* 0x00000011070e7223 */
/* 0x000fe4000000000e */
/*06e0*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*06f0*/ FFMA R14, R7, R18, R14 ; /* 0x00000012070e7223 */
/* 0x000fe4000000000e */
/*0700*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*0710*/ FFMA R19, R19, R7.reuse, R14 ; /* 0x0000000713137223 */
/* 0x080fe4000000000e */
/*0720*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc80000400000 */
/*0730*/ FFMA R12, R7, R12, R19 ; /* 0x0000000c070c7223 */
/* 0x000fe40000000013 */
/*0740*/ FMUL R15, R0, R7 ; /* 0x00000007000f7220 */
/* 0x000fc80000400000 */
/*0750*/ FFMA R7, R15, R13, R12 ; /* 0x0000000d0f077223 */
/* 0x000fe4000000000c */
/*0760*/ FMUL R6, R0, R15 ; /* 0x0000000f00067220 */
/* 0x000fe40000400000 */
/*0770*/ ISETP.NE.OR P0, PT, R10, -0x1, P0 ; /* 0xffffffff0a00780c */
/* 0x000fda0000705670 */
/*0780*/ @!P0 BRA 0x8d0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000122000c1e1900 */
/*07d0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc40007ffe0ff */
/*07e0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ ISETP.NE.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x000fe20003f05270 */
/*0800*/ FFMA R12, R12, R6.reuse, R7 ; /* 0x000000060c0c7223 */
/* 0x084fe40000000007 */
/*0810*/ FMUL R7, R0, R6 ; /* 0x0000000600077220 */
/* 0x020fc80000400000 */
/*0820*/ FFMA R12, R13, R7.reuse, R12 ; /* 0x000000070d0c7223 */
/* 0x088fe2000000000c */
/*0830*/ IADD3 R13, P1, R4, 0x10, RZ ; /* 0x00000010040d7810 */
/* 0x000fe20007f3e0ff */
/*0840*/ FMUL R7, R0, R7 ; /* 0x0000000700077220 */
/* 0x000fc60000400000 */
/*0850*/ IADD3.X R14, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0e7210 */
/* 0x000fe20000ffe4ff */
/*0860*/ FFMA R12, R15, R7, R12 ; /* 0x000000070f0c7223 */
/* 0x010fe2000000000c */
/*0870*/ MOV R4, R13 ; /* 0x0000000d00047202 */
/* 0x001fe20000000f00 */
/*0880*/ FMUL R15, R0, R7 ; /* 0x00000007000f7220 */
/* 0x000fe20000400000 */
/*0890*/ MOV R5, R14 ; /* 0x0000000e00057202 */
/* 0x000fc60000000f00 */
/*08a0*/ FFMA R7, R17, R15.reuse, R12 ; /* 0x0000000f11077223 */
/* 0x080fe4000000000c */
/*08b0*/ FMUL R6, R0, R15 ; /* 0x0000000f00067220 */
/* 0x000fe20000400000 */
/*08c0*/ @P0 BRA 0x790 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*08d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fda0003f05270 */
/*08e0*/ @!P0 BRA 0xa40 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD.WIDE R4, R11, R8, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fca00078e0208 */
/*0900*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R10, P1, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fe40007f3e0ff */
/*0930*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0940*/ IADD3.X R12, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0c7210 */
/* 0x000fe20000ffe4ff */
/*0950*/ FFMA R7, R8, R6, R7 ; /* 0x0000000608077223 */
/* 0x004fd40000000007 */
/*0960*/ @!P0 BRA 0xa40 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0970*/ FMUL R11, R0, R6 ; /* 0x00000006000b7220 */
/* 0x020fe40000400000 */
/*0980*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0990*/ MOV R5, R12 ; /* 0x0000000c00057202 */
/* 0x000fca0000000f00 */
/*09a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*09d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*09e0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*09f0*/ FFMA R7, R4, R11.reuse, R7 ; /* 0x0000000b04077223 */
/* 0x084fe40000000007 */
/*0a00*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x000fd00000400000 */
/*0a10*/ @P0 BRA 0x980 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0a20*/ BRA 0xa40 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a30*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fca0000000f00 */
/*0a40*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20polynomial_expansionPfiiS_
.globl _Z20polynomial_expansionPfiiS_
.p2align 8
.type _Z20polynomial_expansionPfiiS_,@function
_Z20polynomial_expansionPfiiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 0
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_add_i32 s4, s4, 1
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_mov_b32_e32 v4, 1.0
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[0:1], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v4, v3
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20polynomial_expansionPfiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20polynomial_expansionPfiiS_, .Lfunc_end0-_Z20polynomial_expansionPfiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20polynomial_expansionPfiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20polynomial_expansionPfiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002b37d_00000000-6_polynomial_expansion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
.type _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_, @function
_Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20polynomial_expansionPfiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_, .-_Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
.globl _Z20polynomial_expansionPfiiS_
.type _Z20polynomial_expansionPfiiS_, @function
_Z20polynomial_expansionPfiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20polynomial_expansionPfiiS_PfiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20polynomial_expansionPfiiS_, .-_Z20polynomial_expansionPfiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20polynomial_expansionPfiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20polynomial_expansionPfiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "polynomial_expansion.hip"
.globl _Z35__device_stub__polynomial_expansionPfiiS_ # -- Begin function _Z35__device_stub__polynomial_expansionPfiiS_
.p2align 4, 0x90
.type _Z35__device_stub__polynomial_expansionPfiiS_,@function
_Z35__device_stub__polynomial_expansionPfiiS_: # @_Z35__device_stub__polynomial_expansionPfiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20polynomial_expansionPfiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__polynomial_expansionPfiiS_, .Lfunc_end0-_Z35__device_stub__polynomial_expansionPfiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20polynomial_expansionPfiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20polynomial_expansionPfiiS_,@object # @_Z20polynomial_expansionPfiiS_
.section .rodata,"a",@progbits
.globl _Z20polynomial_expansionPfiiS_
.p2align 3, 0x0
_Z20polynomial_expansionPfiiS_:
.quad _Z35__device_stub__polynomial_expansionPfiiS_
.size _Z20polynomial_expansionPfiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20polynomial_expansionPfiiS_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__polynomial_expansionPfiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20polynomial_expansionPfiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define COALESCED_NUM 16
#define blockDimX 512
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 1
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define globalDimX 512
#define globalDimY 1
__global__ void reduction(float * A, int size, int segSize)
{
#pragma gCompiler gValue segSize 262144
__shared__ float shared_1[512];
float tmp_4;
float tmp_5;
float a;
float b;
float c;
a=A[idx];
b=A[(idx+((262144/128)/2))];
c=(a+b);
tmp_4=c;
a=A[(idx+512)];
b=A[((idx+512)+((262144/128)/2))];
c=(a+b);
tmp_5=c;
a=tmp_4;
b=tmp_5;
c=(a+b);
shared_1[(tidx+0)]=c;
__syncthreads();
if ((idx<256))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+256)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<128))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+128)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<64))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+64)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<32))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+32)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<16))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+16)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<8))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+8)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<4))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+4)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<2))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+2)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<1))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+1)];
c=(a+b);
A[idx]=c;
}
} | code for sm_80
Function : _Z9reductionPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ USHF.L.U32 UR4, UR4, 0x9, URZ ; /* 0x0000000904047899 */
/* 0x001fcc000800063f */
/*0060*/ IADD3 R4, R0, UR4, RZ ; /* 0x0000000400047c10 */
/* 0x002fc8000fffe0ff */
/*0070*/ IADD3 R6, R4.reuse, 0x400, RZ ; /* 0x0000040004067810 */
/* 0x040fe40007ffe0ff */
/*0080*/ IADD3 R8, R4.reuse, 0x200, RZ ; /* 0x0000020004087810 */
/* 0x040fe40007ffe0ff */
/*0090*/ IADD3 R10, R4, 0x600, RZ ; /* 0x00000600040a7810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R3, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0003 */
/*00b0*/ IMAD.WIDE.U32 R8, R8, R3.reuse, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x080fe400078e0003 */
/*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE.U32 R10, R10, R3.reuse, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x080fe400078e0003 */
/*00e0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ee4000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R2, R4.reuse, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe400078e0003 */
/*0100*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea2000c1e1900 */
/*0120*/ ISETP.GT.U32.AND P0, PT, R4, 0xff, PT ; /* 0x000000ff0400780c */
/* 0x000fc40003f04070 */
/*0130*/ ISETP.GT.U32.AND P1, PT, R4, 0x7f, PT ; /* 0x0000007f0400780c */
/* 0x000fe20003f24070 */
/*0140*/ FADD R12, R10, R9 ; /* 0x000000090a0c7221 */
/* 0x008fe40000000000 */
/*0150*/ FADD R5, R6, R5 ; /* 0x0000000506057221 */
/* 0x004fc80000000000 */
/*0160*/ FADD R5, R5, R12 ; /* 0x0000000c05057221 */
/* 0x000fca0000000000 */
/*0170*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x000fe80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @!P0 LDS R12, [R0.X4] ; /* 0x00000000000c8984 */
/* 0x000fe80000004800 */
/*01a0*/ @!P0 LDS R7, [R0.X4+0x400] ; /* 0x0004000000078984 */
/* 0x000e240000004800 */
/*01b0*/ @!P0 FADD R7, R12, R7 ; /* 0x000000070c078221 */
/* 0x001fca0000000000 */
/*01c0*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ @!P1 LDS R6, [R0.X4] ; /* 0x0000000000069984 */
/* 0x000fe80000004800 */
/*01f0*/ @!P1 LDS R9, [R0.X4+0x200] ; /* 0x0002000000099984 */
/* 0x000e220000004800 */
/*0200*/ ISETP.GT.U32.AND P0, PT, R4, 0x3f, PT ; /* 0x0000003f0400780c */
/* 0x000fe20003f04070 */
/*0210*/ @!P1 FADD R9, R6, R9 ; /* 0x0000000906099221 */
/* 0x001fca0000000000 */
/*0220*/ @!P1 STS [R0.X4], R9 ; /* 0x0000000900009388 */
/* 0x000fe80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ @!P0 LDS R5, [R0.X4] ; /* 0x0000000000058984 */
/* 0x000fe80000004800 */
/*0250*/ @!P0 LDS R6, [R0.X4+0x100] ; /* 0x0001000000068984 */
/* 0x000e220000004800 */
/*0260*/ ISETP.GT.U32.AND P1, PT, R4, 0x1f, PT ; /* 0x0000001f0400780c */
/* 0x000fe20003f24070 */
/*0270*/ @!P0 FADD R5, R5, R6 ; /* 0x0000000605058221 */
/* 0x001fca0000000000 */
/*0280*/ @!P0 STS [R0.X4], R5 ; /* 0x0000000500008388 */
/* 0x000fe80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ @!P1 LDS R6, [R0.X4] ; /* 0x0000000000069984 */
/* 0x000fe80000004800 */
/*02b0*/ @!P1 LDS R7, [R0.X4+0x80] ; /* 0x0000800000079984 */
/* 0x000e220000004800 */
/*02c0*/ ISETP.GT.U32.AND P0, PT, R4, 0xf, PT ; /* 0x0000000f0400780c */
/* 0x000fe20003f04070 */
/*02d0*/ @!P1 FADD R7, R6, R7 ; /* 0x0000000706079221 */
/* 0x001fca0000000000 */
/*02e0*/ @!P1 STS [R0.X4], R7 ; /* 0x0000000700009388 */
/* 0x000fe80000004800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ @!P0 LDS R6, [R0.X4] ; /* 0x0000000000068984 */
/* 0x000fe80000004800 */
/*0310*/ @!P0 LDS R9, [R0.X4+0x40] ; /* 0x0000400000098984 */
/* 0x000e220000004800 */
/*0320*/ ISETP.GT.U32.AND P1, PT, R4, 0x7, PT ; /* 0x000000070400780c */
/* 0x000fe20003f24070 */
/*0330*/ @!P0 FADD R9, R6, R9 ; /* 0x0000000906098221 */
/* 0x001fca0000000000 */
/*0340*/ @!P0 STS [R0.X4], R9 ; /* 0x0000000900008388 */
/* 0x000fe80000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ @!P1 LDS R5, [R0.X4] ; /* 0x0000000000059984 */
/* 0x000fe80000004800 */
/*0370*/ @!P1 LDS R6, [R0.X4+0x20] ; /* 0x0000200000069984 */
/* 0x000e220000004800 */
/*0380*/ ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f04070 */
/*0390*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*03a0*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03c0*/ @!P0 LDS R6, [R0.X4] ; /* 0x0000000000068984 */
/* 0x000fe80000004800 */
/*03d0*/ @!P0 LDS R7, [R0.X4+0x10] ; /* 0x0000100000078984 */
/* 0x000e220000004800 */
/*03e0*/ ISETP.GT.U32.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f24070 */
/*03f0*/ @!P0 FADD R7, R6, R7 ; /* 0x0000000706078221 */
/* 0x001fca0000000000 */
/*0400*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0420*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0430*/ @!P1 LDS R9, [R0.X4+0x8] ; /* 0x0000080000099984 */
/* 0x000e220000004800 */
/*0440*/ IADD3 R6, -R0, RZ, RZ ; /* 0x000000ff00067210 */
/* 0x000fc80007ffe1ff */
/*0450*/ ISETP.NE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf05270 */
/*0460*/ @!P1 FADD R9, R4, R9 ; /* 0x0000000904099221 */
/* 0x001fca0000000000 */
/*0470*/ @!P1 STS [R0.X4], R9 ; /* 0x0000000900009388 */
/* 0x0001e80000004800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04a0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x001fe80000004800 */
/*04b0*/ LDS R5, [R0.X4+0x4] ; /* 0x0000040000057984 */
/* 0x000e240000004800 */
/*04c0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*04d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define COALESCED_NUM 16
#define blockDimX 512
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 1
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define globalDimX 512
#define globalDimY 1
__global__ void reduction(float * A, int size, int segSize)
{
#pragma gCompiler gValue segSize 262144
__shared__ float shared_1[512];
float tmp_4;
float tmp_5;
float a;
float b;
float c;
a=A[idx];
b=A[(idx+((262144/128)/2))];
c=(a+b);
tmp_4=c;
a=A[(idx+512)];
b=A[((idx+512)+((262144/128)/2))];
c=(a+b);
tmp_5=c;
a=tmp_4;
b=tmp_5;
c=(a+b);
shared_1[(tidx+0)]=c;
__syncthreads();
if ((idx<256))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+256)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<128))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+128)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<64))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+64)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<32))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+32)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<16))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+16)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<8))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+8)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<4))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+4)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<2))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+2)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<1))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+1)];
c=(a+b);
A[idx]=c;
}
} | .file "tmpxft_00182f91_00000000-6_gcompiler_reduction_output.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9reductionPfiiPfii
.type _Z30__device_stub__Z9reductionPfiiPfii, @function
_Z30__device_stub__Z9reductionPfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reductionPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9reductionPfiiPfii, .-_Z30__device_stub__Z9reductionPfiiPfii
.globl _Z9reductionPfii
.type _Z9reductionPfii, @function
_Z9reductionPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9reductionPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPfii, .-_Z9reductionPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define COALESCED_NUM 16
#define blockDimX 512
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 1
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define globalDimX 512
#define globalDimY 1
__global__ void reduction(float * A, int size, int segSize)
{
#pragma gCompiler gValue segSize 262144
__shared__ float shared_1[512];
float tmp_4;
float tmp_5;
float a;
float b;
float c;
a=A[idx];
b=A[(idx+((262144/128)/2))];
c=(a+b);
tmp_4=c;
a=A[(idx+512)];
b=A[((idx+512)+((262144/128)/2))];
c=(a+b);
tmp_5=c;
a=tmp_4;
b=tmp_5;
c=(a+b);
shared_1[(tidx+0)]=c;
__syncthreads();
if ((idx<256))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+256)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<128))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+128)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<64))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+64)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<32))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+32)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<16))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+16)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<8))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+8)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<4))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+4)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<2))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+2)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<1))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+1)];
c=(a+b);
A[idx]=c;
}
} | #include <hip/hip_runtime.h>
#define COALESCED_NUM 16
#define blockDimX 512
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 1
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define globalDimX 512
#define globalDimY 1
__global__ void reduction(float * A, int size, int segSize)
{
#pragma gCompiler gValue segSize 262144
__shared__ float shared_1[512];
float tmp_4;
float tmp_5;
float a;
float b;
float c;
a=A[idx];
b=A[(idx+((262144/128)/2))];
c=(a+b);
tmp_4=c;
a=A[(idx+512)];
b=A[((idx+512)+((262144/128)/2))];
c=(a+b);
tmp_5=c;
a=tmp_4;
b=tmp_5;
c=(a+b);
shared_1[(tidx+0)]=c;
__syncthreads();
if ((idx<256))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+256)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<128))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+128)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<64))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+64)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<32))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+32)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<16))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+16)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<8))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+8)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<4))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+4)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<2))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+2)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<1))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+1)];
c=(a+b);
A[idx]=c;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define COALESCED_NUM 16
#define blockDimX 512
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 1
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define globalDimX 512
#define globalDimY 1
__global__ void reduction(float * A, int size, int segSize)
{
#pragma gCompiler gValue segSize 262144
__shared__ float shared_1[512];
float tmp_4;
float tmp_5;
float a;
float b;
float c;
a=A[idx];
b=A[(idx+((262144/128)/2))];
c=(a+b);
tmp_4=c;
a=A[(idx+512)];
b=A[((idx+512)+((262144/128)/2))];
c=(a+b);
tmp_5=c;
a=tmp_4;
b=tmp_5;
c=(a+b);
shared_1[(tidx+0)]=c;
__syncthreads();
if ((idx<256))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+256)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<128))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+128)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<64))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+64)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<32))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+32)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<16))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+16)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<8))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+8)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<4))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+4)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<2))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+2)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<1))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+1)];
c=(a+b);
A[idx]=c;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfii
.globl _Z9reductionPfii
.p2align 8
.type _Z9reductionPfii,@function
_Z9reductionPfii:
s_load_b64 s[2:3], s[0:1], 0x0
s_lshl_b32 s0, s15, 9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s0, v0
s_mov_b32 s1, exec_lo
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v3, 0x400, v1
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, 0x200, v1
v_dual_mov_b32 v10, v2 :: v_dual_add_nc_u32 v9, 0x600, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v11
v_lshlrev_b64 v[8:9], 2, v[9:10]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_clause 0x3
global_load_b32 v10, v[2:3], off
global_load_b32 v6, v[6:7], off
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[8:9], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v6, v10, v6 :: v_dual_add_f32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v5, v6, v5 :: v_dual_lshlrev_b32 v4, 2, v0
ds_store_b32 v4, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v1
s_cbranch_execz .LBB0_2
ds_load_2addr_stride64_b32 v[5:6], v4 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_store_b32 v4, v5
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v1
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:512
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v1
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:256
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v1
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:128
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 16, v1
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:64
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v1
s_cbranch_execz .LBB0_12
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 4, v1
s_cbranch_execz .LBB0_14
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v1
s_cbranch_execz .LBB0_16
v_lshlrev_b32_e32 v1, 2, v0
ds_load_b32 v5, v4
ds_load_b32 v1, v1 offset:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v5, v1
ds_store_b32 v4, v1
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_eq_u32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_18
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v1, v4
ds_load_b32 v0, v0 offset:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfii, .Lfunc_end0-_Z9reductionPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define COALESCED_NUM 16
#define blockDimX 512
#define blockDimY 1
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define idx (blockIdx.x*blockDimX+threadIdx.x)
#define idy (blockIdx.y*blockDimY+threadIdx.y)
#define bidy (blockIdx.y)
#define bidx (blockIdx.x)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define merger_y 1
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define globalDimX 512
#define globalDimY 1
__global__ void reduction(float * A, int size, int segSize)
{
#pragma gCompiler gValue segSize 262144
__shared__ float shared_1[512];
float tmp_4;
float tmp_5;
float a;
float b;
float c;
a=A[idx];
b=A[(idx+((262144/128)/2))];
c=(a+b);
tmp_4=c;
a=A[(idx+512)];
b=A[((idx+512)+((262144/128)/2))];
c=(a+b);
tmp_5=c;
a=tmp_4;
b=tmp_5;
c=(a+b);
shared_1[(tidx+0)]=c;
__syncthreads();
if ((idx<256))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+256)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<128))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+128)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<64))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+64)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<32))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+32)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<16))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+16)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<8))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+8)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<4))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+4)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<2))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+2)];
c=(a+b);
shared_1[(tidx+0)]=c;
}
__syncthreads();
if ((idx<1))
{
float a;
float b;
float c;
a=shared_1[(tidx+0)];
b=shared_1[(tidx+1)];
c=(a+b);
A[idx]=c;
}
} | .text
.file "gcompiler_reduction_output.hip"
.globl _Z24__device_stub__reductionPfii # -- Begin function _Z24__device_stub__reductionPfii
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfii,@function
_Z24__device_stub__reductionPfii: # @_Z24__device_stub__reductionPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfii, .Lfunc_end0-_Z24__device_stub__reductionPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfii,@object # @_Z9reductionPfii
.section .rodata,"a",@progbits
.globl _Z9reductionPfii
.p2align 3, 0x0
_Z9reductionPfii:
.quad _Z24__device_stub__reductionPfii
.size _Z9reductionPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPfii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reductionPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ USHF.L.U32 UR4, UR4, 0x9, URZ ; /* 0x0000000904047899 */
/* 0x001fcc000800063f */
/*0060*/ IADD3 R4, R0, UR4, RZ ; /* 0x0000000400047c10 */
/* 0x002fc8000fffe0ff */
/*0070*/ IADD3 R6, R4.reuse, 0x400, RZ ; /* 0x0000040004067810 */
/* 0x040fe40007ffe0ff */
/*0080*/ IADD3 R8, R4.reuse, 0x200, RZ ; /* 0x0000020004087810 */
/* 0x040fe40007ffe0ff */
/*0090*/ IADD3 R10, R4, 0x600, RZ ; /* 0x00000600040a7810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R3, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0003 */
/*00b0*/ IMAD.WIDE.U32 R8, R8, R3.reuse, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x080fe400078e0003 */
/*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE.U32 R10, R10, R3.reuse, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x080fe400078e0003 */
/*00e0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ee4000c1e1900 */
/*00f0*/ IMAD.WIDE.U32 R2, R4.reuse, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x040fe400078e0003 */
/*0100*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea2000c1e1900 */
/*0120*/ ISETP.GT.U32.AND P0, PT, R4, 0xff, PT ; /* 0x000000ff0400780c */
/* 0x000fc40003f04070 */
/*0130*/ ISETP.GT.U32.AND P1, PT, R4, 0x7f, PT ; /* 0x0000007f0400780c */
/* 0x000fe20003f24070 */
/*0140*/ FADD R12, R10, R9 ; /* 0x000000090a0c7221 */
/* 0x008fe40000000000 */
/*0150*/ FADD R5, R6, R5 ; /* 0x0000000506057221 */
/* 0x004fc80000000000 */
/*0160*/ FADD R5, R5, R12 ; /* 0x0000000c05057221 */
/* 0x000fca0000000000 */
/*0170*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x000fe80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @!P0 LDS R12, [R0.X4] ; /* 0x00000000000c8984 */
/* 0x000fe80000004800 */
/*01a0*/ @!P0 LDS R7, [R0.X4+0x400] ; /* 0x0004000000078984 */
/* 0x000e240000004800 */
/*01b0*/ @!P0 FADD R7, R12, R7 ; /* 0x000000070c078221 */
/* 0x001fca0000000000 */
/*01c0*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ @!P1 LDS R6, [R0.X4] ; /* 0x0000000000069984 */
/* 0x000fe80000004800 */
/*01f0*/ @!P1 LDS R9, [R0.X4+0x200] ; /* 0x0002000000099984 */
/* 0x000e220000004800 */
/*0200*/ ISETP.GT.U32.AND P0, PT, R4, 0x3f, PT ; /* 0x0000003f0400780c */
/* 0x000fe20003f04070 */
/*0210*/ @!P1 FADD R9, R6, R9 ; /* 0x0000000906099221 */
/* 0x001fca0000000000 */
/*0220*/ @!P1 STS [R0.X4], R9 ; /* 0x0000000900009388 */
/* 0x000fe80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ @!P0 LDS R5, [R0.X4] ; /* 0x0000000000058984 */
/* 0x000fe80000004800 */
/*0250*/ @!P0 LDS R6, [R0.X4+0x100] ; /* 0x0001000000068984 */
/* 0x000e220000004800 */
/*0260*/ ISETP.GT.U32.AND P1, PT, R4, 0x1f, PT ; /* 0x0000001f0400780c */
/* 0x000fe20003f24070 */
/*0270*/ @!P0 FADD R5, R5, R6 ; /* 0x0000000605058221 */
/* 0x001fca0000000000 */
/*0280*/ @!P0 STS [R0.X4], R5 ; /* 0x0000000500008388 */
/* 0x000fe80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ @!P1 LDS R6, [R0.X4] ; /* 0x0000000000069984 */
/* 0x000fe80000004800 */
/*02b0*/ @!P1 LDS R7, [R0.X4+0x80] ; /* 0x0000800000079984 */
/* 0x000e220000004800 */
/*02c0*/ ISETP.GT.U32.AND P0, PT, R4, 0xf, PT ; /* 0x0000000f0400780c */
/* 0x000fe20003f04070 */
/*02d0*/ @!P1 FADD R7, R6, R7 ; /* 0x0000000706079221 */
/* 0x001fca0000000000 */
/*02e0*/ @!P1 STS [R0.X4], R7 ; /* 0x0000000700009388 */
/* 0x000fe80000004800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ @!P0 LDS R6, [R0.X4] ; /* 0x0000000000068984 */
/* 0x000fe80000004800 */
/*0310*/ @!P0 LDS R9, [R0.X4+0x40] ; /* 0x0000400000098984 */
/* 0x000e220000004800 */
/*0320*/ ISETP.GT.U32.AND P1, PT, R4, 0x7, PT ; /* 0x000000070400780c */
/* 0x000fe20003f24070 */
/*0330*/ @!P0 FADD R9, R6, R9 ; /* 0x0000000906098221 */
/* 0x001fca0000000000 */
/*0340*/ @!P0 STS [R0.X4], R9 ; /* 0x0000000900008388 */
/* 0x000fe80000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ @!P1 LDS R5, [R0.X4] ; /* 0x0000000000059984 */
/* 0x000fe80000004800 */
/*0370*/ @!P1 LDS R6, [R0.X4+0x20] ; /* 0x0000200000069984 */
/* 0x000e220000004800 */
/*0380*/ ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f04070 */
/*0390*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*03a0*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03c0*/ @!P0 LDS R6, [R0.X4] ; /* 0x0000000000068984 */
/* 0x000fe80000004800 */
/*03d0*/ @!P0 LDS R7, [R0.X4+0x10] ; /* 0x0000100000078984 */
/* 0x000e220000004800 */
/*03e0*/ ISETP.GT.U32.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f24070 */
/*03f0*/ @!P0 FADD R7, R6, R7 ; /* 0x0000000706078221 */
/* 0x001fca0000000000 */
/*0400*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0420*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0430*/ @!P1 LDS R9, [R0.X4+0x8] ; /* 0x0000080000099984 */
/* 0x000e220000004800 */
/*0440*/ IADD3 R6, -R0, RZ, RZ ; /* 0x000000ff00067210 */
/* 0x000fc80007ffe1ff */
/*0450*/ ISETP.NE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf05270 */
/*0460*/ @!P1 FADD R9, R4, R9 ; /* 0x0000000904099221 */
/* 0x001fca0000000000 */
/*0470*/ @!P1 STS [R0.X4], R9 ; /* 0x0000000900009388 */
/* 0x0001e80000004800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04a0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x001fe80000004800 */
/*04b0*/ LDS R5, [R0.X4+0x4] ; /* 0x0000040000057984 */
/* 0x000e240000004800 */
/*04c0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*04d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfii
.globl _Z9reductionPfii
.p2align 8
.type _Z9reductionPfii,@function
_Z9reductionPfii:
s_load_b64 s[2:3], s[0:1], 0x0
s_lshl_b32 s0, s15, 9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s0, v0
s_mov_b32 s1, exec_lo
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v3, 0x400, v1
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, 0x200, v1
v_dual_mov_b32 v10, v2 :: v_dual_add_nc_u32 v9, 0x600, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v11
v_lshlrev_b64 v[8:9], 2, v[9:10]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_clause 0x3
global_load_b32 v10, v[2:3], off
global_load_b32 v6, v[6:7], off
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[8:9], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v6, v10, v6 :: v_dual_add_f32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v5, v6, v5 :: v_dual_lshlrev_b32 v4, 2, v0
ds_store_b32 v4, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v1
s_cbranch_execz .LBB0_2
ds_load_2addr_stride64_b32 v[5:6], v4 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_store_b32 v4, v5
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v1
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:512
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v1
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:256
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v1
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:128
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 16, v1
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:64
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v1
s_cbranch_execz .LBB0_12
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 4, v1
s_cbranch_execz .LBB0_14
v_lshlrev_b32_e32 v5, 2, v0
ds_load_b32 v6, v4
ds_load_b32 v5, v5 offset:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v6, v5
ds_store_b32 v4, v5
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v1
s_cbranch_execz .LBB0_16
v_lshlrev_b32_e32 v1, 2, v0
ds_load_b32 v5, v4
ds_load_b32 v1, v1 offset:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v5, v1
ds_store_b32 v4, v1
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_eq_u32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_18
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v1, v4
ds_load_b32 v0, v0 offset:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfii, .Lfunc_end0-_Z9reductionPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00182f91_00000000-6_gcompiler_reduction_output.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9reductionPfiiPfii
.type _Z30__device_stub__Z9reductionPfiiPfii, @function
_Z30__device_stub__Z9reductionPfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reductionPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9reductionPfiiPfii, .-_Z30__device_stub__Z9reductionPfiiPfii
.globl _Z9reductionPfii
.type _Z9reductionPfii, @function
_Z9reductionPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9reductionPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPfii, .-_Z9reductionPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gcompiler_reduction_output.hip"
.globl _Z24__device_stub__reductionPfii # -- Begin function _Z24__device_stub__reductionPfii
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfii,@function
_Z24__device_stub__reductionPfii: # @_Z24__device_stub__reductionPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfii, .Lfunc_end0-_Z24__device_stub__reductionPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfii,@object # @_Z9reductionPfii
.section .rodata,"a",@progbits
.globl _Z9reductionPfii
.p2align 3, 0x0
_Z9reductionPfii:
.quad _Z24__device_stub__reductionPfii
.size _Z9reductionPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPfii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
using namespace std;
__global__ void kernel_sum (int *A, int *B, int *C, int n);
void sum (int *A, int *B, int *C, int n);
int main()
{
int n;
cout<<"Enter n:";
cin>>n;
int size=n*sizeof(int);
int *deviceA,*deviceB,*deviceC;
int *hostA = (int*)malloc(size);
int *hostB = (int*)malloc(size);
int *hostC = (int*)malloc(size);
cudaEvent_t start,end,start1,end1;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventCreate(&start1);
cudaEventCreate(&end1);
for(int i=0;i<n;i++)
{
hostA[i]=rand()%n;
hostB[i]=rand()%n;
}
cout<<"\nHost A:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]<<"\t";
}
cout<<"\nHost B:\n";
for(int i=0;i<n;i++)
{
cout<<hostB[i]<<"\t";
}
float t=0,t1=0;
cudaEventRecord(start);
cout<<"\nSequential processing result:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t";
}
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&t,start,end);
cudaMalloc(&deviceA,size);
cudaMalloc(&deviceB,size);
cudaMalloc(&deviceC,size);
cudaMemcpy(deviceA,hostA,size,cudaMemcpyHostToDevice);
cudaMemcpy(deviceB,hostB,size,cudaMemcpyHostToDevice);
cudaEventRecord(start1);
sum(deviceA,deviceB,deviceC,n);
cudaEventRecord(end1);
cudaEventSynchronize(end1);
cudaEventElapsedTime(&t1,start1,end1);
cudaMemcpy(hostC,deviceC,size,cudaMemcpyDeviceToHost);
cout<<"\nParallel Execution:\nExpected\tActual\n\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t\t"<<hostC[i]<<"\n";
}
cout<<"\n";
cout<<"\nSequential time:"<<t;
cout<<"\nParallel time:"<<t1;
cudaFree(deviceA);
cudaFree(deviceB);
cudaFree(deviceC);
return cudaDeviceSynchronize();
}
void sum(int *A, int *B, int *C, int n)
{
int threadsPerBlock, blocksPerGrid;
if(n<512)
{
threadsPerBlock = n;
blocksPerGrid = 1;
}
else
{
threadsPerBlock = 512;
blocksPerGrid = ceil(double(n)/double(threadsPerBlock));
}
kernel_sum<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,n);
}
__global__ void kernel_sum (int *A, int *B, int *C, int n)
{
int index=blockDim.x * blockIdx.x + threadIdx.x;
if(index<n)
C[index] = A[index] + B[index];
} | code for sm_80
Function : _Z10kernel_sumPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
using namespace std;
__global__ void kernel_sum (int *A, int *B, int *C, int n);
void sum (int *A, int *B, int *C, int n);
int main()
{
int n;
cout<<"Enter n:";
cin>>n;
int size=n*sizeof(int);
int *deviceA,*deviceB,*deviceC;
int *hostA = (int*)malloc(size);
int *hostB = (int*)malloc(size);
int *hostC = (int*)malloc(size);
cudaEvent_t start,end,start1,end1;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventCreate(&start1);
cudaEventCreate(&end1);
for(int i=0;i<n;i++)
{
hostA[i]=rand()%n;
hostB[i]=rand()%n;
}
cout<<"\nHost A:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]<<"\t";
}
cout<<"\nHost B:\n";
for(int i=0;i<n;i++)
{
cout<<hostB[i]<<"\t";
}
float t=0,t1=0;
cudaEventRecord(start);
cout<<"\nSequential processing result:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t";
}
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&t,start,end);
cudaMalloc(&deviceA,size);
cudaMalloc(&deviceB,size);
cudaMalloc(&deviceC,size);
cudaMemcpy(deviceA,hostA,size,cudaMemcpyHostToDevice);
cudaMemcpy(deviceB,hostB,size,cudaMemcpyHostToDevice);
cudaEventRecord(start1);
sum(deviceA,deviceB,deviceC,n);
cudaEventRecord(end1);
cudaEventSynchronize(end1);
cudaEventElapsedTime(&t1,start1,end1);
cudaMemcpy(hostC,deviceC,size,cudaMemcpyDeviceToHost);
cout<<"\nParallel Execution:\nExpected\tActual\n\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t\t"<<hostC[i]<<"\n";
}
cout<<"\n";
cout<<"\nSequential time:"<<t;
cout<<"\nParallel time:"<<t1;
cudaFree(deviceA);
cudaFree(deviceB);
cudaFree(deviceC);
return cudaDeviceSynchronize();
}
void sum(int *A, int *B, int *C, int n)
{
int threadsPerBlock, blocksPerGrid;
if(n<512)
{
threadsPerBlock = n;
blocksPerGrid = 1;
}
else
{
threadsPerBlock = 512;
blocksPerGrid = ceil(double(n)/double(threadsPerBlock));
}
kernel_sum<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,n);
}
__global__ void kernel_sum (int *A, int *B, int *C, int n)
{
int index=blockDim.x * blockIdx.x + threadIdx.x;
if(index<n)
C[index] = A[index] + B[index];
} | .file "tmpxft_00168b56_00000000-6_vector_addition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kernel_sumPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i
.globl _Z10kernel_sumPiS_S_i
.type _Z10kernel_sumPiS_S_i, @function
_Z10kernel_sumPiS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z10kernel_sumPiS_S_i, .-_Z10kernel_sumPiS_S_i
.globl _Z3sumPiS_S_i
.type _Z3sumPiS_S_i, @function
_Z3sumPiS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
cmpl $511, %ecx
jle .L15
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L13
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L13:
cvttsd2sil %xmm3, %eax
movl $512, %edx
.L12:
movl %edx, 20(%rsp)
movl $1, 24(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ecx, %edx
movl $1, %eax
jmp .L12
.L17:
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i
jmp .L11
.cfi_endproc
.LFE3670:
.size _Z3sumPiS_S_i, .-_Z3sumPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Enter n:"
.LC6:
.string "\nHost A:\n"
.LC7:
.string "\t"
.LC8:
.string "\nHost B:\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "\nSequential processing result:\n"
.align 8
.LC11:
.string "\nParallel Execution:\nExpected\tActual\n\n"
.section .rodata.str1.1
.LC12:
.string "\t\t"
.LC13:
.string "\n"
.LC14:
.string "\nSequential time:"
.LC15:
.string "\nParallel time:"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %eax
leal 0(,%rax,4), %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
cmpl $0, 4(%rsp)
jle .L19
movl $0, %r12d
.L20:
call rand@PLT
cltd
idivl 4(%rsp)
movl %edx, (%rbx,%r12,4)
call rand@PLT
movl 4(%rsp), %ecx
cltd
idivl %ecx
movl %edx, 0(%rbp,%r12,4)
addq $1, %r12
cmpl %r12d, %ecx
jg .L20
.L19:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
jle .L21
movl $0, %r12d
leaq _ZSt4cout(%rip), %r15
.L22:
movl (%rbx,%r12,4), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, 4(%rsp)
jg .L22
.L21:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
jle .L23
movl $0, %r12d
leaq _ZSt4cout(%rip), %r15
.L24:
movl 0(%rbp,%r12,4), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, 4(%rsp)
jg .L24
.L23:
movl $0x00000000, 8(%rsp)
movl $0x00000000, 12(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
jle .L25
movl $0, %r12d
leaq _ZSt4cout(%rip), %r15
.L26:
movl 0(%rbp,%r12,4), %esi
addl (%rbx,%r12,4), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, 4(%rsp)
jg .L26
.L25:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl 4(%rsp), %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z3sumPiS_S_i
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
jle .L27
movl $0, %r12d
leaq _ZSt4cout(%rip), %r15
.L28:
movl 0(%rbp,%r12,4), %esi
addl (%rbx,%r12,4), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movl $2, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r14,%r12,4), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC13(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, 4(%rsp)
jg .L28
.L27:
leaq .LC13(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceSynchronize@PLT
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L36
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z10kernel_sumPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_sumPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1063256064
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
using namespace std;
__global__ void kernel_sum (int *A, int *B, int *C, int n);
void sum (int *A, int *B, int *C, int n);
int main()
{
int n;
cout<<"Enter n:";
cin>>n;
int size=n*sizeof(int);
int *deviceA,*deviceB,*deviceC;
int *hostA = (int*)malloc(size);
int *hostB = (int*)malloc(size);
int *hostC = (int*)malloc(size);
cudaEvent_t start,end,start1,end1;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventCreate(&start1);
cudaEventCreate(&end1);
for(int i=0;i<n;i++)
{
hostA[i]=rand()%n;
hostB[i]=rand()%n;
}
cout<<"\nHost A:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]<<"\t";
}
cout<<"\nHost B:\n";
for(int i=0;i<n;i++)
{
cout<<hostB[i]<<"\t";
}
float t=0,t1=0;
cudaEventRecord(start);
cout<<"\nSequential processing result:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t";
}
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&t,start,end);
cudaMalloc(&deviceA,size);
cudaMalloc(&deviceB,size);
cudaMalloc(&deviceC,size);
cudaMemcpy(deviceA,hostA,size,cudaMemcpyHostToDevice);
cudaMemcpy(deviceB,hostB,size,cudaMemcpyHostToDevice);
cudaEventRecord(start1);
sum(deviceA,deviceB,deviceC,n);
cudaEventRecord(end1);
cudaEventSynchronize(end1);
cudaEventElapsedTime(&t1,start1,end1);
cudaMemcpy(hostC,deviceC,size,cudaMemcpyDeviceToHost);
cout<<"\nParallel Execution:\nExpected\tActual\n\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t\t"<<hostC[i]<<"\n";
}
cout<<"\n";
cout<<"\nSequential time:"<<t;
cout<<"\nParallel time:"<<t1;
cudaFree(deviceA);
cudaFree(deviceB);
cudaFree(deviceC);
return cudaDeviceSynchronize();
}
void sum(int *A, int *B, int *C, int n)
{
int threadsPerBlock, blocksPerGrid;
if(n<512)
{
threadsPerBlock = n;
blocksPerGrid = 1;
}
else
{
threadsPerBlock = 512;
blocksPerGrid = ceil(double(n)/double(threadsPerBlock));
}
kernel_sum<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,n);
}
__global__ void kernel_sum (int *A, int *B, int *C, int n)
{
int index=blockDim.x * blockIdx.x + threadIdx.x;
if(index<n)
C[index] = A[index] + B[index];
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
using namespace std;
__global__ void kernel_sum (int *A, int *B, int *C, int n);
void sum (int *A, int *B, int *C, int n);
int main()
{
int n;
cout<<"Enter n:";
cin>>n;
int size=n*sizeof(int);
int *deviceA,*deviceB,*deviceC;
int *hostA = (int*)malloc(size);
int *hostB = (int*)malloc(size);
int *hostC = (int*)malloc(size);
hipEvent_t start,end,start1,end1;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventCreate(&start1);
hipEventCreate(&end1);
for(int i=0;i<n;i++)
{
hostA[i]=rand()%n;
hostB[i]=rand()%n;
}
cout<<"\nHost A:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]<<"\t";
}
cout<<"\nHost B:\n";
for(int i=0;i<n;i++)
{
cout<<hostB[i]<<"\t";
}
float t=0,t1=0;
hipEventRecord(start);
cout<<"\nSequential processing result:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t";
}
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&t,start,end);
hipMalloc(&deviceA,size);
hipMalloc(&deviceB,size);
hipMalloc(&deviceC,size);
hipMemcpy(deviceA,hostA,size,hipMemcpyHostToDevice);
hipMemcpy(deviceB,hostB,size,hipMemcpyHostToDevice);
hipEventRecord(start1);
sum(deviceA,deviceB,deviceC,n);
hipEventRecord(end1);
hipEventSynchronize(end1);
hipEventElapsedTime(&t1,start1,end1);
hipMemcpy(hostC,deviceC,size,hipMemcpyDeviceToHost);
cout<<"\nParallel Execution:\nExpected\tActual\n\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t\t"<<hostC[i]<<"\n";
}
cout<<"\n";
cout<<"\nSequential time:"<<t;
cout<<"\nParallel time:"<<t1;
hipFree(deviceA);
hipFree(deviceB);
hipFree(deviceC);
return hipDeviceSynchronize();
}
void sum(int *A, int *B, int *C, int n)
{
int threadsPerBlock, blocksPerGrid;
if(n<512)
{
threadsPerBlock = n;
blocksPerGrid = 1;
}
else
{
threadsPerBlock = 512;
blocksPerGrid = ceil(double(n)/double(threadsPerBlock));
}
kernel_sum<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,n);
}
__global__ void kernel_sum (int *A, int *B, int *C, int n)
{
int index=blockDim.x * blockIdx.x + threadIdx.x;
if(index<n)
C[index] = A[index] + B[index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
using namespace std;
__global__ void kernel_sum (int *A, int *B, int *C, int n);
void sum (int *A, int *B, int *C, int n);
int main()
{
int n;
cout<<"Enter n:";
cin>>n;
int size=n*sizeof(int);
int *deviceA,*deviceB,*deviceC;
int *hostA = (int*)malloc(size);
int *hostB = (int*)malloc(size);
int *hostC = (int*)malloc(size);
hipEvent_t start,end,start1,end1;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventCreate(&start1);
hipEventCreate(&end1);
for(int i=0;i<n;i++)
{
hostA[i]=rand()%n;
hostB[i]=rand()%n;
}
cout<<"\nHost A:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]<<"\t";
}
cout<<"\nHost B:\n";
for(int i=0;i<n;i++)
{
cout<<hostB[i]<<"\t";
}
float t=0,t1=0;
hipEventRecord(start);
cout<<"\nSequential processing result:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t";
}
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&t,start,end);
hipMalloc(&deviceA,size);
hipMalloc(&deviceB,size);
hipMalloc(&deviceC,size);
hipMemcpy(deviceA,hostA,size,hipMemcpyHostToDevice);
hipMemcpy(deviceB,hostB,size,hipMemcpyHostToDevice);
hipEventRecord(start1);
sum(deviceA,deviceB,deviceC,n);
hipEventRecord(end1);
hipEventSynchronize(end1);
hipEventElapsedTime(&t1,start1,end1);
hipMemcpy(hostC,deviceC,size,hipMemcpyDeviceToHost);
cout<<"\nParallel Execution:\nExpected\tActual\n\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t\t"<<hostC[i]<<"\n";
}
cout<<"\n";
cout<<"\nSequential time:"<<t;
cout<<"\nParallel time:"<<t1;
hipFree(deviceA);
hipFree(deviceB);
hipFree(deviceC);
return hipDeviceSynchronize();
}
void sum(int *A, int *B, int *C, int n)
{
int threadsPerBlock, blocksPerGrid;
if(n<512)
{
threadsPerBlock = n;
blocksPerGrid = 1;
}
else
{
threadsPerBlock = 512;
blocksPerGrid = ceil(double(n)/double(threadsPerBlock));
}
kernel_sum<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,n);
}
__global__ void kernel_sum (int *A, int *B, int *C, int n)
{
int index=blockDim.x * blockIdx.x + threadIdx.x;
if(index<n)
C[index] = A[index] + B[index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_sumPiS_S_i
.globl _Z10kernel_sumPiS_S_i
.p2align 8
.type _Z10kernel_sumPiS_S_i,@function
_Z10kernel_sumPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_sumPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_sumPiS_S_i, .Lfunc_end0-_Z10kernel_sumPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_sumPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_sumPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
using namespace std;
__global__ void kernel_sum (int *A, int *B, int *C, int n);
void sum (int *A, int *B, int *C, int n);
int main()
{
int n;
cout<<"Enter n:";
cin>>n;
int size=n*sizeof(int);
int *deviceA,*deviceB,*deviceC;
int *hostA = (int*)malloc(size);
int *hostB = (int*)malloc(size);
int *hostC = (int*)malloc(size);
hipEvent_t start,end,start1,end1;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventCreate(&start1);
hipEventCreate(&end1);
for(int i=0;i<n;i++)
{
hostA[i]=rand()%n;
hostB[i]=rand()%n;
}
cout<<"\nHost A:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]<<"\t";
}
cout<<"\nHost B:\n";
for(int i=0;i<n;i++)
{
cout<<hostB[i]<<"\t";
}
float t=0,t1=0;
hipEventRecord(start);
cout<<"\nSequential processing result:\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t";
}
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&t,start,end);
hipMalloc(&deviceA,size);
hipMalloc(&deviceB,size);
hipMalloc(&deviceC,size);
hipMemcpy(deviceA,hostA,size,hipMemcpyHostToDevice);
hipMemcpy(deviceB,hostB,size,hipMemcpyHostToDevice);
hipEventRecord(start1);
sum(deviceA,deviceB,deviceC,n);
hipEventRecord(end1);
hipEventSynchronize(end1);
hipEventElapsedTime(&t1,start1,end1);
hipMemcpy(hostC,deviceC,size,hipMemcpyDeviceToHost);
cout<<"\nParallel Execution:\nExpected\tActual\n\n";
for(int i=0;i<n;i++)
{
cout<<hostA[i]+hostB[i]<<"\t\t"<<hostC[i]<<"\n";
}
cout<<"\n";
cout<<"\nSequential time:"<<t;
cout<<"\nParallel time:"<<t1;
hipFree(deviceA);
hipFree(deviceB);
hipFree(deviceC);
return hipDeviceSynchronize();
}
void sum(int *A, int *B, int *C, int n)
{
int threadsPerBlock, blocksPerGrid;
if(n<512)
{
threadsPerBlock = n;
blocksPerGrid = 1;
}
else
{
threadsPerBlock = 512;
blocksPerGrid = ceil(double(n)/double(threadsPerBlock));
}
kernel_sum<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,n);
}
__global__ void kernel_sum (int *A, int *B, int *C, int n)
{
int index=blockDim.x * blockIdx.x + threadIdx.x;
if(index<n)
C[index] = A[index] + B[index];
} | .text
.file "vector_addition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 12(%rsp), %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
cmpl $0, 12(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl 12(%rsp)
movl %edx, (%rbx,%r13,4)
callq rand
movslq 12(%rsp), %rcx
cltd
idivl %ecx
movl %edx, (%r14,%r13,4)
incq %r13
cmpq %rcx, %r13
jl .LBB0_2
.LBB0_3: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_6
# %bb.4: # %.lr.ph46.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph46
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_5
.LBB0_6: # %._crit_edge47
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_9
# %bb.7: # %.lr.ph50.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_8: # %.lr.ph50
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_8
.LBB0_9: # %._crit_edge51
movl $0, 20(%rsp)
movl $0, 16(%rsp)
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_12
# %bb.10: # %.lr.ph54.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_11: # %.lr.ph54
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %esi
addl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_11
.LBB0_12: # %._crit_edge55
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
movl 12(%rsp), %ecx
callq _Z3sumPiS_S_i
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_15
# %bb.13: # %.lr.ph58.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_14: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %esi
addl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.6, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15,%r13,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_14
.LBB0_15: # %._crit_edge59
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
callq hipDeviceSynchronize
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3sumPiS_S_i
.LCPI1_0:
.quad 0x3f60000000000000 # double 0.001953125
.text
.globl _Z3sumPiS_S_i
.p2align 4, 0x90
.type _Z3sumPiS_S_i,@function
_Z3sumPiS_S_i: # @_Z3sumPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movabsq $4294967296, %r13 # imm = 0x100000000
cmpl $512, %ecx # imm = 0x200
jge .LBB1_2
# %bb.1:
leaq 1(%r13), %rdi
movl %ebx, %eax
jmp .LBB1_3
.LBB1_2:
cvtsi2sd %ebx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %edi
orq %r13, %rdi
movl $512, %eax # imm = 0x200
.LBB1_3:
movl %eax, %edx
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kernel_sumPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z3sumPiS_S_i, .Lfunc_end1-_Z3sumPiS_S_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__kernel_sumPiS_S_i # -- Begin function _Z25__device_stub__kernel_sumPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__kernel_sumPiS_S_i,@function
_Z25__device_stub__kernel_sumPiS_S_i: # @_Z25__device_stub__kernel_sumPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kernel_sumPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__kernel_sumPiS_S_i, .Lfunc_end2-_Z25__device_stub__kernel_sumPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_sumPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter n:"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nHost A:\n"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\t"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nHost B:\n"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nSequential processing result:\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nParallel Execution:\nExpected\tActual\n\n"
.size .L.str.5, 39
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\t\t"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nSequential time:"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nParallel time:"
.size .L.str.9, 16
.type _Z10kernel_sumPiS_S_i,@object # @_Z10kernel_sumPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10kernel_sumPiS_S_i
.p2align 3, 0x0
_Z10kernel_sumPiS_S_i:
.quad _Z25__device_stub__kernel_sumPiS_S_i
.size _Z10kernel_sumPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_sumPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_sumPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym _Z10kernel_sumPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10kernel_sumPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_sumPiS_S_i
.globl _Z10kernel_sumPiS_S_i
.p2align 8
.type _Z10kernel_sumPiS_S_i,@function
_Z10kernel_sumPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_sumPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_sumPiS_S_i, .Lfunc_end0-_Z10kernel_sumPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_sumPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_sumPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00168b56_00000000-6_vector_addition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kernel_sumPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i
.globl _Z10kernel_sumPiS_S_i
.type _Z10kernel_sumPiS_S_i, @function
_Z10kernel_sumPiS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z10kernel_sumPiS_S_i, .-_Z10kernel_sumPiS_S_i
.globl _Z3sumPiS_S_i
.type _Z3sumPiS_S_i, @function
_Z3sumPiS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
cmpl $511, %ecx
jle .L15
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L13
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L13:
cvttsd2sil %xmm3, %eax
movl $512, %edx
.L12:
movl %edx, 20(%rsp)
movl $1, 24(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ecx, %edx
movl $1, %eax
jmp .L12
.L17:
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z35__device_stub__Z10kernel_sumPiS_S_iPiS_S_i
jmp .L11
.cfi_endproc
.LFE3670:
.size _Z3sumPiS_S_i, .-_Z3sumPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Enter n:"
.LC6:
.string "\nHost A:\n"
.LC7:
.string "\t"
.LC8:
.string "\nHost B:\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "\nSequential processing result:\n"
.align 8
.LC11:
.string "\nParallel Execution:\nExpected\tActual\n\n"
.section .rodata.str1.1
.LC12:
.string "\t\t"
.LC13:
.string "\n"
.LC14:
.string "\nSequential time:"
.LC15:
.string "\nParallel time:"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %eax
leal 0(,%rax,4), %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
cmpl $0, 4(%rsp)
jle .L19
movl $0, %r12d
.L20:
call rand@PLT
cltd
idivl 4(%rsp)
movl %edx, (%rbx,%r12,4)
call rand@PLT
movl 4(%rsp), %ecx
cltd
idivl %ecx
movl %edx, 0(%rbp,%r12,4)
addq $1, %r12
cmpl %r12d, %ecx
jg .L20
.L19:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
jle .L21
movl $0, %r12d
leaq _ZSt4cout(%rip), %r15
.L22:
movl (%rbx,%r12,4), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, 4(%rsp)
jg .L22
.L21:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
jle .L23
movl $0, %r12d
leaq _ZSt4cout(%rip), %r15
.L24:
movl 0(%rbp,%r12,4), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, 4(%rsp)
jg .L24
.L23:
movl $0x00000000, 8(%rsp)
movl $0x00000000, 12(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
jle .L25
movl $0, %r12d
leaq _ZSt4cout(%rip), %r15
.L26:
movl 0(%rbp,%r12,4), %esi
addl (%rbx,%r12,4), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, 4(%rsp)
jg .L26
.L25:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl 4(%rsp), %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z3sumPiS_S_i
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
jle .L27
movl $0, %r12d
leaq _ZSt4cout(%rip), %r15
.L28:
movl 0(%rbp,%r12,4), %esi
addl (%rbx,%r12,4), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movl $2, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r14,%r12,4), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC13(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, 4(%rsp)
jg .L28
.L27:
leaq .LC13(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceSynchronize@PLT
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L36
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z10kernel_sumPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_sumPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1063256064
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_addition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 12(%rsp), %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
cmpl $0, 12(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl 12(%rsp)
movl %edx, (%rbx,%r13,4)
callq rand
movslq 12(%rsp), %rcx
cltd
idivl %ecx
movl %edx, (%r14,%r13,4)
incq %r13
cmpq %rcx, %r13
jl .LBB0_2
.LBB0_3: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_6
# %bb.4: # %.lr.ph46.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph46
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_5
.LBB0_6: # %._crit_edge47
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_9
# %bb.7: # %.lr.ph50.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_8: # %.lr.ph50
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_8
.LBB0_9: # %._crit_edge51
movl $0, 20(%rsp)
movl $0, 16(%rsp)
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_12
# %bb.10: # %.lr.ph54.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_11: # %.lr.ph54
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %esi
addl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_11
.LBB0_12: # %._crit_edge55
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
movl 12(%rsp), %ecx
callq _Z3sumPiS_S_i
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_15
# %bb.13: # %.lr.ph58.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_14: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %esi
addl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.6, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15,%r13,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_14
.LBB0_15: # %._crit_edge59
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
callq hipDeviceSynchronize
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z3sumPiS_S_i
.LCPI1_0:
.quad 0x3f60000000000000 # double 0.001953125
.text
.globl _Z3sumPiS_S_i
.p2align 4, 0x90
.type _Z3sumPiS_S_i,@function
_Z3sumPiS_S_i: # @_Z3sumPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movabsq $4294967296, %r13 # imm = 0x100000000
cmpl $512, %ecx # imm = 0x200
jge .LBB1_2
# %bb.1:
leaq 1(%r13), %rdi
movl %ebx, %eax
jmp .LBB1_3
.LBB1_2:
cvtsi2sd %ebx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %edi
orq %r13, %rdi
movl $512, %eax # imm = 0x200
.LBB1_3:
movl %eax, %edx
orq %r13, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kernel_sumPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z3sumPiS_S_i, .Lfunc_end1-_Z3sumPiS_S_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__kernel_sumPiS_S_i # -- Begin function _Z25__device_stub__kernel_sumPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__kernel_sumPiS_S_i,@function
_Z25__device_stub__kernel_sumPiS_S_i: # @_Z25__device_stub__kernel_sumPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kernel_sumPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__kernel_sumPiS_S_i, .Lfunc_end2-_Z25__device_stub__kernel_sumPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_sumPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter n:"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nHost A:\n"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\t"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nHost B:\n"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nSequential processing result:\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nParallel Execution:\nExpected\tActual\n\n"
.size .L.str.5, 39
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\t\t"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nSequential time:"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nParallel time:"
.size .L.str.9, 16
.type _Z10kernel_sumPiS_S_i,@object # @_Z10kernel_sumPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10kernel_sumPiS_S_i
.p2align 3, 0x0
_Z10kernel_sumPiS_S_i:
.quad _Z25__device_stub__kernel_sumPiS_S_i
.size _Z10kernel_sumPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_sumPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_sumPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym _Z10kernel_sumPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
//execution time: 16.612064 ms
#define n 1024
#define block_size 32
__global__ void mul_matrix(int *a, int *b, int *c){
int my_x, my_y, i,j;
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
my_y = blockIdx.y*blockDim.y + threadIdx.y;
my_x = blockIdx.x*blockDim.x + threadIdx.x;
int local_c;
__shared__ int A_s[32][32];
__shared__ int B_s[32][32];
for (i=0;i<n/block_size;i++)
{
A_s[row][col] = a[my_x*n + (i*blockDim.x + col)];
B_s[row][col] = b[(i*blockDim.y + row)*n + my_y];
__syncthreads();
for(j=0;j<block_size;j++)
local_c += A_s[row][j]*B_s[j][col];
__syncthreads();
}
c[my_x*n+my_y] = local_c;
}
int main(){
int i;
float time;
cudaEvent_t start, stop;
// row major order
// a(i,j) = a[i*1024+j];
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for (i=0; i<n*n; i++){
a[i]=1;
b[i]=2;
c[i]=0;
}
int *gpu_a, *gpu_b, *gpu_c;
cudaMalloc((void**)&gpu_a, sizeof(int)*n*n);
cudaMalloc((void**)&gpu_b, sizeof(int)*n*n);
cudaMalloc((void**)&gpu_c, sizeof(int)*n*n);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(gpu_a, a, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, b, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaEventRecord(start,0);
mul_matrix<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(c, gpu_c, sizeof(int)*n*n, cudaMemcpyDeviceToHost);
//for (i=0; i<n*n; i++)
//printf("%d ", c[i]);
printf("%f ", time);
free(a);
free(b);
free(c);
cudaFree(gpu_a);
cudaFree(gpu_b);
cudaFree(gpu_c);
return 0;
} | code for sm_80
Function : _Z10mul_matrixPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0050*/ S2R R19, SR_CTAID.Y ; /* 0x0000000000137919 */
/* 0x000ea80000002600 */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000ee20000002100 */
/*0070*/ IMAD R3, R17, c[0x0][0x0], RZ ; /* 0x0000000011037a24 */
/* 0x001fe200078e02ff */
/*0080*/ LEA R18, R0, R0, 0xa ; /* 0x0000000000127211 */
/* 0x002fc800078e50ff */
/*0090*/ SHF.L.U32 R3, R3, 0xa, RZ ; /* 0x0000000a03037819 */
/* 0x000fe400000006ff */
/*00a0*/ SHF.L.U32 R23, R0, 0x7, RZ ; /* 0x0000000700177819 */
/* 0x000fe200000006ff */
/*00b0*/ IMAD R18, R19, c[0x0][0x4], R18 ; /* 0x0000010013127a24 */
/* 0x004fc600078e0212 */
/*00c0*/ LEA R21, R2.reuse, R23, 0x2 ; /* 0x0000001702157211 */
/* 0x048fe200078e10ff */
/*00d0*/ IMAD R20, R2, 0x401, R3 ; /* 0x0000040102147824 */
/* 0x000fe400078e0203 */
/*00e0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*00f0*/ IMAD.WIDE.U32 R4, R20, R3, c[0x0][0x160] ; /* 0x0000580014047625 */
/* 0x000fc800078e0003 */
/*0100*/ IMAD.WIDE.U32 R24, R18, R3, c[0x0][0x168] ; /* 0x00005a0012187625 */
/* 0x000fe400078e0003 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ee2000c1e1900 */
/*0130*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fe40007ffe0ff */
/*0140*/ IADD3 R20, R20, c[0x0][0x0], RZ ; /* 0x0000000014147a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.NE.AND P0, PT, R16, 0x20, PT ; /* 0x000000201000780c */
/* 0x000fe20003f05270 */
/*0160*/ STS [R21], R4 ; /* 0x0000000415007388 */
/* 0x004fe80000000800 */
/*0170*/ STS [R21+0x1000], R24 ; /* 0x0010001815007388 */
/* 0x008fe80000000800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ LDS R6, [R2.X4+0x1000] ; /* 0x0010000002067984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS.128 R8, [R23] ; /* 0x0000000017087984 */
/* 0x000e280000000c00 */
/*01b0*/ LDS R28, [R2.X4+0x1080] ; /* 0x00108000021c7984 */
/* 0x000e680000004800 */
/*01c0*/ LDS R29, [R2.X4+0x1100] ; /* 0x00110000021d7984 */
/* 0x000ea80000004800 */
/*01d0*/ LDS R26, [R2.X4+0x1180] ; /* 0x00118000021a7984 */
/* 0x000ee80000004800 */
/*01e0*/ LDS R27, [R2.X4+0x1200] ; /* 0x00120000021b7984 */
/* 0x000fe80000004800 */
/*01f0*/ LDS.128 R12, [R23+0x10] ; /* 0x00001000170c7984 */
/* 0x000f280000000c00 */
/*0200*/ LDS R22, [R2.X4+0x1280] ; /* 0x0012800002167984 */
/* 0x000f680000004800 */
/*0210*/ LDS R25, [R2.X4+0x1300] ; /* 0x0013000002197984 */
/* 0x000f680000004800 */
/*0220*/ LDS R24, [R2.X4+0x1380] ; /* 0x0013800002187984 */
/* 0x000f620000004800 */
/*0230*/ IMAD R6, R6, R8, R7 ; /* 0x0000000806067224 */
/* 0x001fc600078e0207 */
/*0240*/ LDS R8, [R2.X4+0x1480] ; /* 0x0014800002087984 */
/* 0x000fe20000004800 */
/*0250*/ IMAD R9, R28, R9, R6 ; /* 0x000000091c097224 */
/* 0x002fc600078e0206 */
/*0260*/ LDS.128 R4, [R23+0x20] ; /* 0x0000200017047984 */
/* 0x000fe20000000c00 */
/*0270*/ IMAD R10, R29, R10, R9 ; /* 0x0000000a1d0a7224 */
/* 0x004fc600078e0209 */
/*0280*/ LDS R9, [R2.X4+0x1400] ; /* 0x0014000002097984 */
/* 0x000e220000004800 */
/*0290*/ IMAD R10, R26, R11, R10 ; /* 0x0000000b1a0a7224 */
/* 0x008fc600078e020a */
/*02a0*/ LDS R11, [R2.X4+0x1500] ; /* 0x00150000020b7984 */
/* 0x000e680000004800 */
/*02b0*/ LDS R29, [R2.X4+0x1800] ; /* 0x00180000021d7984 */
/* 0x000fe20000004800 */
/*02c0*/ IMAD R10, R27, R12, R10 ; /* 0x0000000c1b0a7224 */
/* 0x010fc600078e020a */
/*02d0*/ LDS R27, [R2.X4+0x1700] ; /* 0x00170000021b7984 */
/* 0x000fe20000004800 */
/*02e0*/ IMAD R10, R22, R13, R10 ; /* 0x0000000d160a7224 */
/* 0x020fc600078e020a */
/*02f0*/ LDS R22, [R2.X4+0x1580] ; /* 0x0015800002167984 */
/* 0x000ea20000004800 */
/*0300*/ IMAD R10, R25, R14, R10 ; /* 0x0000000e190a7224 */
/* 0x000fc600078e020a */
/*0310*/ LDS R25, [R2.X4+0x1600] ; /* 0x0016000002197984 */
/* 0x000fe20000004800 */
/*0320*/ IMAD R10, R24, R15, R10 ; /* 0x0000000f180a7224 */
/* 0x000fc600078e020a */
/*0330*/ LDS.128 R12, [R23+0x30] ; /* 0x00003000170c7984 */
/* 0x000ee80000000c00 */
/*0340*/ LDS R24, [R2.X4+0x1680] ; /* 0x0016800002187984 */
/* 0x000f280000004800 */
/*0350*/ LDS R26, [R2.X4+0x1880] ; /* 0x00188000021a7984 */
/* 0x000fe80000004800 */
/*0360*/ LDS R28, [R2.X4+0x1a80] ; /* 0x001a8000021c7984 */
/* 0x000fe20000004800 */
/*0370*/ IMAD R9, R9, R4, R10 ; /* 0x0000000409097224 */
/* 0x001fc600078e020a */
/*0380*/ LDS R4, [R2.X4+0x1780] ; /* 0x0017800002047984 */
/* 0x000e220000004800 */
/*0390*/ IMAD R5, R8, R5, R9 ; /* 0x0000000508057224 */
/* 0x000fc800078e0209 */
/*03a0*/ IMAD R5, R11, R6, R5 ; /* 0x000000060b057224 */
/* 0x002fe400078e0205 */
/*03b0*/ LDS.128 R8, [R23+0x40] ; /* 0x0000400017087984 */
/* 0x000e640000000c00 */
/*03c0*/ IMAD R5, R22, R7, R5 ; /* 0x0000000716057224 */
/* 0x004fe400078e0205 */
/*03d0*/ LDS R22, [R2.X4+0x1900] ; /* 0x0019000002167984 */
/* 0x000ea40000004800 */
/*03e0*/ IMAD R5, R25, R12, R5 ; /* 0x0000000c19057224 */
/* 0x008fe400078e0205 */
/*03f0*/ LDS R25, [R2.X4+0x1b00] ; /* 0x001b000002197984 */
/* 0x000fe40000004800 */
/*0400*/ IMAD R5, R24, R13, R5 ; /* 0x0000000d18057224 */
/* 0x010fc400078e0205 */
/*0410*/ LDS R24, [R2.X4+0x1980] ; /* 0x0019800002187984 */
/* 0x000ee40000004800 */
/*0420*/ IMAD R5, R27, R14, R5 ; /* 0x0000000e1b057224 */
/* 0x000fe400078e0205 */
/*0430*/ LDS R27, [R2.X4+0x1a00] ; /* 0x001a0000021b7984 */
/* 0x000fe40000004800 */
/*0440*/ IMAD R15, R4, R15, R5 ; /* 0x0000000f040f7224 */
/* 0x001fe400078e0205 */
/*0450*/ LDS.128 R4, [R23+0x50] ; /* 0x0000500017047984 */
/* 0x000e240000000c00 */
/*0460*/ IMAD R15, R29, R8, R15 ; /* 0x000000081d0f7224 */
/* 0x002fc400078e020f */
/*0470*/ LDS R8, [R2.X4+0x1b80] ; /* 0x001b800002087984 */
/* 0x000e640000004800 */
/*0480*/ IMAD R9, R26, R9, R15 ; /* 0x000000091a097224 */
/* 0x000fe400078e020f */
/*0490*/ LDS.128 R12, [R23+0x60] ; /* 0x00006000170c7984 */
/* 0x000fe40000000c00 */
/*04a0*/ IMAD R10, R22, R10, R9 ; /* 0x0000000a160a7224 */
/* 0x004fe400078e0209 */
/*04b0*/ LDS R9, [R2.X4+0x1c00] ; /* 0x001c000002097984 */
/* 0x000ea80000004800 */
/*04c0*/ LDS R22, [R2.X4+0x1d80] ; /* 0x001d800002167984 */
/* 0x000fe20000004800 */
/*04d0*/ IMAD R10, R24, R11, R10 ; /* 0x0000000b180a7224 */
/* 0x008fc600078e020a */
/*04e0*/ LDS R11, [R2.X4+0x1d00] ; /* 0x001d0000020b7984 */
/* 0x000fe20000004800 */
/*04f0*/ IMAD R4, R27, R4, R10 ; /* 0x000000041b047224 */
/* 0x001fc600078e020a */
/*0500*/ LDS R10, [R2.X4+0x1c80] ; /* 0x001c8000020a7984 */
/* 0x000e220000004800 */
/*0510*/ IMAD R4, R28, R5, R4 ; /* 0x000000051c047224 */
/* 0x000fc600078e0204 */
/*0520*/ LDS R27, [R2.X4+0x1e00] ; /* 0x001e0000021b7984 */
/* 0x000fe20000004800 */
/*0530*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fc600078e0204 */
/*0540*/ LDS R25, [R2.X4+0x1f00] ; /* 0x001f000002197984 */
/* 0x000fe20000004800 */
/*0550*/ IMAD R24, R8, R7, R4 ; /* 0x0000000708187224 */
/* 0x002fc600078e0204 */
/*0560*/ LDS.128 R4, [R23+0x70] ; /* 0x0000700017047984 */
/* 0x000e620000000c00 */
/*0570*/ IMAD R9, R9, R12, R24 ; /* 0x0000000c09097224 */
/* 0x004fc600078e0218 */
/*0580*/ LDS R8, [R2.X4+0x1e80] ; /* 0x001e800002087984 */
/* 0x000ea80000004800 */
/*0590*/ LDS R12, [R2.X4+0x1f80] ; /* 0x001f8000020c7984 */
/* 0x000ee20000004800 */
/*05a0*/ IMAD R9, R10, R13, R9 ; /* 0x0000000d0a097224 */
/* 0x001fc800078e0209 */
/*05b0*/ IMAD R9, R11, R14, R9 ; /* 0x0000000e0b097224 */
/* 0x000fc800078e0209 */
/*05c0*/ IMAD R9, R22, R15, R9 ; /* 0x0000000f16097224 */
/* 0x000fc800078e0209 */
/*05d0*/ IMAD R4, R27, R4, R9 ; /* 0x000000041b047224 */
/* 0x002fc800078e0209 */
/*05e0*/ IMAD R4, R8, R5, R4 ; /* 0x0000000508047224 */
/* 0x004fe200078e0204 */
/*05f0*/ MOV R5, c[0x0][0x4] ; /* 0x0000010000057a02 */
/* 0x000fc60000000f00 */
/*0600*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fe200078e0204 */
/*0610*/ LEA R18, R5, R18, 0xa ; /* 0x0000001205127211 */
/* 0x000fc600078e50ff */
/*0620*/ IMAD R7, R12, R7, R4 ; /* 0x000000070c077224 */
/* 0x008fe200078e0204 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ @P0 BRA 0xe0 ; /* 0xfffffa9000000947 */
/* 0x000fea000383ffff */
/*0650*/ IMAD R2, R17, c[0x0][0x0], R2 ; /* 0x0000000011027a24 */
/* 0x000fe400078e0202 */
/*0660*/ IMAD R19, R19, c[0x0][0x4], R0 ; /* 0x0000010013137a24 */
/* 0x000fca00078e0200 */
/*0670*/ LEA R2, R2, R19, 0xa ; /* 0x0000001302027211 */
/* 0x000fca00078e50ff */
/*0680*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0690*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
//execution time: 16.612064 ms
#define n 1024
#define block_size 32
__global__ void mul_matrix(int *a, int *b, int *c){
int my_x, my_y, i,j;
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
my_y = blockIdx.y*blockDim.y + threadIdx.y;
my_x = blockIdx.x*blockDim.x + threadIdx.x;
int local_c;
__shared__ int A_s[32][32];
__shared__ int B_s[32][32];
for (i=0;i<n/block_size;i++)
{
A_s[row][col] = a[my_x*n + (i*blockDim.x + col)];
B_s[row][col] = b[(i*blockDim.y + row)*n + my_y];
__syncthreads();
for(j=0;j<block_size;j++)
local_c += A_s[row][j]*B_s[j][col];
__syncthreads();
}
c[my_x*n+my_y] = local_c;
}
int main(){
int i;
float time;
cudaEvent_t start, stop;
// row major order
// a(i,j) = a[i*1024+j];
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for (i=0; i<n*n; i++){
a[i]=1;
b[i]=2;
c[i]=0;
}
int *gpu_a, *gpu_b, *gpu_c;
cudaMalloc((void**)&gpu_a, sizeof(int)*n*n);
cudaMalloc((void**)&gpu_b, sizeof(int)*n*n);
cudaMalloc((void**)&gpu_c, sizeof(int)*n*n);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(gpu_a, a, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, b, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaEventRecord(start,0);
mul_matrix<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(c, gpu_c, sizeof(int)*n*n, cudaMemcpyDeviceToHost);
//for (i=0; i<n*n; i++)
//printf("%d ", c[i]);
printf("%f ", time);
free(a);
free(b);
free(c);
cudaFree(gpu_a);
cudaFree(gpu_b);
cudaFree(gpu_c);
return 0;
} | .file "tmpxft_00181cb2_00000000-6_phw6_1a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_
.type _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_, @function
_Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mul_matrixPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_, .-_Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_
.globl _Z10mul_matrixPiS_S_
.type _Z10mul_matrixPiS_S_, @function
_Z10mul_matrixPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10mul_matrixPiS_S_, .-_Z10mul_matrixPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %eax
.L12:
movl $1, (%r12,%rax)
movl $2, 0(%rbp,%rax)
movl $0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10mul_matrixPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mul_matrixPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
//execution time: 16.612064 ms
#define n 1024
#define block_size 32
__global__ void mul_matrix(int *a, int *b, int *c){
int my_x, my_y, i,j;
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
my_y = blockIdx.y*blockDim.y + threadIdx.y;
my_x = blockIdx.x*blockDim.x + threadIdx.x;
int local_c;
__shared__ int A_s[32][32];
__shared__ int B_s[32][32];
for (i=0;i<n/block_size;i++)
{
A_s[row][col] = a[my_x*n + (i*blockDim.x + col)];
B_s[row][col] = b[(i*blockDim.y + row)*n + my_y];
__syncthreads();
for(j=0;j<block_size;j++)
local_c += A_s[row][j]*B_s[j][col];
__syncthreads();
}
c[my_x*n+my_y] = local_c;
}
int main(){
int i;
float time;
cudaEvent_t start, stop;
// row major order
// a(i,j) = a[i*1024+j];
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for (i=0; i<n*n; i++){
a[i]=1;
b[i]=2;
c[i]=0;
}
int *gpu_a, *gpu_b, *gpu_c;
cudaMalloc((void**)&gpu_a, sizeof(int)*n*n);
cudaMalloc((void**)&gpu_b, sizeof(int)*n*n);
cudaMalloc((void**)&gpu_c, sizeof(int)*n*n);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(gpu_a, a, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, b, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaEventRecord(start,0);
mul_matrix<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(c, gpu_c, sizeof(int)*n*n, cudaMemcpyDeviceToHost);
//for (i=0; i<n*n; i++)
//printf("%d ", c[i]);
printf("%f ", time);
free(a);
free(b);
free(c);
cudaFree(gpu_a);
cudaFree(gpu_b);
cudaFree(gpu_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
//execution time: 16.612064 ms
#define n 1024
#define block_size 32
__global__ void mul_matrix(int *a, int *b, int *c){
int my_x, my_y, i,j;
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
my_y = blockIdx.y*blockDim.y + threadIdx.y;
my_x = blockIdx.x*blockDim.x + threadIdx.x;
int local_c;
__shared__ int A_s[32][32];
__shared__ int B_s[32][32];
for (i=0;i<n/block_size;i++)
{
A_s[row][col] = a[my_x*n + (i*blockDim.x + col)];
B_s[row][col] = b[(i*blockDim.y + row)*n + my_y];
__syncthreads();
for(j=0;j<block_size;j++)
local_c += A_s[row][j]*B_s[j][col];
__syncthreads();
}
c[my_x*n+my_y] = local_c;
}
int main(){
int i;
float time;
hipEvent_t start, stop;
// row major order
// a(i,j) = a[i*1024+j];
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for (i=0; i<n*n; i++){
a[i]=1;
b[i]=2;
c[i]=0;
}
int *gpu_a, *gpu_b, *gpu_c;
hipMalloc((void**)&gpu_a, sizeof(int)*n*n);
hipMalloc((void**)&gpu_b, sizeof(int)*n*n);
hipMalloc((void**)&gpu_c, sizeof(int)*n*n);
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(gpu_a, a, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, b, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipEventRecord(start,0);
mul_matrix<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(c, gpu_c, sizeof(int)*n*n, hipMemcpyDeviceToHost);
//for (i=0; i<n*n; i++)
//printf("%d ", c[i]);
printf("%f ", time);
free(a);
free(b);
free(c);
hipFree(gpu_a);
hipFree(gpu_b);
hipFree(gpu_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
//execution time: 16.612064 ms
#define n 1024
#define block_size 32
__global__ void mul_matrix(int *a, int *b, int *c){
int my_x, my_y, i,j;
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
my_y = blockIdx.y*blockDim.y + threadIdx.y;
my_x = blockIdx.x*blockDim.x + threadIdx.x;
int local_c;
__shared__ int A_s[32][32];
__shared__ int B_s[32][32];
for (i=0;i<n/block_size;i++)
{
A_s[row][col] = a[my_x*n + (i*blockDim.x + col)];
B_s[row][col] = b[(i*blockDim.y + row)*n + my_y];
__syncthreads();
for(j=0;j<block_size;j++)
local_c += A_s[row][j]*B_s[j][col];
__syncthreads();
}
c[my_x*n+my_y] = local_c;
}
int main(){
int i;
float time;
hipEvent_t start, stop;
// row major order
// a(i,j) = a[i*1024+j];
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for (i=0; i<n*n; i++){
a[i]=1;
b[i]=2;
c[i]=0;
}
int *gpu_a, *gpu_b, *gpu_c;
hipMalloc((void**)&gpu_a, sizeof(int)*n*n);
hipMalloc((void**)&gpu_b, sizeof(int)*n*n);
hipMalloc((void**)&gpu_c, sizeof(int)*n*n);
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(gpu_a, a, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, b, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipEventRecord(start,0);
mul_matrix<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(c, gpu_c, sizeof(int)*n*n, hipMemcpyDeviceToHost);
//for (i=0; i<n*n; i++)
//printf("%d ", c[i]);
printf("%f ", time);
free(a);
free(b);
free(c);
hipFree(gpu_a);
hipFree(gpu_b);
hipFree(gpu_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mul_matrixPiS_S_
.globl _Z10mul_matrixPiS_S_
.p2align 8
.type _Z10mul_matrixPiS_S_,@function
_Z10mul_matrixPiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v4, 2, v3
v_lshlrev_b32_e32 v8, 7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v9, 0x1000, v4
v_add_nc_u32_e32 v10, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, v9, v8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
v_lshl_or_b32 v5, v1, 10, v3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
v_mad_u64_u32 v[12:13], null, s8, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[13:14], null, s8, s2, v[5:6]
v_mov_b32_e32 v14, v7
s_mov_b32 s9, 0
v_lshl_add_u32 v6, v12, 10, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[13:14]
v_lshlrev_b64 v[14:15], 2, v[6:7]
v_mov_b32_e32 v6, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
global_load_b32 v3, v[12:13], off
global_load_b32 v12, v[14:15], off
s_waitcnt vmcnt(1)
ds_store_b32 v10, v3
s_waitcnt vmcnt(0)
ds_store_b32 v11, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v12, v2 :: v_dual_add_nc_u32 v3, s9, v8
s_add_i32 s9, s9, 4
ds_load_b32 v13, v6
ds_load_b32 v14, v3
v_add_nc_u32_e32 v6, 0x80, v6
s_cmpk_lg_i32 s9, 0x80
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v13, v14, v[12:13]
s_cbranch_scc1 .LBB0_2
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 32
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v1, 10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mul_matrixPiS_S_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mul_matrixPiS_S_, .Lfunc_end0-_Z10mul_matrixPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mul_matrixPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mul_matrixPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
//execution time: 16.612064 ms
#define n 1024
#define block_size 32
__global__ void mul_matrix(int *a, int *b, int *c){
int my_x, my_y, i,j;
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
my_y = blockIdx.y*blockDim.y + threadIdx.y;
my_x = blockIdx.x*blockDim.x + threadIdx.x;
int local_c;
__shared__ int A_s[32][32];
__shared__ int B_s[32][32];
for (i=0;i<n/block_size;i++)
{
A_s[row][col] = a[my_x*n + (i*blockDim.x + col)];
B_s[row][col] = b[(i*blockDim.y + row)*n + my_y];
__syncthreads();
for(j=0;j<block_size;j++)
local_c += A_s[row][j]*B_s[j][col];
__syncthreads();
}
c[my_x*n+my_y] = local_c;
}
int main(){
int i;
float time;
hipEvent_t start, stop;
// row major order
// a(i,j) = a[i*1024+j];
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for (i=0; i<n*n; i++){
a[i]=1;
b[i]=2;
c[i]=0;
}
int *gpu_a, *gpu_b, *gpu_c;
hipMalloc((void**)&gpu_a, sizeof(int)*n*n);
hipMalloc((void**)&gpu_b, sizeof(int)*n*n);
hipMalloc((void**)&gpu_c, sizeof(int)*n*n);
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(gpu_a, a, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, b, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipEventRecord(start,0);
mul_matrix<<<dimGrid, dimBlock>>>(gpu_a, gpu_b, gpu_c);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(c, gpu_c, sizeof(int)*n*n, hipMemcpyDeviceToHost);
//for (i=0; i<n*n; i++)
//printf("%d ", c[i]);
printf("%f ", time);
free(a);
free(b);
free(c);
hipFree(gpu_a);
hipFree(gpu_b);
hipFree(gpu_c);
return 0;
} | .text
.file "phw6_1a.hip"
.globl _Z25__device_stub__mul_matrixPiS_S_ # -- Begin function _Z25__device_stub__mul_matrixPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__mul_matrixPiS_S_,@function
_Z25__device_stub__mul_matrixPiS_S_: # @_Z25__device_stub__mul_matrixPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mul_matrixPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__mul_matrixPiS_S_, .Lfunc_end0-_Z25__device_stub__mul_matrixPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r12,4)
movl $2, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10mul_matrixPiS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mul_matrixPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mul_matrixPiS_S_,@object # @_Z10mul_matrixPiS_S_
.section .rodata,"a",@progbits
.globl _Z10mul_matrixPiS_S_
.p2align 3, 0x0
_Z10mul_matrixPiS_S_:
.quad _Z25__device_stub__mul_matrixPiS_S_
.size _Z10mul_matrixPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10mul_matrixPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mul_matrixPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mul_matrixPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10mul_matrixPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0050*/ S2R R19, SR_CTAID.Y ; /* 0x0000000000137919 */
/* 0x000ea80000002600 */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000ee20000002100 */
/*0070*/ IMAD R3, R17, c[0x0][0x0], RZ ; /* 0x0000000011037a24 */
/* 0x001fe200078e02ff */
/*0080*/ LEA R18, R0, R0, 0xa ; /* 0x0000000000127211 */
/* 0x002fc800078e50ff */
/*0090*/ SHF.L.U32 R3, R3, 0xa, RZ ; /* 0x0000000a03037819 */
/* 0x000fe400000006ff */
/*00a0*/ SHF.L.U32 R23, R0, 0x7, RZ ; /* 0x0000000700177819 */
/* 0x000fe200000006ff */
/*00b0*/ IMAD R18, R19, c[0x0][0x4], R18 ; /* 0x0000010013127a24 */
/* 0x004fc600078e0212 */
/*00c0*/ LEA R21, R2.reuse, R23, 0x2 ; /* 0x0000001702157211 */
/* 0x048fe200078e10ff */
/*00d0*/ IMAD R20, R2, 0x401, R3 ; /* 0x0000040102147824 */
/* 0x000fe400078e0203 */
/*00e0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*00f0*/ IMAD.WIDE.U32 R4, R20, R3, c[0x0][0x160] ; /* 0x0000580014047625 */
/* 0x000fc800078e0003 */
/*0100*/ IMAD.WIDE.U32 R24, R18, R3, c[0x0][0x168] ; /* 0x00005a0012187625 */
/* 0x000fe400078e0003 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ee2000c1e1900 */
/*0130*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fe40007ffe0ff */
/*0140*/ IADD3 R20, R20, c[0x0][0x0], RZ ; /* 0x0000000014147a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.NE.AND P0, PT, R16, 0x20, PT ; /* 0x000000201000780c */
/* 0x000fe20003f05270 */
/*0160*/ STS [R21], R4 ; /* 0x0000000415007388 */
/* 0x004fe80000000800 */
/*0170*/ STS [R21+0x1000], R24 ; /* 0x0010001815007388 */
/* 0x008fe80000000800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ LDS R6, [R2.X4+0x1000] ; /* 0x0010000002067984 */
/* 0x000fe80000004800 */
/*01a0*/ LDS.128 R8, [R23] ; /* 0x0000000017087984 */
/* 0x000e280000000c00 */
/*01b0*/ LDS R28, [R2.X4+0x1080] ; /* 0x00108000021c7984 */
/* 0x000e680000004800 */
/*01c0*/ LDS R29, [R2.X4+0x1100] ; /* 0x00110000021d7984 */
/* 0x000ea80000004800 */
/*01d0*/ LDS R26, [R2.X4+0x1180] ; /* 0x00118000021a7984 */
/* 0x000ee80000004800 */
/*01e0*/ LDS R27, [R2.X4+0x1200] ; /* 0x00120000021b7984 */
/* 0x000fe80000004800 */
/*01f0*/ LDS.128 R12, [R23+0x10] ; /* 0x00001000170c7984 */
/* 0x000f280000000c00 */
/*0200*/ LDS R22, [R2.X4+0x1280] ; /* 0x0012800002167984 */
/* 0x000f680000004800 */
/*0210*/ LDS R25, [R2.X4+0x1300] ; /* 0x0013000002197984 */
/* 0x000f680000004800 */
/*0220*/ LDS R24, [R2.X4+0x1380] ; /* 0x0013800002187984 */
/* 0x000f620000004800 */
/*0230*/ IMAD R6, R6, R8, R7 ; /* 0x0000000806067224 */
/* 0x001fc600078e0207 */
/*0240*/ LDS R8, [R2.X4+0x1480] ; /* 0x0014800002087984 */
/* 0x000fe20000004800 */
/*0250*/ IMAD R9, R28, R9, R6 ; /* 0x000000091c097224 */
/* 0x002fc600078e0206 */
/*0260*/ LDS.128 R4, [R23+0x20] ; /* 0x0000200017047984 */
/* 0x000fe20000000c00 */
/*0270*/ IMAD R10, R29, R10, R9 ; /* 0x0000000a1d0a7224 */
/* 0x004fc600078e0209 */
/*0280*/ LDS R9, [R2.X4+0x1400] ; /* 0x0014000002097984 */
/* 0x000e220000004800 */
/*0290*/ IMAD R10, R26, R11, R10 ; /* 0x0000000b1a0a7224 */
/* 0x008fc600078e020a */
/*02a0*/ LDS R11, [R2.X4+0x1500] ; /* 0x00150000020b7984 */
/* 0x000e680000004800 */
/*02b0*/ LDS R29, [R2.X4+0x1800] ; /* 0x00180000021d7984 */
/* 0x000fe20000004800 */
/*02c0*/ IMAD R10, R27, R12, R10 ; /* 0x0000000c1b0a7224 */
/* 0x010fc600078e020a */
/*02d0*/ LDS R27, [R2.X4+0x1700] ; /* 0x00170000021b7984 */
/* 0x000fe20000004800 */
/*02e0*/ IMAD R10, R22, R13, R10 ; /* 0x0000000d160a7224 */
/* 0x020fc600078e020a */
/*02f0*/ LDS R22, [R2.X4+0x1580] ; /* 0x0015800002167984 */
/* 0x000ea20000004800 */
/*0300*/ IMAD R10, R25, R14, R10 ; /* 0x0000000e190a7224 */
/* 0x000fc600078e020a */
/*0310*/ LDS R25, [R2.X4+0x1600] ; /* 0x0016000002197984 */
/* 0x000fe20000004800 */
/*0320*/ IMAD R10, R24, R15, R10 ; /* 0x0000000f180a7224 */
/* 0x000fc600078e020a */
/*0330*/ LDS.128 R12, [R23+0x30] ; /* 0x00003000170c7984 */
/* 0x000ee80000000c00 */
/*0340*/ LDS R24, [R2.X4+0x1680] ; /* 0x0016800002187984 */
/* 0x000f280000004800 */
/*0350*/ LDS R26, [R2.X4+0x1880] ; /* 0x00188000021a7984 */
/* 0x000fe80000004800 */
/*0360*/ LDS R28, [R2.X4+0x1a80] ; /* 0x001a8000021c7984 */
/* 0x000fe20000004800 */
/*0370*/ IMAD R9, R9, R4, R10 ; /* 0x0000000409097224 */
/* 0x001fc600078e020a */
/*0380*/ LDS R4, [R2.X4+0x1780] ; /* 0x0017800002047984 */
/* 0x000e220000004800 */
/*0390*/ IMAD R5, R8, R5, R9 ; /* 0x0000000508057224 */
/* 0x000fc800078e0209 */
/*03a0*/ IMAD R5, R11, R6, R5 ; /* 0x000000060b057224 */
/* 0x002fe400078e0205 */
/*03b0*/ LDS.128 R8, [R23+0x40] ; /* 0x0000400017087984 */
/* 0x000e640000000c00 */
/*03c0*/ IMAD R5, R22, R7, R5 ; /* 0x0000000716057224 */
/* 0x004fe400078e0205 */
/*03d0*/ LDS R22, [R2.X4+0x1900] ; /* 0x0019000002167984 */
/* 0x000ea40000004800 */
/*03e0*/ IMAD R5, R25, R12, R5 ; /* 0x0000000c19057224 */
/* 0x008fe400078e0205 */
/*03f0*/ LDS R25, [R2.X4+0x1b00] ; /* 0x001b000002197984 */
/* 0x000fe40000004800 */
/*0400*/ IMAD R5, R24, R13, R5 ; /* 0x0000000d18057224 */
/* 0x010fc400078e0205 */
/*0410*/ LDS R24, [R2.X4+0x1980] ; /* 0x0019800002187984 */
/* 0x000ee40000004800 */
/*0420*/ IMAD R5, R27, R14, R5 ; /* 0x0000000e1b057224 */
/* 0x000fe400078e0205 */
/*0430*/ LDS R27, [R2.X4+0x1a00] ; /* 0x001a0000021b7984 */
/* 0x000fe40000004800 */
/*0440*/ IMAD R15, R4, R15, R5 ; /* 0x0000000f040f7224 */
/* 0x001fe400078e0205 */
/*0450*/ LDS.128 R4, [R23+0x50] ; /* 0x0000500017047984 */
/* 0x000e240000000c00 */
/*0460*/ IMAD R15, R29, R8, R15 ; /* 0x000000081d0f7224 */
/* 0x002fc400078e020f */
/*0470*/ LDS R8, [R2.X4+0x1b80] ; /* 0x001b800002087984 */
/* 0x000e640000004800 */
/*0480*/ IMAD R9, R26, R9, R15 ; /* 0x000000091a097224 */
/* 0x000fe400078e020f */
/*0490*/ LDS.128 R12, [R23+0x60] ; /* 0x00006000170c7984 */
/* 0x000fe40000000c00 */
/*04a0*/ IMAD R10, R22, R10, R9 ; /* 0x0000000a160a7224 */
/* 0x004fe400078e0209 */
/*04b0*/ LDS R9, [R2.X4+0x1c00] ; /* 0x001c000002097984 */
/* 0x000ea80000004800 */
/*04c0*/ LDS R22, [R2.X4+0x1d80] ; /* 0x001d800002167984 */
/* 0x000fe20000004800 */
/*04d0*/ IMAD R10, R24, R11, R10 ; /* 0x0000000b180a7224 */
/* 0x008fc600078e020a */
/*04e0*/ LDS R11, [R2.X4+0x1d00] ; /* 0x001d0000020b7984 */
/* 0x000fe20000004800 */
/*04f0*/ IMAD R4, R27, R4, R10 ; /* 0x000000041b047224 */
/* 0x001fc600078e020a */
/*0500*/ LDS R10, [R2.X4+0x1c80] ; /* 0x001c8000020a7984 */
/* 0x000e220000004800 */
/*0510*/ IMAD R4, R28, R5, R4 ; /* 0x000000051c047224 */
/* 0x000fc600078e0204 */
/*0520*/ LDS R27, [R2.X4+0x1e00] ; /* 0x001e0000021b7984 */
/* 0x000fe20000004800 */
/*0530*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fc600078e0204 */
/*0540*/ LDS R25, [R2.X4+0x1f00] ; /* 0x001f000002197984 */
/* 0x000fe20000004800 */
/*0550*/ IMAD R24, R8, R7, R4 ; /* 0x0000000708187224 */
/* 0x002fc600078e0204 */
/*0560*/ LDS.128 R4, [R23+0x70] ; /* 0x0000700017047984 */
/* 0x000e620000000c00 */
/*0570*/ IMAD R9, R9, R12, R24 ; /* 0x0000000c09097224 */
/* 0x004fc600078e0218 */
/*0580*/ LDS R8, [R2.X4+0x1e80] ; /* 0x001e800002087984 */
/* 0x000ea80000004800 */
/*0590*/ LDS R12, [R2.X4+0x1f80] ; /* 0x001f8000020c7984 */
/* 0x000ee20000004800 */
/*05a0*/ IMAD R9, R10, R13, R9 ; /* 0x0000000d0a097224 */
/* 0x001fc800078e0209 */
/*05b0*/ IMAD R9, R11, R14, R9 ; /* 0x0000000e0b097224 */
/* 0x000fc800078e0209 */
/*05c0*/ IMAD R9, R22, R15, R9 ; /* 0x0000000f16097224 */
/* 0x000fc800078e0209 */
/*05d0*/ IMAD R4, R27, R4, R9 ; /* 0x000000041b047224 */
/* 0x002fc800078e0209 */
/*05e0*/ IMAD R4, R8, R5, R4 ; /* 0x0000000508047224 */
/* 0x004fe200078e0204 */
/*05f0*/ MOV R5, c[0x0][0x4] ; /* 0x0000010000057a02 */
/* 0x000fc60000000f00 */
/*0600*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fe200078e0204 */
/*0610*/ LEA R18, R5, R18, 0xa ; /* 0x0000001205127211 */
/* 0x000fc600078e50ff */
/*0620*/ IMAD R7, R12, R7, R4 ; /* 0x000000070c077224 */
/* 0x008fe200078e0204 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ @P0 BRA 0xe0 ; /* 0xfffffa9000000947 */
/* 0x000fea000383ffff */
/*0650*/ IMAD R2, R17, c[0x0][0x0], R2 ; /* 0x0000000011027a24 */
/* 0x000fe400078e0202 */
/*0660*/ IMAD R19, R19, c[0x0][0x4], R0 ; /* 0x0000010013137a24 */
/* 0x000fca00078e0200 */
/*0670*/ LEA R2, R2, R19, 0xa ; /* 0x0000001302027211 */
/* 0x000fca00078e50ff */
/*0680*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0690*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mul_matrixPiS_S_
.globl _Z10mul_matrixPiS_S_
.p2align 8
.type _Z10mul_matrixPiS_S_,@function
_Z10mul_matrixPiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v4, 2, v3
v_lshlrev_b32_e32 v8, 7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v9, 0x1000, v4
v_add_nc_u32_e32 v10, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, v9, v8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
v_lshl_or_b32 v5, v1, 10, v3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
v_mad_u64_u32 v[12:13], null, s8, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[13:14], null, s8, s2, v[5:6]
v_mov_b32_e32 v14, v7
s_mov_b32 s9, 0
v_lshl_add_u32 v6, v12, 10, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[13:14]
v_lshlrev_b64 v[14:15], 2, v[6:7]
v_mov_b32_e32 v6, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
global_load_b32 v3, v[12:13], off
global_load_b32 v12, v[14:15], off
s_waitcnt vmcnt(1)
ds_store_b32 v10, v3
s_waitcnt vmcnt(0)
ds_store_b32 v11, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v12, v2 :: v_dual_add_nc_u32 v3, s9, v8
s_add_i32 s9, s9, 4
ds_load_b32 v13, v6
ds_load_b32 v14, v3
v_add_nc_u32_e32 v6, 0x80, v6
s_cmpk_lg_i32 s9, 0x80
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v13, v14, v[12:13]
s_cbranch_scc1 .LBB0_2
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 32
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v1, 10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mul_matrixPiS_S_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mul_matrixPiS_S_, .Lfunc_end0-_Z10mul_matrixPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mul_matrixPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mul_matrixPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00181cb2_00000000-6_phw6_1a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_
.type _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_, @function
_Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mul_matrixPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_, .-_Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_
.globl _Z10mul_matrixPiS_S_
.type _Z10mul_matrixPiS_S_, @function
_Z10mul_matrixPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10mul_matrixPiS_S_, .-_Z10mul_matrixPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %eax
.L12:
movl $1, (%r12,%rax)
movl $2, 0(%rbp,%rax)
movl $0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z10mul_matrixPiS_S_PiS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10mul_matrixPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mul_matrixPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "phw6_1a.hip"
.globl _Z25__device_stub__mul_matrixPiS_S_ # -- Begin function _Z25__device_stub__mul_matrixPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__mul_matrixPiS_S_,@function
_Z25__device_stub__mul_matrixPiS_S_: # @_Z25__device_stub__mul_matrixPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mul_matrixPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__mul_matrixPiS_S_, .Lfunc_end0-_Z25__device_stub__mul_matrixPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r12,4)
movl $2, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10mul_matrixPiS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mul_matrixPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mul_matrixPiS_S_,@object # @_Z10mul_matrixPiS_S_
.section .rodata,"a",@progbits
.globl _Z10mul_matrixPiS_S_
.p2align 3, 0x0
_Z10mul_matrixPiS_S_:
.quad _Z25__device_stub__mul_matrixPiS_S_
.size _Z10mul_matrixPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10mul_matrixPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mul_matrixPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mul_matrixPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void simpleKernel(int N, float *d_a, float *d_b){
// Convert thread and thread-block indices into array index
const int n = threadIdx.x + blockDim.x*blockIdx.x;
// If index is in [0,N-1] add entries
if(n<N)
d_a[N-1-n] = d_b[n];
}
int main(int argc,char **argv){
int N = 512; // size of array for this DEMO
// HOST array
float *h_a = (float*) calloc(N, sizeof(float));
float *h_b = (float*) calloc(N, sizeof(float));
// Allocate DEVICE array
float *d_a, *d_b;
cudaMalloc((void**) &d_a, N*sizeof(float));
cudaMalloc((void**) &d_b, N*sizeof(float));
dim3 dimBlock(512,1,1); // 512 threads per thread-block
dim3 dimGrid((N+511)/512, 1, 1); // Enough thread-blocks to cover N
// Init. HOST array
for(int n=0;n<N;++n){
h_b[n] = n;
}
cudaMemcpy(d_b, h_b, N*sizeof(float), cudaMemcpyDeviceToHost);
// Queue kernel on DEVICE
simpleKernel <<< dimGrid, dimBlock >>> (N, d_a, d_b);
// Transfer result from DEVICE to HOST
cudaMemcpy(h_a, d_a, N*sizeof(float), cudaMemcpyDeviceToHost);
// Print out result
for(int n=0;n<N;++n) printf("h_a[%d] = %f\n", n, h_a[n]);
} | code for sm_80
Function : _Z12simpleKerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fc800078e33ff */
/*00b0*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void simpleKernel(int N, float *d_a, float *d_b){
// Convert thread and thread-block indices into array index
const int n = threadIdx.x + blockDim.x*blockIdx.x;
// If index is in [0,N-1] add entries
if(n<N)
d_a[N-1-n] = d_b[n];
}
int main(int argc,char **argv){
int N = 512; // size of array for this DEMO
// HOST array
float *h_a = (float*) calloc(N, sizeof(float));
float *h_b = (float*) calloc(N, sizeof(float));
// Allocate DEVICE array
float *d_a, *d_b;
cudaMalloc((void**) &d_a, N*sizeof(float));
cudaMalloc((void**) &d_b, N*sizeof(float));
dim3 dimBlock(512,1,1); // 512 threads per thread-block
dim3 dimGrid((N+511)/512, 1, 1); // Enough thread-blocks to cover N
// Init. HOST array
for(int n=0;n<N;++n){
h_b[n] = n;
}
cudaMemcpy(d_b, h_b, N*sizeof(float), cudaMemcpyDeviceToHost);
// Queue kernel on DEVICE
simpleKernel <<< dimGrid, dimBlock >>> (N, d_a, d_b);
// Transfer result from DEVICE to HOST
cudaMemcpy(h_a, d_a, N*sizeof(float), cudaMemcpyDeviceToHost);
// Print out result
for(int n=0;n<N;++n) printf("h_a[%d] = %f\n", n, h_a[n]);
} | .file "tmpxft_00197be6_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12simpleKerneliPfS_iPfS_
.type _Z35__device_stub__Z12simpleKerneliPfS_iPfS_, @function
_Z35__device_stub__Z12simpleKerneliPfS_iPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12simpleKerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z12simpleKerneliPfS_iPfS_, .-_Z35__device_stub__Z12simpleKerneliPfS_iPfS_
.globl _Z12simpleKerneliPfS_
.type _Z12simpleKerneliPfS_, @function
_Z12simpleKerneliPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12simpleKerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12simpleKerneliPfS_, .-_Z12simpleKerneliPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h_a[%d] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $512, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $512, %edi
call calloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $512, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L12
movl $2, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $2048, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r12
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $512, %rbx
jne .L14
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $512, %edi
call _Z35__device_stub__Z12simpleKerneliPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12simpleKerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simpleKerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void simpleKernel(int N, float *d_a, float *d_b){
// Convert thread and thread-block indices into array index
const int n = threadIdx.x + blockDim.x*blockIdx.x;
// If index is in [0,N-1] add entries
if(n<N)
d_a[N-1-n] = d_b[n];
}
int main(int argc,char **argv){
int N = 512; // size of array for this DEMO
// HOST array
float *h_a = (float*) calloc(N, sizeof(float));
float *h_b = (float*) calloc(N, sizeof(float));
// Allocate DEVICE array
float *d_a, *d_b;
cudaMalloc((void**) &d_a, N*sizeof(float));
cudaMalloc((void**) &d_b, N*sizeof(float));
dim3 dimBlock(512,1,1); // 512 threads per thread-block
dim3 dimGrid((N+511)/512, 1, 1); // Enough thread-blocks to cover N
// Init. HOST array
for(int n=0;n<N;++n){
h_b[n] = n;
}
cudaMemcpy(d_b, h_b, N*sizeof(float), cudaMemcpyDeviceToHost);
// Queue kernel on DEVICE
simpleKernel <<< dimGrid, dimBlock >>> (N, d_a, d_b);
// Transfer result from DEVICE to HOST
cudaMemcpy(h_a, d_a, N*sizeof(float), cudaMemcpyDeviceToHost);
// Print out result
for(int n=0;n<N;++n) printf("h_a[%d] = %f\n", n, h_a[n]);
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void simpleKernel(int N, float *d_a, float *d_b){
// Convert thread and thread-block indices into array index
const int n = threadIdx.x + blockDim.x*blockIdx.x;
// If index is in [0,N-1] add entries
if(n<N)
d_a[N-1-n] = d_b[n];
}
int main(int argc,char **argv){
int N = 512; // size of array for this DEMO
// HOST array
float *h_a = (float*) calloc(N, sizeof(float));
float *h_b = (float*) calloc(N, sizeof(float));
// Allocate DEVICE array
float *d_a, *d_b;
hipMalloc((void**) &d_a, N*sizeof(float));
hipMalloc((void**) &d_b, N*sizeof(float));
dim3 dimBlock(512,1,1); // 512 threads per thread-block
dim3 dimGrid((N+511)/512, 1, 1); // Enough thread-blocks to cover N
// Init. HOST array
for(int n=0;n<N;++n){
h_b[n] = n;
}
hipMemcpy(d_b, h_b, N*sizeof(float), hipMemcpyDeviceToHost);
// Queue kernel on DEVICE
simpleKernel <<< dimGrid, dimBlock >>> (N, d_a, d_b);
// Transfer result from DEVICE to HOST
hipMemcpy(h_a, d_a, N*sizeof(float), hipMemcpyDeviceToHost);
// Print out result
for(int n=0;n<N;++n) printf("h_a[%d] = %f\n", n, h_a[n]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void simpleKernel(int N, float *d_a, float *d_b){
// Convert thread and thread-block indices into array index
const int n = threadIdx.x + blockDim.x*blockIdx.x;
// If index is in [0,N-1] add entries
if(n<N)
d_a[N-1-n] = d_b[n];
}
int main(int argc,char **argv){
int N = 512; // size of array for this DEMO
// HOST array
float *h_a = (float*) calloc(N, sizeof(float));
float *h_b = (float*) calloc(N, sizeof(float));
// Allocate DEVICE array
float *d_a, *d_b;
hipMalloc((void**) &d_a, N*sizeof(float));
hipMalloc((void**) &d_b, N*sizeof(float));
dim3 dimBlock(512,1,1); // 512 threads per thread-block
dim3 dimGrid((N+511)/512, 1, 1); // Enough thread-blocks to cover N
// Init. HOST array
for(int n=0;n<N;++n){
h_b[n] = n;
}
hipMemcpy(d_b, h_b, N*sizeof(float), hipMemcpyDeviceToHost);
// Queue kernel on DEVICE
simpleKernel <<< dimGrid, dimBlock >>> (N, d_a, d_b);
// Transfer result from DEVICE to HOST
hipMemcpy(h_a, d_a, N*sizeof(float), hipMemcpyDeviceToHost);
// Print out result
for(int n=0;n<N;++n) printf("h_a[%d] = %f\n", n, h_a[n]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12simpleKerneliPfS_
.globl _Z12simpleKerneliPfS_
.p2align 8
.type _Z12simpleKerneliPfS_,@function
_Z12simpleKerneliPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v0, v1, -1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simpleKerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12simpleKerneliPfS_, .Lfunc_end0-_Z12simpleKerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simpleKerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12simpleKerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void simpleKernel(int N, float *d_a, float *d_b){
// Convert thread and thread-block indices into array index
const int n = threadIdx.x + blockDim.x*blockIdx.x;
// If index is in [0,N-1] add entries
if(n<N)
d_a[N-1-n] = d_b[n];
}
int main(int argc,char **argv){
int N = 512; // size of array for this DEMO
// HOST array
float *h_a = (float*) calloc(N, sizeof(float));
float *h_b = (float*) calloc(N, sizeof(float));
// Allocate DEVICE array
float *d_a, *d_b;
hipMalloc((void**) &d_a, N*sizeof(float));
hipMalloc((void**) &d_b, N*sizeof(float));
dim3 dimBlock(512,1,1); // 512 threads per thread-block
dim3 dimGrid((N+511)/512, 1, 1); // Enough thread-blocks to cover N
// Init. HOST array
for(int n=0;n<N;++n){
h_b[n] = n;
}
hipMemcpy(d_b, h_b, N*sizeof(float), hipMemcpyDeviceToHost);
// Queue kernel on DEVICE
simpleKernel <<< dimGrid, dimBlock >>> (N, d_a, d_b);
// Transfer result from DEVICE to HOST
hipMemcpy(h_a, d_a, N*sizeof(float), hipMemcpyDeviceToHost);
// Print out result
for(int n=0;n<N;++n) printf("h_a[%d] = %f\n", n, h_a[n]);
} | .text
.file "simple.hip"
.globl _Z27__device_stub__simpleKerneliPfS_ # -- Begin function _Z27__device_stub__simpleKerneliPfS_
.p2align 4, 0x90
.type _Z27__device_stub__simpleKerneliPfS_,@function
_Z27__device_stub__simpleKerneliPfS_: # @_Z27__device_stub__simpleKerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12simpleKerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__simpleKerneliPfS_, .Lfunc_end0-_Z27__device_stub__simpleKerneliPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $512, %edi # imm = 0x200
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $512, %edi # imm = 0x200
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl $512, 12(%rsp) # imm = 0x200
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12simpleKerneliPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 24(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $512, %r14 # imm = 0x200
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simpleKerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12simpleKerneliPfS_,@object # @_Z12simpleKerneliPfS_
.section .rodata,"a",@progbits
.globl _Z12simpleKerneliPfS_
.p2align 3, 0x0
_Z12simpleKerneliPfS_:
.quad _Z27__device_stub__simpleKerneliPfS_
.size _Z12simpleKerneliPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_a[%d] = %f\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12simpleKerneliPfS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__simpleKerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12simpleKerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12simpleKerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fc800078e33ff */
/*00b0*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12simpleKerneliPfS_
.globl _Z12simpleKerneliPfS_
.p2align 8
.type _Z12simpleKerneliPfS_,@function
_Z12simpleKerneliPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v0, v1, -1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simpleKerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12simpleKerneliPfS_, .Lfunc_end0-_Z12simpleKerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simpleKerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12simpleKerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00197be6_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12simpleKerneliPfS_iPfS_
.type _Z35__device_stub__Z12simpleKerneliPfS_iPfS_, @function
_Z35__device_stub__Z12simpleKerneliPfS_iPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12simpleKerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z12simpleKerneliPfS_iPfS_, .-_Z35__device_stub__Z12simpleKerneliPfS_iPfS_
.globl _Z12simpleKerneliPfS_
.type _Z12simpleKerneliPfS_, @function
_Z12simpleKerneliPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12simpleKerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12simpleKerneliPfS_, .-_Z12simpleKerneliPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h_a[%d] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $512, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $512, %edi
call calloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $512, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L12
movl $2, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $2048, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r12
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $512, %rbx
jne .L14
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $512, %edi
call _Z35__device_stub__Z12simpleKerneliPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12simpleKerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simpleKerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple.hip"
.globl _Z27__device_stub__simpleKerneliPfS_ # -- Begin function _Z27__device_stub__simpleKerneliPfS_
.p2align 4, 0x90
.type _Z27__device_stub__simpleKerneliPfS_,@function
_Z27__device_stub__simpleKerneliPfS_: # @_Z27__device_stub__simpleKerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12simpleKerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__simpleKerneliPfS_, .Lfunc_end0-_Z27__device_stub__simpleKerneliPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $512, %edi # imm = 0x200
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $512, %edi # imm = 0x200
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl $512, 12(%rsp) # imm = 0x200
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12simpleKerneliPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 24(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $512, %r14 # imm = 0x200
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simpleKerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12simpleKerneliPfS_,@object # @_Z12simpleKerneliPfS_
.section .rodata,"a",@progbits
.globl _Z12simpleKerneliPfS_
.p2align 3, 0x0
_Z12simpleKerneliPfS_:
.quad _Z27__device_stub__simpleKerneliPfS_
.size _Z12simpleKerneliPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_a[%d] = %f\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12simpleKerneliPfS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__simpleKerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12simpleKerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define N 5
void fillMatrix(float *h_A, int size);
void mult(float *h_B, float *h_C, float *h_A, int n);
void printVector(float *h_A, int size);
int main(int argc, char const *argv[]) {
// Input matrix h_B and input vector h_C
float *h_B = (float *) malloc(N * N * sizeof(float));
float *h_C = (float *) malloc(N * sizeof(float));
// Result vector h_A
float *h_A = (float *) malloc(N * sizeof(float));
// Fill vector h_C and matrix h_B
fillMatrix(h_C, N);
fillMatrix(h_B, N * N);
// Save dot product between h_B and h_C in h_A
mult(h_B, h_C, h_A, N);
// Print the result vector
printVector(h_A, N);
//Free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
__global__
void dotProduct(float *d_B, float *d_C, float *d_A, int n)
{
float temp = 0;
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
for (int j = 0; j < n; j++)
temp = temp + (d_B[i * n + j] * d_C[j]);
d_A[i] = temp;
}
}
void fillMatrix(float *h_A, int size)
{
for (int i = 0; i < size; i++)
h_A[i] = i + 1;
}
void mult(float *h_B, float *h_C, float *h_A, int n)
{
// Define sizes of matrix and vectors in device memory
int B_size = N * N * sizeof(float);
int C_size = N * sizeof(float);
// Create device arrays
float *d_A, *d_B, *d_C;
// Allocate device memory for A, B, and C
// copy h_B and h_C to device memory
cudaError_t err = cudaMalloc((void **) &d_B, B_size);
if (err != cudaSuccess)
{
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
cudaMemcpy(d_B, h_B, B_size, cudaMemcpyHostToDevice);
err = cudaMalloc((void **) &d_C, C_size);
if (err != cudaSuccess)
{
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
cudaMemcpy(d_C, h_C, C_size, cudaMemcpyHostToDevice);
err = cudaMalloc((void **) &d_A, C_size);
if (err != cudaSuccess)
{
printf("%s in %s at line %d", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
// Launch kernel for each row
dotProduct<<<ceil(n / 256.0), 256>>>(d_B, d_C, d_A, n);
// Copy the result vector from devive to host
cudaMemcpy(h_A, d_A, C_size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A);
cudaFree(d_C);
cudaFree(d_B);
}
void printVector(float *h_A, int size)
{
for (int i = 0; i < size; i++)
printf("%d ", (int)h_A[i]);
printf("\n");
} | code for sm_80
Function : _Z10dotProductPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fc600000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xa70 ; /* 0x000009c000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fd60000000f00 */
/*0100*/ @!P0 BRA 0x930 ; /* 0x0000082000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R6, c[0x0][0x178], RZ ; /* 0x00005e0006087a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0130*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0140*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0170*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd000078e0203 */
/*01a0*/ @!P0 BRA 0x7b0 ; /* 0x0000060000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x570 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R18, [R4.64+0x4] ; /* 0x0000040404127981 */
/* 0x000ee8000c1e1900 */
/*0220*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040402197981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R19, [R4.64+0x8] ; /* 0x0000080404137981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0404167981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R23, [R4.64+0x10] ; /* 0x0000100404177981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R9, [R4.64+0x14] ; /* 0x0000140404097981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ FFMA R17, R16, R17, R15 ; /* 0x0000001110117223 */
/* 0x004fc6000000000f */
/*0300*/ LDG.E R15, [R4.64+0x20] ; /* 0x00002004040f7981 */
/* 0x0000a8000c1e1900 */
/*0310*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x0002a2000c1e1900 */
/*0320*/ FFMA R25, R18, R25, R17 ; /* 0x0000001912197223 */
/* 0x008fc60000000011 */
/*0330*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x0000e8000c1e1900 */
/*0340*/ LDG.E R18, [R2.64+0x24] ; /* 0x0000240402127981 */
/* 0x0002e2000c1e1900 */
/*0350*/ FFMA R25, R19, R20, R25 ; /* 0x0000001413197223 */
/* 0x010fc60000000019 */
/*0360*/ LDG.E R19, [R4.64+0x28] ; /* 0x0000280404137981 */
/* 0x000128000c1e1900 */
/*0370*/ LDG.E R20, [R2.64+0x28] ; /* 0x0000280402147981 */
/* 0x000322000c1e1900 */
/*0380*/ FFMA R25, R22, R21, R25 ; /* 0x0000001516197223 */
/* 0x020fc60000000019 */
/*0390*/ LDG.E R21, [R4.64+0x2c] ; /* 0x00002c0404157981 */
/* 0x000168000c1e1900 */
/*03a0*/ LDG.E R22, [R2.64+0x2c] ; /* 0x00002c0402167981 */
/* 0x000362000c1e1900 */
/*03b0*/ FFMA R25, R23, R24, R25 ; /* 0x0000001817197223 */
/* 0x000fc60000000019 */
/*03c0*/ LDG.E R23, [R4.64+0x30] ; /* 0x0000300404177981 */
/* 0x000168000c1e1900 */
/*03d0*/ LDG.E R24, [R2.64+0x30] ; /* 0x0000300402187981 */
/* 0x000362000c1e1900 */
/*03e0*/ FFMA R25, R9, R10, R25 ; /* 0x0000000a09197223 */
/* 0x000fc60000000019 */
/*03f0*/ LDG.E R9, [R4.64+0x34] ; /* 0x0000340404097981 */
/* 0x000168000c1e1900 */
/*0400*/ LDG.E R10, [R2.64+0x34] ; /* 0x00003404020a7981 */
/* 0x000362000c1e1900 */
/*0410*/ FFMA R25, R11, R12, R25 ; /* 0x0000000c0b197223 */
/* 0x000fc60000000019 */
/*0420*/ LDG.E R11, [R4.64+0x38] ; /* 0x00003804040b7981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R12, [R2.64+0x38] ; /* 0x00003804020c7981 */
/* 0x000362000c1e1900 */
/*0440*/ FFMA R25, R13, R14, R25 ; /* 0x0000000e0d197223 */
/* 0x000fc60000000019 */
/*0450*/ LDG.E R13, [R4.64+0x3c] ; /* 0x00003c04040d7981 */
/* 0x000168000c1e1900 */
/*0460*/ LDG.E R14, [R2.64+0x3c] ; /* 0x00003c04020e7981 */
/* 0x000362000c1e1900 */
/*0470*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*0480*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe40007ffe0ff */
/*0490*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*04a0*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fc40007f7e0ff */
/*04b0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x002fe40007f5e0ff */
/*04c0*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fc60001ffe4ff */
/*04d0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*04e0*/ FFMA R15, R15, R16, R25 ; /* 0x000000100f0f7223 */
/* 0x004fc80000000019 */
/*04f0*/ FFMA R15, R17, R18, R15 ; /* 0x00000012110f7223 */
/* 0x008fc8000000000f */
/*0500*/ FFMA R15, R19, R20, R15 ; /* 0x00000014130f7223 */
/* 0x010fc8000000000f */
/*0510*/ FFMA R15, R21, R22, R15 ; /* 0x00000016150f7223 */
/* 0x020fc8000000000f */
/*0520*/ FFMA R15, R23, R24, R15 ; /* 0x00000018170f7223 */
/* 0x000fc8000000000f */
/*0530*/ FFMA R9, R9, R10, R15 ; /* 0x0000000a09097223 */
/* 0x000fc8000000000f */
/*0540*/ FFMA R9, R11, R12, R9 ; /* 0x0000000c0b097223 */
/* 0x000fc80000000009 */
/*0550*/ FFMA R15, R13, R14, R9 ; /* 0x0000000e0d0f7223 */
/* 0x000fe20000000009 */
/*0560*/ @P1 BRA 0x1f0 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*0570*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0580*/ @!P1 BRA 0x790 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x0000a8000c1e1900 */
/*05a0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1900 */
/*05b0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x0000e8000c1e1900 */
/*05c0*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000ee8000c1e1900 */
/*05d0*/ LDG.E R21, [R4.64+0x8] ; /* 0x0000080404157981 */
/* 0x000128000c1e1900 */
/*05e0*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000168000c1e1900 */
/*0600*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*0610*/ LDG.E R25, [R4.64+0x10] ; /* 0x0000100404197981 */
/* 0x000168000c1e1900 */
/*0620*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f68000c1e1900 */
/*0630*/ LDG.E R13, [R4.64+0x14] ; /* 0x00001404040d7981 */
/* 0x000168000c1e1900 */
/*0640*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000f68000c1e1900 */
/*0650*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R9, [R4.64+0x1c] ; /* 0x00001c0404097981 */
/* 0x000168000c1e1900 */
/*0680*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c04020a7981 */
/* 0x000362000c1e1900 */
/*0690*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*06a0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f5e0ff */
/*06d0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe400010e0605 */
/*06e0*/ FFMA R16, R16, R17, R15 ; /* 0x0000001110107223 */
/* 0x004fc8000000000f */
/*06f0*/ FFMA R16, R19, R18, R16 ; /* 0x0000001213107223 */
/* 0x008fc80000000010 */
/*0700*/ FFMA R16, R21, R20, R16 ; /* 0x0000001415107223 */
/* 0x010fc80000000010 */
/*0710*/ FFMA R16, R23, R22, R16 ; /* 0x0000001617107223 */
/* 0x020fc80000000010 */
/*0720*/ FFMA R16, R25, R24, R16 ; /* 0x0000001819107223 */
/* 0x000fc80000000010 */
/*0730*/ FFMA R13, R13, R14, R16 ; /* 0x0000000e0d0d7223 */
/* 0x000fc80000000010 */
/*0740*/ FFMA R11, R11, R12, R13 ; /* 0x0000000c0b0b7223 */
/* 0x000fe2000000000d */
/*0750*/ IADD3 R12, P1, R2, 0x20, RZ ; /* 0x00000020020c7810 */
/* 0x000fc80007f3e0ff */
/*0760*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe40000ffe4ff */
/*0770*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x000fe20000000f00 */
/*0780*/ FFMA R15, R9, R10, R11 ; /* 0x0000000a090f7223 */
/* 0x000fe4000000000b */
/*0790*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*07a0*/ @!P0 BRA 0x930 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*07b0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x0000e8000c1e1900 */
/*07e0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000328000c1e1900 */
/*0810*/ LDG.E R16, [R4.64+0xc] ; /* 0x00000c0404107981 */
/* 0x000168000c1e1900 */
/*0820*/ LDG.E R17, [R2.64+0xc] ; /* 0x00000c0402117981 */
/* 0x000362000c1e1900 */
/*0830*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc40007ffe0ff */
/*0840*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0850*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0860*/ FFMA R9, R10, R9, R15 ; /* 0x000000090a097223 */
/* 0x004fe2000000000f */
/*0870*/ IADD3 R10, P2, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fca0007f5e0ff */
/*0880*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fe400078e000a */
/*0890*/ FFMA R9, R12, R11, R9 ; /* 0x0000000b0c097223 */
/* 0x008fe20000000009 */
/*08a0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fc600010e0605 */
/*08c0*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x002fe40000000f00 */
/*08d0*/ MOV R5, R11 ; /* 0x0000000b00057202 */
/* 0x000fe20000000f00 */
/*08e0*/ FFMA R9, R14, R13, R9 ; /* 0x0000000d0e097223 */
/* 0x010fe20000000009 */
/*08f0*/ IADD3.X R13, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0d7210 */
/* 0x000fca0000ffe4ff */
/*0900*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0910*/ FFMA R15, R16, R17, R9 ; /* 0x00000011100f7223 */
/* 0x020fe20000000009 */
/*0920*/ @P0 BRA 0x7b0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0930*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0940*/ @!P0 BRA 0xa70 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0950*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0960*/ IMAD R4, R0, c[0x0][0x178], R7 ; /* 0x00005e0000047a24 */
/* 0x000fd200078e0207 */
/*0970*/ IMAD.WIDE R2, R7, R5, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fc800078e0205 */
/*0980*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0990*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fc60000000f00 */
/*09a0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0004 */
/*09b0*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fe40000000f00 */
/*09c0*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fc80000000f00 */
/*09d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*09e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*09f0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0a00*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*0a10*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a20*/ IADD3 R7, P2, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007f5e0ff */
/*0a30*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fc600008e0603 */
/*0a40*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe200017fe4ff */
/*0a50*/ FFMA R15, R2, R4, R15 ; /* 0x00000004020f7223 */
/* 0x004fcc000000000f */
/*0a60*/ @P0 BRA 0x9b0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0a70*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0a80*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0a90*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0aa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ab0*/ BRA 0xab0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define N 5
void fillMatrix(float *h_A, int size);
void mult(float *h_B, float *h_C, float *h_A, int n);
void printVector(float *h_A, int size);
int main(int argc, char const *argv[]) {
// Input matrix h_B and input vector h_C
float *h_B = (float *) malloc(N * N * sizeof(float));
float *h_C = (float *) malloc(N * sizeof(float));
// Result vector h_A
float *h_A = (float *) malloc(N * sizeof(float));
// Fill vector h_C and matrix h_B
fillMatrix(h_C, N);
fillMatrix(h_B, N * N);
// Save dot product between h_B and h_C in h_A
mult(h_B, h_C, h_A, N);
// Print the result vector
printVector(h_A, N);
//Free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
__global__
void dotProduct(float *d_B, float *d_C, float *d_A, int n)
{
float temp = 0;
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
for (int j = 0; j < n; j++)
temp = temp + (d_B[i * n + j] * d_C[j]);
d_A[i] = temp;
}
}
void fillMatrix(float *h_A, int size)
{
for (int i = 0; i < size; i++)
h_A[i] = i + 1;
}
void mult(float *h_B, float *h_C, float *h_A, int n)
{
// Define sizes of matrix and vectors in device memory
int B_size = N * N * sizeof(float);
int C_size = N * sizeof(float);
// Create device arrays
float *d_A, *d_B, *d_C;
// Allocate device memory for A, B, and C
// copy h_B and h_C to device memory
cudaError_t err = cudaMalloc((void **) &d_B, B_size);
if (err != cudaSuccess)
{
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
cudaMemcpy(d_B, h_B, B_size, cudaMemcpyHostToDevice);
err = cudaMalloc((void **) &d_C, C_size);
if (err != cudaSuccess)
{
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
cudaMemcpy(d_C, h_C, C_size, cudaMemcpyHostToDevice);
err = cudaMalloc((void **) &d_A, C_size);
if (err != cudaSuccess)
{
printf("%s in %s at line %d", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
// Launch kernel for each row
dotProduct<<<ceil(n / 256.0), 256>>>(d_B, d_C, d_A, n);
// Copy the result vector from devive to host
cudaMemcpy(h_A, d_A, C_size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A);
cudaFree(d_C);
cudaFree(d_B);
}
void printVector(float *h_A, int size)
{
for (int i = 0; i < size; i++)
printf("%d ", (int)h_A[i]);
printf("\n");
} | .file "tmpxft_000e605d_00000000-6_matrixVecMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10fillMatrixPfi
.type _Z10fillMatrixPfi, @function
_Z10fillMatrixPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $1, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rdi,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rsi, %rdx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z10fillMatrixPfi, .-_Z10fillMatrixPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z11printVectorPfi
.type _Z11printVectorPfi, @function
_Z11printVectorPfi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L8
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L9:
cvttss2sil (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L9
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z11printVectorPfi, .-_Z11printVectorPfi
.globl _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10dotProductPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
.globl _Z10dotProductPfS_S_i
.type _Z10dotProductPfS_S_i, @function
_Z10dotProductPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10dotProductPfS_S_i, .-_Z10dotProductPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/afmejia/HPC/master/Cuda/matrixVecMult.cu"
.section .rodata.str1.1
.LC3:
.string "%s in %s at line %d\n"
.LC4:
.string "%s in %s at line %d"
.text
.globl _Z4multPfS_S_i
.type _Z4multPfS_S_i, @function
_Z4multPfS_S_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movl $1, %ecx
movl $100, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L29
movl $1, %ecx
movl $20, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC9(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L24
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L24:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L25:
movl $2, %ecx
movl $20, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $71, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $79, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $87, %r8d
leaq .LC2(%rip), %rcx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %ebx, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
jmp .L25
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z4multPfS_S_i, .-_Z4multPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movl $20, %edi
call malloc@PLT
movq %rax, %rbx
movl $20, %edi
call malloc@PLT
movq %rax, %r12
movl $5, %esi
movq %rbx, %rdi
call _Z10fillMatrixPfi
movl $25, %esi
movq %rbp, %rdi
call _Z10fillMatrixPfi
movl $5, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z4multPfS_S_i
movl $5, %esi
movq %r12, %rdi
call _Z11printVectorPfi
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10dotProductPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10dotProductPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1064304640
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC9:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define N 5
void fillMatrix(float *h_A, int size);
void mult(float *h_B, float *h_C, float *h_A, int n);
void printVector(float *h_A, int size);
int main(int argc, char const *argv[]) {
// Input matrix h_B and input vector h_C
float *h_B = (float *) malloc(N * N * sizeof(float));
float *h_C = (float *) malloc(N * sizeof(float));
// Result vector h_A
float *h_A = (float *) malloc(N * sizeof(float));
// Fill vector h_C and matrix h_B
fillMatrix(h_C, N);
fillMatrix(h_B, N * N);
// Save dot product between h_B and h_C in h_A
mult(h_B, h_C, h_A, N);
// Print the result vector
printVector(h_A, N);
//Free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
__global__
void dotProduct(float *d_B, float *d_C, float *d_A, int n)
{
float temp = 0;
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
for (int j = 0; j < n; j++)
temp = temp + (d_B[i * n + j] * d_C[j]);
d_A[i] = temp;
}
}
void fillMatrix(float *h_A, int size)
{
for (int i = 0; i < size; i++)
h_A[i] = i + 1;
}
void mult(float *h_B, float *h_C, float *h_A, int n)
{
// Define sizes of matrix and vectors in device memory
int B_size = N * N * sizeof(float);
int C_size = N * sizeof(float);
// Create device arrays
float *d_A, *d_B, *d_C;
// Allocate device memory for A, B, and C
// copy h_B and h_C to device memory
cudaError_t err = cudaMalloc((void **) &d_B, B_size);
if (err != cudaSuccess)
{
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
cudaMemcpy(d_B, h_B, B_size, cudaMemcpyHostToDevice);
err = cudaMalloc((void **) &d_C, C_size);
if (err != cudaSuccess)
{
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
cudaMemcpy(d_C, h_C, C_size, cudaMemcpyHostToDevice);
err = cudaMalloc((void **) &d_A, C_size);
if (err != cudaSuccess)
{
printf("%s in %s at line %d", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
// Launch kernel for each row
dotProduct<<<ceil(n / 256.0), 256>>>(d_B, d_C, d_A, n);
// Copy the result vector from devive to host
cudaMemcpy(h_A, d_A, C_size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A);
cudaFree(d_C);
cudaFree(d_B);
}
void printVector(float *h_A, int size)
{
for (int i = 0; i < size; i++)
printf("%d ", (int)h_A[i]);
printf("\n");
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define N 5
void fillMatrix(float *h_A, int size);
void mult(float *h_B, float *h_C, float *h_A, int n);
void printVector(float *h_A, int size);
int main(int argc, char const *argv[]) {
// Input matrix h_B and input vector h_C
float *h_B = (float *) malloc(N * N * sizeof(float));
float *h_C = (float *) malloc(N * sizeof(float));
// Result vector h_A
float *h_A = (float *) malloc(N * sizeof(float));
// Fill vector h_C and matrix h_B
fillMatrix(h_C, N);
fillMatrix(h_B, N * N);
// Save dot product between h_B and h_C in h_A
mult(h_B, h_C, h_A, N);
// Print the result vector
printVector(h_A, N);
//Free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
__global__
void dotProduct(float *d_B, float *d_C, float *d_A, int n)
{
float temp = 0;
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
for (int j = 0; j < n; j++)
temp = temp + (d_B[i * n + j] * d_C[j]);
d_A[i] = temp;
}
}
void fillMatrix(float *h_A, int size)
{
for (int i = 0; i < size; i++)
h_A[i] = i + 1;
}
void mult(float *h_B, float *h_C, float *h_A, int n)
{
// Define sizes of matrix and vectors in device memory
int B_size = N * N * sizeof(float);
int C_size = N * sizeof(float);
// Create device arrays
float *d_A, *d_B, *d_C;
// Allocate device memory for A, B, and C
// copy h_B and h_C to device memory
hipError_t err = hipMalloc((void **) &d_B, B_size);
if (err != hipSuccess)
{
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
hipMemcpy(d_B, h_B, B_size, hipMemcpyHostToDevice);
err = hipMalloc((void **) &d_C, C_size);
if (err != hipSuccess)
{
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
hipMemcpy(d_C, h_C, C_size, hipMemcpyHostToDevice);
err = hipMalloc((void **) &d_A, C_size);
if (err != hipSuccess)
{
printf("%s in %s at line %d", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
// Launch kernel for each row
dotProduct<<<ceil(n / 256.0), 256>>>(d_B, d_C, d_A, n);
// Copy the result vector from devive to host
hipMemcpy(h_A, d_A, C_size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A);
hipFree(d_C);
hipFree(d_B);
}
void printVector(float *h_A, int size)
{
for (int i = 0; i < size; i++)
printf("%d ", (int)h_A[i]);
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define N 5
void fillMatrix(float *h_A, int size);
void mult(float *h_B, float *h_C, float *h_A, int n);
void printVector(float *h_A, int size);
int main(int argc, char const *argv[]) {
// Input matrix h_B and input vector h_C
float *h_B = (float *) malloc(N * N * sizeof(float));
float *h_C = (float *) malloc(N * sizeof(float));
// Result vector h_A
float *h_A = (float *) malloc(N * sizeof(float));
// Fill vector h_C and matrix h_B
fillMatrix(h_C, N);
fillMatrix(h_B, N * N);
// Save dot product between h_B and h_C in h_A
mult(h_B, h_C, h_A, N);
// Print the result vector
printVector(h_A, N);
//Free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
__global__
void dotProduct(float *d_B, float *d_C, float *d_A, int n)
{
float temp = 0;
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
for (int j = 0; j < n; j++)
temp = temp + (d_B[i * n + j] * d_C[j]);
d_A[i] = temp;
}
}
void fillMatrix(float *h_A, int size)
{
for (int i = 0; i < size; i++)
h_A[i] = i + 1;
}
void mult(float *h_B, float *h_C, float *h_A, int n)
{
// Define sizes of matrix and vectors in device memory
int B_size = N * N * sizeof(float);
int C_size = N * sizeof(float);
// Create device arrays
float *d_A, *d_B, *d_C;
// Allocate device memory for A, B, and C
// copy h_B and h_C to device memory
hipError_t err = hipMalloc((void **) &d_B, B_size);
if (err != hipSuccess)
{
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
hipMemcpy(d_B, h_B, B_size, hipMemcpyHostToDevice);
err = hipMalloc((void **) &d_C, C_size);
if (err != hipSuccess)
{
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
hipMemcpy(d_C, h_C, C_size, hipMemcpyHostToDevice);
err = hipMalloc((void **) &d_A, C_size);
if (err != hipSuccess)
{
printf("%s in %s at line %d", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
// Launch kernel for each row
dotProduct<<<ceil(n / 256.0), 256>>>(d_B, d_C, d_A, n);
// Copy the result vector from devive to host
hipMemcpy(h_A, d_A, C_size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A);
hipFree(d_C);
hipFree(d_B);
}
void printVector(float *h_A, int size)
{
for (int i = 0; i < size; i++)
printf("%d ", (int)h_A[i]);
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10dotProductPfS_S_i
.globl _Z10dotProductPfS_S_i
.p2align 8
.type _Z10dotProductPfS_S_i,@function
_Z10dotProductPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:
global_load_b32 v4, v[2:3], off
s_load_b32 s3, s[6:7], 0x0
v_add_co_u32 v2, vcc_lo, v2, 4
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s3, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10dotProductPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10dotProductPfS_S_i, .Lfunc_end0-_Z10dotProductPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10dotProductPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10dotProductPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#define N 5
void fillMatrix(float *h_A, int size);
void mult(float *h_B, float *h_C, float *h_A, int n);
void printVector(float *h_A, int size);
int main(int argc, char const *argv[]) {
// Input matrix h_B and input vector h_C
float *h_B = (float *) malloc(N * N * sizeof(float));
float *h_C = (float *) malloc(N * sizeof(float));
// Result vector h_A
float *h_A = (float *) malloc(N * sizeof(float));
// Fill vector h_C and matrix h_B
fillMatrix(h_C, N);
fillMatrix(h_B, N * N);
// Save dot product between h_B and h_C in h_A
mult(h_B, h_C, h_A, N);
// Print the result vector
printVector(h_A, N);
//Free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
__global__
void dotProduct(float *d_B, float *d_C, float *d_A, int n)
{
float temp = 0;
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n)
{
for (int j = 0; j < n; j++)
temp = temp + (d_B[i * n + j] * d_C[j]);
d_A[i] = temp;
}
}
void fillMatrix(float *h_A, int size)
{
for (int i = 0; i < size; i++)
h_A[i] = i + 1;
}
void mult(float *h_B, float *h_C, float *h_A, int n)
{
// Define sizes of matrix and vectors in device memory
int B_size = N * N * sizeof(float);
int C_size = N * sizeof(float);
// Create device arrays
float *d_A, *d_B, *d_C;
// Allocate device memory for A, B, and C
// copy h_B and h_C to device memory
hipError_t err = hipMalloc((void **) &d_B, B_size);
if (err != hipSuccess)
{
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
hipMemcpy(d_B, h_B, B_size, hipMemcpyHostToDevice);
err = hipMalloc((void **) &d_C, C_size);
if (err != hipSuccess)
{
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
hipMemcpy(d_C, h_C, C_size, hipMemcpyHostToDevice);
err = hipMalloc((void **) &d_A, C_size);
if (err != hipSuccess)
{
printf("%s in %s at line %d", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
// Launch kernel for each row
dotProduct<<<ceil(n / 256.0), 256>>>(d_B, d_C, d_A, n);
// Copy the result vector from devive to host
hipMemcpy(h_A, d_A, C_size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A);
hipFree(d_C);
hipFree(d_B);
}
void printVector(float *h_A, int size)
{
for (int i = 0; i < size; i++)
printf("%d ", (int)h_A[i]);
printf("\n");
} | .text
.file "matrixVecMult.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $100, %edi
callq malloc
movq %rax, %rbx
movl $20, %edi
callq malloc
movq %rax, %r14
movl $20, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rax,4)
movq %rcx, %rax
cmpq $5, %rcx
jne .LBB0_1
# %bb.2: # %.lr.ph.i9.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i9
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $25, %rcx
jne .LBB0_3
# %bb.4: # %_Z10fillMatrixPfi.exit13
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $5, %ecx
callq _Z4multPfS_S_i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph.i14
# =>This Inner Loop Header: Depth=1
cvttss2si (%r15,%r12,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $5, %r12
jne .LBB0_5
# %bb.6: # %_Z11printVectorPfi.exit
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z10fillMatrixPfi # -- Begin function _Z10fillMatrixPfi
.p2align 4, 0x90
.type _Z10fillMatrixPfi,@function
_Z10fillMatrixPfi: # @_Z10fillMatrixPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10fillMatrixPfi, .Lfunc_end1-_Z10fillMatrixPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4multPfS_S_i
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z4multPfS_S_i
.p2align 4, 0x90
.type _Z4multPfS_S_i,@function
_Z4multPfS_S_i: # @_Z4multPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 16(%rsp), %rdi
movl $100, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3:
movq 16(%rsp), %rdi
movl $100, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5:
movq 8(%rsp), %rdi
movl $20, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
cvtsi2sd %ebp, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10dotProductPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq 24(%rsp), %rsi
movl $20, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $71, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $79, %ecx
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $87, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z4multPfS_S_i, .Lfunc_end2-_Z4multPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11printVectorPfi # -- Begin function _Z11printVectorPfi
.p2align 4, 0x90
.type _Z11printVectorPfi,@function
_Z11printVectorPfi: # @_Z11printVectorPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cvttss2si (%rbx,%r15,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z11printVectorPfi, .Lfunc_end3-_Z11printVectorPfi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__dotProductPfS_S_i # -- Begin function _Z25__device_stub__dotProductPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__dotProductPfS_S_i,@function
_Z25__device_stub__dotProductPfS_S_i: # @_Z25__device_stub__dotProductPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10dotProductPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z25__device_stub__dotProductPfS_S_i, .Lfunc_end4-_Z25__device_stub__dotProductPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10dotProductPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10dotProductPfS_S_i,@object # @_Z10dotProductPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10dotProductPfS_S_i
.p2align 3, 0x0
_Z10dotProductPfS_S_i:
.quad _Z25__device_stub__dotProductPfS_S_i
.size _Z10dotProductPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/afmejia/HPC/master/Cuda/matrixVecMult.hip"
.size .L.str.1, 99
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10dotProductPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__dotProductPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10dotProductPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10dotProductPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fc600000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xa70 ; /* 0x000009c000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fd60000000f00 */
/*0100*/ @!P0 BRA 0x930 ; /* 0x0000082000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R6, c[0x0][0x178], RZ ; /* 0x00005e0006087a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0130*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0140*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0170*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd000078e0203 */
/*01a0*/ @!P0 BRA 0x7b0 ; /* 0x0000060000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x570 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R18, [R4.64+0x4] ; /* 0x0000040404127981 */
/* 0x000ee8000c1e1900 */
/*0220*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040402197981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R19, [R4.64+0x8] ; /* 0x0000080404137981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0404167981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R23, [R4.64+0x10] ; /* 0x0000100404177981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R9, [R4.64+0x14] ; /* 0x0000140404097981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ FFMA R17, R16, R17, R15 ; /* 0x0000001110117223 */
/* 0x004fc6000000000f */
/*0300*/ LDG.E R15, [R4.64+0x20] ; /* 0x00002004040f7981 */
/* 0x0000a8000c1e1900 */
/*0310*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x0002a2000c1e1900 */
/*0320*/ FFMA R25, R18, R25, R17 ; /* 0x0000001912197223 */
/* 0x008fc60000000011 */
/*0330*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x0000e8000c1e1900 */
/*0340*/ LDG.E R18, [R2.64+0x24] ; /* 0x0000240402127981 */
/* 0x0002e2000c1e1900 */
/*0350*/ FFMA R25, R19, R20, R25 ; /* 0x0000001413197223 */
/* 0x010fc60000000019 */
/*0360*/ LDG.E R19, [R4.64+0x28] ; /* 0x0000280404137981 */
/* 0x000128000c1e1900 */
/*0370*/ LDG.E R20, [R2.64+0x28] ; /* 0x0000280402147981 */
/* 0x000322000c1e1900 */
/*0380*/ FFMA R25, R22, R21, R25 ; /* 0x0000001516197223 */
/* 0x020fc60000000019 */
/*0390*/ LDG.E R21, [R4.64+0x2c] ; /* 0x00002c0404157981 */
/* 0x000168000c1e1900 */
/*03a0*/ LDG.E R22, [R2.64+0x2c] ; /* 0x00002c0402167981 */
/* 0x000362000c1e1900 */
/*03b0*/ FFMA R25, R23, R24, R25 ; /* 0x0000001817197223 */
/* 0x000fc60000000019 */
/*03c0*/ LDG.E R23, [R4.64+0x30] ; /* 0x0000300404177981 */
/* 0x000168000c1e1900 */
/*03d0*/ LDG.E R24, [R2.64+0x30] ; /* 0x0000300402187981 */
/* 0x000362000c1e1900 */
/*03e0*/ FFMA R25, R9, R10, R25 ; /* 0x0000000a09197223 */
/* 0x000fc60000000019 */
/*03f0*/ LDG.E R9, [R4.64+0x34] ; /* 0x0000340404097981 */
/* 0x000168000c1e1900 */
/*0400*/ LDG.E R10, [R2.64+0x34] ; /* 0x00003404020a7981 */
/* 0x000362000c1e1900 */
/*0410*/ FFMA R25, R11, R12, R25 ; /* 0x0000000c0b197223 */
/* 0x000fc60000000019 */
/*0420*/ LDG.E R11, [R4.64+0x38] ; /* 0x00003804040b7981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R12, [R2.64+0x38] ; /* 0x00003804020c7981 */
/* 0x000362000c1e1900 */
/*0440*/ FFMA R25, R13, R14, R25 ; /* 0x0000000e0d197223 */
/* 0x000fc60000000019 */
/*0450*/ LDG.E R13, [R4.64+0x3c] ; /* 0x00003c04040d7981 */
/* 0x000168000c1e1900 */
/*0460*/ LDG.E R14, [R2.64+0x3c] ; /* 0x00003c04020e7981 */
/* 0x000362000c1e1900 */
/*0470*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*0480*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe40007ffe0ff */
/*0490*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*04a0*/ IADD3 R4, P3, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fc40007f7e0ff */
/*04b0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x002fe40007f5e0ff */
/*04c0*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fc60001ffe4ff */
/*04d0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*04e0*/ FFMA R15, R15, R16, R25 ; /* 0x000000100f0f7223 */
/* 0x004fc80000000019 */
/*04f0*/ FFMA R15, R17, R18, R15 ; /* 0x00000012110f7223 */
/* 0x008fc8000000000f */
/*0500*/ FFMA R15, R19, R20, R15 ; /* 0x00000014130f7223 */
/* 0x010fc8000000000f */
/*0510*/ FFMA R15, R21, R22, R15 ; /* 0x00000016150f7223 */
/* 0x020fc8000000000f */
/*0520*/ FFMA R15, R23, R24, R15 ; /* 0x00000018170f7223 */
/* 0x000fc8000000000f */
/*0530*/ FFMA R9, R9, R10, R15 ; /* 0x0000000a09097223 */
/* 0x000fc8000000000f */
/*0540*/ FFMA R9, R11, R12, R9 ; /* 0x0000000c0b097223 */
/* 0x000fc80000000009 */
/*0550*/ FFMA R15, R13, R14, R9 ; /* 0x0000000e0d0f7223 */
/* 0x000fe20000000009 */
/*0560*/ @P1 BRA 0x1f0 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*0570*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0580*/ @!P1 BRA 0x790 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x0000a8000c1e1900 */
/*05a0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1900 */
/*05b0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x0000e8000c1e1900 */
/*05c0*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000ee8000c1e1900 */
/*05d0*/ LDG.E R21, [R4.64+0x8] ; /* 0x0000080404157981 */
/* 0x000128000c1e1900 */
/*05e0*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000168000c1e1900 */
/*0600*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*0610*/ LDG.E R25, [R4.64+0x10] ; /* 0x0000100404197981 */
/* 0x000168000c1e1900 */
/*0620*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000f68000c1e1900 */
/*0630*/ LDG.E R13, [R4.64+0x14] ; /* 0x00001404040d7981 */
/* 0x000168000c1e1900 */
/*0640*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000f68000c1e1900 */
/*0650*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R9, [R4.64+0x1c] ; /* 0x00001c0404097981 */
/* 0x000168000c1e1900 */
/*0680*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c04020a7981 */
/* 0x000362000c1e1900 */
/*0690*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*06a0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f5e0ff */
/*06d0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe400010e0605 */
/*06e0*/ FFMA R16, R16, R17, R15 ; /* 0x0000001110107223 */
/* 0x004fc8000000000f */
/*06f0*/ FFMA R16, R19, R18, R16 ; /* 0x0000001213107223 */
/* 0x008fc80000000010 */
/*0700*/ FFMA R16, R21, R20, R16 ; /* 0x0000001415107223 */
/* 0x010fc80000000010 */
/*0710*/ FFMA R16, R23, R22, R16 ; /* 0x0000001617107223 */
/* 0x020fc80000000010 */
/*0720*/ FFMA R16, R25, R24, R16 ; /* 0x0000001819107223 */
/* 0x000fc80000000010 */
/*0730*/ FFMA R13, R13, R14, R16 ; /* 0x0000000e0d0d7223 */
/* 0x000fc80000000010 */
/*0740*/ FFMA R11, R11, R12, R13 ; /* 0x0000000c0b0b7223 */
/* 0x000fe2000000000d */
/*0750*/ IADD3 R12, P1, R2, 0x20, RZ ; /* 0x00000020020c7810 */
/* 0x000fc80007f3e0ff */
/*0760*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe40000ffe4ff */
/*0770*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x000fe20000000f00 */
/*0780*/ FFMA R15, R9, R10, R11 ; /* 0x0000000a090f7223 */
/* 0x000fe4000000000b */
/*0790*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*07a0*/ @!P0 BRA 0x930 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*07b0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000404040c7981 */
/* 0x0000e8000c1e1900 */
/*07e0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000328000c1e1900 */
/*0810*/ LDG.E R16, [R4.64+0xc] ; /* 0x00000c0404107981 */
/* 0x000168000c1e1900 */
/*0820*/ LDG.E R17, [R2.64+0xc] ; /* 0x00000c0402117981 */
/* 0x000362000c1e1900 */
/*0830*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc40007ffe0ff */
/*0840*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0850*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0860*/ FFMA R9, R10, R9, R15 ; /* 0x000000090a097223 */
/* 0x004fe2000000000f */
/*0870*/ IADD3 R10, P2, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fca0007f5e0ff */
/*0880*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fe400078e000a */
/*0890*/ FFMA R9, R12, R11, R9 ; /* 0x0000000b0c097223 */
/* 0x008fe20000000009 */
/*08a0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fc600010e0605 */
/*08c0*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x002fe40000000f00 */
/*08d0*/ MOV R5, R11 ; /* 0x0000000b00057202 */
/* 0x000fe20000000f00 */
/*08e0*/ FFMA R9, R14, R13, R9 ; /* 0x0000000d0e097223 */
/* 0x010fe20000000009 */
/*08f0*/ IADD3.X R13, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0d7210 */
/* 0x000fca0000ffe4ff */
/*0900*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0910*/ FFMA R15, R16, R17, R9 ; /* 0x00000011100f7223 */
/* 0x020fe20000000009 */
/*0920*/ @P0 BRA 0x7b0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0930*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0940*/ @!P0 BRA 0xa70 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0950*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0960*/ IMAD R4, R0, c[0x0][0x178], R7 ; /* 0x00005e0000047a24 */
/* 0x000fd200078e0207 */
/*0970*/ IMAD.WIDE R2, R7, R5, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fc800078e0205 */
/*0980*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0990*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fc60000000f00 */
/*09a0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0004 */
/*09b0*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fe40000000f00 */
/*09c0*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fc80000000f00 */
/*09d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*09e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*09f0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0a00*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*0a10*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a20*/ IADD3 R7, P2, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007f5e0ff */
/*0a30*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fc600008e0603 */
/*0a40*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe200017fe4ff */
/*0a50*/ FFMA R15, R2, R4, R15 ; /* 0x00000004020f7223 */
/* 0x004fcc000000000f */
/*0a60*/ @P0 BRA 0x9b0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0a70*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0a80*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0a90*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0aa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ab0*/ BRA 0xab0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10dotProductPfS_S_i
.globl _Z10dotProductPfS_S_i
.p2align 8
.type _Z10dotProductPfS_S_i,@function
_Z10dotProductPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:
global_load_b32 v4, v[2:3], off
s_load_b32 s3, s[6:7], 0x0
v_add_co_u32 v2, vcc_lo, v2, 4
s_add_i32 s2, s2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s3, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10dotProductPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10dotProductPfS_S_i, .Lfunc_end0-_Z10dotProductPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10dotProductPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10dotProductPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e605d_00000000-6_matrixVecMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10fillMatrixPfi
.type _Z10fillMatrixPfi, @function
_Z10fillMatrixPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $1, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rdi,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rsi, %rdx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z10fillMatrixPfi, .-_Z10fillMatrixPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z11printVectorPfi
.type _Z11printVectorPfi, @function
_Z11printVectorPfi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L8
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L9:
cvttss2sil (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L9
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z11printVectorPfi, .-_Z11printVectorPfi
.globl _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10dotProductPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
.globl _Z10dotProductPfS_S_i
.type _Z10dotProductPfS_S_i, @function
_Z10dotProductPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10dotProductPfS_S_i, .-_Z10dotProductPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/afmejia/HPC/master/Cuda/matrixVecMult.cu"
.section .rodata.str1.1
.LC3:
.string "%s in %s at line %d\n"
.LC4:
.string "%s in %s at line %d"
.text
.globl _Z4multPfS_S_i
.type _Z4multPfS_S_i, @function
_Z4multPfS_S_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movl $1, %ecx
movl $100, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L29
movl $1, %ecx
movl $20, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC9(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L24
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L24:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L25:
movl $2, %ecx
movl $20, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $71, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $79, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $87, %r8d
leaq .LC2(%rip), %rcx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %ebx, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z10dotProductPfS_S_iPfS_S_i
jmp .L25
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z4multPfS_S_i, .-_Z4multPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movl $20, %edi
call malloc@PLT
movq %rax, %rbx
movl $20, %edi
call malloc@PLT
movq %rax, %r12
movl $5, %esi
movq %rbx, %rdi
call _Z10fillMatrixPfi
movl $25, %esi
movq %rbp, %rdi
call _Z10fillMatrixPfi
movl $5, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z4multPfS_S_i
movl $5, %esi
movq %r12, %rdi
call _Z11printVectorPfi
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10dotProductPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10dotProductPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1064304640
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC9:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixVecMult.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $100, %edi
callq malloc
movq %rax, %rbx
movl $20, %edi
callq malloc
movq %rax, %r14
movl $20, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rax,4)
movq %rcx, %rax
cmpq $5, %rcx
jne .LBB0_1
# %bb.2: # %.lr.ph.i9.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i9
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $25, %rcx
jne .LBB0_3
# %bb.4: # %_Z10fillMatrixPfi.exit13
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $5, %ecx
callq _Z4multPfS_S_i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph.i14
# =>This Inner Loop Header: Depth=1
cvttss2si (%r15,%r12,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $5, %r12
jne .LBB0_5
# %bb.6: # %_Z11printVectorPfi.exit
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z10fillMatrixPfi # -- Begin function _Z10fillMatrixPfi
.p2align 4, 0x90
.type _Z10fillMatrixPfi,@function
_Z10fillMatrixPfi: # @_Z10fillMatrixPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10fillMatrixPfi, .Lfunc_end1-_Z10fillMatrixPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4multPfS_S_i
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z4multPfS_S_i
.p2align 4, 0x90
.type _Z4multPfS_S_i,@function
_Z4multPfS_S_i: # @_Z4multPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 16(%rsp), %rdi
movl $100, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3:
movq 16(%rsp), %rdi
movl $100, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5:
movq 8(%rsp), %rdi
movl $20, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
cvtsi2sd %ebp, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10dotProductPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq 24(%rsp), %rsi
movl $20, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $71, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $79, %ecx
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $87, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z4multPfS_S_i, .Lfunc_end2-_Z4multPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11printVectorPfi # -- Begin function _Z11printVectorPfi
.p2align 4, 0x90
.type _Z11printVectorPfi,@function
_Z11printVectorPfi: # @_Z11printVectorPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cvttss2si (%rbx,%r15,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z11printVectorPfi, .Lfunc_end3-_Z11printVectorPfi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__dotProductPfS_S_i # -- Begin function _Z25__device_stub__dotProductPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__dotProductPfS_S_i,@function
_Z25__device_stub__dotProductPfS_S_i: # @_Z25__device_stub__dotProductPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10dotProductPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z25__device_stub__dotProductPfS_S_i, .Lfunc_end4-_Z25__device_stub__dotProductPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10dotProductPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10dotProductPfS_S_i,@object # @_Z10dotProductPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10dotProductPfS_S_i
.p2align 3, 0x0
_Z10dotProductPfS_S_i:
.quad _Z25__device_stub__dotProductPfS_S_i
.size _Z10dotProductPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/afmejia/HPC/master/Cuda/matrixVecMult.hip"
.size .L.str.1, 99
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d"
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10dotProductPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__dotProductPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10dotProductPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <ctime>
#include <cstdlib>
#include <cmath>
#include "cuda_runtime.h"
#include <thrust/scan.h>
using namespace std;
#define TPB 1024
#define RANGE 10
#define min(a,b) ((a < b) ? a : b)
__global__
void incl_pfsum (float * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
size = min(size, TPB);
__syncthreads();
for (int step = 2; step <= size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
if (tid % TPB == 0) { array[bsize - 1] = 0; }
__syncthreads();
for (int step = size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
//__syncthreads();
array[tid] += array[tid - (step / 2)];
//__syncthreads();
array[tid - (step / 2)] = tmp;
//__syncthreads();
}
__syncthreads();
}
__syncthreads();
}
__global__
void scat_part_sum(float * array, float * array_psums) {
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
array[tid] += array_psums[blockIdx.x];
__syncthreads();
}
__global__
void upsweep (float * array, float * array_aggr1, int size, int size_aggr1) {
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
for (int step = 2; step <= size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
__global__
void downsweep (float * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
__syncthreads();
/*
if (tid >= (1<<step) && (tid < size)) {
tmp = array[tid - (1<<step)];
__syncthreads();
array[tid] = tmp + array[tid];
__syncthreads();
}
*/
}
int main(int argc, char** argv)
{
if (argc != 2) {
cout << "Takes one argument - the number of elements in an array" << endl;
return 0;
}
int size = atoi(argv[1]);
int size_div1 = int(ceil(float(size) / float(TPB)));
int size_div2 = int(ceil(float(size_div1) / float(TPB)));
int nblocks = int(ceil(float(size) / float(TPB)));
int nblocks_div1 = int(ceil(float(nblocks) / float(TPB)));
int nblocks_div2 = int(ceil(float(nblocks_div1) / float(TPB)));
cout << "First stage blocks: " << nblocks << endl;
cout << "Second stage blocks: " << nblocks_div1 << endl;
cout << "Third stage blocks: " << nblocks_div2 << endl;
cout << "First stage size: " << size << endl;
cout << "Second stage size: " << size_div1 << endl;
cout << "Third stage size: " << size_div2 << endl;
cout << "Malloc'ing\n";
float *x = (float*)malloc(size * sizeof(float));
float *x1 = (float*)malloc(size_div1 * sizeof(float));
float *x2 = (float*)malloc(size_div2 * sizeof(float));
float *y = (float*)malloc(size * sizeof(float));
float *d_x, *d_x1, *d_x2;
cudaMalloc(&d_x, size * sizeof(float));
cudaMalloc(&d_x1, size_div1 * sizeof(float));
cudaMalloc(&d_x2, size_div2 * sizeof(float));
cout << "Generating Array\n";
srand(time(NULL));
for (int i = 0; i < size; i++) {
x[i] = rand() % RANGE;
y[i] = x[i];
}
for (int i = 1; i < size; i++) {
y[i] = y[i] + y[i - 1];
}
/*
for (int i = 1; i < size; i++) {
y[i] = y[i] + y[i - 1];
}
*/
cudaMemcpy(d_x, x, size * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_x1, x1, size_div1 * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_x2, x2, size_div2 * sizeof(float), cudaMemcpyHostToDevice);
cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size, nblocks_div1);
cudaDeviceSynchronize();
cout << "Down-Sweep\n" << endl;
downsweep <<<nblocks, TPB>>> (d_x);
cudaDeviceSynchronize();
/*
cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1, nblocks_div2);
cudaDeviceSynchronize();
cout << "Down-Sweep 2\n" << endl;
downsweep <<<nblocks_div1, TPB>>> (d_x1);
cudaDeviceSynchronize();
*/
cout << "Inclusive Sum 1\n" << endl;
incl_pfsum <<<nblocks_div1, TPB>>> (d_x1, size_div1);
cudaDeviceSynchronize();
cudaMemcpy(x1, d_x1, size_div1 * sizeof(float), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for (int i = 0; i < size_div1; i++) {
cout << i << " " << x1[i] << endl;
}
cout << "Inclusive Sum 2\n" << endl;
incl_pfsum <<<nblocks_div2, TPB>>> (d_x2, size_div2);
cudaDeviceSynchronize();
cudaMemcpy(x2, d_x2, size_div2 * sizeof(float), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for (int i = 0; i < size_div2; i++) {
cout << i << " " << x2[i] << endl;
}
cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
cudaDeviceSynchronize();
/*
cudaMemcpy(x1, d_x1, size_div1 * sizeof(float), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for (int i = 0; i < size_div1; i++) {
cout << i << " " << x1[i] << endl;
}
*/
cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
cudaDeviceSynchronize();
/*
for (int i = 0; i < size; i++) {
cout << i << " " << x[i] << endl;
}
*/
/*
thrust::inclusive_scan(x, x + size, x);
cudaDeviceSynchronize();
thrust::inclusive_scan(x, x + size, x);
cudaDeviceSynchronize();
*/
cudaMemcpy(x, d_x, size * sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < size; i++) {
cout << i << " " << x[i] << " " << y[i] << endl;
if (x[i] != y[i]) {
//cout << i << " " << x[i] << " " << y[i] << endl;
//cout << "Not the same" << endl;
//return 0;
}
}
cout << "arrays are the same" << endl;
return 0;
} | #include <iostream>
#include <ctime>
#include <cstdlib>
#include <cmath>
#include "hip/hip_runtime.h"
#include <thrust/scan.h>
using namespace std;
#define TPB 1024
#define RANGE 10
#define min(a,b) ((a < b) ? a : b)
__global__
void incl_pfsum (float * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
size = min(size, TPB);
__syncthreads();
for (int step = 2; step <= size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
if (tid % TPB == 0) { array[bsize - 1] = 0; }
__syncthreads();
for (int step = size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
//__syncthreads();
array[tid] += array[tid - (step / 2)];
//__syncthreads();
array[tid - (step / 2)] = tmp;
//__syncthreads();
}
__syncthreads();
}
__syncthreads();
}
__global__
void scat_part_sum(float * array, float * array_psums) {
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
array[tid] += array_psums[blockIdx.x];
__syncthreads();
}
__global__
void upsweep (float * array, float * array_aggr1, int size, int size_aggr1) {
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
for (int step = 2; step <= size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
__global__
void downsweep (float * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
__syncthreads();
/*
if (tid >= (1<<step) && (tid < size)) {
tmp = array[tid - (1<<step)];
__syncthreads();
array[tid] = tmp + array[tid];
__syncthreads();
}
*/
}
int main(int argc, char** argv)
{
if (argc != 2) {
cout << "Takes one argument - the number of elements in an array" << endl;
return 0;
}
int size = atoi(argv[1]);
int size_div1 = int(ceil(float(size) / float(TPB)));
int size_div2 = int(ceil(float(size_div1) / float(TPB)));
int nblocks = int(ceil(float(size) / float(TPB)));
int nblocks_div1 = int(ceil(float(nblocks) / float(TPB)));
int nblocks_div2 = int(ceil(float(nblocks_div1) / float(TPB)));
cout << "First stage blocks: " << nblocks << endl;
cout << "Second stage blocks: " << nblocks_div1 << endl;
cout << "Third stage blocks: " << nblocks_div2 << endl;
cout << "First stage size: " << size << endl;
cout << "Second stage size: " << size_div1 << endl;
cout << "Third stage size: " << size_div2 << endl;
cout << "Malloc'ing\n";
float *x = (float*)malloc(size * sizeof(float));
float *x1 = (float*)malloc(size_div1 * sizeof(float));
float *x2 = (float*)malloc(size_div2 * sizeof(float));
float *y = (float*)malloc(size * sizeof(float));
float *d_x, *d_x1, *d_x2;
hipMalloc(&d_x, size * sizeof(float));
hipMalloc(&d_x1, size_div1 * sizeof(float));
hipMalloc(&d_x2, size_div2 * sizeof(float));
cout << "Generating Array\n";
srand(time(NULL));
for (int i = 0; i < size; i++) {
x[i] = rand() % RANGE;
y[i] = x[i];
}
for (int i = 1; i < size; i++) {
y[i] = y[i] + y[i - 1];
}
/*
for (int i = 1; i < size; i++) {
y[i] = y[i] + y[i - 1];
}
*/
hipMemcpy(d_x, x, size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_x1, x1, size_div1 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_x2, x2, size_div2 * sizeof(float), hipMemcpyHostToDevice);
cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size, nblocks_div1);
hipDeviceSynchronize();
cout << "Down-Sweep\n" << endl;
downsweep <<<nblocks, TPB>>> (d_x);
hipDeviceSynchronize();
/*
cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1, nblocks_div2);
cudaDeviceSynchronize();
cout << "Down-Sweep 2\n" << endl;
downsweep <<<nblocks_div1, TPB>>> (d_x1);
cudaDeviceSynchronize();
*/
cout << "Inclusive Sum 1\n" << endl;
incl_pfsum <<<nblocks_div1, TPB>>> (d_x1, size_div1);
hipDeviceSynchronize();
hipMemcpy(x1, d_x1, size_div1 * sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for (int i = 0; i < size_div1; i++) {
cout << i << " " << x1[i] << endl;
}
cout << "Inclusive Sum 2\n" << endl;
incl_pfsum <<<nblocks_div2, TPB>>> (d_x2, size_div2);
hipDeviceSynchronize();
hipMemcpy(x2, d_x2, size_div2 * sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for (int i = 0; i < size_div2; i++) {
cout << i << " " << x2[i] << endl;
}
cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
hipDeviceSynchronize();
/*
cudaMemcpy(x1, d_x1, size_div1 * sizeof(float), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for (int i = 0; i < size_div1; i++) {
cout << i << " " << x1[i] << endl;
}
*/
cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
hipDeviceSynchronize();
/*
for (int i = 0; i < size; i++) {
cout << i << " " << x[i] << endl;
}
*/
/*
thrust::inclusive_scan(x, x + size, x);
cudaDeviceSynchronize();
thrust::inclusive_scan(x, x + size, x);
cudaDeviceSynchronize();
*/
hipMemcpy(x, d_x, size * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < size; i++) {
cout << i << " " << x[i] << " " << y[i] << endl;
if (x[i] != y[i]) {
//cout << i << " " << x[i] << " " << y[i] << endl;
//cout << "Not the same" << endl;
//return 0;
}
}
cout << "arrays are the same" << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <ctime>
#include <cstdlib>
#include <cmath>
#include "hip/hip_runtime.h"
#include <thrust/scan.h>
using namespace std;
#define TPB 1024
#define RANGE 10
#define min(a,b) ((a < b) ? a : b)
__global__
void incl_pfsum (float * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
size = min(size, TPB);
__syncthreads();
for (int step = 2; step <= size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
if (tid % TPB == 0) { array[bsize - 1] = 0; }
__syncthreads();
for (int step = size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
//__syncthreads();
array[tid] += array[tid - (step / 2)];
//__syncthreads();
array[tid - (step / 2)] = tmp;
//__syncthreads();
}
__syncthreads();
}
__syncthreads();
}
__global__
void scat_part_sum(float * array, float * array_psums) {
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
array[tid] += array_psums[blockIdx.x];
__syncthreads();
}
__global__
void upsweep (float * array, float * array_aggr1, int size, int size_aggr1) {
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
for (int step = 2; step <= size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
__global__
void downsweep (float * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
__syncthreads();
/*
if (tid >= (1<<step) && (tid < size)) {
tmp = array[tid - (1<<step)];
__syncthreads();
array[tid] = tmp + array[tid];
__syncthreads();
}
*/
}
int main(int argc, char** argv)
{
if (argc != 2) {
cout << "Takes one argument - the number of elements in an array" << endl;
return 0;
}
int size = atoi(argv[1]);
int size_div1 = int(ceil(float(size) / float(TPB)));
int size_div2 = int(ceil(float(size_div1) / float(TPB)));
int nblocks = int(ceil(float(size) / float(TPB)));
int nblocks_div1 = int(ceil(float(nblocks) / float(TPB)));
int nblocks_div2 = int(ceil(float(nblocks_div1) / float(TPB)));
cout << "First stage blocks: " << nblocks << endl;
cout << "Second stage blocks: " << nblocks_div1 << endl;
cout << "Third stage blocks: " << nblocks_div2 << endl;
cout << "First stage size: " << size << endl;
cout << "Second stage size: " << size_div1 << endl;
cout << "Third stage size: " << size_div2 << endl;
cout << "Malloc'ing\n";
float *x = (float*)malloc(size * sizeof(float));
float *x1 = (float*)malloc(size_div1 * sizeof(float));
float *x2 = (float*)malloc(size_div2 * sizeof(float));
float *y = (float*)malloc(size * sizeof(float));
float *d_x, *d_x1, *d_x2;
hipMalloc(&d_x, size * sizeof(float));
hipMalloc(&d_x1, size_div1 * sizeof(float));
hipMalloc(&d_x2, size_div2 * sizeof(float));
cout << "Generating Array\n";
srand(time(NULL));
for (int i = 0; i < size; i++) {
x[i] = rand() % RANGE;
y[i] = x[i];
}
for (int i = 1; i < size; i++) {
y[i] = y[i] + y[i - 1];
}
/*
for (int i = 1; i < size; i++) {
y[i] = y[i] + y[i - 1];
}
*/
hipMemcpy(d_x, x, size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_x1, x1, size_div1 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_x2, x2, size_div2 * sizeof(float), hipMemcpyHostToDevice);
cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size, nblocks_div1);
hipDeviceSynchronize();
cout << "Down-Sweep\n" << endl;
downsweep <<<nblocks, TPB>>> (d_x);
hipDeviceSynchronize();
/*
cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1, nblocks_div2);
cudaDeviceSynchronize();
cout << "Down-Sweep 2\n" << endl;
downsweep <<<nblocks_div1, TPB>>> (d_x1);
cudaDeviceSynchronize();
*/
cout << "Inclusive Sum 1\n" << endl;
incl_pfsum <<<nblocks_div1, TPB>>> (d_x1, size_div1);
hipDeviceSynchronize();
hipMemcpy(x1, d_x1, size_div1 * sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for (int i = 0; i < size_div1; i++) {
cout << i << " " << x1[i] << endl;
}
cout << "Inclusive Sum 2\n" << endl;
incl_pfsum <<<nblocks_div2, TPB>>> (d_x2, size_div2);
hipDeviceSynchronize();
hipMemcpy(x2, d_x2, size_div2 * sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for (int i = 0; i < size_div2; i++) {
cout << i << " " << x2[i] << endl;
}
cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
hipDeviceSynchronize();
/*
cudaMemcpy(x1, d_x1, size_div1 * sizeof(float), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for (int i = 0; i < size_div1; i++) {
cout << i << " " << x1[i] << endl;
}
*/
cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
hipDeviceSynchronize();
/*
for (int i = 0; i < size; i++) {
cout << i << " " << x[i] << endl;
}
*/
/*
thrust::inclusive_scan(x, x + size, x);
cudaDeviceSynchronize();
thrust::inclusive_scan(x, x + size, x);
cudaDeviceSynchronize();
*/
hipMemcpy(x, d_x, size * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < size; i++) {
cout << i << " " << x[i] << " " << y[i] << endl;
if (x[i] != y[i]) {
//cout << i << " " << x[i] << " " << y[i] << endl;
//cout << "Not the same" << endl;
//return 0;
}
}
cout << "arrays are the same" << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10incl_pfsumPfi
.globl _Z10incl_pfsumPfi
.p2align 8
.type _Z10incl_pfsumPfi,@function
_Z10incl_pfsumPfi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s3, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s2, s2, 0xffff
s_min_i32 s4, s5, 0x400
s_mul_i32 s2, s15, s2
s_cmp_lt_i32 s5, 2
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_cbranch_scc1 .LBB0_6
v_ashrrev_i32_e32 v6, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_nc_u32_e32 v4, v0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_xor_b32_e32 v7, v4, v6
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s3, s3, 1
s_waitcnt_vscnt null, 0x0
s_cmp_gt_i32 s3, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_ashr_i32 s6, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s3, s6
s_xor_b32 s6, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, s6
s_sub_i32 s7, 0, s6
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v7, v4
v_mul_lo_u32 v4, v4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v7, v4
v_subrev_nc_u32_e32 v5, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_subrev_nc_u32_e32 v5, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_add_i32 s6, s3, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_xor_b32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v6
v_cmp_eq_u32_e32 vcc_lo, s6, v4
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
s_lshr_b32 s7, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s7, v0
v_cmp_le_i32_e32 vcc_lo, s2, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[2:3], v4, off
s_branch .LBB0_2
.LBB0_6:
v_and_b32_e32 v2, 0x3ff, v0
s_mov_b32 s6, exec_lo
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_8
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v2, 0
s_lshl_b64 s[8:9], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
global_store_b32 v2, v2, s[8:9] offset:-4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_i32 s5, 1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
v_ashrrev_i32_e32 v5, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v0, v5
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_xor_b32_e32 v6, v3, v5
s_branch .LBB0_11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s4, 1
s_cmp_lt_u32 s4, 2
s_mov_b32 s4, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
.LBB0_11:
s_ashr_i32 s3, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s4, s3
s_xor_b32 s3, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v3, s3
s_sub_i32 s5, 0, s3
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v4, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v6, v3
v_mul_lo_u32 v3, v3, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v6, v3
v_subrev_nc_u32_e32 v4, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_add_i32 s3, s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_cmp_eq_u32_e32 vcc_lo, s3, v3
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_10
s_lshr_b32 s5, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v3, s5, v0
v_cmp_le_i32_e32 vcc_lo, s2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_b32 v7, v[1:2], off
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(1)
v_cvt_i32_f32_e32 v9, v7
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_i32_e32 v8, v9
s_clause 0x1
global_store_b32 v[1:2], v7, off
global_store_b32 v[3:4], v8, off
s_branch .LBB0_10
.LBB0_14:
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10incl_pfsumPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10incl_pfsumPfi, .Lfunc_end0-_Z10incl_pfsumPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13scat_part_sumPfS_
.globl _Z13scat_part_sumPfS_
.p2align 8
.type _Z13scat_part_sumPfS_,@function
_Z13scat_part_sumPfS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mov_b32 s5, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
global_load_b32 v2, v[0:1], off
s_addc_u32 s1, s3, s1
s_load_b32 s0, s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13scat_part_sumPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13scat_part_sumPfS_, .Lfunc_end1-_Z13scat_part_sumPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7upsweepPfS_ii
.globl _Z7upsweepPfS_ii
.p2align 8
.type _Z7upsweepPfS_ii,@function
_Z7upsweepPfS_ii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s5, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s4, 2
s_mul_i32 s3, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s3, v0
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB2_6
v_ashrrev_i32_e32 v7, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v5, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_xor_b32_e32 v8, v5, v7
s_branch .LBB2_3
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s8
s_lshl_b32 s5, s5, 1
s_waitcnt_vscnt null, 0x0
s_cmp_gt_i32 s5, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_6
.LBB2_3:
s_ashr_i32 s8, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s5, s8
s_xor_b32 s8, s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v5, s8
s_sub_i32 s9, 0, s8
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v5, v5
v_mul_lo_u32 v6, s9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v6
v_add_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v8, v5
v_mul_lo_u32 v5, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v8, v5
v_subrev_nc_u32_e32 v6, s8, v5
v_cmp_le_u32_e32 vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s8, v5
v_cmp_le_u32_e32 vcc_lo, s8, v5
s_add_i32 s8, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_xor_b32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v7
v_cmp_eq_u32_e32 vcc_lo, s8, v5
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB2_2
s_lshr_b32 s9, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v5, s9, v1
v_cmp_le_i32_e32 vcc_lo, s3, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
global_store_b32 v[3:4], v5, off
s_branch .LBB2_2
.LBB2_6:
s_mov_b32 s8, exec_lo
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0x3ff, v0
s_cbranch_execz .LBB2_8
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_ashr_i32 s5, s4, 31
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[10:11], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_u32 s3, s6, s10
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v3, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_addc_u32 s5, s7, s11
s_add_u32 s3, s3, -4
s_addc_u32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e32 v1, s5, v2, vcc_lo
v_cndmask_b32_e32 v0, s3, v0, vcc_lo
s_mov_b32 s3, 0
s_lshl_b64 s[2:3], s[2:3], 2
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7upsweepPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7upsweepPfS_ii, .Lfunc_end2-_Z7upsweepPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9downsweepPf
.globl _Z9downsweepPf
.p2align 8
.type _Z9downsweepPf,@function
_Z9downsweepPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s1, s15, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s0, s4, 0xffff
s_movk_i32 s4, 0x200
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s1, s1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v0, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v0
v_xor_b32_e32 v6, v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_branch .LBB3_2
.LBB3_1:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_lt_u32 s4, 4
s_mov_b32 s4, s5
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB3_4
.LBB3_2:
v_cvt_f32_u32_e32 v4, s4
s_sub_i32 s0, 0, s4
s_lshr_b32 s5, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s0, v4
s_add_i32 s0, s4, -1
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s4
v_sub_nc_u32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v0
v_sub_nc_u32_e32 v5, v4, v0
v_add_nc_u32_e32 v4, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, s0, v5
v_cmp_gt_i32_e64 s0, s1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, vcc_lo, s0
s_and_saveexec_b32 s0, s6
s_cbranch_execz .LBB3_1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v7, v[2:3], off
global_load_b32 v8, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v7, v8
global_store_b32 v[4:5], v7, off
s_branch .LBB3_1
.LBB3_4:
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9downsweepPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z9downsweepPf, .Lfunc_end3-_Z9downsweepPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10incl_pfsumPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10incl_pfsumPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13scat_part_sumPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13scat_part_sumPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7upsweepPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7upsweepPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9downsweepPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9downsweepPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <ctime>
#include <cstdlib>
#include <cmath>
#include "hip/hip_runtime.h"
#include <thrust/scan.h>
using namespace std;
#define TPB 1024
#define RANGE 10
#define min(a,b) ((a < b) ? a : b)
__global__
void incl_pfsum (float * array, int size) {
int bsize = blockIdx.x * blockDim.x;
int tid = bsize + threadIdx.x;
int tmp;
size = min(size, TPB);
__syncthreads();
for (int step = 2; step <= size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
if (tid % TPB == 0) { array[bsize - 1] = 0; }
__syncthreads();
for (int step = size; step > 0; step /= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bsize)) {
tmp = array[tid];
//__syncthreads();
array[tid] += array[tid - (step / 2)];
//__syncthreads();
array[tid - (step / 2)] = tmp;
//__syncthreads();
}
__syncthreads();
}
__syncthreads();
}
__global__
void scat_part_sum(float * array, float * array_psums) {
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
array[tid] += array_psums[blockIdx.x];
__syncthreads();
}
__global__
void upsweep (float * array, float * array_aggr1, int size, int size_aggr1) {
int bid = blockIdx.x * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
for (int step = 2; step <= size ; step *= 2) {
if (tid % step == (step - 1) && (tid - (step / 2) >= bid)) {
array[tid] += array[tid - (step / 2)];
}
__syncthreads();
}
__syncthreads();
if (threadIdx.x == (TPB - 1)) {
if (tid < size) {
array_aggr1[blockIdx.x] = array[tid];
}
else {
array_aggr1[blockIdx.x] = array[size - 1];
}
}
__syncthreads();
}
__global__
void downsweep (float * array) {
int next_bid = (blockIdx.x + 1) * blockDim.x;
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
__syncthreads();
for (int step = TPB / 2; step > 1; step /= 2) {
if (tid % step == (step - 1) && (tid + (step / 2) < next_bid)) {
array[tid + (step / 2)] += array[tid];
}
__syncthreads();
}
__syncthreads();
/*
if (tid >= (1<<step) && (tid < size)) {
tmp = array[tid - (1<<step)];
__syncthreads();
array[tid] = tmp + array[tid];
__syncthreads();
}
*/
}
int main(int argc, char** argv)
{
if (argc != 2) {
cout << "Takes one argument - the number of elements in an array" << endl;
return 0;
}
int size = atoi(argv[1]);
int size_div1 = int(ceil(float(size) / float(TPB)));
int size_div2 = int(ceil(float(size_div1) / float(TPB)));
int nblocks = int(ceil(float(size) / float(TPB)));
int nblocks_div1 = int(ceil(float(nblocks) / float(TPB)));
int nblocks_div2 = int(ceil(float(nblocks_div1) / float(TPB)));
cout << "First stage blocks: " << nblocks << endl;
cout << "Second stage blocks: " << nblocks_div1 << endl;
cout << "Third stage blocks: " << nblocks_div2 << endl;
cout << "First stage size: " << size << endl;
cout << "Second stage size: " << size_div1 << endl;
cout << "Third stage size: " << size_div2 << endl;
cout << "Malloc'ing\n";
float *x = (float*)malloc(size * sizeof(float));
float *x1 = (float*)malloc(size_div1 * sizeof(float));
float *x2 = (float*)malloc(size_div2 * sizeof(float));
float *y = (float*)malloc(size * sizeof(float));
float *d_x, *d_x1, *d_x2;
hipMalloc(&d_x, size * sizeof(float));
hipMalloc(&d_x1, size_div1 * sizeof(float));
hipMalloc(&d_x2, size_div2 * sizeof(float));
cout << "Generating Array\n";
srand(time(NULL));
for (int i = 0; i < size; i++) {
x[i] = rand() % RANGE;
y[i] = x[i];
}
for (int i = 1; i < size; i++) {
y[i] = y[i] + y[i - 1];
}
/*
for (int i = 1; i < size; i++) {
y[i] = y[i] + y[i - 1];
}
*/
hipMemcpy(d_x, x, size * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_x1, x1, size_div1 * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_x2, x2, size_div2 * sizeof(float), hipMemcpyHostToDevice);
cout << "Up-Sweep\n" << endl;
upsweep <<<nblocks, TPB>>> (d_x, d_x1, size, nblocks_div1);
hipDeviceSynchronize();
cout << "Down-Sweep\n" << endl;
downsweep <<<nblocks, TPB>>> (d_x);
hipDeviceSynchronize();
/*
cout << "Up-Sweep 2\n" << endl;
upsweep <<<nblocks_div1, TPB>>> (d_x1, d_x2, size_div1, nblocks_div2);
cudaDeviceSynchronize();
cout << "Down-Sweep 2\n" << endl;
downsweep <<<nblocks_div1, TPB>>> (d_x1);
cudaDeviceSynchronize();
*/
cout << "Inclusive Sum 1\n" << endl;
incl_pfsum <<<nblocks_div1, TPB>>> (d_x1, size_div1);
hipDeviceSynchronize();
hipMemcpy(x1, d_x1, size_div1 * sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for (int i = 0; i < size_div1; i++) {
cout << i << " " << x1[i] << endl;
}
cout << "Inclusive Sum 2\n" << endl;
incl_pfsum <<<nblocks_div2, TPB>>> (d_x2, size_div2);
hipDeviceSynchronize();
hipMemcpy(x2, d_x2, size_div2 * sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for (int i = 0; i < size_div2; i++) {
cout << i << " " << x2[i] << endl;
}
cout << "Scatter Partial Sums 2\n" << endl;
scat_part_sum <<<nblocks_div1, TPB>>> (d_x1, d_x2);
hipDeviceSynchronize();
/*
cudaMemcpy(x1, d_x1, size_div1 * sizeof(float), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for (int i = 0; i < size_div1; i++) {
cout << i << " " << x1[i] << endl;
}
*/
cout << "Scatter Partial Sums 1\n" << endl;
scat_part_sum <<<nblocks, TPB>>> (d_x, d_x1);
hipDeviceSynchronize();
/*
for (int i = 0; i < size; i++) {
cout << i << " " << x[i] << endl;
}
*/
/*
thrust::inclusive_scan(x, x + size, x);
cudaDeviceSynchronize();
thrust::inclusive_scan(x, x + size, x);
cudaDeviceSynchronize();
*/
hipMemcpy(x, d_x, size * sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < size; i++) {
cout << i << " " << x[i] << " " << y[i] << endl;
if (x[i] != y[i]) {
//cout << i << " " << x[i] << " " << y[i] << endl;
//cout << "Not the same" << endl;
//return 0;
}
}
cout << "arrays are the same" << endl;
return 0;
} | .text
.file "hw1_par.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__incl_pfsumPfi # -- Begin function _Z25__device_stub__incl_pfsumPfi
.p2align 4, 0x90
.type _Z25__device_stub__incl_pfsumPfi,@function
_Z25__device_stub__incl_pfsumPfi: # @_Z25__device_stub__incl_pfsumPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10incl_pfsumPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__incl_pfsumPfi, .Lfunc_end0-_Z25__device_stub__incl_pfsumPfi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__scat_part_sumPfS_ # -- Begin function _Z28__device_stub__scat_part_sumPfS_
.p2align 4, 0x90
.type _Z28__device_stub__scat_part_sumPfS_,@function
_Z28__device_stub__scat_part_sumPfS_: # @_Z28__device_stub__scat_part_sumPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13scat_part_sumPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z28__device_stub__scat_part_sumPfS_, .Lfunc_end1-_Z28__device_stub__scat_part_sumPfS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__upsweepPfS_ii # -- Begin function _Z22__device_stub__upsweepPfS_ii
.p2align 4, 0x90
.type _Z22__device_stub__upsweepPfS_ii,@function
_Z22__device_stub__upsweepPfS_ii: # @_Z22__device_stub__upsweepPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7upsweepPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__upsweepPfS_ii, .Lfunc_end2-_Z22__device_stub__upsweepPfS_ii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__downsweepPf # -- Begin function _Z24__device_stub__downsweepPf
.p2align 4, 0x90
.type _Z24__device_stub__downsweepPf,@function
_Z24__device_stub__downsweepPf: # @_Z24__device_stub__downsweepPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9downsweepPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z24__device_stub__downsweepPf, .Lfunc_end3-_Z24__device_stub__downsweepPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB4_4
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
cvtsi2ss %r13d, %xmm0
mulss .LCPI4_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
cvttps2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm0
mulss .LCPI4_0(%rip), %xmm0
callq ceilf@PLT
movaps %xmm0, 160(%rsp) # 16-byte Spill
cvttps2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm0
mulss .LCPI4_0(%rip), %xmm0
callq ceilf@PLT
movss %xmm0, 80(%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i149
cvttss2si 160(%rsp), %r15d # 16-byte Folded Reload
cmpb $0, 56(%rbx)
je .LBB4_7
# %bb.3:
movzbl 67(%rbx), %ecx
jmp .LBB4_8
.LBB4_4:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $55, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_94
.LBB4_6:
movzbl 67(%rbx), %eax
jmp .LBB4_95
.LBB4_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit152
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i154
cvttss2si 80(%rsp), %ebp # 4-byte Folded Reload
cmpb $0, 56(%rbx)
je .LBB4_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB4_12
.LBB4_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit157
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i159
cmpb $0, 56(%rbx)
je .LBB4_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB4_16
.LBB4_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit162
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r13d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i164
cmpb $0, 56(%rbx)
je .LBB4_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB4_20
.LBB4_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit167
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i169
cmpb $0, 56(%rbx)
je .LBB4_23
# %bb.22:
movzbl 67(%rbx), %ecx
jmp .LBB4_24
.LBB4_23:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit172
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i174
cmpb $0, 56(%rbx)
movl %ebp, 148(%rsp) # 4-byte Spill
je .LBB4_27
# %bb.26:
movzbl 67(%rbx), %ecx
jmp .LBB4_28
.LBB4_27:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit177
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq %r13d, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
movl %r12d, 68(%rsp) # 4-byte Spill
movslq %r12d, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, 160(%rsp) # 8-byte Spill
movl %r15d, 64(%rsp) # 4-byte Spill
movslq %r15d, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %r15
leaq 88(%rsp), %rdi
movq %rbx, 192(%rsp) # 8-byte Spill
movq %rbx, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 136(%rsp), %rdi
movq %r14, 200(%rsp) # 8-byte Spill
movq %r14, %rsi
callq hipMalloc
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r13d, %r13d
jle .LBB4_31
# %bb.29: # %.lr.ph.preheader
movl %r13d, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_30: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%r14,4)
movss %xmm0, (%r15,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB4_30
.LBB4_31: # %.preheader
cmpl $2, %r13d
jl .LBB4_34
# %bb.32: # %.lr.ph263.preheader
movl %r13d, %eax
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $1, %ecx
.p2align 4, 0x90
.LBB4_33: # %.lr.ph263
# =>This Inner Loop Header: Depth=1
addss (%r15,%rcx,4), %xmm0
movss %xmm0, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_33
.LBB4_34: # %._crit_edge
movq 88(%rsp), %rdi
movq %rbp, %rsi
movq 192(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movq 160(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 136(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq 200(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i179
cmpb $0, 56(%rbx)
je .LBB4_37
# %bb.36:
movzbl 67(%rbx), %eax
jmp .LBB4_38
.LBB4_37:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit182
movabsq $4294968320, %rbx # imm = 0x100000400
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 68(%rsp), %r14d # 4-byte Reload
leaq (%r14,%rbx), %rdi
addq $-1024, %rdi # imm = 0xFC00
movq %rdi, 184(%rsp) # 8-byte Spill
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_40
# %bb.39:
movq 88(%rsp), %rax
movq 72(%rsp), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r13d, 156(%rsp)
movl 64(%rsp), %eax # 4-byte Reload
movl %eax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 156(%rsp), %rax
movq %rax, 112(%rsp)
leaq 152(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7upsweepPfS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_40:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i184
cmpb $0, 56(%rbx)
je .LBB4_43
# %bb.42:
movzbl 67(%rbx), %eax
jmp .LBB4_44
.LBB4_43:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit187
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 184(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_46
# %bb.45:
movq 88(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 96(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z9downsweepPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_46:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i189
cmpb $0, 56(%rbx)
movq %r13, 216(%rsp) # 8-byte Spill
je .LBB4_49
# %bb.48:
movzbl 67(%rbx), %eax
jmp .LBB4_50
.LBB4_49:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_50: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit192
movq %rbp, 224(%rsp) # 8-byte Spill
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 64(%rsp), %r13d # 4-byte Reload
movabsq $4294968320, %rdx # imm = 0x100000400
leaq (%rdx,%r13), %rdi
addq $-1024, %rdi # imm = 0xFC00
movq %rdi, 208(%rsp) # 8-byte Spill
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_52
# %bb.51:
movq 72(%rsp), %rax
movq %rax, 32(%rsp)
movl 68(%rsp), %eax # 4-byte Reload
movl %eax, 56(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 24(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10incl_pfsumPfi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_52:
callq hipDeviceSynchronize
movq 72(%rsp), %rsi
movq 160(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
cmpl $0, 68(%rsp) # 4-byte Folded Reload
jle .LBB4_59
# %bb.53: # %.lr.ph266.preheader
xorl %r12d, %r12d
jmp .LBB4_56
.p2align 4, 0x90
.LBB4_54: # in Loop: Header=BB4_56 Depth=1
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_55: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit202
# in Loop: Header=BB4_56 Depth=1
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq %r12, %r14
je .LBB4_59
.LBB4_56: # %.lr.ph266
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.12, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 160(%rsp), %rax # 8-byte Reload
movss (%rax,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .LBB4_96
# %bb.57: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i199
# in Loop: Header=BB4_56 Depth=1
cmpb $0, 56(%rbp)
je .LBB4_54
# %bb.58: # in Loop: Header=BB4_56 Depth=1
movzbl 67(%rbp), %eax
jmp .LBB4_55
.LBB4_59: # %._crit_edge267
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.60: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i194
cmpb $0, 56(%rbx)
movq 224(%rsp), %rbp # 8-byte Reload
movq 80(%rsp), %r14 # 8-byte Reload
je .LBB4_62
# %bb.61:
movzbl 67(%rbx), %eax
jmp .LBB4_63
.LBB4_62:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_63: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit197
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 148(%rsp), %eax # 4-byte Reload
movabsq $4294968320, %rdx # imm = 0x100000400
leaq (%rdx,%rax), %rdi
addq $-1024, %rdi # imm = 0xFC00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_65
# %bb.64:
movq 136(%rsp), %rax
movq %rax, 32(%rsp)
movl 64(%rsp), %eax # 4-byte Reload
movl %eax, 56(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 24(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10incl_pfsumPfi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_65:
callq hipDeviceSynchronize
movq 136(%rsp), %rsi
movq %r14, %rdi
movq 200(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
cmpl $0, 64(%rsp) # 4-byte Folded Reload
jle .LBB4_72
# %bb.66: # %.lr.ph270.preheader
xorl %ebx, %ebx
jmp .LBB4_69
.p2align 4, 0x90
.LBB4_67: # in Loop: Header=BB4_69 Depth=1
movzbl 67(%r12), %ecx
.LBB4_68: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit212
# in Loop: Header=BB4_69 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq %rbx, %r13
je .LBB4_72
.LBB4_69: # %.lr.ph270
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.12, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB4_96
# %bb.70: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i209
# in Loop: Header=BB4_69 Depth=1
cmpb $0, 56(%r12)
jne .LBB4_67
# %bb.71: # in Loop: Header=BB4_69 Depth=1
movq %r12, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
movq 80(%rsp), %r14 # 8-byte Reload
jmp .LBB4_68
.LBB4_72: # %._crit_edge271
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.73: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i204
cmpb $0, 56(%rbx)
movq 216(%rsp), %r14 # 8-byte Reload
je .LBB4_75
# %bb.74:
movzbl 67(%rbx), %eax
jmp .LBB4_76
.LBB4_75:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_76: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit207
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 208(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_78
# %bb.77:
movq 72(%rsp), %rax
movq 136(%rsp), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13scat_part_sumPfS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_78:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.79: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i214
cmpb $0, 56(%rbx)
je .LBB4_81
# %bb.80:
movzbl 67(%rbx), %eax
jmp .LBB4_82
.LBB4_81:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_82: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit217
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 184(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_84
# %bb.83:
movq 88(%rsp), %rax
movq 72(%rsp), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13scat_part_sumPfS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_84:
callq hipDeviceSynchronize
movq 88(%rsp), %rsi
movq %rbp, %rdi
movq 192(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB4_91
# %bb.85: # %.lr.ph274.preheader
movl %r14d, %r14d
xorl %ebx, %ebx
jmp .LBB4_88
.p2align 4, 0x90
.LBB4_86: # in Loop: Header=BB4_88 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB4_87: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit227
# in Loop: Header=BB4_88 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq %rbx, %r14
je .LBB4_91
.LBB4_88: # %.lr.ph274
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.12, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.12, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB4_96
# %bb.89: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i224
# in Loop: Header=BB4_88 Depth=1
cmpb $0, 56(%r12)
je .LBB4_86
# %bb.90: # in Loop: Header=BB4_88 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB4_87
.LBB4_91: # %._crit_edge275
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_96
# %bb.92: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i219
cmpb $0, 56(%rbx)
jne .LBB4_6
.LBB4_94:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_95: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_96:
.cfi_def_cfa_offset 288
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10incl_pfsumPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13scat_part_sumPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7upsweepPfS_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9downsweepPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10incl_pfsumPfi,@object # @_Z10incl_pfsumPfi
.section .rodata,"a",@progbits
.globl _Z10incl_pfsumPfi
.p2align 3, 0x0
_Z10incl_pfsumPfi:
.quad _Z25__device_stub__incl_pfsumPfi
.size _Z10incl_pfsumPfi, 8
.type _Z13scat_part_sumPfS_,@object # @_Z13scat_part_sumPfS_
.globl _Z13scat_part_sumPfS_
.p2align 3, 0x0
_Z13scat_part_sumPfS_:
.quad _Z28__device_stub__scat_part_sumPfS_
.size _Z13scat_part_sumPfS_, 8
.type _Z7upsweepPfS_ii,@object # @_Z7upsweepPfS_ii
.globl _Z7upsweepPfS_ii
.p2align 3, 0x0
_Z7upsweepPfS_ii:
.quad _Z22__device_stub__upsweepPfS_ii
.size _Z7upsweepPfS_ii, 8
.type _Z9downsweepPf,@object # @_Z9downsweepPf
.globl _Z9downsweepPf
.p2align 3, 0x0
_Z9downsweepPf:
.quad _Z24__device_stub__downsweepPf
.size _Z9downsweepPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Takes one argument - the number of elements in an array"
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "First stage blocks: "
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Second stage blocks: "
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Third stage blocks: "
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "First stage size: "
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Second stage size: "
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Third stage size: "
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Malloc'ing\n"
.size .L.str.7, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Generating Array\n"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Up-Sweep\n"
.size .L.str.9, 10
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Down-Sweep\n"
.size .L.str.10, 12
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Inclusive Sum 1\n"
.size .L.str.11, 17
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " "
.size .L.str.12, 2
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Inclusive Sum 2\n"
.size .L.str.13, 17
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Scatter Partial Sums 2\n"
.size .L.str.14, 24
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Scatter Partial Sums 1\n"
.size .L.str.15, 24
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "arrays are the same"
.size .L.str.16, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10incl_pfsumPfi"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13scat_part_sumPfS_"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7upsweepPfS_ii"
.size .L__unnamed_3, 17
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z9downsweepPf"
.size .L__unnamed_4, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__incl_pfsumPfi
.addrsig_sym _Z28__device_stub__scat_part_sumPfS_
.addrsig_sym _Z22__device_stub__upsweepPfS_ii
.addrsig_sym _Z24__device_stub__downsweepPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10incl_pfsumPfi
.addrsig_sym _Z13scat_part_sumPfS_
.addrsig_sym _Z7upsweepPfS_ii
.addrsig_sym _Z9downsweepPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <time.h>
#include <string>
__global__ void matrixMultGPU (double *A, double *B, double *C, int N){
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < N && row < N){
double acc = 0.0;
for(int k=0;k<N;k++)
acc += A[row*N+k] * B[k*N+col];
C[row*N+col] = acc;
}
}
void matrixMultCPU(double *A, double *B, double *C, int N){
double acc;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
acc=0.0;
for(int k=0;k<N;k++)
acc += A[i*N+k]*B[k*N+j];
C[i*N+j] = acc;
}
}
}
std::string testValues(double *A, double *B, int N){
for(int i = 0; i < N*N; ++i)
if(A[i]!=B[i])
return "Mal Cálculo";
return "Buen Cálculo";
}
int main(int argc, char **argv){
cudaError_t error = cudaSuccess;
double *A, *B, *C1, *C2;
double *d_A, *d_B, *d_C;
double CPU, GPU;
if(argc != 2) {
printf("No size given\n");
return -1;
}
int N = atoi(argv[1]);
double size = N*N*sizeof(double);
A = (double*)malloc(size);
B = (double*)malloc(size);
C1 = (double*)malloc(size);
C2 = (double*)malloc(size);
for(int i=0;i<N*N;i++){
A[i]=1;
B[i]=2;
}
//CPU----------------------------
clock_t tic = clock();
matrixMultCPU(A,B,C1, N);
clock_t toc = clock();
//printf("Tiempo CPU: %f segundos", (double)(toc - tic) / CLOCKS_PER_SEC);
CPU = (double)(toc - tic) / CLOCKS_PER_SEC;
printf("%f,",CPU);
//-------------------------------
error = cudaMalloc((void**)&d_A,size);
if(error != cudaSuccess){
printf("Error in cudaMalloc for d_A\n");
exit(0);
}
error = cudaMalloc((void**)&d_B,size);
if(error != cudaSuccess){
printf("Error in cudaMalloc for d_B\n");
exit(0);
}
error = cudaMalloc((void**)&d_C,size);
if(error != cudaSuccess){
printf("Error in cudaMalloc for d_C\n");
exit(0);
}
error = cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error in cudaMemcpy for d_A\n");
exit(0);
}
error = cudaMemcpy(d_B,B,size,cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error in cudaMemcpy for d_B\n");
exit(0);
}
//GPU----------------------------
dim3 dimBlock(32,32);
dim3 dimGrid(ceil(N/float(dimBlock.x)),ceil(N/float(dimBlock.y)));
clock_t tic2 = clock();
matrixMultGPU<<<dimGrid,dimBlock>>>(d_A,d_B,d_C,N);
cudaDeviceSynchronize();
error = cudaMemcpy(C2,d_C,size,cudaMemcpyDeviceToHost);
if(error != cudaSuccess){
printf("Error in cudaMemcpy for C2\n");
exit(0);
}
clock_t toc2 = clock();
//printf("\n\nTiempo GPU: %f segundos\n", (double)(toc2 - tic2) / CLOCKS_PER_SEC);
GPU = (double)(toc2 - tic2) / CLOCKS_PER_SEC;
printf("%f,%f,%s\n",GPU,(CPU/GPU), testValues(C1,C2,N).c_str());
//--------------------------------
/*
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",A[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",B[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C1[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C2[i]);
}
printf("\n---------\n");
*/
free(A);
free(B);
free(C1);
free(C2);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
return 0;
} | code for sm_80
Function : _Z13matrixMultGPUPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <time.h>
#include <string>
__global__ void matrixMultGPU (double *A, double *B, double *C, int N){
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < N && row < N){
double acc = 0.0;
for(int k=0;k<N;k++)
acc += A[row*N+k] * B[k*N+col];
C[row*N+col] = acc;
}
}
void matrixMultCPU(double *A, double *B, double *C, int N){
double acc;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
acc=0.0;
for(int k=0;k<N;k++)
acc += A[i*N+k]*B[k*N+j];
C[i*N+j] = acc;
}
}
}
std::string testValues(double *A, double *B, int N){
for(int i = 0; i < N*N; ++i)
if(A[i]!=B[i])
return "Mal Cálculo";
return "Buen Cálculo";
}
int main(int argc, char **argv){
cudaError_t error = cudaSuccess;
double *A, *B, *C1, *C2;
double *d_A, *d_B, *d_C;
double CPU, GPU;
if(argc != 2) {
printf("No size given\n");
return -1;
}
int N = atoi(argv[1]);
double size = N*N*sizeof(double);
A = (double*)malloc(size);
B = (double*)malloc(size);
C1 = (double*)malloc(size);
C2 = (double*)malloc(size);
for(int i=0;i<N*N;i++){
A[i]=1;
B[i]=2;
}
//CPU----------------------------
clock_t tic = clock();
matrixMultCPU(A,B,C1, N);
clock_t toc = clock();
//printf("Tiempo CPU: %f segundos", (double)(toc - tic) / CLOCKS_PER_SEC);
CPU = (double)(toc - tic) / CLOCKS_PER_SEC;
printf("%f,",CPU);
//-------------------------------
error = cudaMalloc((void**)&d_A,size);
if(error != cudaSuccess){
printf("Error in cudaMalloc for d_A\n");
exit(0);
}
error = cudaMalloc((void**)&d_B,size);
if(error != cudaSuccess){
printf("Error in cudaMalloc for d_B\n");
exit(0);
}
error = cudaMalloc((void**)&d_C,size);
if(error != cudaSuccess){
printf("Error in cudaMalloc for d_C\n");
exit(0);
}
error = cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error in cudaMemcpy for d_A\n");
exit(0);
}
error = cudaMemcpy(d_B,B,size,cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error in cudaMemcpy for d_B\n");
exit(0);
}
//GPU----------------------------
dim3 dimBlock(32,32);
dim3 dimGrid(ceil(N/float(dimBlock.x)),ceil(N/float(dimBlock.y)));
clock_t tic2 = clock();
matrixMultGPU<<<dimGrid,dimBlock>>>(d_A,d_B,d_C,N);
cudaDeviceSynchronize();
error = cudaMemcpy(C2,d_C,size,cudaMemcpyDeviceToHost);
if(error != cudaSuccess){
printf("Error in cudaMemcpy for C2\n");
exit(0);
}
clock_t toc2 = clock();
//printf("\n\nTiempo GPU: %f segundos\n", (double)(toc2 - tic2) / CLOCKS_PER_SEC);
GPU = (double)(toc2 - tic2) / CLOCKS_PER_SEC;
printf("%f,%f,%s\n",GPU,(CPU/GPU), testValues(C1,C2,N).c_str());
//--------------------------------
/*
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",A[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",B[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C1[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C2[i]);
}
printf("\n---------\n");
*/
free(A);
free(B);
free(C1);
free(C2);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
return 0;
} | .file "tmpxft_0009422a_00000000-6_matrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13matrixMultCPUPdS_S_i
.type _Z13matrixMultCPUPdS_S_i, @function
_Z13matrixMultCPUPdS_S_i:
.LFB3056:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r9
movl %ecx, %r12d
movslq %ecx, %r11
leaq 0(,%r11,8), %rcx
movq %rdi, %r10
leaq (%rdi,%rcx), %rsi
movl $0, %ebp
.L5:
movq %rbx, %r8
movl $0, %edi
.L8:
movq %r8, %rdx
movq %r10, %rax
pxor %xmm1, %xmm1
.L6:
movsd (%rax), %xmm0
mulsd (%rdx), %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
addq %rcx, %rdx
cmpq %rsi, %rax
jne .L6
movsd %xmm1, (%r9,%rdi,8)
addq $1, %rdi
addq $8, %r8
cmpq %r11, %rdi
jne .L8
addl $1, %ebp
addq %rcx, %r9
addq %rcx, %r10
addq %rcx, %rsi
cmpl %ebp, %r12d
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3056:
.size _Z13matrixMultCPUPdS_S_i, .-_Z13matrixMultCPUPdS_S_i
.globl _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i
.type _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i, @function
_Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i:
.LFB3083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13matrixMultGPUPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3083:
.size _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i, .-_Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i
.globl _Z13matrixMultGPUPdS_S_i
.type _Z13matrixMultGPUPdS_S_i, @function
_Z13matrixMultGPUPdS_S_i:
.LFB3084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3084:
.size _Z13matrixMultGPUPdS_S_i, .-_Z13matrixMultGPUPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13matrixMultGPUPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matrixMultGPUPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB3461:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L31
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L27
movzbl (%rsi), %eax
movb %al, (%rdi)
.L28:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L26:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L28
.L27:
testq %rdx, %rdx
je .L28
jmp .L26
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3461:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .rodata.str1.1
.LC2:
.string "Mal C\303\241lculo"
.LC3:
.string "Buen C\303\241lculo"
.text
.globl _Z10testValuesB5cxx11PdS_i
.type _Z10testValuesB5cxx11PdS_i, @function
_Z10testValuesB5cxx11PdS_i:
.LFB3057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
imull %ecx, %ecx
testl %ecx, %ecx
jle .L34
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
.L38:
movsd (%rsi,%rax), %xmm0
ucomisd (%rdx,%rax), %xmm0
jp .L39
jne .L39
addq $8, %rax
cmpq %rcx, %rax
jne .L38
.L34:
leaq 16(%rbx), %rax
movq %rax, (%rbx)
leaq 13+.LC3(%rip), %rdx
leaq -13(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.L33:
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
leaq 16(%rbx), %rax
movq %rax, (%rbx)
leaq 12+.LC2(%rip), %rdx
leaq -12(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
jmp .L33
.cfi_endproc
.LFE3057:
.size _Z10testValuesB5cxx11PdS_i, .-_Z10testValuesB5cxx11PdS_i
.section .rodata.str1.1
.LC4:
.string "No size given\n"
.LC9:
.string "%f,"
.LC10:
.string "Error in cudaMalloc for d_A\n"
.LC11:
.string "Error in cudaMalloc for d_B\n"
.LC12:
.string "Error in cudaMalloc for d_C\n"
.LC13:
.string "Error in cudaMemcpy for d_A\n"
.LC14:
.string "Error in cudaMemcpy for d_B\n"
.LC16:
.string "Error in cudaMemcpy for C2\n"
.LC17:
.string "%f,%f,%s\n"
.text
.globl main
.type main, @function
main:
.LFB3058:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3058
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L64
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 4(%rsp)
movl %eax, %r15d
imull %eax, %r15d
movslq %r15d, %rbx
salq $3, %rbx
js .L45
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L46:
comisd .LC5(%rip), %xmm0
jnb .L47
cvttsd2siq %xmm0, %r13
.L48:
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testl %r15d, %r15d
jle .L49
movl $0, %eax
movsd .LC6(%rip), %xmm1
movsd .LC7(%rip), %xmm0
.L50:
movsd %xmm1, 0(%rbp,%rax)
movsd %xmm0, (%r12,%rax)
addq $8, %rax
cmpq %rax, %rbx
jne .L50
.L49:
call clock@PLT
movq %rax, %rbx
movl 4(%rsp), %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z13matrixMultCPUPdS_S_i
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movq %xmm0, %r15
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
.LEHB0:
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
je .L51
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L64:
leaq .LC4(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
.L42:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L65
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq %rbx, %rax
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L46
.L47:
subsd .LC5(%rip), %xmm0
cvttsd2siq %xmm0, %r13
btcq $63, %r13
jmp .L48
.L51:
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
je .L52
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L52:
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
je .L53
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L53:
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L54
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L54:
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L55
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L55:
movl $1, 64(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC15(%rip), %xmm0
call ceilf@PLT
cvttss2siq %xmm0, %rax
movl %eax, 68(%rsp)
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
call clock@PLT
movq %rax, %rbx
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L56:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L57
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L66:
movl 4(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i
jmp .L56
.L57:
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movsd %xmm0, 24(%rsp)
leaq 80(%rsp), %rdi
movl 4(%rsp), %ecx
movq 16(%rsp), %r14
movq %r14, %rdx
movq 8(%rsp), %rbx
movq %rbx, %rsi
call _Z10testValuesB5cxx11PdS_i
.LEHE0:
movq 80(%rsp), %rdx
movq %r15, %xmm1
movsd 24(%rsp), %xmm0
divsd %xmm0, %xmm1
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $2, %eax
.LEHB1:
call __printf_chk@PLT
.LEHE1:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
.LEHB2:
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L42
.L61:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L59
call __stack_chk_fail@PLT
.L59:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE2:
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3058:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3058:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3058-.LLSDACSB3058
.LLSDACSB3058:
.uleb128 .LEHB0-.LFB3058
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3058
.uleb128 .LEHE1-.LEHB1
.uleb128 .L61-.LFB3058
.uleb128 0
.uleb128 .LEHB2-.LFB3058
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3058:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1138753536
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long 0
.long 1073741824
.align 8
.LC8:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1023410176
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <time.h>
#include <string>
__global__ void matrixMultGPU (double *A, double *B, double *C, int N){
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < N && row < N){
double acc = 0.0;
for(int k=0;k<N;k++)
acc += A[row*N+k] * B[k*N+col];
C[row*N+col] = acc;
}
}
void matrixMultCPU(double *A, double *B, double *C, int N){
double acc;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
acc=0.0;
for(int k=0;k<N;k++)
acc += A[i*N+k]*B[k*N+j];
C[i*N+j] = acc;
}
}
}
std::string testValues(double *A, double *B, int N){
for(int i = 0; i < N*N; ++i)
if(A[i]!=B[i])
return "Mal Cálculo";
return "Buen Cálculo";
}
int main(int argc, char **argv){
cudaError_t error = cudaSuccess;
double *A, *B, *C1, *C2;
double *d_A, *d_B, *d_C;
double CPU, GPU;
if(argc != 2) {
printf("No size given\n");
return -1;
}
int N = atoi(argv[1]);
double size = N*N*sizeof(double);
A = (double*)malloc(size);
B = (double*)malloc(size);
C1 = (double*)malloc(size);
C2 = (double*)malloc(size);
for(int i=0;i<N*N;i++){
A[i]=1;
B[i]=2;
}
//CPU----------------------------
clock_t tic = clock();
matrixMultCPU(A,B,C1, N);
clock_t toc = clock();
//printf("Tiempo CPU: %f segundos", (double)(toc - tic) / CLOCKS_PER_SEC);
CPU = (double)(toc - tic) / CLOCKS_PER_SEC;
printf("%f,",CPU);
//-------------------------------
error = cudaMalloc((void**)&d_A,size);
if(error != cudaSuccess){
printf("Error in cudaMalloc for d_A\n");
exit(0);
}
error = cudaMalloc((void**)&d_B,size);
if(error != cudaSuccess){
printf("Error in cudaMalloc for d_B\n");
exit(0);
}
error = cudaMalloc((void**)&d_C,size);
if(error != cudaSuccess){
printf("Error in cudaMalloc for d_C\n");
exit(0);
}
error = cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error in cudaMemcpy for d_A\n");
exit(0);
}
error = cudaMemcpy(d_B,B,size,cudaMemcpyHostToDevice);
if(error != cudaSuccess){
printf("Error in cudaMemcpy for d_B\n");
exit(0);
}
//GPU----------------------------
dim3 dimBlock(32,32);
dim3 dimGrid(ceil(N/float(dimBlock.x)),ceil(N/float(dimBlock.y)));
clock_t tic2 = clock();
matrixMultGPU<<<dimGrid,dimBlock>>>(d_A,d_B,d_C,N);
cudaDeviceSynchronize();
error = cudaMemcpy(C2,d_C,size,cudaMemcpyDeviceToHost);
if(error != cudaSuccess){
printf("Error in cudaMemcpy for C2\n");
exit(0);
}
clock_t toc2 = clock();
//printf("\n\nTiempo GPU: %f segundos\n", (double)(toc2 - tic2) / CLOCKS_PER_SEC);
GPU = (double)(toc2 - tic2) / CLOCKS_PER_SEC;
printf("%f,%f,%s\n",GPU,(CPU/GPU), testValues(C1,C2,N).c_str());
//--------------------------------
/*
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",A[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",B[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C1[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C2[i]);
}
printf("\n---------\n");
*/
free(A);
free(B);
free(C1);
free(C2);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <string>
__global__ void matrixMultGPU (double *A, double *B, double *C, int N){
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < N && row < N){
double acc = 0.0;
for(int k=0;k<N;k++)
acc += A[row*N+k] * B[k*N+col];
C[row*N+col] = acc;
}
}
void matrixMultCPU(double *A, double *B, double *C, int N){
double acc;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
acc=0.0;
for(int k=0;k<N;k++)
acc += A[i*N+k]*B[k*N+j];
C[i*N+j] = acc;
}
}
}
std::string testValues(double *A, double *B, int N){
for(int i = 0; i < N*N; ++i)
if(A[i]!=B[i])
return "Mal Cálculo";
return "Buen Cálculo";
}
int main(int argc, char **argv){
hipError_t error = hipSuccess;
double *A, *B, *C1, *C2;
double *d_A, *d_B, *d_C;
double CPU, GPU;
if(argc != 2) {
printf("No size given\n");
return -1;
}
int N = atoi(argv[1]);
double size = N*N*sizeof(double);
A = (double*)malloc(size);
B = (double*)malloc(size);
C1 = (double*)malloc(size);
C2 = (double*)malloc(size);
for(int i=0;i<N*N;i++){
A[i]=1;
B[i]=2;
}
//CPU----------------------------
clock_t tic = clock();
matrixMultCPU(A,B,C1, N);
clock_t toc = clock();
//printf("Tiempo CPU: %f segundos", (double)(toc - tic) / CLOCKS_PER_SEC);
CPU = (double)(toc - tic) / CLOCKS_PER_SEC;
printf("%f,",CPU);
//-------------------------------
error = hipMalloc((void**)&d_A,size);
if(error != hipSuccess){
printf("Error in hipMalloc for d_A\n");
exit(0);
}
error = hipMalloc((void**)&d_B,size);
if(error != hipSuccess){
printf("Error in hipMalloc for d_B\n");
exit(0);
}
error = hipMalloc((void**)&d_C,size);
if(error != hipSuccess){
printf("Error in hipMalloc for d_C\n");
exit(0);
}
error = hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error in hipMemcpy for d_A\n");
exit(0);
}
error = hipMemcpy(d_B,B,size,hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error in hipMemcpy for d_B\n");
exit(0);
}
//GPU----------------------------
dim3 dimBlock(32,32);
dim3 dimGrid(ceil(N/float(dimBlock.x)),ceil(N/float(dimBlock.y)));
clock_t tic2 = clock();
matrixMultGPU<<<dimGrid,dimBlock>>>(d_A,d_B,d_C,N);
hipDeviceSynchronize();
error = hipMemcpy(C2,d_C,size,hipMemcpyDeviceToHost);
if(error != hipSuccess){
printf("Error in hipMemcpy for C2\n");
exit(0);
}
clock_t toc2 = clock();
//printf("\n\nTiempo GPU: %f segundos\n", (double)(toc2 - tic2) / CLOCKS_PER_SEC);
GPU = (double)(toc2 - tic2) / CLOCKS_PER_SEC;
printf("%f,%f,%s\n",GPU,(CPU/GPU), testValues(C1,C2,N).c_str());
//--------------------------------
/*
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",A[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",B[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C1[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C2[i]);
}
printf("\n---------\n");
*/
free(A);
free(B);
free(C1);
free(C2);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <string>
__global__ void matrixMultGPU (double *A, double *B, double *C, int N){
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < N && row < N){
double acc = 0.0;
for(int k=0;k<N;k++)
acc += A[row*N+k] * B[k*N+col];
C[row*N+col] = acc;
}
}
void matrixMultCPU(double *A, double *B, double *C, int N){
double acc;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
acc=0.0;
for(int k=0;k<N;k++)
acc += A[i*N+k]*B[k*N+j];
C[i*N+j] = acc;
}
}
}
std::string testValues(double *A, double *B, int N){
for(int i = 0; i < N*N; ++i)
if(A[i]!=B[i])
return "Mal Cálculo";
return "Buen Cálculo";
}
int main(int argc, char **argv){
hipError_t error = hipSuccess;
double *A, *B, *C1, *C2;
double *d_A, *d_B, *d_C;
double CPU, GPU;
if(argc != 2) {
printf("No size given\n");
return -1;
}
int N = atoi(argv[1]);
double size = N*N*sizeof(double);
A = (double*)malloc(size);
B = (double*)malloc(size);
C1 = (double*)malloc(size);
C2 = (double*)malloc(size);
for(int i=0;i<N*N;i++){
A[i]=1;
B[i]=2;
}
//CPU----------------------------
clock_t tic = clock();
matrixMultCPU(A,B,C1, N);
clock_t toc = clock();
//printf("Tiempo CPU: %f segundos", (double)(toc - tic) / CLOCKS_PER_SEC);
CPU = (double)(toc - tic) / CLOCKS_PER_SEC;
printf("%f,",CPU);
//-------------------------------
error = hipMalloc((void**)&d_A,size);
if(error != hipSuccess){
printf("Error in hipMalloc for d_A\n");
exit(0);
}
error = hipMalloc((void**)&d_B,size);
if(error != hipSuccess){
printf("Error in hipMalloc for d_B\n");
exit(0);
}
error = hipMalloc((void**)&d_C,size);
if(error != hipSuccess){
printf("Error in hipMalloc for d_C\n");
exit(0);
}
error = hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error in hipMemcpy for d_A\n");
exit(0);
}
error = hipMemcpy(d_B,B,size,hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error in hipMemcpy for d_B\n");
exit(0);
}
//GPU----------------------------
dim3 dimBlock(32,32);
dim3 dimGrid(ceil(N/float(dimBlock.x)),ceil(N/float(dimBlock.y)));
clock_t tic2 = clock();
matrixMultGPU<<<dimGrid,dimBlock>>>(d_A,d_B,d_C,N);
hipDeviceSynchronize();
error = hipMemcpy(C2,d_C,size,hipMemcpyDeviceToHost);
if(error != hipSuccess){
printf("Error in hipMemcpy for C2\n");
exit(0);
}
clock_t toc2 = clock();
//printf("\n\nTiempo GPU: %f segundos\n", (double)(toc2 - tic2) / CLOCKS_PER_SEC);
GPU = (double)(toc2 - tic2) / CLOCKS_PER_SEC;
printf("%f,%f,%s\n",GPU,(CPU/GPU), testValues(C1,C2,N).c_str());
//--------------------------------
/*
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",A[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",B[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C1[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C2[i]);
}
printf("\n---------\n");
*/
free(A);
free(B);
free(C1);
free(C2);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13matrixMultGPUPdS_S_i
.globl _Z13matrixMultGPUPdS_S_i
.p2align 8
.type _Z13matrixMultGPUPdS_S_i,@function
_Z13matrixMultGPUPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13matrixMultGPUPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13matrixMultGPUPdS_S_i, .Lfunc_end0-_Z13matrixMultGPUPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13matrixMultGPUPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13matrixMultGPUPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <string>
__global__ void matrixMultGPU (double *A, double *B, double *C, int N){
int col = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
if(col < N && row < N){
double acc = 0.0;
for(int k=0;k<N;k++)
acc += A[row*N+k] * B[k*N+col];
C[row*N+col] = acc;
}
}
void matrixMultCPU(double *A, double *B, double *C, int N){
double acc;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
acc=0.0;
for(int k=0;k<N;k++)
acc += A[i*N+k]*B[k*N+j];
C[i*N+j] = acc;
}
}
}
std::string testValues(double *A, double *B, int N){
for(int i = 0; i < N*N; ++i)
if(A[i]!=B[i])
return "Mal Cálculo";
return "Buen Cálculo";
}
int main(int argc, char **argv){
hipError_t error = hipSuccess;
double *A, *B, *C1, *C2;
double *d_A, *d_B, *d_C;
double CPU, GPU;
if(argc != 2) {
printf("No size given\n");
return -1;
}
int N = atoi(argv[1]);
double size = N*N*sizeof(double);
A = (double*)malloc(size);
B = (double*)malloc(size);
C1 = (double*)malloc(size);
C2 = (double*)malloc(size);
for(int i=0;i<N*N;i++){
A[i]=1;
B[i]=2;
}
//CPU----------------------------
clock_t tic = clock();
matrixMultCPU(A,B,C1, N);
clock_t toc = clock();
//printf("Tiempo CPU: %f segundos", (double)(toc - tic) / CLOCKS_PER_SEC);
CPU = (double)(toc - tic) / CLOCKS_PER_SEC;
printf("%f,",CPU);
//-------------------------------
error = hipMalloc((void**)&d_A,size);
if(error != hipSuccess){
printf("Error in hipMalloc for d_A\n");
exit(0);
}
error = hipMalloc((void**)&d_B,size);
if(error != hipSuccess){
printf("Error in hipMalloc for d_B\n");
exit(0);
}
error = hipMalloc((void**)&d_C,size);
if(error != hipSuccess){
printf("Error in hipMalloc for d_C\n");
exit(0);
}
error = hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error in hipMemcpy for d_A\n");
exit(0);
}
error = hipMemcpy(d_B,B,size,hipMemcpyHostToDevice);
if(error != hipSuccess){
printf("Error in hipMemcpy for d_B\n");
exit(0);
}
//GPU----------------------------
dim3 dimBlock(32,32);
dim3 dimGrid(ceil(N/float(dimBlock.x)),ceil(N/float(dimBlock.y)));
clock_t tic2 = clock();
matrixMultGPU<<<dimGrid,dimBlock>>>(d_A,d_B,d_C,N);
hipDeviceSynchronize();
error = hipMemcpy(C2,d_C,size,hipMemcpyDeviceToHost);
if(error != hipSuccess){
printf("Error in hipMemcpy for C2\n");
exit(0);
}
clock_t toc2 = clock();
//printf("\n\nTiempo GPU: %f segundos\n", (double)(toc2 - tic2) / CLOCKS_PER_SEC);
GPU = (double)(toc2 - tic2) / CLOCKS_PER_SEC;
printf("%f,%f,%s\n",GPU,(CPU/GPU), testValues(C1,C2,N).c_str());
//--------------------------------
/*
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",A[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",B[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C1[i]);
}
printf("\n---------\n");
for(int i=0;i<N*N;i++){
if(i%N == 0)
printf("\n");
printf("%f ;",C2[i]);
}
printf("\n---------\n");
*/
free(A);
free(B);
free(C1);
free(C2);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
return 0;
} | .text
.file "matrixMult.hip"
.globl _Z28__device_stub__matrixMultGPUPdS_S_i # -- Begin function _Z28__device_stub__matrixMultGPUPdS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__matrixMultGPUPdS_S_i,@function
_Z28__device_stub__matrixMultGPUPdS_S_i: # @_Z28__device_stub__matrixMultGPUPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13matrixMultGPUPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__matrixMultGPUPdS_S_i, .Lfunc_end0-_Z28__device_stub__matrixMultGPUPdS_S_i
.cfi_endproc
# -- End function
.globl _Z13matrixMultCPUPdS_S_i # -- Begin function _Z13matrixMultCPUPdS_S_i
.p2align 4, 0x90
.type _Z13matrixMultCPUPdS_S_i,@function
_Z13matrixMultCPUPdS_S_i: # @_Z13matrixMultCPUPdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_8
# %bb.1: # %.preheader26.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,8), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,8), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,8), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
xorpd %xmm0, %xmm0
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r11,%r13,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%r12), %xmm1
addsd %xmm1, %xmm0
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB1_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB1_3 Depth=2
movsd %xmm0, (%rbx,%r15,8)
incq %r15
addq $8, %r14
cmpq %rax, %r15
jne .LBB1_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB1_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB1_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB1_8: # %._crit_edge32
retq
.Lfunc_end1:
.size _Z13matrixMultCPUPdS_S_i, .Lfunc_end1-_Z13matrixMultCPUPdS_S_i
.cfi_endproc
# -- End function
.globl _Z10testValuesB5cxx11PdS_i # -- Begin function _Z10testValuesB5cxx11PdS_i
.p2align 4, 0x90
.type _Z10testValuesB5cxx11PdS_i,@function
_Z10testValuesB5cxx11PdS_i: # @_Z10testValuesB5cxx11PdS_i
.cfi_startproc
# %bb.0:
# kill: def $ecx killed $ecx def $rcx
movq %rdi, %rax
testl %ecx, %ecx
setne %r8b
je .LBB2_7
# %bb.1: # %.lr.ph.preheader
imull %ecx, %ecx
cmpl $1, %ecx
movl %ecx, %edi
adcl $0, %edi
movsd (%rsi), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rdx), %xmm0
jne .LBB2_6
jp .LBB2_6
# %bb.2: # %.lr.ph31.preheader
decq %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph31
# =>This Inner Loop Header: Depth=1
cmpq %r8, %rdi
je .LBB2_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
movsd 8(%rsi,%r8,8), %xmm0 # xmm0 = mem[0],zero
leaq 1(%r8), %r9
ucomisd 8(%rdx,%r8,8), %xmm0
movq %r9, %r8
jne .LBB2_5
jnp .LBB2_3
.LBB2_5: # %.lr.ph._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit_crit_edge
cmpq %rcx, %r9
setb %r8b
.LBB2_6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
leaq 16(%rax), %rcx
movq %rcx, (%rax)
movabsq $7827752320420831565, %rcx # imm = 0x6CA1C343206C614D
movq %rcx, 16(%rax)
movl $1869378915, 24(%rax) # imm = 0x6F6C7563
movq $12, 8(%rax)
movb $0, 28(%rax)
testb %r8b, %r8b
jne .LBB2_8
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit22
leaq 16(%rax), %rcx
movq %rcx, (%rax)
movabsq $-6790510006574418622, %rcx # imm = 0xA1C343206E657542
movq %rcx, 16(%rax)
movabsq $8028921305579504451, %rcx # imm = 0x6F6C75636CA1C343
movq %rcx, 21(%rax)
movq $13, 8(%rax)
movb $0, 29(%rax)
.LBB2_8:
retq
.Lfunc_end2:
.size _Z10testValuesB5cxx11PdS_i, .Lfunc_end2-_Z10testValuesB5cxx11PdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x3d000000 # float 0.03125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB3_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movl %r13d, %r12d
imull %r12d, %r12d
leaq (,%r12,8), %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
testl %r13d, %r13d
je .LBB3_5
# %bb.3: # %.lr.ph.preheader
cmpl $2, %r12d
movl $1, %eax
cmovael %r12d, %eax
xorl %ecx, %ecx
movabsq $4607182418800017408, %rdx # imm = 0x3FF0000000000000
movabsq $4611686018427387904, %rsi # imm = 0x4000000000000000
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rdx, (%rbx,%rcx,8)
movq %rsi, (%r14,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_4
.LBB3_5: # %._crit_edge
movq %r12, 72(%rsp) # 8-byte Spill
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB3_12
# %bb.6: # %.preheader26.lr.ph.i
movl %r13d, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_7: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
# Child Loop BB3_9 Depth 3
movl %edx, %edi
leaq (%rbx,%rdi,8), %rdi
movq %rsi, %r8
imulq %rax, %r8
leaq (%r15,%r8,8), %r8
movq %r14, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_8: # %.preheader.i
# Parent Loop BB3_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_9 Depth 3
xorpd %xmm0, %xmm0
movq %r9, %r11
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_9: # Parent Loop BB3_7 Depth=1
# Parent Loop BB3_8 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rdi,%r12), %xmm1 # xmm1 = mem[0],zero
mulsd (%r11), %xmm1
addsd %xmm1, %xmm0
addq $8, %r12
addq %rcx, %r11
cmpq %r12, %rcx
jne .LBB3_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB3_8 Depth=2
movsd %xmm0, (%r8,%r10,8)
incq %r10
addq $8, %r9
cmpq %rax, %r10
jne .LBB3_8
# %bb.11: # %._crit_edge30.i
# in Loop: Header=BB3_7 Depth=1
incq %rsi
addl %r13d, %edx
cmpq %rax, %rsi
jne .LBB3_7
.LBB3_12: # %_Z13matrixMultCPUPdS_S_i.exit
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movsd %xmm0, 32(%rsp) # 8-byte Spill
movb $1, %al
callq printf
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_13
# %bb.15:
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_16
# %bb.17:
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_18
# %bb.19:
movq 56(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_20
# %bb.21:
movq 48(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_22
# %bb.23:
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
mulss .LCPI3_1(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12
movl %r12d, %eax
shlq $32, %r12
orq %rax, %r12
callq clock
movq %rax, 80(%rsp) # 8-byte Spill
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_25
# %bb.24:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movl %r13d, 68(%rsp)
leaq 160(%rsp), %rax
movq %rax, (%rsp)
leaq 152(%rsp), %rax
movq %rax, 8(%rsp)
leaq 144(%rsp), %rax
movq %rax, 16(%rsp)
leaq 68(%rsp), %rax
movq %rax, 24(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movq %rsp, %r9
movl $_Z13matrixMultGPUPdS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_25:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movq 88(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_26
# %bb.27:
callq clock
subq 80(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
testl %r13d, %r13d
je .LBB3_33
# %bb.28: # %.lr.ph.preheader.i
movq 72(%rsp), %rcx # 8-byte Reload
cmpl $2, %ecx
movl $1, %eax
cmovael %ecx, %eax
movsd (%r15), %xmm2 # xmm2 = mem[0],zero
ucomisd (%r12), %xmm2
jne .LBB3_34
jnp .LBB3_29
.LBB3_34: # %_Z10testValuesB5cxx11PdS_i.exit.critedge
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movabsq $7827752320420831565, %rax # imm = 0x6CA1C343206C614D
movq %rax, 16(%rsp)
movl $1869378915, 24(%rsp) # imm = 0x6F6C7563
movq $12, 8(%rsp)
movb $0, 28(%rsp)
jmp .LBB3_35
.LBB3_1:
movl $.Lstr.6, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB3_38
.LBB3_29: # %.lr.ph86.preheader
decq %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_30: # %.lr.ph86
# =>This Inner Loop Header: Depth=1
cmpq %rdx, %rax
je .LBB3_33
# %bb.31: # %.lr.ph.i
# in Loop: Header=BB3_30 Depth=1
movsd 8(%r15,%rdx,8), %xmm2 # xmm2 = mem[0],zero
leaq 1(%rdx), %rcx
ucomisd 8(%r12,%rdx,8), %xmm2
movq %rcx, %rdx
jne .LBB3_32
jnp .LBB3_30
.LBB3_32: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit.i
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movabsq $7827752320420831565, %rax # imm = 0x6CA1C343206C614D
movq %rax, 16(%rsp)
movl $1869378915, 24(%rsp) # imm = 0x6F6C7563
movq $12, 8(%rsp)
movb $0, 28(%rsp)
cmpq 72(%rsp), %rcx # 8-byte Folded Reload
jb .LBB3_35
.LBB3_33: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit22.i
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movabsq $-6790510006574418622, %rax # imm = 0xA1C343206E657542
movq %rax, 16(%rsp)
movabsq $8028921305579504451, %rax # imm = 0x6F6C75636CA1C343
movq %rax, 21(%rsp)
movq $13, 8(%rsp)
movb $0, 29(%rsp)
.LBB3_35: # %_Z10testValuesB5cxx11PdS_i.exit
movq (%rsp), %rsi
movl $.L.str.10, %edi
movb $2, %al
callq printf
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB3_37
# %bb.36: # %.critedge.i.i
callq _ZdlPv
.LBB3_37: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB3_38:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_13:
.cfi_def_cfa_offset 224
movl $.Lstr.5, %edi
jmp .LBB3_14
.LBB3_16:
movl $.Lstr.4, %edi
jmp .LBB3_14
.LBB3_18:
movl $.Lstr.3, %edi
jmp .LBB3_14
.LBB3_20:
movl $.Lstr.2, %edi
jmp .LBB3_14
.LBB3_22:
movl $.Lstr.1, %edi
jmp .LBB3_14
.LBB3_26:
movl $.Lstr, %edi
.LBB3_14:
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matrixMultGPUPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13matrixMultGPUPdS_S_i,@object # @_Z13matrixMultGPUPdS_S_i
.section .rodata,"a",@progbits
.globl _Z13matrixMultGPUPdS_S_i
.p2align 3, 0x0
_Z13matrixMultGPUPdS_S_i:
.quad _Z28__device_stub__matrixMultGPUPdS_S_i
.size _Z13matrixMultGPUPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Mal C\303\241lculo"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Buen C\303\241lculo"
.size .L.str.1, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f,"
.size .L.str.3, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%f,%f,%s\n"
.size .L.str.10, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13matrixMultGPUPdS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error in hipMemcpy for C2"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error in hipMemcpy for d_B"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error in hipMemcpy for d_A"
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Error in hipMalloc for d_C"
.size .Lstr.3, 27
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error in hipMalloc for d_B"
.size .Lstr.4, 27
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error in hipMalloc for d_A"
.size .Lstr.5, 27
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "No size given"
.size .Lstr.6, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__matrixMultGPUPdS_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13matrixMultGPUPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13matrixMultGPUPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13matrixMultGPUPdS_S_i
.globl _Z13matrixMultGPUPdS_S_i
.p2align 8
.type _Z13matrixMultGPUPdS_S_i,@function
_Z13matrixMultGPUPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13matrixMultGPUPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13matrixMultGPUPdS_S_i, .Lfunc_end0-_Z13matrixMultGPUPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13matrixMultGPUPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13matrixMultGPUPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009422a_00000000-6_matrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13matrixMultCPUPdS_S_i
.type _Z13matrixMultCPUPdS_S_i, @function
_Z13matrixMultCPUPdS_S_i:
.LFB3056:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r9
movl %ecx, %r12d
movslq %ecx, %r11
leaq 0(,%r11,8), %rcx
movq %rdi, %r10
leaq (%rdi,%rcx), %rsi
movl $0, %ebp
.L5:
movq %rbx, %r8
movl $0, %edi
.L8:
movq %r8, %rdx
movq %r10, %rax
pxor %xmm1, %xmm1
.L6:
movsd (%rax), %xmm0
mulsd (%rdx), %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
addq %rcx, %rdx
cmpq %rsi, %rax
jne .L6
movsd %xmm1, (%r9,%rdi,8)
addq $1, %rdi
addq $8, %r8
cmpq %r11, %rdi
jne .L8
addl $1, %ebp
addq %rcx, %r9
addq %rcx, %r10
addq %rcx, %rsi
cmpl %ebp, %r12d
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3056:
.size _Z13matrixMultCPUPdS_S_i, .-_Z13matrixMultCPUPdS_S_i
.globl _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i
.type _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i, @function
_Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i:
.LFB3083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13matrixMultGPUPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3083:
.size _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i, .-_Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i
.globl _Z13matrixMultGPUPdS_S_i
.type _Z13matrixMultGPUPdS_S_i, @function
_Z13matrixMultGPUPdS_S_i:
.LFB3084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3084:
.size _Z13matrixMultGPUPdS_S_i, .-_Z13matrixMultGPUPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13matrixMultGPUPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matrixMultGPUPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB3461:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L31
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L27
movzbl (%rsi), %eax
movb %al, (%rdi)
.L28:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L26:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L28
.L27:
testq %rdx, %rdx
je .L28
jmp .L26
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3461:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .rodata.str1.1
.LC2:
.string "Mal C\303\241lculo"
.LC3:
.string "Buen C\303\241lculo"
.text
.globl _Z10testValuesB5cxx11PdS_i
.type _Z10testValuesB5cxx11PdS_i, @function
_Z10testValuesB5cxx11PdS_i:
.LFB3057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
imull %ecx, %ecx
testl %ecx, %ecx
jle .L34
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
.L38:
movsd (%rsi,%rax), %xmm0
ucomisd (%rdx,%rax), %xmm0
jp .L39
jne .L39
addq $8, %rax
cmpq %rcx, %rax
jne .L38
.L34:
leaq 16(%rbx), %rax
movq %rax, (%rbx)
leaq 13+.LC3(%rip), %rdx
leaq -13(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.L33:
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
leaq 16(%rbx), %rax
movq %rax, (%rbx)
leaq 12+.LC2(%rip), %rdx
leaq -12(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
jmp .L33
.cfi_endproc
.LFE3057:
.size _Z10testValuesB5cxx11PdS_i, .-_Z10testValuesB5cxx11PdS_i
.section .rodata.str1.1
.LC4:
.string "No size given\n"
.LC9:
.string "%f,"
.LC10:
.string "Error in cudaMalloc for d_A\n"
.LC11:
.string "Error in cudaMalloc for d_B\n"
.LC12:
.string "Error in cudaMalloc for d_C\n"
.LC13:
.string "Error in cudaMemcpy for d_A\n"
.LC14:
.string "Error in cudaMemcpy for d_B\n"
.LC16:
.string "Error in cudaMemcpy for C2\n"
.LC17:
.string "%f,%f,%s\n"
.text
.globl main
.type main, @function
main:
.LFB3058:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3058
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L64
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 4(%rsp)
movl %eax, %r15d
imull %eax, %r15d
movslq %r15d, %rbx
salq $3, %rbx
js .L45
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L46:
comisd .LC5(%rip), %xmm0
jnb .L47
cvttsd2siq %xmm0, %r13
.L48:
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testl %r15d, %r15d
jle .L49
movl $0, %eax
movsd .LC6(%rip), %xmm1
movsd .LC7(%rip), %xmm0
.L50:
movsd %xmm1, 0(%rbp,%rax)
movsd %xmm0, (%r12,%rax)
addq $8, %rax
cmpq %rax, %rbx
jne .L50
.L49:
call clock@PLT
movq %rax, %rbx
movl 4(%rsp), %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z13matrixMultCPUPdS_S_i
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movq %xmm0, %r15
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
.LEHB0:
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
je .L51
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L64:
leaq .LC4(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
.L42:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L65
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq %rbx, %rax
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L46
.L47:
subsd .LC5(%rip), %xmm0
cvttsd2siq %xmm0, %r13
btcq $63, %r13
jmp .L48
.L51:
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
je .L52
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L52:
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
je .L53
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L53:
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L54
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L54:
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L55
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L55:
movl $1, 64(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC15(%rip), %xmm0
call ceilf@PLT
cvttss2siq %xmm0, %rax
movl %eax, 68(%rsp)
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
call clock@PLT
movq %rax, %rbx
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L56:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L57
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L66:
movl 4(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z38__device_stub__Z13matrixMultGPUPdS_S_iPdS_S_i
jmp .L56
.L57:
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movsd %xmm0, 24(%rsp)
leaq 80(%rsp), %rdi
movl 4(%rsp), %ecx
movq 16(%rsp), %r14
movq %r14, %rdx
movq 8(%rsp), %rbx
movq %rbx, %rsi
call _Z10testValuesB5cxx11PdS_i
.LEHE0:
movq 80(%rsp), %rdx
movq %r15, %xmm1
movsd 24(%rsp), %xmm0
divsd %xmm0, %xmm1
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $2, %eax
.LEHB1:
call __printf_chk@PLT
.LEHE1:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
.LEHB2:
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L42
.L61:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L59
call __stack_chk_fail@PLT
.L59:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE2:
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3058:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3058:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3058-.LLSDACSB3058
.LLSDACSB3058:
.uleb128 .LEHB0-.LFB3058
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3058
.uleb128 .LEHE1-.LEHB1
.uleb128 .L61-.LFB3058
.uleb128 0
.uleb128 .LEHB2-.LFB3058
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3058:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1138753536
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long 0
.long 1073741824
.align 8
.LC8:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1023410176
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMult.hip"
.globl _Z28__device_stub__matrixMultGPUPdS_S_i # -- Begin function _Z28__device_stub__matrixMultGPUPdS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__matrixMultGPUPdS_S_i,@function
_Z28__device_stub__matrixMultGPUPdS_S_i: # @_Z28__device_stub__matrixMultGPUPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13matrixMultGPUPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__matrixMultGPUPdS_S_i, .Lfunc_end0-_Z28__device_stub__matrixMultGPUPdS_S_i
.cfi_endproc
# -- End function
.globl _Z13matrixMultCPUPdS_S_i # -- Begin function _Z13matrixMultCPUPdS_S_i
.p2align 4, 0x90
.type _Z13matrixMultCPUPdS_S_i,@function
_Z13matrixMultCPUPdS_S_i: # @_Z13matrixMultCPUPdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_8
# %bb.1: # %.preheader26.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,8), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,8), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,8), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
xorpd %xmm0, %xmm0
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r11,%r13,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%r12), %xmm1
addsd %xmm1, %xmm0
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB1_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB1_3 Depth=2
movsd %xmm0, (%rbx,%r15,8)
incq %r15
addq $8, %r14
cmpq %rax, %r15
jne .LBB1_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB1_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB1_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB1_8: # %._crit_edge32
retq
.Lfunc_end1:
.size _Z13matrixMultCPUPdS_S_i, .Lfunc_end1-_Z13matrixMultCPUPdS_S_i
.cfi_endproc
# -- End function
.globl _Z10testValuesB5cxx11PdS_i # -- Begin function _Z10testValuesB5cxx11PdS_i
.p2align 4, 0x90
.type _Z10testValuesB5cxx11PdS_i,@function
_Z10testValuesB5cxx11PdS_i: # @_Z10testValuesB5cxx11PdS_i
.cfi_startproc
# %bb.0:
# kill: def $ecx killed $ecx def $rcx
movq %rdi, %rax
testl %ecx, %ecx
setne %r8b
je .LBB2_7
# %bb.1: # %.lr.ph.preheader
imull %ecx, %ecx
cmpl $1, %ecx
movl %ecx, %edi
adcl $0, %edi
movsd (%rsi), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rdx), %xmm0
jne .LBB2_6
jp .LBB2_6
# %bb.2: # %.lr.ph31.preheader
decq %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph31
# =>This Inner Loop Header: Depth=1
cmpq %r8, %rdi
je .LBB2_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
movsd 8(%rsi,%r8,8), %xmm0 # xmm0 = mem[0],zero
leaq 1(%r8), %r9
ucomisd 8(%rdx,%r8,8), %xmm0
movq %r9, %r8
jne .LBB2_5
jnp .LBB2_3
.LBB2_5: # %.lr.ph._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit_crit_edge
cmpq %rcx, %r9
setb %r8b
.LBB2_6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
leaq 16(%rax), %rcx
movq %rcx, (%rax)
movabsq $7827752320420831565, %rcx # imm = 0x6CA1C343206C614D
movq %rcx, 16(%rax)
movl $1869378915, 24(%rax) # imm = 0x6F6C7563
movq $12, 8(%rax)
movb $0, 28(%rax)
testb %r8b, %r8b
jne .LBB2_8
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit22
leaq 16(%rax), %rcx
movq %rcx, (%rax)
movabsq $-6790510006574418622, %rcx # imm = 0xA1C343206E657542
movq %rcx, 16(%rax)
movabsq $8028921305579504451, %rcx # imm = 0x6F6C75636CA1C343
movq %rcx, 21(%rax)
movq $13, 8(%rax)
movb $0, 29(%rax)
.LBB2_8:
retq
.Lfunc_end2:
.size _Z10testValuesB5cxx11PdS_i, .Lfunc_end2-_Z10testValuesB5cxx11PdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x3d000000 # float 0.03125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB3_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movl %r13d, %r12d
imull %r12d, %r12d
leaq (,%r12,8), %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
testl %r13d, %r13d
je .LBB3_5
# %bb.3: # %.lr.ph.preheader
cmpl $2, %r12d
movl $1, %eax
cmovael %r12d, %eax
xorl %ecx, %ecx
movabsq $4607182418800017408, %rdx # imm = 0x3FF0000000000000
movabsq $4611686018427387904, %rsi # imm = 0x4000000000000000
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rdx, (%rbx,%rcx,8)
movq %rsi, (%r14,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_4
.LBB3_5: # %._crit_edge
movq %r12, 72(%rsp) # 8-byte Spill
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB3_12
# %bb.6: # %.preheader26.lr.ph.i
movl %r13d, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_7: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
# Child Loop BB3_9 Depth 3
movl %edx, %edi
leaq (%rbx,%rdi,8), %rdi
movq %rsi, %r8
imulq %rax, %r8
leaq (%r15,%r8,8), %r8
movq %r14, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_8: # %.preheader.i
# Parent Loop BB3_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_9 Depth 3
xorpd %xmm0, %xmm0
movq %r9, %r11
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_9: # Parent Loop BB3_7 Depth=1
# Parent Loop BB3_8 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rdi,%r12), %xmm1 # xmm1 = mem[0],zero
mulsd (%r11), %xmm1
addsd %xmm1, %xmm0
addq $8, %r12
addq %rcx, %r11
cmpq %r12, %rcx
jne .LBB3_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB3_8 Depth=2
movsd %xmm0, (%r8,%r10,8)
incq %r10
addq $8, %r9
cmpq %rax, %r10
jne .LBB3_8
# %bb.11: # %._crit_edge30.i
# in Loop: Header=BB3_7 Depth=1
incq %rsi
addl %r13d, %edx
cmpq %rax, %rsi
jne .LBB3_7
.LBB3_12: # %_Z13matrixMultCPUPdS_S_i.exit
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movsd %xmm0, 32(%rsp) # 8-byte Spill
movb $1, %al
callq printf
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_13
# %bb.15:
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_16
# %bb.17:
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_18
# %bb.19:
movq 56(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_20
# %bb.21:
movq 48(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_22
# %bb.23:
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
mulss .LCPI3_1(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12
movl %r12d, %eax
shlq $32, %r12
orq %rax, %r12
callq clock
movq %rax, 80(%rsp) # 8-byte Spill
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_25
# %bb.24:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movl %r13d, 68(%rsp)
leaq 160(%rsp), %rax
movq %rax, (%rsp)
leaq 152(%rsp), %rax
movq %rax, 8(%rsp)
leaq 144(%rsp), %rax
movq %rax, 16(%rsp)
leaq 68(%rsp), %rax
movq %rax, 24(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movq %rsp, %r9
movl $_Z13matrixMultGPUPdS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_25:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movq 88(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_26
# %bb.27:
callq clock
subq 80(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
testl %r13d, %r13d
je .LBB3_33
# %bb.28: # %.lr.ph.preheader.i
movq 72(%rsp), %rcx # 8-byte Reload
cmpl $2, %ecx
movl $1, %eax
cmovael %ecx, %eax
movsd (%r15), %xmm2 # xmm2 = mem[0],zero
ucomisd (%r12), %xmm2
jne .LBB3_34
jnp .LBB3_29
.LBB3_34: # %_Z10testValuesB5cxx11PdS_i.exit.critedge
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movabsq $7827752320420831565, %rax # imm = 0x6CA1C343206C614D
movq %rax, 16(%rsp)
movl $1869378915, 24(%rsp) # imm = 0x6F6C7563
movq $12, 8(%rsp)
movb $0, 28(%rsp)
jmp .LBB3_35
.LBB3_1:
movl $.Lstr.6, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB3_38
.LBB3_29: # %.lr.ph86.preheader
decq %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_30: # %.lr.ph86
# =>This Inner Loop Header: Depth=1
cmpq %rdx, %rax
je .LBB3_33
# %bb.31: # %.lr.ph.i
# in Loop: Header=BB3_30 Depth=1
movsd 8(%r15,%rdx,8), %xmm2 # xmm2 = mem[0],zero
leaq 1(%rdx), %rcx
ucomisd 8(%r12,%rdx,8), %xmm2
movq %rcx, %rdx
jne .LBB3_32
jnp .LBB3_30
.LBB3_32: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit.i
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movabsq $7827752320420831565, %rax # imm = 0x6CA1C343206C614D
movq %rax, 16(%rsp)
movl $1869378915, 24(%rsp) # imm = 0x6F6C7563
movq $12, 8(%rsp)
movb $0, 28(%rsp)
cmpq 72(%rsp), %rcx # 8-byte Folded Reload
jb .LBB3_35
.LBB3_33: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit22.i
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movabsq $-6790510006574418622, %rax # imm = 0xA1C343206E657542
movq %rax, 16(%rsp)
movabsq $8028921305579504451, %rax # imm = 0x6F6C75636CA1C343
movq %rax, 21(%rsp)
movq $13, 8(%rsp)
movb $0, 29(%rsp)
.LBB3_35: # %_Z10testValuesB5cxx11PdS_i.exit
movq (%rsp), %rsi
movl $.L.str.10, %edi
movb $2, %al
callq printf
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB3_37
# %bb.36: # %.critedge.i.i
callq _ZdlPv
.LBB3_37: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB3_38:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_13:
.cfi_def_cfa_offset 224
movl $.Lstr.5, %edi
jmp .LBB3_14
.LBB3_16:
movl $.Lstr.4, %edi
jmp .LBB3_14
.LBB3_18:
movl $.Lstr.3, %edi
jmp .LBB3_14
.LBB3_20:
movl $.Lstr.2, %edi
jmp .LBB3_14
.LBB3_22:
movl $.Lstr.1, %edi
jmp .LBB3_14
.LBB3_26:
movl $.Lstr, %edi
.LBB3_14:
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matrixMultGPUPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13matrixMultGPUPdS_S_i,@object # @_Z13matrixMultGPUPdS_S_i
.section .rodata,"a",@progbits
.globl _Z13matrixMultGPUPdS_S_i
.p2align 3, 0x0
_Z13matrixMultGPUPdS_S_i:
.quad _Z28__device_stub__matrixMultGPUPdS_S_i
.size _Z13matrixMultGPUPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Mal C\303\241lculo"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Buen C\303\241lculo"
.size .L.str.1, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f,"
.size .L.str.3, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%f,%f,%s\n"
.size .L.str.10, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13matrixMultGPUPdS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error in hipMemcpy for C2"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error in hipMemcpy for d_B"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error in hipMemcpy for d_A"
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Error in hipMalloc for d_C"
.size .Lstr.3, 27
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error in hipMalloc for d_B"
.size .Lstr.4, 27
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error in hipMalloc for d_A"
.size .Lstr.5, 27
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "No size given"
.size .Lstr.6, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__matrixMultGPUPdS_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13matrixMultGPUPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* UCLA Spring 2011
* CS239
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#define NUM_BLOCKS 32
#define BLOCK_SIZE 512
// define map/reduce function type
typedef int (*map_function_t) (int, int);
typedef int (*reduce_function_t) (int, int);
__device__ int rand(int init0, int init1)
{
// multiply-with-carry RNG
init0 = 36969 * (init0 & 65535) + (init0 >> 16);
init1 = 18000 * (init1 & 65535) + (init1 >> 16);
return (init0 << 16) + init1; /* 32-bit result */
}
__device__ int square(int op)
{
return op * op;
}
__device__ int mul(int op0, int op1)
{
return op0 * op1;
}
__device__ int sum(int op0, int op1)
{
return op0 + op1;
}
__global__ void map(int *array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x * 2
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// do map in shared mem
if (id < size) {
// do first operation
shared[tid] = array[id];
array[id] = square(shared[tid]);
}
if (id + blockDim.x < size) {
// do second operation
shared[tid + blockDim.x] = array[id + blockDim.x];
array[id + blockDim.x] = square(shared[tid + blockDim.x]);
}
}
__global__ void reduce(int *in_array, int *out_array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// first sum
int t_sum = (id < size) ? in_array[id] : 0;
if (id + blockDim.x < size) {
// current reduce function is sum
t_sum = sum(in_array[id + blockDim.x], t_sum);
}
shared[tid] = t_sum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
// current reduce function is sum
t_sum = sum(t_sum, shared[tid + s]);
shared[tid] = t_sum;
}
__syncthreads();
}
if (tid == 0) {
out_array[blockIdx.x] = shared[0];
}
}
int mapreduce(int blocks, int threads, int *array_h, int size)
{
int res;
int *array_d;
int *in_ptr_d;
int *out_array_d;
int *tmp_d;
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
cudaMalloc((void **)&array_d, size * sizeof(int));
cudaMemcpy(array_d, array_h, size * sizeof(int),
cudaMemcpyHostToDevice);
in_ptr_d = array_d;
// do map
map <<< dim_grid, dim_block, threads * sizeof(int) >>> (array_d, size);
// do reduce in iterations
for (unsigned int s = blocks / 2; s > 0; s >>= 1) {
// allocate array equal to blocks/2
cudaMalloc((void **)&out_array_d, s * sizeof(int));
reduce <<< dim_grid, dim_block,
threads * sizeof(int) >>> (in_ptr_d, out_array_d, size);
// free up the old input array
tmp_d = in_ptr_d;
// should check for tmp_d != array_h but we can just fail silently
cudaFree(tmp_d);
// set input array of next iteration to output array
in_ptr_d = out_array_d;
size = s;
}
// retrieve result
cudaMemcpy(&res, out_array_d, sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(out_array_d);
cudaFree(array_d);
return res;
}
int mapreduce_host(int *array_h, int size)
{
int res = 0;
// map
for (int i = 0; i < size; i++) {
array_h[i] = array_h[i] * array_h[i];
}
// reduce
for (int i = 0; i < size; i++) {
res += array_h[i];
}
return res;
}
void usage(int which)
{
switch (which) {
default:
printf
("usage: mapreduce [-h|-b blocks|-t threads] <filename>\n");
break;
case 1:
printf("mapreduce input format:\nnum count\n1\n...\nn n\n");
break;
case 2:
printf("mapreduce requires numbers <= threads*blocks\n");
break;
}
}
int prepare_numbers(const char *filename, int **array)
{
int count, input, i;
FILE *file;
file = fopen(filename, "r");
// count of data is first line
fscanf(file, "%d", &count);
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (i = 0; i < count; i++) {
if (fscanf(file, "%d", &input) < 0) {
break;
}
numbers[i] = input;
}
fclose(file);
if (count != i) {
free(numbers);
return -1;
} else {
*array = numbers;
return count;
}
}
int main(int argc, char *argv[])
{
int opt, host_mode, blocks, threads, array_size, result;
int *array;
char *filename;
// set options
host_mode = 0;
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
while ((opt = getopt(argc, argv, "hb:t:")) != -1) {
switch (opt) {
case 'h':
host_mode = 1;
break;
case 'b':
blocks = atoi(optarg);
break;
case 't':
threads = atoi(optarg);
break;
default:
usage(0);
return 0;
}
}
// check to make sure we are feeding in correct number of args
if (argc == optind + 1) {
filename = argv[optind];
} else {
usage(0);
return 0;
}
// read file
array = NULL;
array_size = prepare_numbers(filename, &array);
if (array_size < 0) {
free(array);
usage(1);
return 0;
} else if (array_size >= blocks * threads) {
free(array);
usage(2);
return 0;
}
if (host_mode) {
printf("mapreduce using host\n");
result = mapreduce_host(array, array_size);
} else {
printf("mapreduce using CUDA\n");
result = mapreduce(blocks, threads, array, array_size);
}
printf("mapreduce result: %d\n", result);
free(array);
return 0;
} | code for sm_80
Function : _Z6reducePiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ IMAD R2, R6, UR5, R7 ; /* 0x0000000506027c24 */
/* 0x001fca000f8e0207 */
/*0080*/ IADD3 R4, R2.reuse, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x040fe40007ffe0ff */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f26070 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fd60003f06070 */
/*00b0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fe400078e00ff */
/*00c0*/ @!P0 MOV R5, 0x4 ; /* 0x0000000400058802 */
/* 0x000fe40000000f00 */
/*00d0*/ @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fc800078e0003 */
/*00e0*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fe200078e0005 */
/*00f0*/ @!P1 LDG.E R0, [R2.64] ; /* 0x0000000602009981 */
/* 0x000eaa000c1e1900 */
/*0100*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000604058981 */
/* 0x000ea2000c1e1900 */
/*0110*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0120*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fca0003f25270 */
/*0130*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45270 */
/*0140*/ @!P0 IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100008824 */
/* 0x004fca00078e0205 */
/*0150*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P2 BRA 0x230 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*0180*/ SHF.L.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027819 */
/* 0x001fe200000006ff */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f06070 */
/*01b0*/ @!P0 LEA R4, R3, R2, 0x2 ; /* 0x0000000203048211 */
/* 0x000fe400078e10ff */
/*01c0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*01d0*/ @!P0 LDS R5, [R4] ; /* 0x0000000004058984 */
/* 0x000e240000000800 */
/*01e0*/ @!P0 IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100008824 */
/* 0x001fca00078e0205 */
/*01f0*/ @!P0 STS [R7.X4], R0 ; /* 0x0000000007008388 */
/* 0x0001e80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0210*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 BRA 0x1a0 ; /* 0xffffff7000000947 */
/* 0x001fea000383ffff */
/*0230*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*0240*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0250*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0260*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3mapPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e2a0000002100 */
/*0060*/ IMAD R2, R2, UR4, R7 ; /* 0x0000000402027c24 */
/* 0x001fe2000f8e0207 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x040fe40003f06070 */
/*0090*/ IADD3 R4, R2, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x000fc80007ffe0ff */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fce0003f26070 */
/*00b0*/ @P0 BRA 0x120 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fe400078e02ff */
/*0100*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0140*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fca0000000f00 */
/*0150*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0003 */
/*0160*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IADD3 R5, R7, c[0x0][0x0], RZ ; /* 0x0000000007057a10 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD R7, R0, R0, RZ ; /* 0x0000000000077224 */
/* 0x004fc800078e02ff */
/*0190*/ STS [R5.X4], R0 ; /* 0x0000000005007388 */
/* 0x000fe80000004800 */
/*01a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* UCLA Spring 2011
* CS239
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#define NUM_BLOCKS 32
#define BLOCK_SIZE 512
// define map/reduce function type
typedef int (*map_function_t) (int, int);
typedef int (*reduce_function_t) (int, int);
__device__ int rand(int init0, int init1)
{
// multiply-with-carry RNG
init0 = 36969 * (init0 & 65535) + (init0 >> 16);
init1 = 18000 * (init1 & 65535) + (init1 >> 16);
return (init0 << 16) + init1; /* 32-bit result */
}
__device__ int square(int op)
{
return op * op;
}
__device__ int mul(int op0, int op1)
{
return op0 * op1;
}
__device__ int sum(int op0, int op1)
{
return op0 + op1;
}
__global__ void map(int *array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x * 2
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// do map in shared mem
if (id < size) {
// do first operation
shared[tid] = array[id];
array[id] = square(shared[tid]);
}
if (id + blockDim.x < size) {
// do second operation
shared[tid + blockDim.x] = array[id + blockDim.x];
array[id + blockDim.x] = square(shared[tid + blockDim.x]);
}
}
__global__ void reduce(int *in_array, int *out_array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// first sum
int t_sum = (id < size) ? in_array[id] : 0;
if (id + blockDim.x < size) {
// current reduce function is sum
t_sum = sum(in_array[id + blockDim.x], t_sum);
}
shared[tid] = t_sum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
// current reduce function is sum
t_sum = sum(t_sum, shared[tid + s]);
shared[tid] = t_sum;
}
__syncthreads();
}
if (tid == 0) {
out_array[blockIdx.x] = shared[0];
}
}
int mapreduce(int blocks, int threads, int *array_h, int size)
{
int res;
int *array_d;
int *in_ptr_d;
int *out_array_d;
int *tmp_d;
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
cudaMalloc((void **)&array_d, size * sizeof(int));
cudaMemcpy(array_d, array_h, size * sizeof(int),
cudaMemcpyHostToDevice);
in_ptr_d = array_d;
// do map
map <<< dim_grid, dim_block, threads * sizeof(int) >>> (array_d, size);
// do reduce in iterations
for (unsigned int s = blocks / 2; s > 0; s >>= 1) {
// allocate array equal to blocks/2
cudaMalloc((void **)&out_array_d, s * sizeof(int));
reduce <<< dim_grid, dim_block,
threads * sizeof(int) >>> (in_ptr_d, out_array_d, size);
// free up the old input array
tmp_d = in_ptr_d;
// should check for tmp_d != array_h but we can just fail silently
cudaFree(tmp_d);
// set input array of next iteration to output array
in_ptr_d = out_array_d;
size = s;
}
// retrieve result
cudaMemcpy(&res, out_array_d, sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(out_array_d);
cudaFree(array_d);
return res;
}
int mapreduce_host(int *array_h, int size)
{
int res = 0;
// map
for (int i = 0; i < size; i++) {
array_h[i] = array_h[i] * array_h[i];
}
// reduce
for (int i = 0; i < size; i++) {
res += array_h[i];
}
return res;
}
void usage(int which)
{
switch (which) {
default:
printf
("usage: mapreduce [-h|-b blocks|-t threads] <filename>\n");
break;
case 1:
printf("mapreduce input format:\nnum count\n1\n...\nn n\n");
break;
case 2:
printf("mapreduce requires numbers <= threads*blocks\n");
break;
}
}
int prepare_numbers(const char *filename, int **array)
{
int count, input, i;
FILE *file;
file = fopen(filename, "r");
// count of data is first line
fscanf(file, "%d", &count);
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (i = 0; i < count; i++) {
if (fscanf(file, "%d", &input) < 0) {
break;
}
numbers[i] = input;
}
fclose(file);
if (count != i) {
free(numbers);
return -1;
} else {
*array = numbers;
return count;
}
}
int main(int argc, char *argv[])
{
int opt, host_mode, blocks, threads, array_size, result;
int *array;
char *filename;
// set options
host_mode = 0;
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
while ((opt = getopt(argc, argv, "hb:t:")) != -1) {
switch (opt) {
case 'h':
host_mode = 1;
break;
case 'b':
blocks = atoi(optarg);
break;
case 't':
threads = atoi(optarg);
break;
default:
usage(0);
return 0;
}
}
// check to make sure we are feeding in correct number of args
if (argc == optind + 1) {
filename = argv[optind];
} else {
usage(0);
return 0;
}
// read file
array = NULL;
array_size = prepare_numbers(filename, &array);
if (array_size < 0) {
free(array);
usage(1);
return 0;
} else if (array_size >= blocks * threads) {
free(array);
usage(2);
return 0;
}
if (host_mode) {
printf("mapreduce using host\n");
result = mapreduce_host(array, array_size);
} else {
printf("mapreduce using CUDA\n");
result = mapreduce(blocks, threads, array, array_size);
}
printf("mapreduce result: %d\n", result);
free(array);
return 0;
} | .file "tmpxft_000bfa62_00000000-6_mapreduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4randii
.type _Z4randii, @function
_Z4randii:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z4randii, .-_Z4randii
.globl _Z6squarei
.type _Z6squarei, @function
_Z6squarei:
.LFB2071:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z6squarei, .-_Z6squarei
.globl _Z3mulii
.type _Z3mulii, @function
_Z3mulii:
.LFB2072:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2072:
.size _Z3mulii, .-_Z3mulii
.globl _Z3sumii
.type _Z3sumii, @function
_Z3sumii:
.LFB2073:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2073:
.size _Z3sumii, .-_Z3sumii
.globl _Z14mapreduce_hostPii
.type _Z14mapreduce_hostPii, @function
_Z14mapreduce_hostPii:
.LFB2075:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
movq %rdi, %rdx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
.L13:
movl (%rdi), %eax
imull %eax, %eax
movl %eax, (%rdi)
addq $4, %rdi
cmpq %rcx, %rdi
jne .L13
movl $0, %eax
.L14:
addl (%rdx), %eax
addq $4, %rdx
cmpq %rcx, %rdx
jne .L14
ret
.L15:
movl $0, %eax
ret
.cfi_endproc
.LFE2075:
.size _Z14mapreduce_hostPii, .-_Z14mapreduce_hostPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "usage: mapreduce [-h|-b blocks|-t threads] <filename>\n"
.align 8
.LC1:
.string "mapreduce input format:\nnum count\n1\n...\nn n\n"
.align 8
.LC2:
.string "mapreduce requires numbers <= threads*blocks\n"
.text
.globl _Z5usagei
.type _Z5usagei, @function
_Z5usagei:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
cmpl $1, %edi
je .L19
cmpl $2, %edi
je .L20
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L18:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L20:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.cfi_endproc
.LFE2076:
.size _Z5usagei, .-_Z5usagei
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "r"
.LC4:
.string "%d"
.text
.globl _Z15prepare_numbersPKcPPi
.type _Z15prepare_numbersPKcPPi, @function
_Z15prepare_numbersPKcPPi:
.LFB2077:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r15
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r12
movq %rsp, %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl (%rsp), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L29
movq %rax, %rbp
movl $0, %ebx
leaq .LC4(%rip), %r13
.L25:
leaq 4(%rsp), %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
js .L24
movl 4(%rsp), %eax
movl %eax, 0(%rbp)
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, (%rsp)
jg .L25
.L24:
movq %r12, %rdi
call fclose@PLT
movl (%rsp), %eax
cmpl %ebx, %eax
jne .L32
movq %r14, (%r15)
.L23:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L33
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $0, %ebx
jmp .L24
.L32:
movq %r14, %rdi
call free@PLT
movl $-1, %eax
jmp .L23
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z15prepare_numbersPKcPPi, .-_Z15prepare_numbersPKcPPi
.globl _Z23__device_stub__Z3mapPiiPii
.type _Z23__device_stub__Z3mapPiiPii, @function
_Z23__device_stub__Z3mapPiiPii:
.LFB2103:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3mapPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2103:
.size _Z23__device_stub__Z3mapPiiPii, .-_Z23__device_stub__Z3mapPiiPii
.globl _Z3mapPii
.type _Z3mapPii, @function
_Z3mapPii:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3mapPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _Z3mapPii, .-_Z3mapPii
.globl _Z28__device_stub__Z6reducePiS_iPiS_i
.type _Z28__device_stub__Z6reducePiS_iPiS_i, @function
_Z28__device_stub__Z6reducePiS_iPiS_i:
.LFB2105:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducePiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z28__device_stub__Z6reducePiS_iPiS_i, .-_Z28__device_stub__Z6reducePiS_iPiS_i
.globl _Z6reducePiS_i
.type _Z6reducePiS_i, @function
_Z6reducePiS_i:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducePiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _Z6reducePiS_i, .-_Z6reducePiS_i
.globl _Z9mapreduceiiPii
.type _Z9mapreduceiiPii, @function
_Z9mapreduceiiPii:
.LFB2074:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %r12d
movq %rdx, %r14
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edi, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %esi, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movslq %ecx, %rbp
salq $2, %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rbp
movslq %r12d, %r12
salq $2, %r12
movl 52(%rsp), %ecx
movl $0, %r9d
movq %r12, %r8
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L51:
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
movl %eax, %ebx
je .L52
leaq 24(%rsp), %r14
jmp .L54
.L58:
movl %r13d, %esi
movq 16(%rsp), %rdi
call _Z23__device_stub__Z3mapPiiPii
jmp .L51
.L53:
movq %rbp, %rdi
call cudaFree@PLT
movq 24(%rsp), %rbp
movl %ebx, %r13d
shrl %ebx
je .L52
.L54:
movl %ebx, %esi
salq $2, %rsi
movq %r14, %rdi
call cudaMalloc@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movq %r12, %r8
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L53
movl %r13d, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call _Z28__device_stub__Z6reducePiS_iPiS_i
jmp .L53
.L52:
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl 12(%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L59
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z9mapreduceiiPii, .-_Z9mapreduceiiPii
.section .rodata.str1.1
.LC5:
.string "hb:t:"
.LC6:
.string "mapreduce using host\n"
.LC7:
.string "mapreduce using CUDA\n"
.LC8:
.string "mapreduce result: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2078:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $512, %r14d
movl $32, %r13d
movl $0, %r15d
leaq .LC5(%rip), %r12
.L62:
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call getopt@PLT
cmpl $-1, %eax
je .L78
cmpl $104, %eax
je .L75
cmpl $116, %eax
je .L63
cmpl $98, %eax
jne .L64
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r13d
jmp .L62
.L63:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r14d
jmp .L62
.L64:
movl $0, %edi
call _Z5usagei
.L66:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L79
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
movl $1, %r15d
jmp .L62
.L78:
movl optind(%rip), %eax
leal 1(%rax), %edx
cmpl %ebx, %edx
jne .L68
cltq
movq 0(%rbp,%rax,8), %rdi
movq $0, (%rsp)
movq %rsp, %rsi
call _Z15prepare_numbersPKcPPi
movl %eax, %ebx
testl %eax, %eax
js .L80
movl %r13d, %eax
imull %r14d, %eax
cmpl %ebx, %eax
jle .L81
testl %r15d, %r15d
je .L72
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq (%rsp), %rdi
call _Z14mapreduce_hostPii
movl %eax, %edx
.L73:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call free@PLT
jmp .L66
.L68:
movl $0, %edi
call _Z5usagei
jmp .L66
.L80:
movq (%rsp), %rdi
call free@PLT
movl $1, %edi
call _Z5usagei
jmp .L66
.L81:
movq (%rsp), %rdi
call free@PLT
movl $2, %edi
call _Z5usagei
jmp .L66
.L72:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movq (%rsp), %rdx
movl %r14d, %esi
movl %r13d, %edi
call _Z9mapreduceiiPii
movl %eax, %edx
jmp .L73
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2078:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z6reducePiS_i"
.LC10:
.string "_Z3mapPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2108:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mapPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* UCLA Spring 2011
* CS239
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#define NUM_BLOCKS 32
#define BLOCK_SIZE 512
// define map/reduce function type
typedef int (*map_function_t) (int, int);
typedef int (*reduce_function_t) (int, int);
__device__ int rand(int init0, int init1)
{
// multiply-with-carry RNG
init0 = 36969 * (init0 & 65535) + (init0 >> 16);
init1 = 18000 * (init1 & 65535) + (init1 >> 16);
return (init0 << 16) + init1; /* 32-bit result */
}
__device__ int square(int op)
{
return op * op;
}
__device__ int mul(int op0, int op1)
{
return op0 * op1;
}
__device__ int sum(int op0, int op1)
{
return op0 + op1;
}
__global__ void map(int *array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x * 2
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// do map in shared mem
if (id < size) {
// do first operation
shared[tid] = array[id];
array[id] = square(shared[tid]);
}
if (id + blockDim.x < size) {
// do second operation
shared[tid + blockDim.x] = array[id + blockDim.x];
array[id + blockDim.x] = square(shared[tid + blockDim.x]);
}
}
__global__ void reduce(int *in_array, int *out_array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// first sum
int t_sum = (id < size) ? in_array[id] : 0;
if (id + blockDim.x < size) {
// current reduce function is sum
t_sum = sum(in_array[id + blockDim.x], t_sum);
}
shared[tid] = t_sum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
// current reduce function is sum
t_sum = sum(t_sum, shared[tid + s]);
shared[tid] = t_sum;
}
__syncthreads();
}
if (tid == 0) {
out_array[blockIdx.x] = shared[0];
}
}
int mapreduce(int blocks, int threads, int *array_h, int size)
{
int res;
int *array_d;
int *in_ptr_d;
int *out_array_d;
int *tmp_d;
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
cudaMalloc((void **)&array_d, size * sizeof(int));
cudaMemcpy(array_d, array_h, size * sizeof(int),
cudaMemcpyHostToDevice);
in_ptr_d = array_d;
// do map
map <<< dim_grid, dim_block, threads * sizeof(int) >>> (array_d, size);
// do reduce in iterations
for (unsigned int s = blocks / 2; s > 0; s >>= 1) {
// allocate array equal to blocks/2
cudaMalloc((void **)&out_array_d, s * sizeof(int));
reduce <<< dim_grid, dim_block,
threads * sizeof(int) >>> (in_ptr_d, out_array_d, size);
// free up the old input array
tmp_d = in_ptr_d;
// should check for tmp_d != array_h but we can just fail silently
cudaFree(tmp_d);
// set input array of next iteration to output array
in_ptr_d = out_array_d;
size = s;
}
// retrieve result
cudaMemcpy(&res, out_array_d, sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(out_array_d);
cudaFree(array_d);
return res;
}
int mapreduce_host(int *array_h, int size)
{
int res = 0;
// map
for (int i = 0; i < size; i++) {
array_h[i] = array_h[i] * array_h[i];
}
// reduce
for (int i = 0; i < size; i++) {
res += array_h[i];
}
return res;
}
void usage(int which)
{
switch (which) {
default:
printf
("usage: mapreduce [-h|-b blocks|-t threads] <filename>\n");
break;
case 1:
printf("mapreduce input format:\nnum count\n1\n...\nn n\n");
break;
case 2:
printf("mapreduce requires numbers <= threads*blocks\n");
break;
}
}
int prepare_numbers(const char *filename, int **array)
{
int count, input, i;
FILE *file;
file = fopen(filename, "r");
// count of data is first line
fscanf(file, "%d", &count);
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (i = 0; i < count; i++) {
if (fscanf(file, "%d", &input) < 0) {
break;
}
numbers[i] = input;
}
fclose(file);
if (count != i) {
free(numbers);
return -1;
} else {
*array = numbers;
return count;
}
}
int main(int argc, char *argv[])
{
int opt, host_mode, blocks, threads, array_size, result;
int *array;
char *filename;
// set options
host_mode = 0;
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
while ((opt = getopt(argc, argv, "hb:t:")) != -1) {
switch (opt) {
case 'h':
host_mode = 1;
break;
case 'b':
blocks = atoi(optarg);
break;
case 't':
threads = atoi(optarg);
break;
default:
usage(0);
return 0;
}
}
// check to make sure we are feeding in correct number of args
if (argc == optind + 1) {
filename = argv[optind];
} else {
usage(0);
return 0;
}
// read file
array = NULL;
array_size = prepare_numbers(filename, &array);
if (array_size < 0) {
free(array);
usage(1);
return 0;
} else if (array_size >= blocks * threads) {
free(array);
usage(2);
return 0;
}
if (host_mode) {
printf("mapreduce using host\n");
result = mapreduce_host(array, array_size);
} else {
printf("mapreduce using CUDA\n");
result = mapreduce(blocks, threads, array, array_size);
}
printf("mapreduce result: %d\n", result);
free(array);
return 0;
} | /*
* UCLA Spring 2011
* CS239
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#define NUM_BLOCKS 32
#define BLOCK_SIZE 512
// define map/reduce function type
typedef int (*map_function_t) (int, int);
typedef int (*reduce_function_t) (int, int);
__device__ int rand(int init0, int init1)
{
// multiply-with-carry RNG
init0 = 36969 * (init0 & 65535) + (init0 >> 16);
init1 = 18000 * (init1 & 65535) + (init1 >> 16);
return (init0 << 16) + init1; /* 32-bit result */
}
__device__ int square(int op)
{
return op * op;
}
__device__ int mul(int op0, int op1)
{
return op0 * op1;
}
__device__ int sum(int op0, int op1)
{
return op0 + op1;
}
__global__ void map(int *array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x * 2
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// do map in shared mem
if (id < size) {
// do first operation
shared[tid] = array[id];
array[id] = square(shared[tid]);
}
if (id + blockDim.x < size) {
// do second operation
shared[tid + blockDim.x] = array[id + blockDim.x];
array[id + blockDim.x] = square(shared[tid + blockDim.x]);
}
}
__global__ void reduce(int *in_array, int *out_array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// first sum
int t_sum = (id < size) ? in_array[id] : 0;
if (id + blockDim.x < size) {
// current reduce function is sum
t_sum = sum(in_array[id + blockDim.x], t_sum);
}
shared[tid] = t_sum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
// current reduce function is sum
t_sum = sum(t_sum, shared[tid + s]);
shared[tid] = t_sum;
}
__syncthreads();
}
if (tid == 0) {
out_array[blockIdx.x] = shared[0];
}
}
int mapreduce(int blocks, int threads, int *array_h, int size)
{
int res;
int *array_d;
int *in_ptr_d;
int *out_array_d;
int *tmp_d;
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
hipMalloc((void **)&array_d, size * sizeof(int));
hipMemcpy(array_d, array_h, size * sizeof(int),
hipMemcpyHostToDevice);
in_ptr_d = array_d;
// do map
map <<< dim_grid, dim_block, threads * sizeof(int) >>> (array_d, size);
// do reduce in iterations
for (unsigned int s = blocks / 2; s > 0; s >>= 1) {
// allocate array equal to blocks/2
hipMalloc((void **)&out_array_d, s * sizeof(int));
reduce <<< dim_grid, dim_block,
threads * sizeof(int) >>> (in_ptr_d, out_array_d, size);
// free up the old input array
tmp_d = in_ptr_d;
// should check for tmp_d != array_h but we can just fail silently
hipFree(tmp_d);
// set input array of next iteration to output array
in_ptr_d = out_array_d;
size = s;
}
// retrieve result
hipMemcpy(&res, out_array_d, sizeof(int), hipMemcpyDeviceToHost);
hipFree(out_array_d);
hipFree(array_d);
return res;
}
int mapreduce_host(int *array_h, int size)
{
int res = 0;
// map
for (int i = 0; i < size; i++) {
array_h[i] = array_h[i] * array_h[i];
}
// reduce
for (int i = 0; i < size; i++) {
res += array_h[i];
}
return res;
}
void usage(int which)
{
switch (which) {
default:
printf
("usage: mapreduce [-h|-b blocks|-t threads] <filename>\n");
break;
case 1:
printf("mapreduce input format:\nnum count\n1\n...\nn n\n");
break;
case 2:
printf("mapreduce requires numbers <= threads*blocks\n");
break;
}
}
int prepare_numbers(const char *filename, int **array)
{
int count, input, i;
FILE *file;
file = fopen(filename, "r");
// count of data is first line
fscanf(file, "%d", &count);
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (i = 0; i < count; i++) {
if (fscanf(file, "%d", &input) < 0) {
break;
}
numbers[i] = input;
}
fclose(file);
if (count != i) {
free(numbers);
return -1;
} else {
*array = numbers;
return count;
}
}
int main(int argc, char *argv[])
{
int opt, host_mode, blocks, threads, array_size, result;
int *array;
char *filename;
// set options
host_mode = 0;
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
while ((opt = getopt(argc, argv, "hb:t:")) != -1) {
switch (opt) {
case 'h':
host_mode = 1;
break;
case 'b':
blocks = atoi(optarg);
break;
case 't':
threads = atoi(optarg);
break;
default:
usage(0);
return 0;
}
}
// check to make sure we are feeding in correct number of args
if (argc == optind + 1) {
filename = argv[optind];
} else {
usage(0);
return 0;
}
// read file
array = NULL;
array_size = prepare_numbers(filename, &array);
if (array_size < 0) {
free(array);
usage(1);
return 0;
} else if (array_size >= blocks * threads) {
free(array);
usage(2);
return 0;
}
if (host_mode) {
printf("mapreduce using host\n");
result = mapreduce_host(array, array_size);
} else {
printf("mapreduce using CUDA\n");
result = mapreduce(blocks, threads, array, array_size);
}
printf("mapreduce result: %d\n", result);
free(array);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* UCLA Spring 2011
* CS239
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#define NUM_BLOCKS 32
#define BLOCK_SIZE 512
// define map/reduce function type
typedef int (*map_function_t) (int, int);
typedef int (*reduce_function_t) (int, int);
__device__ int rand(int init0, int init1)
{
// multiply-with-carry RNG
init0 = 36969 * (init0 & 65535) + (init0 >> 16);
init1 = 18000 * (init1 & 65535) + (init1 >> 16);
return (init0 << 16) + init1; /* 32-bit result */
}
__device__ int square(int op)
{
return op * op;
}
__device__ int mul(int op0, int op1)
{
return op0 * op1;
}
__device__ int sum(int op0, int op1)
{
return op0 + op1;
}
__global__ void map(int *array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x * 2
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// do map in shared mem
if (id < size) {
// do first operation
shared[tid] = array[id];
array[id] = square(shared[tid]);
}
if (id + blockDim.x < size) {
// do second operation
shared[tid + blockDim.x] = array[id + blockDim.x];
array[id + blockDim.x] = square(shared[tid + blockDim.x]);
}
}
__global__ void reduce(int *in_array, int *out_array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// first sum
int t_sum = (id < size) ? in_array[id] : 0;
if (id + blockDim.x < size) {
// current reduce function is sum
t_sum = sum(in_array[id + blockDim.x], t_sum);
}
shared[tid] = t_sum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
// current reduce function is sum
t_sum = sum(t_sum, shared[tid + s]);
shared[tid] = t_sum;
}
__syncthreads();
}
if (tid == 0) {
out_array[blockIdx.x] = shared[0];
}
}
int mapreduce(int blocks, int threads, int *array_h, int size)
{
int res;
int *array_d;
int *in_ptr_d;
int *out_array_d;
int *tmp_d;
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
hipMalloc((void **)&array_d, size * sizeof(int));
hipMemcpy(array_d, array_h, size * sizeof(int),
hipMemcpyHostToDevice);
in_ptr_d = array_d;
// do map
map <<< dim_grid, dim_block, threads * sizeof(int) >>> (array_d, size);
// do reduce in iterations
for (unsigned int s = blocks / 2; s > 0; s >>= 1) {
// allocate array equal to blocks/2
hipMalloc((void **)&out_array_d, s * sizeof(int));
reduce <<< dim_grid, dim_block,
threads * sizeof(int) >>> (in_ptr_d, out_array_d, size);
// free up the old input array
tmp_d = in_ptr_d;
// should check for tmp_d != array_h but we can just fail silently
hipFree(tmp_d);
// set input array of next iteration to output array
in_ptr_d = out_array_d;
size = s;
}
// retrieve result
hipMemcpy(&res, out_array_d, sizeof(int), hipMemcpyDeviceToHost);
hipFree(out_array_d);
hipFree(array_d);
return res;
}
int mapreduce_host(int *array_h, int size)
{
int res = 0;
// map
for (int i = 0; i < size; i++) {
array_h[i] = array_h[i] * array_h[i];
}
// reduce
for (int i = 0; i < size; i++) {
res += array_h[i];
}
return res;
}
void usage(int which)
{
switch (which) {
default:
printf
("usage: mapreduce [-h|-b blocks|-t threads] <filename>\n");
break;
case 1:
printf("mapreduce input format:\nnum count\n1\n...\nn n\n");
break;
case 2:
printf("mapreduce requires numbers <= threads*blocks\n");
break;
}
}
int prepare_numbers(const char *filename, int **array)
{
int count, input, i;
FILE *file;
file = fopen(filename, "r");
// count of data is first line
fscanf(file, "%d", &count);
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (i = 0; i < count; i++) {
if (fscanf(file, "%d", &input) < 0) {
break;
}
numbers[i] = input;
}
fclose(file);
if (count != i) {
free(numbers);
return -1;
} else {
*array = numbers;
return count;
}
}
int main(int argc, char *argv[])
{
int opt, host_mode, blocks, threads, array_size, result;
int *array;
char *filename;
// set options
host_mode = 0;
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
while ((opt = getopt(argc, argv, "hb:t:")) != -1) {
switch (opt) {
case 'h':
host_mode = 1;
break;
case 'b':
blocks = atoi(optarg);
break;
case 't':
threads = atoi(optarg);
break;
default:
usage(0);
return 0;
}
}
// check to make sure we are feeding in correct number of args
if (argc == optind + 1) {
filename = argv[optind];
} else {
usage(0);
return 0;
}
// read file
array = NULL;
array_size = prepare_numbers(filename, &array);
if (array_size < 0) {
free(array);
usage(1);
return 0;
} else if (array_size >= blocks * threads) {
free(array);
usage(2);
return 0;
}
if (host_mode) {
printf("mapreduce using host\n");
result = mapreduce_host(array, array_size);
} else {
printf("mapreduce using CUDA\n");
result = mapreduce(blocks, threads, array, array_size);
}
printf("mapreduce result: %d\n", result);
free(array);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mapPii
.globl _Z3mapPii
.p2align 8
.type _Z3mapPii,@function
_Z3mapPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_lshl_add_u32 v1, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v6, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v4, v4
ds_store_b32 v6, v4
global_store_b32 v[2:3], v5, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshl_add_u32 v0, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v3, v3
ds_store_b32 v0, v3
global_store_b32 v[1:2], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mapPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mapPii, .Lfunc_end0-_Z3mapPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6reducePiS_i
.globl _Z6reducePiS_i
.p2align 8
.type _Z6reducePiS_i,@function
_Z6reducePiS_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s3
v_lshl_add_u32 v1, s7, 1, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB1_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v1, v3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s6
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB1_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_9
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_5
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v2, v3
ds_store_b32 v1, v3
s_branch .LBB1_5
.LBB1_9:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_11
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducePiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6reducePiS_i, .Lfunc_end1-_Z6reducePiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mapPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mapPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducePiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducePiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* UCLA Spring 2011
* CS239
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#define NUM_BLOCKS 32
#define BLOCK_SIZE 512
// define map/reduce function type
typedef int (*map_function_t) (int, int);
typedef int (*reduce_function_t) (int, int);
__device__ int rand(int init0, int init1)
{
// multiply-with-carry RNG
init0 = 36969 * (init0 & 65535) + (init0 >> 16);
init1 = 18000 * (init1 & 65535) + (init1 >> 16);
return (init0 << 16) + init1; /* 32-bit result */
}
__device__ int square(int op)
{
return op * op;
}
__device__ int mul(int op0, int op1)
{
return op0 * op1;
}
__device__ int sum(int op0, int op1)
{
return op0 + op1;
}
__global__ void map(int *array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x * 2
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// do map in shared mem
if (id < size) {
// do first operation
shared[tid] = array[id];
array[id] = square(shared[tid]);
}
if (id + blockDim.x < size) {
// do second operation
shared[tid + blockDim.x] = array[id + blockDim.x];
array[id + blockDim.x] = square(shared[tid + blockDim.x]);
}
}
__global__ void reduce(int *in_array, int *out_array, int size)
{
// gridDim.x * blockDim.x >= size / 2
// shared should be sized to blockDim.x
extern __shared__ int shared[];
unsigned int tid = threadIdx.x;
unsigned int id = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
// first sum
int t_sum = (id < size) ? in_array[id] : 0;
if (id + blockDim.x < size) {
// current reduce function is sum
t_sum = sum(in_array[id + blockDim.x], t_sum);
}
shared[tid] = t_sum;
__syncthreads();
// do reduction in shared mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
// current reduce function is sum
t_sum = sum(t_sum, shared[tid + s]);
shared[tid] = t_sum;
}
__syncthreads();
}
if (tid == 0) {
out_array[blockIdx.x] = shared[0];
}
}
int mapreduce(int blocks, int threads, int *array_h, int size)
{
int res;
int *array_d;
int *in_ptr_d;
int *out_array_d;
int *tmp_d;
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
hipMalloc((void **)&array_d, size * sizeof(int));
hipMemcpy(array_d, array_h, size * sizeof(int),
hipMemcpyHostToDevice);
in_ptr_d = array_d;
// do map
map <<< dim_grid, dim_block, threads * sizeof(int) >>> (array_d, size);
// do reduce in iterations
for (unsigned int s = blocks / 2; s > 0; s >>= 1) {
// allocate array equal to blocks/2
hipMalloc((void **)&out_array_d, s * sizeof(int));
reduce <<< dim_grid, dim_block,
threads * sizeof(int) >>> (in_ptr_d, out_array_d, size);
// free up the old input array
tmp_d = in_ptr_d;
// should check for tmp_d != array_h but we can just fail silently
hipFree(tmp_d);
// set input array of next iteration to output array
in_ptr_d = out_array_d;
size = s;
}
// retrieve result
hipMemcpy(&res, out_array_d, sizeof(int), hipMemcpyDeviceToHost);
hipFree(out_array_d);
hipFree(array_d);
return res;
}
int mapreduce_host(int *array_h, int size)
{
int res = 0;
// map
for (int i = 0; i < size; i++) {
array_h[i] = array_h[i] * array_h[i];
}
// reduce
for (int i = 0; i < size; i++) {
res += array_h[i];
}
return res;
}
void usage(int which)
{
switch (which) {
default:
printf
("usage: mapreduce [-h|-b blocks|-t threads] <filename>\n");
break;
case 1:
printf("mapreduce input format:\nnum count\n1\n...\nn n\n");
break;
case 2:
printf("mapreduce requires numbers <= threads*blocks\n");
break;
}
}
int prepare_numbers(const char *filename, int **array)
{
int count, input, i;
FILE *file;
file = fopen(filename, "r");
// count of data is first line
fscanf(file, "%d", &count);
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (i = 0; i < count; i++) {
if (fscanf(file, "%d", &input) < 0) {
break;
}
numbers[i] = input;
}
fclose(file);
if (count != i) {
free(numbers);
return -1;
} else {
*array = numbers;
return count;
}
}
int main(int argc, char *argv[])
{
int opt, host_mode, blocks, threads, array_size, result;
int *array;
char *filename;
// set options
host_mode = 0;
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
while ((opt = getopt(argc, argv, "hb:t:")) != -1) {
switch (opt) {
case 'h':
host_mode = 1;
break;
case 'b':
blocks = atoi(optarg);
break;
case 't':
threads = atoi(optarg);
break;
default:
usage(0);
return 0;
}
}
// check to make sure we are feeding in correct number of args
if (argc == optind + 1) {
filename = argv[optind];
} else {
usage(0);
return 0;
}
// read file
array = NULL;
array_size = prepare_numbers(filename, &array);
if (array_size < 0) {
free(array);
usage(1);
return 0;
} else if (array_size >= blocks * threads) {
free(array);
usage(2);
return 0;
}
if (host_mode) {
printf("mapreduce using host\n");
result = mapreduce_host(array, array_size);
} else {
printf("mapreduce using CUDA\n");
result = mapreduce(blocks, threads, array, array_size);
}
printf("mapreduce result: %d\n", result);
free(array);
return 0;
} | .text
.file "mapreduce.hip"
.globl _Z18__device_stub__mapPii # -- Begin function _Z18__device_stub__mapPii
.p2align 4, 0x90
.type _Z18__device_stub__mapPii,@function
_Z18__device_stub__mapPii: # @_Z18__device_stub__mapPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3mapPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__mapPii, .Lfunc_end0-_Z18__device_stub__mapPii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__reducePiS_i # -- Begin function _Z21__device_stub__reducePiS_i
.p2align 4, 0x90
.type _Z21__device_stub__reducePiS_i,@function
_Z21__device_stub__reducePiS_i: # @_Z21__device_stub__reducePiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__reducePiS_i, .Lfunc_end1-_Z21__device_stub__reducePiS_i
.cfi_endproc
# -- End function
.globl _Z9mapreduceiiPii # -- Begin function _Z9mapreduceiiPii
.p2align 4, 0x90
.type _Z9mapreduceiiPii,@function
_Z9mapreduceiiPii: # @_Z9mapreduceiiPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r13d
movq %rdx, %r15
movl %esi, %ebp
# kill: def $edi killed $edi def $rdi
movq %rdi, 128(%rsp) # 8-byte Spill
movl %edi, %ebx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %esi, %r14d
orq %rax, %r14
movslq %ecx, %r12
shlq $2, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %r12
movslq %ebp, %r15
shlq $2, %r15
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl %r13d, 24(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3mapPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 128(%rsp), %rcx # 8-byte Reload
leal 1(%rcx), %eax
cmpl $3, %eax
jae .LBB2_3
.LBB2_7: # %._crit_edge
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl 96(%rsp), %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_3: # %.lr.ph
.cfi_def_cfa_offset 192
movq %rcx, %rax
movl %eax, %ebp
shrl $31, %ebp
addl %eax, %ebp
sarl %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=1
movq %r12, %rdi
callq hipFree
movq 8(%rsp), %r12
movl %ebp, %eax
shrl %eax
movl %ebp, %r13d
cmpl $2, %ebp
movl %eax, %ebp
jb .LBB2_7
.LBB2_4: # =>This Inner Loop Header: Depth=1
movl %ebp, %esi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
movq 8(%rsp), %rax
movq %r12, 80(%rsp)
movq %rax, 72(%rsp)
movl %r13d, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 92(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6reducePiS_i, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_6
.Lfunc_end2:
.size _Z9mapreduceiiPii, .Lfunc_end2-_Z9mapreduceiiPii
.cfi_endproc
# -- End function
.globl _Z14mapreduce_hostPii # -- Begin function _Z14mapreduce_hostPii
.p2align 4, 0x90
.type _Z14mapreduce_hostPii,@function
_Z14mapreduce_hostPii: # @_Z14mapreduce_hostPii
.cfi_startproc
# %bb.0:
movl %esi, %ecx
testl %esi, %esi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%rax,4), %edx
imull %edx, %edx
movl %edx, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rcx
jne .LBB3_2
.LBB3_3: # %.preheader
testl %esi, %esi
jle .LBB3_4
# %bb.6: # %.lr.ph21.preheader
xorl %edx, %edx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_7: # %.lr.ph21
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rdx,4), %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_7
# %bb.5: # %._crit_edge
retq
.LBB3_4:
xorl %eax, %eax
retq
.Lfunc_end3:
.size _Z14mapreduce_hostPii, .Lfunc_end3-_Z14mapreduce_hostPii
.cfi_endproc
# -- End function
.globl _Z5usagei # -- Begin function _Z5usagei
.p2align 4, 0x90
.type _Z5usagei,@function
_Z5usagei: # @_Z5usagei
.cfi_startproc
# %bb.0:
cmpl $2, %edi
movl $.Lstr, %eax
movl $.Lstr.2, %ecx
cmoveq %rax, %rcx
cmpl $1, %edi
movl $.Lstr.1, %edi
cmovneq %rcx, %rdi
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z5usagei, .Lfunc_end4-_Z5usagei
.cfi_endproc
# -- End function
.globl _Z15prepare_numbersPKcPPi # -- Begin function _Z15prepare_numbersPKcPPi
.p2align 4, 0x90
.type _Z15prepare_numbersPKcPPi,@function
_Z15prepare_numbersPKcPPi: # @_Z15prepare_numbersPKcPPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
xorl %r13d, %r13d
leaq 8(%rsp), %rdx
movl $.L.str.4, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq 8(%rsp), %r12
leaq (,%r12,4), %rdi
callq malloc
movq %rax, %r15
testq %r12, %r12
jle .LBB5_4
# %bb.1: # %.lr.ph.preheader
leaq 12(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
js .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl 12(%rsp), %eax
movl %eax, (%r15,%r13,4)
incq %r13
movslq 8(%rsp), %rax
cmpq %rax, %r13
jl .LBB5_2
.LBB5_4: # %._crit_edge
movq %r14, %rdi
callq fclose
movl 8(%rsp), %eax
cmpl %r13d, %eax
jne .LBB5_5
# %bb.6:
movq %r15, (%rbx)
jmp .LBB5_7
.LBB5_5:
movq %r15, %rdi
callq free
movl $-1, %eax
.LBB5_7:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z15prepare_numbersPKcPPi, .Lfunc_end5-_Z15prepare_numbersPKcPPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %ebp
xorl %r12d, %r12d
movl $512, %ebx # imm = 0x200
movl $32, %r14d
.LBB6_1: # %.outer36
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
movl %r12d, %ecx
.p2align 4, 0x90
.LBB6_2: # Parent Loop BB6_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %r12d
movl $.L.str.5, %edx
movl %ebp, %edi
movq %r15, %rsi
callq getopt
movl $1, %ecx
cmpl $104, %eax
je .LBB6_2
# %bb.3: # in Loop: Header=BB6_1 Depth=1
cmpl $-1, %eax
je .LBB6_8
# %bb.4: # in Loop: Header=BB6_1 Depth=1
cmpl $116, %eax
je .LBB6_7
# %bb.5: # in Loop: Header=BB6_1 Depth=1
cmpl $98, %eax
jne .LBB6_18
# %bb.6: # in Loop: Header=BB6_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_7: # in Loop: Header=BB6_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB6_1
.LBB6_8:
movslq optind(%rip), %rax
leal 1(%rax), %ecx
cmpl %ebp, %ecx
jne .LBB6_18
# %bb.9:
movq (%r15,%rax,8), %rdi
movq $0, 8(%rsp)
leaq 8(%rsp), %rsi
callq _Z15prepare_numbersPKcPPi
testl %eax, %eax
js .LBB6_21
# %bb.10:
movl %ebx, %ecx
imull %r14d, %ecx
cmpl %ecx, %eax
jge .LBB6_22
# %bb.11:
movl %eax, %ebp
testl %r12d, %r12d
je .LBB6_23
# %bb.12:
movl $.Lstr.4, %edi
callq puts@PLT
testl %ebp, %ebp
je .LBB6_25
# %bb.13: # %.lr.ph.preheader.i
movq 8(%rsp), %rax
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_14: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%rax,%rdx,4), %esi
imull %esi, %esi
movl %esi, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB6_14
# %bb.15: # %.preheader.i
testl %ebp, %ebp
je .LBB6_25
# %bb.16: # %.lr.ph21.preheader.i
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_17: # %.lr.ph21.i
# =>This Inner Loop Header: Depth=1
addl (%rax,%rdx,4), %esi
incq %rdx
cmpq %rdx, %rcx
jne .LBB6_17
jmp .LBB6_26
.LBB6_18:
movl $.Lstr.2, %edi
.LBB6_19:
callq puts@PLT
.LBB6_20:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_21:
.cfi_def_cfa_offset 64
movq 8(%rsp), %rdi
callq free
movl $.Lstr.1, %edi
jmp .LBB6_19
.LBB6_22:
movq 8(%rsp), %rdi
callq free
movl $.Lstr, %edi
jmp .LBB6_19
.LBB6_25:
xorl %esi, %esi
jmp .LBB6_26
.LBB6_23:
movl $.Lstr.3, %edi
callq puts@PLT
movq 8(%rsp), %rdx
movl %r14d, %edi
movl %ebx, %esi
movl %ebp, %ecx
callq _Z9mapreduceiiPii
movl %eax, %esi
.LBB6_26: # %_Z14mapreduce_hostPii.exit
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq free
jmp .LBB6_20
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mapPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mapPii,@object # @_Z3mapPii
.section .rodata,"a",@progbits
.globl _Z3mapPii
.p2align 3, 0x0
_Z3mapPii:
.quad _Z18__device_stub__mapPii
.size _Z3mapPii, 8
.type _Z6reducePiS_i,@object # @_Z6reducePiS_i
.globl _Z6reducePiS_i
.p2align 3, 0x0
_Z6reducePiS_i:
.quad _Z21__device_stub__reducePiS_i
.size _Z6reducePiS_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hb:t:"
.size .L.str.5, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "mapreduce result: %d\n"
.size .L.str.8, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mapPii"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6reducePiS_i"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "mapreduce requires numbers <= threads*blocks"
.size .Lstr, 45
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "mapreduce input format:\nnum count\n1\n...\nn n"
.size .Lstr.1, 44
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "usage: mapreduce [-h|-b blocks|-t threads] <filename>"
.size .Lstr.2, 54
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "mapreduce using CUDA"
.size .Lstr.3, 21
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "mapreduce using host"
.size .Lstr.4, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mapPii
.addrsig_sym _Z21__device_stub__reducePiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mapPii
.addrsig_sym _Z6reducePiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6reducePiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ IMAD R2, R6, UR5, R7 ; /* 0x0000000506027c24 */
/* 0x001fca000f8e0207 */
/*0080*/ IADD3 R4, R2.reuse, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x040fe40007ffe0ff */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f26070 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fd60003f06070 */
/*00b0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fe400078e00ff */
/*00c0*/ @!P0 MOV R5, 0x4 ; /* 0x0000000400058802 */
/* 0x000fe40000000f00 */
/*00d0*/ @!P1 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fc800078e0003 */
/*00e0*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fe200078e0005 */
/*00f0*/ @!P1 LDG.E R0, [R2.64] ; /* 0x0000000602009981 */
/* 0x000eaa000c1e1900 */
/*0100*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000604058981 */
/* 0x000ea2000c1e1900 */
/*0110*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0120*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fca0003f25270 */
/*0130*/ ISETP.NE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45270 */
/*0140*/ @!P0 IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100008824 */
/* 0x004fca00078e0205 */
/*0150*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P2 BRA 0x230 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*0180*/ SHF.L.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027819 */
/* 0x001fe200000006ff */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f06070 */
/*01b0*/ @!P0 LEA R4, R3, R2, 0x2 ; /* 0x0000000203048211 */
/* 0x000fe400078e10ff */
/*01c0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*01d0*/ @!P0 LDS R5, [R4] ; /* 0x0000000004058984 */
/* 0x000e240000000800 */
/*01e0*/ @!P0 IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100008824 */
/* 0x001fca00078e0205 */
/*01f0*/ @!P0 STS [R7.X4], R0 ; /* 0x0000000007008388 */
/* 0x0001e80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0210*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 BRA 0x1a0 ; /* 0xffffff7000000947 */
/* 0x001fea000383ffff */
/*0230*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*0240*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0250*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0260*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3mapPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e2a0000002100 */
/*0060*/ IMAD R2, R2, UR4, R7 ; /* 0x0000000402027c24 */
/* 0x001fe2000f8e0207 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x040fe40003f06070 */
/*0090*/ IADD3 R4, R2, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x000fc80007ffe0ff */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fce0003f26070 */
/*00b0*/ @P0 BRA 0x120 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fe400078e02ff */
/*0100*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0140*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fca0000000f00 */
/*0150*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0003 */
/*0160*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IADD3 R5, R7, c[0x0][0x0], RZ ; /* 0x0000000007057a10 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD R7, R0, R0, RZ ; /* 0x0000000000077224 */
/* 0x004fc800078e02ff */
/*0190*/ STS [R5.X4], R0 ; /* 0x0000000005007388 */
/* 0x000fe80000004800 */
/*01a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mapPii
.globl _Z3mapPii
.p2align 8
.type _Z3mapPii,@function
_Z3mapPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_lshl_add_u32 v1, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v6, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v4, v4
ds_store_b32 v6, v4
global_store_b32 v[2:3], v5, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshl_add_u32 v0, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v3, v3
ds_store_b32 v0, v3
global_store_b32 v[1:2], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mapPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mapPii, .Lfunc_end0-_Z3mapPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6reducePiS_i
.globl _Z6reducePiS_i
.p2align 8
.type _Z6reducePiS_i,@function
_Z6reducePiS_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s3
v_lshl_add_u32 v1, s7, 1, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB1_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v1, v3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s6
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB1_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_9
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_5
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v2, v3
ds_store_b32 v1, v3
s_branch .LBB1_5
.LBB1_9:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_11
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducePiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6reducePiS_i, .Lfunc_end1-_Z6reducePiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mapPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mapPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducePiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducePiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bfa62_00000000-6_mapreduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4randii
.type _Z4randii, @function
_Z4randii:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z4randii, .-_Z4randii
.globl _Z6squarei
.type _Z6squarei, @function
_Z6squarei:
.LFB2071:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z6squarei, .-_Z6squarei
.globl _Z3mulii
.type _Z3mulii, @function
_Z3mulii:
.LFB2072:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2072:
.size _Z3mulii, .-_Z3mulii
.globl _Z3sumii
.type _Z3sumii, @function
_Z3sumii:
.LFB2073:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2073:
.size _Z3sumii, .-_Z3sumii
.globl _Z14mapreduce_hostPii
.type _Z14mapreduce_hostPii, @function
_Z14mapreduce_hostPii:
.LFB2075:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
movq %rdi, %rdx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
.L13:
movl (%rdi), %eax
imull %eax, %eax
movl %eax, (%rdi)
addq $4, %rdi
cmpq %rcx, %rdi
jne .L13
movl $0, %eax
.L14:
addl (%rdx), %eax
addq $4, %rdx
cmpq %rcx, %rdx
jne .L14
ret
.L15:
movl $0, %eax
ret
.cfi_endproc
.LFE2075:
.size _Z14mapreduce_hostPii, .-_Z14mapreduce_hostPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "usage: mapreduce [-h|-b blocks|-t threads] <filename>\n"
.align 8
.LC1:
.string "mapreduce input format:\nnum count\n1\n...\nn n\n"
.align 8
.LC2:
.string "mapreduce requires numbers <= threads*blocks\n"
.text
.globl _Z5usagei
.type _Z5usagei, @function
_Z5usagei:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
cmpl $1, %edi
je .L19
cmpl $2, %edi
je .L20
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L18:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L20:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.cfi_endproc
.LFE2076:
.size _Z5usagei, .-_Z5usagei
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "r"
.LC4:
.string "%d"
.text
.globl _Z15prepare_numbersPKcPPi
.type _Z15prepare_numbersPKcPPi, @function
_Z15prepare_numbersPKcPPi:
.LFB2077:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r15
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r12
movq %rsp, %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl (%rsp), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L29
movq %rax, %rbp
movl $0, %ebx
leaq .LC4(%rip), %r13
.L25:
leaq 4(%rsp), %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
js .L24
movl 4(%rsp), %eax
movl %eax, 0(%rbp)
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, (%rsp)
jg .L25
.L24:
movq %r12, %rdi
call fclose@PLT
movl (%rsp), %eax
cmpl %ebx, %eax
jne .L32
movq %r14, (%r15)
.L23:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L33
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $0, %ebx
jmp .L24
.L32:
movq %r14, %rdi
call free@PLT
movl $-1, %eax
jmp .L23
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z15prepare_numbersPKcPPi, .-_Z15prepare_numbersPKcPPi
.globl _Z23__device_stub__Z3mapPiiPii
.type _Z23__device_stub__Z3mapPiiPii, @function
_Z23__device_stub__Z3mapPiiPii:
.LFB2103:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3mapPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2103:
.size _Z23__device_stub__Z3mapPiiPii, .-_Z23__device_stub__Z3mapPiiPii
.globl _Z3mapPii
.type _Z3mapPii, @function
_Z3mapPii:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3mapPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _Z3mapPii, .-_Z3mapPii
.globl _Z28__device_stub__Z6reducePiS_iPiS_i
.type _Z28__device_stub__Z6reducePiS_iPiS_i, @function
_Z28__device_stub__Z6reducePiS_iPiS_i:
.LFB2105:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducePiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z28__device_stub__Z6reducePiS_iPiS_i, .-_Z28__device_stub__Z6reducePiS_iPiS_i
.globl _Z6reducePiS_i
.type _Z6reducePiS_i, @function
_Z6reducePiS_i:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducePiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _Z6reducePiS_i, .-_Z6reducePiS_i
.globl _Z9mapreduceiiPii
.type _Z9mapreduceiiPii, @function
_Z9mapreduceiiPii:
.LFB2074:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %r12d
movq %rdx, %r14
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edi, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %esi, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movslq %ecx, %rbp
salq $2, %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rbp
movslq %r12d, %r12
salq $2, %r12
movl 52(%rsp), %ecx
movl $0, %r9d
movq %r12, %r8
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L51:
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
movl %eax, %ebx
je .L52
leaq 24(%rsp), %r14
jmp .L54
.L58:
movl %r13d, %esi
movq 16(%rsp), %rdi
call _Z23__device_stub__Z3mapPiiPii
jmp .L51
.L53:
movq %rbp, %rdi
call cudaFree@PLT
movq 24(%rsp), %rbp
movl %ebx, %r13d
shrl %ebx
je .L52
.L54:
movl %ebx, %esi
salq $2, %rsi
movq %r14, %rdi
call cudaMalloc@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movq %r12, %r8
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L53
movl %r13d, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call _Z28__device_stub__Z6reducePiS_iPiS_i
jmp .L53
.L52:
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl 12(%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L59
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z9mapreduceiiPii, .-_Z9mapreduceiiPii
.section .rodata.str1.1
.LC5:
.string "hb:t:"
.LC6:
.string "mapreduce using host\n"
.LC7:
.string "mapreduce using CUDA\n"
.LC8:
.string "mapreduce result: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2078:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $512, %r14d
movl $32, %r13d
movl $0, %r15d
leaq .LC5(%rip), %r12
.L62:
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call getopt@PLT
cmpl $-1, %eax
je .L78
cmpl $104, %eax
je .L75
cmpl $116, %eax
je .L63
cmpl $98, %eax
jne .L64
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r13d
jmp .L62
.L63:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r14d
jmp .L62
.L64:
movl $0, %edi
call _Z5usagei
.L66:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L79
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
movl $1, %r15d
jmp .L62
.L78:
movl optind(%rip), %eax
leal 1(%rax), %edx
cmpl %ebx, %edx
jne .L68
cltq
movq 0(%rbp,%rax,8), %rdi
movq $0, (%rsp)
movq %rsp, %rsi
call _Z15prepare_numbersPKcPPi
movl %eax, %ebx
testl %eax, %eax
js .L80
movl %r13d, %eax
imull %r14d, %eax
cmpl %ebx, %eax
jle .L81
testl %r15d, %r15d
je .L72
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq (%rsp), %rdi
call _Z14mapreduce_hostPii
movl %eax, %edx
.L73:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call free@PLT
jmp .L66
.L68:
movl $0, %edi
call _Z5usagei
jmp .L66
.L80:
movq (%rsp), %rdi
call free@PLT
movl $1, %edi
call _Z5usagei
jmp .L66
.L81:
movq (%rsp), %rdi
call free@PLT
movl $2, %edi
call _Z5usagei
jmp .L66
.L72:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movq (%rsp), %rdx
movl %r14d, %esi
movl %r13d, %edi
call _Z9mapreduceiiPii
movl %eax, %edx
jmp .L73
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2078:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z6reducePiS_i"
.LC10:
.string "_Z3mapPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2108:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mapPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mapreduce.hip"
.globl _Z18__device_stub__mapPii # -- Begin function _Z18__device_stub__mapPii
.p2align 4, 0x90
.type _Z18__device_stub__mapPii,@function
_Z18__device_stub__mapPii: # @_Z18__device_stub__mapPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3mapPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__mapPii, .Lfunc_end0-_Z18__device_stub__mapPii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__reducePiS_i # -- Begin function _Z21__device_stub__reducePiS_i
.p2align 4, 0x90
.type _Z21__device_stub__reducePiS_i,@function
_Z21__device_stub__reducePiS_i: # @_Z21__device_stub__reducePiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__reducePiS_i, .Lfunc_end1-_Z21__device_stub__reducePiS_i
.cfi_endproc
# -- End function
.globl _Z9mapreduceiiPii # -- Begin function _Z9mapreduceiiPii
.p2align 4, 0x90
.type _Z9mapreduceiiPii,@function
_Z9mapreduceiiPii: # @_Z9mapreduceiiPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r13d
movq %rdx, %r15
movl %esi, %ebp
# kill: def $edi killed $edi def $rdi
movq %rdi, 128(%rsp) # 8-byte Spill
movl %edi, %ebx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %esi, %r14d
orq %rax, %r14
movslq %ecx, %r12
shlq $2, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %r12
movslq %ebp, %r15
shlq $2, %r15
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl %r13d, 24(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3mapPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 128(%rsp), %rcx # 8-byte Reload
leal 1(%rcx), %eax
cmpl $3, %eax
jae .LBB2_3
.LBB2_7: # %._crit_edge
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl 96(%rsp), %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_3: # %.lr.ph
.cfi_def_cfa_offset 192
movq %rcx, %rax
movl %eax, %ebp
shrl $31, %ebp
addl %eax, %ebp
sarl %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=1
movq %r12, %rdi
callq hipFree
movq 8(%rsp), %r12
movl %ebp, %eax
shrl %eax
movl %ebp, %r13d
cmpl $2, %ebp
movl %eax, %ebp
jb .LBB2_7
.LBB2_4: # =>This Inner Loop Header: Depth=1
movl %ebp, %esi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
movq 8(%rsp), %rax
movq %r12, 80(%rsp)
movq %rax, 72(%rsp)
movl %r13d, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 92(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6reducePiS_i, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_6
.Lfunc_end2:
.size _Z9mapreduceiiPii, .Lfunc_end2-_Z9mapreduceiiPii
.cfi_endproc
# -- End function
.globl _Z14mapreduce_hostPii # -- Begin function _Z14mapreduce_hostPii
.p2align 4, 0x90
.type _Z14mapreduce_hostPii,@function
_Z14mapreduce_hostPii: # @_Z14mapreduce_hostPii
.cfi_startproc
# %bb.0:
movl %esi, %ecx
testl %esi, %esi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%rax,4), %edx
imull %edx, %edx
movl %edx, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rcx
jne .LBB3_2
.LBB3_3: # %.preheader
testl %esi, %esi
jle .LBB3_4
# %bb.6: # %.lr.ph21.preheader
xorl %edx, %edx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_7: # %.lr.ph21
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rdx,4), %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_7
# %bb.5: # %._crit_edge
retq
.LBB3_4:
xorl %eax, %eax
retq
.Lfunc_end3:
.size _Z14mapreduce_hostPii, .Lfunc_end3-_Z14mapreduce_hostPii
.cfi_endproc
# -- End function
.globl _Z5usagei # -- Begin function _Z5usagei
.p2align 4, 0x90
.type _Z5usagei,@function
_Z5usagei: # @_Z5usagei
.cfi_startproc
# %bb.0:
cmpl $2, %edi
movl $.Lstr, %eax
movl $.Lstr.2, %ecx
cmoveq %rax, %rcx
cmpl $1, %edi
movl $.Lstr.1, %edi
cmovneq %rcx, %rdi
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z5usagei, .Lfunc_end4-_Z5usagei
.cfi_endproc
# -- End function
.globl _Z15prepare_numbersPKcPPi # -- Begin function _Z15prepare_numbersPKcPPi
.p2align 4, 0x90
.type _Z15prepare_numbersPKcPPi,@function
_Z15prepare_numbersPKcPPi: # @_Z15prepare_numbersPKcPPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
xorl %r13d, %r13d
leaq 8(%rsp), %rdx
movl $.L.str.4, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq 8(%rsp), %r12
leaq (,%r12,4), %rdi
callq malloc
movq %rax, %r15
testq %r12, %r12
jle .LBB5_4
# %bb.1: # %.lr.ph.preheader
leaq 12(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
js .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl 12(%rsp), %eax
movl %eax, (%r15,%r13,4)
incq %r13
movslq 8(%rsp), %rax
cmpq %rax, %r13
jl .LBB5_2
.LBB5_4: # %._crit_edge
movq %r14, %rdi
callq fclose
movl 8(%rsp), %eax
cmpl %r13d, %eax
jne .LBB5_5
# %bb.6:
movq %r15, (%rbx)
jmp .LBB5_7
.LBB5_5:
movq %r15, %rdi
callq free
movl $-1, %eax
.LBB5_7:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z15prepare_numbersPKcPPi, .Lfunc_end5-_Z15prepare_numbersPKcPPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %ebp
xorl %r12d, %r12d
movl $512, %ebx # imm = 0x200
movl $32, %r14d
.LBB6_1: # %.outer36
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
movl %r12d, %ecx
.p2align 4, 0x90
.LBB6_2: # Parent Loop BB6_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %r12d
movl $.L.str.5, %edx
movl %ebp, %edi
movq %r15, %rsi
callq getopt
movl $1, %ecx
cmpl $104, %eax
je .LBB6_2
# %bb.3: # in Loop: Header=BB6_1 Depth=1
cmpl $-1, %eax
je .LBB6_8
# %bb.4: # in Loop: Header=BB6_1 Depth=1
cmpl $116, %eax
je .LBB6_7
# %bb.5: # in Loop: Header=BB6_1 Depth=1
cmpl $98, %eax
jne .LBB6_18
# %bb.6: # in Loop: Header=BB6_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_7: # in Loop: Header=BB6_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB6_1
.LBB6_8:
movslq optind(%rip), %rax
leal 1(%rax), %ecx
cmpl %ebp, %ecx
jne .LBB6_18
# %bb.9:
movq (%r15,%rax,8), %rdi
movq $0, 8(%rsp)
leaq 8(%rsp), %rsi
callq _Z15prepare_numbersPKcPPi
testl %eax, %eax
js .LBB6_21
# %bb.10:
movl %ebx, %ecx
imull %r14d, %ecx
cmpl %ecx, %eax
jge .LBB6_22
# %bb.11:
movl %eax, %ebp
testl %r12d, %r12d
je .LBB6_23
# %bb.12:
movl $.Lstr.4, %edi
callq puts@PLT
testl %ebp, %ebp
je .LBB6_25
# %bb.13: # %.lr.ph.preheader.i
movq 8(%rsp), %rax
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_14: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%rax,%rdx,4), %esi
imull %esi, %esi
movl %esi, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB6_14
# %bb.15: # %.preheader.i
testl %ebp, %ebp
je .LBB6_25
# %bb.16: # %.lr.ph21.preheader.i
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_17: # %.lr.ph21.i
# =>This Inner Loop Header: Depth=1
addl (%rax,%rdx,4), %esi
incq %rdx
cmpq %rdx, %rcx
jne .LBB6_17
jmp .LBB6_26
.LBB6_18:
movl $.Lstr.2, %edi
.LBB6_19:
callq puts@PLT
.LBB6_20:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_21:
.cfi_def_cfa_offset 64
movq 8(%rsp), %rdi
callq free
movl $.Lstr.1, %edi
jmp .LBB6_19
.LBB6_22:
movq 8(%rsp), %rdi
callq free
movl $.Lstr, %edi
jmp .LBB6_19
.LBB6_25:
xorl %esi, %esi
jmp .LBB6_26
.LBB6_23:
movl $.Lstr.3, %edi
callq puts@PLT
movq 8(%rsp), %rdx
movl %r14d, %edi
movl %ebx, %esi
movl %ebp, %ecx
callq _Z9mapreduceiiPii
movl %eax, %esi
.LBB6_26: # %_Z14mapreduce_hostPii.exit
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq free
jmp .LBB6_20
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mapPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mapPii,@object # @_Z3mapPii
.section .rodata,"a",@progbits
.globl _Z3mapPii
.p2align 3, 0x0
_Z3mapPii:
.quad _Z18__device_stub__mapPii
.size _Z3mapPii, 8
.type _Z6reducePiS_i,@object # @_Z6reducePiS_i
.globl _Z6reducePiS_i
.p2align 3, 0x0
_Z6reducePiS_i:
.quad _Z21__device_stub__reducePiS_i
.size _Z6reducePiS_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hb:t:"
.size .L.str.5, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "mapreduce result: %d\n"
.size .L.str.8, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mapPii"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6reducePiS_i"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "mapreduce requires numbers <= threads*blocks"
.size .Lstr, 45
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "mapreduce input format:\nnum count\n1\n...\nn n"
.size .Lstr.1, 44
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "usage: mapreduce [-h|-b blocks|-t threads] <filename>"
.size .Lstr.2, 54
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "mapreduce using CUDA"
.size .Lstr.3, 21
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "mapreduce using host"
.size .Lstr.4, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mapPii
.addrsig_sym _Z21__device_stub__reducePiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mapPii
.addrsig_sym _Z6reducePiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void conv3(int *inp, int *out)
{
int i = 0;
if (inp[0] == out[0]) {
while ( i < 10) {
int tmp = inp[i];
if (tmp == i)
break;
__syncthreads();
out[i] = tmp;
i++;
}
__syncthreads();
out[i] = 31;
}
} | code for sm_80
Function : _Z5conv3PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fc600078e00ff */
/*0060*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.NE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x004fda0003f05270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fd400078e00ff */
/*00d0*/ @!P0 BRA 0x460 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0100*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x004fda0003f05270 */
/*0130*/ @!P0 BRA 0x460 ; /* 0x0000032000008947 */
/* 0x000fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0150*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x0001e8000c101904 */
/*0160*/ LDG.E R7, [R4.64+0x8] ; /* 0x0000080404077981 */
/* 0x000ea2000c1e1900 */
/*0170*/ HFMA2.MMA R0, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff007435 */
/* 0x000fe200000001ff */
/*0180*/ ISETP.NE.AND P0, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x004fda0003f05270 */
/*0190*/ @!P0 BRA 0x460 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*01b0*/ STG.E [R2.64+0x8], R7 ; /* 0x0000080702007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R9, [R4.64+0xc] ; /* 0x00000c0404097981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3 ; /* 0x00000003ff007424 */
/* 0x000fe200078e00ff */
/*01e0*/ ISETP.NE.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x004fda0003f05270 */
/*01f0*/ @!P0 BRA 0x460 ; /* 0x0000026000008947 */
/* 0x000fea0003800000 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0210*/ STG.E [R2.64+0xc], R9 ; /* 0x00000c0902007986 */
/* 0x0001e8000c101904 */
/*0220*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100404077981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0240*/ ISETP.NE.AND P0, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x004fda0003f05270 */
/*0250*/ @!P0 BRA 0x460 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0270*/ STG.E [R2.64+0x10], R7 ; /* 0x0000100702007986 */
/* 0x0001e8000c101904 */
/*0280*/ LDG.E R9, [R4.64+0x14] ; /* 0x0000140404097981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.MOV.U32 R0, RZ, RZ, 0x5 ; /* 0x00000005ff007424 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.NE.AND P0, PT, R9, 0x5, PT ; /* 0x000000050900780c */
/* 0x004fda0003f05270 */
/*02b0*/ @!P0 BRA 0x460 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*02d0*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R7, [R4.64+0x18] ; /* 0x0000180404077981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ MOV R0, 0x6 ; /* 0x0000000600007802 */
/* 0x000fc40000000f00 */
/*0300*/ ISETP.NE.AND P0, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x004fda0003f05270 */
/*0310*/ @!P0 BRA 0x460 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0330*/ STG.E [R2.64+0x18], R7 ; /* 0x0000180702007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R9, [R4.64+0x1c] ; /* 0x00001c0404097981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.MOV.U32 R0, RZ, RZ, 0x7 ; /* 0x00000007ff007424 */
/* 0x000fe200078e00ff */
/*0360*/ ISETP.NE.AND P0, PT, R9, 0x7, PT ; /* 0x000000070900780c */
/* 0x004fda0003f05270 */
/*0370*/ @!P0 BRA 0x460 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0390*/ STG.E [R2.64+0x1c], R9 ; /* 0x00001c0902007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R7, [R4.64+0x20] ; /* 0x0000200404077981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; /* 0x00000008ff007424 */
/* 0x000fe200078e00ff */
/*03c0*/ ISETP.NE.AND P0, PT, R7, 0x8, PT ; /* 0x000000080700780c */
/* 0x004fda0003f05270 */
/*03d0*/ @!P0 BRA 0x460 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*03f0*/ STG.E [R2.64+0x20], R7 ; /* 0x0000200702007986 */
/* 0x0001e8000c101904 */
/*0400*/ LDG.E R5, [R4.64+0x24] ; /* 0x0000240404057981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.MOV.U32 R0, RZ, RZ, 0x9 ; /* 0x00000009ff007424 */
/* 0x000fe200078e00ff */
/*0420*/ ISETP.NE.AND P0, PT, R5, 0x9, PT ; /* 0x000000090500780c */
/* 0x004fda0003f05270 */
/*0430*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fe20000010000 */
/*0440*/ @P0 MOV R0, 0xa ; /* 0x0000000a00000802 */
/* 0x000fca0000000f00 */
/*0450*/ @P0 STG.E [R2.64+0x24], R5 ; /* 0x0000240502000986 */
/* 0x0001e4000c101904 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fe20000010000 */
/*0470*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe200078010ff */
/*0480*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1f ; /* 0x0000001fff057424 */
/* 0x000fc600078e00ff */
/*0490*/ LEA.HI.X R3, R0, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f140b */
/*04a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void conv3(int *inp, int *out)
{
int i = 0;
if (inp[0] == out[0]) {
while ( i < 10) {
int tmp = inp[i];
if (tmp == i)
break;
__syncthreads();
out[i] = tmp;
i++;
}
__syncthreads();
out[i] = 31;
}
} | .file "tmpxft_00086be8_00000000-6_conv3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5conv3PiS_PiS_
.type _Z26__device_stub__Z5conv3PiS_PiS_, @function
_Z26__device_stub__Z5conv3PiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5conv3PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z5conv3PiS_PiS_, .-_Z26__device_stub__Z5conv3PiS_PiS_
.globl _Z5conv3PiS_
.type _Z5conv3PiS_, @function
_Z5conv3PiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5conv3PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5conv3PiS_, .-_Z5conv3PiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5conv3PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5conv3PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void conv3(int *inp, int *out)
{
int i = 0;
if (inp[0] == out[0]) {
while ( i < 10) {
int tmp = inp[i];
if (tmp == i)
break;
__syncthreads();
out[i] = tmp;
i++;
}
__syncthreads();
out[i] = 31;
}
} | #include <hip/hip_runtime.h>
__global__ void conv3(int *inp, int *out)
{
int i = 0;
if (inp[0] == out[0]) {
while ( i < 10) {
int tmp = inp[i];
if (tmp == i)
break;
__syncthreads();
out[i] = tmp;
i++;
}
__syncthreads();
out[i] = 31;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void conv3(int *inp, int *out)
{
int i = 0;
if (inp[0] == out[0]) {
while ( i < 10) {
int tmp = inp[i];
if (tmp == i)
break;
__syncthreads();
out[i] = tmp;
i++;
}
__syncthreads();
out[i] = 31;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5conv3PiS_
.globl _Z5conv3PiS_
.p2align 8
.type _Z5conv3PiS_,@function
_Z5conv3PiS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_load_b32 s5, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s4, s5
s_cbranch_scc1 .LBB0_7
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_6
.LBB0_3:
s_cmp_gt_i32 s4, 9
s_mov_b32 s5, -1
s_cbranch_scc1 .LBB0_2
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[4:5], 2
s_add_u32 s8, s0, s6
s_addc_u32 s9, s1, s7
global_load_b32 v1, v0, s[8:9]
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s5, s4, v1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_2
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_add_i32 s4, s4, 1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[6:7]
s_branch .LBB0_2
.LBB0_6:
s_ashr_i32 s5, s4, 31
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 31
s_lshl_b64 s[0:1], s[4:5], 2
s_waitcnt_vscnt null, 0x0
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5conv3PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5conv3PiS_, .Lfunc_end0-_Z5conv3PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5conv3PiS_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z5conv3PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void conv3(int *inp, int *out)
{
int i = 0;
if (inp[0] == out[0]) {
while ( i < 10) {
int tmp = inp[i];
if (tmp == i)
break;
__syncthreads();
out[i] = tmp;
i++;
}
__syncthreads();
out[i] = 31;
}
} | .text
.file "conv3.hip"
.globl _Z20__device_stub__conv3PiS_ # -- Begin function _Z20__device_stub__conv3PiS_
.p2align 4, 0x90
.type _Z20__device_stub__conv3PiS_,@function
_Z20__device_stub__conv3PiS_: # @_Z20__device_stub__conv3PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5conv3PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__conv3PiS_, .Lfunc_end0-_Z20__device_stub__conv3PiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5conv3PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5conv3PiS_,@object # @_Z5conv3PiS_
.section .rodata,"a",@progbits
.globl _Z5conv3PiS_
.p2align 3, 0x0
_Z5conv3PiS_:
.quad _Z20__device_stub__conv3PiS_
.size _Z5conv3PiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5conv3PiS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__conv3PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5conv3PiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5conv3PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fc600078e00ff */
/*0060*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.NE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x004fda0003f05270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fd400078e00ff */
/*00d0*/ @!P0 BRA 0x460 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0100*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x004fda0003f05270 */
/*0130*/ @!P0 BRA 0x460 ; /* 0x0000032000008947 */
/* 0x000fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0150*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x0001e8000c101904 */
/*0160*/ LDG.E R7, [R4.64+0x8] ; /* 0x0000080404077981 */
/* 0x000ea2000c1e1900 */
/*0170*/ HFMA2.MMA R0, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff007435 */
/* 0x000fe200000001ff */
/*0180*/ ISETP.NE.AND P0, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x004fda0003f05270 */
/*0190*/ @!P0 BRA 0x460 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*01b0*/ STG.E [R2.64+0x8], R7 ; /* 0x0000080702007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R9, [R4.64+0xc] ; /* 0x00000c0404097981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3 ; /* 0x00000003ff007424 */
/* 0x000fe200078e00ff */
/*01e0*/ ISETP.NE.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x004fda0003f05270 */
/*01f0*/ @!P0 BRA 0x460 ; /* 0x0000026000008947 */
/* 0x000fea0003800000 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0210*/ STG.E [R2.64+0xc], R9 ; /* 0x00000c0902007986 */
/* 0x0001e8000c101904 */
/*0220*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100404077981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0240*/ ISETP.NE.AND P0, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x004fda0003f05270 */
/*0250*/ @!P0 BRA 0x460 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0270*/ STG.E [R2.64+0x10], R7 ; /* 0x0000100702007986 */
/* 0x0001e8000c101904 */
/*0280*/ LDG.E R9, [R4.64+0x14] ; /* 0x0000140404097981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.MOV.U32 R0, RZ, RZ, 0x5 ; /* 0x00000005ff007424 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.NE.AND P0, PT, R9, 0x5, PT ; /* 0x000000050900780c */
/* 0x004fda0003f05270 */
/*02b0*/ @!P0 BRA 0x460 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*02d0*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R7, [R4.64+0x18] ; /* 0x0000180404077981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ MOV R0, 0x6 ; /* 0x0000000600007802 */
/* 0x000fc40000000f00 */
/*0300*/ ISETP.NE.AND P0, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x004fda0003f05270 */
/*0310*/ @!P0 BRA 0x460 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0330*/ STG.E [R2.64+0x18], R7 ; /* 0x0000180702007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R9, [R4.64+0x1c] ; /* 0x00001c0404097981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.MOV.U32 R0, RZ, RZ, 0x7 ; /* 0x00000007ff007424 */
/* 0x000fe200078e00ff */
/*0360*/ ISETP.NE.AND P0, PT, R9, 0x7, PT ; /* 0x000000070900780c */
/* 0x004fda0003f05270 */
/*0370*/ @!P0 BRA 0x460 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0390*/ STG.E [R2.64+0x1c], R9 ; /* 0x00001c0902007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R7, [R4.64+0x20] ; /* 0x0000200404077981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; /* 0x00000008ff007424 */
/* 0x000fe200078e00ff */
/*03c0*/ ISETP.NE.AND P0, PT, R7, 0x8, PT ; /* 0x000000080700780c */
/* 0x004fda0003f05270 */
/*03d0*/ @!P0 BRA 0x460 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*03f0*/ STG.E [R2.64+0x20], R7 ; /* 0x0000200702007986 */
/* 0x0001e8000c101904 */
/*0400*/ LDG.E R5, [R4.64+0x24] ; /* 0x0000240404057981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.MOV.U32 R0, RZ, RZ, 0x9 ; /* 0x00000009ff007424 */
/* 0x000fe200078e00ff */
/*0420*/ ISETP.NE.AND P0, PT, R5, 0x9, PT ; /* 0x000000090500780c */
/* 0x004fda0003f05270 */
/*0430*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fe20000010000 */
/*0440*/ @P0 MOV R0, 0xa ; /* 0x0000000a00000802 */
/* 0x000fca0000000f00 */
/*0450*/ @P0 STG.E [R2.64+0x24], R5 ; /* 0x0000240502000986 */
/* 0x0001e4000c101904 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fe20000010000 */
/*0470*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe200078010ff */
/*0480*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1f ; /* 0x0000001fff057424 */
/* 0x000fc600078e00ff */
/*0490*/ LEA.HI.X R3, R0, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f140b */
/*04a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5conv3PiS_
.globl _Z5conv3PiS_
.p2align 8
.type _Z5conv3PiS_,@function
_Z5conv3PiS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_load_b32 s5, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s4, s5
s_cbranch_scc1 .LBB0_7
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_6
.LBB0_3:
s_cmp_gt_i32 s4, 9
s_mov_b32 s5, -1
s_cbranch_scc1 .LBB0_2
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[4:5], 2
s_add_u32 s8, s0, s6
s_addc_u32 s9, s1, s7
global_load_b32 v1, v0, s[8:9]
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s5, s4, v1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_2
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_add_i32 s4, s4, 1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[6:7]
s_branch .LBB0_2
.LBB0_6:
s_ashr_i32 s5, s4, 31
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 31
s_lshl_b64 s[0:1], s[4:5], 2
s_waitcnt_vscnt null, 0x0
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5conv3PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5conv3PiS_, .Lfunc_end0-_Z5conv3PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5conv3PiS_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z5conv3PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00086be8_00000000-6_conv3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5conv3PiS_PiS_
.type _Z26__device_stub__Z5conv3PiS_PiS_, @function
_Z26__device_stub__Z5conv3PiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5conv3PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z5conv3PiS_PiS_, .-_Z26__device_stub__Z5conv3PiS_PiS_
.globl _Z5conv3PiS_
.type _Z5conv3PiS_, @function
_Z5conv3PiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5conv3PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5conv3PiS_, .-_Z5conv3PiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5conv3PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5conv3PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "conv3.hip"
.globl _Z20__device_stub__conv3PiS_ # -- Begin function _Z20__device_stub__conv3PiS_
.p2align 4, 0x90
.type _Z20__device_stub__conv3PiS_,@function
_Z20__device_stub__conv3PiS_: # @_Z20__device_stub__conv3PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5conv3PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__conv3PiS_, .Lfunc_end0-_Z20__device_stub__conv3PiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5conv3PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5conv3PiS_,@object # @_Z5conv3PiS_
.section .rodata,"a",@progbits
.globl _Z5conv3PiS_
.p2align 3, 0x0
_Z5conv3PiS_:
.quad _Z20__device_stub__conv3PiS_
.size _Z5conv3PiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5conv3PiS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__conv3PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5conv3PiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Title: prefixScan.cu
* Author: 陈志韬
* Student ID: SA12011089
*/
#include<stdio.h>
#include<stdlib.h>
#include<assert.h>
/*#include<c*/
#define NUM_BANKS 16
#define LOG_NUM_BANKS 4
#define CONFLICT_FREE_OFFSET(n) \
((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
#define DATA_SIZE 32
#define DEFAULT_BLOCK_SIZE 256
#define RAND_INT 50
//Only generate integers with value 0 or 1
#define MAX_INT_SIZE 2
typedef float calcType;
void randomInit(calcType *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = ((calcType)random() / RAND_MAX) * RAND_INT;
}
}
void randomInit(int *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = random()%MAX_INT_SIZE;
}
}
void printArray(calcType * array, int m)
{
int i = 0;
for(i = 0;i < m; i++)
{
printf("%f ", array[i]);
}
printf("\n");
}
//The size of out is larger than in by one, i.e the size of m is m+1
void cpuCalc(calcType *out, const calcType *in, int m)
{
int j = 0;
out[0] = 0;
for(j = 1;j < m;j++)
{
out[j] = out[j - 1] + in[j - 1];
}
}
__global__ void prescanEasy(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[];
int thid = threadIdx.x;
int pout = 0, pin = 1;
//Make sure the data has been transfomed into the kernel thread
/*g_odata[thid] = g_idata[thid];*/
temp[pout*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
//下面一行GPU Gems 3没有，是我在进行错误的测试的时候认为是错误点添加上的
//但是在修改73行代码之后的时候测试，不对结果产生影响。。
//temp[pin*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
__syncthreads();
/*for(int offset = 1; offset < n; offset *= 2)*/
for(int offset = 1; offset < n; offset *= 2)
{
pout = 1 - pout; //交换双缓冲区的索引
pin = 1 - pin;
if( thid >= offset)
{
//GPU Gems 3 的样例程序的代码如下：
//temp[pout*n+thid] += temp[pin*n+thid - offset];
temp[pout*n + thid] = temp[pin*n + thid] + temp[pin*n + thid -offset];
}
else
temp[pout*n + thid] = temp[pin*n + thid];
__syncthreads();
}
g_odata[thid] = temp[pout*n + thid];
}
__global__ void prescanBank(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
int d, ai, bi;
calcType t;
//Below is A
temp[2*thid] = g_idata[2*thid]; // load input into shared memory
temp[2*thid+1] = g_idata[2*thid+1];
//A end
for (d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
if (thid == 0) { temp[n - 1] = 0; } // clear the last element
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//D end
t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
g_odata[2*thid] = temp[2*thid]; // write results to device memory
g_odata[2*thid+1] = temp[2*thid+1];
//E end
}
__global__ void prescan(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
//Below is A
/*temp[2*thid] = g_idata[2*thid]; // load input into shared memory*/
/*temp[2*thid+1] = g_idata[2*thid+1];*/
int ai = thid;
int bi = thid + (n/2);
int bankOffsetA = CONFLICT_FREE_OFFSET(ai);
int bankOffsetB = CONFLICT_FREE_OFFSET(bi);
temp[ai + bankOffsetA] = g_idata[ai];
temp[bi + bankOffsetB] = g_idata[bi];
//A end
for (int d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
/*if (thid == 0) { temp[n - 1] = 0; } // clear the last element*/
if(thid == 0) { temp[n - 1 + CONFLICT_FREE_OFFSET(n -1)] = 0;}
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//D end
calcType t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
/*g_odata[2*thid] = temp[2*thid]; // write results to device memory*/
/*g_odata[2*thid+1] = temp[2*thid+1];*/
g_odata[ai] = temp[ai + bankOffsetA];
g_odata[bi] = temp[bi + bankOffsetB];
//E end
}
int main(int argc, char *argv[])
{
int data_bytes = DATA_SIZE * sizeof(calcType);
calcType *h_out = 0, *d_out = 0;
calcType *h_in = 0, *d_in = 0;
calcType *cpu = 0;
h_out = (calcType*)malloc(data_bytes);
h_in = (calcType*)malloc(data_bytes);
cpu = (calcType*)malloc(data_bytes);
cudaMalloc( (void**)&d_out, data_bytes);
cudaMalloc( (void**)&d_in, data_bytes);
if(0 == h_out || 0 == h_in || 0 == d_out || 0 == d_in)
{
printf("Couldn't allocate memory\n");
return 1;
}
randomInit(h_in, DATA_SIZE);
printArray(h_in, DATA_SIZE);
cudaMemcpy(d_in, h_in, data_bytes, cudaMemcpyHostToDevice);
cudaMemset(d_out, 0, data_bytes);
//Cpu Calc
cpuCalc(cpu, h_in, DATA_SIZE);
printArray(cpu, DATA_SIZE);
//开始进入GPU执行
dim3 grid, block;
float time;
block.x = DATA_SIZE;
/*grid.x = (DATA_SIZE + block.x - 1)/block.x;*/
grid.x = 1;
cudaEvent_t start, stop;
cudaEventCreate(&start),
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("PrescanEasy Time elapsed: %fms\n", time);
cudaEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("PrescanBank Time elapsed: %fms\n", time);
cudaEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Prescan Time elapsed: %fms\n", time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy( h_out, d_out, data_bytes, cudaMemcpyDeviceToHost );
printArray(h_out, DATA_SIZE);
free(h_in);
free(h_out);
free(cpu);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z7prescanPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0050*/ LEA.HI R2, R10, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c000a027a11 */
/* 0x000fc800078f08ff */
/*0060*/ SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff037819 */
/* 0x000fe20000011402 */
/*0070*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x001fca00078e0205 */
/*0080*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x0000a2000c1e1900 */
/*0090*/ IMAD.WIDE R6, R3, 0x4, R4 ; /* 0x0000000403067825 */
/* 0x000fcc00078e0204 */
/*00a0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ee2000c1e1900 */
/*00b0*/ IMAD.IADD R3, R3, 0x1, R0 ; /* 0x0000000103037824 */
/* 0x000fe200078e0200 */
/*00c0*/ IADD3 R9, R0, 0x10, RZ ; /* 0x0000001000097810 */
/* 0x000fc80007ffe0ff */
/*00d0*/ IADD3 R2, R3, 0x10, RZ ; /* 0x0000001003027810 */
/* 0x000fe40007ffe0ff */
/*00e0*/ SHF.R.S32.HI R9, RZ, R9, R0.reuse ; /* 0x00000009ff097219 */
/* 0x100fe40000011400 */
/*00f0*/ SHF.R.S32.HI R8, RZ, R2, R3 ; /* 0x00000002ff087219 */
/* 0x000fe40000011403 */
/*0100*/ LEA.HI.SX32 R2, R9, R0, 0x18 ; /* 0x0000000009027211 */
/* 0x000fe400078fc2ff */
/*0110*/ LEA.HI.SX32 R3, R8, R3, 0x18 ; /* 0x0000000308037211 */
/* 0x000fe400078fc2ff */
/*0120*/ ISETP.GE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe20003f06270 */
/*0130*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0140*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x001fe20000011400 */
/*0150*/ STS [R2.X4], R11 ; /* 0x0000000b02007388 */
/* 0x0041e80000004800 */
/*0160*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x0081ec0000004800 */
/*0170*/ @!P0 BRA 0x330 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0180*/ LEA R10, R0, 0x1, 0x1 ; /* 0x00000001000a7811 */
/* 0x000fe200078e08ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*01a0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fc80000000000 */
/*01b0*/ SHF.R.S32.HI R13, RZ, 0x1, R4 ; /* 0x00000001ff0d7819 */
/* 0x000fe20000011404 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.GT.AND P2, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fc40003f44270 */
/*01e0*/ ISETP.GE.AND P1, PT, R0, R13, PT ; /* 0x0000000d0000720c */
/* 0x000fc60003f26270 */
/*01f0*/ BSSY B0, 0x300 ; /* 0x0000010000007945 */
/* 0x000ff40003800000 */
/*0200*/ @P1 BRA 0x2f0 ; /* 0x000000e000001947 */
/* 0x001fea0003800000 */
/*0210*/ IMAD R4, R10, UR4, RZ ; /* 0x000000040a047c24 */
/* 0x000fca000f8e02ff */
/*0220*/ IADD3 R7, R4.reuse, UR4, RZ ; /* 0x0000000404077c10 */
/* 0x040fe4000fffe0ff */
/*0230*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x041fe40007ffe0ff */
/*0240*/ IADD3 R9, R4, 0xf, RZ ; /* 0x0000000f04097810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R8, R7.reuse, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x040fe40007ffe0ff */
/*0260*/ IADD3 R11, R7, 0xf, RZ ; /* 0x0000000f070b7810 */
/* 0x000fe40007ffe0ff */
/*0270*/ SHF.R.S32.HI R9, RZ, R9, R6 ; /* 0x00000009ff097219 */
/* 0x000fc40000011406 */
/*0280*/ SHF.R.S32.HI R8, RZ, R11, R8 ; /* 0x0000000bff087219 */
/* 0x000fe40000011408 */
/*0290*/ LEA.HI.SX32 R9, R9, R4, 0x18 ; /* 0x0000000409097211 */
/* 0x000fe400078fc2ff */
/*02a0*/ LEA.HI.SX32 R8, R8, R7, 0x18 ; /* 0x0000000708087211 */
/* 0x000fc800078fc2ff */
/*02b0*/ LDS R9, [R9.X4+-0x4] ; /* 0xfffffc0009097984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS R4, [R8.X4+-0x4] ; /* 0xfffffc0008047984 */
/* 0x000e240000004800 */
/*02d0*/ FADD R7, R4, R9 ; /* 0x0000000904077221 */
/* 0x001fca0000000000 */
/*02e0*/ STS [R8.X4+-0x4], R7 ; /* 0xfffffc0708007388 */
/* 0x0001e40000004800 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0310*/ IMAD.MOV.U32 R4, RZ, RZ, R13 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000d */
/*0320*/ @P2 BRA 0x1b0 ; /* 0xfffffe8000002947 */
/* 0x000fea000383ffff */
/*0330*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*0340*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x001fd800078e00ff */
/*0350*/ @!P1 IADD3 R4, R6.reuse, -0x1, RZ ; /* 0xffffffff06049810 */
/* 0x040fe40007ffe0ff */
/*0360*/ @!P1 IADD3 R7, R6.reuse, 0xf, RZ ; /* 0x0000000f06079810 */
/* 0x040fe40007ffe0ff */
/*0370*/ LEA.HI R6, R6, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0006067a11 */
/* 0x000fe400078f08ff */
/*0380*/ @!P1 SHF.R.S32.HI R4, RZ, R7, R4 ; /* 0x00000007ff049219 */
/* 0x000fe40000011404 */
/*0390*/ SHF.R.S32.HI R15, RZ, 0x1, R6 ; /* 0x00000001ff0f7819 */
/* 0x000fe40000011406 */
/*03a0*/ @!P1 LEA.HI.SX32 R4, R4, c[0x0][0x170], 0x18 ; /* 0x00005c0004049a11 */
/* 0x000fc400078fc2ff */
/*03b0*/ SHF.R.S32.HI R13, RZ, 0x1f, R15 ; /* 0x0000001fff0d7819 */
/* 0x000fc6000001140f */
/*03c0*/ @!P1 IMAD.SHL.U32 R4, R4, 0x4, RZ ; /* 0x0000000404049824 */
/* 0x000fca00078e00ff */
/*03d0*/ @!P1 STS [R4+-0x4], RZ ; /* 0xfffffcff04009388 */
/* 0x0001e20000000800 */
/*03e0*/ @!P0 BRA 0x5a0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*03f0*/ LEA R12, R0, 0x1, 0x1 ; /* 0x00000001000c7811 */
/* 0x000fe200078e08ff */
/*0400*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fc800078e00ff */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0420*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe20003f06270 */
/*0430*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0440*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011404 */
/*0450*/ BSSY B0, 0x590 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0460*/ ISETP.GE.AND P1, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fce0003f26270 */
/*0470*/ @P0 BRA 0x580 ; /* 0x0000010000000947 */
/* 0x001fea0003800000 */
/*0480*/ IMAD R4, R12, UR4, RZ ; /* 0x000000040c047c24 */
/* 0x001fca000f8e02ff */
/*0490*/ IADD3 R6, R4, UR4, RZ ; /* 0x0000000404067c10 */
/* 0x000fc8000fffe0ff */
/*04a0*/ IADD3 R8, R6.reuse, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x040fe40007ffe0ff */
/*04b0*/ IADD3 R9, R6, 0xf, RZ ; /* 0x0000000f06097810 */
/* 0x000fc80007ffe0ff */
/*04c0*/ SHF.R.S32.HI R9, RZ, R9, R8 ; /* 0x00000009ff097219 */
/* 0x000fc80000011408 */
/*04d0*/ LEA.HI.SX32 R8, R9, R6, 0x18 ; /* 0x0000000609087211 */
/* 0x000fe400078fc2ff */
/*04e0*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe40007ffe0ff */
/*04f0*/ IADD3 R9, R4, 0xf, RZ ; /* 0x0000000f04097810 */
/* 0x000fe20007ffe0ff */
/*0500*/ LDS R10, [R8.X4+-0x4] ; /* 0xfffffc00080a7984 */
/* 0x000e260000004800 */
/*0510*/ SHF.R.S32.HI R9, RZ, R9, R6 ; /* 0x00000009ff097219 */
/* 0x000fc80000011406 */
/*0520*/ LEA.HI.SX32 R9, R9, R4, 0x18 ; /* 0x0000000409097211 */
/* 0x000fca00078fc2ff */
/*0530*/ LDS R4, [R9.X4+-0x4] ; /* 0xfffffc0009047984 */
/* 0x000fe80000004800 */
/*0540*/ STS [R9.X4+-0x4], R10 ; /* 0xfffffc0a09007388 */
/* 0x001fe80000004800 */
/*0550*/ LDS R11, [R8.X4+-0x4] ; /* 0xfffffc00080b7984 */
/* 0x000e240000004800 */
/*0560*/ FADD R11, R4, R11 ; /* 0x0000000b040b7221 */
/* 0x001fca0000000000 */
/*0570*/ STS [R8.X4+-0x4], R11 ; /* 0xfffffc0b08007388 */
/* 0x0001e40000004800 */
/*0580*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0590*/ @!P1 BRA 0x410 ; /* 0xfffffe7000009947 */
/* 0x000fea000383ffff */
/*05a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05b0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x001fc800078010ff */
/*05c0*/ LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fe400000f1405 */
/*05d0*/ LEA R6, P0, R15, R4, 0x2 ; /* 0x000000040f067211 */
/* 0x000fc800078010ff */
/*05e0*/ LEA.HI.X R7, R15, R5, R13, 0x2, P0 ; /* 0x000000050f077211 */
/* 0x000fe200000f140d */
/*05f0*/ LDS R9, [R2.X4] ; /* 0x0000000002097984 */
/* 0x000e280000004800 */
/*0600*/ LDS R3, [R3.X4] ; /* 0x0000000003037984 */
/* 0x000e680000004800 */
/*0610*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe8000c101906 */
/*0620*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x002fe2000c101906 */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ BRA 0x640; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11prescanBankPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.SHL.U32 R0, R9, 0x2, RZ ; /* 0x0000000209007824 */
/* 0x001fc800078e00ff */
/*0050*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0060*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*00b0*/ ISETP.GE.AND P1, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe40003f26270 */
/*00c0*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fd20007ffe0ff */
/*00d0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff088624 */
/* 0x000fca00078e00ff */
/*00e0*/ @!P0 LEA R8, R8, 0xfffffffc, 0x2 ; /* 0xfffffffc08088811 */
/* 0x000fe200078e10ff */
/*00f0*/ STS.64 [R9.X8], R6 ; /* 0x0000000609007388 */
/* 0x0041e20000008a00 */
/*0100*/ @!P1 BRA 0x210 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0110*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fe200000001ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fca00078e00ff */
/*0130*/ SHF.R.S32.HI R10, RZ, 0x1, R2 ; /* 0x00000001ff0a7819 */
/* 0x000fe20000011402 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0150*/ ISETP.GE.AND P2, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f46270 */
/*0160*/ @!P2 IMAD R3, R4, R5, RZ ; /* 0x000000050403a224 */
/* 0x000fc800078e02ff */
/*0170*/ @!P2 IMAD.SHL.U32 R6, R3, 0x4, RZ ; /* 0x000000040306a824 */
/* 0x001fe400078e00ff */
/*0180*/ @!P2 LDS R3, [R3.X4+-0x4] ; /* 0xfffffc000303a984 */
/* 0x000fe60000004800 */
/*0190*/ @!P2 LEA R7, R5.reuse, R6, 0x2 ; /* 0x000000060507a211 */
/* 0x040fe200078e10ff */
/*01a0*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fc800078e00ff */
/*01b0*/ @!P2 LDS R6, [R7+-0x4] ; /* 0xfffffc000706a984 */
/* 0x000e240000000800 */
/*01c0*/ @!P2 FADD R6, R6, R3 ; /* 0x000000030606a221 */
/* 0x001fca0000000000 */
/*01d0*/ @!P2 STS [R7+-0x4], R6 ; /* 0xfffffc060700a388 */
/* 0x0001e20000000800 */
/*01e0*/ ISETP.GT.AND P2, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f44270 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fd800078e000a */
/*0200*/ @P2 BRA 0x130 ; /* 0xffffff2000002947 */
/* 0x001fea000383ffff */
/*0210*/ @!P0 STS [R8], RZ ; /* 0x000000ff08008388 */
/* 0x0003e20000000800 */
/*0220*/ SHF.R.S32.HI R13, RZ, 0x1f, R0 ; /* 0x0000001fff0d7819 */
/* 0x000fe20000011400 */
/*0230*/ @!P1 BRA 0x370 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0240*/ MOV R2, 0x1 ; /* 0x0000000100027802 */
/* 0x000fc60000000f00 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.GE.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fe20003f06270 */
/*0270*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x000fe200078e00ff */
/*0280*/ SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fc60000011405 */
/*0290*/ BSSY B0, 0x360 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*02a0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fce0003f26270 */
/*02b0*/ @P0 BRA 0x350 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*02c0*/ IMAD R3, R4, R5, RZ ; /* 0x0000000504037224 */
/* 0x000fc800078e02ff */
/*02d0*/ IMAD.SHL.U32 R6, R3, 0x4, RZ ; /* 0x0000000403067824 */
/* 0x001fca00078e00ff */
/*02e0*/ LEA R11, R5, R6, 0x2 ; /* 0x00000006050b7211 */
/* 0x000fe400078e10ff */
/*02f0*/ LDS R6, [R3.X4+-0x4] ; /* 0xfffffc0003067984 */
/* 0x000fe80000004800 */
/*0300*/ LDS R8, [R11+-0x4] ; /* 0xfffffc000b087984 */
/* 0x002e280000000800 */
/*0310*/ STS [R3.X4+-0x4], R8 ; /* 0xfffffc0803007388 */
/* 0x001fe80000004800 */
/*0320*/ LDS R7, [R11+-0x4] ; /* 0xfffffc000b077984 */
/* 0x000e240000000800 */
/*0330*/ FADD R6, R6, R7 ; /* 0x0000000706067221 */
/* 0x001fca0000000000 */
/*0340*/ STS [R11+-0x4], R6 ; /* 0xfffffc060b007388 */
/* 0x0001e40000000800 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ @!P1 BRA 0x250 ; /* 0xfffffee000009947 */
/* 0x000fea000383ffff */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*0390*/ LEA.HI.X R3, R0, c[0x0][0x164], R13, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fe200000f140d */
/*03a0*/ LDS.64 R4, [R9.X8] ; /* 0x0000000009047984 */
/* 0x000ea80000008a00 */
/*03b0*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x004fe8000c101904 */
/*03c0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101904 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11prescanEasyPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x001fda0003f06270 */
/*0050*/ @P0 IADD3 R2, R9, -0x1, RZ ; /* 0xffffffff09020810 */
/* 0x000fe20007ffe0ff */
/*0060*/ @P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff030424 */
/* 0x000fc800078e00ff */
/*0070*/ @P0 IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002020625 */
/* 0x000fca00078e0203 */
/*0080*/ @P0 LDG.E R0, [R2.64] ; /* 0x0000000402000981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fc800000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD.SHL.U32 R4, R9, 0x4, RZ ; /* 0x0000000409047824 */
/* 0x000fe200078e00ff */
/*00d0*/ STS [R9.X4], R0 ; /* 0x0000000009007388 */
/* 0x0041e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fee0000010000 */
/*00f0*/ @!P0 BRA 0x230 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0100*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x001fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R10, 0x1 ; /* 0x00000001000a7802 */
/* 0x000fc80000000f00 */
/*0130*/ ISETP.GE.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f06270 */
/*0140*/ IADD3 R10, -R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fc40007ffe1ff */
/*0150*/ IADD3 R5, -R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc60007ffe1ff */
/*0160*/ IMAD R3, R10, c[0x0][0x170], RZ ; /* 0x00005c000a037a24 */
/* 0x000fe400078e02ff */
/*0170*/ IMAD R7, R5, c[0x0][0x170], RZ ; /* 0x00005c0005077a24 */
/* 0x000fe400078e02ff */
/*0180*/ IMAD R2, R3, 0x4, R4 ; /* 0x0000000403027824 */
/* 0x000fe400078e0204 */
/*0190*/ @P0 IADD3 R6, -R0.reuse, R3, R9 ; /* 0x0000000300060210 */
/* 0x040fe20007ffe109 */
/*01a0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe200078e00ff */
/*01b0*/ LEA R8, R7, R4, 0x2 ; /* 0x0000000407087211 */
/* 0x000fe200078e10ff */
/*01c0*/ LDS R3, [R2] ; /* 0x0000000002037984 */
/* 0x000fe80000000800 */
/*01d0*/ @P0 LDS R6, [R6.X4] ; /* 0x0000000006060984 */
/* 0x000e240000004800 */
/*01e0*/ @P0 FADD R3, R3, R6 ; /* 0x0000000603030221 */
/* 0x001fe20000000000 */
/*01f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06270 */
/*0200*/ STS [R8], R3 ; /* 0x0000000308007388 */
/* 0x0001e80000000800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0220*/ @!P0 BRA 0x130 ; /* 0xffffff0000008947 */
/* 0x001fea000383ffff */
/*0230*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x001fe400078e02ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0250*/ LEA R5, R5, R4, 0x2 ; /* 0x0000000405057211 */
/* 0x000fe200078e10ff */
/*0260*/ IMAD.WIDE R2, R9, R2, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x000fca00078e0202 */
/*0270*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e280000000800 */
/*0280*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Title: prefixScan.cu
* Author: 陈志韬
* Student ID: SA12011089
*/
#include<stdio.h>
#include<stdlib.h>
#include<assert.h>
/*#include<c*/
#define NUM_BANKS 16
#define LOG_NUM_BANKS 4
#define CONFLICT_FREE_OFFSET(n) \
((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
#define DATA_SIZE 32
#define DEFAULT_BLOCK_SIZE 256
#define RAND_INT 50
//Only generate integers with value 0 or 1
#define MAX_INT_SIZE 2
typedef float calcType;
void randomInit(calcType *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = ((calcType)random() / RAND_MAX) * RAND_INT;
}
}
void randomInit(int *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = random()%MAX_INT_SIZE;
}
}
void printArray(calcType * array, int m)
{
int i = 0;
for(i = 0;i < m; i++)
{
printf("%f ", array[i]);
}
printf("\n");
}
//The size of out is larger than in by one, i.e the size of m is m+1
void cpuCalc(calcType *out, const calcType *in, int m)
{
int j = 0;
out[0] = 0;
for(j = 1;j < m;j++)
{
out[j] = out[j - 1] + in[j - 1];
}
}
__global__ void prescanEasy(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[];
int thid = threadIdx.x;
int pout = 0, pin = 1;
//Make sure the data has been transfomed into the kernel thread
/*g_odata[thid] = g_idata[thid];*/
temp[pout*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
//下面一行GPU Gems 3没有，是我在进行错误的测试的时候认为是错误点添加上的
//但是在修改73行代码之后的时候测试，不对结果产生影响。。
//temp[pin*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
__syncthreads();
/*for(int offset = 1; offset < n; offset *= 2)*/
for(int offset = 1; offset < n; offset *= 2)
{
pout = 1 - pout; //交换双缓冲区的索引
pin = 1 - pin;
if( thid >= offset)
{
//GPU Gems 3 的样例程序的代码如下：
//temp[pout*n+thid] += temp[pin*n+thid - offset];
temp[pout*n + thid] = temp[pin*n + thid] + temp[pin*n + thid -offset];
}
else
temp[pout*n + thid] = temp[pin*n + thid];
__syncthreads();
}
g_odata[thid] = temp[pout*n + thid];
}
__global__ void prescanBank(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
int d, ai, bi;
calcType t;
//Below is A
temp[2*thid] = g_idata[2*thid]; // load input into shared memory
temp[2*thid+1] = g_idata[2*thid+1];
//A end
for (d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
if (thid == 0) { temp[n - 1] = 0; } // clear the last element
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//D end
t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
g_odata[2*thid] = temp[2*thid]; // write results to device memory
g_odata[2*thid+1] = temp[2*thid+1];
//E end
}
__global__ void prescan(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
//Below is A
/*temp[2*thid] = g_idata[2*thid]; // load input into shared memory*/
/*temp[2*thid+1] = g_idata[2*thid+1];*/
int ai = thid;
int bi = thid + (n/2);
int bankOffsetA = CONFLICT_FREE_OFFSET(ai);
int bankOffsetB = CONFLICT_FREE_OFFSET(bi);
temp[ai + bankOffsetA] = g_idata[ai];
temp[bi + bankOffsetB] = g_idata[bi];
//A end
for (int d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
/*if (thid == 0) { temp[n - 1] = 0; } // clear the last element*/
if(thid == 0) { temp[n - 1 + CONFLICT_FREE_OFFSET(n -1)] = 0;}
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//D end
calcType t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
/*g_odata[2*thid] = temp[2*thid]; // write results to device memory*/
/*g_odata[2*thid+1] = temp[2*thid+1];*/
g_odata[ai] = temp[ai + bankOffsetA];
g_odata[bi] = temp[bi + bankOffsetB];
//E end
}
int main(int argc, char *argv[])
{
int data_bytes = DATA_SIZE * sizeof(calcType);
calcType *h_out = 0, *d_out = 0;
calcType *h_in = 0, *d_in = 0;
calcType *cpu = 0;
h_out = (calcType*)malloc(data_bytes);
h_in = (calcType*)malloc(data_bytes);
cpu = (calcType*)malloc(data_bytes);
cudaMalloc( (void**)&d_out, data_bytes);
cudaMalloc( (void**)&d_in, data_bytes);
if(0 == h_out || 0 == h_in || 0 == d_out || 0 == d_in)
{
printf("Couldn't allocate memory\n");
return 1;
}
randomInit(h_in, DATA_SIZE);
printArray(h_in, DATA_SIZE);
cudaMemcpy(d_in, h_in, data_bytes, cudaMemcpyHostToDevice);
cudaMemset(d_out, 0, data_bytes);
//Cpu Calc
cpuCalc(cpu, h_in, DATA_SIZE);
printArray(cpu, DATA_SIZE);
//开始进入GPU执行
dim3 grid, block;
float time;
block.x = DATA_SIZE;
/*grid.x = (DATA_SIZE + block.x - 1)/block.x;*/
grid.x = 1;
cudaEvent_t start, stop;
cudaEventCreate(&start),
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("PrescanEasy Time elapsed: %fms\n", time);
cudaEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("PrescanBank Time elapsed: %fms\n", time);
cudaEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Prescan Time elapsed: %fms\n", time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy( h_out, d_out, data_bytes, cudaMemcpyDeviceToHost );
printArray(h_out, DATA_SIZE);
free(h_in);
free(h_out);
free(cpu);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | .file "tmpxft_000116c0_00000000-6_prefixSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call random@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.globl _Z10randomInitPii
.type _Z10randomInitPii, @function
_Z10randomInitPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L13:
call random@PLT
movq %rax, %rdx
shrq $63, %rdx
addq %rdx, %rax
andl $1, %eax
subq %rdx, %rax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z10randomInitPii, .-_Z10randomInitPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.text
.globl _Z10printArrayPfi
.type _Z10printArrayPfi, @function
_Z10printArrayPfi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L20
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC2(%rip), %rbp
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L21
.L20:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10printArrayPfi, .-_Z10printArrayPfi
.globl _Z7cpuCalcPfPKfi
.type _Z7cpuCalcPfPKfi, @function
_Z7cpuCalcPfPKfi:
.LFB2060:
.cfi_startproc
endbr64
movl $0x00000000, (%rdi)
cmpl $1, %edx
jle .L24
leal -1(%rdx), %edx
movl $0, %eax
.L26:
movss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, 4(%rdi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L26
.L24:
ret
.cfi_endproc
.LFE2060:
.size _Z7cpuCalcPfPKfi, .-_Z7cpuCalcPfPKfi
.globl _Z34__device_stub__Z11prescanEasyPfS_iPfS_i
.type _Z34__device_stub__Z11prescanEasyPfS_iPfS_i, @function
_Z34__device_stub__Z11prescanEasyPfS_iPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11prescanEasyPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z34__device_stub__Z11prescanEasyPfS_iPfS_i, .-_Z34__device_stub__Z11prescanEasyPfS_iPfS_i
.globl _Z11prescanEasyPfS_i
.type _Z11prescanEasyPfS_i, @function
_Z11prescanEasyPfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11prescanEasyPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11prescanEasyPfS_i, .-_Z11prescanEasyPfS_i
.globl _Z34__device_stub__Z11prescanBankPfS_iPfS_i
.type _Z34__device_stub__Z11prescanBankPfS_iPfS_i, @function
_Z34__device_stub__Z11prescanBankPfS_iPfS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11prescanBankPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z34__device_stub__Z11prescanBankPfS_iPfS_i, .-_Z34__device_stub__Z11prescanBankPfS_iPfS_i
.globl _Z11prescanBankPfS_i
.type _Z11prescanBankPfS_i, @function
_Z11prescanBankPfS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11prescanBankPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z11prescanBankPfS_i, .-_Z11prescanBankPfS_i
.globl _Z29__device_stub__Z7prescanPfS_iPfS_i
.type _Z29__device_stub__Z7prescanPfS_iPfS_i, @function
_Z29__device_stub__Z7prescanPfS_iPfS_i:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7prescanPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z29__device_stub__Z7prescanPfS_iPfS_i, .-_Z29__device_stub__Z7prescanPfS_iPfS_i
.globl _Z7prescanPfS_i
.type _Z7prescanPfS_i, @function
_Z7prescanPfS_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7prescanPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z7prescanPfS_i, .-_Z7prescanPfS_i
.section .rodata.str1.1
.LC5:
.string "Couldn't allocate memory\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "PrescanEasy Time elapsed: %fms\n"
.align 8
.LC7:
.string "PrescanBank Time elapsed: %fms\n"
.section .rodata.str1.1
.LC8:
.string "Prescan Time elapsed: %fms\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $128, %edi
call malloc@PLT
movq %rax, %rbx
movl $128, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
testq %rbp, %rbp
je .L53
testq %rbx, %rbx
je .L53
cmpq $0, 16(%rsp)
je .L53
cmpq $0, 24(%rsp)
je .L53
movl $32, %esi
movq %rbx, %rdi
call _Z10randomInitPfi
movl $32, %esi
movq %rbx, %rdi
call _Z10printArrayPfi
movl $1, %ecx
movl $128, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $32, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z7cpuCalcPfPKfi
movl $32, %esi
movq %r12, %rdi
call _Z10printArrayPfi
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32, 60(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $256, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L56:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $256, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L57:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $256, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L58:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $32, %esi
movq %rbp, %rdi
call _Z10printArrayPfi
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L52:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L64
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L52
.L61:
movl $32, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11prescanEasyPfS_iPfS_i
jmp .L56
.L62:
movl $32, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11prescanBankPfS_iPfS_i
jmp .L57
.L63:
movl $32, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z7prescanPfS_iPfS_i
jmp .L58
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z7prescanPfS_i"
.LC10:
.string "_Z11prescanBankPfS_i"
.LC11:
.string "_Z11prescanEasyPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z7prescanPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prescanBankPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prescanEasyPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1112014848
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Title: prefixScan.cu
* Author: 陈志韬
* Student ID: SA12011089
*/
#include<stdio.h>
#include<stdlib.h>
#include<assert.h>
/*#include<c*/
#define NUM_BANKS 16
#define LOG_NUM_BANKS 4
#define CONFLICT_FREE_OFFSET(n) \
((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
#define DATA_SIZE 32
#define DEFAULT_BLOCK_SIZE 256
#define RAND_INT 50
//Only generate integers with value 0 or 1
#define MAX_INT_SIZE 2
typedef float calcType;
void randomInit(calcType *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = ((calcType)random() / RAND_MAX) * RAND_INT;
}
}
void randomInit(int *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = random()%MAX_INT_SIZE;
}
}
void printArray(calcType * array, int m)
{
int i = 0;
for(i = 0;i < m; i++)
{
printf("%f ", array[i]);
}
printf("\n");
}
//The size of out is larger than in by one, i.e the size of m is m+1
void cpuCalc(calcType *out, const calcType *in, int m)
{
int j = 0;
out[0] = 0;
for(j = 1;j < m;j++)
{
out[j] = out[j - 1] + in[j - 1];
}
}
__global__ void prescanEasy(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[];
int thid = threadIdx.x;
int pout = 0, pin = 1;
//Make sure the data has been transfomed into the kernel thread
/*g_odata[thid] = g_idata[thid];*/
temp[pout*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
//下面一行GPU Gems 3没有，是我在进行错误的测试的时候认为是错误点添加上的
//但是在修改73行代码之后的时候测试，不对结果产生影响。。
//temp[pin*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
__syncthreads();
/*for(int offset = 1; offset < n; offset *= 2)*/
for(int offset = 1; offset < n; offset *= 2)
{
pout = 1 - pout; //交换双缓冲区的索引
pin = 1 - pin;
if( thid >= offset)
{
//GPU Gems 3 的样例程序的代码如下：
//temp[pout*n+thid] += temp[pin*n+thid - offset];
temp[pout*n + thid] = temp[pin*n + thid] + temp[pin*n + thid -offset];
}
else
temp[pout*n + thid] = temp[pin*n + thid];
__syncthreads();
}
g_odata[thid] = temp[pout*n + thid];
}
__global__ void prescanBank(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
int d, ai, bi;
calcType t;
//Below is A
temp[2*thid] = g_idata[2*thid]; // load input into shared memory
temp[2*thid+1] = g_idata[2*thid+1];
//A end
for (d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
if (thid == 0) { temp[n - 1] = 0; } // clear the last element
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//D end
t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
g_odata[2*thid] = temp[2*thid]; // write results to device memory
g_odata[2*thid+1] = temp[2*thid+1];
//E end
}
__global__ void prescan(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
//Below is A
/*temp[2*thid] = g_idata[2*thid]; // load input into shared memory*/
/*temp[2*thid+1] = g_idata[2*thid+1];*/
int ai = thid;
int bi = thid + (n/2);
int bankOffsetA = CONFLICT_FREE_OFFSET(ai);
int bankOffsetB = CONFLICT_FREE_OFFSET(bi);
temp[ai + bankOffsetA] = g_idata[ai];
temp[bi + bankOffsetB] = g_idata[bi];
//A end
for (int d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
/*if (thid == 0) { temp[n - 1] = 0; } // clear the last element*/
if(thid == 0) { temp[n - 1 + CONFLICT_FREE_OFFSET(n -1)] = 0;}
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//D end
calcType t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
/*g_odata[2*thid] = temp[2*thid]; // write results to device memory*/
/*g_odata[2*thid+1] = temp[2*thid+1];*/
g_odata[ai] = temp[ai + bankOffsetA];
g_odata[bi] = temp[bi + bankOffsetB];
//E end
}
int main(int argc, char *argv[])
{
int data_bytes = DATA_SIZE * sizeof(calcType);
calcType *h_out = 0, *d_out = 0;
calcType *h_in = 0, *d_in = 0;
calcType *cpu = 0;
h_out = (calcType*)malloc(data_bytes);
h_in = (calcType*)malloc(data_bytes);
cpu = (calcType*)malloc(data_bytes);
cudaMalloc( (void**)&d_out, data_bytes);
cudaMalloc( (void**)&d_in, data_bytes);
if(0 == h_out || 0 == h_in || 0 == d_out || 0 == d_in)
{
printf("Couldn't allocate memory\n");
return 1;
}
randomInit(h_in, DATA_SIZE);
printArray(h_in, DATA_SIZE);
cudaMemcpy(d_in, h_in, data_bytes, cudaMemcpyHostToDevice);
cudaMemset(d_out, 0, data_bytes);
//Cpu Calc
cpuCalc(cpu, h_in, DATA_SIZE);
printArray(cpu, DATA_SIZE);
//开始进入GPU执行
dim3 grid, block;
float time;
block.x = DATA_SIZE;
/*grid.x = (DATA_SIZE + block.x - 1)/block.x;*/
grid.x = 1;
cudaEvent_t start, stop;
cudaEventCreate(&start),
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("PrescanEasy Time elapsed: %fms\n", time);
cudaEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("PrescanBank Time elapsed: %fms\n", time);
cudaEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Prescan Time elapsed: %fms\n", time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy( h_out, d_out, data_bytes, cudaMemcpyDeviceToHost );
printArray(h_out, DATA_SIZE);
free(h_in);
free(h_out);
free(cpu);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | /*
* Title: prefixScan.cu
* Author: 陈志韬
* Student ID: SA12011089
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<assert.h>
/*#include<c*/
#define NUM_BANKS 16
#define LOG_NUM_BANKS 4
#define CONFLICT_FREE_OFFSET(n) \
((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
#define DATA_SIZE 32
#define DEFAULT_BLOCK_SIZE 256
#define RAND_INT 50
//Only generate integers with value 0 or 1
#define MAX_INT_SIZE 2
typedef float calcType;
void randomInit(calcType *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = ((calcType)random() / RAND_MAX) * RAND_INT;
}
}
void randomInit(int *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = random()%MAX_INT_SIZE;
}
}
void printArray(calcType * array, int m)
{
int i = 0;
for(i = 0;i < m; i++)
{
printf("%f ", array[i]);
}
printf("\n");
}
//The size of out is larger than in by one, i.e the size of m is m+1
void cpuCalc(calcType *out, const calcType *in, int m)
{
int j = 0;
out[0] = 0;
for(j = 1;j < m;j++)
{
out[j] = out[j - 1] + in[j - 1];
}
}
__global__ void prescanEasy(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[];
int thid = threadIdx.x;
int pout = 0, pin = 1;
//Make sure the data has been transfomed into the kernel thread
/*g_odata[thid] = g_idata[thid];*/
temp[pout*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
//下面一行GPU Gems 3没有，是我在进行错误的测试的时候认为是错误点添加上的
//但是在修改73行代码之后的时候测试，不对结果产生影响。。
//temp[pin*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
__syncthreads();
/*for(int offset = 1; offset < n; offset *= 2)*/
for(int offset = 1; offset < n; offset *= 2)
{
pout = 1 - pout; //交换双缓冲区的索引
pin = 1 - pin;
if( thid >= offset)
{
//GPU Gems 3 的样例程序的代码如下：
//temp[pout*n+thid] += temp[pin*n+thid - offset];
temp[pout*n + thid] = temp[pin*n + thid] + temp[pin*n + thid -offset];
}
else
temp[pout*n + thid] = temp[pin*n + thid];
__syncthreads();
}
g_odata[thid] = temp[pout*n + thid];
}
__global__ void prescanBank(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
int d, ai, bi;
calcType t;
//Below is A
temp[2*thid] = g_idata[2*thid]; // load input into shared memory
temp[2*thid+1] = g_idata[2*thid+1];
//A end
for (d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
if (thid == 0) { temp[n - 1] = 0; } // clear the last element
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//D end
t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
g_odata[2*thid] = temp[2*thid]; // write results to device memory
g_odata[2*thid+1] = temp[2*thid+1];
//E end
}
__global__ void prescan(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
//Below is A
/*temp[2*thid] = g_idata[2*thid]; // load input into shared memory*/
/*temp[2*thid+1] = g_idata[2*thid+1];*/
int ai = thid;
int bi = thid + (n/2);
int bankOffsetA = CONFLICT_FREE_OFFSET(ai);
int bankOffsetB = CONFLICT_FREE_OFFSET(bi);
temp[ai + bankOffsetA] = g_idata[ai];
temp[bi + bankOffsetB] = g_idata[bi];
//A end
for (int d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
/*if (thid == 0) { temp[n - 1] = 0; } // clear the last element*/
if(thid == 0) { temp[n - 1 + CONFLICT_FREE_OFFSET(n -1)] = 0;}
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//D end
calcType t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
/*g_odata[2*thid] = temp[2*thid]; // write results to device memory*/
/*g_odata[2*thid+1] = temp[2*thid+1];*/
g_odata[ai] = temp[ai + bankOffsetA];
g_odata[bi] = temp[bi + bankOffsetB];
//E end
}
int main(int argc, char *argv[])
{
int data_bytes = DATA_SIZE * sizeof(calcType);
calcType *h_out = 0, *d_out = 0;
calcType *h_in = 0, *d_in = 0;
calcType *cpu = 0;
h_out = (calcType*)malloc(data_bytes);
h_in = (calcType*)malloc(data_bytes);
cpu = (calcType*)malloc(data_bytes);
hipMalloc( (void**)&d_out, data_bytes);
hipMalloc( (void**)&d_in, data_bytes);
if(0 == h_out || 0 == h_in || 0 == d_out || 0 == d_in)
{
printf("Couldn't allocate memory\n");
return 1;
}
randomInit(h_in, DATA_SIZE);
printArray(h_in, DATA_SIZE);
hipMemcpy(d_in, h_in, data_bytes, hipMemcpyHostToDevice);
hipMemset(d_out, 0, data_bytes);
//Cpu Calc
cpuCalc(cpu, h_in, DATA_SIZE);
printArray(cpu, DATA_SIZE);
//开始进入GPU执行
dim3 grid, block;
float time;
block.x = DATA_SIZE;
/*grid.x = (DATA_SIZE + block.x - 1)/block.x;*/
grid.x = 1;
hipEvent_t start, stop;
hipEventCreate(&start),
hipEventCreate(&stop);
hipEventRecord(start, 0);
prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("PrescanEasy Time elapsed: %fms\n", time);
hipEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("PrescanBank Time elapsed: %fms\n", time);
hipEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Prescan Time elapsed: %fms\n", time);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy( h_out, d_out, data_bytes, hipMemcpyDeviceToHost );
printArray(h_out, DATA_SIZE);
free(h_in);
free(h_out);
free(cpu);
hipFree(d_in);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Title: prefixScan.cu
* Author: 陈志韬
* Student ID: SA12011089
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<assert.h>
/*#include<c*/
#define NUM_BANKS 16
#define LOG_NUM_BANKS 4
#define CONFLICT_FREE_OFFSET(n) \
((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
#define DATA_SIZE 32
#define DEFAULT_BLOCK_SIZE 256
#define RAND_INT 50
//Only generate integers with value 0 or 1
#define MAX_INT_SIZE 2
typedef float calcType;
void randomInit(calcType *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = ((calcType)random() / RAND_MAX) * RAND_INT;
}
}
void randomInit(int *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = random()%MAX_INT_SIZE;
}
}
void printArray(calcType * array, int m)
{
int i = 0;
for(i = 0;i < m; i++)
{
printf("%f ", array[i]);
}
printf("\n");
}
//The size of out is larger than in by one, i.e the size of m is m+1
void cpuCalc(calcType *out, const calcType *in, int m)
{
int j = 0;
out[0] = 0;
for(j = 1;j < m;j++)
{
out[j] = out[j - 1] + in[j - 1];
}
}
__global__ void prescanEasy(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[];
int thid = threadIdx.x;
int pout = 0, pin = 1;
//Make sure the data has been transfomed into the kernel thread
/*g_odata[thid] = g_idata[thid];*/
temp[pout*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
//下面一行GPU Gems 3没有，是我在进行错误的测试的时候认为是错误点添加上的
//但是在修改73行代码之后的时候测试，不对结果产生影响。。
//temp[pin*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
__syncthreads();
/*for(int offset = 1; offset < n; offset *= 2)*/
for(int offset = 1; offset < n; offset *= 2)
{
pout = 1 - pout; //交换双缓冲区的索引
pin = 1 - pin;
if( thid >= offset)
{
//GPU Gems 3 的样例程序的代码如下：
//temp[pout*n+thid] += temp[pin*n+thid - offset];
temp[pout*n + thid] = temp[pin*n + thid] + temp[pin*n + thid -offset];
}
else
temp[pout*n + thid] = temp[pin*n + thid];
__syncthreads();
}
g_odata[thid] = temp[pout*n + thid];
}
__global__ void prescanBank(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
int d, ai, bi;
calcType t;
//Below is A
temp[2*thid] = g_idata[2*thid]; // load input into shared memory
temp[2*thid+1] = g_idata[2*thid+1];
//A end
for (d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
if (thid == 0) { temp[n - 1] = 0; } // clear the last element
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//D end
t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
g_odata[2*thid] = temp[2*thid]; // write results to device memory
g_odata[2*thid+1] = temp[2*thid+1];
//E end
}
__global__ void prescan(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
//Below is A
/*temp[2*thid] = g_idata[2*thid]; // load input into shared memory*/
/*temp[2*thid+1] = g_idata[2*thid+1];*/
int ai = thid;
int bi = thid + (n/2);
int bankOffsetA = CONFLICT_FREE_OFFSET(ai);
int bankOffsetB = CONFLICT_FREE_OFFSET(bi);
temp[ai + bankOffsetA] = g_idata[ai];
temp[bi + bankOffsetB] = g_idata[bi];
//A end
for (int d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
/*if (thid == 0) { temp[n - 1] = 0; } // clear the last element*/
if(thid == 0) { temp[n - 1 + CONFLICT_FREE_OFFSET(n -1)] = 0;}
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//D end
calcType t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
/*g_odata[2*thid] = temp[2*thid]; // write results to device memory*/
/*g_odata[2*thid+1] = temp[2*thid+1];*/
g_odata[ai] = temp[ai + bankOffsetA];
g_odata[bi] = temp[bi + bankOffsetB];
//E end
}
int main(int argc, char *argv[])
{
int data_bytes = DATA_SIZE * sizeof(calcType);
calcType *h_out = 0, *d_out = 0;
calcType *h_in = 0, *d_in = 0;
calcType *cpu = 0;
h_out = (calcType*)malloc(data_bytes);
h_in = (calcType*)malloc(data_bytes);
cpu = (calcType*)malloc(data_bytes);
hipMalloc( (void**)&d_out, data_bytes);
hipMalloc( (void**)&d_in, data_bytes);
if(0 == h_out || 0 == h_in || 0 == d_out || 0 == d_in)
{
printf("Couldn't allocate memory\n");
return 1;
}
randomInit(h_in, DATA_SIZE);
printArray(h_in, DATA_SIZE);
hipMemcpy(d_in, h_in, data_bytes, hipMemcpyHostToDevice);
hipMemset(d_out, 0, data_bytes);
//Cpu Calc
cpuCalc(cpu, h_in, DATA_SIZE);
printArray(cpu, DATA_SIZE);
//开始进入GPU执行
dim3 grid, block;
float time;
block.x = DATA_SIZE;
/*grid.x = (DATA_SIZE + block.x - 1)/block.x;*/
grid.x = 1;
hipEvent_t start, stop;
hipEventCreate(&start),
hipEventCreate(&stop);
hipEventRecord(start, 0);
prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("PrescanEasy Time elapsed: %fms\n", time);
hipEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("PrescanBank Time elapsed: %fms\n", time);
hipEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Prescan Time elapsed: %fms\n", time);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy( h_out, d_out, data_bytes, hipMemcpyDeviceToHost );
printArray(h_out, DATA_SIZE);
free(h_in);
free(h_out);
free(cpu);
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11prescanEasyPfS_i
.globl _Z11prescanEasyPfS_i
.p2align 8
.type _Z11prescanEasyPfS_i,@function
_Z11prescanEasyPfS_i:
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[4:5] offset:-4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x10
v_lshl_add_u32 v2, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s3, 2
s_cbranch_scc1 .LBB0_7
s_mov_b32 s4, 1
s_mov_b32 s5, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_sub_i32 s2, 1, s2
s_lshl_b32 s4, s4, 1
v_mad_u64_u32 v[3:4], null, s2, s3, v[0:1]
s_cmp_ge_i32 s4, s3
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v3, 2, 0
s_waitcnt lgkmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_sub_i32 s5, 1, s5
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s5, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v1, 2, 0
ds_load_b32 v2, v2
v_cmpx_le_u32_e64 s4, v0
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v1
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11prescanEasyPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11prescanEasyPfS_i, .Lfunc_end0-_Z11prescanEasyPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11prescanBankPfS_i
.globl _Z11prescanBankPfS_i
.p2align 8
.type _Z11prescanBankPfS_i,@function
_Z11prescanBankPfS_i:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x10
v_lshlrev_b32_e32 v1, 1, v0
v_lshlrev_b32_e32 v3, 3, v0
s_mov_b32 s3, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v2, 1, v1
v_add_nc_u32_e32 v4, 0, v3
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v6, v3, s[4:5]
global_load_b32 v7, v5, s[4:5]
v_add_nc_u32_e32 v3, 0, v5
s_ashr_i32 s4, s2, 1
s_waitcnt vmcnt(1)
ds_store_b32 v4, v6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v7
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_6
v_add_nc_u32_e32 v5, 2, v1
.p2align 6
.LBB1_2:
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB1_4
v_mul_lo_u32 v6, s3, v2
v_mul_lo_u32 v7, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v7, 2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v6, v6, 0, -4
v_add3_u32 v7, v7, 0, -4
ds_load_b32 v6, v6
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v8
ds_store_b32 v7, v6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s3, s3, 1
s_lshr_b32 s5, s4, 1
s_cmp_gt_u32 s4, 1
s_cbranch_scc0 .LBB1_6
s_mov_b32 s4, s5
s_branch .LBB1_2
.LBB1_6:
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_8
s_lshl_b32 s5, s2, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, 0
s_add_i32 s5, s5, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s5
ds_store_b32 v6, v5
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB1_13
v_add_nc_u32_e32 v5, 2, v1
s_mov_b32 s4, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_11
.p2align 6
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s4, s2
s_cbranch_scc1 .LBB1_13
.LBB1_11:
s_lshr_b32 s3, s3, 1
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_10
v_mul_lo_u32 v6, s3, v5
v_mul_lo_u32 v8, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v8, 2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v6, v6, 0, -4
v_add3_u32 v8, v8, 0, -4
ds_load_b32 v7, v6
ds_load_b32 v9, v8
s_waitcnt lgkmcnt(1)
ds_store_b32 v8, v7
ds_load_b32 v7, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v7, v9, v7
ds_store_b32 v6, v7
s_branch .LBB1_10
.LBB1_13:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v0, v4
ds_load_b32 v3, v3
v_lshlrev_b32_e32 v1, 2, v1
v_lshlrev_b32_e32 v2, 2, v2
s_waitcnt lgkmcnt(1)
global_store_b32 v1, v0, s[0:1]
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v3, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11prescanBankPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11prescanBankPfS_i, .Lfunc_end1-_Z11prescanBankPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7prescanPfS_i
.globl _Z7prescanPfS_i
.p2align 8
.type _Z7prescanPfS_i,@function
_Z7prescanPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s2, s3
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s3, v0
s_mov_b32 s3, 1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_clause 0x1
global_load_b32 v6, v5, s[4:5]
global_load_b32 v7, v[3:4], off
v_add_nc_u32_e32 v3, 16, v1
v_add_nc_u32_e32 v4, 0, v5
s_ashr_i32 s4, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lt_i32 s4, 1
v_ashrrev_i32_e32 v3, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 8, v3
v_add_nc_u32_e32 v3, v3, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 2, 0
s_waitcnt vmcnt(1)
ds_store_b32 v4, v6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v7
s_cbranch_scc1 .LBB2_6
v_lshlrev_b32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v5, 1, v6
v_add_nc_u32_e32 v6, 2, v6
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB2_2:
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB2_4
v_mul_lo_u32 v7, s3, v5
v_mul_lo_u32 v8, s3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v9, -1, v7
v_add_nc_u32_e32 v7, 15, v7
v_add_nc_u32_e32 v10, -1, v8
v_add_nc_u32_e32 v8, 15, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, v7, v9
v_ashrrev_i32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 8, v7
v_ashrrev_i32_e32 v8, 8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v7, v9
v_add_nc_u32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v7, v7, 2, 0
v_lshl_add_u32 v8, v8, 2, 0
ds_load_b32 v7, v7
ds_load_b32 v9, v8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v7, v7, v9
ds_store_b32 v8, v7
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s3, s3, 1
s_lshr_b32 s5, s4, 1
s_cmp_lt_u32 s4, 2
s_cbranch_scc1 .LBB2_6
s_mov_b32 s4, s5
s_branch .LBB2_2
.LBB2_6:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_8
s_add_i32 s5, s2, -1
s_add_i32 s6, s2, 15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s5, s6
s_ashr_i32 s6, s6, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s5
s_lshl_b32 s5, s6, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, 0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s5
ds_store_b32 v6, v5
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB2_13
v_lshlrev_b32_e32 v6, 1, v0
s_mov_b32 s4, 1
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v5, 1, v6
v_add_nc_u32_e32 v6, 2, v6
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_11
.p2align 6
.LBB2_10:
s_or_b32 exec_lo, exec_lo, s5
s_lshl_b32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s4, s2
s_cbranch_scc1 .LBB2_13
.LBB2_11:
s_lshr_b32 s3, s3, 1
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB2_10
v_mul_lo_u32 v7, s3, v6
v_mul_lo_u32 v9, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v7, 15, v7
v_ashrrev_i32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 8, v7
v_add_nc_u32_e32 v7, v7, v8
v_add_nc_u32_e32 v8, -1, v9
v_add_nc_u32_e32 v9, 15, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v7, v7, 2, 0
v_ashrrev_i32_e32 v9, v9, v8
ds_load_b32 v10, v7
v_ashrrev_i32_e32 v9, 8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v9, v8
v_lshl_add_u32 v8, v8, 2, 0
ds_load_b32 v9, v8
s_waitcnt lgkmcnt(1)
ds_store_b32 v8, v10
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v8, v9, v8
ds_store_b32 v7, v8
s_branch .LBB2_10
.LBB2_13:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v4
ds_load_b32 v3, v3
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_waitcnt lgkmcnt(1)
global_store_b32 v5, v4, s[0:1]
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7prescanPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7prescanPfS_i, .Lfunc_end2-_Z7prescanPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11prescanEasyPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z11prescanEasyPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11prescanBankPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11prescanBankPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7prescanPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z7prescanPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Title: prefixScan.cu
* Author: 陈志韬
* Student ID: SA12011089
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<assert.h>
/*#include<c*/
#define NUM_BANKS 16
#define LOG_NUM_BANKS 4
#define CONFLICT_FREE_OFFSET(n) \
((n) >> NUM_BANKS + (n) >> (2 * LOG_NUM_BANKS))
#define DATA_SIZE 32
#define DEFAULT_BLOCK_SIZE 256
#define RAND_INT 50
//Only generate integers with value 0 or 1
#define MAX_INT_SIZE 2
typedef float calcType;
void randomInit(calcType *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = ((calcType)random() / RAND_MAX) * RAND_INT;
}
}
void randomInit(int *array, int m)
{
/*srand(time(0));*/
for(int i = 0;i < m; i++)
{
array[i] = random()%MAX_INT_SIZE;
}
}
void printArray(calcType * array, int m)
{
int i = 0;
for(i = 0;i < m; i++)
{
printf("%f ", array[i]);
}
printf("\n");
}
//The size of out is larger than in by one, i.e the size of m is m+1
void cpuCalc(calcType *out, const calcType *in, int m)
{
int j = 0;
out[0] = 0;
for(j = 1;j < m;j++)
{
out[j] = out[j - 1] + in[j - 1];
}
}
__global__ void prescanEasy(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[];
int thid = threadIdx.x;
int pout = 0, pin = 1;
//Make sure the data has been transfomed into the kernel thread
/*g_odata[thid] = g_idata[thid];*/
temp[pout*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
//下面一行GPU Gems 3没有，是我在进行错误的测试的时候认为是错误点添加上的
//但是在修改73行代码之后的时候测试，不对结果产生影响。。
//temp[pin*n + thid] = (thid > 0) ? g_idata[thid - 1] : 0;
__syncthreads();
/*for(int offset = 1; offset < n; offset *= 2)*/
for(int offset = 1; offset < n; offset *= 2)
{
pout = 1 - pout; //交换双缓冲区的索引
pin = 1 - pin;
if( thid >= offset)
{
//GPU Gems 3 的样例程序的代码如下：
//temp[pout*n+thid] += temp[pin*n+thid - offset];
temp[pout*n + thid] = temp[pin*n + thid] + temp[pin*n + thid -offset];
}
else
temp[pout*n + thid] = temp[pin*n + thid];
__syncthreads();
}
g_odata[thid] = temp[pout*n + thid];
}
__global__ void prescanBank(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
int d, ai, bi;
calcType t;
//Below is A
temp[2*thid] = g_idata[2*thid]; // load input into shared memory
temp[2*thid+1] = g_idata[2*thid+1];
//A end
for (d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
if (thid == 0) { temp[n - 1] = 0; } // clear the last element
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
ai = offset*(2*thid+1)-1;
bi = offset*(2*thid+2)-1;
//D end
t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
g_odata[2*thid] = temp[2*thid]; // write results to device memory
g_odata[2*thid+1] = temp[2*thid+1];
//E end
}
__global__ void prescan(calcType *g_odata, calcType *g_idata, int n)
{
extern __shared__ calcType temp[]; // allocated on invocation
int thid = threadIdx.x;
int offset = 1;
//Below is A
/*temp[2*thid] = g_idata[2*thid]; // load input into shared memory*/
/*temp[2*thid+1] = g_idata[2*thid+1];*/
int ai = thid;
int bi = thid + (n/2);
int bankOffsetA = CONFLICT_FREE_OFFSET(ai);
int bankOffsetB = CONFLICT_FREE_OFFSET(bi);
temp[ai + bankOffsetA] = g_idata[ai];
temp[bi + bankOffsetB] = g_idata[bi];
//A end
for (int d = n>>1; d > 0; d >>= 1) // build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
//Below is B
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//B end
temp[bi] += temp[ai];
}
offset *= 2;
}
//Below is C
/*if (thid == 0) { temp[n - 1] = 0; } // clear the last element*/
if(thid == 0) { temp[n - 1 + CONFLICT_FREE_OFFSET(n -1)] = 0;}
//C end
for (int d = 1; d < n; d *= 2) // traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
//Below is D
/*int ai = offset*(2*thid+1)-1;*/
/*int bi = offset*(2*thid+2)-1;*/
int ai = offset * (2*thid + 1) - 1;
int bi = offset * (2*thid + 2) - 1;
ai += CONFLICT_FREE_OFFSET(ai);
bi += CONFLICT_FREE_OFFSET(bi);
//D end
calcType t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
}
__syncthreads();
//Below is E
/*g_odata[2*thid] = temp[2*thid]; // write results to device memory*/
/*g_odata[2*thid+1] = temp[2*thid+1];*/
g_odata[ai] = temp[ai + bankOffsetA];
g_odata[bi] = temp[bi + bankOffsetB];
//E end
}
int main(int argc, char *argv[])
{
int data_bytes = DATA_SIZE * sizeof(calcType);
calcType *h_out = 0, *d_out = 0;
calcType *h_in = 0, *d_in = 0;
calcType *cpu = 0;
h_out = (calcType*)malloc(data_bytes);
h_in = (calcType*)malloc(data_bytes);
cpu = (calcType*)malloc(data_bytes);
hipMalloc( (void**)&d_out, data_bytes);
hipMalloc( (void**)&d_in, data_bytes);
if(0 == h_out || 0 == h_in || 0 == d_out || 0 == d_in)
{
printf("Couldn't allocate memory\n");
return 1;
}
randomInit(h_in, DATA_SIZE);
printArray(h_in, DATA_SIZE);
hipMemcpy(d_in, h_in, data_bytes, hipMemcpyHostToDevice);
hipMemset(d_out, 0, data_bytes);
//Cpu Calc
cpuCalc(cpu, h_in, DATA_SIZE);
printArray(cpu, DATA_SIZE);
//开始进入GPU执行
dim3 grid, block;
float time;
block.x = DATA_SIZE;
/*grid.x = (DATA_SIZE + block.x - 1)/block.x;*/
grid.x = 1;
hipEvent_t start, stop;
hipEventCreate(&start),
hipEventCreate(&stop);
hipEventRecord(start, 0);
prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("PrescanEasy Time elapsed: %fms\n", time);
hipEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
/*prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("PrescanBank Time elapsed: %fms\n", time);
hipEventRecord(start, 0);
/*prescanEasy<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
/*prescanBank<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);*/
prescan<<<grid, block, data_bytes * 2>>>(d_out, d_in, DATA_SIZE);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Prescan Time elapsed: %fms\n", time);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy( h_out, d_out, data_bytes, hipMemcpyDeviceToHost );
printArray(h_out, DATA_SIZE);
free(h_in);
free(h_out);
free(cpu);
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.file "prefixSum.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10randomInitPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x42480000 # float 50
.text
.globl _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
mulss .LCPI0_1(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10randomInitPfi, .Lfunc_end0-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl _Z10randomInitPii # -- Begin function _Z10randomInitPii
.p2align 4, 0x90
.type _Z10randomInitPii,@function
_Z10randomInitPii: # @_Z10randomInitPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq random
movq %rax, %rcx
shrq $63, %rcx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10randomInitPii, .Lfunc_end1-_Z10randomInitPii
.cfi_endproc
# -- End function
.globl _Z10printArrayPfi # -- Begin function _Z10printArrayPfi
.p2align 4, 0x90
.type _Z10printArrayPfi,@function
_Z10printArrayPfi: # @_Z10printArrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z10printArrayPfi, .Lfunc_end2-_Z10printArrayPfi
.cfi_endproc
# -- End function
.globl _Z7cpuCalcPfPKfi # -- Begin function _Z7cpuCalcPfPKfi
.p2align 4, 0x90
.type _Z7cpuCalcPfPKfi,@function
_Z7cpuCalcPfPKfi: # @_Z7cpuCalcPfPKfi
.cfi_startproc
# %bb.0:
movl $0, (%rdi)
cmpl $2, %edx
jl .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
decq %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, 4(%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z7cpuCalcPfPKfi, .Lfunc_end3-_Z7cpuCalcPfPKfi
.cfi_endproc
# -- End function
.globl _Z26__device_stub__prescanEasyPfS_i # -- Begin function _Z26__device_stub__prescanEasyPfS_i
.p2align 4, 0x90
.type _Z26__device_stub__prescanEasyPfS_i,@function
_Z26__device_stub__prescanEasyPfS_i: # @_Z26__device_stub__prescanEasyPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11prescanEasyPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z26__device_stub__prescanEasyPfS_i, .Lfunc_end4-_Z26__device_stub__prescanEasyPfS_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__prescanBankPfS_i # -- Begin function _Z26__device_stub__prescanBankPfS_i
.p2align 4, 0x90
.type _Z26__device_stub__prescanBankPfS_i,@function
_Z26__device_stub__prescanBankPfS_i: # @_Z26__device_stub__prescanBankPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11prescanBankPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z26__device_stub__prescanBankPfS_i, .Lfunc_end5-_Z26__device_stub__prescanBankPfS_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__prescanPfS_i # -- Begin function _Z22__device_stub__prescanPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__prescanPfS_i,@function
_Z22__device_stub__prescanPfS_i: # @_Z22__device_stub__prescanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7prescanPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z22__device_stub__prescanPfS_i, .Lfunc_end6-_Z22__device_stub__prescanPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI7_1:
.long 0x42480000 # float 50
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 24(%rsp)
movq $0, 40(%rsp)
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $128, %edi
callq malloc
movq %rax, %r15
movl $128, %edi
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 40(%rsp), %rdi
movl $128, %esi
callq hipMalloc
testq %rbx, %rbx
je .LBB7_22
# %bb.1:
testq %r15, %r15
je .LBB7_22
# %bb.2:
cmpq $0, 24(%rsp)
je .LBB7_22
# %bb.3:
cmpq $0, 40(%rsp)
je .LBB7_22
# %bb.4: # %.lr.ph.i.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI7_0(%rip), %xmm0
mulss .LCPI7_1(%rip), %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $32, %r12
jne .LBB7_5
# %bb.6: # %.lr.ph.i55.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_7: # %.lr.ph.i55
# =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $32, %r12
jne .LBB7_7
# %bb.8: # %_Z10printArrayPfi.exit
movl $10, %edi
callq putchar@PLT
movq 40(%rsp), %rdi
movl $128, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $128, %edx
xorl %esi, %esi
callq hipMemset
movl $0, (%r14)
movl $1, %eax
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB7_9: # %.lr.ph.i59
# =>This Inner Loop Header: Depth=1
addss -4(%r15,%rax,4), %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB7_9
# %bb.10: # %.lr.ph.i63.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_11: # %.lr.ph.i63
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $32, %r12
jne .LBB7_11
# %bb.12: # %_Z10printArrayPfi.exit68
movabsq $4294967297, %r12 # imm = 0x100000001
movl $10, %edi
callq putchar@PLT
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 31(%r12), %r13
movl $256, %r8d # imm = 0x100
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_14
# %bb.13:
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $32, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11prescanEasyPfS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_14:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $256, %r8d # imm = 0x100
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_16
# %bb.15:
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $32, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11prescanBankPfS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_16:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $256, %r8d # imm = 0x100
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_18
# %bb.17:
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $32, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7prescanPfS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_18:
movq 16(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB7_19: # %.lr.ph.i81
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $32, %r12
jne .LBB7_19
# %bb.20: # %_Z10printArrayPfi.exit86
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB7_21
.LBB7_22:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
.LBB7_21:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prescanEasyPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prescanBankPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7prescanPfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type _Z11prescanEasyPfS_i,@object # @_Z11prescanEasyPfS_i
.section .rodata,"a",@progbits
.globl _Z11prescanEasyPfS_i
.p2align 3, 0x0
_Z11prescanEasyPfS_i:
.quad _Z26__device_stub__prescanEasyPfS_i
.size _Z11prescanEasyPfS_i, 8
.type _Z11prescanBankPfS_i,@object # @_Z11prescanBankPfS_i
.globl _Z11prescanBankPfS_i
.p2align 3, 0x0
_Z11prescanBankPfS_i:
.quad _Z26__device_stub__prescanBankPfS_i
.size _Z11prescanBankPfS_i, 8
.type _Z7prescanPfS_i,@object # @_Z7prescanPfS_i
.globl _Z7prescanPfS_i
.p2align 3, 0x0
_Z7prescanPfS_i:
.quad _Z22__device_stub__prescanPfS_i
.size _Z7prescanPfS_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "PrescanEasy Time elapsed: %fms\n"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "PrescanBank Time elapsed: %fms\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Prescan Time elapsed: %fms\n"
.size .L.str.5, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11prescanEasyPfS_i"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11prescanBankPfS_i"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7prescanPfS_i"
.size .L__unnamed_3, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__prescanEasyPfS_i
.addrsig_sym _Z26__device_stub__prescanBankPfS_i
.addrsig_sym _Z22__device_stub__prescanPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11prescanEasyPfS_i
.addrsig_sym _Z11prescanBankPfS_i
.addrsig_sym _Z7prescanPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000116c0_00000000-6_prefixSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call random@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.globl _Z10randomInitPii
.type _Z10randomInitPii, @function
_Z10randomInitPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L13:
call random@PLT
movq %rax, %rdx
shrq $63, %rdx
addq %rdx, %rax
andl $1, %eax
subq %rdx, %rax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z10randomInitPii, .-_Z10randomInitPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.text
.globl _Z10printArrayPfi
.type _Z10printArrayPfi, @function
_Z10printArrayPfi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L20
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC2(%rip), %rbp
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L21
.L20:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10printArrayPfi, .-_Z10printArrayPfi
.globl _Z7cpuCalcPfPKfi
.type _Z7cpuCalcPfPKfi, @function
_Z7cpuCalcPfPKfi:
.LFB2060:
.cfi_startproc
endbr64
movl $0x00000000, (%rdi)
cmpl $1, %edx
jle .L24
leal -1(%rdx), %edx
movl $0, %eax
.L26:
movss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, 4(%rdi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L26
.L24:
ret
.cfi_endproc
.LFE2060:
.size _Z7cpuCalcPfPKfi, .-_Z7cpuCalcPfPKfi
.globl _Z34__device_stub__Z11prescanEasyPfS_iPfS_i
.type _Z34__device_stub__Z11prescanEasyPfS_iPfS_i, @function
_Z34__device_stub__Z11prescanEasyPfS_iPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11prescanEasyPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z34__device_stub__Z11prescanEasyPfS_iPfS_i, .-_Z34__device_stub__Z11prescanEasyPfS_iPfS_i
.globl _Z11prescanEasyPfS_i
.type _Z11prescanEasyPfS_i, @function
_Z11prescanEasyPfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11prescanEasyPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11prescanEasyPfS_i, .-_Z11prescanEasyPfS_i
.globl _Z34__device_stub__Z11prescanBankPfS_iPfS_i
.type _Z34__device_stub__Z11prescanBankPfS_iPfS_i, @function
_Z34__device_stub__Z11prescanBankPfS_iPfS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11prescanBankPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z34__device_stub__Z11prescanBankPfS_iPfS_i, .-_Z34__device_stub__Z11prescanBankPfS_iPfS_i
.globl _Z11prescanBankPfS_i
.type _Z11prescanBankPfS_i, @function
_Z11prescanBankPfS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11prescanBankPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z11prescanBankPfS_i, .-_Z11prescanBankPfS_i
.globl _Z29__device_stub__Z7prescanPfS_iPfS_i
.type _Z29__device_stub__Z7prescanPfS_iPfS_i, @function
_Z29__device_stub__Z7prescanPfS_iPfS_i:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7prescanPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z29__device_stub__Z7prescanPfS_iPfS_i, .-_Z29__device_stub__Z7prescanPfS_iPfS_i
.globl _Z7prescanPfS_i
.type _Z7prescanPfS_i, @function
_Z7prescanPfS_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7prescanPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z7prescanPfS_i, .-_Z7prescanPfS_i
.section .rodata.str1.1
.LC5:
.string "Couldn't allocate memory\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "PrescanEasy Time elapsed: %fms\n"
.align 8
.LC7:
.string "PrescanBank Time elapsed: %fms\n"
.section .rodata.str1.1
.LC8:
.string "Prescan Time elapsed: %fms\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $128, %edi
call malloc@PLT
movq %rax, %rbx
movl $128, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
testq %rbp, %rbp
je .L53
testq %rbx, %rbx
je .L53
cmpq $0, 16(%rsp)
je .L53
cmpq $0, 24(%rsp)
je .L53
movl $32, %esi
movq %rbx, %rdi
call _Z10randomInitPfi
movl $32, %esi
movq %rbx, %rdi
call _Z10printArrayPfi
movl $1, %ecx
movl $128, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $32, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z7cpuCalcPfPKfi
movl $32, %esi
movq %r12, %rdi
call _Z10printArrayPfi
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32, 60(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $256, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L56:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $256, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L57:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $256, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L58:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $32, %esi
movq %rbp, %rdi
call _Z10printArrayPfi
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L52:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L64
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L52
.L61:
movl $32, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11prescanEasyPfS_iPfS_i
jmp .L56
.L62:
movl $32, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11prescanBankPfS_iPfS_i
jmp .L57
.L63:
movl $32, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z7prescanPfS_iPfS_i
jmp .L58
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z7prescanPfS_i"
.LC10:
.string "_Z11prescanBankPfS_i"
.LC11:
.string "_Z11prescanEasyPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z7prescanPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prescanBankPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prescanEasyPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1112014848
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prefixSum.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10randomInitPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x42480000 # float 50
.text
.globl _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
mulss .LCPI0_1(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10randomInitPfi, .Lfunc_end0-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl _Z10randomInitPii # -- Begin function _Z10randomInitPii
.p2align 4, 0x90
.type _Z10randomInitPii,@function
_Z10randomInitPii: # @_Z10randomInitPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq random
movq %rax, %rcx
shrq $63, %rcx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10randomInitPii, .Lfunc_end1-_Z10randomInitPii
.cfi_endproc
# -- End function
.globl _Z10printArrayPfi # -- Begin function _Z10printArrayPfi
.p2align 4, 0x90
.type _Z10printArrayPfi,@function
_Z10printArrayPfi: # @_Z10printArrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z10printArrayPfi, .Lfunc_end2-_Z10printArrayPfi
.cfi_endproc
# -- End function
.globl _Z7cpuCalcPfPKfi # -- Begin function _Z7cpuCalcPfPKfi
.p2align 4, 0x90
.type _Z7cpuCalcPfPKfi,@function
_Z7cpuCalcPfPKfi: # @_Z7cpuCalcPfPKfi
.cfi_startproc
# %bb.0:
movl $0, (%rdi)
cmpl $2, %edx
jl .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
decq %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, 4(%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z7cpuCalcPfPKfi, .Lfunc_end3-_Z7cpuCalcPfPKfi
.cfi_endproc
# -- End function
.globl _Z26__device_stub__prescanEasyPfS_i # -- Begin function _Z26__device_stub__prescanEasyPfS_i
.p2align 4, 0x90
.type _Z26__device_stub__prescanEasyPfS_i,@function
_Z26__device_stub__prescanEasyPfS_i: # @_Z26__device_stub__prescanEasyPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11prescanEasyPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z26__device_stub__prescanEasyPfS_i, .Lfunc_end4-_Z26__device_stub__prescanEasyPfS_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__prescanBankPfS_i # -- Begin function _Z26__device_stub__prescanBankPfS_i
.p2align 4, 0x90
.type _Z26__device_stub__prescanBankPfS_i,@function
_Z26__device_stub__prescanBankPfS_i: # @_Z26__device_stub__prescanBankPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11prescanBankPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z26__device_stub__prescanBankPfS_i, .Lfunc_end5-_Z26__device_stub__prescanBankPfS_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__prescanPfS_i # -- Begin function _Z22__device_stub__prescanPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__prescanPfS_i,@function
_Z22__device_stub__prescanPfS_i: # @_Z22__device_stub__prescanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7prescanPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z22__device_stub__prescanPfS_i, .Lfunc_end6-_Z22__device_stub__prescanPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI7_1:
.long 0x42480000 # float 50
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 24(%rsp)
movq $0, 40(%rsp)
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $128, %edi
callq malloc
movq %rax, %r15
movl $128, %edi
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 40(%rsp), %rdi
movl $128, %esi
callq hipMalloc
testq %rbx, %rbx
je .LBB7_22
# %bb.1:
testq %r15, %r15
je .LBB7_22
# %bb.2:
cmpq $0, 24(%rsp)
je .LBB7_22
# %bb.3:
cmpq $0, 40(%rsp)
je .LBB7_22
# %bb.4: # %.lr.ph.i.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI7_0(%rip), %xmm0
mulss .LCPI7_1(%rip), %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $32, %r12
jne .LBB7_5
# %bb.6: # %.lr.ph.i55.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_7: # %.lr.ph.i55
# =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $32, %r12
jne .LBB7_7
# %bb.8: # %_Z10printArrayPfi.exit
movl $10, %edi
callq putchar@PLT
movq 40(%rsp), %rdi
movl $128, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $128, %edx
xorl %esi, %esi
callq hipMemset
movl $0, (%r14)
movl $1, %eax
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB7_9: # %.lr.ph.i59
# =>This Inner Loop Header: Depth=1
addss -4(%r15,%rax,4), %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB7_9
# %bb.10: # %.lr.ph.i63.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_11: # %.lr.ph.i63
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $32, %r12
jne .LBB7_11
# %bb.12: # %_Z10printArrayPfi.exit68
movabsq $4294967297, %r12 # imm = 0x100000001
movl $10, %edi
callq putchar@PLT
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 31(%r12), %r13
movl $256, %r8d # imm = 0x100
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_14
# %bb.13:
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $32, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11prescanEasyPfS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_14:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $256, %r8d # imm = 0x100
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_16
# %bb.15:
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $32, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11prescanBankPfS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_16:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $256, %r8d # imm = 0x100
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_18
# %bb.17:
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $32, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7prescanPfS_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_18:
movq 16(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB7_19: # %.lr.ph.i81
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $32, %r12
jne .LBB7_19
# %bb.20: # %_Z10printArrayPfi.exit86
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB7_21
.LBB7_22:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
.LBB7_21:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prescanEasyPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prescanBankPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7prescanPfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type _Z11prescanEasyPfS_i,@object # @_Z11prescanEasyPfS_i
.section .rodata,"a",@progbits
.globl _Z11prescanEasyPfS_i
.p2align 3, 0x0
_Z11prescanEasyPfS_i:
.quad _Z26__device_stub__prescanEasyPfS_i
.size _Z11prescanEasyPfS_i, 8
.type _Z11prescanBankPfS_i,@object # @_Z11prescanBankPfS_i
.globl _Z11prescanBankPfS_i
.p2align 3, 0x0
_Z11prescanBankPfS_i:
.quad _Z26__device_stub__prescanBankPfS_i
.size _Z11prescanBankPfS_i, 8
.type _Z7prescanPfS_i,@object # @_Z7prescanPfS_i
.globl _Z7prescanPfS_i
.p2align 3, 0x0
_Z7prescanPfS_i:
.quad _Z22__device_stub__prescanPfS_i
.size _Z7prescanPfS_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "PrescanEasy Time elapsed: %fms\n"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "PrescanBank Time elapsed: %fms\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Prescan Time elapsed: %fms\n"
.size .L.str.5, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11prescanEasyPfS_i"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11prescanBankPfS_i"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7prescanPfS_i"
.size .L__unnamed_3, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__prescanEasyPfS_i
.addrsig_sym _Z26__device_stub__prescanBankPfS_i
.addrsig_sym _Z22__device_stub__prescanPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11prescanEasyPfS_i
.addrsig_sym _Z11prescanBankPfS_i
.addrsig_sym _Z7prescanPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Written by Vasily Volkov.
// Copyright (c) 2008, The Regents of the University of California.
// All rights reserved.
#include <time.h>
#include "sgemmN.cuh"
#include "cuda_runtime.h"
#define BLOCK_SIZE 32
__device__ void saxpy( float a, float *b, float *c )
{
c[0] += a*b[0];
c[1] += a*b[1];
c[2] += a*b[2];
c[3] += a*b[3];
c[4] += a*b[4];
c[5] += a*b[5];
c[6] += a*b[6];
c[7] += a*b[7];
c[8] += a*b[8];
c[9] += a*b[9];
c[10] += a*b[10];
c[11] += a*b[11];
c[12] += a*b[12];
c[13] += a*b[13];
c[14] += a*b[14];
c[15] += a*b[15];
}
__device__ void saxpy2( const float* a, const float *b, const float *a2, float *c )
{
c[0] += a[0] *b[0] * a2[0];
c[1] += a[1] *b[1] * a2[0];
c[2] += a[2] *b[2] * a2[0];
c[3] += a[3] *b[3] * a2[0];
c[4] += a[4] *b[4] * a2[0];
c[5] += a[5] *b[5] * a2[0];
c[6] += a[6] *b[6] * a2[0];
c[7] += a[7] *b[7] * a2[0];
c[8] += a[8] *b[8] * a2[0];
c[9] += a[9] *b[9] * a2[0];
c[10] += a[10]*b[10] * a2[0];
c[11] += a[11]*b[11] * a2[0];
c[12] += a[12]*b[12] * a2[0];
c[13] += a[13]*b[13] * a2[0];
c[14] += a[14]*b[14] * a2[0];
c[15] += a[15]*b[15] * a2[0];
}
__device__ void saxpy3( const float* a, const float *b, float *c )
{
c[0] += a[0] *b[0] ;
c[1] += a[1] *b[1] ;
c[2] += a[2] *b[2] ;
c[3] += a[3] *b[3] ;
c[4] += a[4] *b[4] ;
c[5] += a[5] *b[5] ;
c[6] += a[6] *b[6] ;
c[7] += a[7] *b[7] ;
c[8] += a[8] *b[8] ;
c[9] += a[9] *b[9] ;
c[10] += a[10]*b[10] ;
c[11] += a[11]*b[11] ;
c[12] += a[12]*b[12] ;
c[13] += a[13]*b[13] ;
c[14] += a[14]*b[14] ;
c[15] += a[15]*b[15] ;
}
__device__ void saxpy64( const float* a, const float *b, float *c )
{
#pragma unroll
for( int i = 0; i < 64; i++)
c[i] = a[i]*b[i] ;
}
__device__ void saxpy32( const float* a, const float *b, float *c, const float* balance )
{
#pragma unroll
for( int i = 0; i < 32; i++)
c[i] = a[i]*b[i]* balance[0];
}
__device__ void redux32sum( const float* a, float* res )
{
float c2[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
float c[8] = {0,0,0,0,0,0,0,0};
// 32 -> 16
#pragma unroll
for( int i = 0; i < 16; i++)
c2[i] = a[i] + a[16+i];
// 16 -> 8
#pragma unroll
for( int i = 0; i < 8; i++)
c[i] = c2[8+i] + c2[i];
//8 -> 4
#pragma unroll
for( int i = 0; i < 4; i++)
c2[i] = c[4+i] + c[i];
//4->2
#pragma unroll
for( int i = 0; i < 2; i++)
c[i] = c2[2+i] + c2[i];
// 2->1
*res = c[0] + c[1];
}
__device__ void redux64sum( const float* a, float* res )
{
float c[32] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
float c2[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
// 64 -> 32
#pragma unroll
for( int i = 0; i < 64; i++)
c[i] = a[i] + a[32+i];
// 32 -> 16
#pragma unroll
for( int i = 0; i < 16; i++)
c2[i] = c[16+i] + c[i];
// 16 -> 8
#pragma unroll
for( int i = 0; i < 8; i++)
c[i] = c2[8+i] + c2[i];
//8 -> 4
#pragma unroll
for( int i = 0; i < 4; i++)
c2[i] = c[4+i] + c[i];
//4->2
#pragma unroll
for( int i = 0; i < 2; i++)
c[i] = c2[2+i] + c2[i];
// 2->1
*res = c[0] + c[1];
}
__device__ void redux16sum( const float* a, float* res )
{
float c[8] = {0,0,0,0,0,0,0,0};
// 16 -> 8
#pragma unroll
for( int i = 0; i < 8; i++)
c[i] += a[i] + a[i*2];
//8 -> 4
#pragma unroll
for( int i = 0; i < 4; i++)
c[i] += a[i] + a[i*2];
//4->2
#pragma unroll
for( int i = 0; i < 2; i++)
c[i] += a[i] + a[i*2];
// 2->1
*res = c[0] + c[1];
}
extern "C" __global__ void sgemmNT( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
const int inx = threadIdx.x;
const int iny = threadIdx.y;
const int ibx = blockIdx.x * 64;
const int iby = blockIdx.y * 16;
const int id = inx + iny*16;
A += ibx + id;
B += iby + inx + __mul24( iny, ldb );
C += ibx + id + __mul24( iby, ldc );
const float *Blast = B + k*ldb;
float c[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
__shared__ float bs[16][16];
do
{
#pragma unroll
for( int i = 0; i < 16; i += 4 )
bs[iny+i][inx] = B[i*ldb];
__syncthreads();
#pragma unroll
for( int i = 0; i < 16; i++, A += lda )
saxpy( A[0], &bs[i][0], c );
B += 16*ldb;
__syncthreads();
} while( B < Blast );
for( int i = 0; i < 16; i++, C += ldc )
C[0] = alpha*c[i] + beta*C[0];
}
extern "C" __global__ void sgemmNN( const float *A, int lda, const float *B, int ldb, float* C, int ldc, int k, float alpha, float beta )
{
const int inx = threadIdx.x;
const int iny = threadIdx.y;
const int ibx = blockIdx.x * 64;
const int iby = blockIdx.y * 16;
const int id = inx + iny*16;
A += ibx + id;
B += inx + __mul24( iby + iny, ldb );
C += ibx + id + __mul24( iby, ldc );
const float *Blast = B + k;
float c[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
__shared__ float bs[16][17];
do
{
#pragma unroll
for( int i = 0; i < 16; i += 4 )
bs[inx][iny+i] = B[i*ldb];
__syncthreads();
#pragma unroll
for( int i = 0; i < 16; i++, A += lda )
saxpy( A[0], &bs[i][0], c );
B += 16;
__syncthreads();
} while( B < Blast );
for( int i = 0; i < 16; i++, C += ldc )
C[0] = alpha*c[i] + beta*C[0];
}
extern "C" __global__ void vec_mat_vec_mult(const float *A, int lda,
const float *B, int ldb,
float *C, int k,
float alpha, float beta )
{
// FOR 16 threads
const int inx = threadIdx.x;
//const int iny = threadIdx.y;
const int ibx = blockIdx.x * 16;
const int iby = blockIdx.y * 16;
const int id = inx;
const float* ARow = A;
A += ibx + id;
B += ibx;
const float *Blast = B + k;
// vector de multiplicacion local
float c[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
// vector de sumatorio a lo largo de la columna
float r[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
// valor temporal
float res = 0;
// cargamos la parte del vector que toca
__shared__ float bs[16];
bs[id] = A[0];
C[id] = -1;
__syncthreads();
do
{
saxpy3( &B[0], &bs[0], c );
redux16sum(c, &res);
r[id] += res*ARow[0];
__syncthreads();
B += 16;
ARow += 16;
} while( B < Blast );
redux16sum(r, &C[ibx]);
}
extern "C" __global__ void vmSymv(const float *A, int lda,
const float *B, int ldb,
float *C, int k, int length,
float alpha, float beta )
{
// FOR 16 threads
const int inx = threadIdx.x;
const int ibx = blockIdx.x * 16;
const int iby = blockIdx.y * 16;
const int id = threadIdx.x;
const float* ARow = A;
A += ibx + id;
B += ibx + __mul24(iby+inx,ldb);
const float *Blast = ARow + k;
// vector de multiplicacion local
float c[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
// vector de sumatorio a lo largo de la columna
__shared__ float r[16];
// valor temporal
float res = 0;
// cargamos la parte del vector que toca
__shared__ float bs[16];
bs[id] = A[0];
r[id] = 0;
__syncthreads();
int steps = ldb/16;
int counter = 0;
do
{
saxpy3( &B[0], &bs[0], c );
redux16sum(c, &res);
r[id] += res*ARow[0];
__syncthreads();
B += 16 * ldb;
ARow += 16;
counter++;
} while( counter < steps );
if(id == 0)
redux16sum(r, &C[ibx]);
}
extern "C" __global__ void vmv(const float *A, int lda,
const float *B, int ldb,
float *C, int k,
float alpha, float beta )
{
// FOR 64 threads
const int id = threadIdx.x;
const int ibx = blockIdx.x * BLOCK_SIZE;
B += ibx + id*ldb;
// vector de multiplicacion local
float c[BLOCK_SIZE] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
// cargamos la parte del vector que toca
__shared__ float bs[BLOCK_SIZE];
float r[BLOCK_SIZE] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
// valor temporal
float res;
bs[id] = A[ibx + id];
__syncthreads();
const int BStep = ldb*BLOCK_SIZE;
const float* blast = A + lda;
do
{
saxpy32( &B[0], &bs[0], c, &A[id]);
redux32sum(c, &res);
r[id] += res;
B += BStep;
A += BLOCK_SIZE;
} while( A < blast );
C[ibx+id] = r[id];
}
extern "C" void ourSgemm( char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc )
{
dim3 grid( m/64, n/16 ), threads( 16, 4 );
if( transb == 'N' || transb == 'n' )
sgemmNN<<<grid, threads>>>( A, lda, B, ldb, C, ldc, k, alpha, beta );
else
sgemmNT<<<grid, threads>>>( A, lda, B, ldb, C, ldc, k, alpha, beta );
}
//
// auxiliary routines
//
void fill( float *A, int n, int maxi )
{
for( int j = 0; j < n; j++ )
A[j] = float( (rand()%(maxi*2+1)) - maxi ) / ( maxi + 1.f );
}
float diff( int m, int n, float *A, int lda, float *B, int ldb )
{
float err = 0;
for( int j = 0; j < n; j++ )
for( int i = 0; i < m; i++ )
err = max( err, fabs( A[i+j*lda] - B[i+j*ldb] ) );
return err;
}
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#include "cublas_v2.h"
#define MSize 6
#define NSize 512*32
#define IDX2C(i,j,ld) (((j)*(ld))+(i))
static __inline__ void modify (cublasHandle_t handle, float *m, int ldm, int
n, int p, int q, float alpha, float beta)
{
cublasSscal (handle, n-p, &alpha, &m[IDX2C(p,q,ldm)], ldm);
cublasSscal (handle, ldm-p, &beta, &m[IDX2C(p,q,ldm)], 1);
}
int cublas_example()
{
cudaError_t cudaStat;
cublasStatus_t stat;
cublasHandle_t handle;
int i, j;
// Matriz simetrica, column-mayor
float *B = (float*)malloc( (NSize*(NSize+1))/2*sizeof( float ) );
float *BComplete = (float*)malloc( NSize*NSize*sizeof( float ) );
// Vector
float *AVec = (float*)malloc( NSize*sizeof( float ) );
fill( BComplete, NSize*NSize, 31 );
fill( AVec, NSize, 31 );
int count = 0;
for(int i = 0; i< NSize; i++)
{
for(int j = 0; j < NSize; j++)
{
if(j <= i)
{
BComplete[i*NSize + j] = BComplete[j * NSize + i];
B[count] = BComplete[i*NSize + j];
count++;
}
}
}
// resultados
float *cuda_result = (float*)malloc( NSize*sizeof( float ) );
for(int i = 0; i< NSize; i++)
cuda_result[i]= 0;
//float *cpu_result= (float*)malloc( NSize*sizeof( float ) );
float* devPtrB, *devPtrAVec, *devPtrRes, devPtrBSym;
cudaStat = cudaMalloc ((void**)&devPtrB, NSize*NSize*sizeof(float));
cudaStat = cudaMalloc ((void**)&devPtrAVec, NSize*sizeof(float));
cudaStat = cudaMalloc ((void**)&devPtrRes, NSize*sizeof(float));
cudaStat = cudaMalloc ((void**)&devPtrBSym, ((NSize+1)*NSize)/2*sizeof(float));
if (cudaStat != cudaSuccess) {
printf ("device memory allocation failed");
return EXIT_FAILURE;
}
stat = cublasCreate(&handle);
if (stat != CUBLAS_STATUS_SUCCESS) {
printf ("CUBLAS initialization failed\n");
return EXIT_FAILURE;
}
cublasSetAtomicsMode(handle, CUBLAS_ATOMICS_ALLOWED);
stat = cublasSetMatrix (NSize, NSize, sizeof(float), BComplete, NSize, devPtrB, NSize);
//cudaStat = cudaMemcpy(&devPtrBSym, &B, ((NSize+1)*NSize)/2*sizeof(float), cudaMemcpyHostToDevice);
//cudaStat = cudaMemcpy(&devPtrB, &BComplete, NSize*NSize*sizeof(float), cudaMemcpyHostToDevice);
stat = cublasSetVector (NSize, sizeof(float), AVec, 1, devPtrAVec, 1);
stat = cublasSetVector (NSize, sizeof(float), cuda_result, 1, devPtrRes, 1);
if (stat != CUBLAS_STATUS_SUCCESS) {
printf ("data download failed");
cudaFree (devPtrAVec);
cublasDestroy(handle);
return EXIT_FAILURE;
}
float alpha = 1;
float beta = 0;
cudaEvent_t start, end;
Q( cudaEventCreate( &start ) );
Q( cudaEventCreate( &end ) );
cudaEventRecord(start, 0);
float* sum = (float*)malloc(sizeof(float));
stat = cublasSgemv( handle, CUBLAS_OP_T, NSize, NSize, &alpha, devPtrB, NSize, devPtrAVec, 1, &beta, devPtrRes, 1 );
//stat = cublasSsymv( handle, CUBLAS_FILL_MODE_LOWER, NSize, &alpha, devPtrB, NSize, devPtrAVec, 1, &beta, devPtrRes, 1 );
if (stat != CUBLAS_STATUS_SUCCESS) {
printf ("cublasSgemv failed");
cudaFree (devPtrAVec);
cublasDestroy(handle);
return EXIT_FAILURE;
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
float time;
cudaEventElapsedTime(&time, start, end);
cudaEventRecord(start, 0);
stat = cublasSdot( handle, NSize, devPtrAVec, 1, devPtrRes, 1, sum );
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
float time2;
cudaEventElapsedTime(&time2, start, end);
stat = cublasGetVector (NSize, sizeof(float), devPtrRes, 1, cuda_result, 1);
if (stat != CUBLAS_STATUS_SUCCESS) {
printf ("data upload failed");
cudaFree (devPtrAVec);
cublasDestroy(handle);
return EXIT_FAILURE;
}
cudaFree (devPtrAVec);
cublasDestroy(handle);
/*float sum = 0;
for (j = 0; j < NSize; j++) {
sum += cuda_result[j]*AVec[j];
}*/
float sumCPU = 0;
clock_t ini = clock();
for(int i = 0; i< NSize; i++)
{
float sumCPUTemp = 0;
for(int j = 0; j< NSize; j++)
{
sumCPUTemp += BComplete[i*NSize+j]*AVec[j];
}
sumCPU+= sumCPUTemp*AVec[i];
}
clock_t fin = clock();
float sumDot = 0;
clock_t ini2 = clock();
for(int ii = 0; ii< 1000; ii++)
{
for(int jj = 0; jj< NSize; jj++)
{
sumDot += BComplete[jj*NSize+ii]*AVec[jj];
}
}
clock_t fin2 = clock();
printf("Multiplicacion mxv de %d elems.\n", NSize );
printf("Sumatorio completo en CUDA: %f en %f + %f ms.\n", *sum, time, time2);
printf("Sumatorio completo en CPU: %f en %f y %f ms.\n", sumCPU, ((double)(fin-ini))/CLOCKS_PER_SEC*1000, ((double)(fin2-ini2))/CLOCKS_PER_SEC*1000);
return EXIT_SUCCESS;
}
//
// main()
//
int ejecutar_sgemmNN(int items)//( int argc, char **argv )
{
/*
int N = items;
if(N < 16)
N = 16;
//FILE* cout;
//cout = fopen("C:\\Users\\chus\\Documents\\dev\\Data\\models\\multmatrix.txt", "a");
//
// startup
//
int idevice = 0;
Q( cudaSetDevice( idevice ) );
struct cudaDeviceProp prop;
Q( cudaGetDeviceProperties( &prop, idevice ) );
printf( "\nDevice: %s, %.0f MHz clock, %.0f MB memory.\n", prop.name, prop.clockRate/1000.f, prop.totalGlobalMem/1024.f/1024.f );
cudaEvent_t start, end;
Q( cudaEventCreate( &start ) );
Q( cudaEventCreate( &end ) );
//Q( cublasInit( ) );
//
// allocate memory
//
//float *A = (float*)malloc( N*N*sizeof( float ) );
float *B = (float*)malloc( N*N*sizeof( float ) );
float *AVec = (float*)malloc( N*sizeof( float ) );
//float *C = (float*)malloc( N*N*sizeof( float ) );
//float *cublas_result = (float*)malloc( N*N*sizeof( float ) );
//float *our_result = (float*)malloc( N*N*sizeof( float ) );
float *our_result_for_sum = (float*)malloc( N*sizeof( float ) );
float *our_result= (float*)malloc( N*sizeof( float ) );
//fill( A, N*N, 31 );
fill( B, N*N, 31 );
//fill( C, N*N, 31 );
fill( AVec, N, 31 );
for(int i = 0; i< N; i++)
our_result_for_sum[i] = 0;
float *dA, *dB, *dC, *dAVec, *dCVec;
//Q( cublasAlloc( N*N, sizeof(float), (void**)&dA ) );
Q( cublasAlloc( N*N, sizeof(float), (void**)&dB ) );
//Q( cublasAlloc( N*N, sizeof(float), (void**)&dC ) );
Q( cublasAlloc( N, sizeof(float), (void**)&dAVec ) );
Q( cublasAlloc( N, sizeof(float), (void**)&dCVec ) );
//Q( cudaMemcpy( dA, A, N*N*sizeof(float), cudaMemcpyHostToDevice ) );
Q( cudaMemcpy( dB, B, N*N*sizeof(float), cudaMemcpyHostToDevice ) );
Q( cudaMemcpy( dAVec, AVec, N*sizeof(float), cudaMemcpyHostToDevice ) );
Q( cudaMemcpy( dCVec, our_result_for_sum, N*sizeof(float), cudaMemcpyHostToDevice ) );
//
// bench square matrices
//
int i = 0;
//for( int i = 0; i < 2; i++ )
{
const char transa = 'N';
const char transb = i ? 'T' : 'N';
//printf( "\ntesting sgemm( '%c', '%c', n, n, n, ... )\n\n", transa, transb );
const int nb = 64;
//printf( " n CUBLAS,Gflop/s we,Gflop/s \"error\"\n" );
int idim = 1;
//for(idim = 1; idim <= N/nb; idim = int((idim+1)*1.25) )
//{
idim = N/nb;
int dim = idim*nb;
//
// set up the parameters
//
const int m = dim;
const int n = dim;
const int k = dim;
const int lda = dim;
const int ldb = dim;
const int ldc = dim;
const float alpha = 1;
const float beta = -1;
//
// compute with CUBLAS
//
/*
Q( cublasSetMatrix( m, n, sizeof( float ), C, ldc, dC, ldc ) );
clock_t ini1 = clock();
cublasSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
cudaError_t cudaStatus = cudaDeviceSynchronize();
clock_t fin1 = clock();
Q( cublasGetError( ) );
Q( cublasGetMatrix( m, n, sizeof( float ), dC, ldc, cublas_result, ldc ) );
//
// compute with our routine
//
Q( cublasSetMatrix( m, n, sizeof( float ), C, ldc, dC, ldc ) );
clock_t ini2 = clock();
ourSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
cudaError_t cudaStatus2 = cudaDeviceSynchronize();
clock_t fin2 = clock();
Q( cublasGetMatrix( m, n, sizeof( float ), dC, ldc, our_result, ldc ) );
*/
/*
dim3 grid( m/16 , 0, 0), threads( 16 , 0, 0);
//Q( cublasSetMatrix( m, n, sizeof( float ), C, ldc, dC, ldc ) );
clock_t ini3 = clock();
vec_mat_vec_mult<<<grid, threads>>>( AVec, lda, B, ldb, dCVec, k, alpha, beta );
clock_t fin3 = clock();
cudaError_t cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess)
{
printf("cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
printf("Error String: %s\n", cudaGetErrorString(cudaStatus));
}
Q( cudaMemcpy( our_result_for_sum, dCVec, (m/16)*sizeof(float), cudaMemcpyDeviceToHost ) );
float resFinal = 0;
for(int i = 0; i< (m/16); i++)
{
resFinal += our_result_for_sum[i];
}
printf("Resultado Final en cuda: %f en %f ms\n", resFinal, ((double)(fin3-ini3))/CLOCKS_PER_SEC*1000);
//
// check the difference in results
//
//float difference = diff( m, n, cublas_result, ldc, our_result, ldc );
//
// bench cublas
//
/*
double cublas_time;
cublasSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
BEGIN_TIMING( );
cublasSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
END_TIMING( cublas_time );
double cublas_gflops = 2.*m*n*k/cublas_time/1e9;
//
// bench our routine
//
double our_time;
ourSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
BEGIN_TIMING( );
ourSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
END_TIMING( our_time );
double our_gflops = 2.*m*n*k/our_time/1e9;
*/
//
// report the results
//
/*
clock_t ini = clock();
float result = 0;
for(int i = 0; i< n; i++)
{
double tempSum = 0.0;
for(int k = 0; k< n; k++)
{
tempSum += AVec[k]*B[i*n+k];
}
result += tempSum*AVec[i];
}
clock_t fin = clock();
printf("Resultado Final en cpu: %f en %f ms\n", result, ((double)(fin-ini))/CLOCKS_PER_SEC*1000);
//printf( "TIME: %5d %11.2f %14.2f\n", n, cublas_time, our_time);
//double time1 = ((double)(fin1-ini1))/CLOCKS_PER_SEC * 1000.0;
//double time2 = ((double)(fin2-ini2))/CLOCKS_PER_SEC * 1000.0;
//printf( "TIME MINE: %d, %f, %f, CPU: %f \n", n, time1, time2, ((double)(fin-ini))/CLOCKS_PER_SEC * 1000.0);
//printf( "%5d %11.2f %14.2f %8g\n", n, cublas_gflops, our_gflops, difference );
//fprintf(cout, "%d, %f, %f, %f \n", n, time1, time2 , ((double)(fin-ini))/CLOCKS_PER_SEC * 1000.0);
//fflush(cout);
//}
}
//fclose(cout);
//
// shutdown
//
//cublasFree( dAVec );
//cublasFree( dB );
//cublasFree( dCVec );
free( AVec );
free( B );
free( our_result_for_sum );
//free( cublas_result );
free( our_result );
//Q( cublasShutdown( ) );
return 0;
*/
return 0;
}
int ejecutar_matrixVector(int items)//( int argc, char **argv )
{
int N = items;
if(N < 16)
N = 16;
//FILE* cout;
//cout = fopen("C:\\Users\\chus\\Documents\\dev\\Data\\models\\multmatrix.txt", "a");
int idevice = 0;
Q( cudaSetDevice( idevice ) );
struct cudaDeviceProp prop;
Q( cudaGetDeviceProperties( &prop, idevice ) );
printf( "\nDevice: %s, %.0f MHz clock, %.0f MB memory.\n", prop.name, prop.clockRate/1000.f, prop.totalGlobalMem/1024.f/1024.f );
cudaEvent_t start, end;
Q( cudaEventCreate( &start ) );
Q( cudaEventCreate( &end ) );
//
// allocate memory
//
printf("%d Elementos.\n", N);
// Matriz simetrica, row-mayor
float *B = (float*)malloc( (N*(N+1))/2*sizeof( float ) );
float *BComplete = (float*)malloc( N*N*sizeof( float ) );
// Vector
float *AVec = (float*)malloc( N*sizeof( float ) );
// resultados
float *cuda_result = (float*)malloc( N*sizeof( float ) );
float *cpu_result= (float*)malloc( N*sizeof( float ) );
// Inicializacion
fill( BComplete, N*N, 31 );
fill( AVec, N, 31 );
int count = 0;
for(int i = 0; i< N; i++)
{
for(int j= i; j< N; j++)
{
B[count] = BComplete[i*N + j ];
count++;
}
}
for(int i = 0; i< N; i++) cuda_result[i] = 0;
float *dA, *dB, *dAVec, *dCVec, *cuda_final_result, *cudaFinalResFloat;
cudaError_t cudaStat;
//cudaStat = cudaMalloc( (void**)&dB, (N*(N+1))/2 * sizeof(float) );
cudaStat = cudaMalloc( (void**)&dB, N*N * sizeof(float) );
cudaStat = cudaMalloc( (void**)&dAVec, N* sizeof(float) );
cudaStat = cudaMalloc( (void**)&dCVec, N* sizeof(float) );
cudaStat = cudaMalloc( (void**)&cudaFinalResFloat, sizeof(float) );
//cudaMemcpy( dB, B, (N*(N+1))/2*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( dB, BComplete, N*N*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( dAVec, AVec, N*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( dCVec, cuda_result, N*sizeof(float), cudaMemcpyHostToDevice );
// set up the parameters
const int dim = N;
const int m = dim;
const int n = dim;
const int k = dim;
const int lda = dim;
const int ldb = dim;
const int ldc = dim;
const float alpha = 1;
const float beta = 0;
// compute with CUBLAS
clock_t ini1 = clock();
//for(int tempI = 0; tempI< 1000; tempI++)
{
/*
cublasSsymv( h, CUBLAS_FILL_MODE_UPPER, N, &alpha, dB, lda, dAVec, 1, &beta, dCVec, 1 );
cudaError_t cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess)
{
printf("cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
printf("Error String: %s\n", cudaGetErrorString(cudaStatus));
}
Q( cudaMemcpy( cuda_result, dCVec, N*sizeof(float), cudaMemcpyDeviceToHost ) );
printf("Que pasa:\n %f %f %f %f %f \n", cuda_result[0], cuda_result[1], cuda_result[2], cuda_result[3], cuda_result[4]);
cublasSdot( h, N, dAVec, 1, dCVec, 1 , cudaFinalResFloat);
cudaMemcpy( &hostRes, cudaFinalResFloat, sizeof(float), cudaMemcpyDeviceToHost );
*/
dim3 grid(N/32), threads(32);
vmv<<<grid, threads>>>( dAVec, lda, dB, ldb, dCVec, k, alpha, beta );
}
cudaError_t cudaStatus = cudaDeviceSynchronize();
Q( cudaMemcpy( cuda_result, dCVec, N*sizeof(float), cudaMemcpyDeviceToHost ) );
float res001 = 0;
for(int f = 0; f < N; f++)
res001 += cuda_result[f];
clock_t fin1 = clock();
printf("Resultado Final en cuda: %f en %f ms\n", res001, ((double)(fin1-ini1))/CLOCKS_PER_SEC*1000);
float masHostRes = 0, masHostRes2 = 0;
/*
clock_t ini2 = clock();
for(int tempI = 0; tempI< 1000; tempI++)
cublasSdot( h, N, dAVec, 1, dAVec, 1, cudaFinalResFloat);
clock_t fin2 = clock();
printf("masHostRes:%f en %fms\n", masHostRes, ((double)(fin2-ini2))/CLOCKS_PER_SEC);
clock_t ini3 = clock();
for(int tempI = 0; tempI< 1000; tempI++)
{
masHostRes2 = 0;
for(int i = 0; i<N; i++)
masHostRes2 += AVec[i]*AVec[i];
}
clock_t fin3 = clock();
printf("masHostResCPU:%f en %fms\n", masHostRes2, ((double)(fin3-ini3))/CLOCKS_PER_SEC);
*/
/*
Q( cublasSetMatrix( m, n, sizeof( float ), C, ldc, dC, ldc ) );
Q( cublasGetError( ) );
Q( cublasGetMatrix( m, n, sizeof( float ), dC, ldc, cublas_result, ldc ) );
//
// compute with our routine
//
Q( cublasSetMatrix( m, n, sizeof( float ), C, ldc, dC, ldc ) );
clock_t ini2 = clock();
ourSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
cudaError_t cudaStatus2 = cudaDeviceSynchronize();
clock_t fin2 = clock();
Q( cublasGetMatrix( m, n, sizeof( float ), dC, ldc, our_result, ldc ) );
*/
/*
dim3 grid( m/16 , 0, 0), threads( 16 , 0, 0);
//Q( cublasSetMatrix( m, n, sizeof( float ), C, ldc, dC, ldc ) );
clock_t ini3 = clock();
vec_mat_vec_mult<<<grid, threads>>>( AVec, lda, B, ldb, dCVec, k, alpha, beta );
clock_t fin3 = clock();
cudaError_t cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess)
{
printf("cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
printf("Error String: %s\n", cudaGetErrorString(cudaStatus));
}
Q( cudaMemcpy( our_result_for_sum, dCVec, (m/16)*sizeof(float), cudaMemcpyDeviceToHost ) );
*/
//printf("Resultado Final en cuda: %f en %f ms\n", hostRes, ((double)(fin1-ini1))/CLOCKS_PER_SEC);
//
// check the difference in results
//
//float difference = diff( m, n, cublas_result, ldc, our_result, ldc );
//
// bench cublas
//
/*
double cublas_time;
cublasSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
BEGIN_TIMING( );
cublasSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
END_TIMING( cublas_time );
double cublas_gflops = 2.*m*n*k/cublas_time/1e9;
//
// bench our routine
//
double our_time;
ourSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
BEGIN_TIMING( );
ourSgemm( transa, transb, m, n, k, alpha, dA, lda, dB, ldb, beta, dC, ldc );
END_TIMING( our_time );
double our_gflops = 2.*m*n*k/our_time/1e9;
*/
//
// report the results
//
clock_t ini = clock();
float result = 0;
for(int i = 0; i< N; i++)
{
float tempSum = 0.0;
for(int k = 0; k< N; k++)
{
float AvecValue = AVec[k];
float BValue = BComplete[i*N+k];
float tempValue = AVec[k]*BComplete[i*N+k];
tempSum += tempValue;
}
result += tempSum*AVec[i];
}
clock_t fin = clock();
printf("Resultado Final en cpu: %f en %f ms\n", result, ((double)(fin-ini))/CLOCKS_PER_SEC*1000);
//printf( "TIME: %5d %11.2f %14.2f\n", n, cublas_time, our_time);
//double time1 = ((double)(fin1-ini1))/CLOCKS_PER_SEC * 1000.0;
//double time2 = ((double)(fin2-ini2))/CLOCKS_PER_SEC * 1000.0;
//printf( "TIME MINE: %d, %f, %f, CPU: %f \n", n, time1, time2, ((double)(fin-ini))/CLOCKS_PER_SEC * 1000.0);
//printf( "%5d %11.2f %14.2f %8g\n", n, cublas_gflops, our_gflops, difference );
//fprintf(cout, "%d, %f, %f, %f \n", n, time1, time2 , ((double)(fin-ini))/CLOCKS_PER_SEC * 1000.0);
//fflush(cout);
//}
//}
//fclose(cout);
//
// shutdown
//
//cublasDestroy(h);
cudaFree( dAVec );
cudaFree( dB );
cudaFree( dCVec );
free( AVec );
free( B );
free( cuda_result );
//free( cublas_result );
free( cpu_result );
return 0;
}
////////////////////// | #ifndef CUDA_SGEMMN_H
#define CUDA_SGEMMN_H
// Written by Vasily Volkov.
// Copyright (c) 2008, The Regents of the University of California.
// All rights reserved.
#include <stdio.h>
#include "hip/hip_runtime.h"
#define TIMER_TOLERANCE 0.1f
#define BEGIN_TIMING( ) \
{\
unsigned int n_iterations; \
for( n_iterations = 1; n_iterations < 0x80000000; n_iterations *= 2 )\
{\
Q( hipDeviceSynchronize( ) );\
Q( hipEventRecord( start, 0 ) );\
for( unsigned int iteration = 0; iteration < n_iterations; iteration++ ){
#define END_TIMING( seconds ) }\
Q( hipEventRecord( end, 0 ) );\
Q( hipEventSynchronize( end ) );\
float milliseconds;\
Q( hipEventElapsedTime( &milliseconds, start, end ) );\
seconds = milliseconds/1e3f;\
if( seconds >= TIMER_TOLERANCE )\
break;\
}\
seconds /= n_iterations;\
}
#define Q( condition ) {if( (condition) != 0 ) { printf( "\n FAILURE in %s, line %d\n", __FILE__, __LINE__ );exit( 1 );}}
int ejecutar_sgemmNN( int items/*int argc, char **argv */);
int ejecutar_matrixVector( int items/*int argc, char **argv */);
int cublas_example();
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef CUDA_SGEMMN_H
#define CUDA_SGEMMN_H
// Written by Vasily Volkov.
// Copyright (c) 2008, The Regents of the University of California.
// All rights reserved.
#include <stdio.h>
#include "hip/hip_runtime.h"
#define TIMER_TOLERANCE 0.1f
#define BEGIN_TIMING( ) \
{\
unsigned int n_iterations; \
for( n_iterations = 1; n_iterations < 0x80000000; n_iterations *= 2 )\
{\
Q( hipDeviceSynchronize( ) );\
Q( hipEventRecord( start, 0 ) );\
for( unsigned int iteration = 0; iteration < n_iterations; iteration++ ){
#define END_TIMING( seconds ) }\
Q( hipEventRecord( end, 0 ) );\
Q( hipEventSynchronize( end ) );\
float milliseconds;\
Q( hipEventElapsedTime( &milliseconds, start, end ) );\
seconds = milliseconds/1e3f;\
if( seconds >= TIMER_TOLERANCE )\
break;\
}\
seconds /= n_iterations;\
}
#define Q( condition ) {if( (condition) != 0 ) { printf( "\n FAILURE in %s, line %d\n", __FILE__, __LINE__ );exit( 1 );}}
int ejecutar_sgemmNN( int items/*int argc, char **argv */);
int ejecutar_matrixVector( int items/*int argc, char **argv */);
int cublas_example();
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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