system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* This file is copied from https://github.com/jzbonter/mc-cnn */
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void copy_fill(float *in, float *out, int size, int in_size2, int in_size3, int out_size2, int out_size3)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
int out_x = id % out_size3;
int out_y = id / out_size3;
int in_x = out_x - (out_size3 - in_size3) / 2;
int in_y = out_y - (out_size2 - in_size2) / 2;
int x = min(in_size3 - 1, max(0, in_x));
int y = min(in_size2 - 1, max(0, in_y));
out[id] = in[y * in_size3 + x];
}
} | .file "tmpxft_000a1ade_00000000-6_copy_fill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii
.type _Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii, @function
_Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9copy_fillPfS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii, .-_Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii
.globl _Z9copy_fillPfS_iiiii
.type _Z9copy_fillPfS_iiiii, @function
_Z9copy_fillPfS_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9copy_fillPfS_iiiii, .-_Z9copy_fillPfS_iiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9copy_fillPfS_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9copy_fillPfS_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* This file is copied from https://github.com/jzbonter/mc-cnn */
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void copy_fill(float *in, float *out, int size, int in_size2, int in_size3, int out_size2, int out_size3)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
int out_x = id % out_size3;
int out_y = id / out_size3;
int in_x = out_x - (out_size3 - in_size3) / 2;
int in_y = out_y - (out_size2 - in_size2) / 2;
int x = min(in_size3 - 1, max(0, in_x));
int y = min(in_size2 - 1, max(0, in_y));
out[id] = in[y * in_size3 + x];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/* This file is copied from https://github.com/jzbonter/mc-cnn */
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void copy_fill(float *in, float *out, int size, int in_size2, int in_size3, int out_size2, int out_size3)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
int out_x = id % out_size3;
int out_y = id / out_size3;
int in_x = out_x - (out_size3 - in_size3) / 2;
int in_y = out_y - (out_size2 - in_size2) / 2;
int x = min(in_size3 - 1, max(0, in_x));
int y = min(in_size2 - 1, max(0, in_y));
out[id] = in[y * in_size3 + x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* This file is copied from https://github.com/jzbonter/mc-cnn */
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void copy_fill(float *in, float *out, int size, int in_size2, int in_size3, int out_size2, int out_size3)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
int out_x = id % out_size3;
int out_y = id / out_size3;
int in_x = out_x - (out_size3 - in_size3) / 2;
int in_y = out_y - (out_size2 - in_size2) / 2;
int x = min(in_size3 - 1, max(0, in_x));
int y = min(in_size2 - 1, max(0, in_y));
out[id] = in[y * in_size3 + x];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9copy_fillPfS_iiiii
.globl _Z9copy_fillPfS_iiiii
.p2align 8
.type _Z9copy_fillPfS_iiiii,@function
_Z9copy_fillPfS_iiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x14
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s7, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s3, s7, s2
v_xor_b32_e32 v3, s2, v3
s_xor_b32 s3, s3, s2
s_sub_i32 s2, s6, s4
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s8, 0, s3
s_lshr_b32 s6, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, s6
v_rcp_iflag_f32_e32 v0, v0
s_ashr_i32 s2, s2, 1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_sub_i32 s3, s7, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_mul_lo_u32 v2, v0, s7
s_lshr_b32 s7, s3, 31
v_subrev_nc_u32_e32 v0, s2, v0
s_add_i32 s3, s3, s7
s_add_i32 s2, s4, -1
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_maxmin_i32 v4, v0, 0, s2
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_subrev_nc_u32_e32 v2, s3, v2
s_add_i32 s3, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_maxmin_i32 v0, v2, 0, s3
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, s5, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9copy_fillPfS_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9copy_fillPfS_iiiii, .Lfunc_end0-_Z9copy_fillPfS_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9copy_fillPfS_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9copy_fillPfS_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* This file is copied from https://github.com/jzbonter/mc-cnn */
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void copy_fill(float *in, float *out, int size, int in_size2, int in_size3, int out_size2, int out_size3)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
int out_x = id % out_size3;
int out_y = id / out_size3;
int in_x = out_x - (out_size3 - in_size3) / 2;
int in_y = out_y - (out_size2 - in_size2) / 2;
int x = min(in_size3 - 1, max(0, in_x));
int y = min(in_size2 - 1, max(0, in_y));
out[id] = in[y * in_size3 + x];
}
} | .text
.file "copy_fill.hip"
.globl _Z24__device_stub__copy_fillPfS_iiiii # -- Begin function _Z24__device_stub__copy_fillPfS_iiiii
.p2align 4, 0x90
.type _Z24__device_stub__copy_fillPfS_iiiii,@function
_Z24__device_stub__copy_fillPfS_iiiii: # @_Z24__device_stub__copy_fillPfS_iiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9copy_fillPfS_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__copy_fillPfS_iiiii, .Lfunc_end0-_Z24__device_stub__copy_fillPfS_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9copy_fillPfS_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9copy_fillPfS_iiiii,@object # @_Z9copy_fillPfS_iiiii
.section .rodata,"a",@progbits
.globl _Z9copy_fillPfS_iiiii
.p2align 3, 0x0
_Z9copy_fillPfS_iiiii:
.quad _Z24__device_stub__copy_fillPfS_iiiii
.size _Z9copy_fillPfS_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9copy_fillPfS_iiiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__copy_fillPfS_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9copy_fillPfS_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9copy_fillPfS_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IABS R5, c[0x0][0x180] ; /* 0x0000600000057a13 */
/* 0x000fe20000000000 */
/*0070*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0080*/ ULDC UR6, c[0x0][0x174] ; /* 0x00005d0000067ab9 */
/* 0x000fe20000000800 */
/*0090*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00a0*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ UIADD3 UR4, UR4, -UR8, URZ ; /* 0x8000000804047290 */
/* 0x000fe4000fffe03f */
/*00c0*/ UIADD3 UR5, UR9, -UR6, URZ ; /* 0x8000000609057290 */
/* 0x000fe4000fffe03f */
/*00d0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc4000f8f083f */
/*00e0*/ ULEA.HI UR5, UR5, UR5, URZ, 0x1 ; /* 0x0000000505057291 */
/* 0x000fe4000f8f083f */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011404 */
/*0100*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe40008011405 */
/*0110*/ UMOV UR7, 0x1 ; /* 0x0000000100077882 */
/* 0x000fe20000000000 */
/*0120*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0130*/ UIADD3 UR6, -UR7, UR6, URZ ; /* 0x0000000607067290 */
/* 0x000fe2000fffe13f */
/*0140*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0180*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0190*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*01a0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*01b0*/ LOP3.LUT R2, R0, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600000027a12 */
/* 0x000fc800078e3cff */
/*01c0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*01d0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01f0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*0200*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*0210*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*0220*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f45270 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0260*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0270*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff03aa12 */
/* 0x000fca00078e33ff */
/*0280*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a03 */
/*0290*/ IADD3 R3, R3, -UR5, RZ ; /* 0x8000000503037c10 */
/* 0x000fc6000fffe0ff */
/*02a0*/ IMAD R2, R5, c[0x0][0x180], R0 ; /* 0x0000600005027a24 */
/* 0x000fe200078e0200 */
/*02b0*/ IMNMX R3, RZ, R3, !PT ; /* 0x00000003ff037217 */
/* 0x000fe20007800200 */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*02d0*/ IADD3 R2, R2, -UR4, RZ ; /* 0x8000000402027c10 */
/* 0x000fe2000fffe0ff */
/*02e0*/ UIADD3 UR4, -UR7, UR8, URZ ; /* 0x0000000807047290 */
/* 0x000fe2000fffe13f */
/*02f0*/ IMNMX R3, R3, UR6, PT ; /* 0x0000000603037c17 */
/* 0x000fe4000b800200 */
/*0300*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fc80007800200 */
/*0310*/ IMNMX R2, R2, UR4, PT ; /* 0x0000000402027c17 */
/* 0x000fe2000b800200 */
/*0320*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0330*/ IMAD R2, R3, c[0x0][0x178], R2 ; /* 0x00005e0003027a24 */
/* 0x000fc800078e0202 */
/*0340*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0350*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0370*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9copy_fillPfS_iiiii
.globl _Z9copy_fillPfS_iiiii
.p2align 8
.type _Z9copy_fillPfS_iiiii,@function
_Z9copy_fillPfS_iiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x14
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s7, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s3, s7, s2
v_xor_b32_e32 v3, s2, v3
s_xor_b32 s3, s3, s2
s_sub_i32 s2, s6, s4
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s8, 0, s3
s_lshr_b32 s6, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, s6
v_rcp_iflag_f32_e32 v0, v0
s_ashr_i32 s2, s2, 1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_sub_i32 s3, s7, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_mul_lo_u32 v2, v0, s7
s_lshr_b32 s7, s3, 31
v_subrev_nc_u32_e32 v0, s2, v0
s_add_i32 s3, s3, s7
s_add_i32 s2, s4, -1
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_maxmin_i32 v4, v0, 0, s2
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_subrev_nc_u32_e32 v2, s3, v2
s_add_i32 s3, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_maxmin_i32 v0, v2, 0, s3
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, s5, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9copy_fillPfS_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9copy_fillPfS_iiiii, .Lfunc_end0-_Z9copy_fillPfS_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9copy_fillPfS_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9copy_fillPfS_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a1ade_00000000-6_copy_fill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii
.type _Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii, @function
_Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9copy_fillPfS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii, .-_Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii
.globl _Z9copy_fillPfS_iiiii
.type _Z9copy_fillPfS_iiiii, @function
_Z9copy_fillPfS_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z35__device_stub__Z9copy_fillPfS_iiiiiPfS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9copy_fillPfS_iiiii, .-_Z9copy_fillPfS_iiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9copy_fillPfS_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9copy_fillPfS_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copy_fill.hip"
.globl _Z24__device_stub__copy_fillPfS_iiiii # -- Begin function _Z24__device_stub__copy_fillPfS_iiiii
.p2align 4, 0x90
.type _Z24__device_stub__copy_fillPfS_iiiii,@function
_Z24__device_stub__copy_fillPfS_iiiii: # @_Z24__device_stub__copy_fillPfS_iiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9copy_fillPfS_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__copy_fillPfS_iiiii, .Lfunc_end0-_Z24__device_stub__copy_fillPfS_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9copy_fillPfS_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9copy_fillPfS_iiiii,@object # @_Z9copy_fillPfS_iiiii
.section .rodata,"a",@progbits
.globl _Z9copy_fillPfS_iiiii
.p2align 3, 0x0
_Z9copy_fillPfS_iiiii:
.quad _Z24__device_stub__copy_fillPfS_iiiii
.size _Z9copy_fillPfS_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9copy_fillPfS_iiiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__copy_fillPfS_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9copy_fillPfS_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | int main() {
int a = 10;
#pragma omp parallel for
for (int i = 0; i < 10; ++i);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | int main() {
int a = 10;
#pragma omp parallel for
for (int i = 0; i < 10; ++i);
return 0;
} | .file "tmpxft_001296a1_00000000-6_t.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | int main() {
int a = 10;
#pragma omp parallel for
for (int i = 0; i < 10; ++i);
return 0;
} | #include <hip/hip_runtime.h>
int main() {
int a = 10;
#pragma omp parallel for
for (int i = 0; i < 10; ++i);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
int main() {
int a = 10;
#pragma omp parallel for
for (int i = 0; i < 10; ++i);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
int main() {
int a = 10;
#pragma omp parallel for
for (int i = 0; i < 10; ++i);
return 0;
} | .text
.file "t.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001296a1_00000000-6_t.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "t.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
__device__ float devData;
__global__ void checkGlobalVariable()
{
printf("Device: The value of global variable is %f\n", devData);
devData += 2.0;
}
int main()
{
float value = 3.14f;
cudaMemcpyToSymbol(&devData, &value, sizeof(value));
printf("Host: copied %f to the global variable\n", value);
checkGlobalVariable<<<1, 1 >>> ();
cudaMemcpyFromSymbol(&value, &devData, sizeof(value));
printf("Host: Value changed by kernel to %f\n", value);
cudaDeviceReset();
system("Pause");
return 0;
} | code for sm_80
Function : _Z19checkGlobalVariablev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff107624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff117624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0050*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fc600078e00ff */
/*00a0*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e220000000a00 */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00c0*/ F2F.F64.F32 R2, R0 ; /* 0x0000000000027310 */
/* 0x004e640000201800 */
/*00d0*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0023ea0000100a00 */
/*00e0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*00f0*/ MOV R11, 0x160 ; /* 0x00000160000b7802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R20, 0xe0 ; /* 0x000000e000147802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0130*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0140*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0150*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0160*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FADD R3, R0, 2 ; /* 0x4000000000037421 */
/* 0x004fca0000000000 */
/*0180*/ STG.E [R16.64], R3 ; /* 0x0000000310007986 */
/* 0x000fe2000c101924 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
__device__ float devData;
__global__ void checkGlobalVariable()
{
printf("Device: The value of global variable is %f\n", devData);
devData += 2.0;
}
int main()
{
float value = 3.14f;
cudaMemcpyToSymbol(&devData, &value, sizeof(value));
printf("Host: copied %f to the global variable\n", value);
checkGlobalVariable<<<1, 1 >>> ();
cudaMemcpyFromSymbol(&value, &devData, sizeof(value));
printf("Host: Value changed by kernel to %f\n", value);
cudaDeviceReset();
system("Pause");
return 0;
} | .file "tmpxft_000030c1_00000000-6_SaticGlobalMemory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z19checkGlobalVariablevv
.type _Z38__device_stub__Z19checkGlobalVariablevv, @function
_Z38__device_stub__Z19checkGlobalVariablevv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z19checkGlobalVariablev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z38__device_stub__Z19checkGlobalVariablevv, .-_Z38__device_stub__Z19checkGlobalVariablevv
.globl _Z19checkGlobalVariablev
.type _Z19checkGlobalVariablev, @function
_Z19checkGlobalVariablev:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z19checkGlobalVariablevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z19checkGlobalVariablev, .-_Z19checkGlobalVariablev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Host: copied %f to the global variable\n"
.align 8
.LC2:
.string "Host: Value changed by kernel to %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Pause"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0x4048f5c3, 8(%rsp)
leaq _ZL7devData(%rip), %rax
movq %rax, 24(%rsp)
leaq 8(%rsp), %rsi
leaq 24(%rsp), %rdi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
call cudaMemcpyToSymbol@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq _ZL7devData(%rip), %rax
movq %rax, 24(%rsp)
leaq 24(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
call cudaMemcpyFromSymbol@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
leaq .LC3(%rip), %rdi
call system@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z38__device_stub__Z19checkGlobalVariablevv
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z19checkGlobalVariablev"
.LC5:
.string "devData"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19checkGlobalVariablev(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7devData(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7devData
.comm _ZL7devData,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
__device__ float devData;
__global__ void checkGlobalVariable()
{
printf("Device: The value of global variable is %f\n", devData);
devData += 2.0;
}
int main()
{
float value = 3.14f;
cudaMemcpyToSymbol(&devData, &value, sizeof(value));
printf("Host: copied %f to the global variable\n", value);
checkGlobalVariable<<<1, 1 >>> ();
cudaMemcpyFromSymbol(&value, &devData, sizeof(value));
printf("Host: Value changed by kernel to %f\n", value);
cudaDeviceReset();
system("Pause");
return 0;
} | #include "hip/hip_runtime.h"
#include <iostream>
#include <stdio.h>
__device__ float devData;
__global__ void checkGlobalVariable()
{
printf("Device: The value of global variable is %f\n", devData);
devData += 2.0;
}
int main()
{
float value = 3.14f;
hipMemcpyToSymbol(HIP_SYMBOL(&devData), &value, sizeof(value));
printf("Host: copied %f to the global variable\n", value);
checkGlobalVariable<<<1, 1 >>> ();
hipMemcpyFromSymbol(&value, HIP_SYMBOL(&devData), sizeof(value));
printf("Host: Value changed by kernel to %f\n", value);
hipDeviceReset();
system("Pause");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <stdio.h>
__device__ float devData;
__global__ void checkGlobalVariable()
{
printf("Device: The value of global variable is %f\n", devData);
devData += 2.0;
}
int main()
{
float value = 3.14f;
hipMemcpyToSymbol(HIP_SYMBOL(&devData), &value, sizeof(value));
printf("Host: copied %f to the global variable\n", value);
checkGlobalVariable<<<1, 1 >>> ();
hipMemcpyFromSymbol(&value, HIP_SYMBOL(&devData), sizeof(value));
printf("Host: Value changed by kernel to %f\n", value);
hipDeviceReset();
system("Pause");
return 0;
} | .text
.file "SaticGlobalMemory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z34__device_stub__checkGlobalVariablev # -- Begin function _Z34__device_stub__checkGlobalVariablev
.p2align 4, 0x90
.type _Z34__device_stub__checkGlobalVariablev,@function
_Z34__device_stub__checkGlobalVariablev: # @_Z34__device_stub__checkGlobalVariablev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19checkGlobalVariablev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z34__device_stub__checkGlobalVariablev, .Lfunc_end0-_Z34__device_stub__checkGlobalVariablev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $1078523331, 12(%rsp) # imm = 0x4048F5C3
movq $devData, 16(%rsp)
leaq 16(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19checkGlobalVariablev, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq $devData, 16(%rsp)
leaq 12(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $4, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
callq hipDeviceReset
movl $.L.str.2, %edi
callq system
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19checkGlobalVariablev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $devData, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type devData,@object # @devData
.local devData
.comm devData,4,4
.type _Z19checkGlobalVariablev,@object # @_Z19checkGlobalVariablev
.section .rodata,"a",@progbits
.globl _Z19checkGlobalVariablev
.p2align 3, 0x0
_Z19checkGlobalVariablev:
.quad _Z34__device_stub__checkGlobalVariablev
.size _Z19checkGlobalVariablev, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host: copied %f to the global variable\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Host: Value changed by kernel to %f\n"
.size .L.str.1, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Pause"
.size .L.str.2, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19checkGlobalVariablev"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "devData"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__checkGlobalVariablev
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym devData
.addrsig_sym _Z19checkGlobalVariablev
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000030c1_00000000-6_SaticGlobalMemory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z19checkGlobalVariablevv
.type _Z38__device_stub__Z19checkGlobalVariablevv, @function
_Z38__device_stub__Z19checkGlobalVariablevv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z19checkGlobalVariablev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z38__device_stub__Z19checkGlobalVariablevv, .-_Z38__device_stub__Z19checkGlobalVariablevv
.globl _Z19checkGlobalVariablev
.type _Z19checkGlobalVariablev, @function
_Z19checkGlobalVariablev:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z19checkGlobalVariablevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z19checkGlobalVariablev, .-_Z19checkGlobalVariablev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Host: copied %f to the global variable\n"
.align 8
.LC2:
.string "Host: Value changed by kernel to %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Pause"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0x4048f5c3, 8(%rsp)
leaq _ZL7devData(%rip), %rax
movq %rax, 24(%rsp)
leaq 8(%rsp), %rsi
leaq 24(%rsp), %rdi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
call cudaMemcpyToSymbol@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq _ZL7devData(%rip), %rax
movq %rax, 24(%rsp)
leaq 24(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
call cudaMemcpyFromSymbol@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
leaq .LC3(%rip), %rdi
call system@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z38__device_stub__Z19checkGlobalVariablevv
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z19checkGlobalVariablev"
.LC5:
.string "devData"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19checkGlobalVariablev(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7devData(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7devData
.comm _ZL7devData,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SaticGlobalMemory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z34__device_stub__checkGlobalVariablev # -- Begin function _Z34__device_stub__checkGlobalVariablev
.p2align 4, 0x90
.type _Z34__device_stub__checkGlobalVariablev,@function
_Z34__device_stub__checkGlobalVariablev: # @_Z34__device_stub__checkGlobalVariablev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19checkGlobalVariablev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z34__device_stub__checkGlobalVariablev, .Lfunc_end0-_Z34__device_stub__checkGlobalVariablev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $1078523331, 12(%rsp) # imm = 0x4048F5C3
movq $devData, 16(%rsp)
leaq 16(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19checkGlobalVariablev, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq $devData, 16(%rsp)
leaq 12(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $4, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
callq hipDeviceReset
movl $.L.str.2, %edi
callq system
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19checkGlobalVariablev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $devData, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type devData,@object # @devData
.local devData
.comm devData,4,4
.type _Z19checkGlobalVariablev,@object # @_Z19checkGlobalVariablev
.section .rodata,"a",@progbits
.globl _Z19checkGlobalVariablev
.p2align 3, 0x0
_Z19checkGlobalVariablev:
.quad _Z34__device_stub__checkGlobalVariablev
.size _Z19checkGlobalVariablev, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host: copied %f to the global variable\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Host: Value changed by kernel to %f\n"
.size .L.str.1, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Pause"
.size .L.str.2, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19checkGlobalVariablev"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "devData"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__checkGlobalVariablev
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym devData
.addrsig_sym _Z19checkGlobalVariablev
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuda_graph_avgpool_bprop(float* gradInput, const float *gradOutput, const float* clusters, const int nClusters, const int poolsize, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
}
}
__syncthreads();
if (tidx < poolsize) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)(clusters[i*poolsize+tidx]-1)] += gradOutput[i]/poolsize;
}
}
/*
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[tidx*poolsize+j]-1)] += gradOutput[tidx]/poolsize;
__syncthreads();
}
*/
__syncthreads();
/*
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
// int idx = tidx + i*blockDim.x;
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[i*poolsize+j]-1)] += gradOutput[i]/poolsize;
}
}
}
*/
/*
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)clusters[idx*poolsize+j]] += gradOutput_data[idx]/poolsize;
}
}
}
*/
} | .file "tmpxft_00172c58_00000000-6_cuda_graph_avgpool_bprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii
.type _Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii, @function
_Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii, .-_Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii
.globl _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.type _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, @function
_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, .-_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuda_graph_avgpool_bprop(float* gradInput, const float *gradOutput, const float* clusters, const int nClusters, const int poolsize, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
}
}
__syncthreads();
if (tidx < poolsize) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)(clusters[i*poolsize+tidx]-1)] += gradOutput[i]/poolsize;
}
}
/*
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[tidx*poolsize+j]-1)] += gradOutput[tidx]/poolsize;
__syncthreads();
}
*/
__syncthreads();
/*
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
// int idx = tidx + i*blockDim.x;
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[i*poolsize+j]-1)] += gradOutput[i]/poolsize;
}
}
}
*/
/*
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)clusters[idx*poolsize+j]] += gradOutput_data[idx]/poolsize;
}
}
}
*/
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_graph_avgpool_bprop(float* gradInput, const float *gradOutput, const float* clusters, const int nClusters, const int poolsize, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
}
}
__syncthreads();
if (tidx < poolsize) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)(clusters[i*poolsize+tidx]-1)] += gradOutput[i]/poolsize;
}
}
/*
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[tidx*poolsize+j]-1)] += gradOutput[tidx]/poolsize;
__syncthreads();
}
*/
__syncthreads();
/*
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
// int idx = tidx + i*blockDim.x;
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[i*poolsize+j]-1)] += gradOutput[i]/poolsize;
}
}
}
*/
/*
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)clusters[idx*poolsize+j]] += gradOutput_data[idx]/poolsize;
}
}
}
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_graph_avgpool_bprop(float* gradInput, const float *gradOutput, const float* clusters, const int nClusters, const int poolsize, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
}
}
__syncthreads();
if (tidx < poolsize) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)(clusters[i*poolsize+tidx]-1)] += gradOutput[i]/poolsize;
}
}
/*
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[tidx*poolsize+j]-1)] += gradOutput[tidx]/poolsize;
__syncthreads();
}
*/
__syncthreads();
/*
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
// int idx = tidx + i*blockDim.x;
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[i*poolsize+j]-1)] += gradOutput[i]/poolsize;
}
}
}
*/
/*
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)clusters[idx*poolsize+j]] += gradOutput_data[idx]/poolsize;
}
}
}
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.globl _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.p2align 8
.type _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii,@function
_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x24
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mul_i32 s8, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s2, s2, s8
s_addc_u32 s3, s3, s9
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_5
s_load_b32 s5, s[0:1], 0x34
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s7, s5, 2
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v3, s7, v3
v_add_nc_u32_e32 v1, s5, v1
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mov_b32 s8, exec_lo
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
s_branch .LBB0_2
.LBB0_5:
s_load_b32 s4, s[0:1], 0x1c
s_cmp_gt_i32 s6, 0
s_waitcnt lgkmcnt(0)
s_cselect_b32 s5, -1, 0
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_and_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s5
s_cbranch_execz .LBB0_8
s_clause 0x2
s_load_b32 s5, s[0:1], 0x20
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_mov_b32 s11, 0
v_cvt_f32_i32_e32 v2, s4
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s15, s5
v_add_co_u32 v0, s5, s8, v0
s_lshl_b64 s[10:11], s[10:11], 2
v_add_co_ci_u32_e64 v1, null, s9, 0, s5
s_add_u32 s8, s0, s10
s_addc_u32 s9, s1, s11
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_7:
global_load_b32 v4, v[0:1], off
global_load_b32 v6, v3, s[2:3]
s_add_i32 s6, s6, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s6, 0
s_waitcnt vmcnt(0)
v_div_scale_f32 v8, null, v2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v8, v9, 1.0
v_dual_add_f32 v4, -1.0, v4 :: v_dual_fmac_f32 v9, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v4
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_div_scale_f32 v11, vcc_lo, v6, v2, v6
global_load_b32 v7, v[4:5], off
v_mul_f32_e32 v10, v11, v9
v_fma_f32 v12, -v8, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v12, v9
v_fma_f32 v8, -v8, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v8, v8, v9, v10
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f32 v6, v8, v2, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_7
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, .Lfunc_end0-_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_graph_avgpool_bprop(float* gradInput, const float *gradOutput, const float* clusters, const int nClusters, const int poolsize, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
}
}
__syncthreads();
if (tidx < poolsize) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)(clusters[i*poolsize+tidx]-1)] += gradOutput[i]/poolsize;
}
}
/*
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[tidx*poolsize+j]-1)] += gradOutput[tidx]/poolsize;
__syncthreads();
}
*/
__syncthreads();
/*
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
// int idx = tidx + i*blockDim.x;
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)(clusters[i*poolsize+j]-1)] += gradOutput[i]/poolsize;
}
}
}
*/
/*
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
for (int j = 0; j < poolsize; ++j) {
gradInput[(int)clusters[idx*poolsize+j]] += gradOutput_data[idx]/poolsize;
}
}
}
*/
} | .text
.file "cuda_graph_avgpool_bprop.hip"
.globl _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii # -- Begin function _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.p2align 4, 0x90
.type _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii,@function
_Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii: # @_Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii, .Lfunc_end0-_Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii,@object # @_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.section .rodata,"a",@progbits
.globl _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.p2align 3, 0x0
_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii:
.quad _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.size _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00172c58_00000000-6_cuda_graph_avgpool_bprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii
.type _Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii, @function
_Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii, .-_Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii
.globl _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.type _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, @function
_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z24cuda_graph_avgpool_bpropPfPKfS1_iiiiPfPKfS1_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, .-_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_graph_avgpool_bprop.hip"
.globl _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii # -- Begin function _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.p2align 4, 0x90
.type _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii,@function
_Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii: # @_Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii, .Lfunc_end0-_Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii,@object # @_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.section .rodata,"a",@progbits
.globl _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.p2align 3, 0x0
_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii:
.quad _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.size _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24cuda_graph_avgpool_bpropPfPKfS1_iiii"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__cuda_graph_avgpool_bpropPfPKfS1_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24cuda_graph_avgpool_bpropPfPKfS1_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define CUDA_CALL(...) \
do { \
cudaError_t err = __VA_ARGS__; \
if (err != cudaSuccess) \
{ \
printf("CUDA ERROR: %s: %s\n", \
cudaGetErrorName(err), cudaGetErrorString(err)); \
return err; \
} \
} while (false)
int main()
{
int selected_device;
CUDA_CALL(cudaGetDevice(&selected_device));
cudaDeviceProp device_prop;
CUDA_CALL(cudaGetDeviceProperties(&device_prop, selected_device));
FILE * output = fopen("sm", "w");
fprintf(output, "%d%d\n", device_prop.major, device_prop.minor);
fclose(output);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define CUDA_CALL(...) \
do { \
cudaError_t err = __VA_ARGS__; \
if (err != cudaSuccess) \
{ \
printf("CUDA ERROR: %s: %s\n", \
cudaGetErrorName(err), cudaGetErrorString(err)); \
return err; \
} \
} while (false)
int main()
{
int selected_device;
CUDA_CALL(cudaGetDevice(&selected_device));
cudaDeviceProp device_prop;
CUDA_CALL(cudaGetDeviceProperties(&device_prop, selected_device));
FILE * output = fopen("sm", "w");
fprintf(output, "%d%d\n", device_prop.major, device_prop.minor);
fclose(output);
} | .file "tmpxft_00013089_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA ERROR: %s: %s\n"
.LC1:
.string "w"
.LC2:
.string "sm"
.LC3:
.string "%d%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
jne .L9
leaq 16(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L10
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movl 380(%rsp), %r8d
movl 376(%rsp), %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
movq %rbp, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
jmp .L3
.L10:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
movq %rbp, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
jmp .L3
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define CUDA_CALL(...) \
do { \
cudaError_t err = __VA_ARGS__; \
if (err != cudaSuccess) \
{ \
printf("CUDA ERROR: %s: %s\n", \
cudaGetErrorName(err), cudaGetErrorString(err)); \
return err; \
} \
} while (false)
int main()
{
int selected_device;
CUDA_CALL(cudaGetDevice(&selected_device));
cudaDeviceProp device_prop;
CUDA_CALL(cudaGetDeviceProperties(&device_prop, selected_device));
FILE * output = fopen("sm", "w");
fprintf(output, "%d%d\n", device_prop.major, device_prop.minor);
fclose(output);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define CUDA_CALL(...) \
do { \
hipError_t err = __VA_ARGS__; \
if (err != hipSuccess) \
{ \
printf("CUDA ERROR: %s: %s\n", \
hipGetErrorName(err), hipGetErrorString(err)); \
return err; \
} \
} while (false)
int main()
{
int selected_device;
CUDA_CALL(hipGetDevice(&selected_device));
hipDeviceProp_t device_prop;
CUDA_CALL(hipGetDeviceProperties(&device_prop, selected_device));
FILE * output = fopen("sm", "w");
fprintf(output, "%d%d\n", device_prop.major, device_prop.minor);
fclose(output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define CUDA_CALL(...) \
do { \
hipError_t err = __VA_ARGS__; \
if (err != hipSuccess) \
{ \
printf("CUDA ERROR: %s: %s\n", \
hipGetErrorName(err), hipGetErrorString(err)); \
return err; \
} \
} while (false)
int main()
{
int selected_device;
CUDA_CALL(hipGetDevice(&selected_device));
hipDeviceProp_t device_prop;
CUDA_CALL(hipGetDeviceProperties(&device_prop, selected_device));
FILE * output = fopen("sm", "w");
fprintf(output, "%d%d\n", device_prop.major, device_prop.minor);
fclose(output);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define CUDA_CALL(...) \
do { \
hipError_t err = __VA_ARGS__; \
if (err != hipSuccess) \
{ \
printf("CUDA ERROR: %s: %s\n", \
hipGetErrorName(err), hipGetErrorString(err)); \
return err; \
} \
} while (false)
int main()
{
int selected_device;
CUDA_CALL(hipGetDevice(&selected_device));
hipDeviceProp_t device_prop;
CUDA_CALL(hipGetDeviceProperties(&device_prop, selected_device));
FILE * output = fopen("sm", "w");
fprintf(output, "%d%d\n", device_prop.major, device_prop.minor);
fclose(output);
} | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl %eax, %ebp
testl %eax, %eax
je .LBB0_1
# %bb.2:
movl %ebp, %edi
callq hipGetErrorName
movq %rax, %rbx
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl %ebp, %ebx
testl %ebp, %ebp
jne .LBB0_8
jmp .LBB0_4
.LBB0_1:
xorl %ebx, %ebx
testl %ebp, %ebp
jne .LBB0_8
.LBB0_4:
movl 12(%rsp), %esi
leaq 16(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl %eax, %ebp
testl %eax, %eax
je .LBB0_6
# %bb.5:
movl %ebp, %edi
callq hipGetErrorName
movq %rax, %rbx
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl %ebp, %ebx
.LBB0_6:
testl %ebp, %ebp
jne .LBB0_8
# %bb.7:
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
movl 376(%rsp), %edx
movl 380(%rsp), %ecx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movq %r14, %rdi
callq fclose
.LBB0_8:
movl %ebx, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA ERROR: %s: %s\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "sm"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "w"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d%d\n"
.size .L.str.3, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00013089_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA ERROR: %s: %s\n"
.LC1:
.string "w"
.LC2:
.string "sm"
.LC3:
.string "%d%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
jne .L9
leaq 16(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L10
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movl 380(%rsp), %r8d
movl 376(%rsp), %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
movq %rbp, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
jmp .L3
.L10:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
movq %rbp, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
jmp .L3
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl %eax, %ebp
testl %eax, %eax
je .LBB0_1
# %bb.2:
movl %ebp, %edi
callq hipGetErrorName
movq %rax, %rbx
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl %ebp, %ebx
testl %ebp, %ebp
jne .LBB0_8
jmp .LBB0_4
.LBB0_1:
xorl %ebx, %ebx
testl %ebp, %ebp
jne .LBB0_8
.LBB0_4:
movl 12(%rsp), %esi
leaq 16(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl %eax, %ebp
testl %eax, %eax
je .LBB0_6
# %bb.5:
movl %ebp, %edi
callq hipGetErrorName
movq %rax, %rbx
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl %ebp, %ebx
.LBB0_6:
testl %ebp, %ebp
jne .LBB0_8
# %bb.7:
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
movl 376(%rsp), %edx
movl 380(%rsp), %ecx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movq %r14, %rdi
callq fclose
.LBB0_8:
movl %ebx, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA ERROR: %s: %s\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "sm"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "w"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d%d\n"
.size .L.str.3, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gemm(float* A, float* B, float* C, int m, int n, int k) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Each thread block computes one sub-matrix Csub of C
float* Csub = &C[BLOCK_SIZE * k * blockRow + BLOCK_SIZE * blockCol];
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Each thread computes one element of Csub
// by accumulating results into Cvalue
// block_size = 16 -> 256 threads, one per Csub element
float Cvalue = 0.0;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int i = 0; i < (n / BLOCK_SIZE); ++i) {
// Get sub-matrix Asub of A
float* Asub = &A[BLOCK_SIZE * blockRow * n + BLOCK_SIZE * i];
// Get sub-matrix Bsub of B
float* Bsub = &B[BLOCK_SIZE * k * i + BLOCK_SIZE * blockCol];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = Asub[row*n+col];
Bs[row][col] = Bsub[row*k+col];
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int j = 0; j < BLOCK_SIZE; ++j) Cvalue += As[row][j] * Bs[j][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
if(col + blockCol* BLOCK_SIZE< k && row + blockRow* BLOCK_SIZE< m) Csub[row*k+col] = Cvalue;
} | code for sm_80
Function : _Z4gemmPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.GE.AND P1, PT, R4, 0x10, PT ; /* 0x000000100400780c */
/* 0x000fe20003f26270 */
/*0080*/ USHF.L.U32 UR5, UR5, 0x4, URZ ; /* 0x0000000405057899 */
/* 0x000fe2000800063f */
/*0090*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000ea80000002200 */
/*00a0*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000ea20000002600 */
/*00b0*/ IMAD.SHL.U32 R13, R13, 0x10, RZ ; /* 0x000000100d0d7824 */
/* 0x001fca00078e00ff */
/*00c0*/ IADD3 R5, R13, R0, RZ ; /* 0x000000000d057210 */
/* 0x002fc80007ffe0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe40003f06270 */
/*00e0*/ LEA R6, R2, R3, 0x4 ; /* 0x0000000302067211 */
/* 0x004fc800078e20ff */
/*00f0*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x000fe20000706670 */
/*0100*/ @!P1 BRA 0x560 ; /* 0x0000045000009947 */
/* 0x000ff60003800000 */
/*0110*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ; /* 0x0000001fff047819 */
/* 0x000fe20000011404 */
/*0120*/ IMAD R19, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002137a24 */
/* 0x000fe200078e02ff */
/*0130*/ SHF.L.U32 R15, R3.reuse, 0x6, RZ ; /* 0x00000006030f7819 */
/* 0x040fe200000006ff */
/*0140*/ IMAD R14, R3.reuse, c[0x0][0x17c], R0.reuse ; /* 0x00005f00030e7a24 */
/* 0x140fe200078e0200 */
/*0150*/ LEA.HI R4, R4, c[0x0][0x17c], RZ, 0x4 ; /* 0x00005f0004047a11 */
/* 0x000fe200078f20ff */
/*0160*/ IMAD R17, R3, c[0x0][0x180], R0 ; /* 0x0000600003117a24 */
/* 0x000fe200078e0200 */
/*0170*/ MOV R12, R13 ; /* 0x0000000d000c7202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0190*/ LEA R18, R0, R15, 0x2 ; /* 0x0000000f00127211 */
/* 0x000fe200078e10ff */
/*01a0*/ IMAD.SHL.U32 R19, R19, 0x10, RZ ; /* 0x0000001013137824 */
/* 0x000fe200078e00ff */
/*01b0*/ SHF.R.S32.HI R16, RZ, 0x4, R4 ; /* 0x00000004ff107819 */
/* 0x000fe20000011404 */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*01d0*/ SHF.R.S32.HI R4, RZ, 0x1f, R12 ; /* 0x0000001fff047819 */
/* 0x000fe4000001140c */
/*01e0*/ IADD3 R6, P2, R17, R12, RZ ; /* 0x0000000c11067210 */
/* 0x000fc40007f5e0ff */
/*01f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R19 ; /* 0x0000001fff057819 */
/* 0x000fe40000011413 */
/*0200*/ IADD3 R8, P1, R14.reuse, R19, RZ ; /* 0x000000130e087210 */
/* 0x040fe40007f3e0ff */
/*0210*/ LEA.HI.X.SX32 R7, R17, R4, 0x1, P2 ; /* 0x0000000411077211 */
/* 0x000fe400010f0eff */
/*0220*/ LEA.HI.X.SX32 R5, R14, R5, 0x1, P1 ; /* 0x000000050e057211 */
/* 0x000fe400008f0eff */
/*0230*/ LEA R24, P2, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006187a11 */
/* 0x000fe400078410ff */
/*0240*/ LEA R4, P1, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008047a11 */
/* 0x000fc400078210ff */
/*0250*/ LEA.HI.X R25, R6, c[0x0][0x16c], R7, 0x2, P2 ; /* 0x00005b0006197a11 */
/* 0x000fe400010f1407 */
/*0260*/ LEA.HI.X R5, R8, c[0x0][0x164], R5, 0x2, P1 ; /* 0x0000590008057a11 */
/* 0x000fc800008f1405 */
/*0270*/ LDG.E R25, [R24.64] ; /* 0x0000000618197981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R29, [R4.64] ; /* 0x00000006041d7981 */
/* 0x000ee2000c1e1900 */
/*0290*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*02a0*/ ISETP.LE.AND P1, PT, R16, UR4, PT ; /* 0x0000000410007c0c */
/* 0x000fe4000bf23270 */
/*02b0*/ IADD3 R12, R12, UR5, RZ ; /* 0x000000050c0c7c10 */
/* 0x000fe4000fffe0ff */
/*02c0*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ STS [R18+0x400], R25 ; /* 0x0004001912007388 */
/* 0x004fe80000000800 */
/*02e0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x008fe80000000800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ LDS R22, [R0.X4+0x400] ; /* 0x0004000000167984 */
/* 0x000fe80000004800 */
/*0310*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*0320*/ LDS R28, [R0.X4+0x440] ; /* 0x00044000001c7984 */
/* 0x000e680000004800 */
/*0330*/ LDS R27, [R0.X4+0x480] ; /* 0x00048000001b7984 */
/* 0x000ea80000004800 */
/*0340*/ LDS R26, [R0.X4+0x4c0] ; /* 0x0004c000001a7984 */
/* 0x000ee80000004800 */
/*0350*/ LDS R23, [R0.X4+0x500] ; /* 0x0005000000177984 */
/* 0x000fe80000004800 */
/*0360*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*0370*/ LDS R20, [R0.X4+0x540] ; /* 0x0005400000147984 */
/* 0x000f680000004800 */
/*0380*/ LDS R25, [R0.X4+0x580] ; /* 0x0005800000197984 */
/* 0x000f680000004800 */
/*0390*/ LDS R24, [R0.X4+0x640] ; /* 0x0006400000187984 */
/* 0x000fe20000004800 */
/*03a0*/ FFMA R8, R22, R8, R21 ; /* 0x0000000816087223 */
/* 0x001fc60000000015 */
/*03b0*/ LDS R22, [R0.X4+0x5c0] ; /* 0x0005c00000167984 */
/* 0x000e220000004800 */
/*03c0*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc60000000008 */
/*03d0*/ LDS R21, [R0.X4+0x600] ; /* 0x0006000000157984 */
/* 0x000fe20000004800 */
/*03e0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*03f0*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0400*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e640000000c00 */
/*0410*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0420*/ LDS R23, [R0.X4+0x680] ; /* 0x0006800000177984 */
/* 0x000ea40000004800 */
/*0430*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0440*/ LDS R20, [R0.X4+0x6c0] ; /* 0x0006c00000147984 */
/* 0x000ee40000004800 */
/*0450*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0460*/ LDS R25, [R0.X4+0x700] ; /* 0x0007000000197984 */
/* 0x000fe40000004800 */
/*0470*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x001fe40000000004 */
/*0480*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000e280000000c00 */
/*0490*/ LDS R22, [R0.X4+0x740] ; /* 0x0007400000167984 */
/* 0x000f220000004800 */
/*04a0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x002fc6000000001a */
/*04b0*/ LDS R21, [R0.X4+0x780] ; /* 0x0007800000157984 */
/* 0x000e680000004800 */
/*04c0*/ LDS R8, [R0.X4+0x7c0] ; /* 0x0007c00000087984 */
/* 0x000f620000004800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc8000000001a */
/*04e0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x004fc80000000009 */
/*04f0*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x008fc80000000009 */
/*0500*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x001fc80000000009 */
/*0510*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fc80000000004 */
/*0520*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x002fc80000000004 */
/*0530*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @!P1 BRA 0x1d0 ; /* 0xfffffc7000009947 */
/* 0x000fea000383ffff */
/*0560*/ IMAD R2, R2, UR5, R13 ; /* 0x0000000502027c24 */
/* 0x000fe2000f8e020d */
/*0570*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*0580*/ IMAD R5, R3, c[0x0][0x180], R0 ; /* 0x0000600003057a24 */
/* 0x000fe200078e0200 */
/*0590*/ SHF.R.S32.HI R0, RZ, 0x1f, R2 ; /* 0x0000001fff007819 */
/* 0x000fc80000011402 */
/*05a0*/ IADD3 R3, P0, R5, R2, RZ ; /* 0x0000000205037210 */
/* 0x000fc80007f1e0ff */
/*05b0*/ LEA.HI.X.SX32 R0, R5, R0, 0x1, P0 ; /* 0x0000000005007211 */
/* 0x000fe400000f0eff */
/*05c0*/ LEA R2, P0, R3, c[0x0][0x170], 0x2 ; /* 0x00005c0003027a11 */
/* 0x000fc800078010ff */
/*05d0*/ LEA.HI.X R3, R3, c[0x0][0x174], R0, 0x2, P0 ; /* 0x00005d0003037a11 */
/* 0x000fca00000f1400 */
/*05e0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gemm(float* A, float* B, float* C, int m, int n, int k) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Each thread block computes one sub-matrix Csub of C
float* Csub = &C[BLOCK_SIZE * k * blockRow + BLOCK_SIZE * blockCol];
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Each thread computes one element of Csub
// by accumulating results into Cvalue
// block_size = 16 -> 256 threads, one per Csub element
float Cvalue = 0.0;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int i = 0; i < (n / BLOCK_SIZE); ++i) {
// Get sub-matrix Asub of A
float* Asub = &A[BLOCK_SIZE * blockRow * n + BLOCK_SIZE * i];
// Get sub-matrix Bsub of B
float* Bsub = &B[BLOCK_SIZE * k * i + BLOCK_SIZE * blockCol];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = Asub[row*n+col];
Bs[row][col] = Bsub[row*k+col];
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int j = 0; j < BLOCK_SIZE; ++j) Cvalue += As[row][j] * Bs[j][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
if(col + blockCol* BLOCK_SIZE< k && row + blockRow* BLOCK_SIZE< m) Csub[row*k+col] = Cvalue;
} | .file "tmpxft_0015829e_00000000-6_gemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii
.type _Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii, @function
_Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4gemmPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii, .-_Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii
.globl _Z4gemmPfS_S_iii
.type _Z4gemmPfS_S_iii, @function
_Z4gemmPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4gemmPfS_S_iii, .-_Z4gemmPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4gemmPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4gemmPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gemm(float* A, float* B, float* C, int m, int n, int k) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Each thread block computes one sub-matrix Csub of C
float* Csub = &C[BLOCK_SIZE * k * blockRow + BLOCK_SIZE * blockCol];
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Each thread computes one element of Csub
// by accumulating results into Cvalue
// block_size = 16 -> 256 threads, one per Csub element
float Cvalue = 0.0;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int i = 0; i < (n / BLOCK_SIZE); ++i) {
// Get sub-matrix Asub of A
float* Asub = &A[BLOCK_SIZE * blockRow * n + BLOCK_SIZE * i];
// Get sub-matrix Bsub of B
float* Bsub = &B[BLOCK_SIZE * k * i + BLOCK_SIZE * blockCol];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = Asub[row*n+col];
Bs[row][col] = Bsub[row*k+col];
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int j = 0; j < BLOCK_SIZE; ++j) Cvalue += As[row][j] * Bs[j][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
if(col + blockCol* BLOCK_SIZE< k && row + blockRow* BLOCK_SIZE< m) Csub[row*k+col] = Cvalue;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gemm(float* A, float* B, float* C, int m, int n, int k) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Each thread block computes one sub-matrix Csub of C
float* Csub = &C[BLOCK_SIZE * k * blockRow + BLOCK_SIZE * blockCol];
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Each thread computes one element of Csub
// by accumulating results into Cvalue
// block_size = 16 -> 256 threads, one per Csub element
float Cvalue = 0.0;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int i = 0; i < (n / BLOCK_SIZE); ++i) {
// Get sub-matrix Asub of A
float* Asub = &A[BLOCK_SIZE * blockRow * n + BLOCK_SIZE * i];
// Get sub-matrix Bsub of B
float* Bsub = &B[BLOCK_SIZE * k * i + BLOCK_SIZE * blockCol];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = Asub[row*n+col];
Bs[row][col] = Bsub[row*k+col];
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int j = 0; j < BLOCK_SIZE; ++j) Cvalue += As[row][j] * Bs[j][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
if(col + blockCol* BLOCK_SIZE< k && row + blockRow* BLOCK_SIZE< m) Csub[row*k+col] = Cvalue;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gemm(float* A, float* B, float* C, int m, int n, int k) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Each thread block computes one sub-matrix Csub of C
float* Csub = &C[BLOCK_SIZE * k * blockRow + BLOCK_SIZE * blockCol];
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Each thread computes one element of Csub
// by accumulating results into Cvalue
// block_size = 16 -> 256 threads, one per Csub element
float Cvalue = 0.0;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int i = 0; i < (n / BLOCK_SIZE); ++i) {
// Get sub-matrix Asub of A
float* Asub = &A[BLOCK_SIZE * blockRow * n + BLOCK_SIZE * i];
// Get sub-matrix Bsub of B
float* Bsub = &B[BLOCK_SIZE * k * i + BLOCK_SIZE * blockCol];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = Asub[row*n+col];
Bs[row][col] = Bsub[row*k+col];
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int j = 0; j < BLOCK_SIZE; ++j) Cvalue += As[row][j] * Bs[j][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
if(col + blockCol* BLOCK_SIZE< k && row + blockRow* BLOCK_SIZE< m) Csub[row*k+col] = Cvalue;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4gemmPfS_S_iii
.globl _Z4gemmPfS_S_iii
.p2align 8
.type _Z4gemmPfS_S_iii,@function
_Z4gemmPfS_S_iii:
s_load_b64 s[2:3], s[0:1], 0x1c
v_mov_b32_e32 v2, 0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s4, s14, 4
s_waitcnt lgkmcnt(0)
s_lshl_b32 s5, s3, 4
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[6:7], null, v3, s3, v[0:1]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
v_lshlrev_b32_e32 v4, 6, v3
s_ashr_i32 s6, s2, 31
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
s_lshr_b32 s6, s6, 28
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_add_nc_u32_e32 v1, v4, v5
v_add_nc_u32_e32 v5, 0x400, v5
v_lshlrev_b64 v[10:11], 2, v[6:7]
s_add_i32 s6, s2, s6
s_mul_i32 s2, s15, s2
s_ashr_i32 s6, s6, 4
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v11, vcc_lo
v_add_nc_u32_e32 v10, v5, v4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_add_i32 s8, s7, s2
s_mul_i32 s9, s7, s5
s_lshl_b32 s8, s8, 4
s_add_i32 s10, s9, s4
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v6, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v7, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v8, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v9, vcc_lo
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v5
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b32 v1, v12
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s8, v4
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 64, v11
s_cmp_eq_u32 s8, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v12, v13
s_cbranch_scc0 .LBB0_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s6
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s2, s[0:1], 0x18
v_add_nc_u32_e32 v1, s4, v0
v_lshl_add_u32 v4, s15, 4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v3, s3, v[0:1]
s_mul_i32 s2, s5, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
s_lshl_b64 s[2:3], s[2:3], 2
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4gemmPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4gemmPfS_S_iii, .Lfunc_end0-_Z4gemmPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4gemmPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4gemmPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gemm(float* A, float* B, float* C, int m, int n, int k) {
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;
// Each thread block computes one sub-matrix Csub of C
float* Csub = &C[BLOCK_SIZE * k * blockRow + BLOCK_SIZE * blockCol];
// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
// Each thread computes one element of Csub
// by accumulating results into Cvalue
// block_size = 16 -> 256 threads, one per Csub element
float Cvalue = 0.0;
// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int i = 0; i < (n / BLOCK_SIZE); ++i) {
// Get sub-matrix Asub of A
float* Asub = &A[BLOCK_SIZE * blockRow * n + BLOCK_SIZE * i];
// Get sub-matrix Bsub of B
float* Bsub = &B[BLOCK_SIZE * k * i + BLOCK_SIZE * blockCol];
// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = Asub[row*n+col];
Bs[row][col] = Bsub[row*k+col];
// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();
// Multiply Asub and Bsub together
for (int j = 0; j < BLOCK_SIZE; ++j) Cvalue += As[row][j] * Bs[j][col];
// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}
// Write Csub to device memory
// Each thread writes one element
if(col + blockCol* BLOCK_SIZE< k && row + blockRow* BLOCK_SIZE< m) Csub[row*k+col] = Cvalue;
} | .text
.file "gemm.hip"
.globl _Z19__device_stub__gemmPfS_S_iii # -- Begin function _Z19__device_stub__gemmPfS_S_iii
.p2align 4, 0x90
.type _Z19__device_stub__gemmPfS_S_iii,@function
_Z19__device_stub__gemmPfS_S_iii: # @_Z19__device_stub__gemmPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4gemmPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__gemmPfS_S_iii, .Lfunc_end0-_Z19__device_stub__gemmPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4gemmPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4gemmPfS_S_iii,@object # @_Z4gemmPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z4gemmPfS_S_iii
.p2align 3, 0x0
_Z4gemmPfS_S_iii:
.quad _Z19__device_stub__gemmPfS_S_iii
.size _Z4gemmPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4gemmPfS_S_iii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__gemmPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4gemmPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4gemmPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.GE.AND P1, PT, R4, 0x10, PT ; /* 0x000000100400780c */
/* 0x000fe20003f26270 */
/*0080*/ USHF.L.U32 UR5, UR5, 0x4, URZ ; /* 0x0000000405057899 */
/* 0x000fe2000800063f */
/*0090*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000ea80000002200 */
/*00a0*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000ea20000002600 */
/*00b0*/ IMAD.SHL.U32 R13, R13, 0x10, RZ ; /* 0x000000100d0d7824 */
/* 0x001fca00078e00ff */
/*00c0*/ IADD3 R5, R13, R0, RZ ; /* 0x000000000d057210 */
/* 0x002fc80007ffe0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */
/* 0x000fe40003f06270 */
/*00e0*/ LEA R6, R2, R3, 0x4 ; /* 0x0000000302067211 */
/* 0x004fc800078e20ff */
/*00f0*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x000fe20000706670 */
/*0100*/ @!P1 BRA 0x560 ; /* 0x0000045000009947 */
/* 0x000ff60003800000 */
/*0110*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ; /* 0x0000001fff047819 */
/* 0x000fe20000011404 */
/*0120*/ IMAD R19, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002137a24 */
/* 0x000fe200078e02ff */
/*0130*/ SHF.L.U32 R15, R3.reuse, 0x6, RZ ; /* 0x00000006030f7819 */
/* 0x040fe200000006ff */
/*0140*/ IMAD R14, R3.reuse, c[0x0][0x17c], R0.reuse ; /* 0x00005f00030e7a24 */
/* 0x140fe200078e0200 */
/*0150*/ LEA.HI R4, R4, c[0x0][0x17c], RZ, 0x4 ; /* 0x00005f0004047a11 */
/* 0x000fe200078f20ff */
/*0160*/ IMAD R17, R3, c[0x0][0x180], R0 ; /* 0x0000600003117a24 */
/* 0x000fe200078e0200 */
/*0170*/ MOV R12, R13 ; /* 0x0000000d000c7202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0190*/ LEA R18, R0, R15, 0x2 ; /* 0x0000000f00127211 */
/* 0x000fe200078e10ff */
/*01a0*/ IMAD.SHL.U32 R19, R19, 0x10, RZ ; /* 0x0000001013137824 */
/* 0x000fe200078e00ff */
/*01b0*/ SHF.R.S32.HI R16, RZ, 0x4, R4 ; /* 0x00000004ff107819 */
/* 0x000fe20000011404 */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*01d0*/ SHF.R.S32.HI R4, RZ, 0x1f, R12 ; /* 0x0000001fff047819 */
/* 0x000fe4000001140c */
/*01e0*/ IADD3 R6, P2, R17, R12, RZ ; /* 0x0000000c11067210 */
/* 0x000fc40007f5e0ff */
/*01f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R19 ; /* 0x0000001fff057819 */
/* 0x000fe40000011413 */
/*0200*/ IADD3 R8, P1, R14.reuse, R19, RZ ; /* 0x000000130e087210 */
/* 0x040fe40007f3e0ff */
/*0210*/ LEA.HI.X.SX32 R7, R17, R4, 0x1, P2 ; /* 0x0000000411077211 */
/* 0x000fe400010f0eff */
/*0220*/ LEA.HI.X.SX32 R5, R14, R5, 0x1, P1 ; /* 0x000000050e057211 */
/* 0x000fe400008f0eff */
/*0230*/ LEA R24, P2, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006187a11 */
/* 0x000fe400078410ff */
/*0240*/ LEA R4, P1, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008047a11 */
/* 0x000fc400078210ff */
/*0250*/ LEA.HI.X R25, R6, c[0x0][0x16c], R7, 0x2, P2 ; /* 0x00005b0006197a11 */
/* 0x000fe400010f1407 */
/*0260*/ LEA.HI.X R5, R8, c[0x0][0x164], R5, 0x2, P1 ; /* 0x0000590008057a11 */
/* 0x000fc800008f1405 */
/*0270*/ LDG.E R25, [R24.64] ; /* 0x0000000618197981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R29, [R4.64] ; /* 0x00000006041d7981 */
/* 0x000ee2000c1e1900 */
/*0290*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*02a0*/ ISETP.LE.AND P1, PT, R16, UR4, PT ; /* 0x0000000410007c0c */
/* 0x000fe4000bf23270 */
/*02b0*/ IADD3 R12, R12, UR5, RZ ; /* 0x000000050c0c7c10 */
/* 0x000fe4000fffe0ff */
/*02c0*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ STS [R18+0x400], R25 ; /* 0x0004001912007388 */
/* 0x004fe80000000800 */
/*02e0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x008fe80000000800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ LDS R22, [R0.X4+0x400] ; /* 0x0004000000167984 */
/* 0x000fe80000004800 */
/*0310*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*0320*/ LDS R28, [R0.X4+0x440] ; /* 0x00044000001c7984 */
/* 0x000e680000004800 */
/*0330*/ LDS R27, [R0.X4+0x480] ; /* 0x00048000001b7984 */
/* 0x000ea80000004800 */
/*0340*/ LDS R26, [R0.X4+0x4c0] ; /* 0x0004c000001a7984 */
/* 0x000ee80000004800 */
/*0350*/ LDS R23, [R0.X4+0x500] ; /* 0x0005000000177984 */
/* 0x000fe80000004800 */
/*0360*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*0370*/ LDS R20, [R0.X4+0x540] ; /* 0x0005400000147984 */
/* 0x000f680000004800 */
/*0380*/ LDS R25, [R0.X4+0x580] ; /* 0x0005800000197984 */
/* 0x000f680000004800 */
/*0390*/ LDS R24, [R0.X4+0x640] ; /* 0x0006400000187984 */
/* 0x000fe20000004800 */
/*03a0*/ FFMA R8, R22, R8, R21 ; /* 0x0000000816087223 */
/* 0x001fc60000000015 */
/*03b0*/ LDS R22, [R0.X4+0x5c0] ; /* 0x0005c00000167984 */
/* 0x000e220000004800 */
/*03c0*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc60000000008 */
/*03d0*/ LDS R21, [R0.X4+0x600] ; /* 0x0006000000157984 */
/* 0x000fe20000004800 */
/*03e0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*03f0*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0400*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e640000000c00 */
/*0410*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0420*/ LDS R23, [R0.X4+0x680] ; /* 0x0006800000177984 */
/* 0x000ea40000004800 */
/*0430*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0440*/ LDS R20, [R0.X4+0x6c0] ; /* 0x0006c00000147984 */
/* 0x000ee40000004800 */
/*0450*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0460*/ LDS R25, [R0.X4+0x700] ; /* 0x0007000000197984 */
/* 0x000fe40000004800 */
/*0470*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x001fe40000000004 */
/*0480*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000e280000000c00 */
/*0490*/ LDS R22, [R0.X4+0x740] ; /* 0x0007400000167984 */
/* 0x000f220000004800 */
/*04a0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x002fc6000000001a */
/*04b0*/ LDS R21, [R0.X4+0x780] ; /* 0x0007800000157984 */
/* 0x000e680000004800 */
/*04c0*/ LDS R8, [R0.X4+0x7c0] ; /* 0x0007c00000087984 */
/* 0x000f620000004800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc8000000001a */
/*04e0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x004fc80000000009 */
/*04f0*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x008fc80000000009 */
/*0500*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x001fc80000000009 */
/*0510*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fc80000000004 */
/*0520*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x002fc80000000004 */
/*0530*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @!P1 BRA 0x1d0 ; /* 0xfffffc7000009947 */
/* 0x000fea000383ffff */
/*0560*/ IMAD R2, R2, UR5, R13 ; /* 0x0000000502027c24 */
/* 0x000fe2000f8e020d */
/*0570*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*0580*/ IMAD R5, R3, c[0x0][0x180], R0 ; /* 0x0000600003057a24 */
/* 0x000fe200078e0200 */
/*0590*/ SHF.R.S32.HI R0, RZ, 0x1f, R2 ; /* 0x0000001fff007819 */
/* 0x000fc80000011402 */
/*05a0*/ IADD3 R3, P0, R5, R2, RZ ; /* 0x0000000205037210 */
/* 0x000fc80007f1e0ff */
/*05b0*/ LEA.HI.X.SX32 R0, R5, R0, 0x1, P0 ; /* 0x0000000005007211 */
/* 0x000fe400000f0eff */
/*05c0*/ LEA R2, P0, R3, c[0x0][0x170], 0x2 ; /* 0x00005c0003027a11 */
/* 0x000fc800078010ff */
/*05d0*/ LEA.HI.X R3, R3, c[0x0][0x174], R0, 0x2, P0 ; /* 0x00005d0003037a11 */
/* 0x000fca00000f1400 */
/*05e0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4gemmPfS_S_iii
.globl _Z4gemmPfS_S_iii
.p2align 8
.type _Z4gemmPfS_S_iii,@function
_Z4gemmPfS_S_iii:
s_load_b64 s[2:3], s[0:1], 0x1c
v_mov_b32_e32 v2, 0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s4, s14, 4
s_waitcnt lgkmcnt(0)
s_lshl_b32 s5, s3, 4
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[6:7], null, v3, s3, v[0:1]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
v_lshlrev_b32_e32 v4, 6, v3
s_ashr_i32 s6, s2, 31
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
s_lshr_b32 s6, s6, 28
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_add_nc_u32_e32 v1, v4, v5
v_add_nc_u32_e32 v5, 0x400, v5
v_lshlrev_b64 v[10:11], 2, v[6:7]
s_add_i32 s6, s2, s6
s_mul_i32 s2, s15, s2
s_ashr_i32 s6, s6, 4
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v11, vcc_lo
v_add_nc_u32_e32 v10, v5, v4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_add_i32 s8, s7, s2
s_mul_i32 s9, s7, s5
s_lshl_b32 s8, s8, 4
s_add_i32 s10, s9, s4
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v6, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v7, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v8, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v9, vcc_lo
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v5
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b32 v1, v12
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s8, v4
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 64, v11
s_cmp_eq_u32 s8, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v12, v13
s_cbranch_scc0 .LBB0_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s6
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s2, s[0:1], 0x18
v_add_nc_u32_e32 v1, s4, v0
v_lshl_add_u32 v4, s15, 4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v3, s3, v[0:1]
s_mul_i32 s2, s5, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
s_lshl_b64 s[2:3], s[2:3], 2
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4gemmPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4gemmPfS_S_iii, .Lfunc_end0-_Z4gemmPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4gemmPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4gemmPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015829e_00000000-6_gemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii
.type _Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii, @function
_Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4gemmPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii, .-_Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii
.globl _Z4gemmPfS_S_iii
.type _Z4gemmPfS_S_iii, @function
_Z4gemmPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4gemmPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4gemmPfS_S_iii, .-_Z4gemmPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4gemmPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4gemmPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gemm.hip"
.globl _Z19__device_stub__gemmPfS_S_iii # -- Begin function _Z19__device_stub__gemmPfS_S_iii
.p2align 4, 0x90
.type _Z19__device_stub__gemmPfS_S_iii,@function
_Z19__device_stub__gemmPfS_S_iii: # @_Z19__device_stub__gemmPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4gemmPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__gemmPfS_S_iii, .Lfunc_end0-_Z19__device_stub__gemmPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4gemmPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4gemmPfS_S_iii,@object # @_Z4gemmPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z4gemmPfS_S_iii
.p2align 3, 0x0
_Z4gemmPfS_S_iii:
.quad _Z19__device_stub__gemmPfS_S_iii
.size _Z4gemmPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4gemmPfS_S_iii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__gemmPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4gemmPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add3(float *val1, float *val2, int *num_elem)
{
int i = threadIdx.x;
val1[i] += val2[i];
} | code for sm_80
Function : _Z4add3PfS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FADD R7, R2, R7 ; /* 0x0000000702077221 */
/* 0x004fca0000000000 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add3(float *val1, float *val2, int *num_elem)
{
int i = threadIdx.x;
val1[i] += val2[i];
} | .file "tmpxft_000c6dfe_00000000-6_add3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4add3PfS_PiPfS_Pi
.type _Z27__device_stub__Z4add3PfS_PiPfS_Pi, @function
_Z27__device_stub__Z4add3PfS_PiPfS_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4add3PfS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z4add3PfS_PiPfS_Pi, .-_Z27__device_stub__Z4add3PfS_PiPfS_Pi
.globl _Z4add3PfS_Pi
.type _Z4add3PfS_Pi, @function
_Z4add3PfS_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4add3PfS_PiPfS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4add3PfS_Pi, .-_Z4add3PfS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4add3PfS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4add3PfS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add3(float *val1, float *val2, int *num_elem)
{
int i = threadIdx.x;
val1[i] += val2[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add3(float *val1, float *val2, int *num_elem)
{
int i = threadIdx.x;
val1[i] += val2[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add3(float *val1, float *val2, int *num_elem)
{
int i = threadIdx.x;
val1[i] += val2[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4add3PfS_Pi
.globl _Z4add3PfS_Pi
.p2align 8
.type _Z4add3PfS_Pi,@function
_Z4add3PfS_Pi:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4add3PfS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4add3PfS_Pi, .Lfunc_end0-_Z4add3PfS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4add3PfS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4add3PfS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add3(float *val1, float *val2, int *num_elem)
{
int i = threadIdx.x;
val1[i] += val2[i];
} | .text
.file "add3.hip"
.globl _Z19__device_stub__add3PfS_Pi # -- Begin function _Z19__device_stub__add3PfS_Pi
.p2align 4, 0x90
.type _Z19__device_stub__add3PfS_Pi,@function
_Z19__device_stub__add3PfS_Pi: # @_Z19__device_stub__add3PfS_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4add3PfS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__add3PfS_Pi, .Lfunc_end0-_Z19__device_stub__add3PfS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4add3PfS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4add3PfS_Pi,@object # @_Z4add3PfS_Pi
.section .rodata,"a",@progbits
.globl _Z4add3PfS_Pi
.p2align 3, 0x0
_Z4add3PfS_Pi:
.quad _Z19__device_stub__add3PfS_Pi
.size _Z4add3PfS_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4add3PfS_Pi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__add3PfS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4add3PfS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4add3PfS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FADD R7, R2, R7 ; /* 0x0000000702077221 */
/* 0x004fca0000000000 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4add3PfS_Pi
.globl _Z4add3PfS_Pi
.p2align 8
.type _Z4add3PfS_Pi,@function
_Z4add3PfS_Pi:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4add3PfS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4add3PfS_Pi, .Lfunc_end0-_Z4add3PfS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4add3PfS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4add3PfS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c6dfe_00000000-6_add3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4add3PfS_PiPfS_Pi
.type _Z27__device_stub__Z4add3PfS_PiPfS_Pi, @function
_Z27__device_stub__Z4add3PfS_PiPfS_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4add3PfS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z4add3PfS_PiPfS_Pi, .-_Z27__device_stub__Z4add3PfS_PiPfS_Pi
.globl _Z4add3PfS_Pi
.type _Z4add3PfS_Pi, @function
_Z4add3PfS_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4add3PfS_PiPfS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4add3PfS_Pi, .-_Z4add3PfS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4add3PfS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4add3PfS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add3.hip"
.globl _Z19__device_stub__add3PfS_Pi # -- Begin function _Z19__device_stub__add3PfS_Pi
.p2align 4, 0x90
.type _Z19__device_stub__add3PfS_Pi,@function
_Z19__device_stub__add3PfS_Pi: # @_Z19__device_stub__add3PfS_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4add3PfS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__add3PfS_Pi, .Lfunc_end0-_Z19__device_stub__add3PfS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4add3PfS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4add3PfS_Pi,@object # @_Z4add3PfS_Pi
.section .rodata,"a",@progbits
.globl _Z4add3PfS_Pi
.p2align 3, 0x0
_Z4add3PfS_Pi:
.quad _Z19__device_stub__add3PfS_Pi
.size _Z4add3PfS_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4add3PfS_Pi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__add3PfS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4add3PfS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MATRIX_TYPE int
#define BLOCK_SIZE 8
#define THREAD_SIZE 64
#define TILE 64
void stopwatch(int);
//CUDA 배열 곱
__global__ void cuda_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void shared_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void exam_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
int main()
{
//1024 by 1024 행렬
const int width = 1024;
const int height = width;
const int matrix_size = width*height;
const int buffer_size = matrix_size*sizeof(MATRIX_TYPE);
MATRIX_TYPE *host_A,*host_B,*host_C;
host_A = (MATRIX_TYPE*)malloc(buffer_size);
host_B = (MATRIX_TYPE*)malloc(buffer_size);
host_C = (MATRIX_TYPE*)malloc(buffer_size);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
printf("Multiply matrix (%dX%d ) * (%dX%d)\n",width,width,width,width);
MATRIX_TYPE *device_A,*device_B,*device_C;
dim3 Db(1024,1024,1);
cudaMalloc((void**)&device_A,buffer_size );
cudaMalloc((void**)&device_B,buffer_size );
cudaMalloc((void**)&device_C,buffer_size );
printf("cuda_mul\n");
stopwatch(0);
cudaMemcpy(device_A,host_A,buffer_size,cudaMemcpyHostToDevice);
cudaMemcpy(device_B,host_B,buffer_size,cudaMemcpyHostToDevice);
cuda_mul<<<1,Db>>>(device_A,device_B,device_C,width);
cudaMemcpy(host_C,device_C,buffer_size,cudaMemcpyDeviceToHost);
stopwatch(1);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
dim3 Sg(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 Sb(THREAD_SIZE,THREAD_SIZE,1);
printf("shared_mul\n");
stopwatch(0);
cudaMemcpy(device_A,host_A,buffer_size,cudaMemcpyHostToDevice);
cudaMemcpy(device_B,host_B,buffer_size,cudaMemcpyHostToDevice);
exam_mul<<<1,Db>>>(device_A,device_B,device_C,width);
cudaMemcpy(host_C,device_C,buffer_size,cudaMemcpyDeviceToHost);
stopwatch(1);
cudaFree(device_A);
cudaFree(device_B);
cudaFree(device_C);
free(host_A);
free(host_B);
free(host_C);
return 0;
}
__global__ void cuda_mul(MATRIX_TYPE* A, MATRIX_TYPE* B, MATRIX_TYPE* C, int w)
{
MATRIX_TYPE v;
v = 0;
for(int i =0;i<w;i++)
{
v += A[threadIdx.y*w + i] * B[threadIdx.x *w + i];
}
C[threadIdx.x *w + threadIdx.y] = v;
}
__global__ void shared_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
/*
Dg(16,16,1)
Db(64,64,1)
0,0 1,0
---------
|
0,1 | 1,1
|
1 0 2 4
1
0
2
4
*/
__shared__ MATRIX_TYPE SA[THREAD_SIZE][THREAD_SIZE];
__shared__ MATRIX_TYPE SB[THREAD_SIZE][THREAD_SIZE];
MATRIX_TYPE v;
SA[threadIdx.x][threadIdx.y] = A[blockIdx.y *w +blockIdx.x];
SB[threadIdx.x][threadIdx.y] = B[blockIdx.x *w +blockIdx.y];
v = 0;
/*
A 의 한 타일을 사용하는 모든 B의 타일들을 연산
O O O O X X X X
O O O O O O O O
X O O O O O O O
O O O O O O O O
*/
}
void stopwatch(int flag)
{
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long Diff = 0;
//start
if(flag == 0)
{
Diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
Diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
printf("elapsed time : % lld micros\n",Diff/1000);
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
}
__global__ void exam_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = w * TILE * by;
int aEnd = aBegin +w -1;
int aStep = TILE;
int bBegin = TILE *bx;
int bStep = TILE * w;
MATRIX_TYPE Csub = 0;
for(int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b+= bStep)
{
__shared__ MATRIX_TYPE As[TILE][TILE];
__shared__ MATRIX_TYPE Bs[TILE][TILE];
As[ty][tx] = A[a + w * ty + tx];
Bs[ty][tx] = B[b + w * ty + tx];
__syncthreads();
for(int k=0;k<TILE;k++)
Csub += As[ty][k] * Bs[k][tx];
__syncthreads();
}
int c = w * TILE * by + TILE * bx;
C[c + w * ty + ty] = Csub;
} | code for sm_80
Function : _Z8exam_mulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0030*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0040*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0050*/ USHF.L.U32 UR4, UR4, 0x6, URZ ; /* 0x0000000604047899 */
/* 0x000fe4000800063f */
/*0060*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0070*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000eae0000002600 */
/*0080*/ @!P0 MOV R9, RZ ; /* 0x000000ff00098202 */
/* 0x000fe20000000f00 */
/*0090*/ USHF.L.U32 UR6, UR6, 0x6, URZ ; /* 0x0000000606067899 */
/* 0x001fc4000800063f */
/*00a0*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x004fe2000f8e023f */
/*00b0*/ @!P0 BRA 0xb40 ; /* 0x00000a8000008947 */
/* 0x000fea0003800000 */
/*00c0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x002e220000002100 */
/*00d0*/ SHF.L.U32 R18, R0.reuse, 0x8, RZ ; /* 0x0000000800127819 */
/* 0x040fe200000006ff */
/*00e0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00f0*/ MOV R2, UR5 ; /* 0x0000000500027c02 */
/* 0x000fe20008000f00 */
/*0100*/ ULDC UR7, c[0x0][0x178] ; /* 0x00005e0000077ab9 */
/* 0x000fe40000000800 */
/*0110*/ UIADD3 UR7, UR5, UR7, URZ ; /* 0x0000000705077290 */
/* 0x000fe4000fffe03f */
/*0120*/ UMOV UR8, UR6 ; /* 0x0000000600087c82 */
/* 0x000fe20008000000 */
/*0130*/ IMAD R17, R0, c[0x0][0x178], R3 ; /* 0x00005e0000117a24 */
/* 0x001fe200078e0203 */
/*0140*/ LEA R16, R3, R18, 0x2 ; /* 0x0000001203107211 */
/* 0x000fc800078e10ff */
/*0150*/ IADD3 R4, R17, R2, RZ ; /* 0x0000000211047210 */
/* 0x000fe40007ffe0ff */
/*0160*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fc40000000f00 */
/*0170*/ IADD3 R10, R17, UR8, RZ ; /* 0x00000008110a7c10 */
/* 0x000fc6000fffe0ff */
/*0180*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e020b */
/*0190*/ IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fe200078e020b */
/*01a0*/ LDG.E R19, [R4.64] ; /* 0x0000000a04137981 */
/* 0x000eaa000c1e1900 */
/*01b0*/ LDG.E R11, [R10.64] ; /* 0x0000000a0a0b7981 */
/* 0x000ee2000c1e1900 */
/*01c0*/ IADD3 R2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ UIADD3 UR8, UR4, UR8, URZ ; /* 0x0000000804087290 */
/* 0x000fc6000fffe03f */
/*01e0*/ ISETP.GE.AND P0, PT, R2, UR7, PT ; /* 0x0000000702007c0c */
/* 0x000fe2000bf06270 */
/*01f0*/ STS [R16], R19 ; /* 0x0000001310007388 */
/* 0x004fe80000000800 */
/*0200*/ STS [R16+0x4000], R11 ; /* 0x0040000b10007388 */
/* 0x008fe80000000800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0220*/ LDS R8, [R3.X4+0x4000] ; /* 0x0040000003087984 */
/* 0x000fe80000004800 */
/*0230*/ LDS.128 R12, [R18] ; /* 0x00000000120c7984 */
/* 0x000e280000000c00 */
/*0240*/ LDS R21, [R3.X4+0x4100] ; /* 0x0041000003157984 */
/* 0x000e680000004800 */
/*0250*/ LDS R23, [R3.X4+0x4200] ; /* 0x0042000003177984 */
/* 0x000ea80000004800 */
/*0260*/ LDS R24, [R3.X4+0x4300] ; /* 0x0043000003187984 */
/* 0x000ee80000004800 */
/*0270*/ LDS R25, [R3.X4+0x4400] ; /* 0x0044000003197984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R4, [R18+0x10] ; /* 0x0000100012047984 */
/* 0x000f280000000c00 */
/*0290*/ LDS R22, [R3.X4+0x4500] ; /* 0x0045000003167984 */
/* 0x000f680000004800 */
/*02a0*/ LDS R19, [R3.X4+0x4600] ; /* 0x0046000003137984 */
/* 0x000f680000004800 */
/*02b0*/ LDS R20, [R3.X4+0x4700] ; /* 0x0047000003147984 */
/* 0x000f680000004800 */
/*02c0*/ LDS R26, [R3.X4+0x4900] ; /* 0x00490000031a7984 */
/* 0x000fe20000004800 */
/*02d0*/ IMAD R8, R8, R12, R9 ; /* 0x0000000c08087224 */
/* 0x001fc800078e0209 */
/*02e0*/ IMAD R13, R21, R13, R8 ; /* 0x0000000d150d7224 */
/* 0x002fe400078e0208 */
/*02f0*/ LDS R21, [R3.X4+0x4800] ; /* 0x0048000003157984 */
/* 0x000fe40000004800 */
/*0300*/ IMAD R13, R23, R14, R13 ; /* 0x0000000e170d7224 */
/* 0x004fe400078e020d */
/*0310*/ LDS.128 R8, [R18+0x20] ; /* 0x0000200012087984 */
/* 0x000e240000000c00 */
/*0320*/ IMAD R13, R24, R15, R13 ; /* 0x0000000f180d7224 */
/* 0x008fe400078e020d */
/*0330*/ LDS R23, [R3.X4+0x4a00] ; /* 0x004a000003177984 */
/* 0x000e680000004800 */
/*0340*/ LDS R24, [R3.X4+0x4b00] ; /* 0x004b000003187984 */
/* 0x000ea20000004800 */
/*0350*/ IMAD R4, R25, R4, R13 ; /* 0x0000000419047224 */
/* 0x010fc600078e020d */
/*0360*/ LDS R25, [R3.X4+0x4c00] ; /* 0x004c000003197984 */
/* 0x000fe20000004800 */
/*0370*/ IMAD R4, R22, R5, R4 ; /* 0x0000000516047224 */
/* 0x020fc600078e0204 */
/*0380*/ LDS.128 R12, [R18+0x30] ; /* 0x00003000120c7984 */
/* 0x000ee20000000c00 */
/*0390*/ IMAD R4, R19, R6, R4 ; /* 0x0000000613047224 */
/* 0x000fc600078e0204 */
/*03a0*/ LDS R22, [R3.X4+0x4d00] ; /* 0x004d000003167984 */
/* 0x000f220000004800 */
/*03b0*/ IMAD R4, R20, R7, R4 ; /* 0x0000000714047224 */
/* 0x000fc600078e0204 */
/*03c0*/ LDS R19, [R3.X4+0x4e00] ; /* 0x004e000003137984 */
/* 0x000f680000004800 */
/*03d0*/ LDS R20, [R3.X4+0x4f00] ; /* 0x004f000003147984 */
/* 0x000f620000004800 */
/*03e0*/ IMAD R4, R21, R8, R4 ; /* 0x0000000815047224 */
/* 0x001fc600078e0204 */
/*03f0*/ LDS R21, [R3.X4+0x5000] ; /* 0x0050000003157984 */
/* 0x000fe20000004800 */
/*0400*/ IMAD R9, R26, R9, R4 ; /* 0x000000091a097224 */
/* 0x000fc600078e0204 */
/*0410*/ LDS.128 R4, [R18+0x40] ; /* 0x0000400012047984 */
/* 0x000e220000000c00 */
/*0420*/ IMAD R9, R23, R10, R9 ; /* 0x0000000a17097224 */
/* 0x002fc600078e0209 */
/*0430*/ LDS R26, [R3.X4+0x5100] ; /* 0x00510000031a7984 */
/* 0x000e620000004800 */
/*0440*/ IMAD R9, R24, R11, R9 ; /* 0x0000000b18097224 */
/* 0x004fc600078e0209 */
/*0450*/ LDS R23, [R3.X4+0x5200] ; /* 0x0052000003177984 */
/* 0x000ea20000004800 */
/*0460*/ IMAD R9, R25, R12, R9 ; /* 0x0000000c19097224 */
/* 0x008fc600078e0209 */
/*0470*/ LDS R24, [R3.X4+0x5300] ; /* 0x0053000003187984 */
/* 0x000ee20000004800 */
/*0480*/ IMAD R13, R22, R13, R9 ; /* 0x0000000d160d7224 */
/* 0x010fc600078e0209 */
/*0490*/ LDS R25, [R3.X4+0x5400] ; /* 0x0054000003197984 */
/* 0x000fe20000004800 */
/*04a0*/ IMAD R13, R19, R14, R13 ; /* 0x0000000e130d7224 */
/* 0x020fc600078e020d */
/*04b0*/ LDS.128 R8, [R18+0x50] ; /* 0x0000500012087984 */
/* 0x000f220000000c00 */
/*04c0*/ IMAD R13, R20, R15, R13 ; /* 0x0000000f140d7224 */
/* 0x000fc600078e020d */
/*04d0*/ LDS R22, [R3.X4+0x5500] ; /* 0x0055000003167984 */
/* 0x000f680000004800 */
/*04e0*/ LDS R19, [R3.X4+0x5600] ; /* 0x0056000003137984 */
/* 0x000f680000004800 */
/*04f0*/ LDS R20, [R3.X4+0x5700] ; /* 0x0057000003147984 */
/* 0x000f620000004800 */
/*0500*/ IMAD R4, R21, R4, R13 ; /* 0x0000000415047224 */
/* 0x001fc600078e020d */
/*0510*/ LDS R21, [R3.X4+0x5800] ; /* 0x0058000003157984 */
/* 0x000fe20000004800 */
/*0520*/ IMAD R4, R26, R5, R4 ; /* 0x000000051a047224 */
/* 0x002fc600078e0204 */
/*0530*/ LDS.128 R12, [R18+0x60] ; /* 0x00006000120c7984 */
/* 0x000e220000000c00 */
/*0540*/ IMAD R4, R23, R6, R4 ; /* 0x0000000617047224 */
/* 0x004fc600078e0204 */
/*0550*/ LDS R26, [R3.X4+0x5900] ; /* 0x00590000031a7984 */
/* 0x000e620000004800 */
/*0560*/ IMAD R4, R24, R7, R4 ; /* 0x0000000718047224 */
/* 0x008fc600078e0204 */
/*0570*/ LDS R23, [R3.X4+0x5a00] ; /* 0x005a000003177984 */
/* 0x000ea80000004800 */
/*0580*/ LDS R24, [R3.X4+0x5b00] ; /* 0x005b000003187984 */
/* 0x000ee20000004800 */
/*0590*/ IMAD R4, R25, R8, R4 ; /* 0x0000000819047224 */
/* 0x010fc600078e0204 */
/*05a0*/ LDS R25, [R3.X4+0x5c00] ; /* 0x005c000003197984 */
/* 0x000fe20000004800 */
/*05b0*/ IMAD R9, R22, R9, R4 ; /* 0x0000000916097224 */
/* 0x020fc600078e0204 */
/*05c0*/ LDS.128 R4, [R18+0x70] ; /* 0x0000700012047984 */
/* 0x000f220000000c00 */
/*05d0*/ IMAD R9, R19, R10, R9 ; /* 0x0000000a13097224 */
/* 0x000fc600078e0209 */
/*05e0*/ LDS R22, [R3.X4+0x5d00] ; /* 0x005d000003167984 */
/* 0x000f620000004800 */
/*05f0*/ IMAD R9, R20, R11, R9 ; /* 0x0000000b14097224 */
/* 0x000fc600078e0209 */
/*0600*/ LDS R19, [R3.X4+0x5e00] ; /* 0x005e000003137984 */
/* 0x000f680000004800 */
/*0610*/ LDS R20, [R3.X4+0x5f00] ; /* 0x005f000003147984 */
/* 0x000f620000004800 */
/*0620*/ IMAD R9, R21, R12, R9 ; /* 0x0000000c15097224 */
/* 0x001fc600078e0209 */
/*0630*/ LDS R21, [R3.X4+0x6000] ; /* 0x0060000003157984 */
/* 0x000fe20000004800 */
/*0640*/ IMAD R13, R26, R13, R9 ; /* 0x0000000d1a0d7224 */
/* 0x002fc600078e0209 */
/*0650*/ LDS.128 R8, [R18+0x80] ; /* 0x0000800012087984 */
/* 0x000e220000000c00 */
/*0660*/ IMAD R13, R23, R14, R13 ; /* 0x0000000e170d7224 */
/* 0x004fc600078e020d */
/*0670*/ LDS R26, [R3.X4+0x6100] ; /* 0x00610000031a7984 */
/* 0x000e620000004800 */
/*0680*/ IMAD R13, R24, R15, R13 ; /* 0x0000000f180d7224 */
/* 0x008fc600078e020d */
/*0690*/ LDS R23, [R3.X4+0x6200] ; /* 0x0062000003177984 */
/* 0x000ea80000004800 */
/*06a0*/ LDS R24, [R3.X4+0x6300] ; /* 0x0063000003187984 */
/* 0x000ee20000004800 */
/*06b0*/ IMAD R4, R25, R4, R13 ; /* 0x0000000419047224 */
/* 0x010fc600078e020d */
/*06c0*/ LDS R25, [R3.X4+0x6400] ; /* 0x0064000003197984 */
/* 0x000fe20000004800 */
/*06d0*/ IMAD R4, R22, R5, R4 ; /* 0x0000000516047224 */
/* 0x020fc600078e0204 */
/*06e0*/ LDS.128 R12, [R18+0x90] ; /* 0x00009000120c7984 */
/* 0x000f220000000c00 */
/*06f0*/ IMAD R4, R19, R6, R4 ; /* 0x0000000613047224 */
/* 0x000fc600078e0204 */
/*0700*/ LDS R22, [R3.X4+0x6500] ; /* 0x0065000003167984 */
/* 0x000f620000004800 */
/*0710*/ IMAD R4, R20, R7, R4 ; /* 0x0000000714047224 */
/* 0x000fc600078e0204 */
/*0720*/ LDS R19, [R3.X4+0x6600] ; /* 0x0066000003137984 */
/* 0x000f680000004800 */
/*0730*/ LDS R20, [R3.X4+0x6700] ; /* 0x0067000003147984 */
/* 0x000f620000004800 */
/*0740*/ IMAD R4, R21, R8, R4 ; /* 0x0000000815047224 */
/* 0x001fc600078e0204 */
/*0750*/ LDS R21, [R3.X4+0x6800] ; /* 0x0068000003157984 */
/* 0x000fe20000004800 */
/*0760*/ IMAD R9, R26, R9, R4 ; /* 0x000000091a097224 */
/* 0x002fc600078e0204 */
/*0770*/ LDS.128 R4, [R18+0xa0] ; /* 0x0000a00012047984 */
/* 0x000e220000000c00 */
/*0780*/ IMAD R9, R23, R10, R9 ; /* 0x0000000a17097224 */
/* 0x004fc600078e0209 */
/*0790*/ LDS R26, [R3.X4+0x6900] ; /* 0x00690000031a7984 */
/* 0x000e620000004800 */
/*07a0*/ IMAD R9, R24, R11, R9 ; /* 0x0000000b18097224 */
/* 0x008fc600078e0209 */
/*07b0*/ LDS R23, [R3.X4+0x6a00] ; /* 0x006a000003177984 */
/* 0x000ea80000004800 */
/*07c0*/ LDS R24, [R3.X4+0x6b00] ; /* 0x006b000003187984 */
/* 0x000ee20000004800 */
/*07d0*/ IMAD R9, R25, R12, R9 ; /* 0x0000000c19097224 */
/* 0x010fc600078e0209 */
/*07e0*/ LDS R25, [R3.X4+0x6c00] ; /* 0x006c000003197984 */
/* 0x000fe20000004800 */
/*07f0*/ IMAD R13, R22, R13, R9 ; /* 0x0000000d160d7224 */
/* 0x020fc600078e0209 */
/*0800*/ LDS.128 R8, [R18+0xb0] ; /* 0x0000b00012087984 */
/* 0x000f220000000c00 */
/*0810*/ IMAD R13, R19, R14, R13 ; /* 0x0000000e130d7224 */
/* 0x000fc600078e020d */
/*0820*/ LDS R22, [R3.X4+0x6d00] ; /* 0x006d000003167984 */
/* 0x000f620000004800 */
/*0830*/ IMAD R13, R20, R15, R13 ; /* 0x0000000f140d7224 */
/* 0x000fc600078e020d */
/*0840*/ LDS R19, [R3.X4+0x6e00] ; /* 0x006e000003137984 */
/* 0x000f680000004800 */
/*0850*/ LDS R20, [R3.X4+0x6f00] ; /* 0x006f000003147984 */
/* 0x000f620000004800 */
/*0860*/ IMAD R4, R21, R4, R13 ; /* 0x0000000415047224 */
/* 0x001fc600078e020d */
/*0870*/ LDS R21, [R3.X4+0x7000] ; /* 0x0070000003157984 */
/* 0x000fe20000004800 */
/*0880*/ IMAD R4, R26, R5, R4 ; /* 0x000000051a047224 */
/* 0x002fc600078e0204 */
/*0890*/ LDS.128 R12, [R18+0xc0] ; /* 0x0000c000120c7984 */
/* 0x000e220000000c00 */
/*08a0*/ IMAD R4, R23, R6, R4 ; /* 0x0000000617047224 */
/* 0x004fc600078e0204 */
/*08b0*/ LDS R26, [R3.X4+0x7100] ; /* 0x00710000031a7984 */
/* 0x000e620000004800 */
/*08c0*/ IMAD R4, R24, R7, R4 ; /* 0x0000000718047224 */
/* 0x008fc600078e0204 */
/*08d0*/ LDS R23, [R3.X4+0x7200] ; /* 0x0072000003177984 */
/* 0x000ea80000004800 */
/*08e0*/ LDS R24, [R3.X4+0x7300] ; /* 0x0073000003187984 */
/* 0x000ee20000004800 */
/*08f0*/ IMAD R4, R25, R8, R4 ; /* 0x0000000819047224 */
/* 0x010fc600078e0204 */
/*0900*/ LDS R25, [R3.X4+0x7400] ; /* 0x0074000003197984 */
/* 0x000fe20000004800 */
/*0910*/ IMAD R9, R22, R9, R4 ; /* 0x0000000916097224 */
/* 0x020fc600078e0204 */
/*0920*/ LDS.128 R4, [R18+0xd0] ; /* 0x0000d00012047984 */
/* 0x000f220000000c00 */
/*0930*/ IMAD R9, R19, R10, R9 ; /* 0x0000000a13097224 */
/* 0x000fc600078e0209 */
/*0940*/ LDS R22, [R3.X4+0x7500] ; /* 0x0075000003167984 */
/* 0x000f620000004800 */
/*0950*/ IMAD R9, R20, R11, R9 ; /* 0x0000000b14097224 */
/* 0x000fc600078e0209 */
/*0960*/ LDS R19, [R3.X4+0x7600] ; /* 0x0076000003137984 */
/* 0x000f680000004800 */
/*0970*/ LDS R20, [R3.X4+0x7700] ; /* 0x0077000003147984 */
/* 0x000f620000004800 */
/*0980*/ IMAD R9, R21, R12, R9 ; /* 0x0000000c15097224 */
/* 0x001fc600078e0209 */
/*0990*/ LDS R21, [R3.X4+0x7800] ; /* 0x0078000003157984 */
/* 0x000fe20000004800 */
/*09a0*/ IMAD R13, R26, R13, R9 ; /* 0x0000000d1a0d7224 */
/* 0x002fc600078e0209 */
/*09b0*/ LDS.128 R8, [R18+0xe0] ; /* 0x0000e00012087984 */
/* 0x000e220000000c00 */
/*09c0*/ IMAD R13, R23, R14, R13 ; /* 0x0000000e170d7224 */
/* 0x004fc600078e020d */
/*09d0*/ LDS R26, [R3.X4+0x7900] ; /* 0x00790000031a7984 */
/* 0x000e620000004800 */
/*09e0*/ IMAD R13, R24, R15, R13 ; /* 0x0000000f180d7224 */
/* 0x008fc600078e020d */
/*09f0*/ LDS R23, [R3.X4+0x7a00] ; /* 0x007a000003177984 */
/* 0x000ea20000004800 */
/*0a00*/ IMAD R13, R25, R4, R13 ; /* 0x00000004190d7224 */
/* 0x010fc600078e020d */
/*0a10*/ LDS R4, [R3.X4+0x7b00] ; /* 0x007b000003047984 */
/* 0x000ee20000004800 */
/*0a20*/ IMAD R24, R22, R5, R13 ; /* 0x0000000516187224 */
/* 0x020fc600078e020d */
/*0a30*/ LDS R5, [R3.X4+0x7c00] ; /* 0x007c000003057984 */
/* 0x000fe20000004800 */
/*0a40*/ IMAD R24, R19, R6, R24 ; /* 0x0000000613187224 */
/* 0x000fc600078e0218 */
/*0a50*/ LDS.128 R12, [R18+0xf0] ; /* 0x0000f000120c7984 */
/* 0x000f220000000c00 */
/*0a60*/ IMAD R7, R20, R7, R24 ; /* 0x0000000714077224 */
/* 0x000fc600078e0218 */
/*0a70*/ LDS R22, [R3.X4+0x7d00] ; /* 0x007d000003167984 */
/* 0x000f680000004800 */
/*0a80*/ LDS R19, [R3.X4+0x7e00] ; /* 0x007e000003137984 */
/* 0x000f680000004800 */
/*0a90*/ LDS R6, [R3.X4+0x7f00] ; /* 0x007f000003067984 */
/* 0x000f620000004800 */
/*0aa0*/ IMAD R7, R21, R8, R7 ; /* 0x0000000815077224 */
/* 0x001fc800078e0207 */
/*0ab0*/ IMAD R7, R26, R9, R7 ; /* 0x000000091a077224 */
/* 0x002fc800078e0207 */
/*0ac0*/ IMAD R7, R23, R10, R7 ; /* 0x0000000a17077224 */
/* 0x004fc800078e0207 */
/*0ad0*/ IMAD R4, R4, R11, R7 ; /* 0x0000000b04047224 */
/* 0x008fc800078e0207 */
/*0ae0*/ IMAD R4, R5, R12, R4 ; /* 0x0000000c05047224 */
/* 0x010fc800078e0204 */
/*0af0*/ IMAD R4, R22, R13, R4 ; /* 0x0000000d16047224 */
/* 0x020fc800078e0204 */
/*0b00*/ IMAD R4, R19, R14, R4 ; /* 0x0000000e13047224 */
/* 0x000fc800078e0204 */
/*0b10*/ IMAD R9, R6, R15, R4 ; /* 0x0000000f06097224 */
/* 0x000fe200078e0204 */
/*0b20*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b30*/ @!P0 BRA 0x150 ; /* 0xfffff61000008947 */
/* 0x000fea000383ffff */
/*0b40*/ IADD3 R3, R0, UR6, RZ ; /* 0x0000000600037c10 */
/* 0x002fe2000fffe0ff */
/*0b50*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc800000001ff */
/*0b60*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fca00078e0203 */
/*0b70*/ IADD3 R3, R3, UR5, RZ ; /* 0x0000000503037c10 */
/* 0x000fca000fffe0ff */
/*0b80*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0b90*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c10190a */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10shared_mulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8cuda_mulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0030*/ @!P0 MOV R16, RZ ; /* 0x000000ff00108202 */
/* 0x000fe20000000f00 */
/*0040*/ @!P0 BRA 0x440 ; /* 0x000003f000008947 */
/* 0x000fea0003800000 */
/*0050*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0060*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002200 */
/*0070*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe40000000f00 */
/*0080*/ IADD3 R0, R2.reuse, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x040fe20007ffe0ff */
/*0090*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000e620000002100 */
/*00a0*/ LOP3.LUT R15, R2, 0x3, RZ, 0xc0, !PT ; /* 0x00000003020f7812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*00c0*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*00d0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fd60003f05270 */
/*00e0*/ @!P1 BRA 0x360 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD R14, R19, R2.reuse, 0x3 ; /* 0x00000003130e7424 */
/* 0x082fe200078e0202 */
/*0100*/ IADD3 R21, R15, -c[0x0][0x178], RZ ; /* 0x80005e000f157a10 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R18, R17, R2.reuse, 0x3 ; /* 0x0000000311127424 */
/* 0x081fe200078e0202 */
/*0120*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD R23, R19, R2.reuse, 0x1 ; /* 0x0000000113177424 */
/* 0x080fe400078e0202 */
/*0140*/ IMAD R25, R17, R2, 0x1 ; /* 0x0000000111197424 */
/* 0x000fc600078e0202 */
/*0150*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0160*/ IMAD R26, R19, c[0x0][0x178], R0.reuse ; /* 0x00005e00131a7a24 */
/* 0x100fe200078e0200 */
/*0170*/ IADD3 R8, R25, R0.reuse, RZ ; /* 0x0000000019087210 */
/* 0x080fe20007ffe0ff */
/*0180*/ IMAD R10, R17, c[0x0][0x178], R0 ; /* 0x00005e00110a7a24 */
/* 0x000fe200078e0200 */
/*0190*/ IADD3 R4, R23, R0, RZ ; /* 0x0000000017047210 */
/* 0x000fc40007ffe0ff */
/*01a0*/ IADD3 R6, R18, -0x1, RZ ; /* 0xffffffff12067810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ IMAD.WIDE.U32 R26, R26, R13, c[0x0][0x168] ; /* 0x00005a001a1a7625 */
/* 0x000fe200078e000d */
/*01c0*/ IADD3 R2, R14, -0x1, RZ ; /* 0xffffffff0e027810 */
/* 0x000fc60007ffe0ff */
/*01d0*/ IMAD.WIDE.U32 R10, R10, R13.reuse, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x080fe400078e000d */
/*01e0*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000ea4000c1e1900 */
/*01f0*/ IMAD.WIDE.U32 R8, R8, R13.reuse, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x080fe400078e000d */
/*0200*/ LDG.E R29, [R10.64] ; /* 0x000000040a1d7981 */
/* 0x0000a4000c1e1900 */
/*0210*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x080fe400078e000d */
/*0220*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0002e4000c1e1900 */
/*0230*/ IMAD.WIDE.U32 R6, R6, R13, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc400078e000d */
/*0240*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1900 */
/*0250*/ IMAD.WIDE.U32 R2, R2, R13.reuse, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x080fe400078e000d */
/*0260*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f24000c1e1900 */
/*0270*/ IMAD.WIDE.U32 R10, R18, R13.reuse, c[0x0][0x160] ; /* 0x00005800120a7625 */
/* 0x081fe400078e000d */
/*0280*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000f24000c1e1900 */
/*0290*/ IMAD.WIDE.U32 R12, R14, R13, c[0x0][0x168] ; /* 0x00005a000e0c7625 */
/* 0x000fc400078e000d */
/*02a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f62000c1e1900 */
/*02c0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ IADD3 R9, R21, R0, RZ ; /* 0x0000000015097210 */
/* 0x002fc80007ffe0ff */
/*02e0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*02f0*/ IADD3 R18, R18, 0x4, RZ ; /* 0x0000000412127810 */
/* 0x000fe40007ffe0ff */
/*0300*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD R29, R26, R29, R16 ; /* 0x0000001d1a1d7224 */
/* 0x004fc800078e0210 */
/*0320*/ IMAD R8, R4, R8, R29 ; /* 0x0000000804087224 */
/* 0x008fc800078e021d */
/*0330*/ IMAD R6, R3, R6, R8 ; /* 0x0000000603067224 */
/* 0x010fc800078e0208 */
/*0340*/ IMAD R16, R13, R10, R6 ; /* 0x0000000a0d107224 */
/* 0x020fe200078e0206 */
/*0350*/ @P1 BRA 0x150 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0360*/ @!P0 BRA 0x440 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD R19, R19, c[0x0][0x178], R0.reuse ; /* 0x00005e0013137a24 */
/* 0x102fe400078e0200 */
/*0380*/ IMAD R0, R17, c[0x0][0x178], R0 ; /* 0x00005e0011007a24 */
/* 0x001fe400078e0200 */
/*0390*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fca0000000f00 */
/*03a0*/ IMAD.WIDE.U32 R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0004 */
/*03b0*/ IMAD.WIDE.U32 R4, R19, R4, c[0x0][0x168] ; /* 0x00005a0013047625 */
/* 0x000fe400078e0004 */
/*03c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IADD3 R15, R15, -0x1, RZ ; /* 0xffffffff0f0f7810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0400*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc40003f05270 */
/*0410*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*0420*/ IMAD R16, R5, R2, R16 ; /* 0x0000000205107224 */
/* 0x004fd400078e0210 */
/*0430*/ @P0 BRA 0x390 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0440*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000ea20000002100 */
/*0450*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0460*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000ea40000002200 */
/*0470*/ IMAD R2, R2, c[0x0][0x178], R3 ; /* 0x00005e0002027a24 */
/* 0x004fca00078e0203 */
/*0480*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0005 */
/*0490*/ STG.E [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x000fe2000c101904 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MATRIX_TYPE int
#define BLOCK_SIZE 8
#define THREAD_SIZE 64
#define TILE 64
void stopwatch(int);
//CUDA 배열 곱
__global__ void cuda_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void shared_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void exam_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
int main()
{
//1024 by 1024 행렬
const int width = 1024;
const int height = width;
const int matrix_size = width*height;
const int buffer_size = matrix_size*sizeof(MATRIX_TYPE);
MATRIX_TYPE *host_A,*host_B,*host_C;
host_A = (MATRIX_TYPE*)malloc(buffer_size);
host_B = (MATRIX_TYPE*)malloc(buffer_size);
host_C = (MATRIX_TYPE*)malloc(buffer_size);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
printf("Multiply matrix (%dX%d ) * (%dX%d)\n",width,width,width,width);
MATRIX_TYPE *device_A,*device_B,*device_C;
dim3 Db(1024,1024,1);
cudaMalloc((void**)&device_A,buffer_size );
cudaMalloc((void**)&device_B,buffer_size );
cudaMalloc((void**)&device_C,buffer_size );
printf("cuda_mul\n");
stopwatch(0);
cudaMemcpy(device_A,host_A,buffer_size,cudaMemcpyHostToDevice);
cudaMemcpy(device_B,host_B,buffer_size,cudaMemcpyHostToDevice);
cuda_mul<<<1,Db>>>(device_A,device_B,device_C,width);
cudaMemcpy(host_C,device_C,buffer_size,cudaMemcpyDeviceToHost);
stopwatch(1);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
dim3 Sg(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 Sb(THREAD_SIZE,THREAD_SIZE,1);
printf("shared_mul\n");
stopwatch(0);
cudaMemcpy(device_A,host_A,buffer_size,cudaMemcpyHostToDevice);
cudaMemcpy(device_B,host_B,buffer_size,cudaMemcpyHostToDevice);
exam_mul<<<1,Db>>>(device_A,device_B,device_C,width);
cudaMemcpy(host_C,device_C,buffer_size,cudaMemcpyDeviceToHost);
stopwatch(1);
cudaFree(device_A);
cudaFree(device_B);
cudaFree(device_C);
free(host_A);
free(host_B);
free(host_C);
return 0;
}
__global__ void cuda_mul(MATRIX_TYPE* A, MATRIX_TYPE* B, MATRIX_TYPE* C, int w)
{
MATRIX_TYPE v;
v = 0;
for(int i =0;i<w;i++)
{
v += A[threadIdx.y*w + i] * B[threadIdx.x *w + i];
}
C[threadIdx.x *w + threadIdx.y] = v;
}
__global__ void shared_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
/*
Dg(16,16,1)
Db(64,64,1)
0,0 1,0
---------
|
0,1 | 1,1
|
1 0 2 4
1
0
2
4
*/
__shared__ MATRIX_TYPE SA[THREAD_SIZE][THREAD_SIZE];
__shared__ MATRIX_TYPE SB[THREAD_SIZE][THREAD_SIZE];
MATRIX_TYPE v;
SA[threadIdx.x][threadIdx.y] = A[blockIdx.y *w +blockIdx.x];
SB[threadIdx.x][threadIdx.y] = B[blockIdx.x *w +blockIdx.y];
v = 0;
/*
A 의 한 타일을 사용하는 모든 B의 타일들을 연산
O O O O X X X X
O O O O O O O O
X O O O O O O O
O O O O O O O O
*/
}
void stopwatch(int flag)
{
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long Diff = 0;
//start
if(flag == 0)
{
Diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
Diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
printf("elapsed time : % lld micros\n",Diff/1000);
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
}
__global__ void exam_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = w * TILE * by;
int aEnd = aBegin +w -1;
int aStep = TILE;
int bBegin = TILE *bx;
int bStep = TILE * w;
MATRIX_TYPE Csub = 0;
for(int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b+= bStep)
{
__shared__ MATRIX_TYPE As[TILE][TILE];
__shared__ MATRIX_TYPE Bs[TILE][TILE];
As[ty][tx] = A[a + w * ty + tx];
Bs[ty][tx] = B[b + w * ty + tx];
__syncthreads();
for(int k=0;k<TILE;k++)
Csub += As[ty][k] * Bs[k][tx];
__syncthreads();
}
int c = w * TILE * by + TILE * bx;
C[c + w * ty + ty] = Csub;
} | .file "tmpxft_001149e5_00000000-6_4_sharedMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to call clock_gettime\n"
.LC1:
.string "elapsed time : % lld micros\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "wrong flag | 0 : start, 1 : end\n"
.text
.globl _Z9stopwatchi
.type _Z9stopwatchi, @function
_Z9stopwatchi:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edi, %edi
je .L9
cmpl $1, %edi
je .L10
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
leaq _ZZ9stopwatchiE7startTS(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
jne .L3
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L10:
leaq _ZZ9stopwatchiE5endTS(%rip), %rsi
call clock_gettime@PLT
cmpl $-1, %eax
je .L11
.L7:
movq _ZZ9stopwatchiE5endTS(%rip), %rcx
subq _ZZ9stopwatchiE7startTS(%rip), %rcx
imulq $1000000000, %rcx, %rcx
addq 8+_ZZ9stopwatchiE5endTS(%rip), %rcx
subq 8+_ZZ9stopwatchiE7startTS(%rip), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L11:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z9stopwatchi, .-_Z9stopwatchi
.globl _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cuda_mulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
.globl _Z8cuda_mulPiS_S_i
.type _Z8cuda_mulPiS_S_i, @function
_Z8cuda_mulPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8cuda_mulPiS_S_i, .-_Z8cuda_mulPiS_S_i
.globl _Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10shared_mulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i
.globl _Z10shared_mulPiS_S_i
.type _Z10shared_mulPiS_S_i, @function
_Z10shared_mulPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10shared_mulPiS_S_i, .-_Z10shared_mulPiS_S_i
.globl _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8exam_mulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i
.globl _Z8exam_mulPiS_S_i
.type _Z8exam_mulPiS_S_i, @function
_Z8exam_mulPiS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8exam_mulPiS_S_i, .-_Z8exam_mulPiS_S_i
.section .rodata.str1.8
.align 8
.LC3:
.string "Multiply matrix (%dX%d ) * (%dX%d)\n"
.section .rodata.str1.1
.LC4:
.string "cuda_mul\n"
.LC5:
.string "shared_mul\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L37:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L37
movl $1024, %r9d
movl $1024, %r8d
movl $1024, %ecx
movl $1024, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 32(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L38:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movl $0, %eax
.L39:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L39
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L40:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
jmp .L38
.L46:
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i
jmp .L40
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8exam_mulPiS_S_i"
.LC7:
.string "_Z10shared_mulPiS_S_i"
.LC8:
.string "_Z8cuda_mulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8exam_mulPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10shared_mulPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cuda_mulPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ9stopwatchiE5endTS
.comm _ZZ9stopwatchiE5endTS,16,16
.local _ZZ9stopwatchiE7startTS
.comm _ZZ9stopwatchiE7startTS,16,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MATRIX_TYPE int
#define BLOCK_SIZE 8
#define THREAD_SIZE 64
#define TILE 64
void stopwatch(int);
//CUDA 배열 곱
__global__ void cuda_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void shared_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void exam_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
int main()
{
//1024 by 1024 행렬
const int width = 1024;
const int height = width;
const int matrix_size = width*height;
const int buffer_size = matrix_size*sizeof(MATRIX_TYPE);
MATRIX_TYPE *host_A,*host_B,*host_C;
host_A = (MATRIX_TYPE*)malloc(buffer_size);
host_B = (MATRIX_TYPE*)malloc(buffer_size);
host_C = (MATRIX_TYPE*)malloc(buffer_size);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
printf("Multiply matrix (%dX%d ) * (%dX%d)\n",width,width,width,width);
MATRIX_TYPE *device_A,*device_B,*device_C;
dim3 Db(1024,1024,1);
cudaMalloc((void**)&device_A,buffer_size );
cudaMalloc((void**)&device_B,buffer_size );
cudaMalloc((void**)&device_C,buffer_size );
printf("cuda_mul\n");
stopwatch(0);
cudaMemcpy(device_A,host_A,buffer_size,cudaMemcpyHostToDevice);
cudaMemcpy(device_B,host_B,buffer_size,cudaMemcpyHostToDevice);
cuda_mul<<<1,Db>>>(device_A,device_B,device_C,width);
cudaMemcpy(host_C,device_C,buffer_size,cudaMemcpyDeviceToHost);
stopwatch(1);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
dim3 Sg(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 Sb(THREAD_SIZE,THREAD_SIZE,1);
printf("shared_mul\n");
stopwatch(0);
cudaMemcpy(device_A,host_A,buffer_size,cudaMemcpyHostToDevice);
cudaMemcpy(device_B,host_B,buffer_size,cudaMemcpyHostToDevice);
exam_mul<<<1,Db>>>(device_A,device_B,device_C,width);
cudaMemcpy(host_C,device_C,buffer_size,cudaMemcpyDeviceToHost);
stopwatch(1);
cudaFree(device_A);
cudaFree(device_B);
cudaFree(device_C);
free(host_A);
free(host_B);
free(host_C);
return 0;
}
__global__ void cuda_mul(MATRIX_TYPE* A, MATRIX_TYPE* B, MATRIX_TYPE* C, int w)
{
MATRIX_TYPE v;
v = 0;
for(int i =0;i<w;i++)
{
v += A[threadIdx.y*w + i] * B[threadIdx.x *w + i];
}
C[threadIdx.x *w + threadIdx.y] = v;
}
__global__ void shared_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
/*
Dg(16,16,1)
Db(64,64,1)
0,0 1,0
---------
|
0,1 | 1,1
|
1 0 2 4
1
0
2
4
*/
__shared__ MATRIX_TYPE SA[THREAD_SIZE][THREAD_SIZE];
__shared__ MATRIX_TYPE SB[THREAD_SIZE][THREAD_SIZE];
MATRIX_TYPE v;
SA[threadIdx.x][threadIdx.y] = A[blockIdx.y *w +blockIdx.x];
SB[threadIdx.x][threadIdx.y] = B[blockIdx.x *w +blockIdx.y];
v = 0;
/*
A 의 한 타일을 사용하는 모든 B의 타일들을 연산
O O O O X X X X
O O O O O O O O
X O O O O O O O
O O O O O O O O
*/
}
void stopwatch(int flag)
{
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long Diff = 0;
//start
if(flag == 0)
{
Diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
Diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
printf("elapsed time : % lld micros\n",Diff/1000);
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
}
__global__ void exam_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = w * TILE * by;
int aEnd = aBegin +w -1;
int aStep = TILE;
int bBegin = TILE *bx;
int bStep = TILE * w;
MATRIX_TYPE Csub = 0;
for(int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b+= bStep)
{
__shared__ MATRIX_TYPE As[TILE][TILE];
__shared__ MATRIX_TYPE Bs[TILE][TILE];
As[ty][tx] = A[a + w * ty + tx];
Bs[ty][tx] = B[b + w * ty + tx];
__syncthreads();
for(int k=0;k<TILE;k++)
Csub += As[ty][k] * Bs[k][tx];
__syncthreads();
}
int c = w * TILE * by + TILE * bx;
C[c + w * ty + ty] = Csub;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MATRIX_TYPE int
#define BLOCK_SIZE 8
#define THREAD_SIZE 64
#define TILE 64
void stopwatch(int);
//CUDA 배열 곱
__global__ void cuda_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void shared_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void exam_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
int main()
{
//1024 by 1024 행렬
const int width = 1024;
const int height = width;
const int matrix_size = width*height;
const int buffer_size = matrix_size*sizeof(MATRIX_TYPE);
MATRIX_TYPE *host_A,*host_B,*host_C;
host_A = (MATRIX_TYPE*)malloc(buffer_size);
host_B = (MATRIX_TYPE*)malloc(buffer_size);
host_C = (MATRIX_TYPE*)malloc(buffer_size);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
printf("Multiply matrix (%dX%d ) * (%dX%d)\n",width,width,width,width);
MATRIX_TYPE *device_A,*device_B,*device_C;
dim3 Db(1024,1024,1);
hipMalloc((void**)&device_A,buffer_size );
hipMalloc((void**)&device_B,buffer_size );
hipMalloc((void**)&device_C,buffer_size );
printf("cuda_mul\n");
stopwatch(0);
hipMemcpy(device_A,host_A,buffer_size,hipMemcpyHostToDevice);
hipMemcpy(device_B,host_B,buffer_size,hipMemcpyHostToDevice);
cuda_mul<<<1,Db>>>(device_A,device_B,device_C,width);
hipMemcpy(host_C,device_C,buffer_size,hipMemcpyDeviceToHost);
stopwatch(1);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
dim3 Sg(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 Sb(THREAD_SIZE,THREAD_SIZE,1);
printf("shared_mul\n");
stopwatch(0);
hipMemcpy(device_A,host_A,buffer_size,hipMemcpyHostToDevice);
hipMemcpy(device_B,host_B,buffer_size,hipMemcpyHostToDevice);
exam_mul<<<1,Db>>>(device_A,device_B,device_C,width);
hipMemcpy(host_C,device_C,buffer_size,hipMemcpyDeviceToHost);
stopwatch(1);
hipFree(device_A);
hipFree(device_B);
hipFree(device_C);
free(host_A);
free(host_B);
free(host_C);
return 0;
}
__global__ void cuda_mul(MATRIX_TYPE* A, MATRIX_TYPE* B, MATRIX_TYPE* C, int w)
{
MATRIX_TYPE v;
v = 0;
for(int i =0;i<w;i++)
{
v += A[threadIdx.y*w + i] * B[threadIdx.x *w + i];
}
C[threadIdx.x *w + threadIdx.y] = v;
}
__global__ void shared_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
/*
Dg(16,16,1)
Db(64,64,1)
0,0 1,0
---------
|
0,1 | 1,1
|
1 0 2 4
1
0
2
4
*/
__shared__ MATRIX_TYPE SA[THREAD_SIZE][THREAD_SIZE];
__shared__ MATRIX_TYPE SB[THREAD_SIZE][THREAD_SIZE];
MATRIX_TYPE v;
SA[threadIdx.x][threadIdx.y] = A[blockIdx.y *w +blockIdx.x];
SB[threadIdx.x][threadIdx.y] = B[blockIdx.x *w +blockIdx.y];
v = 0;
/*
A 의 한 타일을 사용하는 모든 B의 타일들을 연산
O O O O X X X X
O O O O O O O O
X O O O O O O O
O O O O O O O O
*/
}
void stopwatch(int flag)
{
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long Diff = 0;
//start
if(flag == 0)
{
Diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
Diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
printf("elapsed time : % lld micros\n",Diff/1000);
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
}
__global__ void exam_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = w * TILE * by;
int aEnd = aBegin +w -1;
int aStep = TILE;
int bBegin = TILE *bx;
int bStep = TILE * w;
MATRIX_TYPE Csub = 0;
for(int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b+= bStep)
{
__shared__ MATRIX_TYPE As[TILE][TILE];
__shared__ MATRIX_TYPE Bs[TILE][TILE];
As[ty][tx] = A[a + w * ty + tx];
Bs[ty][tx] = B[b + w * ty + tx];
__syncthreads();
for(int k=0;k<TILE;k++)
Csub += As[ty][k] * Bs[k][tx];
__syncthreads();
}
int c = w * TILE * by + TILE * bx;
C[c + w * ty + ty] = Csub;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MATRIX_TYPE int
#define BLOCK_SIZE 8
#define THREAD_SIZE 64
#define TILE 64
void stopwatch(int);
//CUDA 배열 곱
__global__ void cuda_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void shared_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void exam_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
int main()
{
//1024 by 1024 행렬
const int width = 1024;
const int height = width;
const int matrix_size = width*height;
const int buffer_size = matrix_size*sizeof(MATRIX_TYPE);
MATRIX_TYPE *host_A,*host_B,*host_C;
host_A = (MATRIX_TYPE*)malloc(buffer_size);
host_B = (MATRIX_TYPE*)malloc(buffer_size);
host_C = (MATRIX_TYPE*)malloc(buffer_size);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
printf("Multiply matrix (%dX%d ) * (%dX%d)\n",width,width,width,width);
MATRIX_TYPE *device_A,*device_B,*device_C;
dim3 Db(1024,1024,1);
hipMalloc((void**)&device_A,buffer_size );
hipMalloc((void**)&device_B,buffer_size );
hipMalloc((void**)&device_C,buffer_size );
printf("cuda_mul\n");
stopwatch(0);
hipMemcpy(device_A,host_A,buffer_size,hipMemcpyHostToDevice);
hipMemcpy(device_B,host_B,buffer_size,hipMemcpyHostToDevice);
cuda_mul<<<1,Db>>>(device_A,device_B,device_C,width);
hipMemcpy(host_C,device_C,buffer_size,hipMemcpyDeviceToHost);
stopwatch(1);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
dim3 Sg(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 Sb(THREAD_SIZE,THREAD_SIZE,1);
printf("shared_mul\n");
stopwatch(0);
hipMemcpy(device_A,host_A,buffer_size,hipMemcpyHostToDevice);
hipMemcpy(device_B,host_B,buffer_size,hipMemcpyHostToDevice);
exam_mul<<<1,Db>>>(device_A,device_B,device_C,width);
hipMemcpy(host_C,device_C,buffer_size,hipMemcpyDeviceToHost);
stopwatch(1);
hipFree(device_A);
hipFree(device_B);
hipFree(device_C);
free(host_A);
free(host_B);
free(host_C);
return 0;
}
__global__ void cuda_mul(MATRIX_TYPE* A, MATRIX_TYPE* B, MATRIX_TYPE* C, int w)
{
MATRIX_TYPE v;
v = 0;
for(int i =0;i<w;i++)
{
v += A[threadIdx.y*w + i] * B[threadIdx.x *w + i];
}
C[threadIdx.x *w + threadIdx.y] = v;
}
__global__ void shared_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
/*
Dg(16,16,1)
Db(64,64,1)
0,0 1,0
---------
|
0,1 | 1,1
|
1 0 2 4
1
0
2
4
*/
__shared__ MATRIX_TYPE SA[THREAD_SIZE][THREAD_SIZE];
__shared__ MATRIX_TYPE SB[THREAD_SIZE][THREAD_SIZE];
MATRIX_TYPE v;
SA[threadIdx.x][threadIdx.y] = A[blockIdx.y *w +blockIdx.x];
SB[threadIdx.x][threadIdx.y] = B[blockIdx.x *w +blockIdx.y];
v = 0;
/*
A 의 한 타일을 사용하는 모든 B의 타일들을 연산
O O O O X X X X
O O O O O O O O
X O O O O O O O
O O O O O O O O
*/
}
void stopwatch(int flag)
{
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long Diff = 0;
//start
if(flag == 0)
{
Diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
Diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
printf("elapsed time : % lld micros\n",Diff/1000);
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
}
__global__ void exam_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = w * TILE * by;
int aEnd = aBegin +w -1;
int aStep = TILE;
int bBegin = TILE *bx;
int bStep = TILE * w;
MATRIX_TYPE Csub = 0;
for(int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b+= bStep)
{
__shared__ MATRIX_TYPE As[TILE][TILE];
__shared__ MATRIX_TYPE Bs[TILE][TILE];
As[ty][tx] = A[a + w * ty + tx];
Bs[ty][tx] = B[b + w * ty + tx];
__syncthreads();
for(int k=0;k<TILE;k++)
Csub += As[ty][k] * Bs[k][tx];
__syncthreads();
}
int c = w * TILE * by + TILE * bx;
C[c + w * ty + ty] = Csub;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cuda_mulPiS_S_i
.globl _Z8cuda_mulPiS_S_i
.p2align 8
.type _Z8cuda_mulPiS_S_i,@function
_Z8cuda_mulPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_mul_lo_u32 v3, v1, s2
v_mov_b32_e32 v4, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v5, v2, s2
v_mov_b32_e32 v2, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v6, v4
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v10, vcc_lo
global_load_b32 v10, v[6:7], off
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v8, v10, v[2:3]
v_add_nc_u32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, 1, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_mov_b32_e32 v4, 0
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cuda_mulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cuda_mulPiS_S_i, .Lfunc_end0-_Z8cuda_mulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10shared_mulPiS_S_i
.globl _Z10shared_mulPiS_S_i
.p2align 8
.type _Z10shared_mulPiS_S_i,@function
_Z10shared_mulPiS_S_i:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10shared_mulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10shared_mulPiS_S_i, .Lfunc_end1-_Z10shared_mulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8exam_mulPiS_S_i
.globl _Z8exam_mulPiS_S_i
.p2align 8
.type _Z8exam_mulPiS_S_i,@function
_Z8exam_mulPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
s_lshl_b32 s8, s14, 6
s_waitcnt lgkmcnt(0)
s_lshl_b32 s9, s2, 6
s_cmp_lt_i32 s2, 1
s_mul_i32 s3, s9, s15
s_cbranch_scc1 .LBB2_5
v_and_b32_e32 v0, 0x3ff, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 8, v3
s_add_i32 s10, s3, s2
s_mov_b32 s11, s8
v_lshlrev_b32_e32 v6, 2, v0
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b32 s12, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v5, 0x4000, v6
v_add_nc_u32_e32 v2, v4, v6
v_add_nc_u32_e32 v6, v5, v4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB2_2:
v_add_nc_u32_e32 v7, s12, v1
v_add_nc_u32_e32 v9, s11, v1
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v8, v[7:8], off
global_load_b32 v9, v[9:10], off
v_mov_b32_e32 v7, v5
s_waitcnt vmcnt(1)
ds_store_b32 v2, v8
s_waitcnt vmcnt(0)
ds_store_b32 v6, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_3:
v_add_nc_u32_e32 v8, s13, v4
s_add_i32 s13, s13, 4
ds_load_b32 v10, v7
ds_load_b32 v11, v8
s_cmpk_eq_i32 s13, 0x100
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[8:9], null, v10, v11, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v8 :: v_dual_add_nc_u32 v7, 0x100, v7
s_cbranch_scc0 .LBB2_3
s_add_i32 s12, s12, 64
s_add_i32 s11, s11, s9
s_cmp_ge_i32 s12, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_6
.LBB2_5:
v_mov_b32_e32 v0, 0
.LBB2_6:
s_set_inst_prefetch_distance 0x2
v_mul_lo_u32 v1, v3, s2
v_add_nc_u32_e32 v2, s8, v3
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v2, v1, s3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8exam_mulPiS_S_i
.amdhsa_group_segment_fixed_size 32768
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8exam_mulPiS_S_i, .Lfunc_end2-_Z8exam_mulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cuda_mulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8cuda_mulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10shared_mulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10shared_mulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 32768
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8exam_mulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8exam_mulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MATRIX_TYPE int
#define BLOCK_SIZE 8
#define THREAD_SIZE 64
#define TILE 64
void stopwatch(int);
//CUDA 배열 곱
__global__ void cuda_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void shared_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
__global__ void exam_mul(MATRIX_TYPE*,MATRIX_TYPE*,MATRIX_TYPE*,int);
int main()
{
//1024 by 1024 행렬
const int width = 1024;
const int height = width;
const int matrix_size = width*height;
const int buffer_size = matrix_size*sizeof(MATRIX_TYPE);
MATRIX_TYPE *host_A,*host_B,*host_C;
host_A = (MATRIX_TYPE*)malloc(buffer_size);
host_B = (MATRIX_TYPE*)malloc(buffer_size);
host_C = (MATRIX_TYPE*)malloc(buffer_size);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
printf("Multiply matrix (%dX%d ) * (%dX%d)\n",width,width,width,width);
MATRIX_TYPE *device_A,*device_B,*device_C;
dim3 Db(1024,1024,1);
hipMalloc((void**)&device_A,buffer_size );
hipMalloc((void**)&device_B,buffer_size );
hipMalloc((void**)&device_C,buffer_size );
printf("cuda_mul\n");
stopwatch(0);
hipMemcpy(device_A,host_A,buffer_size,hipMemcpyHostToDevice);
hipMemcpy(device_B,host_B,buffer_size,hipMemcpyHostToDevice);
cuda_mul<<<1,Db>>>(device_A,device_B,device_C,width);
hipMemcpy(host_C,device_C,buffer_size,hipMemcpyDeviceToHost);
stopwatch(1);
for(int i=0;i<matrix_size;i++)
{
host_A[i] = i;
host_B[i] = i;
host_C[i] =0;
}
dim3 Sg(BLOCK_SIZE,BLOCK_SIZE,1);
dim3 Sb(THREAD_SIZE,THREAD_SIZE,1);
printf("shared_mul\n");
stopwatch(0);
hipMemcpy(device_A,host_A,buffer_size,hipMemcpyHostToDevice);
hipMemcpy(device_B,host_B,buffer_size,hipMemcpyHostToDevice);
exam_mul<<<1,Db>>>(device_A,device_B,device_C,width);
hipMemcpy(host_C,device_C,buffer_size,hipMemcpyDeviceToHost);
stopwatch(1);
hipFree(device_A);
hipFree(device_B);
hipFree(device_C);
free(host_A);
free(host_B);
free(host_C);
return 0;
}
__global__ void cuda_mul(MATRIX_TYPE* A, MATRIX_TYPE* B, MATRIX_TYPE* C, int w)
{
MATRIX_TYPE v;
v = 0;
for(int i =0;i<w;i++)
{
v += A[threadIdx.y*w + i] * B[threadIdx.x *w + i];
}
C[threadIdx.x *w + threadIdx.y] = v;
}
__global__ void shared_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
/*
Dg(16,16,1)
Db(64,64,1)
0,0 1,0
---------
|
0,1 | 1,1
|
1 0 2 4
1
0
2
4
*/
__shared__ MATRIX_TYPE SA[THREAD_SIZE][THREAD_SIZE];
__shared__ MATRIX_TYPE SB[THREAD_SIZE][THREAD_SIZE];
MATRIX_TYPE v;
SA[threadIdx.x][threadIdx.y] = A[blockIdx.y *w +blockIdx.x];
SB[threadIdx.x][threadIdx.y] = B[blockIdx.x *w +blockIdx.y];
v = 0;
/*
A 의 한 타일을 사용하는 모든 B의 타일들을 연산
O O O O X X X X
O O O O O O O O
X O O O O O O O
O O O O O O O O
*/
}
void stopwatch(int flag)
{
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long Diff = 0;
//start
if(flag == 0)
{
Diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
Diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
printf("elapsed time : % lld micros\n",Diff/1000);
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
}
__global__ void exam_mul(MATRIX_TYPE*A,MATRIX_TYPE*B,MATRIX_TYPE*C,int w)
{
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = w * TILE * by;
int aEnd = aBegin +w -1;
int aStep = TILE;
int bBegin = TILE *bx;
int bStep = TILE * w;
MATRIX_TYPE Csub = 0;
for(int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b+= bStep)
{
__shared__ MATRIX_TYPE As[TILE][TILE];
__shared__ MATRIX_TYPE Bs[TILE][TILE];
As[ty][tx] = A[a + w * ty + tx];
Bs[ty][tx] = B[b + w * ty + tx];
__syncthreads();
for(int k=0;k<TILE;k++)
Csub += As[ty][k] * Bs[k][tx];
__syncthreads();
}
int c = w * TILE * by + TILE * bx;
C[c + w * ty + ty] = Csub;
} | .text
.file "4_sharedMul.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %r12d, (%rbx,%r12,4)
movl %r12d, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB0_1
# %bb.2:
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
movl $1024, %ecx # imm = 0x400
movl $1024, %r8d # imm = 0x400
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB0_4
# %bb.3:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB0_4: # %_Z9stopwatchi.exit
movabsq $4398046512128, %r12 # imm = 0x40000000400
movabsq $4294967297, %r13 # imm = 0x100000001
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 12(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8cuda_mulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB0_8
# %bb.7:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB0_8: # %_Z9stopwatchi.exit41
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
movabsq $2361183241434822607, %rbp # imm = 0x20C49BA5E353F7CF
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
xorl %r12d, %r12d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movl %r12d, (%rbx,%r12,4)
movl %r12d, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB0_9
# %bb.10:
movl $.Lstr.1, %edi
callq puts@PLT
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB0_12
# %bb.11:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB0_12: # %_Z9stopwatchi.exit43
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
movl $1, %esi
movabsq $4398046512128, %rdx # imm = 0x40000000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_14
# %bb.13:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 12(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8exam_mulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_14:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB0_16
# %bb.15:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB0_16: # %_Z9stopwatchi.exit51
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z9stopwatchi # -- Begin function _Z9stopwatchi
.p2align 4, 0x90
.type _Z9stopwatchi,@function
_Z9stopwatchi: # @_Z9stopwatchi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpl $1, %edi
je .LBB1_4
# %bb.1:
testl %edi, %edi
jne .LBB1_7
# %bb.2:
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB1_3
# %bb.8:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 16
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB1_6
# %bb.5:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB1_6:
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB1_7:
.cfi_def_cfa_offset 16
movl $.Lstr.2, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB1_3:
.cfi_def_cfa_offset 16
movl $.Lstr.4, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z9stopwatchi, .Lfunc_end1-_Z9stopwatchi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__cuda_mulPiS_S_i # -- Begin function _Z23__device_stub__cuda_mulPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__cuda_mulPiS_S_i,@function
_Z23__device_stub__cuda_mulPiS_S_i: # @_Z23__device_stub__cuda_mulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cuda_mulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z23__device_stub__cuda_mulPiS_S_i, .Lfunc_end2-_Z23__device_stub__cuda_mulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__exam_mulPiS_S_i # -- Begin function _Z23__device_stub__exam_mulPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__exam_mulPiS_S_i,@function
_Z23__device_stub__exam_mulPiS_S_i: # @_Z23__device_stub__exam_mulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8exam_mulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z23__device_stub__exam_mulPiS_S_i, .Lfunc_end3-_Z23__device_stub__exam_mulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__shared_mulPiS_S_i # -- Begin function _Z25__device_stub__shared_mulPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__shared_mulPiS_S_i,@function
_Z25__device_stub__shared_mulPiS_S_i: # @_Z25__device_stub__shared_mulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10shared_mulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z25__device_stub__shared_mulPiS_S_i, .Lfunc_end4-_Z25__device_stub__shared_mulPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cuda_mulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10shared_mulPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8exam_mulPiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Multiply matrix (%dX%d ) * (%dX%d)\n"
.size .L.str, 36
.type _Z8cuda_mulPiS_S_i,@object # @_Z8cuda_mulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8cuda_mulPiS_S_i
.p2align 3, 0x0
_Z8cuda_mulPiS_S_i:
.quad _Z23__device_stub__cuda_mulPiS_S_i
.size _Z8cuda_mulPiS_S_i, 8
.type _Z8exam_mulPiS_S_i,@object # @_Z8exam_mulPiS_S_i
.globl _Z8exam_mulPiS_S_i
.p2align 3, 0x0
_Z8exam_mulPiS_S_i:
.quad _Z23__device_stub__exam_mulPiS_S_i
.size _Z8exam_mulPiS_S_i, 8
.type _Z10shared_mulPiS_S_i,@object # @_Z10shared_mulPiS_S_i
.globl _Z10shared_mulPiS_S_i
.p2align 3, 0x0
_Z10shared_mulPiS_S_i:
.quad _Z25__device_stub__shared_mulPiS_S_i
.size _Z10shared_mulPiS_S_i, 8
.type _ZZ9stopwatchiE7startTS,@object # @_ZZ9stopwatchiE7startTS
.local _ZZ9stopwatchiE7startTS
.comm _ZZ9stopwatchiE7startTS,16,8
.type _ZZ9stopwatchiE5endTS,@object # @_ZZ9stopwatchiE5endTS
.local _ZZ9stopwatchiE5endTS
.comm _ZZ9stopwatchiE5endTS,16,8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "elapsed time : % lld micros\n"
.size .L.str.4, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8cuda_mulPiS_S_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10shared_mulPiS_S_i"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8exam_mulPiS_S_i"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "cuda_mul"
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "shared_mul"
.size .Lstr.1, 11
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "wrong flag | 0 : start, 1 : end"
.size .Lstr.2, 32
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Failed to call clock_gettime"
.size .Lstr.4, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cuda_mulPiS_S_i
.addrsig_sym _Z23__device_stub__exam_mulPiS_S_i
.addrsig_sym _Z25__device_stub__shared_mulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cuda_mulPiS_S_i
.addrsig_sym _Z8exam_mulPiS_S_i
.addrsig_sym _Z10shared_mulPiS_S_i
.addrsig_sym _ZZ9stopwatchiE7startTS
.addrsig_sym _ZZ9stopwatchiE5endTS
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001149e5_00000000-6_4_sharedMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to call clock_gettime\n"
.LC1:
.string "elapsed time : % lld micros\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "wrong flag | 0 : start, 1 : end\n"
.text
.globl _Z9stopwatchi
.type _Z9stopwatchi, @function
_Z9stopwatchi:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edi, %edi
je .L9
cmpl $1, %edi
je .L10
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
leaq _ZZ9stopwatchiE7startTS(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
jne .L3
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L10:
leaq _ZZ9stopwatchiE5endTS(%rip), %rsi
call clock_gettime@PLT
cmpl $-1, %eax
je .L11
.L7:
movq _ZZ9stopwatchiE5endTS(%rip), %rcx
subq _ZZ9stopwatchiE7startTS(%rip), %rcx
imulq $1000000000, %rcx, %rcx
addq 8+_ZZ9stopwatchiE5endTS(%rip), %rcx
subq 8+_ZZ9stopwatchiE7startTS(%rip), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L11:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z9stopwatchi, .-_Z9stopwatchi
.globl _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cuda_mulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
.globl _Z8cuda_mulPiS_S_i
.type _Z8cuda_mulPiS_S_i, @function
_Z8cuda_mulPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8cuda_mulPiS_S_i, .-_Z8cuda_mulPiS_S_i
.globl _Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10shared_mulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i
.globl _Z10shared_mulPiS_S_i
.type _Z10shared_mulPiS_S_i, @function
_Z10shared_mulPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10shared_mulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10shared_mulPiS_S_i, .-_Z10shared_mulPiS_S_i
.globl _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8exam_mulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i
.globl _Z8exam_mulPiS_S_i
.type _Z8exam_mulPiS_S_i, @function
_Z8exam_mulPiS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8exam_mulPiS_S_i, .-_Z8exam_mulPiS_S_i
.section .rodata.str1.8
.align 8
.LC3:
.string "Multiply matrix (%dX%d ) * (%dX%d)\n"
.section .rodata.str1.1
.LC4:
.string "cuda_mul\n"
.LC5:
.string "shared_mul\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L37:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L37
movl $1024, %r9d
movl $1024, %r8d
movl $1024, %ecx
movl $1024, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 32(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L38:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movl $0, %eax
.L39:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L39
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L40:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
jmp .L38
.L46:
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8exam_mulPiS_S_iPiS_S_i
jmp .L40
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8exam_mulPiS_S_i"
.LC7:
.string "_Z10shared_mulPiS_S_i"
.LC8:
.string "_Z8cuda_mulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8exam_mulPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10shared_mulPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cuda_mulPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ9stopwatchiE5endTS
.comm _ZZ9stopwatchiE5endTS,16,16
.local _ZZ9stopwatchiE7startTS
.comm _ZZ9stopwatchiE7startTS,16,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "4_sharedMul.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %r12d, (%rbx,%r12,4)
movl %r12d, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB0_1
# %bb.2:
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
movl $1024, %ecx # imm = 0x400
movl $1024, %r8d # imm = 0x400
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB0_4
# %bb.3:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB0_4: # %_Z9stopwatchi.exit
movabsq $4398046512128, %r12 # imm = 0x40000000400
movabsq $4294967297, %r13 # imm = 0x100000001
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 12(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8cuda_mulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB0_8
# %bb.7:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB0_8: # %_Z9stopwatchi.exit41
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
movabsq $2361183241434822607, %rbp # imm = 0x20C49BA5E353F7CF
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
xorl %r12d, %r12d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movl %r12d, (%rbx,%r12,4)
movl %r12d, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB0_9
# %bb.10:
movl $.Lstr.1, %edi
callq puts@PLT
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB0_12
# %bb.11:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB0_12: # %_Z9stopwatchi.exit43
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
movl $1, %esi
movabsq $4398046512128, %rdx # imm = 0x40000000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_14
# %bb.13:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 12(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8exam_mulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_14:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB0_16
# %bb.15:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB0_16: # %_Z9stopwatchi.exit51
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z9stopwatchi # -- Begin function _Z9stopwatchi
.p2align 4, 0x90
.type _Z9stopwatchi,@function
_Z9stopwatchi: # @_Z9stopwatchi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpl $1, %edi
je .LBB1_4
# %bb.1:
testl %edi, %edi
jne .LBB1_7
# %bb.2:
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB1_3
# %bb.8:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 16
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB1_6
# %bb.5:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB1_6:
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB1_7:
.cfi_def_cfa_offset 16
movl $.Lstr.2, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB1_3:
.cfi_def_cfa_offset 16
movl $.Lstr.4, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z9stopwatchi, .Lfunc_end1-_Z9stopwatchi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__cuda_mulPiS_S_i # -- Begin function _Z23__device_stub__cuda_mulPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__cuda_mulPiS_S_i,@function
_Z23__device_stub__cuda_mulPiS_S_i: # @_Z23__device_stub__cuda_mulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cuda_mulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z23__device_stub__cuda_mulPiS_S_i, .Lfunc_end2-_Z23__device_stub__cuda_mulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__exam_mulPiS_S_i # -- Begin function _Z23__device_stub__exam_mulPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__exam_mulPiS_S_i,@function
_Z23__device_stub__exam_mulPiS_S_i: # @_Z23__device_stub__exam_mulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8exam_mulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z23__device_stub__exam_mulPiS_S_i, .Lfunc_end3-_Z23__device_stub__exam_mulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__shared_mulPiS_S_i # -- Begin function _Z25__device_stub__shared_mulPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__shared_mulPiS_S_i,@function
_Z25__device_stub__shared_mulPiS_S_i: # @_Z25__device_stub__shared_mulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10shared_mulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z25__device_stub__shared_mulPiS_S_i, .Lfunc_end4-_Z25__device_stub__shared_mulPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cuda_mulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10shared_mulPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8exam_mulPiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Multiply matrix (%dX%d ) * (%dX%d)\n"
.size .L.str, 36
.type _Z8cuda_mulPiS_S_i,@object # @_Z8cuda_mulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8cuda_mulPiS_S_i
.p2align 3, 0x0
_Z8cuda_mulPiS_S_i:
.quad _Z23__device_stub__cuda_mulPiS_S_i
.size _Z8cuda_mulPiS_S_i, 8
.type _Z8exam_mulPiS_S_i,@object # @_Z8exam_mulPiS_S_i
.globl _Z8exam_mulPiS_S_i
.p2align 3, 0x0
_Z8exam_mulPiS_S_i:
.quad _Z23__device_stub__exam_mulPiS_S_i
.size _Z8exam_mulPiS_S_i, 8
.type _Z10shared_mulPiS_S_i,@object # @_Z10shared_mulPiS_S_i
.globl _Z10shared_mulPiS_S_i
.p2align 3, 0x0
_Z10shared_mulPiS_S_i:
.quad _Z25__device_stub__shared_mulPiS_S_i
.size _Z10shared_mulPiS_S_i, 8
.type _ZZ9stopwatchiE7startTS,@object # @_ZZ9stopwatchiE7startTS
.local _ZZ9stopwatchiE7startTS
.comm _ZZ9stopwatchiE7startTS,16,8
.type _ZZ9stopwatchiE5endTS,@object # @_ZZ9stopwatchiE5endTS
.local _ZZ9stopwatchiE5endTS
.comm _ZZ9stopwatchiE5endTS,16,8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "elapsed time : % lld micros\n"
.size .L.str.4, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8cuda_mulPiS_S_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10shared_mulPiS_S_i"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8exam_mulPiS_S_i"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "cuda_mul"
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "shared_mul"
.size .Lstr.1, 11
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "wrong flag | 0 : start, 1 : end"
.size .Lstr.2, 32
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Failed to call clock_gettime"
.size .Lstr.4, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cuda_mulPiS_S_i
.addrsig_sym _Z23__device_stub__exam_mulPiS_S_i
.addrsig_sym _Z25__device_stub__shared_mulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cuda_mulPiS_S_i
.addrsig_sym _Z8exam_mulPiS_S_i
.addrsig_sym _Z10shared_mulPiS_S_i
.addrsig_sym _ZZ9stopwatchiE7startTS
.addrsig_sym _ZZ9stopwatchiE5endTS
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/scan.h>
#include <thrust/functional.h>
// #include <iomanip>
#include <iostream>
int main(int argc, char *argv[]) {
long n = atol(argv[1]);
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
thrust::host_vector<float> h_vec(n);
for (long i = 0; i < n; i++) {
h_vec[i] = 1.1;
}
thrust::device_vector<float> d_vec(h_vec.size());
thrust::device_vector<float> d_vec1(h_vec.size());
thrust::copy(h_vec.begin(), h_vec.end(), d_vec.begin());
float init = 0.0;
cudaEventRecord(start);
// No need to allocate another device vector. Do it in place
thrust::exclusive_scan(d_vec.begin(), d_vec.end(), d_vec1.begin(), init, thrust::plus<float>());
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float ms;
cudaEventElapsedTime(&ms, start, stop);
thrust::copy(d_vec1.begin(), d_vec1.end(), h_vec.begin());
//for (long i = 0; i < n; i++) {
// std::cout << setprecision(12) << h_vec[i] << " ";
//}
//std::cout << std::endl;
std::cout << h_vec[n-1] << std::endl;
std::cout << ms << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/scan.h>
#include <thrust/functional.h>
// #include <iomanip>
#include <iostream>
int main(int argc, char *argv[]) {
long n = atol(argv[1]);
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
thrust::host_vector<float> h_vec(n);
for (long i = 0; i < n; i++) {
h_vec[i] = 1.1;
}
thrust::device_vector<float> d_vec(h_vec.size());
thrust::device_vector<float> d_vec1(h_vec.size());
thrust::copy(h_vec.begin(), h_vec.end(), d_vec.begin());
float init = 0.0;
hipEventRecord(start);
// No need to allocate another device vector. Do it in place
thrust::exclusive_scan(d_vec.begin(), d_vec.end(), d_vec1.begin(), init, thrust::plus<float>());
hipEventRecord(stop);
hipEventSynchronize(stop);
float ms;
hipEventElapsedTime(&ms, start, stop);
thrust::copy(d_vec1.begin(), d_vec1.end(), h_vec.begin());
//for (long i = 0; i < n; i++) {
// std::cout << setprecision(12) << h_vec[i] << " ";
//}
//std::cout << std::endl;
std::cout << h_vec[n-1] << std::endl;
std::cout << ms << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // includes, system
#include <stdio.h>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
// Part 3 of 5: implement the kernel
__global__ void myFirstKernel(int *d_a)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
d_a[i] = blockIdx.x + threadIdx.x;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
cudaSetDevice(MYDEVICE);
// pointer for host memory
int *h_a;
// pointer for device memory
int *d_a;
// define grid and block size
int numBlocks = 8;
int numThreadsPerBlock = 8;
// Part 1 of 5: allocate host and device memory
size_t memSize = numBlocks * numThreadsPerBlock * sizeof(int);
h_a = (int *) malloc(memSize);
cudaMalloc((void **) &d_a, memSize);
// Part 2 of 5: configure and launch kernel
dim3 dimGrid( numBlocks );
dim3 dimBlock( numThreadsPerBlock );
myFirstKernel<<< dimGrid , dimBlock >>>(d_a);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
// Part 4 of 5: device to host copy
cudaMemcpy( h_a, d_a, memSize ,cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("cudaMemcpy");
// Part 5 of 5: verify the data returned to the host is correct
for (int i = 0; i < numBlocks ; i++)
{
for (int j = 0; j < numThreadsPerBlock ; j++)
{
assert(h_a[i * numThreadsPerBlock + j] == i + j);
}
}
// free device memory
cudaFree(d_a);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Correct!\n");
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(-1);
}
} | code for sm_80
Function : _Z13myFirstKernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R5.reuse, c[0x0][0x0], R0 ; /* 0x0000000005027a24 */
/* 0x041fe200078e0200 */
/*0060*/ IADD3 R5, R5, R0, RZ ; /* 0x0000000005057210 */
/* 0x000fc80007ffe0ff */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // includes, system
#include <stdio.h>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
// Part 3 of 5: implement the kernel
__global__ void myFirstKernel(int *d_a)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
d_a[i] = blockIdx.x + threadIdx.x;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
cudaSetDevice(MYDEVICE);
// pointer for host memory
int *h_a;
// pointer for device memory
int *d_a;
// define grid and block size
int numBlocks = 8;
int numThreadsPerBlock = 8;
// Part 1 of 5: allocate host and device memory
size_t memSize = numBlocks * numThreadsPerBlock * sizeof(int);
h_a = (int *) malloc(memSize);
cudaMalloc((void **) &d_a, memSize);
// Part 2 of 5: configure and launch kernel
dim3 dimGrid( numBlocks );
dim3 dimBlock( numThreadsPerBlock );
myFirstKernel<<< dimGrid , dimBlock >>>(d_a);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
// Part 4 of 5: device to host copy
cudaMemcpy( h_a, d_a, memSize ,cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("cudaMemcpy");
// Part 5 of 5: verify the data returned to the host is correct
for (int i = 0; i < numBlocks ; i++)
{
for (int j = 0; j < numThreadsPerBlock ; j++)
{
assert(h_a[i * numThreadsPerBlock + j] == i + j);
}
}
// free device memory
cudaFree(d_a);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Correct!\n");
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(-1);
}
} | .file "tmpxft_0015b402_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z33__device_stub__Z13myFirstKernelPiPi
.type _Z33__device_stub__Z13myFirstKernelPiPi, @function
_Z33__device_stub__Z13myFirstKernelPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13myFirstKernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z13myFirstKernelPiPi, .-_Z33__device_stub__Z13myFirstKernelPiPi
.globl _Z13myFirstKernelPi
.type _Z13myFirstKernelPi, @function
_Z13myFirstKernelPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13myFirstKernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13myFirstKernelPi, .-_Z13myFirstKernelPi
.section .rodata.str1.1
.LC1:
.string "kernel execution"
.LC2:
.string "cudaMemcpy"
.LC3:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $256, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $8, 16(%rsp)
movl $1, 20(%rsp)
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaThreadSynchronize@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $256, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z33__device_stub__Z13myFirstKernelPiPi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13myFirstKernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13myFirstKernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // includes, system
#include <stdio.h>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
// Part 3 of 5: implement the kernel
__global__ void myFirstKernel(int *d_a)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
d_a[i] = blockIdx.x + threadIdx.x;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
cudaSetDevice(MYDEVICE);
// pointer for host memory
int *h_a;
// pointer for device memory
int *d_a;
// define grid and block size
int numBlocks = 8;
int numThreadsPerBlock = 8;
// Part 1 of 5: allocate host and device memory
size_t memSize = numBlocks * numThreadsPerBlock * sizeof(int);
h_a = (int *) malloc(memSize);
cudaMalloc((void **) &d_a, memSize);
// Part 2 of 5: configure and launch kernel
dim3 dimGrid( numBlocks );
dim3 dimBlock( numThreadsPerBlock );
myFirstKernel<<< dimGrid , dimBlock >>>(d_a);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
// Part 4 of 5: device to host copy
cudaMemcpy( h_a, d_a, memSize ,cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("cudaMemcpy");
// Part 5 of 5: verify the data returned to the host is correct
for (int i = 0; i < numBlocks ; i++)
{
for (int j = 0; j < numThreadsPerBlock ; j++)
{
assert(h_a[i * numThreadsPerBlock + j] == i + j);
}
}
// free device memory
cudaFree(d_a);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Correct!\n");
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(-1);
}
} | // includes, system
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
// Part 3 of 5: implement the kernel
__global__ void myFirstKernel(int *d_a)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
d_a[i] = blockIdx.x + threadIdx.x;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
hipSetDevice(MYDEVICE);
// pointer for host memory
int *h_a;
// pointer for device memory
int *d_a;
// define grid and block size
int numBlocks = 8;
int numThreadsPerBlock = 8;
// Part 1 of 5: allocate host and device memory
size_t memSize = numBlocks * numThreadsPerBlock * sizeof(int);
h_a = (int *) malloc(memSize);
hipMalloc((void **) &d_a, memSize);
// Part 2 of 5: configure and launch kernel
dim3 dimGrid( numBlocks );
dim3 dimBlock( numThreadsPerBlock );
myFirstKernel<<< dimGrid , dimBlock >>>(d_a);
// block until the device has completed
hipDeviceSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
// Part 4 of 5: device to host copy
hipMemcpy( h_a, d_a, memSize ,hipMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("hipMemcpy");
// Part 5 of 5: verify the data returned to the host is correct
for (int i = 0; i < numBlocks ; i++)
{
for (int j = 0; j < numThreadsPerBlock ; j++)
{
assert(h_a[i * numThreadsPerBlock + j] == i + j);
}
}
// free device memory
hipFree(d_a);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Correct!\n");
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(-1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // includes, system
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
// Part 3 of 5: implement the kernel
__global__ void myFirstKernel(int *d_a)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
d_a[i] = blockIdx.x + threadIdx.x;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
hipSetDevice(MYDEVICE);
// pointer for host memory
int *h_a;
// pointer for device memory
int *d_a;
// define grid and block size
int numBlocks = 8;
int numThreadsPerBlock = 8;
// Part 1 of 5: allocate host and device memory
size_t memSize = numBlocks * numThreadsPerBlock * sizeof(int);
h_a = (int *) malloc(memSize);
hipMalloc((void **) &d_a, memSize);
// Part 2 of 5: configure and launch kernel
dim3 dimGrid( numBlocks );
dim3 dimBlock( numThreadsPerBlock );
myFirstKernel<<< dimGrid , dimBlock >>>(d_a);
// block until the device has completed
hipDeviceSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
// Part 4 of 5: device to host copy
hipMemcpy( h_a, d_a, memSize ,hipMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("hipMemcpy");
// Part 5 of 5: verify the data returned to the host is correct
for (int i = 0; i < numBlocks ; i++)
{
for (int j = 0; j < numThreadsPerBlock ; j++)
{
assert(h_a[i * numThreadsPerBlock + j] == i + j);
}
}
// free device memory
hipFree(d_a);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Correct!\n");
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(-1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13myFirstKernelPi
.globl _Z13myFirstKernelPi
.p2align 8
.type _Z13myFirstKernelPi,@function
_Z13myFirstKernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v3, s15, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13myFirstKernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13myFirstKernelPi, .Lfunc_end0-_Z13myFirstKernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13myFirstKernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13myFirstKernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // includes, system
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
// Part 3 of 5: implement the kernel
__global__ void myFirstKernel(int *d_a)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
d_a[i] = blockIdx.x + threadIdx.x;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
hipSetDevice(MYDEVICE);
// pointer for host memory
int *h_a;
// pointer for device memory
int *d_a;
// define grid and block size
int numBlocks = 8;
int numThreadsPerBlock = 8;
// Part 1 of 5: allocate host and device memory
size_t memSize = numBlocks * numThreadsPerBlock * sizeof(int);
h_a = (int *) malloc(memSize);
hipMalloc((void **) &d_a, memSize);
// Part 2 of 5: configure and launch kernel
dim3 dimGrid( numBlocks );
dim3 dimBlock( numThreadsPerBlock );
myFirstKernel<<< dimGrid , dimBlock >>>(d_a);
// block until the device has completed
hipDeviceSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
// Part 4 of 5: device to host copy
hipMemcpy( h_a, d_a, memSize ,hipMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("hipMemcpy");
// Part 5 of 5: verify the data returned to the host is correct
for (int i = 0; i < numBlocks ; i++)
{
for (int j = 0; j < numThreadsPerBlock ; j++)
{
assert(h_a[i * numThreadsPerBlock + j] == i + j);
}
}
// free device memory
hipFree(d_a);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Correct!\n");
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(-1);
}
} | .text
.file "kernel.hip"
.globl _Z28__device_stub__myFirstKernelPi # -- Begin function _Z28__device_stub__myFirstKernelPi
.p2align 4, 0x90
.type _Z28__device_stub__myFirstKernelPi,@function
_Z28__device_stub__myFirstKernelPi: # @_Z28__device_stub__myFirstKernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13myFirstKernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z28__device_stub__myFirstKernelPi, .Lfunc_end0-_Z28__device_stub__myFirstKernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13myFirstKernelPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_Z14checkCUDAErrorPKc.exit
movq 8(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %.preheader.preheader
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.1, %edx
.LBB1_4:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB2_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z14checkCUDAErrorPKc, .Lfunc_end2-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13myFirstKernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13myFirstKernelPi,@object # @_Z13myFirstKernelPi
.section .rodata,"a",@progbits
.globl _Z13myFirstKernelPi
.p2align 3, 0x0
_Z13myFirstKernelPi:
.quad _Z28__device_stub__myFirstKernelPi
.size _Z13myFirstKernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "kernel execution"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMemcpy"
.size .L.str.1, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13myFirstKernelPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__myFirstKernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13myFirstKernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13myFirstKernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R5.reuse, c[0x0][0x0], R0 ; /* 0x0000000005027a24 */
/* 0x041fe200078e0200 */
/*0060*/ IADD3 R5, R5, R0, RZ ; /* 0x0000000005057210 */
/* 0x000fc80007ffe0ff */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13myFirstKernelPi
.globl _Z13myFirstKernelPi
.p2align 8
.type _Z13myFirstKernelPi,@function
_Z13myFirstKernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v3, s15, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13myFirstKernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13myFirstKernelPi, .Lfunc_end0-_Z13myFirstKernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13myFirstKernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13myFirstKernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015b402_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z33__device_stub__Z13myFirstKernelPiPi
.type _Z33__device_stub__Z13myFirstKernelPiPi, @function
_Z33__device_stub__Z13myFirstKernelPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13myFirstKernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z13myFirstKernelPiPi, .-_Z33__device_stub__Z13myFirstKernelPiPi
.globl _Z13myFirstKernelPi
.type _Z13myFirstKernelPi, @function
_Z13myFirstKernelPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13myFirstKernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13myFirstKernelPi, .-_Z13myFirstKernelPi
.section .rodata.str1.1
.LC1:
.string "kernel execution"
.LC2:
.string "cudaMemcpy"
.LC3:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $256, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $8, 16(%rsp)
movl $1, 20(%rsp)
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaThreadSynchronize@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $256, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z33__device_stub__Z13myFirstKernelPiPi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13myFirstKernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13myFirstKernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z28__device_stub__myFirstKernelPi # -- Begin function _Z28__device_stub__myFirstKernelPi
.p2align 4, 0x90
.type _Z28__device_stub__myFirstKernelPi,@function
_Z28__device_stub__myFirstKernelPi: # @_Z28__device_stub__myFirstKernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13myFirstKernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z28__device_stub__myFirstKernelPi, .Lfunc_end0-_Z28__device_stub__myFirstKernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13myFirstKernelPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_Z14checkCUDAErrorPKc.exit
movq 8(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %.preheader.preheader
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %edx
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.1, %edx
.LBB1_4:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB2_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z14checkCUDAErrorPKc, .Lfunc_end2-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13myFirstKernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13myFirstKernelPi,@object # @_Z13myFirstKernelPi
.section .rodata,"a",@progbits
.globl _Z13myFirstKernelPi
.p2align 3, 0x0
_Z13myFirstKernelPi:
.quad _Z28__device_stub__myFirstKernelPi
.size _Z13myFirstKernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "kernel execution"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMemcpy"
.size .L.str.1, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13myFirstKernelPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__myFirstKernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13myFirstKernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
extern "C" __global__ void add_n(int *nums, int n, int size) {
nums[threadIdx.x] += n;
} | code for sm_80
Function : add_n
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IADD3 R5, R0, c[0x0][0x168], RZ ; /* 0x00005a0000057a10 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
extern "C" __global__ void add_n(int *nums, int n, int size) {
nums[threadIdx.x] += n;
} | .file "tmpxft_00195b0a_00000000-6_addn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5add_nPiiiPiii
.type _Z26__device_stub__Z5add_nPiiiPiii, @function
_Z26__device_stub__Z5add_nPiiiPiii:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq add_n(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z26__device_stub__Z5add_nPiiiPiii, .-_Z26__device_stub__Z5add_nPiiiPiii
.globl add_n
.type add_n, @function
add_n:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5add_nPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size add_n, .-add_n
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add_n"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add_n(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
extern "C" __global__ void add_n(int *nums, int n, int size) {
nums[threadIdx.x] += n;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
extern "C" __global__ void add_n(int *nums, int n, int size) {
nums[threadIdx.x] += n;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
extern "C" __global__ void add_n(int *nums, int n, int size) {
nums[threadIdx.x] += n;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add_n
.globl add_n
.p2align 8
.type add_n,@function
add_n:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, s0, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add_n
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add_n, .Lfunc_end0-add_n
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add_n
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: add_n.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
extern "C" __global__ void add_n(int *nums, int n, int size) {
nums[threadIdx.x] += n;
} | .text
.file "addn.hip"
.globl __device_stub__add_n # -- Begin function __device_stub__add_n
.p2align 4, 0x90
.type __device_stub__add_n,@function
__device_stub__add_n: # @__device_stub__add_n
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $add_n, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__add_n, .Lfunc_end0-__device_stub__add_n
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add_n, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add_n,@object # @add_n
.section .rodata,"a",@progbits
.globl add_n
.p2align 3, 0x0
add_n:
.quad __device_stub__add_n
.size add_n, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add_n"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add_n
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add_n
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : add_n
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IADD3 R5, R0, c[0x0][0x168], RZ ; /* 0x00005a0000057a10 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add_n
.globl add_n
.p2align 8
.type add_n,@function
add_n:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, s0, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add_n
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add_n, .Lfunc_end0-add_n
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add_n
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: add_n.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00195b0a_00000000-6_addn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5add_nPiiiPiii
.type _Z26__device_stub__Z5add_nPiiiPiii, @function
_Z26__device_stub__Z5add_nPiiiPiii:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq add_n(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z26__device_stub__Z5add_nPiiiPiii, .-_Z26__device_stub__Z5add_nPiiiPiii
.globl add_n
.type add_n, @function
add_n:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5add_nPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size add_n, .-add_n
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add_n"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add_n(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addn.hip"
.globl __device_stub__add_n # -- Begin function __device_stub__add_n
.p2align 4, 0x90
.type __device_stub__add_n,@function
__device_stub__add_n: # @__device_stub__add_n
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $add_n, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__add_n, .Lfunc_end0-__device_stub__add_n
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add_n, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add_n,@object # @add_n
.section .rodata,"a",@progbits
.globl add_n
.p2align 3, 0x0
add_n:
.quad __device_stub__add_n
.size add_n, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add_n"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add_n
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add_n
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha , int wb,int wa)
{
int th = getTid();
if(th<(ha*wb))
{
int row = th/wb;
int col = th%wb;
int i = 0 , sum = 0;
for(i = 0;i<wa;i++)
{
sum += a[row*wa+i]*b[wb*i+col];
}
c[th] = sum;
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
int hb , wb;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
printf("Enter the dimensions of second matrix \n");
scanf("%d %d",&hb,&wb);
int size1 = sizeof(int)*ha*wa;
int size2 = sizeof(int)*hb*wb;
int size3 = sizeof(int)*ha*wb;
a = (int*)malloc(ha*wa*sizeof(int));
b = (int*)malloc(hb*wb*sizeof(int));
t = (int*)malloc(ha*wb*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<hb*wb;i++)
scanf("%d",&b[i]);
cudaMalloc((void**)&d_a,size1);
cudaMalloc((void**)&d_b,size2);
cudaMalloc((void**)&d_t,size3);
cudaMemcpy(d_a,a,size1,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size2,cudaMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wb/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wb,wa);
cudaMemcpy(t,d_t,size3,cudaMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wb;j++)
printf("%d ",t[i*wb+j]);
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | code for sm_80
Function : _Z10mulElementPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha , int wb,int wa)
{
int th = getTid();
if(th<(ha*wb))
{
int row = th/wb;
int col = th%wb;
int i = 0 , sum = 0;
for(i = 0;i<wa;i++)
{
sum += a[row*wa+i]*b[wb*i+col];
}
c[th] = sum;
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
int hb , wb;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
printf("Enter the dimensions of second matrix \n");
scanf("%d %d",&hb,&wb);
int size1 = sizeof(int)*ha*wa;
int size2 = sizeof(int)*hb*wb;
int size3 = sizeof(int)*ha*wb;
a = (int*)malloc(ha*wa*sizeof(int));
b = (int*)malloc(hb*wb*sizeof(int));
t = (int*)malloc(ha*wb*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<hb*wb;i++)
scanf("%d",&b[i]);
cudaMalloc((void**)&d_a,size1);
cudaMalloc((void**)&d_b,size2);
cudaMalloc((void**)&d_t,size3);
cudaMemcpy(d_a,a,size1,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size2,cudaMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wb/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wb,wa);
cudaMemcpy(t,d_t,size3,cudaMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wb;j++)
printf("%d ",t[i*wb+j]);
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | .file "tmpxft_000450e8_00000000-6_first.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6getTidv
.type _Z6getTidv, @function
_Z6getTidv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6getTidv, .-_Z6getTidv
.globl _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii
.type _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii, @function
_Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10mulElementPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii, .-_Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii
.globl _Z10mulElementPiS_S_iii
.type _Z10mulElementPiS_S_iii, @function
_Z10mulElementPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10mulElementPiS_S_iii, .-_Z10mulElementPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter the dimensions of first matrix \n "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC2:
.string "Enter the dimensions of second matrix \n"
.section .rodata.str1.1
.LC3:
.string "Enter input matrix 1 : \n"
.LC4:
.string "%d"
.LC5:
.string "Enter input matrix 2 : \n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Enter the dimension of the grid \n"
.align 8
.LC10:
.string "The dimensions of block are : \n %d %d \n"
.section .rodata.str1.1
.LC11:
.string "Result vector is :\n"
.LC12:
.string "%d "
.LC13:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 36(%rsp), %rdx
leaq 32(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 44(%rsp), %rdx
leaq 40(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 32(%rsp), %ebx
movl 36(%rsp), %eax
movl %ebx, %r14d
imull %eax, %r14d
sall $2, %r14d
movl 40(%rsp), %ebp
movl 44(%rsp), %r12d
movl %r12d, %r13d
imull %ebp, %r13d
sall $2, %r13d
movl %ebx, %edx
imull %r12d, %edx
leal 0(,%rdx,4), %ecx
movl %ecx, 20(%rsp)
imull %ebx, %eax
movslq %eax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 24(%rsp)
imull %r12d, %ebp
movslq %ebp, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
imull %r12d, %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rsp), %eax
imull 36(%rsp), %eax
testl %eax, %eax
jle .L14
movq %r15, %r12
movl $0, %ebp
leaq .LC4(%rip), %r15
.L15:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
movl 32(%rsp), %eax
imull 36(%rsp), %eax
cmpl %ebp, %eax
jg .L15
.L14:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 40(%rsp), %eax
imull 44(%rsp), %eax
testl %eax, %eax
jle .L16
movq 8(%rsp), %r12
movl $0, %ebp
leaq .LC4(%rip), %r15
.L17:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
movl 40(%rsp), %eax
imull 44(%rsp), %eax
cmpl %ebp, %eax
jg .L17
.L16:
movslq %r14d, %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movslq %r13d, %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movslq 20(%rsp), %rbp
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 52(%rsp), %rdx
leaq 48(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 32(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 48(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC14(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC7(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L18
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC9(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L18:
cvttsd2sil %xmm3, %r12d
pxor %xmm0, %xmm0
cvtsi2sdl 44(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 52(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC14(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC7(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L19
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC9(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L19:
cvttsd2sil %xmm3, %r13d
movl %r13d, %ecx
movl %r12d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 48(%rsp), %eax
movl %eax, 80(%rsp)
movl 52(%rsp), %eax
movl %eax, 84(%rsp)
movl %r12d, 92(%rsp)
movl %r13d, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L20:
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC12(%rip), %r13
leaq .LC13(%rip), %r14
cmpl $0, 32(%rsp)
jg .L21
.L22:
movq stdin(%rip), %rdi
call getc@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl 36(%rsp), %r9d
movl 44(%rsp), %r8d
movl 32(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii
jmp .L20
.L23:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 44(%rsp), %eax
cmpl %ebp, %eax
jg .L23
.L24:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 32(%rsp)
jle .L22
.L21:
movl 44(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L23
jmp .L24
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z10mulElementPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mulElementPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1127219200
.align 8
.LC9:
.long 0
.long 1072693248
.align 8
.LC14:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha , int wb,int wa)
{
int th = getTid();
if(th<(ha*wb))
{
int row = th/wb;
int col = th%wb;
int i = 0 , sum = 0;
for(i = 0;i<wa;i++)
{
sum += a[row*wa+i]*b[wb*i+col];
}
c[th] = sum;
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
int hb , wb;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
printf("Enter the dimensions of second matrix \n");
scanf("%d %d",&hb,&wb);
int size1 = sizeof(int)*ha*wa;
int size2 = sizeof(int)*hb*wb;
int size3 = sizeof(int)*ha*wb;
a = (int*)malloc(ha*wa*sizeof(int));
b = (int*)malloc(hb*wb*sizeof(int));
t = (int*)malloc(ha*wb*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<hb*wb;i++)
scanf("%d",&b[i]);
cudaMalloc((void**)&d_a,size1);
cudaMalloc((void**)&d_b,size2);
cudaMalloc((void**)&d_t,size3);
cudaMemcpy(d_a,a,size1,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size2,cudaMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wb/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wb,wa);
cudaMemcpy(t,d_t,size3,cudaMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wb;j++)
printf("%d ",t[i*wb+j]);
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha , int wb,int wa)
{
int th = getTid();
if(th<(ha*wb))
{
int row = th/wb;
int col = th%wb;
int i = 0 , sum = 0;
for(i = 0;i<wa;i++)
{
sum += a[row*wa+i]*b[wb*i+col];
}
c[th] = sum;
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
int hb , wb;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
printf("Enter the dimensions of second matrix \n");
scanf("%d %d",&hb,&wb);
int size1 = sizeof(int)*ha*wa;
int size2 = sizeof(int)*hb*wb;
int size3 = sizeof(int)*ha*wb;
a = (int*)malloc(ha*wa*sizeof(int));
b = (int*)malloc(hb*wb*sizeof(int));
t = (int*)malloc(ha*wb*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<hb*wb;i++)
scanf("%d",&b[i]);
hipMalloc((void**)&d_a,size1);
hipMalloc((void**)&d_b,size2);
hipMalloc((void**)&d_t,size3);
hipMemcpy(d_a,a,size1,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size2,hipMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wb/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wb,wa);
hipMemcpy(t,d_t,size3,hipMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wb;j++)
printf("%d ",t[i*wb+j]);
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha , int wb,int wa)
{
int th = getTid();
if(th<(ha*wb))
{
int row = th/wb;
int col = th%wb;
int i = 0 , sum = 0;
for(i = 0;i<wa;i++)
{
sum += a[row*wa+i]*b[wb*i+col];
}
c[th] = sum;
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
int hb , wb;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
printf("Enter the dimensions of second matrix \n");
scanf("%d %d",&hb,&wb);
int size1 = sizeof(int)*ha*wa;
int size2 = sizeof(int)*hb*wb;
int size3 = sizeof(int)*ha*wb;
a = (int*)malloc(ha*wa*sizeof(int));
b = (int*)malloc(hb*wb*sizeof(int));
t = (int*)malloc(ha*wb*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<hb*wb;i++)
scanf("%d",&b[i]);
hipMalloc((void**)&d_a,size1);
hipMalloc((void**)&d_b,size2);
hipMalloc((void**)&d_t,size3);
hipMemcpy(d_a,a,size1,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size2,hipMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wb/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wb,wa);
hipMemcpy(t,d_t,size3,hipMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wb;j++)
printf("%d ",t[i*wb+j]);
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mulElementPiS_S_iii
.globl _Z10mulElementPiS_S_iii
.p2align 8
.type _Z10mulElementPiS_S_iii,@function
_Z10mulElementPiS_S_iii:
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mulElementPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mulElementPiS_S_iii, .Lfunc_end0-_Z10mulElementPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mulElementPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10mulElementPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha , int wb,int wa)
{
int th = getTid();
if(th<(ha*wb))
{
int row = th/wb;
int col = th%wb;
int i = 0 , sum = 0;
for(i = 0;i<wa;i++)
{
sum += a[row*wa+i]*b[wb*i+col];
}
c[th] = sum;
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
int hb , wb;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
printf("Enter the dimensions of second matrix \n");
scanf("%d %d",&hb,&wb);
int size1 = sizeof(int)*ha*wa;
int size2 = sizeof(int)*hb*wb;
int size3 = sizeof(int)*ha*wb;
a = (int*)malloc(ha*wa*sizeof(int));
b = (int*)malloc(hb*wb*sizeof(int));
t = (int*)malloc(ha*wb*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<hb*wb;i++)
scanf("%d",&b[i]);
hipMalloc((void**)&d_a,size1);
hipMalloc((void**)&d_b,size2);
hipMalloc((void**)&d_t,size3);
hipMemcpy(d_a,a,size1,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size2,hipMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wb/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wb,wa);
hipMemcpy(t,d_t,size3,hipMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wb;j++)
printf("%d ",t[i*wb+j]);
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.file "first.hip"
.globl _Z25__device_stub__mulElementPiS_S_iii # -- Begin function _Z25__device_stub__mulElementPiS_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__mulElementPiS_S_iii,@function
_Z25__device_stub__mulElementPiS_S_iii: # @_Z25__device_stub__mulElementPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10mulElementPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__mulElementPiS_S_iii, .Lfunc_end0-_Z25__device_stub__mulElementPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
leaq 16(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
leaq 20(%rsp), %rsi
leaq 8(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %ebx
leal (,%rbx,4), %eax
movl %eax, 48(%rsp) # 4-byte Spill
movl 16(%rsp), %r13d
movl 8(%rsp), %r15d
movl 20(%rsp), %ebp
imull %r15d, %ebp
movl %r13d, %eax
imull %ebx, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
movslq %ebp, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
imull %r15d, %ebx
movslq %ebx, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr.1, %edi
callq puts@PLT
movl 16(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq 72(%rsp), %r14 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 12(%rsp), %rax
movslq 16(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r14
cmpq %rcx, %r12
jl .LBB1_2
.LBB1_3: # %._crit_edge
movl 48(%rsp), %eax # 4-byte Reload
imull %eax, %r13d
shll $2, %ebp
imull %eax, %r15d
movl $.Lstr.2, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 20(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph44.preheader
movq 64(%rsp), %r14 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph44
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 20(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r14
cmpq %rcx, %r12
jl .LBB1_5
.LBB1_6: # %._crit_edge45
movslq %r13d, %r13
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movslq %ebp, %rbp
leaq 80(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movslq %r15d, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
leaq 28(%rsp), %rsi
leaq 24(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cvtsi2sdl 12(%rsp), %xmm0
cvtsi2sdl 28(%rsp), %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
xorps %xmm0, %xmm0
cvtsi2sdl 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdl 24(%rsp), %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r12d
movl $.L.str.7, %edi
movl %r15d, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl 28(%rsp), %eax
movl 24(%rsp), %edi
shlq $32, %rdi
orq %rax, %rdi
shlq $32, %r12
orq %r15, %r12
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 40(%rsp), %rax
movq 80(%rsp), %rcx
movq 32(%rsp), %rdx
movl 12(%rsp), %esi
movl 8(%rsp), %edi
movl 16(%rsp), %r8d
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %esi, 60(%rsp)
movl %edi, 56(%rsp)
movl %r8d, 52(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 60(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 52(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z10mulElementPiS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 32(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.4, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_14
# %bb.9: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_13: # %._crit_edge48
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_14
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_13
# %bb.11: # %.lr.ph47.preheader
# in Loop: Header=BB1_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph47
# Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_12
jmp .LBB1_13
.LBB1_14: # %._crit_edge50
movq stdin(%rip), %rdi
callq getc
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mulElementPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mulElementPiS_S_iii,@object # @_Z10mulElementPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z10mulElementPiS_S_iii
.p2align 3, 0x0
_Z10mulElementPiS_S_iii:
.quad _Z25__device_stub__mulElementPiS_S_iii
.size _Z10mulElementPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the dimensions of first matrix \n "
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "The dimensions of block are : \n %d %d \n"
.size .L.str.7, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d "
.size .L.str.9, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10mulElementPiS_S_iii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter the dimensions of second matrix "
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter input matrix 1 : "
.size .Lstr.1, 24
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Enter input matrix 2 : "
.size .Lstr.2, 24
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Enter the dimension of the grid "
.size .Lstr.3, 33
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Result vector is :"
.size .Lstr.4, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mulElementPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mulElementPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10mulElementPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mulElementPiS_S_iii
.globl _Z10mulElementPiS_S_iii
.p2align 8
.type _Z10mulElementPiS_S_iii,@function
_Z10mulElementPiS_S_iii:
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mulElementPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mulElementPiS_S_iii, .Lfunc_end0-_Z10mulElementPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mulElementPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10mulElementPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000450e8_00000000-6_first.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6getTidv
.type _Z6getTidv, @function
_Z6getTidv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6getTidv, .-_Z6getTidv
.globl _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii
.type _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii, @function
_Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10mulElementPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii, .-_Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii
.globl _Z10mulElementPiS_S_iii
.type _Z10mulElementPiS_S_iii, @function
_Z10mulElementPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10mulElementPiS_S_iii, .-_Z10mulElementPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter the dimensions of first matrix \n "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC2:
.string "Enter the dimensions of second matrix \n"
.section .rodata.str1.1
.LC3:
.string "Enter input matrix 1 : \n"
.LC4:
.string "%d"
.LC5:
.string "Enter input matrix 2 : \n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Enter the dimension of the grid \n"
.align 8
.LC10:
.string "The dimensions of block are : \n %d %d \n"
.section .rodata.str1.1
.LC11:
.string "Result vector is :\n"
.LC12:
.string "%d "
.LC13:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 36(%rsp), %rdx
leaq 32(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 44(%rsp), %rdx
leaq 40(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 32(%rsp), %ebx
movl 36(%rsp), %eax
movl %ebx, %r14d
imull %eax, %r14d
sall $2, %r14d
movl 40(%rsp), %ebp
movl 44(%rsp), %r12d
movl %r12d, %r13d
imull %ebp, %r13d
sall $2, %r13d
movl %ebx, %edx
imull %r12d, %edx
leal 0(,%rdx,4), %ecx
movl %ecx, 20(%rsp)
imull %ebx, %eax
movslq %eax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 24(%rsp)
imull %r12d, %ebp
movslq %ebp, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
imull %r12d, %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rsp), %eax
imull 36(%rsp), %eax
testl %eax, %eax
jle .L14
movq %r15, %r12
movl $0, %ebp
leaq .LC4(%rip), %r15
.L15:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
movl 32(%rsp), %eax
imull 36(%rsp), %eax
cmpl %ebp, %eax
jg .L15
.L14:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 40(%rsp), %eax
imull 44(%rsp), %eax
testl %eax, %eax
jle .L16
movq 8(%rsp), %r12
movl $0, %ebp
leaq .LC4(%rip), %r15
.L17:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
movl 40(%rsp), %eax
imull 44(%rsp), %eax
cmpl %ebp, %eax
jg .L17
.L16:
movslq %r14d, %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movslq %r13d, %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movslq 20(%rsp), %rbp
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 52(%rsp), %rdx
leaq 48(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 32(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 48(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC14(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC7(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L18
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC9(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L18:
cvttsd2sil %xmm3, %r12d
pxor %xmm0, %xmm0
cvtsi2sdl 44(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 52(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC14(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC7(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L19
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC9(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L19:
cvttsd2sil %xmm3, %r13d
movl %r13d, %ecx
movl %r12d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 48(%rsp), %eax
movl %eax, 80(%rsp)
movl 52(%rsp), %eax
movl %eax, 84(%rsp)
movl %r12d, 92(%rsp)
movl %r13d, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L20:
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC12(%rip), %r13
leaq .LC13(%rip), %r14
cmpl $0, 32(%rsp)
jg .L21
.L22:
movq stdin(%rip), %rdi
call getc@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl 36(%rsp), %r9d
movl 44(%rsp), %r8d
movl 32(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z37__device_stub__Z10mulElementPiS_S_iiiPiS_S_iii
jmp .L20
.L23:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 44(%rsp), %eax
cmpl %ebp, %eax
jg .L23
.L24:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 32(%rsp)
jle .L22
.L21:
movl 44(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L23
jmp .L24
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z10mulElementPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mulElementPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1127219200
.align 8
.LC9:
.long 0
.long 1072693248
.align 8
.LC14:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "first.hip"
.globl _Z25__device_stub__mulElementPiS_S_iii # -- Begin function _Z25__device_stub__mulElementPiS_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__mulElementPiS_S_iii,@function
_Z25__device_stub__mulElementPiS_S_iii: # @_Z25__device_stub__mulElementPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10mulElementPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__mulElementPiS_S_iii, .Lfunc_end0-_Z25__device_stub__mulElementPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
leaq 16(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
leaq 20(%rsp), %rsi
leaq 8(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %ebx
leal (,%rbx,4), %eax
movl %eax, 48(%rsp) # 4-byte Spill
movl 16(%rsp), %r13d
movl 8(%rsp), %r15d
movl 20(%rsp), %ebp
imull %r15d, %ebp
movl %r13d, %eax
imull %ebx, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
movslq %ebp, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
imull %r15d, %ebx
movslq %ebx, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr.1, %edi
callq puts@PLT
movl 16(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq 72(%rsp), %r14 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 12(%rsp), %rax
movslq 16(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r14
cmpq %rcx, %r12
jl .LBB1_2
.LBB1_3: # %._crit_edge
movl 48(%rsp), %eax # 4-byte Reload
imull %eax, %r13d
shll $2, %ebp
imull %eax, %r15d
movl $.Lstr.2, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 20(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph44.preheader
movq 64(%rsp), %r14 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph44
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 20(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r14
cmpq %rcx, %r12
jl .LBB1_5
.LBB1_6: # %._crit_edge45
movslq %r13d, %r13
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movslq %ebp, %rbp
leaq 80(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movslq %r15d, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
leaq 28(%rsp), %rsi
leaq 24(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cvtsi2sdl 12(%rsp), %xmm0
cvtsi2sdl 28(%rsp), %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
xorps %xmm0, %xmm0
cvtsi2sdl 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdl 24(%rsp), %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r12d
movl $.L.str.7, %edi
movl %r15d, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl 28(%rsp), %eax
movl 24(%rsp), %edi
shlq $32, %rdi
orq %rax, %rdi
shlq $32, %r12
orq %r15, %r12
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 40(%rsp), %rax
movq 80(%rsp), %rcx
movq 32(%rsp), %rdx
movl 12(%rsp), %esi
movl 8(%rsp), %edi
movl 16(%rsp), %r8d
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %esi, 60(%rsp)
movl %edi, 56(%rsp)
movl %r8d, 52(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 60(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 52(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z10mulElementPiS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 32(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.4, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_14
# %bb.9: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_13: # %._crit_edge48
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_14
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_13
# %bb.11: # %.lr.ph47.preheader
# in Loop: Header=BB1_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph47
# Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_12
jmp .LBB1_13
.LBB1_14: # %._crit_edge50
movq stdin(%rip), %rdi
callq getc
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mulElementPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mulElementPiS_S_iii,@object # @_Z10mulElementPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z10mulElementPiS_S_iii
.p2align 3, 0x0
_Z10mulElementPiS_S_iii:
.quad _Z25__device_stub__mulElementPiS_S_iii
.size _Z10mulElementPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the dimensions of first matrix \n "
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "The dimensions of block are : \n %d %d \n"
.size .L.str.7, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d "
.size .L.str.9, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10mulElementPiS_S_iii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter the dimensions of second matrix "
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter input matrix 1 : "
.size .Lstr.1, 24
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Enter input matrix 2 : "
.size .Lstr.2, 24
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Enter the dimension of the grid "
.size .Lstr.3, 33
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Result vector is :"
.size .Lstr.4, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mulElementPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mulElementPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#define TEST_SIZE 35
#define BLOCK_WIDTH 4
#define CEILING_DIVIDE(X, Y) (1 + (((X) - 1) / (Y)))
// Computes a blockwise exclusive sum scan
__global__ void partialScan(unsigned int *d_in,
unsigned int *d_out,
unsigned int *d_total,
size_t n)
{
__shared__ unsigned int temp[BLOCK_WIDTH];
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
temp[tx] = d_in[index];
} else { temp[tx] = 0; }
__syncthreads();
// Perform the actual scan
for(int offset = 1; offset < BLOCK_WIDTH; offset <<= 1) {
if(tx + offset < BLOCK_WIDTH) {
temp[tx + offset] += temp[tx];
}
__syncthreads();
}
// Shift when copying the result so as to make it an exclusive scan
if(tx +1 < BLOCK_WIDTH && index + 1 < n) {
d_out[index + 1] = temp[tx];
}
d_out[0] = 0;
// Store the total sum of each block
d_total[bx] = temp[BLOCK_WIDTH - 1];
}
// Compute a map on a partial scan to create a total scan from
__global__ void mapScan(unsigned int *d_array, unsigned int *d_total, size_t n) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
d_array[index] += d_total[bx];
}
}
// Compute exclusive sum scan for arbitrary sized array (device pointers as input)
void totalScan(unsigned int *d_in, unsigned int *d_out, size_t n) {
size_t numBlocks = CEILING_DIVIDE(n, BLOCK_WIDTH);
unsigned int *d_total;
cudaMalloc(&d_total, sizeof(unsigned int) * numBlocks);
cudaMemset(d_total, 0, sizeof(unsigned int) * numBlocks);
partialScan<<<numBlocks, BLOCK_WIDTH>>>(d_in, d_out, d_total, n);
if(numBlocks > 1) {
unsigned int *d_total_scanned;
cudaMalloc(&d_total_scanned, sizeof(unsigned int) * numBlocks);
cudaMemset(d_total_scanned, 0, sizeof(unsigned int) * numBlocks);
totalScan(d_total, d_total_scanned, numBlocks);
mapScan<<<numBlocks, BLOCK_WIDTH>>>(d_out, d_total_scanned, n);
cudaFree(d_total_scanned);
}
cudaFree(d_total);
}
////////////////////////////////////////////////////////////////////////////////
// Wrapper for totalScan (host pointers as input)
void totalScanHost(unsigned int *h_in, unsigned int *h_out, size_t n) {
unsigned int *d_in;
unsigned int *d_out;
size_t memsize = sizeof(unsigned int) * n;
cudaMalloc(&d_in, memsize);
cudaMalloc(&d_out, memsize);
cudaMemcpy(d_in, h_in, memsize, cudaMemcpyHostToDevice);
totalScan(d_in, d_out, n);
cudaMemcpy(h_out, d_out, memsize, cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
}
int main(int argc, char **argv) {
unsigned int *h_in;
unsigned int *h_out;
size_t memsize = sizeof(unsigned int) * TEST_SIZE;
h_in = (unsigned int*)malloc(memsize);
h_out = (unsigned int*)malloc(memsize);
// Test values 1 .. TEST_SIZE
for(int i=0; i<TEST_SIZE; i++){ h_in[i] = i+1; }
// Compute
totalScanHost(h_in, h_out, TEST_SIZE);
// Print input
printf("h_in = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_in[i]); }
printf("];\n");
// Print output
printf("h_out = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_out[i]); }
printf("];\n");
free(h_in);
free(h_out);
return 0;
} | code for sm_80
Function : _Z7mapScanPjS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, 0x4, R0 ; /* 0x0000000403007824 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0090*/ LEA R4, P0, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x040fe200078010ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0202 */
/*00c0*/ LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1405 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0100*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11partialScanPjS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x110 ; /* 0x000000d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R8, 0x4, R13 ; /* 0x0000000408007824 */
/* 0x001fe200078e020d */
/*0060*/ ISETP.GT.AND P0, PT, R13, 0x2, PT ; /* 0x000000020d00780c */
/* 0x000fc80003f04270 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f26070 */
/*0080*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0090*/ ISETP.GE.U32.AND.EX P1, PT, R3, c[0x0][0x17c], PT, P1 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f26110 */
/*00a0*/ @P1 STS [R13.X4], RZ ; /* 0x000000ff0d001388 */
/* 0x0001e20000004800 */
/*00b0*/ @P1 BRA 0x100 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00c0*/ LEA R2, P1, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078210ff */
/*00d0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P1 ; /* 0x0000590000037a11 */
/* 0x000fca00008f1403 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R13.X4], R2 ; /* 0x000000020d007388 */
/* 0x0043e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ ISETP.GT.AND P1, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fe20003f24270 */
/*0130*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fc80007ffe0ff */
/*0150*/ SHF.R.S32.HI R10, RZ, 0x1f, R5 ; /* 0x0000001fff0a7819 */
/* 0x000fe20000011405 */
/*0160*/ @!P0 LDS R2, [R13.X4] ; /* 0x000000000d028984 */
/* 0x002fe80000004800 */
/*0170*/ @!P0 LDS R3, [R13.X4+0x4] ; /* 0x000004000d038984 */
/* 0x000e640000004800 */
/*0180*/ @!P0 IMAD.IADD R2, R2, 0x1, R3 ; /* 0x0000000102028824 */
/* 0x002fca00078e0203 */
/*0190*/ @!P0 STS [R13.X4+0x4], R2 ; /* 0x000004020d008388 */
/* 0x0003e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fc80003f06070 */
/*01c0*/ ISETP.GE.U32.AND.EX P0, PT, R10, c[0x0][0x17c], PT, P0 ; /* 0x00005f000a007a0c */
/* 0x000fe20003f06100 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x002fc600078e00ff */
/*01e0*/ ISETP.GT.OR P0, PT, R13, 0x2, P0 ; /* 0x000000020d00780c */
/* 0x000fe20000704670 */
/*01f0*/ @!P1 LDS R3, [R13.X4] ; /* 0x000000000d039984 */
/* 0x000fe80000004800 */
/*0200*/ @!P1 LDS R4, [R13.X4+0x8] ; /* 0x000008000d049984 */
/* 0x000e640000004800 */
/*0210*/ @!P1 IMAD.IADD R0, R3, 0x1, R4 ; /* 0x0000000103009824 */
/* 0x002fe400078e0204 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc600078e00ff */
/*0230*/ @!P1 STS [R13.X4+0x8], R0 ; /* 0x000008000d009388 */
/* 0x000fe80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ @!P0 LEA R6, P1, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005068a11 */
/* 0x000fc800078210ff */
/*0260*/ @!P0 LEA.HI.X R7, R5, c[0x0][0x16c], R10, 0x2, P1 ; /* 0x00005b0005078a11 */
/* 0x000fe200008f140a */
/*0270*/ IMAD.WIDE R4, R8, R15, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fe200078e020f */
/*0280*/ @!P0 LDS R9, [R13.X4] ; /* 0x000000000d098984 */
/* 0x000e680000004800 */
/*0290*/ LDS R11, [0xc] ; /* 0x00000c00ff0b7984 */
/* 0x000ea80000000800 */
/*02a0*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x002fe8000c101904 */
/*02b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*02c0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x004fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#define TEST_SIZE 35
#define BLOCK_WIDTH 4
#define CEILING_DIVIDE(X, Y) (1 + (((X) - 1) / (Y)))
// Computes a blockwise exclusive sum scan
__global__ void partialScan(unsigned int *d_in,
unsigned int *d_out,
unsigned int *d_total,
size_t n)
{
__shared__ unsigned int temp[BLOCK_WIDTH];
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
temp[tx] = d_in[index];
} else { temp[tx] = 0; }
__syncthreads();
// Perform the actual scan
for(int offset = 1; offset < BLOCK_WIDTH; offset <<= 1) {
if(tx + offset < BLOCK_WIDTH) {
temp[tx + offset] += temp[tx];
}
__syncthreads();
}
// Shift when copying the result so as to make it an exclusive scan
if(tx +1 < BLOCK_WIDTH && index + 1 < n) {
d_out[index + 1] = temp[tx];
}
d_out[0] = 0;
// Store the total sum of each block
d_total[bx] = temp[BLOCK_WIDTH - 1];
}
// Compute a map on a partial scan to create a total scan from
__global__ void mapScan(unsigned int *d_array, unsigned int *d_total, size_t n) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
d_array[index] += d_total[bx];
}
}
// Compute exclusive sum scan for arbitrary sized array (device pointers as input)
void totalScan(unsigned int *d_in, unsigned int *d_out, size_t n) {
size_t numBlocks = CEILING_DIVIDE(n, BLOCK_WIDTH);
unsigned int *d_total;
cudaMalloc(&d_total, sizeof(unsigned int) * numBlocks);
cudaMemset(d_total, 0, sizeof(unsigned int) * numBlocks);
partialScan<<<numBlocks, BLOCK_WIDTH>>>(d_in, d_out, d_total, n);
if(numBlocks > 1) {
unsigned int *d_total_scanned;
cudaMalloc(&d_total_scanned, sizeof(unsigned int) * numBlocks);
cudaMemset(d_total_scanned, 0, sizeof(unsigned int) * numBlocks);
totalScan(d_total, d_total_scanned, numBlocks);
mapScan<<<numBlocks, BLOCK_WIDTH>>>(d_out, d_total_scanned, n);
cudaFree(d_total_scanned);
}
cudaFree(d_total);
}
////////////////////////////////////////////////////////////////////////////////
// Wrapper for totalScan (host pointers as input)
void totalScanHost(unsigned int *h_in, unsigned int *h_out, size_t n) {
unsigned int *d_in;
unsigned int *d_out;
size_t memsize = sizeof(unsigned int) * n;
cudaMalloc(&d_in, memsize);
cudaMalloc(&d_out, memsize);
cudaMemcpy(d_in, h_in, memsize, cudaMemcpyHostToDevice);
totalScan(d_in, d_out, n);
cudaMemcpy(h_out, d_out, memsize, cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
}
int main(int argc, char **argv) {
unsigned int *h_in;
unsigned int *h_out;
size_t memsize = sizeof(unsigned int) * TEST_SIZE;
h_in = (unsigned int*)malloc(memsize);
h_out = (unsigned int*)malloc(memsize);
// Test values 1 .. TEST_SIZE
for(int i=0; i<TEST_SIZE; i++){ h_in[i] = i+1; }
// Compute
totalScanHost(h_in, h_out, TEST_SIZE);
// Print input
printf("h_in = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_in[i]); }
printf("];\n");
// Print output
printf("h_out = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_out[i]); }
printf("];\n");
free(h_in);
free(h_out);
return 0;
} | .file "tmpxft_0008563e_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
.type _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m, @function
_Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11partialScanPjS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m, .-_Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
.globl _Z11partialScanPjS_S_m
.type _Z11partialScanPjS_S_m, @function
_Z11partialScanPjS_S_m:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11partialScanPjS_S_m, .-_Z11partialScanPjS_S_m
.globl _Z29__device_stub__Z7mapScanPjS_mPjS_m
.type _Z29__device_stub__Z7mapScanPjS_mPjS_m, @function
_Z29__device_stub__Z7mapScanPjS_mPjS_m:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mapScanPjS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z7mapScanPjS_mPjS_m, .-_Z29__device_stub__Z7mapScanPjS_mPjS_m
.globl _Z7mapScanPjS_m
.type _Z7mapScanPjS_m, @function
_Z7mapScanPjS_m:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7mapScanPjS_mPjS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7mapScanPjS_m, .-_Z7mapScanPjS_m
.globl _Z9totalScanPjS_m
.type _Z9totalScanPjS_m, @function
_Z9totalScanPjS_m:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq -1(%rdx), %rbx
shrq $2, %rbx
addq $1, %rbx
leaq 0(,%rbx,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
cmpq $1, %rbx
ja .L26
.L21:
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq %rbp, %rcx
movq (%rsp), %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
jmp .L20
.L26:
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z9totalScanPjS_m
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L22:
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L21
.L28:
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call _Z29__device_stub__Z7mapScanPjS_mPjS_m
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9totalScanPjS_m, .-_Z9totalScanPjS_m
.globl _Z13totalScanHostPjS_m
.type _Z13totalScanHostPjS_m, @function
_Z13totalScanHostPjS_m:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 0(,%rdx,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z9totalScanPjS_m
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z13totalScanHostPjS_m, .-_Z13totalScanHostPjS_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h_in = [ "
.LC1:
.string "%d "
.LC2:
.string "];\n"
.LC3:
.string "h_out = [ "
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $140, %edi
call malloc@PLT
movq %rax, %rbp
movl $140, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %eax
.L34:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $36, %rax
jne .L34
movl $35, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z13totalScanHostPjS_m
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 140(%rbp), %r14
leaq .LC1(%rip), %r12
.L35:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L35
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 140(%r13), %r14
leaq .LC1(%rip), %r12
.L36:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L36
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7mapScanPjS_m"
.LC5:
.string "_Z11partialScanPjS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mapScanPjS_m(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11partialScanPjS_S_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#define TEST_SIZE 35
#define BLOCK_WIDTH 4
#define CEILING_DIVIDE(X, Y) (1 + (((X) - 1) / (Y)))
// Computes a blockwise exclusive sum scan
__global__ void partialScan(unsigned int *d_in,
unsigned int *d_out,
unsigned int *d_total,
size_t n)
{
__shared__ unsigned int temp[BLOCK_WIDTH];
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
temp[tx] = d_in[index];
} else { temp[tx] = 0; }
__syncthreads();
// Perform the actual scan
for(int offset = 1; offset < BLOCK_WIDTH; offset <<= 1) {
if(tx + offset < BLOCK_WIDTH) {
temp[tx + offset] += temp[tx];
}
__syncthreads();
}
// Shift when copying the result so as to make it an exclusive scan
if(tx +1 < BLOCK_WIDTH && index + 1 < n) {
d_out[index + 1] = temp[tx];
}
d_out[0] = 0;
// Store the total sum of each block
d_total[bx] = temp[BLOCK_WIDTH - 1];
}
// Compute a map on a partial scan to create a total scan from
__global__ void mapScan(unsigned int *d_array, unsigned int *d_total, size_t n) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
d_array[index] += d_total[bx];
}
}
// Compute exclusive sum scan for arbitrary sized array (device pointers as input)
void totalScan(unsigned int *d_in, unsigned int *d_out, size_t n) {
size_t numBlocks = CEILING_DIVIDE(n, BLOCK_WIDTH);
unsigned int *d_total;
cudaMalloc(&d_total, sizeof(unsigned int) * numBlocks);
cudaMemset(d_total, 0, sizeof(unsigned int) * numBlocks);
partialScan<<<numBlocks, BLOCK_WIDTH>>>(d_in, d_out, d_total, n);
if(numBlocks > 1) {
unsigned int *d_total_scanned;
cudaMalloc(&d_total_scanned, sizeof(unsigned int) * numBlocks);
cudaMemset(d_total_scanned, 0, sizeof(unsigned int) * numBlocks);
totalScan(d_total, d_total_scanned, numBlocks);
mapScan<<<numBlocks, BLOCK_WIDTH>>>(d_out, d_total_scanned, n);
cudaFree(d_total_scanned);
}
cudaFree(d_total);
}
////////////////////////////////////////////////////////////////////////////////
// Wrapper for totalScan (host pointers as input)
void totalScanHost(unsigned int *h_in, unsigned int *h_out, size_t n) {
unsigned int *d_in;
unsigned int *d_out;
size_t memsize = sizeof(unsigned int) * n;
cudaMalloc(&d_in, memsize);
cudaMalloc(&d_out, memsize);
cudaMemcpy(d_in, h_in, memsize, cudaMemcpyHostToDevice);
totalScan(d_in, d_out, n);
cudaMemcpy(h_out, d_out, memsize, cudaMemcpyDeviceToHost);
cudaFree(d_in);
cudaFree(d_out);
}
int main(int argc, char **argv) {
unsigned int *h_in;
unsigned int *h_out;
size_t memsize = sizeof(unsigned int) * TEST_SIZE;
h_in = (unsigned int*)malloc(memsize);
h_out = (unsigned int*)malloc(memsize);
// Test values 1 .. TEST_SIZE
for(int i=0; i<TEST_SIZE; i++){ h_in[i] = i+1; }
// Compute
totalScanHost(h_in, h_out, TEST_SIZE);
// Print input
printf("h_in = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_in[i]); }
printf("];\n");
// Print output
printf("h_out = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_out[i]); }
printf("];\n");
free(h_in);
free(h_out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define TEST_SIZE 35
#define BLOCK_WIDTH 4
#define CEILING_DIVIDE(X, Y) (1 + (((X) - 1) / (Y)))
// Computes a blockwise exclusive sum scan
__global__ void partialScan(unsigned int *d_in,
unsigned int *d_out,
unsigned int *d_total,
size_t n)
{
__shared__ unsigned int temp[BLOCK_WIDTH];
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
temp[tx] = d_in[index];
} else { temp[tx] = 0; }
__syncthreads();
// Perform the actual scan
for(int offset = 1; offset < BLOCK_WIDTH; offset <<= 1) {
if(tx + offset < BLOCK_WIDTH) {
temp[tx + offset] += temp[tx];
}
__syncthreads();
}
// Shift when copying the result so as to make it an exclusive scan
if(tx +1 < BLOCK_WIDTH && index + 1 < n) {
d_out[index + 1] = temp[tx];
}
d_out[0] = 0;
// Store the total sum of each block
d_total[bx] = temp[BLOCK_WIDTH - 1];
}
// Compute a map on a partial scan to create a total scan from
__global__ void mapScan(unsigned int *d_array, unsigned int *d_total, size_t n) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
d_array[index] += d_total[bx];
}
}
// Compute exclusive sum scan for arbitrary sized array (device pointers as input)
void totalScan(unsigned int *d_in, unsigned int *d_out, size_t n) {
size_t numBlocks = CEILING_DIVIDE(n, BLOCK_WIDTH);
unsigned int *d_total;
hipMalloc(&d_total, sizeof(unsigned int) * numBlocks);
hipMemset(d_total, 0, sizeof(unsigned int) * numBlocks);
partialScan<<<numBlocks, BLOCK_WIDTH>>>(d_in, d_out, d_total, n);
if(numBlocks > 1) {
unsigned int *d_total_scanned;
hipMalloc(&d_total_scanned, sizeof(unsigned int) * numBlocks);
hipMemset(d_total_scanned, 0, sizeof(unsigned int) * numBlocks);
totalScan(d_total, d_total_scanned, numBlocks);
mapScan<<<numBlocks, BLOCK_WIDTH>>>(d_out, d_total_scanned, n);
hipFree(d_total_scanned);
}
hipFree(d_total);
}
////////////////////////////////////////////////////////////////////////////////
// Wrapper for totalScan (host pointers as input)
void totalScanHost(unsigned int *h_in, unsigned int *h_out, size_t n) {
unsigned int *d_in;
unsigned int *d_out;
size_t memsize = sizeof(unsigned int) * n;
hipMalloc(&d_in, memsize);
hipMalloc(&d_out, memsize);
hipMemcpy(d_in, h_in, memsize, hipMemcpyHostToDevice);
totalScan(d_in, d_out, n);
hipMemcpy(h_out, d_out, memsize, hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
}
int main(int argc, char **argv) {
unsigned int *h_in;
unsigned int *h_out;
size_t memsize = sizeof(unsigned int) * TEST_SIZE;
h_in = (unsigned int*)malloc(memsize);
h_out = (unsigned int*)malloc(memsize);
// Test values 1 .. TEST_SIZE
for(int i=0; i<TEST_SIZE; i++){ h_in[i] = i+1; }
// Compute
totalScanHost(h_in, h_out, TEST_SIZE);
// Print input
printf("h_in = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_in[i]); }
printf("];\n");
// Print output
printf("h_out = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_out[i]); }
printf("];\n");
free(h_in);
free(h_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define TEST_SIZE 35
#define BLOCK_WIDTH 4
#define CEILING_DIVIDE(X, Y) (1 + (((X) - 1) / (Y)))
// Computes a blockwise exclusive sum scan
__global__ void partialScan(unsigned int *d_in,
unsigned int *d_out,
unsigned int *d_total,
size_t n)
{
__shared__ unsigned int temp[BLOCK_WIDTH];
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
temp[tx] = d_in[index];
} else { temp[tx] = 0; }
__syncthreads();
// Perform the actual scan
for(int offset = 1; offset < BLOCK_WIDTH; offset <<= 1) {
if(tx + offset < BLOCK_WIDTH) {
temp[tx + offset] += temp[tx];
}
__syncthreads();
}
// Shift when copying the result so as to make it an exclusive scan
if(tx +1 < BLOCK_WIDTH && index + 1 < n) {
d_out[index + 1] = temp[tx];
}
d_out[0] = 0;
// Store the total sum of each block
d_total[bx] = temp[BLOCK_WIDTH - 1];
}
// Compute a map on a partial scan to create a total scan from
__global__ void mapScan(unsigned int *d_array, unsigned int *d_total, size_t n) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
d_array[index] += d_total[bx];
}
}
// Compute exclusive sum scan for arbitrary sized array (device pointers as input)
void totalScan(unsigned int *d_in, unsigned int *d_out, size_t n) {
size_t numBlocks = CEILING_DIVIDE(n, BLOCK_WIDTH);
unsigned int *d_total;
hipMalloc(&d_total, sizeof(unsigned int) * numBlocks);
hipMemset(d_total, 0, sizeof(unsigned int) * numBlocks);
partialScan<<<numBlocks, BLOCK_WIDTH>>>(d_in, d_out, d_total, n);
if(numBlocks > 1) {
unsigned int *d_total_scanned;
hipMalloc(&d_total_scanned, sizeof(unsigned int) * numBlocks);
hipMemset(d_total_scanned, 0, sizeof(unsigned int) * numBlocks);
totalScan(d_total, d_total_scanned, numBlocks);
mapScan<<<numBlocks, BLOCK_WIDTH>>>(d_out, d_total_scanned, n);
hipFree(d_total_scanned);
}
hipFree(d_total);
}
////////////////////////////////////////////////////////////////////////////////
// Wrapper for totalScan (host pointers as input)
void totalScanHost(unsigned int *h_in, unsigned int *h_out, size_t n) {
unsigned int *d_in;
unsigned int *d_out;
size_t memsize = sizeof(unsigned int) * n;
hipMalloc(&d_in, memsize);
hipMalloc(&d_out, memsize);
hipMemcpy(d_in, h_in, memsize, hipMemcpyHostToDevice);
totalScan(d_in, d_out, n);
hipMemcpy(h_out, d_out, memsize, hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
}
int main(int argc, char **argv) {
unsigned int *h_in;
unsigned int *h_out;
size_t memsize = sizeof(unsigned int) * TEST_SIZE;
h_in = (unsigned int*)malloc(memsize);
h_out = (unsigned int*)malloc(memsize);
// Test values 1 .. TEST_SIZE
for(int i=0; i<TEST_SIZE; i++){ h_in[i] = i+1; }
// Compute
totalScanHost(h_in, h_out, TEST_SIZE);
// Print input
printf("h_in = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_in[i]); }
printf("];\n");
// Print output
printf("h_out = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_out[i]); }
printf("];\n");
free(h_in);
free(h_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11partialScanPjS_S_m
.globl _Z11partialScanPjS_S_m
.p2align 8
.type _Z11partialScanPjS_S_m,@function
_Z11partialScanPjS_S_m:
s_load_b64 s[2:3], s[0:1], 0x18
s_mov_b32 s4, s15
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v1, s4, 2, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s5, 1
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s5, s5, 1
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s5, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
v_add_nc_u32_e32 v3, s5, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 4, v3
s_cbranch_execz .LBB0_3
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v2
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
ds_store_b32 v3, v4
s_branch .LBB0_3
.LBB0_6:
s_load_b64 s[6:7], s[0:1], 0x8
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
v_cmp_gt_u32_e64 s2, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0 offset:12
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_clause 0x1
global_store_b32 v0, v0, s[6:7]
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11partialScanPjS_S_m
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11partialScanPjS_S_m, .Lfunc_end0-_Z11partialScanPjS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mapScanPjS_m
.globl _Z7mapScanPjS_m
.p2align 8
.type _Z7mapScanPjS_m,@function
_Z7mapScanPjS_m:
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, s15
s_mov_b32 s3, exec_lo
v_lshl_add_u32 v0, s2, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[4:5], v[0:1]
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b32 s0, s[0:1], 0x0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mapScanPjS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mapScanPjS_m, .Lfunc_end1-_Z7mapScanPjS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11partialScanPjS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11partialScanPjS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mapScanPjS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mapScanPjS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define TEST_SIZE 35
#define BLOCK_WIDTH 4
#define CEILING_DIVIDE(X, Y) (1 + (((X) - 1) / (Y)))
// Computes a blockwise exclusive sum scan
__global__ void partialScan(unsigned int *d_in,
unsigned int *d_out,
unsigned int *d_total,
size_t n)
{
__shared__ unsigned int temp[BLOCK_WIDTH];
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
temp[tx] = d_in[index];
} else { temp[tx] = 0; }
__syncthreads();
// Perform the actual scan
for(int offset = 1; offset < BLOCK_WIDTH; offset <<= 1) {
if(tx + offset < BLOCK_WIDTH) {
temp[tx + offset] += temp[tx];
}
__syncthreads();
}
// Shift when copying the result so as to make it an exclusive scan
if(tx +1 < BLOCK_WIDTH && index + 1 < n) {
d_out[index + 1] = temp[tx];
}
d_out[0] = 0;
// Store the total sum of each block
d_total[bx] = temp[BLOCK_WIDTH - 1];
}
// Compute a map on a partial scan to create a total scan from
__global__ void mapScan(unsigned int *d_array, unsigned int *d_total, size_t n) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
if(index < n) {
d_array[index] += d_total[bx];
}
}
// Compute exclusive sum scan for arbitrary sized array (device pointers as input)
void totalScan(unsigned int *d_in, unsigned int *d_out, size_t n) {
size_t numBlocks = CEILING_DIVIDE(n, BLOCK_WIDTH);
unsigned int *d_total;
hipMalloc(&d_total, sizeof(unsigned int) * numBlocks);
hipMemset(d_total, 0, sizeof(unsigned int) * numBlocks);
partialScan<<<numBlocks, BLOCK_WIDTH>>>(d_in, d_out, d_total, n);
if(numBlocks > 1) {
unsigned int *d_total_scanned;
hipMalloc(&d_total_scanned, sizeof(unsigned int) * numBlocks);
hipMemset(d_total_scanned, 0, sizeof(unsigned int) * numBlocks);
totalScan(d_total, d_total_scanned, numBlocks);
mapScan<<<numBlocks, BLOCK_WIDTH>>>(d_out, d_total_scanned, n);
hipFree(d_total_scanned);
}
hipFree(d_total);
}
////////////////////////////////////////////////////////////////////////////////
// Wrapper for totalScan (host pointers as input)
void totalScanHost(unsigned int *h_in, unsigned int *h_out, size_t n) {
unsigned int *d_in;
unsigned int *d_out;
size_t memsize = sizeof(unsigned int) * n;
hipMalloc(&d_in, memsize);
hipMalloc(&d_out, memsize);
hipMemcpy(d_in, h_in, memsize, hipMemcpyHostToDevice);
totalScan(d_in, d_out, n);
hipMemcpy(h_out, d_out, memsize, hipMemcpyDeviceToHost);
hipFree(d_in);
hipFree(d_out);
}
int main(int argc, char **argv) {
unsigned int *h_in;
unsigned int *h_out;
size_t memsize = sizeof(unsigned int) * TEST_SIZE;
h_in = (unsigned int*)malloc(memsize);
h_out = (unsigned int*)malloc(memsize);
// Test values 1 .. TEST_SIZE
for(int i=0; i<TEST_SIZE; i++){ h_in[i] = i+1; }
// Compute
totalScanHost(h_in, h_out, TEST_SIZE);
// Print input
printf("h_in = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_in[i]); }
printf("];\n");
// Print output
printf("h_out = [ ");
for(int i=0; i<TEST_SIZE; i++){ printf("%d ", h_out[i]); }
printf("];\n");
free(h_in);
free(h_out);
return 0;
} | .text
.file "scan.hip"
.globl _Z26__device_stub__partialScanPjS_S_m # -- Begin function _Z26__device_stub__partialScanPjS_S_m
.p2align 4, 0x90
.type _Z26__device_stub__partialScanPjS_S_m,@function
_Z26__device_stub__partialScanPjS_S_m: # @_Z26__device_stub__partialScanPjS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11partialScanPjS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__partialScanPjS_S_m, .Lfunc_end0-_Z26__device_stub__partialScanPjS_S_m
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mapScanPjS_m # -- Begin function _Z22__device_stub__mapScanPjS_m
.p2align 4, 0x90
.type _Z22__device_stub__mapScanPjS_m,@function
_Z22__device_stub__mapScanPjS_m: # @_Z22__device_stub__mapScanPjS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mapScanPjS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__mapScanPjS_m, .Lfunc_end1-_Z22__device_stub__mapScanPjS_m
.cfi_endproc
# -- End function
.globl _Z9totalScanPjS_m # -- Begin function _Z9totalScanPjS_m
.p2align 4, 0x90
.type _Z9totalScanPjS_m,@function
_Z9totalScanPjS_m: # @_Z9totalScanPjS_m
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 104(%rsp) # 8-byte Spill
movq %rdi, %r14
movabsq $4294967300, %rbx # imm = 0x100000004
movq %rdx, 96(%rsp) # 8-byte Spill
leaq -1(%rdx), %r15
movq %r15, %r12
shrq $2, %r12
leaq 4(,%r12,4), %r13
incq %r12
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
movl %r12d, %eax
leaq (%rax,%rbx), %rbp
addq $-4, %rbp
movq %rbp, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_1
# %bb.2:
cmpq $4, %r15
jae .LBB2_3
jmp .LBB2_6
.LBB2_1:
movq 16(%rsp), %rax
movq %r14, 88(%rsp)
movq 104(%rsp), %rcx # 8-byte Reload
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11partialScanPjS_S_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpq $4, %r15
jb .LBB2_6
.LBB2_3:
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r12, %rdx
callq _Z9totalScanPjS_m
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967300, %rdx # imm = 0x100000004
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 8(%rsp), %rax
movq 104(%rsp), %rcx # 8-byte Reload
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7mapScanPjS_m, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 8(%rsp), %rdi
callq hipFree
.LBB2_6:
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9totalScanPjS_m, .Lfunc_end2-_Z9totalScanPjS_m
.cfi_endproc
# -- End function
.globl _Z13totalScanHostPjS_m # -- Begin function _Z13totalScanHostPjS_m
.p2align 4, 0x90
.type _Z13totalScanHostPjS_m,@function
_Z13totalScanHostPjS_m: # @_Z13totalScanHostPjS_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r12
leaq (,%rdx,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r15, %rdx
callq _Z9totalScanPjS_m
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z13totalScanHostPjS_m, .Lfunc_end3-_Z13totalScanHostPjS_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $140, %edi
callq malloc
movq %rax, %rbx
movl $140, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $35, %rcx
jne .LBB4_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $140, %esi
callq hipMalloc
movq %rsp, %rdi
movl $140, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $140, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq (%rsp), %rsi
movl $35, %edx
callq _Z9totalScanPjS_m
movq (%rsp), %rsi
movl $140, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $35, %r15
jne .LBB4_3
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $35, %r15
jne .LBB4_5
# %bb.6:
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11partialScanPjS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mapScanPjS_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11partialScanPjS_S_m,@object # @_Z11partialScanPjS_S_m
.section .rodata,"a",@progbits
.globl _Z11partialScanPjS_S_m
.p2align 3, 0x0
_Z11partialScanPjS_S_m:
.quad _Z26__device_stub__partialScanPjS_S_m
.size _Z11partialScanPjS_S_m, 8
.type _Z7mapScanPjS_m,@object # @_Z7mapScanPjS_m
.globl _Z7mapScanPjS_m
.p2align 3, 0x0
_Z7mapScanPjS_m:
.quad _Z22__device_stub__mapScanPjS_m
.size _Z7mapScanPjS_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_in = [ "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "h_out = [ "
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11partialScanPjS_S_m"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7mapScanPjS_m"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "]
.size .Lstr.1, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__partialScanPjS_S_m
.addrsig_sym _Z22__device_stub__mapScanPjS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11partialScanPjS_S_m
.addrsig_sym _Z7mapScanPjS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mapScanPjS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, 0x4, R0 ; /* 0x0000000403007824 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0090*/ LEA R4, P0, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x040fe200078010ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0202 */
/*00c0*/ LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1405 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0100*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11partialScanPjS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x110 ; /* 0x000000d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R8, 0x4, R13 ; /* 0x0000000408007824 */
/* 0x001fe200078e020d */
/*0060*/ ISETP.GT.AND P0, PT, R13, 0x2, PT ; /* 0x000000020d00780c */
/* 0x000fc80003f04270 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f26070 */
/*0080*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0090*/ ISETP.GE.U32.AND.EX P1, PT, R3, c[0x0][0x17c], PT, P1 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f26110 */
/*00a0*/ @P1 STS [R13.X4], RZ ; /* 0x000000ff0d001388 */
/* 0x0001e20000004800 */
/*00b0*/ @P1 BRA 0x100 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00c0*/ LEA R2, P1, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078210ff */
/*00d0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P1 ; /* 0x0000590000037a11 */
/* 0x000fca00008f1403 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R13.X4], R2 ; /* 0x000000020d007388 */
/* 0x0043e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ ISETP.GT.AND P1, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fe20003f24270 */
/*0130*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fc80007ffe0ff */
/*0150*/ SHF.R.S32.HI R10, RZ, 0x1f, R5 ; /* 0x0000001fff0a7819 */
/* 0x000fe20000011405 */
/*0160*/ @!P0 LDS R2, [R13.X4] ; /* 0x000000000d028984 */
/* 0x002fe80000004800 */
/*0170*/ @!P0 LDS R3, [R13.X4+0x4] ; /* 0x000004000d038984 */
/* 0x000e640000004800 */
/*0180*/ @!P0 IMAD.IADD R2, R2, 0x1, R3 ; /* 0x0000000102028824 */
/* 0x002fca00078e0203 */
/*0190*/ @!P0 STS [R13.X4+0x4], R2 ; /* 0x000004020d008388 */
/* 0x0003e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fc80003f06070 */
/*01c0*/ ISETP.GE.U32.AND.EX P0, PT, R10, c[0x0][0x17c], PT, P0 ; /* 0x00005f000a007a0c */
/* 0x000fe20003f06100 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x002fc600078e00ff */
/*01e0*/ ISETP.GT.OR P0, PT, R13, 0x2, P0 ; /* 0x000000020d00780c */
/* 0x000fe20000704670 */
/*01f0*/ @!P1 LDS R3, [R13.X4] ; /* 0x000000000d039984 */
/* 0x000fe80000004800 */
/*0200*/ @!P1 LDS R4, [R13.X4+0x8] ; /* 0x000008000d049984 */
/* 0x000e640000004800 */
/*0210*/ @!P1 IMAD.IADD R0, R3, 0x1, R4 ; /* 0x0000000103009824 */
/* 0x002fe400078e0204 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc600078e00ff */
/*0230*/ @!P1 STS [R13.X4+0x8], R0 ; /* 0x000008000d009388 */
/* 0x000fe80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ @!P0 LEA R6, P1, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005068a11 */
/* 0x000fc800078210ff */
/*0260*/ @!P0 LEA.HI.X R7, R5, c[0x0][0x16c], R10, 0x2, P1 ; /* 0x00005b0005078a11 */
/* 0x000fe200008f140a */
/*0270*/ IMAD.WIDE R4, R8, R15, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fe200078e020f */
/*0280*/ @!P0 LDS R9, [R13.X4] ; /* 0x000000000d098984 */
/* 0x000e680000004800 */
/*0290*/ LDS R11, [0xc] ; /* 0x00000c00ff0b7984 */
/* 0x000ea80000000800 */
/*02a0*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x002fe8000c101904 */
/*02b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*02c0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x004fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11partialScanPjS_S_m
.globl _Z11partialScanPjS_S_m
.p2align 8
.type _Z11partialScanPjS_S_m,@function
_Z11partialScanPjS_S_m:
s_load_b64 s[2:3], s[0:1], 0x18
s_mov_b32 s4, s15
v_mov_b32_e32 v3, 0
v_lshl_add_u32 v1, s4, 2, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s5, 1
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s5, s5, 1
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s5, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
v_add_nc_u32_e32 v3, s5, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 4, v3
s_cbranch_execz .LBB0_3
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v2
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
ds_store_b32 v3, v4
s_branch .LBB0_3
.LBB0_6:
s_load_b64 s[6:7], s[0:1], 0x8
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
v_cmp_gt_u32_e64 s2, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0 offset:12
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_clause 0x1
global_store_b32 v0, v0, s[6:7]
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11partialScanPjS_S_m
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11partialScanPjS_S_m, .Lfunc_end0-_Z11partialScanPjS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mapScanPjS_m
.globl _Z7mapScanPjS_m
.p2align 8
.type _Z7mapScanPjS_m,@function
_Z7mapScanPjS_m:
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, s15
s_mov_b32 s3, exec_lo
v_lshl_add_u32 v0, s2, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[4:5], v[0:1]
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b32 s0, s[0:1], 0x0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mapScanPjS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mapScanPjS_m, .Lfunc_end1-_Z7mapScanPjS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11partialScanPjS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11partialScanPjS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mapScanPjS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mapScanPjS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008563e_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
.type _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m, @function
_Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11partialScanPjS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m, .-_Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
.globl _Z11partialScanPjS_S_m
.type _Z11partialScanPjS_S_m, @function
_Z11partialScanPjS_S_m:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11partialScanPjS_S_m, .-_Z11partialScanPjS_S_m
.globl _Z29__device_stub__Z7mapScanPjS_mPjS_m
.type _Z29__device_stub__Z7mapScanPjS_mPjS_m, @function
_Z29__device_stub__Z7mapScanPjS_mPjS_m:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mapScanPjS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z7mapScanPjS_mPjS_m, .-_Z29__device_stub__Z7mapScanPjS_mPjS_m
.globl _Z7mapScanPjS_m
.type _Z7mapScanPjS_m, @function
_Z7mapScanPjS_m:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7mapScanPjS_mPjS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7mapScanPjS_m, .-_Z7mapScanPjS_m
.globl _Z9totalScanPjS_m
.type _Z9totalScanPjS_m, @function
_Z9totalScanPjS_m:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq -1(%rdx), %rbx
shrq $2, %rbx
addq $1, %rbx
leaq 0(,%rbx,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
cmpq $1, %rbx
ja .L26
.L21:
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq %rbp, %rcx
movq (%rsp), %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
jmp .L20
.L26:
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z9totalScanPjS_m
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L22:
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L21
.L28:
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call _Z29__device_stub__Z7mapScanPjS_mPjS_m
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9totalScanPjS_m, .-_Z9totalScanPjS_m
.globl _Z13totalScanHostPjS_m
.type _Z13totalScanHostPjS_m, @function
_Z13totalScanHostPjS_m:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 0(,%rdx,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z9totalScanPjS_m
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z13totalScanHostPjS_m, .-_Z13totalScanHostPjS_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h_in = [ "
.LC1:
.string "%d "
.LC2:
.string "];\n"
.LC3:
.string "h_out = [ "
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $140, %edi
call malloc@PLT
movq %rax, %rbp
movl $140, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %eax
.L34:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $36, %rax
jne .L34
movl $35, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z13totalScanHostPjS_m
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 140(%rbp), %r14
leaq .LC1(%rip), %r12
.L35:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L35
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 140(%r13), %r14
leaq .LC1(%rip), %r12
.L36:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L36
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7mapScanPjS_m"
.LC5:
.string "_Z11partialScanPjS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mapScanPjS_m(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11partialScanPjS_S_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan.hip"
.globl _Z26__device_stub__partialScanPjS_S_m # -- Begin function _Z26__device_stub__partialScanPjS_S_m
.p2align 4, 0x90
.type _Z26__device_stub__partialScanPjS_S_m,@function
_Z26__device_stub__partialScanPjS_S_m: # @_Z26__device_stub__partialScanPjS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11partialScanPjS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__partialScanPjS_S_m, .Lfunc_end0-_Z26__device_stub__partialScanPjS_S_m
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mapScanPjS_m # -- Begin function _Z22__device_stub__mapScanPjS_m
.p2align 4, 0x90
.type _Z22__device_stub__mapScanPjS_m,@function
_Z22__device_stub__mapScanPjS_m: # @_Z22__device_stub__mapScanPjS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mapScanPjS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__mapScanPjS_m, .Lfunc_end1-_Z22__device_stub__mapScanPjS_m
.cfi_endproc
# -- End function
.globl _Z9totalScanPjS_m # -- Begin function _Z9totalScanPjS_m
.p2align 4, 0x90
.type _Z9totalScanPjS_m,@function
_Z9totalScanPjS_m: # @_Z9totalScanPjS_m
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 104(%rsp) # 8-byte Spill
movq %rdi, %r14
movabsq $4294967300, %rbx # imm = 0x100000004
movq %rdx, 96(%rsp) # 8-byte Spill
leaq -1(%rdx), %r15
movq %r15, %r12
shrq $2, %r12
leaq 4(,%r12,4), %r13
incq %r12
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
movl %r12d, %eax
leaq (%rax,%rbx), %rbp
addq $-4, %rbp
movq %rbp, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_1
# %bb.2:
cmpq $4, %r15
jae .LBB2_3
jmp .LBB2_6
.LBB2_1:
movq 16(%rsp), %rax
movq %r14, 88(%rsp)
movq 104(%rsp), %rcx # 8-byte Reload
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11partialScanPjS_S_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpq $4, %r15
jb .LBB2_6
.LBB2_3:
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r12, %rdx
callq _Z9totalScanPjS_m
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967300, %rdx # imm = 0x100000004
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 8(%rsp), %rax
movq 104(%rsp), %rcx # 8-byte Reload
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7mapScanPjS_m, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 8(%rsp), %rdi
callq hipFree
.LBB2_6:
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9totalScanPjS_m, .Lfunc_end2-_Z9totalScanPjS_m
.cfi_endproc
# -- End function
.globl _Z13totalScanHostPjS_m # -- Begin function _Z13totalScanHostPjS_m
.p2align 4, 0x90
.type _Z13totalScanHostPjS_m,@function
_Z13totalScanHostPjS_m: # @_Z13totalScanHostPjS_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r12
leaq (,%rdx,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r15, %rdx
callq _Z9totalScanPjS_m
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z13totalScanHostPjS_m, .Lfunc_end3-_Z13totalScanHostPjS_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $140, %edi
callq malloc
movq %rax, %rbx
movl $140, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $35, %rcx
jne .LBB4_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $140, %esi
callq hipMalloc
movq %rsp, %rdi
movl $140, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $140, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq (%rsp), %rsi
movl $35, %edx
callq _Z9totalScanPjS_m
movq (%rsp), %rsi
movl $140, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $35, %r15
jne .LBB4_3
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $35, %r15
jne .LBB4_5
# %bb.6:
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11partialScanPjS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mapScanPjS_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11partialScanPjS_S_m,@object # @_Z11partialScanPjS_S_m
.section .rodata,"a",@progbits
.globl _Z11partialScanPjS_S_m
.p2align 3, 0x0
_Z11partialScanPjS_S_m:
.quad _Z26__device_stub__partialScanPjS_S_m
.size _Z11partialScanPjS_S_m, 8
.type _Z7mapScanPjS_m,@object # @_Z7mapScanPjS_m
.globl _Z7mapScanPjS_m
.p2align 3, 0x0
_Z7mapScanPjS_m:
.quad _Z22__device_stub__mapScanPjS_m
.size _Z7mapScanPjS_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_in = [ "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "h_out = [ "
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11partialScanPjS_S_m"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7mapScanPjS_m"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "]
.size .Lstr.1, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__partialScanPjS_S_m
.addrsig_sym _Z22__device_stub__mapScanPjS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11partialScanPjS_S_m
.addrsig_sym _Z7mapScanPjS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //xfail:BOOGIE_ERROR
//--blockDim=1024 --gridDim=1 --no-inline
//error: possible null pointer access
#include <stdio.h>
#include <assert.h>
#include <cuda.h>
#define N 2//8
#define tid (blockIdx.x * blockDim.x + threadIdx.x)
__device__ float multiplyByTwo(float *v, unsigned int index)
{
return v[index] * 2.0f;
}
__device__ float divideByTwo(float *v, unsigned int index)
{
return v[index] * 0.5f;
}
typedef float(*funcType)(float*, unsigned int);
__global__ void foo(float *v)
{
funcType f = (funcType)3; // it's a null pointer
v[tid] = (*f)(v, tid);
} | code for sm_80
Function : _Z3fooPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe40000000f00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3 ; /* 0x00000003ff087424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*00a0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc80000000f00 */
/*00c0*/ CALL.REL.NOINC R8 0x0 ; /* 0xffffff3008007344 */
/* 0x000fea0003c3ffff */
/*00d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*00f0*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101924 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //xfail:BOOGIE_ERROR
//--blockDim=1024 --gridDim=1 --no-inline
//error: possible null pointer access
#include <stdio.h>
#include <assert.h>
#include <cuda.h>
#define N 2//8
#define tid (blockIdx.x * blockDim.x + threadIdx.x)
__device__ float multiplyByTwo(float *v, unsigned int index)
{
return v[index] * 2.0f;
}
__device__ float divideByTwo(float *v, unsigned int index)
{
return v[index] * 0.5f;
}
typedef float(*funcType)(float*, unsigned int);
__global__ void foo(float *v)
{
funcType f = (funcType)3; // it's a null pointer
v[tid] = (*f)(v, tid);
} | .file "tmpxft_0002196b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13multiplyByTwoPfj
.type _Z13multiplyByTwoPfj, @function
_Z13multiplyByTwoPfj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13multiplyByTwoPfj, .-_Z13multiplyByTwoPfj
.globl _Z11divideByTwoPfj
.type _Z11divideByTwoPfj, @function
_Z11divideByTwoPfj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11divideByTwoPfj, .-_Z11divideByTwoPfj
.globl _Z22__device_stub__Z3fooPfPf
.type _Z22__device_stub__Z3fooPfPf, @function
_Z22__device_stub__Z3fooPfPf:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z22__device_stub__Z3fooPfPf, .-_Z22__device_stub__Z3fooPfPf
.globl _Z3fooPf
.type _Z3fooPf, @function
_Z3fooPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3fooPf, .-_Z3fooPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //xfail:BOOGIE_ERROR
//--blockDim=1024 --gridDim=1 --no-inline
//error: possible null pointer access
#include <stdio.h>
#include <assert.h>
#include <cuda.h>
#define N 2//8
#define tid (blockIdx.x * blockDim.x + threadIdx.x)
__device__ float multiplyByTwo(float *v, unsigned int index)
{
return v[index] * 2.0f;
}
__device__ float divideByTwo(float *v, unsigned int index)
{
return v[index] * 0.5f;
}
typedef float(*funcType)(float*, unsigned int);
__global__ void foo(float *v)
{
funcType f = (funcType)3; // it's a null pointer
v[tid] = (*f)(v, tid);
} | //xfail:BOOGIE_ERROR
//--blockDim=1024 --gridDim=1 --no-inline
//error: possible null pointer access
#include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 2//8
#define tid (blockIdx.x * blockDim.x + threadIdx.x)
__device__ float multiplyByTwo(float *v, unsigned int index)
{
return v[index] * 2.0f;
}
__device__ float divideByTwo(float *v, unsigned int index)
{
return v[index] * 0.5f;
}
typedef float(*funcType)(float*, unsigned int);
__global__ void foo(float *v)
{
funcType f = (funcType)3; // it's a null pointer
v[tid] = (*f)(v, tid);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //xfail:BOOGIE_ERROR
//--blockDim=1024 --gridDim=1 --no-inline
//error: possible null pointer access
#include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 2//8
#define tid (blockIdx.x * blockDim.x + threadIdx.x)
__device__ float multiplyByTwo(float *v, unsigned int index)
{
return v[index] * 2.0f;
}
__device__ float divideByTwo(float *v, unsigned int index)
{
return v[index] * 0.5f;
}
typedef float(*funcType)(float*, unsigned int);
__global__ void foo(float *v)
{
funcType f = (funcType)3; // it's a null pointer
v[tid] = (*f)(v, tid);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPf
.globl _Z3fooPf
.p2align 8
.type _Z3fooPf,@function
_Z3fooPf:
s_mov_b64 s[10:11], s[4:5]
s_clause 0x1
s_load_b32 s4, s[2:3], 0x14
s_load_b64 s[34:35], s[2:3], 0x0
v_and_b32_e32 v1, 0x3ff, v0
s_mov_b32 s12, s13
v_mov_b32_e32 v31, v0
s_mov_b32 s13, s14
s_mov_b32 s14, s15
s_mov_b32 s32, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
v_mov_b32_e32 v0, s34
v_mad_u64_u32 v[40:41], null, s12, s4, v[1:2]
v_mov_b32_e32 v1, s35
s_add_u32 s8, s2, 8
s_addc_u32 s9, s3, 0
s_mov_b64 s[4:5], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v40
s_swappc_b64 s[30:31], 3
v_mov_b32_e32 v41, 0
v_lshlrev_b64 v[1:2], 2, v[40:41]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s34, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 1
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 1
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 42
.amdhsa_next_free_sgpr 36
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPf, .Lfunc_end0-_Z3fooPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
- .offset: 88
.size: 8
.value_kind: hidden_hostcall_buffer
- .offset: 96
.size: 8
.value_kind: hidden_multigrid_sync_arg
- .offset: 104
.size: 8
.value_kind: hidden_heap_v1
- .offset: 112
.size: 8
.value_kind: hidden_default_queue
- .offset: 208
.size: 8
.value_kind: hidden_queue_ptr
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPf
.private_segment_fixed_size: 0
.sgpr_count: 38
.sgpr_spill_count: 0
.symbol: _Z3fooPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: true
.vgpr_count: 42
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //xfail:BOOGIE_ERROR
//--blockDim=1024 --gridDim=1 --no-inline
//error: possible null pointer access
#include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 2//8
#define tid (blockIdx.x * blockDim.x + threadIdx.x)
__device__ float multiplyByTwo(float *v, unsigned int index)
{
return v[index] * 2.0f;
}
__device__ float divideByTwo(float *v, unsigned int index)
{
return v[index] * 0.5f;
}
typedef float(*funcType)(float*, unsigned int);
__global__ void foo(float *v)
{
funcType f = (funcType)3; // it's a null pointer
v[tid] = (*f)(v, tid);
} | .text
.file "main.hip"
.globl _Z18__device_stub__fooPf # -- Begin function _Z18__device_stub__fooPf
.p2align 4, 0x90
.type _Z18__device_stub__fooPf,@function
_Z18__device_stub__fooPf: # @_Z18__device_stub__fooPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPf, .Lfunc_end0-_Z18__device_stub__fooPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPf,@object # @_Z3fooPf
.section .rodata,"a",@progbits
.globl _Z3fooPf
.p2align 3, 0x0
_Z3fooPf:
.quad _Z18__device_stub__fooPf
.size _Z3fooPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPf"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fooPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe40000000f00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3 ; /* 0x00000003ff087424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*00a0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc80000000f00 */
/*00c0*/ CALL.REL.NOINC R8 0x0 ; /* 0xffffff3008007344 */
/* 0x000fea0003c3ffff */
/*00d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*00f0*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101924 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPf
.globl _Z3fooPf
.p2align 8
.type _Z3fooPf,@function
_Z3fooPf:
s_mov_b64 s[10:11], s[4:5]
s_clause 0x1
s_load_b32 s4, s[2:3], 0x14
s_load_b64 s[34:35], s[2:3], 0x0
v_and_b32_e32 v1, 0x3ff, v0
s_mov_b32 s12, s13
v_mov_b32_e32 v31, v0
s_mov_b32 s13, s14
s_mov_b32 s14, s15
s_mov_b32 s32, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
v_mov_b32_e32 v0, s34
v_mad_u64_u32 v[40:41], null, s12, s4, v[1:2]
v_mov_b32_e32 v1, s35
s_add_u32 s8, s2, 8
s_addc_u32 s9, s3, 0
s_mov_b64 s[4:5], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v40
s_swappc_b64 s[30:31], 3
v_mov_b32_e32 v41, 0
v_lshlrev_b64 v[1:2], 2, v[40:41]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s34, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 1
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 1
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 42
.amdhsa_next_free_sgpr 36
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPf, .Lfunc_end0-_Z3fooPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
- .offset: 88
.size: 8
.value_kind: hidden_hostcall_buffer
- .offset: 96
.size: 8
.value_kind: hidden_multigrid_sync_arg
- .offset: 104
.size: 8
.value_kind: hidden_heap_v1
- .offset: 112
.size: 8
.value_kind: hidden_default_queue
- .offset: 208
.size: 8
.value_kind: hidden_queue_ptr
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPf
.private_segment_fixed_size: 0
.sgpr_count: 38
.sgpr_spill_count: 0
.symbol: _Z3fooPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: true
.vgpr_count: 42
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002196b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13multiplyByTwoPfj
.type _Z13multiplyByTwoPfj, @function
_Z13multiplyByTwoPfj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13multiplyByTwoPfj, .-_Z13multiplyByTwoPfj
.globl _Z11divideByTwoPfj
.type _Z11divideByTwoPfj, @function
_Z11divideByTwoPfj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11divideByTwoPfj, .-_Z11divideByTwoPfj
.globl _Z22__device_stub__Z3fooPfPf
.type _Z22__device_stub__Z3fooPfPf, @function
_Z22__device_stub__Z3fooPfPf:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z22__device_stub__Z3fooPfPf, .-_Z22__device_stub__Z3fooPfPf
.globl _Z3fooPf
.type _Z3fooPf, @function
_Z3fooPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3fooPf, .-_Z3fooPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z18__device_stub__fooPf # -- Begin function _Z18__device_stub__fooPf
.p2align 4, 0x90
.type _Z18__device_stub__fooPf,@function
_Z18__device_stub__fooPf: # @_Z18__device_stub__fooPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPf, .Lfunc_end0-_Z18__device_stub__fooPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPf,@object # @_Z3fooPf
.section .rodata,"a",@progbits
.globl _Z3fooPf
.p2align 3, 0x0
_Z3fooPf:
.quad _Z18__device_stub__fooPf
.size _Z3fooPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPf"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "curand_kernel.h"
#include <cuda.h>
#include <curand.h>
#include <iostream>
#include <numeric>
using namespace std;
const long steps = 1 << 21;
__global__ void belongs_circle(double* x, double* y, double* result) {
const int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= steps)
return;
if (((x[tid] - 0.5) * (x[tid] - 0.5)) + ((y[tid] - 0.5) * (y[tid] - 0.5)) <= (0.5 * 0.5)) {
result[tid] = 1;
} else {
result[tid] = 0;
}
}
int main() {
const long size = steps * sizeof(double);
long blockSize = 256;
long numBlocks = (steps + blockSize - 1) / blockSize;
curandGenerator_t gen;
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
curandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
double *result, *x, *y;
cudaMalloc(&result, size);
cudaMalloc(&x, size);
cudaMalloc(&y, size);
curandGenerateUniformDouble(gen, x, steps);
curandGenerateUniformDouble(gen, y, steps);
belongs_circle <<<numBlocks, blockSize>>>(x, y, result);
double check[steps];
cudaMemcpy(check, result, size, cudaMemcpyDeviceToHost);
double sum = 0;
for (long i = 0; i < steps; ++i) {
sum += check[i];
}
cout << "Sum is " << sum << endl;
cout << "Pi is " << 4 * sum / steps << endl;
cudaFree(result);
cudaFree(x);
cudaFree(y);
return 0;
} | code for sm_80
Function : _Z14belongs_circlePdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x1fffff, PT ; /* 0x001fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e020b */
/*00a0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ DADD R8, R6, -0.5 ; /* 0xbfe0000006087429 */
/* 0x004e080000000000 */
/*00d0*/ DADD R4, R2, -0.5 ; /* 0xbfe0000002047429 */
/* 0x008fc80000000000 */
/*00e0*/ DMUL R8, R8, R8 ; /* 0x0000000808087228 */
/* 0x001e0c0000000000 */
/*00f0*/ DFMA R8, R4, R4, R8 ; /* 0x000000040408722b */
/* 0x0010640000000008 */
/*0100*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x001fc800078e020b */
/*0110*/ DSETP.GTU.AND P0, PT, R8, 0.25, PT ; /* 0x3fd000000800742a */
/* 0x002e1c0003f0c000 */
/*0120*/ @!P0 MOV R8, 0x0 ; /* 0x0000000000088802 */
/* 0x001fe40000000f00 */
/*0130*/ @!P0 MOV R9, 0x3ff00000 ; /* 0x3ff0000000098802 */
/* 0x000fca0000000f00 */
/*0140*/ @!P0 STG.E.64 [R4.64], R8 ; /* 0x0000000804008986 */
/* 0x0001e2000c101b04 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101b04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "curand_kernel.h"
#include <cuda.h>
#include <curand.h>
#include <iostream>
#include <numeric>
using namespace std;
const long steps = 1 << 21;
__global__ void belongs_circle(double* x, double* y, double* result) {
const int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= steps)
return;
if (((x[tid] - 0.5) * (x[tid] - 0.5)) + ((y[tid] - 0.5) * (y[tid] - 0.5)) <= (0.5 * 0.5)) {
result[tid] = 1;
} else {
result[tid] = 0;
}
}
int main() {
const long size = steps * sizeof(double);
long blockSize = 256;
long numBlocks = (steps + blockSize - 1) / blockSize;
curandGenerator_t gen;
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
curandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
double *result, *x, *y;
cudaMalloc(&result, size);
cudaMalloc(&x, size);
cudaMalloc(&y, size);
curandGenerateUniformDouble(gen, x, steps);
curandGenerateUniformDouble(gen, y, steps);
belongs_circle <<<numBlocks, blockSize>>>(x, y, result);
double check[steps];
cudaMemcpy(check, result, size, cudaMemcpyDeviceToHost);
double sum = 0;
for (long i = 0; i < steps; ++i) {
sum += check[i];
}
cout << "Sum is " << sum << endl;
cout << "Pi is " << 4 * sum / steps << endl;
cudaFree(result);
cudaFree(x);
cudaFree(y);
return 0;
} | .file "tmpxft_0005e9bb_00000000-6_Pi.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3925:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3925:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_
.type _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_, @function
_Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_:
.LFB3947:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14belongs_circlePdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3947:
.size _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_, .-_Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_
.globl _Z14belongs_circlePdS_S_
.type _Z14belongs_circlePdS_S_, @function
_Z14belongs_circlePdS_S_:
.LFB3948:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3948:
.size _Z14belongs_circlePdS_S_, .-_Z14belongs_circlePdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Sum is "
.LC2:
.string "Pi is "
.text
.globl main
.type main, @function
main:
.LFB3922:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -16777216(%rsp), %r11
.cfi_def_cfa 11, 16777240
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 16777328
movq %fs:40, %rax
movq %rax, 16777288(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $100, %esi
call curandCreateGenerator@PLT
movl $1234, %esi
movq 8(%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $2097152, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call curandGenerateUniformDouble@PLT
movl $2097152, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call curandGenerateUniformDouble@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $8192, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $16777216, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 16777280(%rsp), %rdx
movl $0x000000000, %ebx
.L13:
movq %rbx, %xmm1
addsd (%rax), %xmm1
movq %xmm1, %rbx
addq $8, %rax
cmpq %rdx, %rax
jne .L13
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
mulsd .LC3(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 16777288(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $16777304, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3922:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z14belongs_circlePdS_S_"
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3950:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14belongs_circlePdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1074790400
.align 8
.LC4:
.long 0
.long 1050673152
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "curand_kernel.h"
#include <cuda.h>
#include <curand.h>
#include <iostream>
#include <numeric>
using namespace std;
const long steps = 1 << 21;
__global__ void belongs_circle(double* x, double* y, double* result) {
const int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= steps)
return;
if (((x[tid] - 0.5) * (x[tid] - 0.5)) + ((y[tid] - 0.5) * (y[tid] - 0.5)) <= (0.5 * 0.5)) {
result[tid] = 1;
} else {
result[tid] = 0;
}
}
int main() {
const long size = steps * sizeof(double);
long blockSize = 256;
long numBlocks = (steps + blockSize - 1) / blockSize;
curandGenerator_t gen;
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
curandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
double *result, *x, *y;
cudaMalloc(&result, size);
cudaMalloc(&x, size);
cudaMalloc(&y, size);
curandGenerateUniformDouble(gen, x, steps);
curandGenerateUniformDouble(gen, y, steps);
belongs_circle <<<numBlocks, blockSize>>>(x, y, result);
double check[steps];
cudaMemcpy(check, result, size, cudaMemcpyDeviceToHost);
double sum = 0;
for (long i = 0; i < steps; ++i) {
sum += check[i];
}
cout << "Sum is " << sum << endl;
cout << "Pi is " << 4 * sum / steps << endl;
cudaFree(result);
cudaFree(x);
cudaFree(y);
return 0;
} | #include "hip/hip_runtime.h"
#include "hiprand/hiprand_kernel.h"
#include <hiprand/hiprand.h>
#include <iostream>
#include <numeric>
using namespace std;
const long steps = 1 << 21;
__global__ void belongs_circle(double* x, double* y, double* result) {
const int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= steps)
return;
if (((x[tid] - 0.5) * (x[tid] - 0.5)) + ((y[tid] - 0.5) * (y[tid] - 0.5)) <= (0.5 * 0.5)) {
result[tid] = 1;
} else {
result[tid] = 0;
}
}
int main() {
const long size = steps * sizeof(double);
long blockSize = 256;
long numBlocks = (steps + blockSize - 1) / blockSize;
hiprandGenerator_t gen;
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
hiprandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
double *result, *x, *y;
hipMalloc(&result, size);
hipMalloc(&x, size);
hipMalloc(&y, size);
hiprandGenerateUniformDouble(gen, x, steps);
hiprandGenerateUniformDouble(gen, y, steps);
belongs_circle <<<numBlocks, blockSize>>>(x, y, result);
double check[steps];
hipMemcpy(check, result, size, hipMemcpyDeviceToHost);
double sum = 0;
for (long i = 0; i < steps; ++i) {
sum += check[i];
}
cout << "Sum is " << sum << endl;
cout << "Pi is " << 4 * sum / steps << endl;
hipFree(result);
hipFree(x);
hipFree(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "hiprand/hiprand_kernel.h"
#include <hiprand/hiprand.h>
#include <iostream>
#include <numeric>
using namespace std;
const long steps = 1 << 21;
__global__ void belongs_circle(double* x, double* y, double* result) {
const int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= steps)
return;
if (((x[tid] - 0.5) * (x[tid] - 0.5)) + ((y[tid] - 0.5) * (y[tid] - 0.5)) <= (0.5 * 0.5)) {
result[tid] = 1;
} else {
result[tid] = 0;
}
}
int main() {
const long size = steps * sizeof(double);
long blockSize = 256;
long numBlocks = (steps + blockSize - 1) / blockSize;
hiprandGenerator_t gen;
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
hiprandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
double *result, *x, *y;
hipMalloc(&result, size);
hipMalloc(&x, size);
hipMalloc(&y, size);
hiprandGenerateUniformDouble(gen, x, steps);
hiprandGenerateUniformDouble(gen, y, steps);
belongs_circle <<<numBlocks, blockSize>>>(x, y, result);
double check[steps];
hipMemcpy(check, result, size, hipMemcpyDeviceToHost);
double sum = 0;
for (long i = 0; i < steps; ++i) {
sum += check[i];
}
cout << "Sum is " << sum << endl;
cout << "Pi is " << 4 * sum / steps << endl;
hipFree(result);
hipFree(x);
hipFree(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14belongs_circlePdS_S_
.globl _Z14belongs_circlePdS_S_
.p2align 8
.type _Z14belongs_circlePdS_S_,@function
_Z14belongs_circlePdS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x200000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], -0.5
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], -0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[2:3]
v_fma_f64 v[2:3], v[4:5], v[4:5], v[2:3]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_nge_f64_e32 vcc_lo, 0x3fd00000, v[2:3]
v_cndmask_b32_e64 v5, 0x3ff00000, 0, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14belongs_circlePdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14belongs_circlePdS_S_, .Lfunc_end0-_Z14belongs_circlePdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14belongs_circlePdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14belongs_circlePdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "hiprand/hiprand_kernel.h"
#include <hiprand/hiprand.h>
#include <iostream>
#include <numeric>
using namespace std;
const long steps = 1 << 21;
__global__ void belongs_circle(double* x, double* y, double* result) {
const int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= steps)
return;
if (((x[tid] - 0.5) * (x[tid] - 0.5)) + ((y[tid] - 0.5) * (y[tid] - 0.5)) <= (0.5 * 0.5)) {
result[tid] = 1;
} else {
result[tid] = 0;
}
}
int main() {
const long size = steps * sizeof(double);
long blockSize = 256;
long numBlocks = (steps + blockSize - 1) / blockSize;
hiprandGenerator_t gen;
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
hiprandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
double *result, *x, *y;
hipMalloc(&result, size);
hipMalloc(&x, size);
hipMalloc(&y, size);
hiprandGenerateUniformDouble(gen, x, steps);
hiprandGenerateUniformDouble(gen, y, steps);
belongs_circle <<<numBlocks, blockSize>>>(x, y, result);
double check[steps];
hipMemcpy(check, result, size, hipMemcpyDeviceToHost);
double sum = 0;
for (long i = 0; i < steps; ++i) {
sum += check[i];
}
cout << "Sum is " << sum << endl;
cout << "Pi is " << 4 * sum / steps << endl;
hipFree(result);
hipFree(x);
hipFree(y);
return 0;
} | .text
.file "Pi.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__belongs_circlePdS_S_ # -- Begin function _Z29__device_stub__belongs_circlePdS_S_
.p2align 4, 0x90
.type _Z29__device_stub__belongs_circlePdS_S_,@function
_Z29__device_stub__belongs_circlePdS_S_: # @_Z29__device_stub__belongs_circlePdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14belongs_circlePdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__belongs_circlePdS_S_, .Lfunc_end0-_Z29__device_stub__belongs_circlePdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4010000000000000 # double 4
.LCPI1_1:
.quad 0x3ea0000000000000 # double 4.76837158203125E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $16777336, %rsp # imm = 0x1000078
.cfi_def_cfa_offset 16777360
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
movq 24(%rsp), %rdi
movl $1234, %esi # imm = 0x4D2
callq hiprandSetPseudoRandomGeneratorSeed
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 24(%rsp), %rdi
movq 8(%rsp), %rsi
movl $2097152, %edx # imm = 0x200000
callq hiprandGenerateUniformDouble
movq 24(%rsp), %rdi
movq (%rsp), %rsi
movl $2097152, %edx # imm = 0x200000
callq hiprandGenerateUniformDouble
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 7936(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14belongs_circlePdS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addsd 112(%rsp,%rax,8), %xmm0
incq %rax
cmpq $2097152, %rax # imm = 0x200000
jne .LBB1_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
movsd %xmm0, 32(%rsp) # 8-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $16777336, %rsp # imm = 0x1000078
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 16777360
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14belongs_circlePdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14belongs_circlePdS_S_,@object # @_Z14belongs_circlePdS_S_
.section .rodata,"a",@progbits
.globl _Z14belongs_circlePdS_S_
.p2align 3, 0x0
_Z14belongs_circlePdS_S_:
.quad _Z29__device_stub__belongs_circlePdS_S_
.size _Z14belongs_circlePdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Sum is "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Pi is "
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14belongs_circlePdS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__belongs_circlePdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14belongs_circlePdS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14belongs_circlePdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x1fffff, PT ; /* 0x001fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e020b */
/*00a0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ DADD R8, R6, -0.5 ; /* 0xbfe0000006087429 */
/* 0x004e080000000000 */
/*00d0*/ DADD R4, R2, -0.5 ; /* 0xbfe0000002047429 */
/* 0x008fc80000000000 */
/*00e0*/ DMUL R8, R8, R8 ; /* 0x0000000808087228 */
/* 0x001e0c0000000000 */
/*00f0*/ DFMA R8, R4, R4, R8 ; /* 0x000000040408722b */
/* 0x0010640000000008 */
/*0100*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x001fc800078e020b */
/*0110*/ DSETP.GTU.AND P0, PT, R8, 0.25, PT ; /* 0x3fd000000800742a */
/* 0x002e1c0003f0c000 */
/*0120*/ @!P0 MOV R8, 0x0 ; /* 0x0000000000088802 */
/* 0x001fe40000000f00 */
/*0130*/ @!P0 MOV R9, 0x3ff00000 ; /* 0x3ff0000000098802 */
/* 0x000fca0000000f00 */
/*0140*/ @!P0 STG.E.64 [R4.64], R8 ; /* 0x0000000804008986 */
/* 0x0001e2000c101b04 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101b04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14belongs_circlePdS_S_
.globl _Z14belongs_circlePdS_S_
.p2align 8
.type _Z14belongs_circlePdS_S_,@function
_Z14belongs_circlePdS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x200000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], -0.5
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], -0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[2:3]
v_fma_f64 v[2:3], v[4:5], v[4:5], v[2:3]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_nge_f64_e32 vcc_lo, 0x3fd00000, v[2:3]
v_cndmask_b32_e64 v5, 0x3ff00000, 0, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14belongs_circlePdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14belongs_circlePdS_S_, .Lfunc_end0-_Z14belongs_circlePdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14belongs_circlePdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14belongs_circlePdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005e9bb_00000000-6_Pi.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3925:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3925:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_
.type _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_, @function
_Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_:
.LFB3947:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14belongs_circlePdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3947:
.size _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_, .-_Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_
.globl _Z14belongs_circlePdS_S_
.type _Z14belongs_circlePdS_S_, @function
_Z14belongs_circlePdS_S_:
.LFB3948:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3948:
.size _Z14belongs_circlePdS_S_, .-_Z14belongs_circlePdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Sum is "
.LC2:
.string "Pi is "
.text
.globl main
.type main, @function
main:
.LFB3922:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -16777216(%rsp), %r11
.cfi_def_cfa 11, 16777240
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 16777328
movq %fs:40, %rax
movq %rax, 16777288(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $100, %esi
call curandCreateGenerator@PLT
movl $1234, %esi
movq 8(%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $2097152, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call curandGenerateUniformDouble@PLT
movl $2097152, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call curandGenerateUniformDouble@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $8192, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $16777216, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 16777280(%rsp), %rdx
movl $0x000000000, %ebx
.L13:
movq %rbx, %xmm1
addsd (%rax), %xmm1
movq %xmm1, %rbx
addq $8, %rax
cmpq %rdx, %rax
jne .L13
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
mulsd .LC3(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 16777288(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $16777304, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z14belongs_circlePdS_S_PdS_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3922:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z14belongs_circlePdS_S_"
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3950:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z14belongs_circlePdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1074790400
.align 8
.LC4:
.long 0
.long 1050673152
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Pi.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__belongs_circlePdS_S_ # -- Begin function _Z29__device_stub__belongs_circlePdS_S_
.p2align 4, 0x90
.type _Z29__device_stub__belongs_circlePdS_S_,@function
_Z29__device_stub__belongs_circlePdS_S_: # @_Z29__device_stub__belongs_circlePdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14belongs_circlePdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__belongs_circlePdS_S_, .Lfunc_end0-_Z29__device_stub__belongs_circlePdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4010000000000000 # double 4
.LCPI1_1:
.quad 0x3ea0000000000000 # double 4.76837158203125E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $16777336, %rsp # imm = 0x1000078
.cfi_def_cfa_offset 16777360
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
movq 24(%rsp), %rdi
movl $1234, %esi # imm = 0x4D2
callq hiprandSetPseudoRandomGeneratorSeed
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 24(%rsp), %rdi
movq 8(%rsp), %rsi
movl $2097152, %edx # imm = 0x200000
callq hiprandGenerateUniformDouble
movq 24(%rsp), %rdi
movq (%rsp), %rsi
movl $2097152, %edx # imm = 0x200000
callq hiprandGenerateUniformDouble
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 7936(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14belongs_circlePdS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addsd 112(%rsp,%rax,8), %xmm0
incq %rax
cmpq $2097152, %rax # imm = 0x200000
jne .LBB1_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
movsd %xmm0, 32(%rsp) # 8-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $16777336, %rsp # imm = 0x1000078
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 16777360
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14belongs_circlePdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14belongs_circlePdS_S_,@object # @_Z14belongs_circlePdS_S_
.section .rodata,"a",@progbits
.globl _Z14belongs_circlePdS_S_
.p2align 3, 0x0
_Z14belongs_circlePdS_S_:
.quad _Z29__device_stub__belongs_circlePdS_S_
.size _Z14belongs_circlePdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Sum is "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Pi is "
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14belongs_circlePdS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__belongs_circlePdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14belongs_circlePdS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <pthread.h>
#include <unistd.h> //sleep
void *hello (void *arg) {
int *ptrToThreadNumber = (int *)arg;
sleep(5);
printf("HelloThread %d\n",*ptrToThreadNumber);
return 0;
}
int main(void) {
pthread_t tid;
int threadNum=1;
//pthread_create creates a new thread and makes it executable.
//This routine can be called any number of times from anywhere within your code.
pthread_create(&tid,NULL,hello,&threadNum);
//"Joining" is one way to accomplish synchronization between threads
//The pthread_join() subroutine blocks the calling thread until the
//specified threadid thread terminates.
pthread_join(tid,NULL);
printf("------------------------\n");
return(0);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <pthread.h>
#include <unistd.h> //sleep
void *hello (void *arg) {
int *ptrToThreadNumber = (int *)arg;
sleep(5);
printf("HelloThread %d\n",*ptrToThreadNumber);
return 0;
}
int main(void) {
pthread_t tid;
int threadNum=1;
//pthread_create creates a new thread and makes it executable.
//This routine can be called any number of times from anywhere within your code.
pthread_create(&tid,NULL,hello,&threadNum);
//"Joining" is one way to accomplish synchronization between threads
//The pthread_join() subroutine blocks the calling thread until the
//specified threadid thread terminates.
pthread_join(tid,NULL);
printf("------------------------\n");
return(0);
} | .file "tmpxft_000e367c_00000000-6_01hello_pthreads.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "HelloThread %d\n"
#NO_APP
.text
.globl _Z5helloPv
.type _Z5helloPv, @function
_Z5helloPv:
.LFB2080:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $5, %edi
call sleep@PLT
movl (%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2080:
.size _Z5helloPv, .-_Z5helloPv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC1:
.string "------------------------\n"
.text
.globl main
.type main, @function
main:
.LFB2081:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $1, 12(%rsp)
leaq 12(%rsp), %rcx
leaq 16(%rsp), %rdi
leaq _Z5helloPv(%rip), %rdx
movl $0, %esi
call pthread_create@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call pthread_join@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <pthread.h>
#include <unistd.h> //sleep
void *hello (void *arg) {
int *ptrToThreadNumber = (int *)arg;
sleep(5);
printf("HelloThread %d\n",*ptrToThreadNumber);
return 0;
}
int main(void) {
pthread_t tid;
int threadNum=1;
//pthread_create creates a new thread and makes it executable.
//This routine can be called any number of times from anywhere within your code.
pthread_create(&tid,NULL,hello,&threadNum);
//"Joining" is one way to accomplish synchronization between threads
//The pthread_join() subroutine blocks the calling thread until the
//specified threadid thread terminates.
pthread_join(tid,NULL);
printf("------------------------\n");
return(0);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <pthread.h>
#include <unistd.h> //sleep
void *hello (void *arg) {
int *ptrToThreadNumber = (int *)arg;
sleep(5);
printf("HelloThread %d\n",*ptrToThreadNumber);
return 0;
}
int main(void) {
pthread_t tid;
int threadNum=1;
//pthread_create creates a new thread and makes it executable.
//This routine can be called any number of times from anywhere within your code.
pthread_create(&tid,NULL,hello,&threadNum);
//"Joining" is one way to accomplish synchronization between threads
//The pthread_join() subroutine blocks the calling thread until the
//specified threadid thread terminates.
pthread_join(tid,NULL);
printf("------------------------\n");
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <pthread.h>
#include <unistd.h> //sleep
void *hello (void *arg) {
int *ptrToThreadNumber = (int *)arg;
sleep(5);
printf("HelloThread %d\n",*ptrToThreadNumber);
return 0;
}
int main(void) {
pthread_t tid;
int threadNum=1;
//pthread_create creates a new thread and makes it executable.
//This routine can be called any number of times from anywhere within your code.
pthread_create(&tid,NULL,hello,&threadNum);
//"Joining" is one way to accomplish synchronization between threads
//The pthread_join() subroutine blocks the calling thread until the
//specified threadid thread terminates.
pthread_join(tid,NULL);
printf("------------------------\n");
return(0);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <pthread.h>
#include <unistd.h> //sleep
void *hello (void *arg) {
int *ptrToThreadNumber = (int *)arg;
sleep(5);
printf("HelloThread %d\n",*ptrToThreadNumber);
return 0;
}
int main(void) {
pthread_t tid;
int threadNum=1;
//pthread_create creates a new thread and makes it executable.
//This routine can be called any number of times from anywhere within your code.
pthread_create(&tid,NULL,hello,&threadNum);
//"Joining" is one way to accomplish synchronization between threads
//The pthread_join() subroutine blocks the calling thread until the
//specified threadid thread terminates.
pthread_join(tid,NULL);
printf("------------------------\n");
return(0);
} | .text
.file "01hello_pthreads.hip"
.globl _Z5helloPv # -- Begin function _Z5helloPv
.p2align 4, 0x90
.type _Z5helloPv,@function
_Z5helloPv: # @_Z5helloPv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $5, %edi
callq sleep
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5helloPv, .Lfunc_end0-_Z5helloPv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
leaq 16(%rsp), %rdi
leaq 12(%rsp), %rcx
movl $_Z5helloPv, %edx
xorl %esi, %esi
callq pthread_create
movq 16(%rsp), %rdi
xorl %esi, %esi
callq pthread_join
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "HelloThread %d\n"
.size .L.str, 16
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "------------------------"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z5helloPv
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e367c_00000000-6_01hello_pthreads.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "HelloThread %d\n"
#NO_APP
.text
.globl _Z5helloPv
.type _Z5helloPv, @function
_Z5helloPv:
.LFB2080:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $5, %edi
call sleep@PLT
movl (%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2080:
.size _Z5helloPv, .-_Z5helloPv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC1:
.string "------------------------\n"
.text
.globl main
.type main, @function
main:
.LFB2081:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $1, 12(%rsp)
leaq 12(%rsp), %rcx
leaq 16(%rsp), %rdi
leaq _Z5helloPv(%rip), %rdx
movl $0, %esi
call pthread_create@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call pthread_join@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "01hello_pthreads.hip"
.globl _Z5helloPv # -- Begin function _Z5helloPv
.p2align 4, 0x90
.type _Z5helloPv,@function
_Z5helloPv: # @_Z5helloPv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $5, %edi
callq sleep
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5helloPv, .Lfunc_end0-_Z5helloPv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
leaq 16(%rsp), %rdi
leaq 12(%rsp), %rcx
movl $_Z5helloPv, %edx
xorl %esi, %esi
callq pthread_create
movq 16(%rsp), %rdi
xorl %esi, %esi
callq pthread_join
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "HelloThread %d\n"
.size .L.str, 16
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "------------------------"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z5helloPv
.addrsig_sym __hip_cuid_ |
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