system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_2_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
__global__ void MatrixMulKernel_row_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.x;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.y;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
int main(int argc,char **argv) {
int N = 8192;
size_t size = N *N* sizeof(double);
int thread_dim_ll[8];
int thread_dim;
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
int loop, loop1, loop2; // loop variables
float time_spent;
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("Thread dims\n");
for (loop=0;loop<8;loop++){
thread_dim_ll[loop]=pow(2,2+loop);
}
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
}
double* d_matA; cudaMalloc(&d_matA, size);
double* d_matB; cudaMalloc(&d_matB, size);
double* d_matC; cudaMalloc(&d_matC, size);
//GPU timing
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Copy vectors from host memory to device memory
cudaMemcpy(d_matA, h_matA, size,cudaMemcpyHostToDevice);
cudaMemcpy(d_matB, h_matB, size,cudaMemcpyHostToDevice);
for (loop = 0; loop < 8; loop++){
//thread dim
thread_dim=thread_dim_ll[loop];
// Invoke kernel
dim3 threadsPerBlock = (thread_dim,thread_dim);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
cudaEventRecord(start, 0);
MatrixMulKernel_col_maj<<<blocksPerGrid, threadsPerBlock>>>(d_matA,d_matB, d_matC, N);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f with threadsPerBlock %d \n",time_spent,thread_dim);
}
// h_C contains the result in host memory
cudaMemcpy(h_matC, d_matC, size,cudaMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
cudaFree(d_matA);
cudaFree(d_matB);
cudaFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
return 0;
} | .file "tmpxft_0005130a_00000000-6_ee16b068_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fill_matrixPdjj
.type _Z11fill_matrixPdjj, @function
_Z11fill_matrixPdjj:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r9
movl $0, %r8d
movl $0, %r10d
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
testl %esi, %esi
jne .L4
ret
.L11:
movl %r10d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
mulss %xmm3, %xmm1
movl $0, %eax
.L10:
leal (%r8,%rax), %ecx
movl %eax, %edi
pxor %xmm0, %xmm0
cvtsi2ssq %rdi, %xmm0
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%r9,%rcx,8)
addl $1, %eax
cmpl %eax, %edx
jne .L10
.L12:
addl $1, %r10d
addl %edx, %r8d
cmpl %r10d, %esi
je .L3
.L4:
testl %edx, %edx
jne .L11
jmp .L12
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z11fill_matrixPdjj, .-_Z11fill_matrixPdjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "w"
.LC3:
.string "assignment2_2_out"
.LC4:
.string "%4.4f "
.LC5:
.string "\n"
.text
.globl _Z20print_matrix_to_filePdjj
.type _Z20print_matrix_to_filePdjj, @function
_Z20print_matrix_to_filePdjj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl %r15d, %ebp
movl $0, 8(%rsp)
leaq .LC4(%rip), %r14
testl %ebx, %ebx
jne .L17
.L18:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %ebx, %eax
movsd 0(%r13,%rax,8), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L19
.L21:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, %ebp
cmpl %eax, 12(%rsp)
je .L18
.L17:
movl %ebp, %ebx
subl %r15d, %ebx
testl %r15d, %r15d
jne .L19
jmp .L21
.cfi_endproc
.LFE2058:
.size _Z20print_matrix_to_filePdjj, .-_Z20print_matrix_to_filePdjj
.globl _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i
.type _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i, @function
_Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23MatrixMulKernel_col_majPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i, .-_Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i
.globl _Z23MatrixMulKernel_col_majPdS_S_i
.type _Z23MatrixMulKernel_col_majPdS_S_i, @function
_Z23MatrixMulKernel_col_majPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z23MatrixMulKernel_col_majPdS_S_i, .-_Z23MatrixMulKernel_col_majPdS_S_i
.section .rodata.str1.1
.LC6:
.string "Thread dims\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "\nMatrix A (first 10*10 inputs)\n"
.section .rodata.str1.1
.LC9:
.string "%f "
.section .rodata.str1.8
.align 8
.LC10:
.string "\n\nMatrix B (first 10*10 inputs)\n"
.align 8
.LC11:
.string "\nTime spent in col maj %f with threadsPerBlock %d \n"
.align 8
.LC12:
.string "\n\nMatrix C (first 10*10 outputs)\n"
.align 8
.LC13:
.string "\nWritting to file assignment_2_1_out as Mat C"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $536870912, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, 8(%rsp)
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 16(%rsp)
movl $536870912, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movl $8192, %edx
movl $8192, %esi
movq %r15, %rdi
call _Z11fill_matrixPdjj
movl $8192, %edx
movl $8192, %esi
movq %rbx, %rdi
call _Z11fill_matrixPdjj
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %r12
leaq 144(%rsp), %r13
movq %r12, %rbx
movl $2, %ebp
.L36:
pxor %xmm1, %xmm1
cvtsi2sdl %ebp, %xmm1
movsd .LC7(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %eax
movl %eax, (%rbx)
addl $1, %ebp
addq $4, %rbx
cmpq %r13, %rbx
jne .L36
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 80(%rax), %rbp
leaq 655440(%rax), %r15
leaq .LC9(%rip), %r14
.L37:
leaq -80(%rbp), %rbx
.L38:
movsd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L38
addq $65536, %rbp
cmpq %r15, %rbp
jne .L37
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rax
leaq 80(%rax), %rbp
leaq 655440(%rax), %r15
leaq .LC9(%rip), %r14
.L40:
leaq -80(%rbp), %rbx
.L41:
movsd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L41
addq $65536, %rbp
cmpq %r15, %rbp
jne .L40
leaq 48(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $536870912, %edx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $536870912, %edx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC11(%rip), %rbp
jmp .L44
.L43:
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r13, %r12
je .L55
.L44:
movl (%r12), %ebx
movl $1, 96(%rsp)
leal 8191(%rbx), %eax
movl $0, %edx
divl %ebx
movl %eax, 100(%rsp)
movl $8192, 104(%rsp)
movl $1, 108(%rsp)
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebx, 88(%rsp)
movl $1, 92(%rsp)
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L43
movl $8192, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i
jmp .L43
.L55:
movl $2, %ecx
movl $536870912, %edx
movq 64(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rbx), %rbp
leaq 655440(%rbx), %r13
leaq .LC9(%rip), %r12
.L45:
leaq -80(%rbp), %rbx
.L46:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L46
addq $65536, %rbp
cmpq %r13, %rbp
jne .L45
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8192, %edx
movl $8192, %esi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call _Z20print_matrix_to_filePdjj
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.globl _Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i
.type _Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i, @function
_Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23MatrixMulKernel_row_majPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i, .-_Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i
.globl _Z23MatrixMulKernel_row_majPdS_S_i
.type _Z23MatrixMulKernel_row_majPdS_S_i, @function
_Z23MatrixMulKernel_row_majPdS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z23MatrixMulKernel_row_majPdS_S_i, .-_Z23MatrixMulKernel_row_majPdS_S_i
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z23MatrixMulKernel_row_majPdS_S_i"
.align 8
.LC15:
.string "_Z23MatrixMulKernel_col_majPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z23MatrixMulKernel_row_majPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z23MatrixMulKernel_col_majPdS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1074161254
.align 4
.LC1:
.long 1078774989
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_2_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
__global__ void MatrixMulKernel_row_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.x;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.y;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
int main(int argc,char **argv) {
int N = 8192;
size_t size = N *N* sizeof(double);
int thread_dim_ll[8];
int thread_dim;
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
int loop, loop1, loop2; // loop variables
float time_spent;
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("Thread dims\n");
for (loop=0;loop<8;loop++){
thread_dim_ll[loop]=pow(2,2+loop);
}
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
}
double* d_matA; cudaMalloc(&d_matA, size);
double* d_matB; cudaMalloc(&d_matB, size);
double* d_matC; cudaMalloc(&d_matC, size);
//GPU timing
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Copy vectors from host memory to device memory
cudaMemcpy(d_matA, h_matA, size,cudaMemcpyHostToDevice);
cudaMemcpy(d_matB, h_matB, size,cudaMemcpyHostToDevice);
for (loop = 0; loop < 8; loop++){
//thread dim
thread_dim=thread_dim_ll[loop];
// Invoke kernel
dim3 threadsPerBlock = (thread_dim,thread_dim);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
cudaEventRecord(start, 0);
MatrixMulKernel_col_maj<<<blocksPerGrid, threadsPerBlock>>>(d_matA,d_matB, d_matC, N);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f with threadsPerBlock %d \n",time_spent,thread_dim);
}
// h_C contains the result in host memory
cudaMemcpy(h_matC, d_matC, size,cudaMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
cudaFree(d_matA);
cudaFree(d_matB);
cudaFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_2_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
__global__ void MatrixMulKernel_row_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.x;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.y;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
int main(int argc,char **argv) {
int N = 8192;
size_t size = N *N* sizeof(double);
int thread_dim_ll[8];
int thread_dim;
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
int loop, loop1, loop2; // loop variables
float time_spent;
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("Thread dims\n");
for (loop=0;loop<8;loop++){
thread_dim_ll[loop]=pow(2,2+loop);
}
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
}
double* d_matA; hipMalloc(&d_matA, size);
double* d_matB; hipMalloc(&d_matB, size);
double* d_matC; hipMalloc(&d_matC, size);
//GPU timing
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Copy vectors from host memory to device memory
hipMemcpy(d_matA, h_matA, size,hipMemcpyHostToDevice);
hipMemcpy(d_matB, h_matB, size,hipMemcpyHostToDevice);
for (loop = 0; loop < 8; loop++){
//thread dim
thread_dim=thread_dim_ll[loop];
// Invoke kernel
dim3 threadsPerBlock = (thread_dim,thread_dim);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
hipEventRecord(start, 0);
MatrixMulKernel_col_maj<<<blocksPerGrid, threadsPerBlock>>>(d_matA,d_matB, d_matC, N);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f with threadsPerBlock %d \n",time_spent,thread_dim);
}
// h_C contains the result in host memory
hipMemcpy(h_matC, d_matC, size,hipMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
hipFree(d_matA);
hipFree(d_matB);
hipFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_2_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
__global__ void MatrixMulKernel_row_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.x;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.y;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
int main(int argc,char **argv) {
int N = 8192;
size_t size = N *N* sizeof(double);
int thread_dim_ll[8];
int thread_dim;
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
int loop, loop1, loop2; // loop variables
float time_spent;
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("Thread dims\n");
for (loop=0;loop<8;loop++){
thread_dim_ll[loop]=pow(2,2+loop);
}
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
}
double* d_matA; hipMalloc(&d_matA, size);
double* d_matB; hipMalloc(&d_matB, size);
double* d_matC; hipMalloc(&d_matC, size);
//GPU timing
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Copy vectors from host memory to device memory
hipMemcpy(d_matA, h_matA, size,hipMemcpyHostToDevice);
hipMemcpy(d_matB, h_matB, size,hipMemcpyHostToDevice);
for (loop = 0; loop < 8; loop++){
//thread dim
thread_dim=thread_dim_ll[loop];
// Invoke kernel
dim3 threadsPerBlock = (thread_dim,thread_dim);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
hipEventRecord(start, 0);
MatrixMulKernel_col_maj<<<blocksPerGrid, threadsPerBlock>>>(d_matA,d_matB, d_matC, N);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f with threadsPerBlock %d \n",time_spent,thread_dim);
}
// h_C contains the result in host memory
hipMemcpy(h_matC, d_matC, size,hipMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
hipFree(d_matA);
hipFree(d_matB);
hipFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23MatrixMulKernel_col_majPdS_S_i
.globl _Z23MatrixMulKernel_col_majPdS_S_i
.p2align 8
.type _Z23MatrixMulKernel_col_majPdS_S_i,@function
_Z23MatrixMulKernel_col_majPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_7
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[5:6], v6
v_add_nc_u32_e32 v4, s2, v4
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[2:3], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[5:6], v[9:10], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v6, v[5:6]
s_cbranch_scc0 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v6
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23MatrixMulKernel_col_majPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23MatrixMulKernel_col_majPdS_S_i, .Lfunc_end0-_Z23MatrixMulKernel_col_majPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23MatrixMulKernel_row_majPdS_S_i
.globl _Z23MatrixMulKernel_row_majPdS_S_i
.p2align 8
.type _Z23MatrixMulKernel_row_majPdS_S_i,@function
_Z23MatrixMulKernel_row_majPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB1_7
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB1_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[5:6], v6
v_add_nc_u32_e32 v4, s2, v4
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[2:3], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[5:6], v[9:10], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v6, v[5:6]
s_cbranch_scc0 .LBB1_3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v6
s_branch .LBB1_6
.LBB1_5:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB1_6:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23MatrixMulKernel_row_majPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z23MatrixMulKernel_row_majPdS_S_i, .Lfunc_end1-_Z23MatrixMulKernel_row_majPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23MatrixMulKernel_col_majPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23MatrixMulKernel_col_majPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23MatrixMulKernel_row_majPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23MatrixMulKernel_row_majPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
void fill_matrix(double *mat, unsigned numRows, unsigned numCols)
{
for(unsigned i=0; i < numRows; i++)
for(unsigned j=0; j < numCols; j++)
{
mat[i*numCols + j] = i*2.1f + j*3.2f;
}
}
void print_matrix_to_file(double *mat, unsigned numRows, unsigned numCols)
{
const char *fname = "assignment2_2_out";
FILE *f = fopen(fname, "w");
for(unsigned i=0; i < numRows; i++)
{
for(unsigned j=0; j < numCols; j++)
fprintf(f,"%4.4f ", mat[i*numCols + j]);
fprintf(f,"\n");
}
fclose(f); }
__global__ void MatrixMulKernel_col_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.x;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
__global__ void MatrixMulKernel_row_maj(double* M, double* N, double* P, int Width) {
// Calculate the row index of the P element and M
int Row = blockIdx.y*blockDim.y+threadIdx.x;
// Calculate the column index of P and N
int Col = blockIdx.x*blockDim.x+threadIdx.y;
if ((Row < Width) && (Col < Width)) {
float Pvalue = 0;
for (int k = 0; k < Width; ++k) {
Pvalue += M[Row*Width+k]*N[k*Width+Col];
}
P[Row*Width+Col] = Pvalue;
}
}
int main(int argc,char **argv) {
int N = 8192;
size_t size = N *N* sizeof(double);
int thread_dim_ll[8];
int thread_dim;
double*h_matA = (double*)malloc(size);
double*h_matB = (double*)malloc(size);
double*h_matC = (double*)malloc(size); // result
int loop, loop1, loop2; // loop variables
float time_spent;
fill_matrix(h_matA,N,N);
fill_matrix(h_matB,N,N);
printf("Thread dims\n");
for (loop=0;loop<8;loop++){
thread_dim_ll[loop]=pow(2,2+loop);
}
printf("\nMatrix A (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matA + N*loop1 + loop2));
}
printf("\n\nMatrix B (first 10*10 inputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matB + N*loop1 + loop2));
}
double* d_matA; hipMalloc(&d_matA, size);
double* d_matB; hipMalloc(&d_matB, size);
double* d_matC; hipMalloc(&d_matC, size);
//GPU timing
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Copy vectors from host memory to device memory
hipMemcpy(d_matA, h_matA, size,hipMemcpyHostToDevice);
hipMemcpy(d_matB, h_matB, size,hipMemcpyHostToDevice);
for (loop = 0; loop < 8; loop++){
//thread dim
thread_dim=thread_dim_ll[loop];
// Invoke kernel
dim3 threadsPerBlock = (thread_dim,thread_dim);
dim3 blocksPerGrid ((N + threadsPerBlock.x - 1) /threadsPerBlock.x,(N + threadsPerBlock.y - 1) /threadsPerBlock.y);
hipEventRecord(start, 0);
MatrixMulKernel_col_maj<<<blocksPerGrid, threadsPerBlock>>>(d_matA,d_matB, d_matC, N);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_spent, start, stop);
printf("\nTime spent in col maj %f with threadsPerBlock %d \n",time_spent,thread_dim);
}
// h_C contains the result in host memory
hipMemcpy(h_matC, d_matC, size,hipMemcpyDeviceToHost);
printf("\n\nMatrix C (first 10*10 outputs)\n");
for(loop1 = 0; loop1 < 10; loop1++){
for (loop2=0;loop2 < 10; loop2++)
printf("%f ", *(h_matC + N*loop1 + loop2));
}
// Log outputs
printf("\nWritting to file assignment_2_1_out as Mat C");
print_matrix_to_file(h_matC,N,N);
// Free device memory
hipFree(d_matA);
hipFree(d_matB);
hipFree(d_matC);
// Free host memory
free(h_matA);
free(h_matB);
free(h_matC);
return 0;
} | .text
.file "ee16b068_2.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_matrixPdjj
.LCPI0_0:
.long 0x40066666 # float 2.0999999
.LCPI0_1:
.long 0x404ccccd # float 3.20000005
.text
.globl _Z11fill_matrixPdjj
.p2align 4, 0x90
.type _Z11fill_matrixPdjj,@function
_Z11fill_matrixPdjj: # @_Z11fill_matrixPdjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incl %r8d
addq %rax, %rcx
cmpl %esi, %r8d
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
je .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r8d, %r9d
xorps %xmm2, %xmm2
cvtsi2ss %r9, %xmm2
mulss %xmm0, %xmm2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r9d, %r10d
xorps %xmm3, %xmm3
cvtsi2ss %r10, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
leal (%rcx,%r9), %r10d
movsd %xmm3, (%rdi,%r10,8)
incq %r9
cmpq %r9, %rax
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge15
retq
.Lfunc_end0:
.size _Z11fill_matrixPdjj, .Lfunc_end0-_Z11fill_matrixPdjj
.cfi_endproc
# -- End function
.globl _Z20print_matrix_to_filePdjj # -- Begin function _Z20print_matrix_to_filePdjj
.p2align 4, 0x90
.type _Z20print_matrix_to_filePdjj,@function
_Z20print_matrix_to_filePdjj: # @_Z20print_matrix_to_filePdjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
movl %ebp, 12(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB1_4
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ecx
movl %ebx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %ebp, %ebp
movl %ecx, 8(%rsp) # 4-byte Spill
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_3: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
movq %r15, %rsi
callq fputc@PLT
incl %ebp
movl 8(%rsp), %ecx # 4-byte Reload
addl %ecx, %ebx
cmpl 12(%rsp), %ebp # 4-byte Folded Reload
je .LBB1_4
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movq 16(%rsp), %r12 # 8-byte Reload
movl %ebx, %r13d
testl %ecx, %ecx
je .LBB1_3
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, %eax
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incl %r13d
decq %r12
jne .LBB1_5
jmp .LBB1_3
.LBB1_4: # %._crit_edge17
movq %r15, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z20print_matrix_to_filePdjj, .Lfunc_end1-_Z20print_matrix_to_filePdjj
.cfi_endproc
# -- End function
.globl _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i # -- Begin function _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.p2align 4, 0x90
.type _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i,@function
_Z38__device_stub__MatrixMulKernel_col_majPdS_S_i: # @_Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23MatrixMulKernel_col_majPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i, .Lfunc_end2-_Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.cfi_endproc
# -- End function
.globl _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i # -- Begin function _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.p2align 4, 0x90
.type _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i,@function
_Z38__device_stub__MatrixMulKernel_row_majPdS_S_i: # @_Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23MatrixMulKernel_row_majPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i, .Lfunc_end3-_Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x40066666 # float 2.0999999
.LCPI4_1:
.long 0x404ccccd # float 3.20000005
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_2:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r12
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r13
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r14
xorl %eax, %eax
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %r12, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $8192, %rdx # imm = 0x2000
jne .LBB4_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB4_1 Depth=1
incl %eax
addq $65536, %rcx # imm = 0x10000
cmpl $8192, %eax # imm = 0x2000
jne .LBB4_1
# %bb.4: # %.preheader.i75.preheader
xorl %eax, %eax
movq %r13, %rcx
.p2align 4, 0x90
.LBB4_5: # %.preheader.i75
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $8192, %rdx # imm = 0x2000
jne .LBB4_6
# %bb.7: # %._crit_edge.i80
# in Loop: Header=BB4_5 Depth=1
incl %eax
addq $65536, %rcx # imm = 0x10000
cmpl $8192, %eax # imm = 0x2000
jne .LBB4_5
# %bb.8: # %_Z11fill_matrixPdjj.exit82
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_9: # =>This Inner Loop Header: Depth=1
leal 2(%rbx), %edi
movsd .LCPI4_2(%rip), %xmm0 # xmm0 = mem[0],zero
callq ldexp@PLT
cvttsd2si %xmm0, %eax
movl %eax, 176(%rsp,%rbx,4)
incq %rbx
cmpq $8, %rbx
jne .LBB4_9
# %bb.10:
movq %r14, 48(%rsp) # 8-byte Spill
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
movq %r12, %r14
.p2align 4, 0x90
.LBB4_11: # %.preheader91
# =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_12: # Parent Loop BB4_11 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB4_12
# %bb.13: # in Loop: Header=BB4_11 Depth=1
incq %rbx
addq $65536, %r14 # imm = 0x10000
cmpq $10, %rbx
jne .LBB4_11
# %bb.14:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %ebx, %ebx
movq %r13, %r14
.p2align 4, 0x90
.LBB4_15: # %.preheader90
# =>This Loop Header: Depth=1
# Child Loop BB4_16 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_16: # Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB4_16
# %bb.17: # in Loop: Header=BB4_15 Depth=1
incq %rbx
addq $65536, %r14 # imm = 0x10000
cmpq $10, %rbx
jne .LBB4_15
# %bb.18:
leaq 24(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 40(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %r12, 64(%rsp) # 8-byte Spill
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %r13, 56(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movabsq $35184372088832, %r14 # imm = 0x200000000000
leaq 32(%rsp), %r15
jmp .LBB4_19
.p2align 4, 0x90
.LBB4_21: # in Loop: Header=BB4_19 Depth=1
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq (%rsp), %rdx
movq %r15, %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movl %r13d, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
je .LBB4_22
.LBB4_19: # =>This Inner Loop Header: Depth=1
movl 176(%rsp,%rbx,4), %r13d
movq %r13, %r12
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
leal 8191(%r13), %eax
xorl %edx, %edx
divl %r13d
# kill: def $eax killed $eax def $rax
leaq (%rax,%r14), %rbp
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_21
# %bb.20: # in Loop: Header=BB4_19 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $8192, 36(%rsp) # imm = 0x2000
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z23MatrixMulKernel_col_majPdS_S_i, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_21
.LBB4_22:
movq 8(%rsp), %rsi
movl $536870912, %edx # imm = 0x20000000
movq 48(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
xorl %ebx, %ebx
movq %rbp, %r14
.p2align 4, 0x90
.LBB4_23: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_24 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_24: # Parent Loop BB4_23 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB4_24
# %bb.25: # in Loop: Header=BB4_23 Depth=1
incq %rbx
addq $65536, %r14 # imm = 0x10000
cmpq $10, %rbx
jne .LBB4_23
# %bb.26:
xorl %r14d, %r14d
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movq %rbp, %r15
movq 56(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB4_27: # %.preheader.i83
# =>This Loop Header: Depth=1
# Child Loop BB4_28 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_28: # Parent Loop BB4_27 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $8192, %r12 # imm = 0x2000
jne .LBB4_28
# %bb.29: # %._crit_edge.i87
# in Loop: Header=BB4_27 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incl %r14d
addq $65536, %r15 # imm = 0x10000
cmpl $8192, %r14d # imm = 0x2000
jne .LBB4_27
# %bb.30: # %_Z20print_matrix_to_filePdjj.exit
movq %rbx, %rdi
callq fclose
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23MatrixMulKernel_col_majPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23MatrixMulKernel_row_majPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "assignment2_2_out"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4.4f "
.size .L.str.2, 7
.type _Z23MatrixMulKernel_col_majPdS_S_i,@object # @_Z23MatrixMulKernel_col_majPdS_S_i
.section .rodata,"a",@progbits
.globl _Z23MatrixMulKernel_col_majPdS_S_i
.p2align 3, 0x0
_Z23MatrixMulKernel_col_majPdS_S_i:
.quad _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.size _Z23MatrixMulKernel_col_majPdS_S_i, 8
.type _Z23MatrixMulKernel_row_majPdS_S_i,@object # @_Z23MatrixMulKernel_row_majPdS_S_i
.globl _Z23MatrixMulKernel_row_majPdS_S_i
.p2align 3, 0x0
_Z23MatrixMulKernel_row_majPdS_S_i:
.quad _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.size _Z23MatrixMulKernel_row_majPdS_S_i, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%f "
.size .L.str.6, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nTime spent in col maj %f with threadsPerBlock %d \n"
.size .L.str.8, 52
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nWritting to file assignment_2_1_out as Mat C"
.size .L.str.10, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23MatrixMulKernel_col_majPdS_S_i"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23MatrixMulKernel_row_majPdS_S_i"
.size .L__unnamed_2, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Thread dims"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nMatrix A (first 10*10 inputs)"
.size .Lstr.1, 31
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\nMatrix B (first 10*10 inputs)"
.size .Lstr.2, 32
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n\nMatrix C (first 10*10 outputs)"
.size .Lstr.3, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.addrsig_sym _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23MatrixMulKernel_col_majPdS_S_i
.addrsig_sym _Z23MatrixMulKernel_row_majPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005130a_00000000-6_ee16b068_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fill_matrixPdjj
.type _Z11fill_matrixPdjj, @function
_Z11fill_matrixPdjj:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r9
movl $0, %r8d
movl $0, %r10d
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
testl %esi, %esi
jne .L4
ret
.L11:
movl %r10d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
mulss %xmm3, %xmm1
movl $0, %eax
.L10:
leal (%r8,%rax), %ecx
movl %eax, %edi
pxor %xmm0, %xmm0
cvtsi2ssq %rdi, %xmm0
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%r9,%rcx,8)
addl $1, %eax
cmpl %eax, %edx
jne .L10
.L12:
addl $1, %r10d
addl %edx, %r8d
cmpl %r10d, %esi
je .L3
.L4:
testl %edx, %edx
jne .L11
jmp .L12
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z11fill_matrixPdjj, .-_Z11fill_matrixPdjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "w"
.LC3:
.string "assignment2_2_out"
.LC4:
.string "%4.4f "
.LC5:
.string "\n"
.text
.globl _Z20print_matrix_to_filePdjj
.type _Z20print_matrix_to_filePdjj, @function
_Z20print_matrix_to_filePdjj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl %r15d, %ebp
movl $0, 8(%rsp)
leaq .LC4(%rip), %r14
testl %ebx, %ebx
jne .L17
.L18:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %ebx, %eax
movsd 0(%r13,%rax,8), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L19
.L21:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, %ebp
cmpl %eax, 12(%rsp)
je .L18
.L17:
movl %ebp, %ebx
subl %r15d, %ebx
testl %r15d, %r15d
jne .L19
jmp .L21
.cfi_endproc
.LFE2058:
.size _Z20print_matrix_to_filePdjj, .-_Z20print_matrix_to_filePdjj
.globl _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i
.type _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i, @function
_Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23MatrixMulKernel_col_majPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i, .-_Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i
.globl _Z23MatrixMulKernel_col_majPdS_S_i
.type _Z23MatrixMulKernel_col_majPdS_S_i, @function
_Z23MatrixMulKernel_col_majPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z23MatrixMulKernel_col_majPdS_S_i, .-_Z23MatrixMulKernel_col_majPdS_S_i
.section .rodata.str1.1
.LC6:
.string "Thread dims\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "\nMatrix A (first 10*10 inputs)\n"
.section .rodata.str1.1
.LC9:
.string "%f "
.section .rodata.str1.8
.align 8
.LC10:
.string "\n\nMatrix B (first 10*10 inputs)\n"
.align 8
.LC11:
.string "\nTime spent in col maj %f with threadsPerBlock %d \n"
.align 8
.LC12:
.string "\n\nMatrix C (first 10*10 outputs)\n"
.align 8
.LC13:
.string "\nWritting to file assignment_2_1_out as Mat C"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $536870912, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, 8(%rsp)
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 16(%rsp)
movl $536870912, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movl $8192, %edx
movl $8192, %esi
movq %r15, %rdi
call _Z11fill_matrixPdjj
movl $8192, %edx
movl $8192, %esi
movq %rbx, %rdi
call _Z11fill_matrixPdjj
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %r12
leaq 144(%rsp), %r13
movq %r12, %rbx
movl $2, %ebp
.L36:
pxor %xmm1, %xmm1
cvtsi2sdl %ebp, %xmm1
movsd .LC7(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %eax
movl %eax, (%rbx)
addl $1, %ebp
addq $4, %rbx
cmpq %r13, %rbx
jne .L36
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 80(%rax), %rbp
leaq 655440(%rax), %r15
leaq .LC9(%rip), %r14
.L37:
leaq -80(%rbp), %rbx
.L38:
movsd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L38
addq $65536, %rbp
cmpq %r15, %rbp
jne .L37
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rax
leaq 80(%rax), %rbp
leaq 655440(%rax), %r15
leaq .LC9(%rip), %r14
.L40:
leaq -80(%rbp), %rbx
.L41:
movsd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L41
addq $65536, %rbp
cmpq %r15, %rbp
jne .L40
leaq 48(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $536870912, %edx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $536870912, %edx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC11(%rip), %rbp
jmp .L44
.L43:
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r13, %r12
je .L55
.L44:
movl (%r12), %ebx
movl $1, 96(%rsp)
leal 8191(%rbx), %eax
movl $0, %edx
divl %ebx
movl %eax, 100(%rsp)
movl $8192, 104(%rsp)
movl $1, 108(%rsp)
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl %ebx, 88(%rsp)
movl $1, 92(%rsp)
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L43
movl $8192, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z48__device_stub__Z23MatrixMulKernel_col_majPdS_S_iPdS_S_i
jmp .L43
.L55:
movl $2, %ecx
movl $536870912, %edx
movq 64(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rbx), %rbp
leaq 655440(%rbx), %r13
leaq .LC9(%rip), %r12
.L45:
leaq -80(%rbp), %rbx
.L46:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L46
addq $65536, %rbp
cmpq %r13, %rbp
jne .L45
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8192, %edx
movl $8192, %esi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call _Z20print_matrix_to_filePdjj
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.globl _Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i
.type _Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i, @function
_Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23MatrixMulKernel_row_majPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i, .-_Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i
.globl _Z23MatrixMulKernel_row_majPdS_S_i
.type _Z23MatrixMulKernel_row_majPdS_S_i, @function
_Z23MatrixMulKernel_row_majPdS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23MatrixMulKernel_row_majPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z23MatrixMulKernel_row_majPdS_S_i, .-_Z23MatrixMulKernel_row_majPdS_S_i
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z23MatrixMulKernel_row_majPdS_S_i"
.align 8
.LC15:
.string "_Z23MatrixMulKernel_col_majPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z23MatrixMulKernel_row_majPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z23MatrixMulKernel_col_majPdS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1074161254
.align 4
.LC1:
.long 1078774989
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ee16b068_2.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_matrixPdjj
.LCPI0_0:
.long 0x40066666 # float 2.0999999
.LCPI0_1:
.long 0x404ccccd # float 3.20000005
.text
.globl _Z11fill_matrixPdjj
.p2align 4, 0x90
.type _Z11fill_matrixPdjj,@function
_Z11fill_matrixPdjj: # @_Z11fill_matrixPdjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incl %r8d
addq %rax, %rcx
cmpl %esi, %r8d
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
je .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r8d, %r9d
xorps %xmm2, %xmm2
cvtsi2ss %r9, %xmm2
mulss %xmm0, %xmm2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r9d, %r10d
xorps %xmm3, %xmm3
cvtsi2ss %r10, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
leal (%rcx,%r9), %r10d
movsd %xmm3, (%rdi,%r10,8)
incq %r9
cmpq %r9, %rax
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge15
retq
.Lfunc_end0:
.size _Z11fill_matrixPdjj, .Lfunc_end0-_Z11fill_matrixPdjj
.cfi_endproc
# -- End function
.globl _Z20print_matrix_to_filePdjj # -- Begin function _Z20print_matrix_to_filePdjj
.p2align 4, 0x90
.type _Z20print_matrix_to_filePdjj,@function
_Z20print_matrix_to_filePdjj: # @_Z20print_matrix_to_filePdjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
movl %ebp, 12(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB1_4
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ecx
movl %ebx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %ebp, %ebp
movl %ecx, 8(%rsp) # 4-byte Spill
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_3: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
movq %r15, %rsi
callq fputc@PLT
incl %ebp
movl 8(%rsp), %ecx # 4-byte Reload
addl %ecx, %ebx
cmpl 12(%rsp), %ebp # 4-byte Folded Reload
je .LBB1_4
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movq 16(%rsp), %r12 # 8-byte Reload
movl %ebx, %r13d
testl %ecx, %ecx
je .LBB1_3
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, %eax
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incl %r13d
decq %r12
jne .LBB1_5
jmp .LBB1_3
.LBB1_4: # %._crit_edge17
movq %r15, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z20print_matrix_to_filePdjj, .Lfunc_end1-_Z20print_matrix_to_filePdjj
.cfi_endproc
# -- End function
.globl _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i # -- Begin function _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.p2align 4, 0x90
.type _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i,@function
_Z38__device_stub__MatrixMulKernel_col_majPdS_S_i: # @_Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23MatrixMulKernel_col_majPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i, .Lfunc_end2-_Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.cfi_endproc
# -- End function
.globl _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i # -- Begin function _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.p2align 4, 0x90
.type _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i,@function
_Z38__device_stub__MatrixMulKernel_row_majPdS_S_i: # @_Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23MatrixMulKernel_row_majPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i, .Lfunc_end3-_Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x40066666 # float 2.0999999
.LCPI4_1:
.long 0x404ccccd # float 3.20000005
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_2:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r12
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r13
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r14
xorl %eax, %eax
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %r12, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $8192, %rdx # imm = 0x2000
jne .LBB4_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB4_1 Depth=1
incl %eax
addq $65536, %rcx # imm = 0x10000
cmpl $8192, %eax # imm = 0x2000
jne .LBB4_1
# %bb.4: # %.preheader.i75.preheader
xorl %eax, %eax
movq %r13, %rcx
.p2align 4, 0x90
.LBB4_5: # %.preheader.i75
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $8192, %rdx # imm = 0x2000
jne .LBB4_6
# %bb.7: # %._crit_edge.i80
# in Loop: Header=BB4_5 Depth=1
incl %eax
addq $65536, %rcx # imm = 0x10000
cmpl $8192, %eax # imm = 0x2000
jne .LBB4_5
# %bb.8: # %_Z11fill_matrixPdjj.exit82
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_9: # =>This Inner Loop Header: Depth=1
leal 2(%rbx), %edi
movsd .LCPI4_2(%rip), %xmm0 # xmm0 = mem[0],zero
callq ldexp@PLT
cvttsd2si %xmm0, %eax
movl %eax, 176(%rsp,%rbx,4)
incq %rbx
cmpq $8, %rbx
jne .LBB4_9
# %bb.10:
movq %r14, 48(%rsp) # 8-byte Spill
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
movq %r12, %r14
.p2align 4, 0x90
.LBB4_11: # %.preheader91
# =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_12: # Parent Loop BB4_11 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB4_12
# %bb.13: # in Loop: Header=BB4_11 Depth=1
incq %rbx
addq $65536, %r14 # imm = 0x10000
cmpq $10, %rbx
jne .LBB4_11
# %bb.14:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %ebx, %ebx
movq %r13, %r14
.p2align 4, 0x90
.LBB4_15: # %.preheader90
# =>This Loop Header: Depth=1
# Child Loop BB4_16 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_16: # Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB4_16
# %bb.17: # in Loop: Header=BB4_15 Depth=1
incq %rbx
addq $65536, %r14 # imm = 0x10000
cmpq $10, %rbx
jne .LBB4_15
# %bb.18:
leaq 24(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 40(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %r12, 64(%rsp) # 8-byte Spill
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %r13, 56(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movabsq $35184372088832, %r14 # imm = 0x200000000000
leaq 32(%rsp), %r15
jmp .LBB4_19
.p2align 4, 0x90
.LBB4_21: # in Loop: Header=BB4_19 Depth=1
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq (%rsp), %rdx
movq %r15, %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movl %r13d, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $8, %rbx
je .LBB4_22
.LBB4_19: # =>This Inner Loop Header: Depth=1
movl 176(%rsp,%rbx,4), %r13d
movq %r13, %r12
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
leal 8191(%r13), %eax
xorl %edx, %edx
divl %r13d
# kill: def $eax killed $eax def $rax
leaq (%rax,%r14), %rbp
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_21
# %bb.20: # in Loop: Header=BB4_19 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $8192, 36(%rsp) # imm = 0x2000
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z23MatrixMulKernel_col_majPdS_S_i, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_21
.LBB4_22:
movq 8(%rsp), %rsi
movl $536870912, %edx # imm = 0x20000000
movq 48(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
xorl %ebx, %ebx
movq %rbp, %r14
.p2align 4, 0x90
.LBB4_23: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_24 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_24: # Parent Loop BB4_23 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB4_24
# %bb.25: # in Loop: Header=BB4_23 Depth=1
incq %rbx
addq $65536, %r14 # imm = 0x10000
cmpq $10, %rbx
jne .LBB4_23
# %bb.26:
xorl %r14d, %r14d
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movq %rbp, %r15
movq 56(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB4_27: # %.preheader.i83
# =>This Loop Header: Depth=1
# Child Loop BB4_28 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_28: # Parent Loop BB4_27 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $8192, %r12 # imm = 0x2000
jne .LBB4_28
# %bb.29: # %._crit_edge.i87
# in Loop: Header=BB4_27 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incl %r14d
addq $65536, %r15 # imm = 0x10000
cmpl $8192, %r14d # imm = 0x2000
jne .LBB4_27
# %bb.30: # %_Z20print_matrix_to_filePdjj.exit
movq %rbx, %rdi
callq fclose
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23MatrixMulKernel_col_majPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23MatrixMulKernel_row_majPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "assignment2_2_out"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4.4f "
.size .L.str.2, 7
.type _Z23MatrixMulKernel_col_majPdS_S_i,@object # @_Z23MatrixMulKernel_col_majPdS_S_i
.section .rodata,"a",@progbits
.globl _Z23MatrixMulKernel_col_majPdS_S_i
.p2align 3, 0x0
_Z23MatrixMulKernel_col_majPdS_S_i:
.quad _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.size _Z23MatrixMulKernel_col_majPdS_S_i, 8
.type _Z23MatrixMulKernel_row_majPdS_S_i,@object # @_Z23MatrixMulKernel_row_majPdS_S_i
.globl _Z23MatrixMulKernel_row_majPdS_S_i
.p2align 3, 0x0
_Z23MatrixMulKernel_row_majPdS_S_i:
.quad _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.size _Z23MatrixMulKernel_row_majPdS_S_i, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%f "
.size .L.str.6, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nTime spent in col maj %f with threadsPerBlock %d \n"
.size .L.str.8, 52
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nWritting to file assignment_2_1_out as Mat C"
.size .L.str.10, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23MatrixMulKernel_col_majPdS_S_i"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23MatrixMulKernel_row_majPdS_S_i"
.size .L__unnamed_2, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Thread dims"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nMatrix A (first 10*10 inputs)"
.size .Lstr.1, 31
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\nMatrix B (first 10*10 inputs)"
.size .Lstr.2, 32
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n\nMatrix C (first 10*10 outputs)"
.size .Lstr.3, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__MatrixMulKernel_col_majPdS_S_i
.addrsig_sym _Z38__device_stub__MatrixMulKernel_row_majPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23MatrixMulKernel_col_majPdS_S_i
.addrsig_sym _Z23MatrixMulKernel_row_majPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void grayScale2(uchar3 *input, uchar3 *output,int width, int height) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int w = blockDim.x * gridDim.x;
//if ((gridDim.x * gridDim.y) < width * height){
int tid = y*w + x;
output[tid].x = (input[tid].x + input[tid].y +
input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
// }
} | code for sm_80
Function : _Z10grayScale2P6uchar3S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fe200078e0200 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff077435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00b0*/ LDG.E.U8 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1100 */
/*00c0*/ LDG.E.U8 R5, [R2.64+0x1] ; /* 0x0000010402057981 */
/* 0x000ea8000c1e1100 */
/*00d0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x004fe20007ffe004 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0207 */
/*0100*/ IMAD.WIDE.U32 R4, R4, -0x55555555, RZ ; /* 0xaaaaaaab04047825 */
/* 0x000fca00078e00ff */
/*0110*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fca0000011605 */
/*0120*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe8000c101104 */
/*0130*/ STG.E.U8 [R6.64+0x1], R5 ; /* 0x0000010506007986 */
/* 0x000fe8000c101104 */
/*0140*/ STG.E.U8 [R6.64+0x2], R5 ; /* 0x0000020506007986 */
/* 0x000fe2000c101104 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void grayScale2(uchar3 *input, uchar3 *output,int width, int height) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int w = blockDim.x * gridDim.x;
//if ((gridDim.x * gridDim.y) < width * height){
int tid = y*w + x;
output[tid].x = (input[tid].x + input[tid].y +
input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
// }
} | .file "tmpxft_00025f45_00000000-6_grayScale2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii
.type _Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii, @function
_Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10grayScale2P6uchar3S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii, .-_Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii
.globl _Z10grayScale2P6uchar3S0_ii
.type _Z10grayScale2P6uchar3S0_ii, @function
_Z10grayScale2P6uchar3S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10grayScale2P6uchar3S0_ii, .-_Z10grayScale2P6uchar3S0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10grayScale2P6uchar3S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10grayScale2P6uchar3S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void grayScale2(uchar3 *input, uchar3 *output,int width, int height) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int w = blockDim.x * gridDim.x;
//if ((gridDim.x * gridDim.y) < width * height){
int tid = y*w + x;
output[tid].x = (input[tid].x + input[tid].y +
input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
// }
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void grayScale2(uchar3 *input, uchar3 *output,int width, int height) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int w = blockDim.x * gridDim.x;
//if ((gridDim.x * gridDim.y) < width * height){
int tid = y*w + x;
output[tid].x = (input[tid].x + input[tid].y +
input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
// }
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void grayScale2(uchar3 *input, uchar3 *output,int width, int height) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int w = blockDim.x * gridDim.x;
//if ((gridDim.x * gridDim.y) < width * height){
int tid = y*w + x;
output[tid].x = (input[tid].x + input[tid].y +
input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
// }
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.globl _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.p2align 8
.type _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii,@function
_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_i64_i32 v[2:3], null, v1, 3, s[0:1]
s_clause 0x2
global_load_u8 v0, v[2:3], off
global_load_u8 v4, v[2:3], off offset:1
global_load_u8 v2, v[2:3], off offset:2
s_waitcnt vmcnt(1)
v_add_nc_u16 v0, v4, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u16 v0, v0, v2
v_mad_i64_i32 v[2:3], null, v1, 3, s[2:3]
v_and_b32_e32 v0, 0xffff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v0, 0x5556, v0
v_lshrrev_b32_e32 v0, 16, v0
s_clause 0x2
global_store_b8 v[2:3], v0, off
global_store_b8 v[2:3], v0, off offset:1
global_store_b8 v[2:3], v0, off offset:2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void grayScale2(uchar3 *input, uchar3 *output,int width, int height) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int w = blockDim.x * gridDim.x;
//if ((gridDim.x * gridDim.y) < width * height){
int tid = y*w + x;
output[tid].x = (input[tid].x + input[tid].y +
input[tid].z) / 3;
output[tid].z = output[tid].y = output[tid].x;
// }
} | .text
.file "grayScale2.hip"
.globl _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.p2align 4, 0x90
.type _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii,@function
_Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii: # @_Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii,@object # @_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.section .rodata,"a",@progbits
.globl _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.p2align 3, 0x0
_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii:
.quad _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.size _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10grayScale2P6uchar3S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fe200078e0200 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff077435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*00b0*/ LDG.E.U8 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1100 */
/*00c0*/ LDG.E.U8 R5, [R2.64+0x1] ; /* 0x0000010402057981 */
/* 0x000ea8000c1e1100 */
/*00d0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x004fe20007ffe004 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0207 */
/*0100*/ IMAD.WIDE.U32 R4, R4, -0x55555555, RZ ; /* 0xaaaaaaab04047825 */
/* 0x000fca00078e00ff */
/*0110*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fca0000011605 */
/*0120*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe8000c101104 */
/*0130*/ STG.E.U8 [R6.64+0x1], R5 ; /* 0x0000010506007986 */
/* 0x000fe8000c101104 */
/*0140*/ STG.E.U8 [R6.64+0x2], R5 ; /* 0x0000020506007986 */
/* 0x000fe2000c101104 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.globl _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.p2align 8
.type _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii,@function
_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_i64_i32 v[2:3], null, v1, 3, s[0:1]
s_clause 0x2
global_load_u8 v0, v[2:3], off
global_load_u8 v4, v[2:3], off offset:1
global_load_u8 v2, v[2:3], off offset:2
s_waitcnt vmcnt(1)
v_add_nc_u16 v0, v4, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u16 v0, v0, v2
v_mad_i64_i32 v[2:3], null, v1, 3, s[2:3]
v_and_b32_e32 v0, 0xffff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v0, 0x5556, v0
v_lshrrev_b32_e32 v0, 16, v0
s_clause 0x2
global_store_b8 v[2:3], v0, off
global_store_b8 v[2:3], v0, off offset:1
global_store_b8 v[2:3], v0, off offset:2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00025f45_00000000-6_grayScale2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii
.type _Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii, @function
_Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10grayScale2P6uchar3S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii, .-_Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii
.globl _Z10grayScale2P6uchar3S0_ii
.type _Z10grayScale2P6uchar3S0_ii, @function
_Z10grayScale2P6uchar3S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10grayScale2P6uchar3S0_iiP6uchar3S0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10grayScale2P6uchar3S0_ii, .-_Z10grayScale2P6uchar3S0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10grayScale2P6uchar3S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10grayScale2P6uchar3S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "grayScale2.hip"
.globl _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.p2align 4, 0x90
.type _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii,@function
_Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii: # @_Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii,@object # @_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.section .rodata,"a",@progbits
.globl _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.p2align 3, 0x0
_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii:
.quad _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.size _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__grayScale2P15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10grayScale2P15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sync_ndconv_groups() { } | code for sm_80
Function : _Z18sync_ndconv_groupsv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sync_ndconv_groups() { } | .file "tmpxft_000b925a_00000000-6_sync_ndconv_groups.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z18sync_ndconv_groupsvv
.type _Z37__device_stub__Z18sync_ndconv_groupsvv, @function
_Z37__device_stub__Z18sync_ndconv_groupsvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z18sync_ndconv_groupsv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z18sync_ndconv_groupsvv, .-_Z37__device_stub__Z18sync_ndconv_groupsvv
.globl _Z18sync_ndconv_groupsv
.type _Z18sync_ndconv_groupsv, @function
_Z18sync_ndconv_groupsv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z18sync_ndconv_groupsvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18sync_ndconv_groupsv, .-_Z18sync_ndconv_groupsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18sync_ndconv_groupsv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18sync_ndconv_groupsv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sync_ndconv_groups() { } | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sync_ndconv_groups() { } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sync_ndconv_groups() { } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18sync_ndconv_groupsv
.globl _Z18sync_ndconv_groupsv
.p2align 8
.type _Z18sync_ndconv_groupsv,@function
_Z18sync_ndconv_groupsv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18sync_ndconv_groupsv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18sync_ndconv_groupsv, .Lfunc_end0-_Z18sync_ndconv_groupsv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18sync_ndconv_groupsv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z18sync_ndconv_groupsv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sync_ndconv_groups() { } | .text
.file "sync_ndconv_groups.hip"
.globl _Z33__device_stub__sync_ndconv_groupsv # -- Begin function _Z33__device_stub__sync_ndconv_groupsv
.p2align 4, 0x90
.type _Z33__device_stub__sync_ndconv_groupsv,@function
_Z33__device_stub__sync_ndconv_groupsv: # @_Z33__device_stub__sync_ndconv_groupsv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z18sync_ndconv_groupsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z33__device_stub__sync_ndconv_groupsv, .Lfunc_end0-_Z33__device_stub__sync_ndconv_groupsv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18sync_ndconv_groupsv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18sync_ndconv_groupsv,@object # @_Z18sync_ndconv_groupsv
.section .rodata,"a",@progbits
.globl _Z18sync_ndconv_groupsv
.p2align 3, 0x0
_Z18sync_ndconv_groupsv:
.quad _Z33__device_stub__sync_ndconv_groupsv
.size _Z18sync_ndconv_groupsv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18sync_ndconv_groupsv"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__sync_ndconv_groupsv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18sync_ndconv_groupsv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18sync_ndconv_groupsv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18sync_ndconv_groupsv
.globl _Z18sync_ndconv_groupsv
.p2align 8
.type _Z18sync_ndconv_groupsv,@function
_Z18sync_ndconv_groupsv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18sync_ndconv_groupsv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18sync_ndconv_groupsv, .Lfunc_end0-_Z18sync_ndconv_groupsv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18sync_ndconv_groupsv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z18sync_ndconv_groupsv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b925a_00000000-6_sync_ndconv_groups.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z18sync_ndconv_groupsvv
.type _Z37__device_stub__Z18sync_ndconv_groupsvv, @function
_Z37__device_stub__Z18sync_ndconv_groupsvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z18sync_ndconv_groupsv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z18sync_ndconv_groupsvv, .-_Z37__device_stub__Z18sync_ndconv_groupsvv
.globl _Z18sync_ndconv_groupsv
.type _Z18sync_ndconv_groupsv, @function
_Z18sync_ndconv_groupsv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z18sync_ndconv_groupsvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18sync_ndconv_groupsv, .-_Z18sync_ndconv_groupsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18sync_ndconv_groupsv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18sync_ndconv_groupsv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sync_ndconv_groups.hip"
.globl _Z33__device_stub__sync_ndconv_groupsv # -- Begin function _Z33__device_stub__sync_ndconv_groupsv
.p2align 4, 0x90
.type _Z33__device_stub__sync_ndconv_groupsv,@function
_Z33__device_stub__sync_ndconv_groupsv: # @_Z33__device_stub__sync_ndconv_groupsv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z18sync_ndconv_groupsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z33__device_stub__sync_ndconv_groupsv, .Lfunc_end0-_Z33__device_stub__sync_ndconv_groupsv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18sync_ndconv_groupsv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18sync_ndconv_groupsv,@object # @_Z18sync_ndconv_groupsv
.section .rodata,"a",@progbits
.globl _Z18sync_ndconv_groupsv
.p2align 3, 0x0
_Z18sync_ndconv_groupsv:
.quad _Z33__device_stub__sync_ndconv_groupsv
.size _Z18sync_ndconv_groupsv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18sync_ndconv_groupsv"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__sync_ndconv_groupsv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18sync_ndconv_groupsv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <asm/unistd.h>
#include <fcntl.h>
#include <inttypes.h>
#include <linux/kernel-page-flags.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mount.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/sysinfo.h>
#include <sys/wait.h>
#include <time.h>
#include <unistd.h>
#include <vector>
#include <sys/time.h>
#include <assert.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true)
{
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads, float * dsum ,volatile int * d_mapping, int cnt, int fence_system_flag, int fence_block_flag)
{
int i;
/*printf("D: i am [%d] \n", blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x);
*/
for(i=0; i < cnt ; i++){
*dsum = i;
d_mapping[0] = *dsum;
if(fence_system_flag){
__threadfence_system();
}
if(fence_block_flag){
__threadfence_block();
}
}
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, cnt =10000, fence_system_flag =0, fence_block_flag = 0;
cudaEvent_t start, stop;
float elapsed_time =0;
gpuErrchk(cudaEventCreate(&start));
gpuErrchk(cudaEventCreate(&stop));
while ((opt = getopt(argc, argv, "b:t:n:f:s:")) != -1) {
switch (opt) {
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'n':
cnt = atoi(optarg);
break;
case 'f':
fence_system_flag = atoi(optarg);
break;
case 's':
fence_block_flag = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
float * dsum;
gpuErrchk(cudaMallocManaged((void **) &dsum, sizeof(uint64_t)));
volatile int * h_mapping;
gpuErrchk(cudaHostAlloc( (void**)&h_mapping, sizeof(volatile int), cudaHostAllocMapped));
volatile int * d_mapping;
gpuErrchk(cudaHostGetDevicePointer((void**)&d_mapping,(void*)h_mapping,0));
*dsum = 0;
cudaEventRecord(start, 0);
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS,dsum,d_mapping, cnt, fence_system_flag, fence_block_flag);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaEventRecord(stop, 0));
gpuErrchk(cudaEventSynchronize(stop));
gpuErrchk(cudaEventElapsedTime
(&elapsed_time, start, stop));
assert(*dsum != 0);
printf("H: elapsed_time is : %f \n", elapsed_time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | code for sm_80
Function : _Z6kerneliPfPViiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05270 */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe40007ffe0ff */
/*0070*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fd200078ec0ff */
/*0080*/ @!P0 BRA 0x570 ; /* 0x000004e000008947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*00a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fd80008000000 */
/*00b0*/ @!P0 BRA 0x420 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R6, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0120*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x009e220008201400 */
/*0130*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0140*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f25270 */
/*0150*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fcc0003f0f070 */
/*0170*/ I2F R11, UR5 ; /* 0x00000005000b7d06 */
/* 0x004fe20008201400 */
/*0180*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fe2000fffe03f */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ec000c101908 */
/*01a0*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x000e70000020f100 */
/*01b0*/ I2F R15, UR6 ; /* 0x00000006000f7d06 */
/* 0x000ea20008201400 */
/*01c0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0021ee000c115908 */
/*01d0*/ I2F R17, UR5 ; /* 0x0000000500117d06 */
/* 0x000e700008201400 */
/*01e0*/ F2I.TRUNC.NTZ R13, R11 ; /* 0x0000000b000d7305 */
/* 0x0000e2000020f100 */
/*01f0*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*0200*/ ERRBAR ; /* 0x00000000000079ab */
/* 0x004fc00000000000 */
/*0210*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0220*/ @!P1 BRA 0x250 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0230*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0250*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e2000c101908 */
/*0260*/ F2I.TRUNC.NTZ R7, R15 ; /* 0x0000000f00077305 */
/* 0x001426000020f100 */
/*0270*/ STG.E.STRONG.SYS [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0085e2000c115908 */
/*0280*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*0290*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*02a0*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*02b0*/ @P0 BRA 0x2d0 ; /* 0x0000001000000947 */
/* 0x000fea0003800000 */
/*02c0*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*02d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e2000c101908 */
/*02e0*/ F2I.TRUNC.NTZ R9, R17 ; /* 0x0000001100097305 */
/* 0x002662000020f100 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0300*/ STG.E.STRONG.SYS [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0017e2000c115908 */
/*0310*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*0320*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0330*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0340*/ @!P1 BRA 0x370 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0350*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0360*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0370*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e2000c101908 */
/*0380*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc60007ffe0ff */
/*0390*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0021e2000c115908 */
/*03a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*03b0*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*03c0*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*03d0*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*03e0*/ @P0 BRA 0x400 ; /* 0x0000001000000947 */
/* 0x000fea0003800000 */
/*03f0*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0400*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0410*/ @P1 BRA 0x120 ; /* 0xfffffd0000001947 */
/* 0x000ff0000383ffff */
/*0420*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x00dfe400078e00ff */
/*0450*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0470*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0480*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x002e220008201400 */
/*0490*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f25270 */
/*04b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*04c0*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x001e22000020f100 */
/*04d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c101908 */
/*04e0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0013e2000c115908 */
/*04f0*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*0500*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0510*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0520*/ @!P1 BRA 0x540 ; /* 0x0000001000009947 */
/* 0x000fea0003800000 */
/*0530*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0540*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0550*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0560*/ BRA 0x480 ; /* 0xffffff1000007947 */
/* 0x000ff0000383ffff */
/*0570*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fda0003f05270 */
/*0580*/ @!P0 BRA 0x8d0 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*05a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fd80008000000 */
/*05b0*/ @!P0 BRA 0x7d0 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*05c0*/ IADD3 R6, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a10 */
/* 0x000fe20007ffe1ff */
/*05d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*05e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*05f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0600*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0610*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0620*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x004e220008201400 */
/*0630*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe4000fffe03f */
/*0640*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fce000fffe03f */
/*0650*/ I2F R11, UR5 ; /* 0x00000005000b7d06 */
/* 0x002fe20008201400 */
/*0660*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fe2000fffe03f */
/*0670*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ec000c101908 */
/*0680*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x000e70000020f100 */
/*0690*/ I2F R15, UR6 ; /* 0x00000006000f7d06 */
/* 0x008ea20008201400 */
/*06a0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0021ee000c115908 */
/*06b0*/ I2F R19, UR5 ; /* 0x0000000500137d06 */
/* 0x000e700008201400 */
/*06c0*/ F2I.TRUNC.NTZ R13, R11 ; /* 0x0000000b000d7305 */
/* 0x0000f0000020f100 */
/*06d0*/ F2I.TRUNC.NTZ R17, R15 ; /* 0x0000000f00117305 */
/* 0x0040a2000020f100 */
/*06e0*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*06f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0023e2000c101908 */
/*0700*/ F2I.TRUNC.NTZ R7, R19 ; /* 0x0000001300077305 */
/* 0x001226000020f100 */
/*0710*/ STG.E.STRONG.SYS [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0083e2000c115908 */
/*0720*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0730*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101908 */
/*0740*/ STG.E.STRONG.SYS [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0047e2000c115908 */
/*0750*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0760*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e2000c101908 */
/*0770*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc60007ffe0ff */
/*0780*/ STG.E.STRONG.SYS [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0015e2000c115908 */
/*0790*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*07a0*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000ff60000000000 */
/*07b0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*07c0*/ @P0 BRA 0x620 ; /* 0xfffffe5000000947 */
/* 0x000ff0000383ffff */
/*07d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*07e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x00efe400078e00ff */
/*0800*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0820*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0830*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x002e220008201400 */
/*0840*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0850*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*0860*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x001e22000020f100 */
/*0870*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c101908 */
/*0880*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0013e2000c115908 */
/*0890*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*08a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*08c0*/ BRA 0x830 ; /* 0xffffff6000007947 */
/* 0x000ff0000383ffff */
/*08d0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*08e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*08f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f05270 */
/*0900*/ @!P1 BRA 0xab0 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0910*/ IADD3 R6, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a10 */
/* 0x000fe20007ffe1ff */
/*0920*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0930*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0940*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe400078e00ff */
/*0950*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0970*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0980*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x001e220008201400 */
/*0990*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*09a0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09b0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*09c0*/ I2F R8, UR5 ; /* 0x0000000500087d06 */
/* 0x000e620008201400 */
/*09d0*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fe4000fffe03f */
/*09e0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fca000fffe03f */
/*09f0*/ I2F R10, UR6 ; /* 0x00000006000a7d06 */
/* 0x000eb00008201400 */
/*0a00*/ I2F R13, UR5 ; /* 0x00000005000d7d06 */
/* 0x000ff00008201400 */
/*0a10*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x001e30000020f100 */
/*0a20*/ F2I.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x002e70000020f100 */
/*0a30*/ F2I.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x004ea2000020f100 */
/*0a40*/ STG.E.STRONG.SYS [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ee000c115908 */
/*0a50*/ F2I.TRUNC.NTZ R15, R13 ; /* 0x0000000d000f7305 */
/* 0x000ee2000020f100 */
/*0a60*/ STG.E.STRONG.SYS [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0021e8000c115908 */
/*0a70*/ STG.E.STRONG.SYS [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0041e8000c115908 */
/*0a80*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e8000c101908 */
/*0a90*/ STG.E.STRONG.SYS [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0081e2000c115908 */
/*0aa0*/ @P1 BRA 0x970 ; /* 0xfffffec000001947 */
/* 0x000fea000383ffff */
/*0ab0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x001fe400078e00ff */
/*0ad0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc400078e00ff */
/*0ae0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0af0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0b00*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x002e220008201400 */
/*0b10*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc6000fffe03f */
/*0b30*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*0b40*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x001e22000020f100 */
/*0b50*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c101908 */
/*0b60*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0013ea000c115908 */
/*0b70*/ @P0 BRA 0xb00 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0b80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <asm/unistd.h>
#include <fcntl.h>
#include <inttypes.h>
#include <linux/kernel-page-flags.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mount.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/sysinfo.h>
#include <sys/wait.h>
#include <time.h>
#include <unistd.h>
#include <vector>
#include <sys/time.h>
#include <assert.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true)
{
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads, float * dsum ,volatile int * d_mapping, int cnt, int fence_system_flag, int fence_block_flag)
{
int i;
/*printf("D: i am [%d] \n", blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x);
*/
for(i=0; i < cnt ; i++){
*dsum = i;
d_mapping[0] = *dsum;
if(fence_system_flag){
__threadfence_system();
}
if(fence_block_flag){
__threadfence_block();
}
}
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, cnt =10000, fence_system_flag =0, fence_block_flag = 0;
cudaEvent_t start, stop;
float elapsed_time =0;
gpuErrchk(cudaEventCreate(&start));
gpuErrchk(cudaEventCreate(&stop));
while ((opt = getopt(argc, argv, "b:t:n:f:s:")) != -1) {
switch (opt) {
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'n':
cnt = atoi(optarg);
break;
case 'f':
fence_system_flag = atoi(optarg);
break;
case 's':
fence_block_flag = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
float * dsum;
gpuErrchk(cudaMallocManaged((void **) &dsum, sizeof(uint64_t)));
volatile int * h_mapping;
gpuErrchk(cudaHostAlloc( (void**)&h_mapping, sizeof(volatile int), cudaHostAllocMapped));
volatile int * d_mapping;
gpuErrchk(cudaHostGetDevicePointer((void**)&d_mapping,(void*)h_mapping,0));
*dsum = 0;
cudaEventRecord(start, 0);
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS,dsum,d_mapping, cnt, fence_system_flag, fence_block_flag);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaEventRecord(stop, 0));
gpuErrchk(cudaEventSynchronize(stop));
gpuErrchk(cudaEventElapsedTime
(&elapsed_time, start, stop));
assert(*dsum != 0);
printf("H: elapsed_time is : %f \n", elapsed_time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_0002120d_00000000-6_fence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3440:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3440:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3436:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3436:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii
.type _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii, @function
_Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii:
.LFB3462:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kerneliPfPViiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3462:
.size _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii, .-_Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii
.globl _Z6kerneliPfPViiii
.type _Z6kerneliPfPViiii, @function
_Z6kerneliPfPViiii:
.LFB3463:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3463:
.size _Z6kerneliPfPViiii, .-_Z6kerneliPfPViiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gganagno/GHammer/master/2_indexing_and_synchronisation/fencing/fence_test/fence.cu"
.align 8
.LC3:
.string "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "b:t:n:f:s:"
.LC5:
.string "H: elapsed_time is : %f \n"
.text
.globl main
.type main, @function
main:
.LFB3437:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r12d
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0x00000000, 20(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $69, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $70, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, 12(%rsp)
movl $0, 8(%rsp)
movl $10000, 4(%rsp)
movl $1, %r15d
movl $1, %r14d
leaq .LC4(%rip), %r13
leaq .L23(%rip), %rbx
jmp .L20
.L27:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r14d
.L20:
movq %r13, %rdx
movq %rbp, %rsi
movl %r12d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L33
subl $98, %eax
cmpl $18, %eax
ja .L21
movl %eax, %eax
movslq (%rbx,%rax,4), %rax
addq %rbx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L23:
.long .L27-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L26-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L25-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L24-.L23
.long .L22-.L23
.text
.L22:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
jmp .L20
.L25:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
jmp .L20
.L26:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
jmp .L20
.L24:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 12(%rsp)
jmp .L20
.L21:
movq 0(%rbp), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
leaq 40(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $102, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 48(%rsp), %rdi
movl $2, %edx
movl $4, %esi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $107, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 56(%rsp), %rdi
movl $0, %edx
movq 48(%rsp), %rsi
call cudaHostGetDevicePointer@PLT
movl %eax, %edi
movl $1, %ecx
movl $111, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 40(%rsp), %rax
movl $0x00000000, (%rax)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, 76(%rsp)
movl $1, 80(%rsp)
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $121, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $1, %ecx
movl $123, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $125, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $1, %ecx
movl $127, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %r14d, %edi
imull %r15d, %edi
movl 12(%rsp), %r9d
movl 8(%rsp), %r8d
movl 4(%rsp), %ecx
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3437:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z6kerneliPfPViiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3465:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kerneliPfPViiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3465:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <asm/unistd.h>
#include <fcntl.h>
#include <inttypes.h>
#include <linux/kernel-page-flags.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mount.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/sysinfo.h>
#include <sys/wait.h>
#include <time.h>
#include <unistd.h>
#include <vector>
#include <sys/time.h>
#include <assert.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true)
{
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads, float * dsum ,volatile int * d_mapping, int cnt, int fence_system_flag, int fence_block_flag)
{
int i;
/*printf("D: i am [%d] \n", blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x);
*/
for(i=0; i < cnt ; i++){
*dsum = i;
d_mapping[0] = *dsum;
if(fence_system_flag){
__threadfence_system();
}
if(fence_block_flag){
__threadfence_block();
}
}
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, cnt =10000, fence_system_flag =0, fence_block_flag = 0;
cudaEvent_t start, stop;
float elapsed_time =0;
gpuErrchk(cudaEventCreate(&start));
gpuErrchk(cudaEventCreate(&stop));
while ((opt = getopt(argc, argv, "b:t:n:f:s:")) != -1) {
switch (opt) {
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'n':
cnt = atoi(optarg);
break;
case 'f':
fence_system_flag = atoi(optarg);
break;
case 's':
fence_block_flag = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
float * dsum;
gpuErrchk(cudaMallocManaged((void **) &dsum, sizeof(uint64_t)));
volatile int * h_mapping;
gpuErrchk(cudaHostAlloc( (void**)&h_mapping, sizeof(volatile int), cudaHostAllocMapped));
volatile int * d_mapping;
gpuErrchk(cudaHostGetDevicePointer((void**)&d_mapping,(void*)h_mapping,0));
*dsum = 0;
cudaEventRecord(start, 0);
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS,dsum,d_mapping, cnt, fence_system_flag, fence_block_flag);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaEventRecord(stop, 0));
gpuErrchk(cudaEventSynchronize(stop));
gpuErrchk(cudaEventElapsedTime
(&elapsed_time, start, stop));
assert(*dsum != 0);
printf("H: elapsed_time is : %f \n", elapsed_time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <asm/unistd.h>
#include <fcntl.h>
#include <inttypes.h>
#include <linux/kernel-page-flags.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mount.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/sysinfo.h>
#include <sys/wait.h>
#include <time.h>
#include <unistd.h>
#include <vector>
#include <sys/time.h>
#include <assert.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true)
{
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads, float * dsum ,volatile int * d_mapping, int cnt, int fence_system_flag, int fence_block_flag)
{
int i;
/*printf("D: i am [%d] \n", blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x);
*/
for(i=0; i < cnt ; i++){
*dsum = i;
d_mapping[0] = *dsum;
if(fence_system_flag){
__threadfence_system();
}
if(fence_block_flag){
__threadfence_block();
}
}
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, cnt =10000, fence_system_flag =0, fence_block_flag = 0;
hipEvent_t start, stop;
float elapsed_time =0;
gpuErrchk(hipEventCreate(&start));
gpuErrchk(hipEventCreate(&stop));
while ((opt = getopt(argc, argv, "b:t:n:f:s:")) != -1) {
switch (opt) {
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'n':
cnt = atoi(optarg);
break;
case 'f':
fence_system_flag = atoi(optarg);
break;
case 's':
fence_block_flag = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
float * dsum;
gpuErrchk(hipMallocManaged((void **) &dsum, sizeof(uint64_t)));
volatile int * h_mapping;
gpuErrchk(hipHostAlloc( (void**)&h_mapping, sizeof(volatile int), hipHostMallocMapped));
volatile int * d_mapping;
gpuErrchk(hipHostGetDevicePointer((void**)&d_mapping,(void*)h_mapping,0));
*dsum = 0;
hipEventRecord(start, 0);
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS,dsum,d_mapping, cnt, fence_system_flag, fence_block_flag);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipEventRecord(stop, 0));
gpuErrchk(hipEventSynchronize(stop));
gpuErrchk(hipEventElapsedTime
(&elapsed_time, start, stop));
assert(*dsum != 0);
printf("H: elapsed_time is : %f \n", elapsed_time);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <asm/unistd.h>
#include <fcntl.h>
#include <inttypes.h>
#include <linux/kernel-page-flags.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mount.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/sysinfo.h>
#include <sys/wait.h>
#include <time.h>
#include <unistd.h>
#include <vector>
#include <sys/time.h>
#include <assert.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true)
{
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads, float * dsum ,volatile int * d_mapping, int cnt, int fence_system_flag, int fence_block_flag)
{
int i;
/*printf("D: i am [%d] \n", blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x);
*/
for(i=0; i < cnt ; i++){
*dsum = i;
d_mapping[0] = *dsum;
if(fence_system_flag){
__threadfence_system();
}
if(fence_block_flag){
__threadfence_block();
}
}
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, cnt =10000, fence_system_flag =0, fence_block_flag = 0;
hipEvent_t start, stop;
float elapsed_time =0;
gpuErrchk(hipEventCreate(&start));
gpuErrchk(hipEventCreate(&stop));
while ((opt = getopt(argc, argv, "b:t:n:f:s:")) != -1) {
switch (opt) {
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'n':
cnt = atoi(optarg);
break;
case 'f':
fence_system_flag = atoi(optarg);
break;
case 's':
fence_block_flag = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
float * dsum;
gpuErrchk(hipMallocManaged((void **) &dsum, sizeof(uint64_t)));
volatile int * h_mapping;
gpuErrchk(hipHostAlloc( (void**)&h_mapping, sizeof(volatile int), hipHostMallocMapped));
volatile int * d_mapping;
gpuErrchk(hipHostGetDevicePointer((void**)&d_mapping,(void*)h_mapping,0));
*dsum = 0;
hipEventRecord(start, 0);
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS,dsum,d_mapping, cnt, fence_system_flag, fence_block_flag);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipEventRecord(stop, 0));
gpuErrchk(hipEventSynchronize(stop));
gpuErrchk(hipEventElapsedTime
(&elapsed_time, start, stop));
assert(*dsum != 0);
printf("H: elapsed_time is : %f \n", elapsed_time);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kerneliPfPViiii
.globl _Z6kerneliPfPViiii
.p2align 8
.type _Z6kerneliPfPViiii,@function
_Z6kerneliPfPViiii:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s8, 0
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
s_cselect_b32 s0, -1, 0
s_cmp_lg_u32 s9, 0
v_cndmask_b32_e64 v3, 0, 1, s0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, 0, 1, s0
v_cmp_ne_u32_e64 s0, 1, v3
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e64 s1, 1, v4
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, s3
s_cbranch_scc0 .LBB0_7
.LBB0_3:
v_cvt_f32_i32_e32 v3, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s0
v_cvt_i32_f32_e32 v4, v3
global_store_b32 v2, v3, s[4:5]
flat_store_b32 v[0:1], v4 dlc
s_waitcnt_vscnt null, 0x0
s_cbranch_vccnz .LBB0_5
s_waitcnt lgkmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
.LBB0_5:
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_2
s_waitcnt lgkmcnt(0)
buffer_gl0_inv
s_branch .LBB0_2
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kerneliPfPViiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kerneliPfPViiii, .Lfunc_end0-_Z6kerneliPfPViiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kerneliPfPViiii
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z6kerneliPfPViiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <asm/unistd.h>
#include <fcntl.h>
#include <inttypes.h>
#include <linux/kernel-page-flags.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mount.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/sysinfo.h>
#include <sys/wait.h>
#include <time.h>
#include <unistd.h>
#include <vector>
#include <sys/time.h>
#include <assert.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true)
{
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code),
file, line);
if (abort)
exit(code);
}
}
__global__ void kernel(int number_of_threads, float * dsum ,volatile int * d_mapping, int cnt, int fence_system_flag, int fence_block_flag)
{
int i;
/*printf("D: i am [%d] \n", blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x);
*/
for(i=0; i < cnt ; i++){
*dsum = i;
d_mapping[0] = *dsum;
if(fence_system_flag){
__threadfence_system();
}
if(fence_block_flag){
__threadfence_block();
}
}
}
int main(int argc, char **argv)
{
int opt, BLOCKS = 1, THREADS = 1, cnt =10000, fence_system_flag =0, fence_block_flag = 0;
hipEvent_t start, stop;
float elapsed_time =0;
gpuErrchk(hipEventCreate(&start));
gpuErrchk(hipEventCreate(&stop));
while ((opt = getopt(argc, argv, "b:t:n:f:s:")) != -1) {
switch (opt) {
case 'b':
BLOCKS = atoi(optarg);
break;
case 't':
THREADS = atoi(optarg);
break;
case 'n':
cnt = atoi(optarg);
break;
case 'f':
fence_system_flag = atoi(optarg);
break;
case 's':
fence_block_flag = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n",
argv[0]);
exit(EXIT_FAILURE);
}
}
float * dsum;
gpuErrchk(hipMallocManaged((void **) &dsum, sizeof(uint64_t)));
volatile int * h_mapping;
gpuErrchk(hipHostAlloc( (void**)&h_mapping, sizeof(volatile int), hipHostMallocMapped));
volatile int * d_mapping;
gpuErrchk(hipHostGetDevicePointer((void**)&d_mapping,(void*)h_mapping,0));
*dsum = 0;
hipEventRecord(start, 0);
kernel <<< BLOCKS, THREADS >>> (BLOCKS * THREADS,dsum,d_mapping, cnt, fence_system_flag, fence_block_flag);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipEventRecord(stop, 0));
gpuErrchk(hipEventSynchronize(stop));
gpuErrchk(hipEventElapsedTime
(&elapsed_time, start, stop));
assert(*dsum != 0);
printf("H: elapsed_time is : %f \n", elapsed_time);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.file "fence.hip"
.globl _Z21__device_stub__kerneliPfPViiii # -- Begin function _Z21__device_stub__kerneliPfPViiii
.p2align 4, 0x90
.type _Z21__device_stub__kerneliPfPViiii,@function
_Z21__device_stub__kerneliPfPViiii: # @_Z21__device_stub__kerneliPfPViiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kerneliPfPViiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__kerneliPfPViiii, .Lfunc_end0-_Z21__device_stub__kerneliPfPViiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
movl %edi, %ebx
movl $0, 12(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_32
# %bb.4: # %_Z9gpuAssert10hipError_tPKcib.exit23.outer.preheader
movl $1, %r12d
movl $10000, %r14d # imm = 0x2710
xorl %eax, %eax
movq %rax, 48(%rsp) # 8-byte Spill
xorl %r15d, %r15d
movl $1, %r13d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
.LBB1_5: # %_Z9gpuAssert10hipError_tPKcib.exit23
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edx
movl %ebx, %edi
movq %rbp, %rsi
callq getopt
# kill: def $eax killed $eax def $rax
cmpl $98, %eax
je .LBB1_10
# %bb.6: # %_Z9gpuAssert10hipError_tPKcib.exit23
# in Loop: Header=BB1_5 Depth=1
leal -102(%rax), %ecx
cmpl $14, %ecx
ja .LBB1_7
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit23
# in Loop: Header=BB1_5 Depth=1
jmpq *.LJTI1_0(,%rcx,8)
.LBB1_13: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
jmp .LBB1_5
.LBB1_11: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
jmp .LBB1_5
.LBB1_12: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB1_5
.LBB1_14: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 48(%rsp) # 8-byte Spill
jmp .LBB1_5
.LBB1_7: # %_Z9gpuAssert10hipError_tPKcib.exit23
cmpl $-1, %eax
jne .LBB1_8
# %bb.15:
leaq 56(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit25
leaq 72(%rsp), %rdi
movl $4, %esi
movl $2, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit27
movq 72(%rsp), %rsi
leaq 64(%rsp), %rdi
xorl %edx, %edx
callq hipHostGetDevicePointer
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit29
movq 56(%rsp), %rax
movl $0, (%rax)
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_23
# %bb.22:
imull %r12d, %r13d
movq 56(%rsp), %rax
movq 64(%rsp), %rcx
movl %r13d, 44(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %r14d, 40(%rsp)
movl %r15d, 36(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 32(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 136(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6kerneliPfPViiii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_23:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit31
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit33
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_28
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit35
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit37
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rdi
movq (%rbp), %rdx
movl $.L.str.2, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $69, %r8d
jmp .LBB1_2
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $70, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $102, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $107, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $111, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $121, %r8d
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $123, %r8d
jmp .LBB1_2
.LBB1_28:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
jmp .LBB1_2
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $128, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI1_0:
.quad .LBB1_13
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_12
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_14
.quad .LBB1_11
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kerneliPfPViiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kerneliPfPViiii,@object # @_Z6kerneliPfPViiii
.section .rodata,"a",@progbits
.globl _Z6kerneliPfPViiii
.p2align 3, 0x0
_Z6kerneliPfPViiii:
.quad _Z21__device_stub__kerneliPfPViiii
.size _Z6kerneliPfPViiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gganagno/GHammer/master/2_indexing_and_synchronisation/fencing/fence_test/fence.hip"
.size .L.str, 141
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "b:t:n:f:s:"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n"
.size .L.str.2, 96
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "H: elapsed_time is : %f \n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kerneliPfPViiii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kerneliPfPViiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kerneliPfPViiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kerneliPfPViiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05270 */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe40007ffe0ff */
/*0070*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fd200078ec0ff */
/*0080*/ @!P0 BRA 0x570 ; /* 0x000004e000008947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*00a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fd80008000000 */
/*00b0*/ @!P0 BRA 0x420 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R6, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0120*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x009e220008201400 */
/*0130*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0140*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f25270 */
/*0150*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fcc0003f0f070 */
/*0170*/ I2F R11, UR5 ; /* 0x00000005000b7d06 */
/* 0x004fe20008201400 */
/*0180*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fe2000fffe03f */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ec000c101908 */
/*01a0*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x000e70000020f100 */
/*01b0*/ I2F R15, UR6 ; /* 0x00000006000f7d06 */
/* 0x000ea20008201400 */
/*01c0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0021ee000c115908 */
/*01d0*/ I2F R17, UR5 ; /* 0x0000000500117d06 */
/* 0x000e700008201400 */
/*01e0*/ F2I.TRUNC.NTZ R13, R11 ; /* 0x0000000b000d7305 */
/* 0x0000e2000020f100 */
/*01f0*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*0200*/ ERRBAR ; /* 0x00000000000079ab */
/* 0x004fc00000000000 */
/*0210*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0220*/ @!P1 BRA 0x250 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0230*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0250*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e2000c101908 */
/*0260*/ F2I.TRUNC.NTZ R7, R15 ; /* 0x0000000f00077305 */
/* 0x001426000020f100 */
/*0270*/ STG.E.STRONG.SYS [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0085e2000c115908 */
/*0280*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*0290*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*02a0*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*02b0*/ @P0 BRA 0x2d0 ; /* 0x0000001000000947 */
/* 0x000fea0003800000 */
/*02c0*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*02d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e2000c101908 */
/*02e0*/ F2I.TRUNC.NTZ R9, R17 ; /* 0x0000001100097305 */
/* 0x002662000020f100 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0300*/ STG.E.STRONG.SYS [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0017e2000c115908 */
/*0310*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*0320*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0330*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0340*/ @!P1 BRA 0x370 ; /* 0x0000002000009947 */
/* 0x000fea0003800000 */
/*0350*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0360*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0370*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e2000c101908 */
/*0380*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc60007ffe0ff */
/*0390*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0021e2000c115908 */
/*03a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*03b0*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*03c0*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*03d0*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*03e0*/ @P0 BRA 0x400 ; /* 0x0000001000000947 */
/* 0x000fea0003800000 */
/*03f0*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0400*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0410*/ @P1 BRA 0x120 ; /* 0xfffffd0000001947 */
/* 0x000ff0000383ffff */
/*0420*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x00dfe400078e00ff */
/*0450*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0470*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0480*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x002e220008201400 */
/*0490*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f25270 */
/*04b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*04c0*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x001e22000020f100 */
/*04d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c101908 */
/*04e0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0013e2000c115908 */
/*04f0*/ MEMBAR.SC.SYS ; /* 0x0000000000007992 */
/* 0x000fec0000003000 */
/*0500*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0510*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0520*/ @!P1 BRA 0x540 ; /* 0x0000001000009947 */
/* 0x000fea0003800000 */
/*0530*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0540*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0550*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0560*/ BRA 0x480 ; /* 0xffffff1000007947 */
/* 0x000ff0000383ffff */
/*0570*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fda0003f05270 */
/*0580*/ @!P0 BRA 0x8d0 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*05a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fd80008000000 */
/*05b0*/ @!P0 BRA 0x7d0 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*05c0*/ IADD3 R6, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a10 */
/* 0x000fe20007ffe1ff */
/*05d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*05e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*05f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0600*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0610*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0620*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x004e220008201400 */
/*0630*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe4000fffe03f */
/*0640*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fce000fffe03f */
/*0650*/ I2F R11, UR5 ; /* 0x00000005000b7d06 */
/* 0x002fe20008201400 */
/*0660*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fe2000fffe03f */
/*0670*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ec000c101908 */
/*0680*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x000e70000020f100 */
/*0690*/ I2F R15, UR6 ; /* 0x00000006000f7d06 */
/* 0x008ea20008201400 */
/*06a0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0021ee000c115908 */
/*06b0*/ I2F R19, UR5 ; /* 0x0000000500137d06 */
/* 0x000e700008201400 */
/*06c0*/ F2I.TRUNC.NTZ R13, R11 ; /* 0x0000000b000d7305 */
/* 0x0000f0000020f100 */
/*06d0*/ F2I.TRUNC.NTZ R17, R15 ; /* 0x0000000f00117305 */
/* 0x0040a2000020f100 */
/*06e0*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*06f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0023e2000c101908 */
/*0700*/ F2I.TRUNC.NTZ R7, R19 ; /* 0x0000001300077305 */
/* 0x001226000020f100 */
/*0710*/ STG.E.STRONG.SYS [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0083e2000c115908 */
/*0720*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0730*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101908 */
/*0740*/ STG.E.STRONG.SYS [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0047e2000c115908 */
/*0750*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*0760*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e2000c101908 */
/*0770*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc60007ffe0ff */
/*0780*/ STG.E.STRONG.SYS [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0015e2000c115908 */
/*0790*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*07a0*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000ff60000000000 */
/*07b0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*07c0*/ @P0 BRA 0x620 ; /* 0xfffffe5000000947 */
/* 0x000ff0000383ffff */
/*07d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*07e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x00efe400078e00ff */
/*0800*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0820*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0830*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x002e220008201400 */
/*0840*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0850*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*0860*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x001e22000020f100 */
/*0870*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c101908 */
/*0880*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0013e2000c115908 */
/*0890*/ MEMBAR.SC.CTA ; /* 0x0000000000007992 */
/* 0x000fec0000000000 */
/*08a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*08c0*/ BRA 0x830 ; /* 0xffffff6000007947 */
/* 0x000ff0000383ffff */
/*08d0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*08e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*08f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f05270 */
/*0900*/ @!P1 BRA 0xab0 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0910*/ IADD3 R6, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a10 */
/* 0x000fe20007ffe1ff */
/*0920*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0930*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0940*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe400078e00ff */
/*0950*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0970*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0980*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x001e220008201400 */
/*0990*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*09a0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09b0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*09c0*/ I2F R8, UR5 ; /* 0x0000000500087d06 */
/* 0x000e620008201400 */
/*09d0*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fe4000fffe03f */
/*09e0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fca000fffe03f */
/*09f0*/ I2F R10, UR6 ; /* 0x00000006000a7d06 */
/* 0x000eb00008201400 */
/*0a00*/ I2F R13, UR5 ; /* 0x00000005000d7d06 */
/* 0x000ff00008201400 */
/*0a10*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x001e30000020f100 */
/*0a20*/ F2I.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x002e70000020f100 */
/*0a30*/ F2I.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x004ea2000020f100 */
/*0a40*/ STG.E.STRONG.SYS [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ee000c115908 */
/*0a50*/ F2I.TRUNC.NTZ R15, R13 ; /* 0x0000000d000f7305 */
/* 0x000ee2000020f100 */
/*0a60*/ STG.E.STRONG.SYS [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0021e8000c115908 */
/*0a70*/ STG.E.STRONG.SYS [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0041e8000c115908 */
/*0a80*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e8000c101908 */
/*0a90*/ STG.E.STRONG.SYS [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0081e2000c115908 */
/*0aa0*/ @P1 BRA 0x970 ; /* 0xfffffec000001947 */
/* 0x000fea000383ffff */
/*0ab0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x001fe400078e00ff */
/*0ad0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc400078e00ff */
/*0ae0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0af0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*0b00*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x002e220008201400 */
/*0b10*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc6000fffe03f */
/*0b30*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*0b40*/ F2I.TRUNC.NTZ R9, R7 ; /* 0x0000000700097305 */
/* 0x001e22000020f100 */
/*0b50*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e8000c101908 */
/*0b60*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0013ea000c115908 */
/*0b70*/ @P0 BRA 0xb00 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0b80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kerneliPfPViiii
.globl _Z6kerneliPfPViiii
.p2align 8
.type _Z6kerneliPfPViiii,@function
_Z6kerneliPfPViiii:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s8, 0
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
s_cselect_b32 s0, -1, 0
s_cmp_lg_u32 s9, 0
v_cndmask_b32_e64 v3, 0, 1, s0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, 0, 1, s0
v_cmp_ne_u32_e64 s0, 1, v3
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e64 s1, 1, v4
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, s3
s_cbranch_scc0 .LBB0_7
.LBB0_3:
v_cvt_f32_i32_e32 v3, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s0
v_cvt_i32_f32_e32 v4, v3
global_store_b32 v2, v3, s[4:5]
flat_store_b32 v[0:1], v4 dlc
s_waitcnt_vscnt null, 0x0
s_cbranch_vccnz .LBB0_5
s_waitcnt lgkmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
.LBB0_5:
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_2
s_waitcnt lgkmcnt(0)
buffer_gl0_inv
s_branch .LBB0_2
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kerneliPfPViiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kerneliPfPViiii, .Lfunc_end0-_Z6kerneliPfPViiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kerneliPfPViiii
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z6kerneliPfPViiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002120d_00000000-6_fence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3440:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3440:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3436:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3436:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii
.type _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii, @function
_Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii:
.LFB3462:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kerneliPfPViiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3462:
.size _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii, .-_Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii
.globl _Z6kerneliPfPViiii
.type _Z6kerneliPfPViiii, @function
_Z6kerneliPfPViiii:
.LFB3463:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3463:
.size _Z6kerneliPfPViiii, .-_Z6kerneliPfPViiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gganagno/GHammer/master/2_indexing_and_synchronisation/fencing/fence_test/fence.cu"
.align 8
.LC3:
.string "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "b:t:n:f:s:"
.LC5:
.string "H: elapsed_time is : %f \n"
.text
.globl main
.type main, @function
main:
.LFB3437:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r12d
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0x00000000, 20(%rsp)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $69, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $1, %ecx
movl $70, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, 12(%rsp)
movl $0, 8(%rsp)
movl $10000, 4(%rsp)
movl $1, %r15d
movl $1, %r14d
leaq .LC4(%rip), %r13
leaq .L23(%rip), %rbx
jmp .L20
.L27:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r14d
.L20:
movq %r13, %rdx
movq %rbp, %rsi
movl %r12d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L33
subl $98, %eax
cmpl $18, %eax
ja .L21
movl %eax, %eax
movslq (%rbx,%rax,4), %rax
addq %rbx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L23:
.long .L27-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L26-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L25-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L21-.L23
.long .L24-.L23
.long .L22-.L23
.text
.L22:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
jmp .L20
.L25:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
jmp .L20
.L26:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
jmp .L20
.L24:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 12(%rsp)
jmp .L20
.L21:
movq 0(%rbp), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
leaq 40(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $102, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 48(%rsp), %rdi
movl $2, %edx
movl $4, %esi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $107, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 56(%rsp), %rdi
movl $0, %edx
movq 48(%rsp), %rsi
call cudaHostGetDevicePointer@PLT
movl %eax, %edi
movl $1, %ecx
movl $111, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 40(%rsp), %rax
movl $0x00000000, (%rax)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, 76(%rsp)
movl $1, 80(%rsp)
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $121, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $1, %ecx
movl $123, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $125, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $1, %ecx
movl $127, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %r14d, %edi
imull %r15d, %edi
movl 12(%rsp), %r9d
movl 8(%rsp), %r8d
movl 4(%rsp), %ecx
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call _Z32__device_stub__Z6kerneliPfPViiiiiPfPViiii
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3437:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z6kerneliPfPViiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3465:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kerneliPfPViiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3465:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fence.hip"
.globl _Z21__device_stub__kerneliPfPViiii # -- Begin function _Z21__device_stub__kerneliPfPViiii
.p2align 4, 0x90
.type _Z21__device_stub__kerneliPfPViiii,@function
_Z21__device_stub__kerneliPfPViiii: # @_Z21__device_stub__kerneliPfPViiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kerneliPfPViiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__kerneliPfPViiii, .Lfunc_end0-_Z21__device_stub__kerneliPfPViiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
movl %edi, %ebx
movl $0, 12(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_32
# %bb.4: # %_Z9gpuAssert10hipError_tPKcib.exit23.outer.preheader
movl $1, %r12d
movl $10000, %r14d # imm = 0x2710
xorl %eax, %eax
movq %rax, 48(%rsp) # 8-byte Spill
xorl %r15d, %r15d
movl $1, %r13d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
.LBB1_5: # %_Z9gpuAssert10hipError_tPKcib.exit23
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edx
movl %ebx, %edi
movq %rbp, %rsi
callq getopt
# kill: def $eax killed $eax def $rax
cmpl $98, %eax
je .LBB1_10
# %bb.6: # %_Z9gpuAssert10hipError_tPKcib.exit23
# in Loop: Header=BB1_5 Depth=1
leal -102(%rax), %ecx
cmpl $14, %ecx
ja .LBB1_7
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit23
# in Loop: Header=BB1_5 Depth=1
jmpq *.LJTI1_0(,%rcx,8)
.LBB1_13: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
jmp .LBB1_5
.LBB1_11: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
jmp .LBB1_5
.LBB1_12: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB1_5
.LBB1_14: # in Loop: Header=BB1_5 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 48(%rsp) # 8-byte Spill
jmp .LBB1_5
.LBB1_7: # %_Z9gpuAssert10hipError_tPKcib.exit23
cmpl $-1, %eax
jne .LBB1_8
# %bb.15:
leaq 56(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit25
leaq 72(%rsp), %rdi
movl $4, %esi
movl $2, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit27
movq 72(%rsp), %rsi
leaq 64(%rsp), %rdi
xorl %edx, %edx
callq hipHostGetDevicePointer
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit29
movq 56(%rsp), %rax
movl $0, (%rax)
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_23
# %bb.22:
imull %r12d, %r13d
movq 56(%rsp), %rax
movq 64(%rsp), %rcx
movl %r13d, 44(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl %r14d, 40(%rsp)
movl %r15d, 36(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 32(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 136(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6kerneliPfPViiii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_23:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit31
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit33
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_28
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit35
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit37
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rdi
movq (%rbp), %rdx
movl $.L.str.2, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $69, %r8d
jmp .LBB1_2
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $70, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $102, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $107, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $111, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $121, %r8d
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $123, %r8d
jmp .LBB1_2
.LBB1_28:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
jmp .LBB1_2
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $128, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI1_0:
.quad .LBB1_13
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_12
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_8
.quad .LBB1_14
.quad .LBB1_11
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kerneliPfPViiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kerneliPfPViiii,@object # @_Z6kerneliPfPViiii
.section .rodata,"a",@progbits
.globl _Z6kerneliPfPViiii
.p2align 3, 0x0
_Z6kerneliPfPViiii:
.quad _Z21__device_stub__kerneliPfPViiii
.size _Z6kerneliPfPViiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gganagno/GHammer/master/2_indexing_and_synchronisation/fencing/fence_test/fence.hip"
.size .L.str, 141
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "b:t:n:f:s:"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Usage: %s -b [blocks] -t [threads] -n [count of iterations] -f [fence_system] -s [fence_block]\n"
.size .L.str.2, 96
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "H: elapsed_time is : %f \n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kerneliPfPViiii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kerneliPfPViiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kerneliPfPViiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void saxpy_float4s_shmem_doublebuffer ( float* y, float* x, float a, clock_t * timer_vals)
{
volatile __shared__ float sdata_x0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_1 [COMPUTE_THREADS_PER_CTA];
int tid = threadIdx.x ;
unsigned int idx0, idx1;
idx0 = blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
idx1 = COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 result_y;
for (int i=0; i < NUM_ITERS/4; i+=2) {
float4 tmp1_x, tmp1_y;
__syncthreads();
tmp1_x = x_as_float4[idx0];
tmp1_y = y_as_float4[idx0];
if (i!=0) {
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
idx1 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
}
sdata_x0_0[tid] = tmp1_x.x;
sdata_x1_0[tid] = tmp1_x.y;
sdata_x2_0[tid] = tmp1_x.z;
sdata_x3_0[tid] = tmp1_x.w;
sdata_y0_0[tid] = tmp1_y.x;
sdata_y1_0[tid] = tmp1_y.y;
sdata_y2_0[tid] = tmp1_y.z;
sdata_y3_0[tid] = tmp1_y.w;
__syncthreads();
tmp1_x = x_as_float4[idx1];
tmp1_y = y_as_float4[idx1];
result_y.x = a * sdata_x0_0[tid] + sdata_y0_0[tid];
result_y.y = a * sdata_x1_0[tid] + sdata_y1_0[tid];
result_y.z = a * sdata_x2_0[tid] + sdata_y2_0[tid];
result_y.w = a * sdata_x3_0[tid] + sdata_y3_0[tid];
y_as_float4[idx0] = result_y;
idx0 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
sdata_x0_1[tid] = tmp1_x.x;
sdata_x1_1[tid] = tmp1_x.y;
sdata_x2_1[tid] = tmp1_x.z;
sdata_x3_1[tid] = tmp1_x.w;
sdata_y0_1[tid] = tmp1_y.x;
sdata_y1_1[tid] = tmp1_y.y;
sdata_y2_1[tid] = tmp1_y.z;
sdata_y3_1[tid] = tmp1_y.w;
}
__syncthreads();
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
} | code for sm_80
Function : _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R2, 0xe00 ; /* 0x00000e0000027802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ LEA R17, R17, R0, 0x7 ; /* 0x0000000011117211 */
/* 0x001fc800078e38ff */
/*0070*/ IADD3 R16, R17, 0x700, RZ ; /* 0x0000070011107810 */
/* 0x000fe40007ffe0ff */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0090*/ MOV R18, 0x10 ; /* 0x0000001000127802 */
/* 0x000fca0000000f00 */
/*00a0*/ IMAD.WIDE.U32 R4, R17, R18, c[0x0][0x168] ; /* 0x00005a0011047625 */
/* 0x001fc800078e0012 */
/*00b0*/ IMAD.WIDE.U32 R20, R17, R18, c[0x0][0x160] ; /* 0x0000580011147625 */
/* 0x000fe400078e0012 */
/*00c0*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1d00 */
/*00d0*/ LDG.E.128 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1d00 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, 0xe00, PT ; /* 0x00000e000200780c */
/* 0x000fda0003f05270 */
/*00f0*/ @P0 LDS R12, [R0.X4+0x1000] ; /* 0x00100000000c0984 */
/* 0x000fe20000004800 */
/*0100*/ @P0 IMAD.WIDE.U32 R24, R16.reuse, R18, c[0x0][0x160] ; /* 0x0000580010180625 */
/* 0x040fe200078e0012 */
/*0110*/ @P0 IADD3 R16, R16, 0xe00, RZ ; /* 0x00000e0010100810 */
/* 0x000fe40007ffe0ff */
/*0120*/ @P0 LDS R13, [R0.X4+0x1800] ; /* 0x00180000000d0984 */
/* 0x000e280000004800 */
/*0130*/ @P0 LDS R14, [R0.X4+0x1200] ; /* 0x00120000000e0984 */
/* 0x000fe80000004800 */
/*0140*/ @P0 LDS R15, [R0.X4+0x1a00] ; /* 0x001a0000000f0984 */
/* 0x000e680000004800 */
/*0150*/ @P0 LDS R19, [R0.X4+0x1400] ; /* 0x0014000000130984 */
/* 0x000fe80000004800 */
/*0160*/ @P0 LDS R22, [R0.X4+0x1c00] ; /* 0x001c000000160984 */
/* 0x000f280000004800 */
/*0170*/ @P0 LDS R23, [R0.X4+0x1600] ; /* 0x0016000000170984 */
/* 0x000fe80000004800 */
/*0180*/ @P0 LDS R26, [R0.X4+0x1e00] ; /* 0x001e0000001a0984 */
/* 0x000f620000004800 */
/*0190*/ @P0 FFMA R12, R12, c[0x0][0x170], R13 ; /* 0x00005c000c0c0a23 */
/* 0x001fc4000000000d */
/*01a0*/ @P0 FFMA R13, R14, c[0x0][0x170], R15 ; /* 0x00005c000e0d0a23 */
/* 0x002fe4000000000f */
/*01b0*/ @P0 FFMA R14, R19, c[0x0][0x170], R22 ; /* 0x00005c00130e0a23 */
/* 0x010fe40000000016 */
/*01c0*/ @P0 FFMA R15, R23, c[0x0][0x170], R26 ; /* 0x00005c00170f0a23 */
/* 0x020fe4000000001a */
/*01d0*/ IMAD.WIDE.U32 R26, R16, R18, c[0x0][0x168] ; /* 0x00005a00101a7625 */
/* 0x000fc600078e0012 */
/*01e0*/ @P0 STG.E.128 [R24.64], R12 ; /* 0x0000000c18000986 */
/* 0x000fe2000c101d04 */
/*01f0*/ IMAD.WIDE.U32 R22, R16, R18, c[0x0][0x160] ; /* 0x0000580010167625 */
/* 0x000fc600078e0012 */
/*0200*/ STS [R0.X4], R4 ; /* 0x0000000400007388 */
/* 0x004fe80000004800 */
/*0210*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x000fe80000004800 */
/*0220*/ STS [R0.X4+0x400], R6 ; /* 0x0004000600007388 */
/* 0x000fe80000004800 */
/*0230*/ STS [R0.X4+0x600], R7 ; /* 0x0006000700007388 */
/* 0x0001e80000004800 */
/*0240*/ STS [R0.X4+0x800], R8 ; /* 0x0008000800007388 */
/* 0x008fe80000004800 */
/*0250*/ STS [R0.X4+0xa00], R9 ; /* 0x000a000900007388 */
/* 0x000fe80000004800 */
/*0260*/ STS [R0.X4+0xc00], R10 ; /* 0x000c000a00007388 */
/* 0x000fe80000004800 */
/*0270*/ STS [R0.X4+0xe00], R11 ; /* 0x000e000b00007388 */
/* 0x0003e80000004800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDG.E.128 R4, [R26.64] ; /* 0x000000041a047981 */
/* 0x0010a8000c1e1d00 */
/*02a0*/ LDG.E.128 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x002ee8000c1e1d00 */
/*02b0*/ LDS R12, [R0.X4] ; /* 0x00000000000c7984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS R13, [R0.X4+0x800] ; /* 0x00080000000d7984 */
/* 0x000e680000004800 */
/*02d0*/ LDS R14, [R0.X4+0x200] ; /* 0x00020000000e7984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS R19, [R0.X4+0xa00] ; /* 0x000a000000137984 */
/* 0x000f280000004800 */
/*02f0*/ LDS R25, [R0.X4+0x400] ; /* 0x0004000000197984 */
/* 0x000fe80000004800 */
/*0300*/ LDS R28, [R0.X4+0xc00] ; /* 0x000c0000001c7984 */
/* 0x000f680000004800 */
/*0310*/ LDS R15, [R0.X4+0x600] ; /* 0x00060000000f7984 */
/* 0x000fe80000004800 */
/*0320*/ LDS R24, [R0.X4+0xe00] ; /* 0x000e000000187984 */
/* 0x000e220000004800 */
/*0330*/ FFMA R12, R12, c[0x0][0x170], R13 ; /* 0x00005c000c0c7a23 */
/* 0x002fc4000000000d */
/*0340*/ FFMA R13, R14, c[0x0][0x170], R19 ; /* 0x00005c000e0d7a23 */
/* 0x010fe40000000013 */
/*0350*/ FFMA R14, R25, c[0x0][0x170], R28 ; /* 0x00005c00190e7a23 */
/* 0x020fe2000000001c */
/*0360*/ IADD3 R25, R17, 0xe00, RZ ; /* 0x00000e0011197810 */
/* 0x000fca0007ffe0ff */
/*0370*/ IMAD.WIDE.U32 R26, R25, R18, c[0x0][0x168] ; /* 0x00005a00191a7625 */
/* 0x001fc800078e0012 */
/*0380*/ FFMA R15, R15, c[0x0][0x170], R24 ; /* 0x00005c000f0f7a23 */
/* 0x000fca0000000018 */
/*0390*/ STG.E.128 [R20.64], R12 ; /* 0x0000000c14007986 */
/* 0x000fe2000c101d04 */
/*03a0*/ IMAD.WIDE.U32 R24, R25, R18, c[0x0][0x160] ; /* 0x0000580019187625 */
/* 0x000fc600078e0012 */
/*03b0*/ STS [R0.X4+0x1000], R4 ; /* 0x0010000400007388 */
/* 0x004fe80000004800 */
/*03c0*/ STS [R0.X4+0x1200], R5 ; /* 0x0012000500007388 */
/* 0x000fe80000004800 */
/*03d0*/ STS [R0.X4+0x1400], R6 ; /* 0x0014000600007388 */
/* 0x000fe80000004800 */
/*03e0*/ STS [R0.X4+0x1600], R7 ; /* 0x0016000700007388 */
/* 0x0001e80000004800 */
/*03f0*/ STS [R0.X4+0x1800], R8 ; /* 0x0018000800007388 */
/* 0x008fe80000004800 */
/*0400*/ STS [R0.X4+0x1a00], R9 ; /* 0x001a000900007388 */
/* 0x000fe80000004800 */
/*0410*/ STS [R0.X4+0x1c00], R10 ; /* 0x001c000a00007388 */
/* 0x000fe80000004800 */
/*0420*/ STS [R0.X4+0x1e00], R11 ; /* 0x001e000b00007388 */
/* 0x0003e80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ LDG.E.128 R4, [R26.64] ; /* 0x000000041a047981 */
/* 0x001ea8000c1e1d00 */
/*0450*/ LDG.E.128 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x002ee2000c1e1d00 */
/*0460*/ IADD3 R16, R16, 0xe00, RZ ; /* 0x00000e0010107810 */
/* 0x000fc60007ffe0ff */
/*0470*/ LDS R12, [R0.X4+0x1000] ; /* 0x00100000000c7984 */
/* 0x000fe80000004800 */
/*0480*/ LDS R13, [R0.X4+0x1800] ; /* 0x00180000000d7984 */
/* 0x000e280000004800 */
/*0490*/ LDS R14, [R0.X4+0x1200] ; /* 0x00120000000e7984 */
/* 0x000fe80000004800 */
/*04a0*/ LDS R15, [R0.X4+0x1a00] ; /* 0x001a0000000f7984 */
/* 0x000e680000004800 */
/*04b0*/ LDS R19, [R0.X4+0x1400] ; /* 0x0014000000137984 */
/* 0x000fe80000004800 */
/*04c0*/ LDS R20, [R0.X4+0x1c00] ; /* 0x001c000000147984 */
/* 0x000f280000004800 */
/*04d0*/ LDS R21, [R0.X4+0x1600] ; /* 0x0016000000157984 */
/* 0x000fe80000004800 */
/*04e0*/ LDS R28, [R0.X4+0x1e00] ; /* 0x001e0000001c7984 */
/* 0x000f620000004800 */
/*04f0*/ FFMA R12, R12, c[0x0][0x170], R13 ; /* 0x00005c000c0c7a23 */
/* 0x001fc4000000000d */
/*0500*/ FFMA R13, R14, c[0x0][0x170], R15 ; /* 0x00005c000e0d7a23 */
/* 0x002fe4000000000f */
/*0510*/ FFMA R14, R19, c[0x0][0x170], R20 ; /* 0x00005c00130e7a23 */
/* 0x010fe40000000014 */
/*0520*/ FFMA R15, R21, c[0x0][0x170], R28 ; /* 0x00005c00150f7a23 */
/* 0x020fe4000000001c */
/*0530*/ IMAD.WIDE.U32 R20, R16, R18, c[0x0][0x168] ; /* 0x00005a0010147625 */
/* 0x000fc600078e0012 */
/*0540*/ STG.E.128 [R22.64], R12 ; /* 0x0000000c16007986 */
/* 0x000fe2000c101d04 */
/*0550*/ IMAD.WIDE.U32 R18, R16, R18, c[0x0][0x160] ; /* 0x0000580010127625 */
/* 0x000fc600078e0012 */
/*0560*/ STS [R0.X4], R4 ; /* 0x0000000400007388 */
/* 0x004fe80000004800 */
/*0570*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x000fe80000004800 */
/*0580*/ STS [R0.X4+0x400], R6 ; /* 0x0004000600007388 */
/* 0x000fe80000004800 */
/*0590*/ STS [R0.X4+0x600], R7 ; /* 0x0006000700007388 */
/* 0x0001e80000004800 */
/*05a0*/ STS [R0.X4+0x800], R8 ; /* 0x0008000800007388 */
/* 0x008fe80000004800 */
/*05b0*/ STS [R0.X4+0xa00], R9 ; /* 0x000a000900007388 */
/* 0x000fe80000004800 */
/*05c0*/ STS [R0.X4+0xc00], R10 ; /* 0x000c000a00007388 */
/* 0x000fe80000004800 */
/*05d0*/ STS [R0.X4+0xe00], R11 ; /* 0x000e000b00007388 */
/* 0x0003e80000004800 */
/*05e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05f0*/ LDG.E.128 R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x001ea8000c1e1d00 */
/*0600*/ LDG.E.128 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x002ee2000c1e1d00 */
/*0610*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc40007ffe0ff */
/*0620*/ IADD3 R2, R2, 0x1c00, RZ ; /* 0x00001c0002027810 */
/* 0x000fe20007ffe0ff */
/*0630*/ LDS R12, [R0.X4] ; /* 0x00000000000c7984 */
/* 0x000fe20000004800 */
/*0640*/ ISETP.GE.U32.AND P0, PT, R3, 0x200, PT ; /* 0x000002000300780c */
/* 0x000fe40003f06070 */
/*0650*/ IADD3 R17, R17, 0x1c00, RZ ; /* 0x00001c0011117810 */
/* 0x000fe20007ffe0ff */
/*0660*/ LDS R13, [R0.X4+0x800] ; /* 0x00080000000d7984 */
/* 0x000e280000004800 */
/*0670*/ LDS R14, [R0.X4+0x200] ; /* 0x00020000000e7984 */
/* 0x000fe80000004800 */
/*0680*/ LDS R15, [R0.X4+0xa00] ; /* 0x000a0000000f7984 */
/* 0x000e680000004800 */
/*0690*/ LDS R22, [R0.X4+0x400] ; /* 0x0004000000167984 */
/* 0x000fe80000004800 */
/*06a0*/ LDS R23, [R0.X4+0xc00] ; /* 0x000c000000177984 */
/* 0x000f280000004800 */
/*06b0*/ LDS R26, [R0.X4+0x600] ; /* 0x00060000001a7984 */
/* 0x000fe80000004800 */
/*06c0*/ LDS R27, [R0.X4+0xe00] ; /* 0x000e0000001b7984 */
/* 0x000f620000004800 */
/*06d0*/ FFMA R12, R12, c[0x0][0x170], R13 ; /* 0x00005c000c0c7a23 */
/* 0x001fc4000000000d */
/*06e0*/ FFMA R13, R14, c[0x0][0x170], R15 ; /* 0x00005c000e0d7a23 */
/* 0x002fe4000000000f */
/*06f0*/ FFMA R14, R22, c[0x0][0x170], R23 ; /* 0x00005c00160e7a23 */
/* 0x010fe40000000017 */
/*0700*/ FFMA R15, R26, c[0x0][0x170], R27 ; /* 0x00005c001a0f7a23 */
/* 0x020fca000000001b */
/*0710*/ STG.E.128 [R24.64], R12 ; /* 0x0000000c18007986 */
/* 0x0001e8000c101d04 */
/*0720*/ STS [R0.X4+0x1000], R4 ; /* 0x0010000400007388 */
/* 0x0041e80000004800 */
/*0730*/ STS [R0.X4+0x1200], R5 ; /* 0x0012000500007388 */
/* 0x0001e80000004800 */
/*0740*/ STS [R0.X4+0x1400], R6 ; /* 0x0014000600007388 */
/* 0x0001e80000004800 */
/*0750*/ STS [R0.X4+0x1600], R7 ; /* 0x0016000700007388 */
/* 0x0001e80000004800 */
/*0760*/ STS [R0.X4+0x1800], R8 ; /* 0x0018000800007388 */
/* 0x0081e80000004800 */
/*0770*/ STS [R0.X4+0x1a00], R9 ; /* 0x001a000900007388 */
/* 0x0001e80000004800 */
/*0780*/ STS [R0.X4+0x1c00], R10 ; /* 0x001c000a00007388 */
/* 0x0001e80000004800 */
/*0790*/ STS [R0.X4+0x1e00], R11 ; /* 0x001e000b00007388 */
/* 0x0001e20000004800 */
/*07a0*/ @!P0 BRA 0x80 ; /* 0xfffff8d000008947 */
/* 0x000fea000383ffff */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ LDS R4, [R0.X4+0x1000] ; /* 0x0010000000047984 */
/* 0x001fe80000004800 */
/*07d0*/ LDS R3, [R0.X4+0x1800] ; /* 0x0018000000037984 */
/* 0x000e280000004800 */
/*07e0*/ LDS R5, [R0.X4+0x1200] ; /* 0x0012000000057984 */
/* 0x000fe80000004800 */
/*07f0*/ LDS R2, [R0.X4+0x1a00] ; /* 0x001a000000027984 */
/* 0x000e680000004800 */
/*0800*/ LDS R6, [R0.X4+0x1400] ; /* 0x0014000000067984 */
/* 0x000fe80000004800 */
/*0810*/ LDS R7, [R0.X4+0x1c00] ; /* 0x001c000000077984 */
/* 0x000ea80000004800 */
/*0820*/ LDS R8, [R0.X4+0x1600] ; /* 0x0016000000087984 */
/* 0x000fe80000004800 */
/*0830*/ LDS R9, [R0.X4+0x1e00] ; /* 0x001e000000097984 */
/* 0x000ee20000004800 */
/*0840*/ FFMA R4, R4, c[0x0][0x170], R3 ; /* 0x00005c0004047a23 */
/* 0x001fc40000000003 */
/*0850*/ FFMA R5, R5, c[0x0][0x170], R2 ; /* 0x00005c0005057a23 */
/* 0x002fe40000000002 */
/*0860*/ FFMA R6, R6, c[0x0][0x170], R7 ; /* 0x00005c0006067a23 */
/* 0x004fe40000000007 */
/*0870*/ FFMA R7, R8, c[0x0][0x170], R9 ; /* 0x00005c0008077a23 */
/* 0x008fca0000000009 */
/*0880*/ STG.E.128 [R18.64], R4 ; /* 0x0000000412007986 */
/* 0x000fe2000c101d04 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void saxpy_float4s_shmem_doublebuffer ( float* y, float* x, float a, clock_t * timer_vals)
{
volatile __shared__ float sdata_x0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_1 [COMPUTE_THREADS_PER_CTA];
int tid = threadIdx.x ;
unsigned int idx0, idx1;
idx0 = blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
idx1 = COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 result_y;
for (int i=0; i < NUM_ITERS/4; i+=2) {
float4 tmp1_x, tmp1_y;
__syncthreads();
tmp1_x = x_as_float4[idx0];
tmp1_y = y_as_float4[idx0];
if (i!=0) {
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
idx1 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
}
sdata_x0_0[tid] = tmp1_x.x;
sdata_x1_0[tid] = tmp1_x.y;
sdata_x2_0[tid] = tmp1_x.z;
sdata_x3_0[tid] = tmp1_x.w;
sdata_y0_0[tid] = tmp1_y.x;
sdata_y1_0[tid] = tmp1_y.y;
sdata_y2_0[tid] = tmp1_y.z;
sdata_y3_0[tid] = tmp1_y.w;
__syncthreads();
tmp1_x = x_as_float4[idx1];
tmp1_y = y_as_float4[idx1];
result_y.x = a * sdata_x0_0[tid] + sdata_y0_0[tid];
result_y.y = a * sdata_x1_0[tid] + sdata_y1_0[tid];
result_y.z = a * sdata_x2_0[tid] + sdata_y2_0[tid];
result_y.w = a * sdata_x3_0[tid] + sdata_y3_0[tid];
y_as_float4[idx0] = result_y;
idx0 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
sdata_x0_1[tid] = tmp1_x.x;
sdata_x1_1[tid] = tmp1_x.y;
sdata_x2_1[tid] = tmp1_x.z;
sdata_x3_1[tid] = tmp1_x.w;
sdata_y0_1[tid] = tmp1_y.x;
sdata_y1_1[tid] = tmp1_y.y;
sdata_y2_1[tid] = tmp1_y.z;
sdata_y3_1[tid] = tmp1_y.w;
}
__syncthreads();
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
} | .file "tmpxft_0012ed74_00000000-6_saxpy_float4s_shmem_doublebuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl
.type _Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl, @function
_Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z32saxpy_float4s_shmem_doublebufferPfS_fPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl, .-_Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl
.globl _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.type _Z32saxpy_float4s_shmem_doublebufferPfS_fPl, @function
_Z32saxpy_float4s_shmem_doublebufferPfS_fPl:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32saxpy_float4s_shmem_doublebufferPfS_fPl, .-_Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32saxpy_float4s_shmem_doublebufferPfS_fPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32saxpy_float4s_shmem_doublebufferPfS_fPl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void saxpy_float4s_shmem_doublebuffer ( float* y, float* x, float a, clock_t * timer_vals)
{
volatile __shared__ float sdata_x0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_1 [COMPUTE_THREADS_PER_CTA];
int tid = threadIdx.x ;
unsigned int idx0, idx1;
idx0 = blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
idx1 = COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 result_y;
for (int i=0; i < NUM_ITERS/4; i+=2) {
float4 tmp1_x, tmp1_y;
__syncthreads();
tmp1_x = x_as_float4[idx0];
tmp1_y = y_as_float4[idx0];
if (i!=0) {
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
idx1 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
}
sdata_x0_0[tid] = tmp1_x.x;
sdata_x1_0[tid] = tmp1_x.y;
sdata_x2_0[tid] = tmp1_x.z;
sdata_x3_0[tid] = tmp1_x.w;
sdata_y0_0[tid] = tmp1_y.x;
sdata_y1_0[tid] = tmp1_y.y;
sdata_y2_0[tid] = tmp1_y.z;
sdata_y3_0[tid] = tmp1_y.w;
__syncthreads();
tmp1_x = x_as_float4[idx1];
tmp1_y = y_as_float4[idx1];
result_y.x = a * sdata_x0_0[tid] + sdata_y0_0[tid];
result_y.y = a * sdata_x1_0[tid] + sdata_y1_0[tid];
result_y.z = a * sdata_x2_0[tid] + sdata_y2_0[tid];
result_y.w = a * sdata_x3_0[tid] + sdata_y3_0[tid];
y_as_float4[idx0] = result_y;
idx0 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
sdata_x0_1[tid] = tmp1_x.x;
sdata_x1_1[tid] = tmp1_x.y;
sdata_x2_1[tid] = tmp1_x.z;
sdata_x3_1[tid] = tmp1_x.w;
sdata_y0_1[tid] = tmp1_y.x;
sdata_y1_1[tid] = tmp1_y.y;
sdata_y2_1[tid] = tmp1_y.z;
sdata_y3_1[tid] = tmp1_y.w;
}
__syncthreads();
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_float4s_shmem_doublebuffer ( float* y, float* x, float a, clock_t * timer_vals)
{
volatile __shared__ float sdata_x0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_1 [COMPUTE_THREADS_PER_CTA];
int tid = threadIdx.x ;
unsigned int idx0, idx1;
idx0 = blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
idx1 = COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 result_y;
for (int i=0; i < NUM_ITERS/4; i+=2) {
float4 tmp1_x, tmp1_y;
__syncthreads();
tmp1_x = x_as_float4[idx0];
tmp1_y = y_as_float4[idx0];
if (i!=0) {
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
idx1 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
}
sdata_x0_0[tid] = tmp1_x.x;
sdata_x1_0[tid] = tmp1_x.y;
sdata_x2_0[tid] = tmp1_x.z;
sdata_x3_0[tid] = tmp1_x.w;
sdata_y0_0[tid] = tmp1_y.x;
sdata_y1_0[tid] = tmp1_y.y;
sdata_y2_0[tid] = tmp1_y.z;
sdata_y3_0[tid] = tmp1_y.w;
__syncthreads();
tmp1_x = x_as_float4[idx1];
tmp1_y = y_as_float4[idx1];
result_y.x = a * sdata_x0_0[tid] + sdata_y0_0[tid];
result_y.y = a * sdata_x1_0[tid] + sdata_y1_0[tid];
result_y.z = a * sdata_x2_0[tid] + sdata_y2_0[tid];
result_y.w = a * sdata_x3_0[tid] + sdata_y3_0[tid];
y_as_float4[idx0] = result_y;
idx0 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
sdata_x0_1[tid] = tmp1_x.x;
sdata_x1_1[tid] = tmp1_x.y;
sdata_x2_1[tid] = tmp1_x.z;
sdata_x3_1[tid] = tmp1_x.w;
sdata_y0_1[tid] = tmp1_y.x;
sdata_y1_1[tid] = tmp1_y.y;
sdata_y2_1[tid] = tmp1_y.z;
sdata_y3_1[tid] = tmp1_y.w;
}
__syncthreads();
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_float4s_shmem_doublebuffer ( float* y, float* x, float a, clock_t * timer_vals)
{
volatile __shared__ float sdata_x0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_1 [COMPUTE_THREADS_PER_CTA];
int tid = threadIdx.x ;
unsigned int idx0, idx1;
idx0 = blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
idx1 = COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 result_y;
for (int i=0; i < NUM_ITERS/4; i+=2) {
float4 tmp1_x, tmp1_y;
__syncthreads();
tmp1_x = x_as_float4[idx0];
tmp1_y = y_as_float4[idx0];
if (i!=0) {
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
idx1 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
}
sdata_x0_0[tid] = tmp1_x.x;
sdata_x1_0[tid] = tmp1_x.y;
sdata_x2_0[tid] = tmp1_x.z;
sdata_x3_0[tid] = tmp1_x.w;
sdata_y0_0[tid] = tmp1_y.x;
sdata_y1_0[tid] = tmp1_y.y;
sdata_y2_0[tid] = tmp1_y.z;
sdata_y3_0[tid] = tmp1_y.w;
__syncthreads();
tmp1_x = x_as_float4[idx1];
tmp1_y = y_as_float4[idx1];
result_y.x = a * sdata_x0_0[tid] + sdata_y0_0[tid];
result_y.y = a * sdata_x1_0[tid] + sdata_y1_0[tid];
result_y.z = a * sdata_x2_0[tid] + sdata_y2_0[tid];
result_y.w = a * sdata_x3_0[tid] + sdata_y3_0[tid];
y_as_float4[idx0] = result_y;
idx0 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
sdata_x0_1[tid] = tmp1_x.x;
sdata_x1_1[tid] = tmp1_x.y;
sdata_x2_1[tid] = tmp1_x.z;
sdata_x3_1[tid] = tmp1_x.w;
sdata_y0_1[tid] = tmp1_y.x;
sdata_y1_1[tid] = tmp1_y.y;
sdata_y2_1[tid] = tmp1_y.z;
sdata_y3_1[tid] = tmp1_y.w;
}
__syncthreads();
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.globl _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.p2align 8
.type _Z32saxpy_float4s_shmem_doublebufferPfS_fPl,@function
_Z32saxpy_float4s_shmem_doublebufferPfS_fPl:
v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_mov_b64 s[2:3], src_shared_base
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v11, s15, 7, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_add_nc_u32_e32 v3, 0x1200, v1
v_add_nc_u32_e32 v5, 0x1600, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v9, 0x700, v11
v_cndmask_b32_e32 v13, 0, v1, vcc_lo
v_cndmask_b32_e64 v14, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_dual_cndmask_b32 v17, 0, v3 :: v_dual_add_nc_u32 v2, 0x200, v1
v_cndmask_b32_e64 v18, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_add_nc_u32_e32 v3, 0x1a00, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e64 s0, -1, v2
v_cndmask_b32_e32 v21, 0, v5, vcc_lo
v_cndmask_b32_e64 v22, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_add_nc_u32_e32 v4, 0x600, v1
v_cndmask_b32_e64 v15, 0, v2, s0
v_cndmask_b32_e64 v16, 0, s3, s0
v_dual_cndmask_b32 v25, 0, v3 :: v_dual_add_nc_u32 v2, 0xa00, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, -1, v4
v_cndmask_b32_e64 v26, 0, s3, vcc_lo
v_add_nc_u32_e32 v3, 0x400, v1
v_cndmask_b32_e64 v19, 0, v4, s0
v_cndmask_b32_e64 v20, 0, s3, s0
v_cmp_ne_u32_e64 s0, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v23, 0, v2, s0
v_add_nc_u32_e32 v2, 0x1e00, v1
v_cndmask_b32_e64 v24, 0, s3, s0
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_dual_cndmask_b32 v29, 0, v2 :: v_dual_add_nc_u32 v4, 0xe00, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, -1, v4
v_add_nc_u32_e32 v2, 0x800, v1
v_cndmask_b32_e64 v30, 0, s3, vcc_lo
v_cndmask_b32_e64 v27, 0, v4, s0
v_cndmask_b32_e64 v28, 0, s3, s0
v_cmp_ne_u32_e64 s0, -1, v3
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_add_nc_u32_e32 v4, 0xc00, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v31, 0, v3, s0
v_cndmask_b32_e32 v33, 0, v2, vcc_lo
v_cndmask_b32_e64 v32, 0, s3, s0
v_cmp_ne_u32_e64 s0, -1, v4
v_or_b32_e32 v2, 0x1000, v1
v_cndmask_b32_e64 v34, 0, s3, vcc_lo
v_add_nc_u32_e32 v3, 0x1400, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v35, 0, v4, s0
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_add_nc_u32_e32 v4, 0x1800, v1
v_add_nc_u32_e32 v1, 0x1c00, v1
v_cndmask_b32_e64 v36, 0, s3, s0
v_cmp_ne_u32_e64 s0, -1, v3
v_cndmask_b32_e32 v37, 0, v2, vcc_lo
v_cndmask_b32_e64 v38, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cmp_ne_u32_e64 s1, -1, v1
v_cndmask_b32_e64 v39, 0, v3, s0
v_cndmask_b32_e64 v40, 0, s3, s0
s_mov_b32 s0, -2
v_cndmask_b32_e32 v41, 0, v4, vcc_lo
v_cndmask_b32_e64 v42, 0, s3, vcc_lo
v_cndmask_b32_e64 v43, 0, v1, s1
v_cndmask_b32_e64 v44, 0, s3, s1
s_branch .LBB0_2
.LBB0_1:
v_mov_b32_e32 v10, v12
s_waitcnt vmcnt(1)
flat_store_b32 v[13:14], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[31:32], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[33:34], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[35:36], v8 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt vmcnt(0)
flat_store_b32 v[37:38], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[39:40], v2 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[41:42], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[43:44], v4 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
v_lshlrev_b64 v[5:6], 4, v[9:10]
buffer_gl0_inv
s_add_i32 s0, s0, 2
v_add_nc_u32_e32 v11, 0xe00, v11
s_cmpk_gt_u32 s0, 0x1fd
v_add_co_u32 v1, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b128 v[1:4], v[1:2], off
global_load_b128 v[5:8], v[5:6], off
flat_load_b32 v10, v[13:14] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v47, v[37:38] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v51, v[31:32] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v48, v[39:40] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v52, v[33:34] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v49, v[41:42] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v53, v[35:36] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v50, v[43:44] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(4)
v_dual_fmac_f32 v47, s2, v10 :: v_dual_fmac_f32 v48, s2, v51
s_waitcnt lgkmcnt(0)
v_dual_fmac_f32 v49, s2, v52 :: v_dual_fmac_f32 v50, s2, v53
global_store_b128 v[45:46], v[47:50], off
flat_store_b32 v[15:16], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[19:20], v2 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[23:24], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[27:28], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[17:18], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[21:22], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[25:26], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[29:30], v8 dlc
s_waitcnt_vscnt null, 0x0
s_cbranch_scc1 .LBB0_4
.LBB0_2:
v_lshlrev_b64 v[1:2], 4, v[11:12]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_eq_u32 s0, -2
v_add_co_u32 v3, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v45, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v2, vcc_lo
global_load_b128 v[5:8], v[3:4], off
global_load_b128 v[1:4], v[45:46], off
s_cbranch_scc1 .LBB0_1
flat_load_b32 v53, v[15:16] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v47, v[17:18] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v54, v[19:20] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v48, v[21:22] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v55, v[23:24] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v49, v[25:26] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v56, v[27:28] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v50, v[29:30] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(6)
v_dual_mov_b32 v10, v12 :: v_dual_fmac_f32 v47, s2, v53
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[51:52], 4, v[9:10]
s_waitcnt lgkmcnt(4)
v_dual_fmac_f32 v48, s2, v54 :: v_dual_add_nc_u32 v9, 0xe00, v9
s_waitcnt lgkmcnt(0)
v_dual_fmac_f32 v49, s2, v55 :: v_dual_fmac_f32 v50, s2, v56
v_add_co_u32 v51, vcc_lo, s4, v51
v_add_co_ci_u32_e32 v52, vcc_lo, s5, v52, vcc_lo
global_store_b128 v[51:52], v[47:50], off
s_branch .LBB0_1
.LBB0_4:
v_lshlrev_b32_e32 v6, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v0, 0x200, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_dual_cndmask_b32 v0, 0, v0 :: v_dual_add_nc_u32 v7, 0x1600, v6
v_cndmask_b32_e64 v1, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v7
flat_load_b32 v12, v[0:1] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v7, vcc_lo
v_add_nc_u32_e32 v7, 0xe00, v6
v_add_nc_u32_e32 v2, 0x1200, v6
v_add_nc_u32_e32 v4, 0x600, v6
v_add_nc_u32_e32 v10, 0x1e00, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, -1, v2
v_cmp_ne_u32_e64 s1, -1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, 0, v2, s0
v_cndmask_b32_e64 v3, 0, s7, s0
v_cndmask_b32_e64 v4, 0, v4, s1
v_cndmask_b32_e64 v5, 0, s7, s1
v_cmp_ne_u32_e64 s1, -1, v10
flat_load_b32 v0, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0xa00, v6
flat_load_b32 v13, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 0x1a00, v6
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cndmask_b32_e64 v10, 0, v10, s1
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e64 v11, 0, s7, s1
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v7
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cndmask_b32_e64 v8, 0, s7, vcc_lo
s_waitcnt lgkmcnt(1)
v_fmac_f32_e32 v0, s2, v12
v_cmp_ne_u32_e64 s0, -1, v5
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0, v5, s0
v_cndmask_b32_e64 v6, 0, s7, s0
flat_load_b32 v1, v[1:2] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v14, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v3, v[10:11] glc dlc
s_waitcnt vmcnt(0)
v_mov_b32_e32 v10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[9:10]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_waitcnt lgkmcnt(2)
v_dual_fmac_f32 v1, s2, v13 :: v_dual_fmac_f32 v2, s2, v14
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, s2, v6
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 57
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32saxpy_float4s_shmem_doublebufferPfS_fPl, .Lfunc_end0-_Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32saxpy_float4s_shmem_doublebufferPfS_fPl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 57
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_float4s_shmem_doublebuffer ( float* y, float* x, float a, clock_t * timer_vals)
{
volatile __shared__ float sdata_x0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_0 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_x3_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y0_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y1_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y2_1 [COMPUTE_THREADS_PER_CTA];
volatile __shared__ float sdata_y3_1 [COMPUTE_THREADS_PER_CTA];
int tid = threadIdx.x ;
unsigned int idx0, idx1;
idx0 = blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
idx1 = COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + tid;
float4 * x_as_float4 = (float4 *)x;
float4 * y_as_float4 = (float4 *)y;
float4 result_y;
for (int i=0; i < NUM_ITERS/4; i+=2) {
float4 tmp1_x, tmp1_y;
__syncthreads();
tmp1_x = x_as_float4[idx0];
tmp1_y = y_as_float4[idx0];
if (i!=0) {
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
idx1 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
}
sdata_x0_0[tid] = tmp1_x.x;
sdata_x1_0[tid] = tmp1_x.y;
sdata_x2_0[tid] = tmp1_x.z;
sdata_x3_0[tid] = tmp1_x.w;
sdata_y0_0[tid] = tmp1_y.x;
sdata_y1_0[tid] = tmp1_y.y;
sdata_y2_0[tid] = tmp1_y.z;
sdata_y3_0[tid] = tmp1_y.w;
__syncthreads();
tmp1_x = x_as_float4[idx1];
tmp1_y = y_as_float4[idx1];
result_y.x = a * sdata_x0_0[tid] + sdata_y0_0[tid];
result_y.y = a * sdata_x1_0[tid] + sdata_y1_0[tid];
result_y.z = a * sdata_x2_0[tid] + sdata_y2_0[tid];
result_y.w = a * sdata_x3_0[tid] + sdata_y3_0[tid];
y_as_float4[idx0] = result_y;
idx0 += 2 * COMPUTE_THREADS_PER_CTA * CTA_COUNT ;
sdata_x0_1[tid] = tmp1_x.x;
sdata_x1_1[tid] = tmp1_x.y;
sdata_x2_1[tid] = tmp1_x.z;
sdata_x3_1[tid] = tmp1_x.w;
sdata_y0_1[tid] = tmp1_y.x;
sdata_y1_1[tid] = tmp1_y.y;
sdata_y2_1[tid] = tmp1_y.z;
sdata_y3_1[tid] = tmp1_y.w;
}
__syncthreads();
result_y.x = a * sdata_x0_1[tid] + sdata_y0_1[tid];
result_y.y = a * sdata_x1_1[tid] + sdata_y1_1[tid];
result_y.z = a * sdata_x2_1[tid] + sdata_y2_1[tid];
result_y.w = a * sdata_x3_1[tid] + sdata_y3_1[tid];
y_as_float4[idx1] = result_y;
} | .text
.file "saxpy_float4s_shmem_doublebuffer.hip"
.globl _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl # -- Begin function _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.p2align 4, 0x90
.type _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl,@function
_Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl: # @_Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z32saxpy_float4s_shmem_doublebufferPfS_fPl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl, .Lfunc_end0-_Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32saxpy_float4s_shmem_doublebufferPfS_fPl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32saxpy_float4s_shmem_doublebufferPfS_fPl,@object # @_Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.section .rodata,"a",@progbits
.globl _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.p2align 3, 0x0
_Z32saxpy_float4s_shmem_doublebufferPfS_fPl:
.quad _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.size _Z32saxpy_float4s_shmem_doublebufferPfS_fPl, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32saxpy_float4s_shmem_doublebufferPfS_fPl"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R2, 0xe00 ; /* 0x00000e0000027802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ LEA R17, R17, R0, 0x7 ; /* 0x0000000011117211 */
/* 0x001fc800078e38ff */
/*0070*/ IADD3 R16, R17, 0x700, RZ ; /* 0x0000070011107810 */
/* 0x000fe40007ffe0ff */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0090*/ MOV R18, 0x10 ; /* 0x0000001000127802 */
/* 0x000fca0000000f00 */
/*00a0*/ IMAD.WIDE.U32 R4, R17, R18, c[0x0][0x168] ; /* 0x00005a0011047625 */
/* 0x001fc800078e0012 */
/*00b0*/ IMAD.WIDE.U32 R20, R17, R18, c[0x0][0x160] ; /* 0x0000580011147625 */
/* 0x000fe400078e0012 */
/*00c0*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1d00 */
/*00d0*/ LDG.E.128 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1d00 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, 0xe00, PT ; /* 0x00000e000200780c */
/* 0x000fda0003f05270 */
/*00f0*/ @P0 LDS R12, [R0.X4+0x1000] ; /* 0x00100000000c0984 */
/* 0x000fe20000004800 */
/*0100*/ @P0 IMAD.WIDE.U32 R24, R16.reuse, R18, c[0x0][0x160] ; /* 0x0000580010180625 */
/* 0x040fe200078e0012 */
/*0110*/ @P0 IADD3 R16, R16, 0xe00, RZ ; /* 0x00000e0010100810 */
/* 0x000fe40007ffe0ff */
/*0120*/ @P0 LDS R13, [R0.X4+0x1800] ; /* 0x00180000000d0984 */
/* 0x000e280000004800 */
/*0130*/ @P0 LDS R14, [R0.X4+0x1200] ; /* 0x00120000000e0984 */
/* 0x000fe80000004800 */
/*0140*/ @P0 LDS R15, [R0.X4+0x1a00] ; /* 0x001a0000000f0984 */
/* 0x000e680000004800 */
/*0150*/ @P0 LDS R19, [R0.X4+0x1400] ; /* 0x0014000000130984 */
/* 0x000fe80000004800 */
/*0160*/ @P0 LDS R22, [R0.X4+0x1c00] ; /* 0x001c000000160984 */
/* 0x000f280000004800 */
/*0170*/ @P0 LDS R23, [R0.X4+0x1600] ; /* 0x0016000000170984 */
/* 0x000fe80000004800 */
/*0180*/ @P0 LDS R26, [R0.X4+0x1e00] ; /* 0x001e0000001a0984 */
/* 0x000f620000004800 */
/*0190*/ @P0 FFMA R12, R12, c[0x0][0x170], R13 ; /* 0x00005c000c0c0a23 */
/* 0x001fc4000000000d */
/*01a0*/ @P0 FFMA R13, R14, c[0x0][0x170], R15 ; /* 0x00005c000e0d0a23 */
/* 0x002fe4000000000f */
/*01b0*/ @P0 FFMA R14, R19, c[0x0][0x170], R22 ; /* 0x00005c00130e0a23 */
/* 0x010fe40000000016 */
/*01c0*/ @P0 FFMA R15, R23, c[0x0][0x170], R26 ; /* 0x00005c00170f0a23 */
/* 0x020fe4000000001a */
/*01d0*/ IMAD.WIDE.U32 R26, R16, R18, c[0x0][0x168] ; /* 0x00005a00101a7625 */
/* 0x000fc600078e0012 */
/*01e0*/ @P0 STG.E.128 [R24.64], R12 ; /* 0x0000000c18000986 */
/* 0x000fe2000c101d04 */
/*01f0*/ IMAD.WIDE.U32 R22, R16, R18, c[0x0][0x160] ; /* 0x0000580010167625 */
/* 0x000fc600078e0012 */
/*0200*/ STS [R0.X4], R4 ; /* 0x0000000400007388 */
/* 0x004fe80000004800 */
/*0210*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x000fe80000004800 */
/*0220*/ STS [R0.X4+0x400], R6 ; /* 0x0004000600007388 */
/* 0x000fe80000004800 */
/*0230*/ STS [R0.X4+0x600], R7 ; /* 0x0006000700007388 */
/* 0x0001e80000004800 */
/*0240*/ STS [R0.X4+0x800], R8 ; /* 0x0008000800007388 */
/* 0x008fe80000004800 */
/*0250*/ STS [R0.X4+0xa00], R9 ; /* 0x000a000900007388 */
/* 0x000fe80000004800 */
/*0260*/ STS [R0.X4+0xc00], R10 ; /* 0x000c000a00007388 */
/* 0x000fe80000004800 */
/*0270*/ STS [R0.X4+0xe00], R11 ; /* 0x000e000b00007388 */
/* 0x0003e80000004800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDG.E.128 R4, [R26.64] ; /* 0x000000041a047981 */
/* 0x0010a8000c1e1d00 */
/*02a0*/ LDG.E.128 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x002ee8000c1e1d00 */
/*02b0*/ LDS R12, [R0.X4] ; /* 0x00000000000c7984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS R13, [R0.X4+0x800] ; /* 0x00080000000d7984 */
/* 0x000e680000004800 */
/*02d0*/ LDS R14, [R0.X4+0x200] ; /* 0x00020000000e7984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS R19, [R0.X4+0xa00] ; /* 0x000a000000137984 */
/* 0x000f280000004800 */
/*02f0*/ LDS R25, [R0.X4+0x400] ; /* 0x0004000000197984 */
/* 0x000fe80000004800 */
/*0300*/ LDS R28, [R0.X4+0xc00] ; /* 0x000c0000001c7984 */
/* 0x000f680000004800 */
/*0310*/ LDS R15, [R0.X4+0x600] ; /* 0x00060000000f7984 */
/* 0x000fe80000004800 */
/*0320*/ LDS R24, [R0.X4+0xe00] ; /* 0x000e000000187984 */
/* 0x000e220000004800 */
/*0330*/ FFMA R12, R12, c[0x0][0x170], R13 ; /* 0x00005c000c0c7a23 */
/* 0x002fc4000000000d */
/*0340*/ FFMA R13, R14, c[0x0][0x170], R19 ; /* 0x00005c000e0d7a23 */
/* 0x010fe40000000013 */
/*0350*/ FFMA R14, R25, c[0x0][0x170], R28 ; /* 0x00005c00190e7a23 */
/* 0x020fe2000000001c */
/*0360*/ IADD3 R25, R17, 0xe00, RZ ; /* 0x00000e0011197810 */
/* 0x000fca0007ffe0ff */
/*0370*/ IMAD.WIDE.U32 R26, R25, R18, c[0x0][0x168] ; /* 0x00005a00191a7625 */
/* 0x001fc800078e0012 */
/*0380*/ FFMA R15, R15, c[0x0][0x170], R24 ; /* 0x00005c000f0f7a23 */
/* 0x000fca0000000018 */
/*0390*/ STG.E.128 [R20.64], R12 ; /* 0x0000000c14007986 */
/* 0x000fe2000c101d04 */
/*03a0*/ IMAD.WIDE.U32 R24, R25, R18, c[0x0][0x160] ; /* 0x0000580019187625 */
/* 0x000fc600078e0012 */
/*03b0*/ STS [R0.X4+0x1000], R4 ; /* 0x0010000400007388 */
/* 0x004fe80000004800 */
/*03c0*/ STS [R0.X4+0x1200], R5 ; /* 0x0012000500007388 */
/* 0x000fe80000004800 */
/*03d0*/ STS [R0.X4+0x1400], R6 ; /* 0x0014000600007388 */
/* 0x000fe80000004800 */
/*03e0*/ STS [R0.X4+0x1600], R7 ; /* 0x0016000700007388 */
/* 0x0001e80000004800 */
/*03f0*/ STS [R0.X4+0x1800], R8 ; /* 0x0018000800007388 */
/* 0x008fe80000004800 */
/*0400*/ STS [R0.X4+0x1a00], R9 ; /* 0x001a000900007388 */
/* 0x000fe80000004800 */
/*0410*/ STS [R0.X4+0x1c00], R10 ; /* 0x001c000a00007388 */
/* 0x000fe80000004800 */
/*0420*/ STS [R0.X4+0x1e00], R11 ; /* 0x001e000b00007388 */
/* 0x0003e80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ LDG.E.128 R4, [R26.64] ; /* 0x000000041a047981 */
/* 0x001ea8000c1e1d00 */
/*0450*/ LDG.E.128 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x002ee2000c1e1d00 */
/*0460*/ IADD3 R16, R16, 0xe00, RZ ; /* 0x00000e0010107810 */
/* 0x000fc60007ffe0ff */
/*0470*/ LDS R12, [R0.X4+0x1000] ; /* 0x00100000000c7984 */
/* 0x000fe80000004800 */
/*0480*/ LDS R13, [R0.X4+0x1800] ; /* 0x00180000000d7984 */
/* 0x000e280000004800 */
/*0490*/ LDS R14, [R0.X4+0x1200] ; /* 0x00120000000e7984 */
/* 0x000fe80000004800 */
/*04a0*/ LDS R15, [R0.X4+0x1a00] ; /* 0x001a0000000f7984 */
/* 0x000e680000004800 */
/*04b0*/ LDS R19, [R0.X4+0x1400] ; /* 0x0014000000137984 */
/* 0x000fe80000004800 */
/*04c0*/ LDS R20, [R0.X4+0x1c00] ; /* 0x001c000000147984 */
/* 0x000f280000004800 */
/*04d0*/ LDS R21, [R0.X4+0x1600] ; /* 0x0016000000157984 */
/* 0x000fe80000004800 */
/*04e0*/ LDS R28, [R0.X4+0x1e00] ; /* 0x001e0000001c7984 */
/* 0x000f620000004800 */
/*04f0*/ FFMA R12, R12, c[0x0][0x170], R13 ; /* 0x00005c000c0c7a23 */
/* 0x001fc4000000000d */
/*0500*/ FFMA R13, R14, c[0x0][0x170], R15 ; /* 0x00005c000e0d7a23 */
/* 0x002fe4000000000f */
/*0510*/ FFMA R14, R19, c[0x0][0x170], R20 ; /* 0x00005c00130e7a23 */
/* 0x010fe40000000014 */
/*0520*/ FFMA R15, R21, c[0x0][0x170], R28 ; /* 0x00005c00150f7a23 */
/* 0x020fe4000000001c */
/*0530*/ IMAD.WIDE.U32 R20, R16, R18, c[0x0][0x168] ; /* 0x00005a0010147625 */
/* 0x000fc600078e0012 */
/*0540*/ STG.E.128 [R22.64], R12 ; /* 0x0000000c16007986 */
/* 0x000fe2000c101d04 */
/*0550*/ IMAD.WIDE.U32 R18, R16, R18, c[0x0][0x160] ; /* 0x0000580010127625 */
/* 0x000fc600078e0012 */
/*0560*/ STS [R0.X4], R4 ; /* 0x0000000400007388 */
/* 0x004fe80000004800 */
/*0570*/ STS [R0.X4+0x200], R5 ; /* 0x0002000500007388 */
/* 0x000fe80000004800 */
/*0580*/ STS [R0.X4+0x400], R6 ; /* 0x0004000600007388 */
/* 0x000fe80000004800 */
/*0590*/ STS [R0.X4+0x600], R7 ; /* 0x0006000700007388 */
/* 0x0001e80000004800 */
/*05a0*/ STS [R0.X4+0x800], R8 ; /* 0x0008000800007388 */
/* 0x008fe80000004800 */
/*05b0*/ STS [R0.X4+0xa00], R9 ; /* 0x000a000900007388 */
/* 0x000fe80000004800 */
/*05c0*/ STS [R0.X4+0xc00], R10 ; /* 0x000c000a00007388 */
/* 0x000fe80000004800 */
/*05d0*/ STS [R0.X4+0xe00], R11 ; /* 0x000e000b00007388 */
/* 0x0003e80000004800 */
/*05e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05f0*/ LDG.E.128 R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x001ea8000c1e1d00 */
/*0600*/ LDG.E.128 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x002ee2000c1e1d00 */
/*0610*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc40007ffe0ff */
/*0620*/ IADD3 R2, R2, 0x1c00, RZ ; /* 0x00001c0002027810 */
/* 0x000fe20007ffe0ff */
/*0630*/ LDS R12, [R0.X4] ; /* 0x00000000000c7984 */
/* 0x000fe20000004800 */
/*0640*/ ISETP.GE.U32.AND P0, PT, R3, 0x200, PT ; /* 0x000002000300780c */
/* 0x000fe40003f06070 */
/*0650*/ IADD3 R17, R17, 0x1c00, RZ ; /* 0x00001c0011117810 */
/* 0x000fe20007ffe0ff */
/*0660*/ LDS R13, [R0.X4+0x800] ; /* 0x00080000000d7984 */
/* 0x000e280000004800 */
/*0670*/ LDS R14, [R0.X4+0x200] ; /* 0x00020000000e7984 */
/* 0x000fe80000004800 */
/*0680*/ LDS R15, [R0.X4+0xa00] ; /* 0x000a0000000f7984 */
/* 0x000e680000004800 */
/*0690*/ LDS R22, [R0.X4+0x400] ; /* 0x0004000000167984 */
/* 0x000fe80000004800 */
/*06a0*/ LDS R23, [R0.X4+0xc00] ; /* 0x000c000000177984 */
/* 0x000f280000004800 */
/*06b0*/ LDS R26, [R0.X4+0x600] ; /* 0x00060000001a7984 */
/* 0x000fe80000004800 */
/*06c0*/ LDS R27, [R0.X4+0xe00] ; /* 0x000e0000001b7984 */
/* 0x000f620000004800 */
/*06d0*/ FFMA R12, R12, c[0x0][0x170], R13 ; /* 0x00005c000c0c7a23 */
/* 0x001fc4000000000d */
/*06e0*/ FFMA R13, R14, c[0x0][0x170], R15 ; /* 0x00005c000e0d7a23 */
/* 0x002fe4000000000f */
/*06f0*/ FFMA R14, R22, c[0x0][0x170], R23 ; /* 0x00005c00160e7a23 */
/* 0x010fe40000000017 */
/*0700*/ FFMA R15, R26, c[0x0][0x170], R27 ; /* 0x00005c001a0f7a23 */
/* 0x020fca000000001b */
/*0710*/ STG.E.128 [R24.64], R12 ; /* 0x0000000c18007986 */
/* 0x0001e8000c101d04 */
/*0720*/ STS [R0.X4+0x1000], R4 ; /* 0x0010000400007388 */
/* 0x0041e80000004800 */
/*0730*/ STS [R0.X4+0x1200], R5 ; /* 0x0012000500007388 */
/* 0x0001e80000004800 */
/*0740*/ STS [R0.X4+0x1400], R6 ; /* 0x0014000600007388 */
/* 0x0001e80000004800 */
/*0750*/ STS [R0.X4+0x1600], R7 ; /* 0x0016000700007388 */
/* 0x0001e80000004800 */
/*0760*/ STS [R0.X4+0x1800], R8 ; /* 0x0018000800007388 */
/* 0x0081e80000004800 */
/*0770*/ STS [R0.X4+0x1a00], R9 ; /* 0x001a000900007388 */
/* 0x0001e80000004800 */
/*0780*/ STS [R0.X4+0x1c00], R10 ; /* 0x001c000a00007388 */
/* 0x0001e80000004800 */
/*0790*/ STS [R0.X4+0x1e00], R11 ; /* 0x001e000b00007388 */
/* 0x0001e20000004800 */
/*07a0*/ @!P0 BRA 0x80 ; /* 0xfffff8d000008947 */
/* 0x000fea000383ffff */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ LDS R4, [R0.X4+0x1000] ; /* 0x0010000000047984 */
/* 0x001fe80000004800 */
/*07d0*/ LDS R3, [R0.X4+0x1800] ; /* 0x0018000000037984 */
/* 0x000e280000004800 */
/*07e0*/ LDS R5, [R0.X4+0x1200] ; /* 0x0012000000057984 */
/* 0x000fe80000004800 */
/*07f0*/ LDS R2, [R0.X4+0x1a00] ; /* 0x001a000000027984 */
/* 0x000e680000004800 */
/*0800*/ LDS R6, [R0.X4+0x1400] ; /* 0x0014000000067984 */
/* 0x000fe80000004800 */
/*0810*/ LDS R7, [R0.X4+0x1c00] ; /* 0x001c000000077984 */
/* 0x000ea80000004800 */
/*0820*/ LDS R8, [R0.X4+0x1600] ; /* 0x0016000000087984 */
/* 0x000fe80000004800 */
/*0830*/ LDS R9, [R0.X4+0x1e00] ; /* 0x001e000000097984 */
/* 0x000ee20000004800 */
/*0840*/ FFMA R4, R4, c[0x0][0x170], R3 ; /* 0x00005c0004047a23 */
/* 0x001fc40000000003 */
/*0850*/ FFMA R5, R5, c[0x0][0x170], R2 ; /* 0x00005c0005057a23 */
/* 0x002fe40000000002 */
/*0860*/ FFMA R6, R6, c[0x0][0x170], R7 ; /* 0x00005c0006067a23 */
/* 0x004fe40000000007 */
/*0870*/ FFMA R7, R8, c[0x0][0x170], R9 ; /* 0x00005c0008077a23 */
/* 0x008fca0000000009 */
/*0880*/ STG.E.128 [R18.64], R4 ; /* 0x0000000412007986 */
/* 0x000fe2000c101d04 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.globl _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.p2align 8
.type _Z32saxpy_float4s_shmem_doublebufferPfS_fPl,@function
_Z32saxpy_float4s_shmem_doublebufferPfS_fPl:
v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_mov_b64 s[2:3], src_shared_base
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v11, s15, 7, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_add_nc_u32_e32 v3, 0x1200, v1
v_add_nc_u32_e32 v5, 0x1600, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v9, 0x700, v11
v_cndmask_b32_e32 v13, 0, v1, vcc_lo
v_cndmask_b32_e64 v14, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_dual_cndmask_b32 v17, 0, v3 :: v_dual_add_nc_u32 v2, 0x200, v1
v_cndmask_b32_e64 v18, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_add_nc_u32_e32 v3, 0x1a00, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e64 s0, -1, v2
v_cndmask_b32_e32 v21, 0, v5, vcc_lo
v_cndmask_b32_e64 v22, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_add_nc_u32_e32 v4, 0x600, v1
v_cndmask_b32_e64 v15, 0, v2, s0
v_cndmask_b32_e64 v16, 0, s3, s0
v_dual_cndmask_b32 v25, 0, v3 :: v_dual_add_nc_u32 v2, 0xa00, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, -1, v4
v_cndmask_b32_e64 v26, 0, s3, vcc_lo
v_add_nc_u32_e32 v3, 0x400, v1
v_cndmask_b32_e64 v19, 0, v4, s0
v_cndmask_b32_e64 v20, 0, s3, s0
v_cmp_ne_u32_e64 s0, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v23, 0, v2, s0
v_add_nc_u32_e32 v2, 0x1e00, v1
v_cndmask_b32_e64 v24, 0, s3, s0
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_dual_cndmask_b32 v29, 0, v2 :: v_dual_add_nc_u32 v4, 0xe00, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, -1, v4
v_add_nc_u32_e32 v2, 0x800, v1
v_cndmask_b32_e64 v30, 0, s3, vcc_lo
v_cndmask_b32_e64 v27, 0, v4, s0
v_cndmask_b32_e64 v28, 0, s3, s0
v_cmp_ne_u32_e64 s0, -1, v3
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_add_nc_u32_e32 v4, 0xc00, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v31, 0, v3, s0
v_cndmask_b32_e32 v33, 0, v2, vcc_lo
v_cndmask_b32_e64 v32, 0, s3, s0
v_cmp_ne_u32_e64 s0, -1, v4
v_or_b32_e32 v2, 0x1000, v1
v_cndmask_b32_e64 v34, 0, s3, vcc_lo
v_add_nc_u32_e32 v3, 0x1400, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v35, 0, v4, s0
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_add_nc_u32_e32 v4, 0x1800, v1
v_add_nc_u32_e32 v1, 0x1c00, v1
v_cndmask_b32_e64 v36, 0, s3, s0
v_cmp_ne_u32_e64 s0, -1, v3
v_cndmask_b32_e32 v37, 0, v2, vcc_lo
v_cndmask_b32_e64 v38, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cmp_ne_u32_e64 s1, -1, v1
v_cndmask_b32_e64 v39, 0, v3, s0
v_cndmask_b32_e64 v40, 0, s3, s0
s_mov_b32 s0, -2
v_cndmask_b32_e32 v41, 0, v4, vcc_lo
v_cndmask_b32_e64 v42, 0, s3, vcc_lo
v_cndmask_b32_e64 v43, 0, v1, s1
v_cndmask_b32_e64 v44, 0, s3, s1
s_branch .LBB0_2
.LBB0_1:
v_mov_b32_e32 v10, v12
s_waitcnt vmcnt(1)
flat_store_b32 v[13:14], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[31:32], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[33:34], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[35:36], v8 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt vmcnt(0)
flat_store_b32 v[37:38], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[39:40], v2 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[41:42], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[43:44], v4 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
v_lshlrev_b64 v[5:6], 4, v[9:10]
buffer_gl0_inv
s_add_i32 s0, s0, 2
v_add_nc_u32_e32 v11, 0xe00, v11
s_cmpk_gt_u32 s0, 0x1fd
v_add_co_u32 v1, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b128 v[1:4], v[1:2], off
global_load_b128 v[5:8], v[5:6], off
flat_load_b32 v10, v[13:14] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v47, v[37:38] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v51, v[31:32] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v48, v[39:40] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v52, v[33:34] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v49, v[41:42] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v53, v[35:36] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v50, v[43:44] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(4)
v_dual_fmac_f32 v47, s2, v10 :: v_dual_fmac_f32 v48, s2, v51
s_waitcnt lgkmcnt(0)
v_dual_fmac_f32 v49, s2, v52 :: v_dual_fmac_f32 v50, s2, v53
global_store_b128 v[45:46], v[47:50], off
flat_store_b32 v[15:16], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[19:20], v2 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[23:24], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[27:28], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[17:18], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[21:22], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[25:26], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[29:30], v8 dlc
s_waitcnt_vscnt null, 0x0
s_cbranch_scc1 .LBB0_4
.LBB0_2:
v_lshlrev_b64 v[1:2], 4, v[11:12]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_eq_u32 s0, -2
v_add_co_u32 v3, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v45, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v46, vcc_lo, s5, v2, vcc_lo
global_load_b128 v[5:8], v[3:4], off
global_load_b128 v[1:4], v[45:46], off
s_cbranch_scc1 .LBB0_1
flat_load_b32 v53, v[15:16] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v47, v[17:18] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v54, v[19:20] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v48, v[21:22] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v55, v[23:24] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v49, v[25:26] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v56, v[27:28] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v50, v[29:30] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(6)
v_dual_mov_b32 v10, v12 :: v_dual_fmac_f32 v47, s2, v53
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[51:52], 4, v[9:10]
s_waitcnt lgkmcnt(4)
v_dual_fmac_f32 v48, s2, v54 :: v_dual_add_nc_u32 v9, 0xe00, v9
s_waitcnt lgkmcnt(0)
v_dual_fmac_f32 v49, s2, v55 :: v_dual_fmac_f32 v50, s2, v56
v_add_co_u32 v51, vcc_lo, s4, v51
v_add_co_ci_u32_e32 v52, vcc_lo, s5, v52, vcc_lo
global_store_b128 v[51:52], v[47:50], off
s_branch .LBB0_1
.LBB0_4:
v_lshlrev_b32_e32 v6, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v0, 0x200, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_dual_cndmask_b32 v0, 0, v0 :: v_dual_add_nc_u32 v7, 0x1600, v6
v_cndmask_b32_e64 v1, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v7
flat_load_b32 v12, v[0:1] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v7, vcc_lo
v_add_nc_u32_e32 v7, 0xe00, v6
v_add_nc_u32_e32 v2, 0x1200, v6
v_add_nc_u32_e32 v4, 0x600, v6
v_add_nc_u32_e32 v10, 0x1e00, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, -1, v2
v_cmp_ne_u32_e64 s1, -1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, 0, v2, s0
v_cndmask_b32_e64 v3, 0, s7, s0
v_cndmask_b32_e64 v4, 0, v4, s1
v_cndmask_b32_e64 v5, 0, s7, s1
v_cmp_ne_u32_e64 s1, -1, v10
flat_load_b32 v0, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0xa00, v6
flat_load_b32 v13, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 0x1a00, v6
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cndmask_b32_e64 v10, 0, v10, s1
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e64 v11, 0, s7, s1
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v7
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cndmask_b32_e64 v8, 0, s7, vcc_lo
s_waitcnt lgkmcnt(1)
v_fmac_f32_e32 v0, s2, v12
v_cmp_ne_u32_e64 s0, -1, v5
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0, v5, s0
v_cndmask_b32_e64 v6, 0, s7, s0
flat_load_b32 v1, v[1:2] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v14, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v3, v[10:11] glc dlc
s_waitcnt vmcnt(0)
v_mov_b32_e32 v10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[9:10]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_waitcnt lgkmcnt(2)
v_dual_fmac_f32 v1, s2, v13 :: v_dual_fmac_f32 v2, s2, v14
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, s2, v6
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 57
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32saxpy_float4s_shmem_doublebufferPfS_fPl, .Lfunc_end0-_Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32saxpy_float4s_shmem_doublebufferPfS_fPl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 57
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012ed74_00000000-6_saxpy_float4s_shmem_doublebuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl
.type _Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl, @function
_Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z32saxpy_float4s_shmem_doublebufferPfS_fPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl, .-_Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl
.globl _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.type _Z32saxpy_float4s_shmem_doublebufferPfS_fPl, @function
_Z32saxpy_float4s_shmem_doublebufferPfS_fPl:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z32saxpy_float4s_shmem_doublebufferPfS_fPlPfS_fPl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32saxpy_float4s_shmem_doublebufferPfS_fPl, .-_Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32saxpy_float4s_shmem_doublebufferPfS_fPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32saxpy_float4s_shmem_doublebufferPfS_fPl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy_float4s_shmem_doublebuffer.hip"
.globl _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl # -- Begin function _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.p2align 4, 0x90
.type _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl,@function
_Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl: # @_Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z32saxpy_float4s_shmem_doublebufferPfS_fPl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl, .Lfunc_end0-_Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32saxpy_float4s_shmem_doublebufferPfS_fPl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32saxpy_float4s_shmem_doublebufferPfS_fPl,@object # @_Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.section .rodata,"a",@progbits
.globl _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.p2align 3, 0x0
_Z32saxpy_float4s_shmem_doublebufferPfS_fPl:
.quad _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.size _Z32saxpy_float4s_shmem_doublebufferPfS_fPl, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32saxpy_float4s_shmem_doublebufferPfS_fPl"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__saxpy_float4s_shmem_doublebufferPfS_fPl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32saxpy_float4s_shmem_doublebufferPfS_fPl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
}
__global__ void sgd_with_momentum(float* w, const float* dw, float learning_rate, float momentum, float* v, unsigned int len) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if (tid < len) {
v[tid] = momentum * v[tid] + dw[tid];
w[tid] -= learning_rate * v[tid];
}
} | code for sm_80
Function : _Z17sgd_with_momentumPfPKfffS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FFMA R9, R0, c[0x0][0x174], R5 ; /* 0x00005d0000097a23 */
/* 0x004fca0000000005 */
/*00e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00f0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*0100*/ FFMA R11, -R9, c[0x0][0x170], R0 ; /* 0x00005c00090b7a23 */
/* 0x004fca0000000100 */
/*0110*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
__global__ void sgd_with_momentum(float* w, const float* dw, float learning_rate, float momentum, float* v, unsigned int len) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if (tid < len) {
v[tid] = momentum * v[tid] + dw[tid];
w[tid] -= learning_rate * v[tid];
}
} | .file "tmpxft_001ae999_00000000-6_sgd_with_momentum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j
.type _Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j, @function
_Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17sgd_with_momentumPfPKfffS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j, .-_Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j
.globl _Z17sgd_with_momentumPfPKfffS_j
.type _Z17sgd_with_momentumPfPKfffS_j, @function
_Z17sgd_with_momentumPfPKfffS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17sgd_with_momentumPfPKfffS_j, .-_Z17sgd_with_momentumPfPKfffS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17sgd_with_momentumPfPKfffS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sgd_with_momentumPfPKfffS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
__global__ void sgd_with_momentum(float* w, const float* dw, float learning_rate, float momentum, float* v, unsigned int len) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if (tid < len) {
v[tid] = momentum * v[tid] + dw[tid];
w[tid] -= learning_rate * v[tid];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void sgd_with_momentum(float* w, const float* dw, float learning_rate, float momentum, float* v, unsigned int len) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if (tid < len) {
v[tid] = momentum * v[tid] + dw[tid];
w[tid] -= learning_rate * v[tid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void sgd_with_momentum(float* w, const float* dw, float learning_rate, float momentum, float* v, unsigned int len) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if (tid < len) {
v[tid] = momentum * v[tid] + dw[tid];
w[tid] -= learning_rate * v[tid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17sgd_with_momentumPfPKfffS_j
.globl _Z17sgd_with_momentumPfPKfffS_j
.p2align 8
.type _Z17sgd_with_momentumPfPKfffS_j,@function
_Z17sgd_with_momentumPfPKfffS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s5, v6
global_store_b32 v[2:3], v4, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, -v4, s4, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17sgd_with_momentumPfPKfffS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17sgd_with_momentumPfPKfffS_j, .Lfunc_end0-_Z17sgd_with_momentumPfPKfffS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17sgd_with_momentumPfPKfffS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17sgd_with_momentumPfPKfffS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void sgd_with_momentum(float* w, const float* dw, float learning_rate, float momentum, float* v, unsigned int len) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if (tid < len) {
v[tid] = momentum * v[tid] + dw[tid];
w[tid] -= learning_rate * v[tid];
}
} | .text
.file "sgd_with_momentum.hip"
.globl _Z32__device_stub__sgd_with_momentumPfPKfffS_j # -- Begin function _Z32__device_stub__sgd_with_momentumPfPKfffS_j
.p2align 4, 0x90
.type _Z32__device_stub__sgd_with_momentumPfPKfffS_j,@function
_Z32__device_stub__sgd_with_momentumPfPKfffS_j: # @_Z32__device_stub__sgd_with_momentumPfPKfffS_j
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17sgd_with_momentumPfPKfffS_j, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__sgd_with_momentumPfPKfffS_j, .Lfunc_end0-_Z32__device_stub__sgd_with_momentumPfPKfffS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sgd_with_momentumPfPKfffS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17sgd_with_momentumPfPKfffS_j,@object # @_Z17sgd_with_momentumPfPKfffS_j
.section .rodata,"a",@progbits
.globl _Z17sgd_with_momentumPfPKfffS_j
.p2align 3, 0x0
_Z17sgd_with_momentumPfPKfffS_j:
.quad _Z32__device_stub__sgd_with_momentumPfPKfffS_j
.size _Z17sgd_with_momentumPfPKfffS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17sgd_with_momentumPfPKfffS_j"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__sgd_with_momentumPfPKfffS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17sgd_with_momentumPfPKfffS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17sgd_with_momentumPfPKfffS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FFMA R9, R0, c[0x0][0x174], R5 ; /* 0x00005d0000097a23 */
/* 0x004fca0000000005 */
/*00e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00f0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*0100*/ FFMA R11, -R9, c[0x0][0x170], R0 ; /* 0x00005c00090b7a23 */
/* 0x004fca0000000100 */
/*0110*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17sgd_with_momentumPfPKfffS_j
.globl _Z17sgd_with_momentumPfPKfffS_j
.p2align 8
.type _Z17sgd_with_momentumPfPKfffS_j,@function
_Z17sgd_with_momentumPfPKfffS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s5, v6
global_store_b32 v[2:3], v4, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, -v4, s4, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17sgd_with_momentumPfPKfffS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17sgd_with_momentumPfPKfffS_j, .Lfunc_end0-_Z17sgd_with_momentumPfPKfffS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17sgd_with_momentumPfPKfffS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17sgd_with_momentumPfPKfffS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ae999_00000000-6_sgd_with_momentum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j
.type _Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j, @function
_Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17sgd_with_momentumPfPKfffS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j, .-_Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j
.globl _Z17sgd_with_momentumPfPKfffS_j
.type _Z17sgd_with_momentumPfPKfffS_j, @function
_Z17sgd_with_momentumPfPKfffS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17sgd_with_momentumPfPKfffS_jPfPKfffS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17sgd_with_momentumPfPKfffS_j, .-_Z17sgd_with_momentumPfPKfffS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17sgd_with_momentumPfPKfffS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sgd_with_momentumPfPKfffS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sgd_with_momentum.hip"
.globl _Z32__device_stub__sgd_with_momentumPfPKfffS_j # -- Begin function _Z32__device_stub__sgd_with_momentumPfPKfffS_j
.p2align 4, 0x90
.type _Z32__device_stub__sgd_with_momentumPfPKfffS_j,@function
_Z32__device_stub__sgd_with_momentumPfPKfffS_j: # @_Z32__device_stub__sgd_with_momentumPfPKfffS_j
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17sgd_with_momentumPfPKfffS_j, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__sgd_with_momentumPfPKfffS_j, .Lfunc_end0-_Z32__device_stub__sgd_with_momentumPfPKfffS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sgd_with_momentumPfPKfffS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17sgd_with_momentumPfPKfffS_j,@object # @_Z17sgd_with_momentumPfPKfffS_j
.section .rodata,"a",@progbits
.globl _Z17sgd_with_momentumPfPKfffS_j
.p2align 3, 0x0
_Z17sgd_with_momentumPfPKfffS_j:
.quad _Z32__device_stub__sgd_with_momentumPfPKfffS_j
.size _Z17sgd_with_momentumPfPKfffS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17sgd_with_momentumPfPKfffS_j"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__sgd_with_momentumPfPKfffS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17sgd_with_momentumPfPKfffS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Copyright (c) 2018 John Biddiscombe
//
// Distributed under the Boost Software License, Version 1.0. (See accompanying
// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
#include "cuda_runtime.h"
__global__
void saxpy(int n, float a, float *x, float *y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) y[i] = a * x[i] + y[i];
} | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Copyright (c) 2018 John Biddiscombe
//
// Distributed under the Boost Software License, Version 1.0. (See accompanying
// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
#include "cuda_runtime.h"
__global__
void saxpy(int n, float a, float *x, float *y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) y[i] = a * x[i] + y[i];
} | .file "tmpxft_00088ded_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5saxpyifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Copyright (c) 2018 John Biddiscombe
//
// Distributed under the Boost Software License, Version 1.0. (See accompanying
// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
#include "cuda_runtime.h"
__global__
void saxpy(int n, float a, float *x, float *y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) y[i] = a * x[i] + y[i];
} | // Copyright (c) 2018 John Biddiscombe
//
// Distributed under the Boost Software License, Version 1.0. (See accompanying
// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
#include "hip/hip_runtime.h"
__global__
void saxpy(int n, float a, float *x, float *y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) y[i] = a * x[i] + y[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Copyright (c) 2018 John Biddiscombe
//
// Distributed under the Boost Software License, Version 1.0. (See accompanying
// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
#include "hip/hip_runtime.h"
__global__
void saxpy(int n, float a, float *x, float *y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) y[i] = a * x[i] + y[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Copyright (c) 2018 John Biddiscombe
//
// Distributed under the Boost Software License, Version 1.0. (See accompanying
// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
#include "hip/hip_runtime.h"
__global__
void saxpy(int n, float a, float *x, float *y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) y[i] = a * x[i] + y[i];
} | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00088ded_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5saxpyifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sumMatrixOnGPU(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * nx + ix;
//printf("nx: %d, ny: %d, ix: %d, iy: %d, idx: %d\n", nx, ny, ix, iy, idx);
if (ix<nx && iy<ny)
{
MatC[idx] = MatA[idx] + MatB[idx];
//printf("GPU Add: %f + %f = %f.\n", MatA[idx], MatB[idx], MatC[idx]);
}
} | code for sm_80
Function : _Z14sumMatrixOnGPUPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0007 */
/*00e0*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0007 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sumMatrixOnGPU(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * nx + ix;
//printf("nx: %d, ny: %d, ix: %d, iy: %d, idx: %d\n", nx, ny, ix, iy, idx);
if (ix<nx && iy<ny)
{
MatC[idx] = MatA[idx] + MatB[idx];
//printf("GPU Add: %f + %f = %f.\n", MatA[idx], MatB[idx], MatC[idx]);
}
} | .file "tmpxft_001b0c1d_00000000-6_sumMatrixOnGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii
.type _Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii, @function
_Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sumMatrixOnGPUPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii, .-_Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii
.globl _Z14sumMatrixOnGPUPfS_S_ii
.type _Z14sumMatrixOnGPUPfS_S_ii, @function
_Z14sumMatrixOnGPUPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sumMatrixOnGPUPfS_S_ii, .-_Z14sumMatrixOnGPUPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sumMatrixOnGPUPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sumMatrixOnGPUPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sumMatrixOnGPU(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * nx + ix;
//printf("nx: %d, ny: %d, ix: %d, iy: %d, idx: %d\n", nx, ny, ix, iy, idx);
if (ix<nx && iy<ny)
{
MatC[idx] = MatA[idx] + MatB[idx];
//printf("GPU Add: %f + %f = %f.\n", MatA[idx], MatB[idx], MatC[idx]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumMatrixOnGPU(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * nx + ix;
//printf("nx: %d, ny: %d, ix: %d, iy: %d, idx: %d\n", nx, ny, ix, iy, idx);
if (ix<nx && iy<ny)
{
MatC[idx] = MatA[idx] + MatB[idx];
//printf("GPU Add: %f + %f = %f.\n", MatA[idx], MatB[idx], MatC[idx]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumMatrixOnGPU(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * nx + ix;
//printf("nx: %d, ny: %d, ix: %d, iy: %d, idx: %d\n", nx, ny, ix, iy, idx);
if (ix<nx && iy<ny)
{
MatC[idx] = MatA[idx] + MatB[idx];
//printf("GPU Add: %f + %f = %f.\n", MatA[idx], MatB[idx], MatC[idx]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sumMatrixOnGPUPfS_S_ii
.globl _Z14sumMatrixOnGPUPfS_S_ii
.p2align 8
.type _Z14sumMatrixOnGPUPfS_S_ii,@function
_Z14sumMatrixOnGPUPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sumMatrixOnGPUPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sumMatrixOnGPUPfS_S_ii, .Lfunc_end0-_Z14sumMatrixOnGPUPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sumMatrixOnGPUPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sumMatrixOnGPUPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumMatrixOnGPU(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * nx + ix;
//printf("nx: %d, ny: %d, ix: %d, iy: %d, idx: %d\n", nx, ny, ix, iy, idx);
if (ix<nx && iy<ny)
{
MatC[idx] = MatA[idx] + MatB[idx];
//printf("GPU Add: %f + %f = %f.\n", MatA[idx], MatB[idx], MatC[idx]);
}
} | .text
.file "sumMatrixOnGPU.hip"
.globl _Z29__device_stub__sumMatrixOnGPUPfS_S_ii # -- Begin function _Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.p2align 4, 0x90
.type _Z29__device_stub__sumMatrixOnGPUPfS_S_ii,@function
_Z29__device_stub__sumMatrixOnGPUPfS_S_ii: # @_Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sumMatrixOnGPUPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__sumMatrixOnGPUPfS_S_ii, .Lfunc_end0-_Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sumMatrixOnGPUPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sumMatrixOnGPUPfS_S_ii,@object # @_Z14sumMatrixOnGPUPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z14sumMatrixOnGPUPfS_S_ii
.p2align 3, 0x0
_Z14sumMatrixOnGPUPfS_S_ii:
.quad _Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.size _Z14sumMatrixOnGPUPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sumMatrixOnGPUPfS_S_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sumMatrixOnGPUPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14sumMatrixOnGPUPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0007 */
/*00e0*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0007 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sumMatrixOnGPUPfS_S_ii
.globl _Z14sumMatrixOnGPUPfS_S_ii
.p2align 8
.type _Z14sumMatrixOnGPUPfS_S_ii,@function
_Z14sumMatrixOnGPUPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sumMatrixOnGPUPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sumMatrixOnGPUPfS_S_ii, .Lfunc_end0-_Z14sumMatrixOnGPUPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sumMatrixOnGPUPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sumMatrixOnGPUPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b0c1d_00000000-6_sumMatrixOnGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii
.type _Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii, @function
_Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sumMatrixOnGPUPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii, .-_Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii
.globl _Z14sumMatrixOnGPUPfS_S_ii
.type _Z14sumMatrixOnGPUPfS_S_ii, @function
_Z14sumMatrixOnGPUPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14sumMatrixOnGPUPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sumMatrixOnGPUPfS_S_ii, .-_Z14sumMatrixOnGPUPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sumMatrixOnGPUPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sumMatrixOnGPUPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumMatrixOnGPU.hip"
.globl _Z29__device_stub__sumMatrixOnGPUPfS_S_ii # -- Begin function _Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.p2align 4, 0x90
.type _Z29__device_stub__sumMatrixOnGPUPfS_S_ii,@function
_Z29__device_stub__sumMatrixOnGPUPfS_S_ii: # @_Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sumMatrixOnGPUPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__sumMatrixOnGPUPfS_S_ii, .Lfunc_end0-_Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sumMatrixOnGPUPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sumMatrixOnGPUPfS_S_ii,@object # @_Z14sumMatrixOnGPUPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z14sumMatrixOnGPUPfS_S_ii
.p2align 3, 0x0
_Z14sumMatrixOnGPUPfS_S_ii:
.quad _Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.size _Z14sumMatrixOnGPUPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sumMatrixOnGPUPfS_S_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sumMatrixOnGPUPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sumMatrixOnGPUPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* MSU CUDA Course Examples and Exercises.
*
* Copyright (c) 2011 Dmitry Mikushin
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising
* from the use of this software.
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it freely,
* without any restrictons.
*/
#include <cuda_runtime.h>
#include <malloc.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
// Maximum allowed results difference.
#define EPS 1e-04
// Grid block size (see comment in pattern2d below).
#define BLOCK_LENGTH 32
#define BLOCK_HEIGHT 16
#define IN(i,j) in[i + (j) * nx]
#define OUT(i,j) out[i + (j) * nx]
// GPU device kernel.
__global__ void pattern2d_gpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
// Compute absolute (i,j) indexes for
// the current GPU thread using grid mapping params.
int i = blockIdx.x * BLOCK_LENGTH + threadIdx.x + bx;
int j = blockIdx.y * BLOCK_HEIGHT + threadIdx.y + by;
// Compute one data point - a piece of
// work for the current GPU thread.
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// CPU control implementation.
void pattern2d_cpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
for (int j = by; j < ny - ey; j++)
for (int i = bx; i < nx - ex; i++)
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// Perform some dummy 2D field processing on GPU and CPU,
// and compare results.
int pattern2d(int nx, int ny, float* in, float* out, int pid, int step)
{
if ((nx <= 0) || (ny <= 0)) return -1;
long np = nx * ny;
size_t size = sizeof(float) * np;
// Create GPU data array and copy input data to it.
float* in_gpu;
cudaError_t status = cudaMalloc((void**)&in_gpu, size);
if (status != cudaSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc input memory on GPU by process", pid, status);
return status;
}
status = cudaMemcpy(in_gpu, in, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot copy data from host to gpu by process %d, status = %d\n",
pid, status);
return status;
}
// Create CPU data output array and get
// control result using CPU function.
float* control = (float*)malloc(size);
memset(control, 0, size);
pattern2d_cpu(
1, nx, 1, 1, ny, 1, in, control);
// Configure GPU computational grid:
// nx = nblocks_x * block_length
// ny = nblocks_y * block_height
//
// NOTE: we have degree of freedom in
// selecting how real problem grid maps onto
// computational grid. Usually these params
// are tuned to get optimal performance.
//
// NOTE: chose of grid/block config is
// also limited by device properties:
// - Maximum number of threads per block (512)
// - Maximum sizes of each dimension of a block (512 x 512 x 64)
// - Maximum sizes of each dimension of a grid (65535 x 65535 x 1)
int nblocks_x = (nx - 2) / BLOCK_LENGTH;
int nblocks_y = (ny - 2) / BLOCK_HEIGHT;
// Perform the same processing on GPU,
// returning result to GPU array.
float* out_gpu;
status = cudaMalloc((void**)&out_gpu, size);
if (status != cudaSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc output memory on GPU by process", pid, status);
return status;
}
status = cudaMemset(out_gpu, 0, size);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot erase output memory on GPU by process %d, status = %d\n",
pid, status);
return status;
}
pattern2d_gpu<<<
dim3(nblocks_x, nblocks_y, 1),
dim3(BLOCK_LENGTH, BLOCK_HEIGHT, 1)>>>(
1, nx, 1, 1, ny, 1, in_gpu, out_gpu);
status = cudaGetLastError();
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot execute CUDA kernel by process %d, status = %d\n",
pid, status);
return status;
}
status = cudaThreadSynchronize();
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot synchronize thread by process %d, status = %d\n",
pid, status);
return status;
}
// Copy GPU result from GPU memory to CPU buffer.
status = cudaMemcpy(out, out_gpu, size, cudaMemcpyDeviceToHost);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot copy data from gpu to host by process %d, status = %d\n",
pid, status);
return status;
}
// Don't bother with processing the remainder
// on GPU. Do it on CPU instead.
pattern2d_cpu(
1, nx, 1,
ny - (ny - 2) % BLOCK_HEIGHT - 2, ny, 1,
in, out);
pattern2d_cpu(
nx - (nx - 2) % BLOCK_LENGTH - 2, nx, 1,
1, ny, 1,
in, out);
// Compare results and find the maximum abs difference.
int maxi = 0, maxj = 0;
float maxdiff = fabs(out[0] - control[0]);
float* diffs = (float*)malloc(size);
memset(diffs, 0, size);
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
{
float diff = fabs(
out[i + j * nx] -
control[i + j * nx]);
if (diff > maxdiff)
{
maxdiff = diff;
maxi = i; maxj = j;
}
diffs[i + j * nx] = diff;
}
// Release data arrays.
status = cudaFree(in_gpu);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot free device input memory by process %d, status = %d\n",
pid, status);
return status;
}
free(control);
status = cudaFree(out_gpu);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot free device output memory by process %d, status = %d\n",
pid, status);
return status;
}
free(diffs);
printf("Step %d result abs max diff by process %d = %f @ (%d,%d)\n",
step, pid, maxdiff, maxi, maxj);
return 0;
} | code for sm_80
Function : _Z13pattern2d_gpuiiiiiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ MOV R10, c[0x0][0x164] ; /* 0x00005900000a7a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0080*/ LEA R2, R2, R5, 0x4 ; /* 0x0000000502027211 */
/* 0x001fc400078e20ff */
/*0090*/ LEA R0, R0, R3, 0x5 ; /* 0x0000000300007211 */
/* 0x002fe400078e28ff */
/*00a0*/ IADD3 R3, R2, c[0x0][0x16c], RZ ; /* 0x00005b0002037a10 */
/* 0x000fe40007ffe0ff */
/*00b0*/ IADD3 R4, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc60007ffe0ff */
/*00c0*/ IMAD R5, R3.reuse, R10, -c[0x0][0x164] ; /* 0x8000590003057624 */
/* 0x040fe400078e020a */
/*00d0*/ IMAD R0, R3, c[0x0][0x164], R4 ; /* 0x0000590003007a24 */
/* 0x000fc600078e0204 */
/*00e0*/ IADD3 R6, R4, R5, RZ ; /* 0x0000000504067210 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e0207 */
/*0100*/ IMAD.WIDE R4, R6, R7, c[0x0][0x178] ; /* 0x00005e0006047625 */
/* 0x000fe200078e0207 */
/*0110*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0120*/ LEA R6, R10, R6, 0x1 ; /* 0x000000060a067211 */
/* 0x000fc600078e08ff */
/*0130*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0402097981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe400078e0207 */
/*0150*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f28000c1e1900 */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f62000c1e1900 */
/*0180*/ BSSY B0, 0x2b0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0190*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000000 */
/*01a0*/ FADD R8, R8, R11 ; /* 0x0000000b08087221 */
/* 0x008fe40000000000 */
/*01b0*/ FADD R9, R4, R4 ; /* 0x0000000404097221 */
/* 0x010fc80000000000 */
/*01c0*/ FADD R8, R8, -R9 ; /* 0x8000000908087221 */
/* 0x000fc80000000000 */
/*01d0*/ FFMA R8, R7, 3, R8 ; /* 0x4040000007087823 */
/* 0x020fc80000000008 */
/*01e0*/ FADD R10, |R8|, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fe20000000200 */
/*01f0*/ MUFU.RSQ R3, |R8| ; /* 0x4000000800037308 */
/* 0x0000680000001400 */
/*0200*/ IADD3 R9, R10, -0xd000000, RZ ; /* 0xf30000000a097810 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GT.U32.AND P0, PT, R9, 0x727fffff, PT ; /* 0x727fffff0900780c */
/* 0x000fda0003f04070 */
/*0220*/ @!P0 BRA 0x260 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R7, 0x250 ; /* 0x0000025000077802 */
/* 0x003fe40000000f00 */
/*0240*/ CALL.REL.NOINC 0x2f0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0250*/ BRA 0x2a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0260*/ FMUL.FTZ R5, |R8|, R3 ; /* 0x0000000308057220 */
/* 0x003fe40000410200 */
/*0270*/ FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000410000 */
/*0280*/ FFMA R8, -R5, R5, |R8| ; /* 0x0000000505087223 */
/* 0x000fc80000000508 */
/*0290*/ FFMA R5, R8, R3, R5 ; /* 0x0000000308057223 */
/* 0x000fe40000000005 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*02c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0203 */
/*02d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*0300*/ @!P0 MOV R2, R10 ; /* 0x0000000a00028202 */
/* 0x000fe20000000f00 */
/*0310*/ @!P0 BRA 0x420 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f1e000 */
/*0330*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0340*/ @!P0 BRA 0x420 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1c200 */
/*0360*/ @P0 FADD.FTZ R2, R10, 1 ; /* 0x3f8000000a020421 */
/* 0x000fe20000010000 */
/*0370*/ @P0 BRA 0x420 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0380*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1d200 */
/*0390*/ @P0 FFMA R3, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a030823 */
/* 0x000fc800000000ff */
/*03a0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*03b0*/ @P0 FMUL.FTZ R4, R3, R2 ; /* 0x0000000203040220 */
/* 0x001fe40000410000 */
/*03c0*/ @P0 FMUL.FTZ R6, R2, 0.5 ; /* 0x3f00000002060820 */
/* 0x000fe20000410000 */
/*03d0*/ @!P0 MOV R2, R10 ; /* 0x0000000a00028202 */
/* 0x000fe20000000f00 */
/*03e0*/ @P0 FADD.FTZ R5, -R4, -RZ ; /* 0x800000ff04050221 */
/* 0x000fc80000010100 */
/*03f0*/ @P0 FFMA R5, R4, R5, R3 ; /* 0x0000000504050223 */
/* 0x000fc80000000003 */
/*0400*/ @P0 FFMA R5, R5, R6, R4 ; /* 0x0000000605050223 */
/* 0x000fc80000000004 */
/*0410*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0420*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0430*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x000fe40000000f00 */
/*0440*/ MOV R2, R7 ; /* 0x0000000700027202 */
/* 0x000fc80000000f00 */
/*0450*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffba002007950 */
/* 0x000fea0003c3ffff */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* MSU CUDA Course Examples and Exercises.
*
* Copyright (c) 2011 Dmitry Mikushin
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising
* from the use of this software.
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it freely,
* without any restrictons.
*/
#include <cuda_runtime.h>
#include <malloc.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
// Maximum allowed results difference.
#define EPS 1e-04
// Grid block size (see comment in pattern2d below).
#define BLOCK_LENGTH 32
#define BLOCK_HEIGHT 16
#define IN(i,j) in[i + (j) * nx]
#define OUT(i,j) out[i + (j) * nx]
// GPU device kernel.
__global__ void pattern2d_gpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
// Compute absolute (i,j) indexes for
// the current GPU thread using grid mapping params.
int i = blockIdx.x * BLOCK_LENGTH + threadIdx.x + bx;
int j = blockIdx.y * BLOCK_HEIGHT + threadIdx.y + by;
// Compute one data point - a piece of
// work for the current GPU thread.
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// CPU control implementation.
void pattern2d_cpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
for (int j = by; j < ny - ey; j++)
for (int i = bx; i < nx - ex; i++)
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// Perform some dummy 2D field processing on GPU and CPU,
// and compare results.
int pattern2d(int nx, int ny, float* in, float* out, int pid, int step)
{
if ((nx <= 0) || (ny <= 0)) return -1;
long np = nx * ny;
size_t size = sizeof(float) * np;
// Create GPU data array and copy input data to it.
float* in_gpu;
cudaError_t status = cudaMalloc((void**)&in_gpu, size);
if (status != cudaSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc input memory on GPU by process", pid, status);
return status;
}
status = cudaMemcpy(in_gpu, in, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot copy data from host to gpu by process %d, status = %d\n",
pid, status);
return status;
}
// Create CPU data output array and get
// control result using CPU function.
float* control = (float*)malloc(size);
memset(control, 0, size);
pattern2d_cpu(
1, nx, 1, 1, ny, 1, in, control);
// Configure GPU computational grid:
// nx = nblocks_x * block_length
// ny = nblocks_y * block_height
//
// NOTE: we have degree of freedom in
// selecting how real problem grid maps onto
// computational grid. Usually these params
// are tuned to get optimal performance.
//
// NOTE: chose of grid/block config is
// also limited by device properties:
// - Maximum number of threads per block (512)
// - Maximum sizes of each dimension of a block (512 x 512 x 64)
// - Maximum sizes of each dimension of a grid (65535 x 65535 x 1)
int nblocks_x = (nx - 2) / BLOCK_LENGTH;
int nblocks_y = (ny - 2) / BLOCK_HEIGHT;
// Perform the same processing on GPU,
// returning result to GPU array.
float* out_gpu;
status = cudaMalloc((void**)&out_gpu, size);
if (status != cudaSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc output memory on GPU by process", pid, status);
return status;
}
status = cudaMemset(out_gpu, 0, size);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot erase output memory on GPU by process %d, status = %d\n",
pid, status);
return status;
}
pattern2d_gpu<<<
dim3(nblocks_x, nblocks_y, 1),
dim3(BLOCK_LENGTH, BLOCK_HEIGHT, 1)>>>(
1, nx, 1, 1, ny, 1, in_gpu, out_gpu);
status = cudaGetLastError();
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot execute CUDA kernel by process %d, status = %d\n",
pid, status);
return status;
}
status = cudaThreadSynchronize();
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot synchronize thread by process %d, status = %d\n",
pid, status);
return status;
}
// Copy GPU result from GPU memory to CPU buffer.
status = cudaMemcpy(out, out_gpu, size, cudaMemcpyDeviceToHost);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot copy data from gpu to host by process %d, status = %d\n",
pid, status);
return status;
}
// Don't bother with processing the remainder
// on GPU. Do it on CPU instead.
pattern2d_cpu(
1, nx, 1,
ny - (ny - 2) % BLOCK_HEIGHT - 2, ny, 1,
in, out);
pattern2d_cpu(
nx - (nx - 2) % BLOCK_LENGTH - 2, nx, 1,
1, ny, 1,
in, out);
// Compare results and find the maximum abs difference.
int maxi = 0, maxj = 0;
float maxdiff = fabs(out[0] - control[0]);
float* diffs = (float*)malloc(size);
memset(diffs, 0, size);
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
{
float diff = fabs(
out[i + j * nx] -
control[i + j * nx]);
if (diff > maxdiff)
{
maxdiff = diff;
maxi = i; maxj = j;
}
diffs[i + j * nx] = diff;
}
// Release data arrays.
status = cudaFree(in_gpu);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot free device input memory by process %d, status = %d\n",
pid, status);
return status;
}
free(control);
status = cudaFree(out_gpu);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot free device output memory by process %d, status = %d\n",
pid, status);
return status;
}
free(diffs);
printf("Step %d result abs max diff by process %d = %f @ (%d,%d)\n",
step, pid, maxdiff, maxi, maxj);
return 0;
} | .file "tmpxft_000a59a6_00000000-6_pattern2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13pattern2d_cpuiiiiiiPfS_
.type _Z13pattern2d_cpuiiiiiiPfS_, @function
_Z13pattern2d_cpuiiiiiiPfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %edi, %ebp
movl %ecx, %ebx
movq 56(%rsp), %rcx
movq 64(%rsp), %rdi
subl %r9d, %r8d
cmpl %r8d, %ebx
jge .L3
movl %esi, %r12d
movl %ebx, %r11d
imull %esi, %r11d
movl %esi, %r13d
subl %edx, %r13d
movslq %ebp, %r14
movl %r13d, %eax
subl %ebp, %eax
addq %r14, %rax
movq %rax, -8(%rsp)
leal (%rsi,%rsi), %r15d
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
jmp .L5
.L7:
movl %r11d, %r10d
subl %r12d, %r10d
movslq %r11d, %r9
leaq (%r9,%r14), %rax
salq $2, %rax
movq -8(%rsp), %rsi
addq %r9, %rsi
salq $2, %rsi
negq %r9
salq $2, %r9
movslq %r10d, %rdx
leaq (%r9,%rdx,4), %rdx
addq %rcx, %rdx
addl %r15d, %r10d
movslq %r10d, %r10
leaq (%r9,%r10,4), %r9
addq %rcx, %r9
.L6:
movss (%rcx,%rax), %xmm0
addss -4(%rcx,%rax), %xmm0
addss 4(%rcx,%rax), %xmm0
movss (%rdx,%rax), %xmm1
addss %xmm1, %xmm1
subss %xmm1, %xmm0
movaps %xmm3, %xmm1
mulss (%r9,%rax), %xmm1
addss %xmm1, %xmm0
andps %xmm2, %xmm0
sqrtss %xmm0, %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L6
.L8:
addl $1, %ebx
addl %r12d, %r11d
cmpl %r8d, %ebx
je .L3
.L5:
cmpl %r13d, %ebp
jl .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13pattern2d_cpuiiiiiiPfS_, .-_Z13pattern2d_cpuiiiiiiPfS_
.globl _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
.type _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_, @function
_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 208(%rsp), %rax
movq %rax, 16(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13pattern2d_gpuiiiiiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_, .-_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
.globl _Z13pattern2d_gpuiiiiiiPfS_
.type _Z13pattern2d_gpuiiiiiiPfS_, @function
_Z13pattern2d_gpuiiiiiiPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13pattern2d_gpuiiiiiiPfS_, .-_Z13pattern2d_gpuiiiiiiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Cannot malloc input memory on GPU by process"
.align 8
.LC3:
.string "%s %d, status = %d\nInsufficient GPU memory?\n"
.align 8
.LC4:
.string "Cannot copy data from host to gpu by process %d, status = %d\n"
.align 8
.LC5:
.string "Cannot malloc output memory on GPU by process"
.align 8
.LC6:
.string "Cannot erase output memory on GPU by process %d, status = %d\n"
.align 8
.LC7:
.string "Cannot execute CUDA kernel by process %d, status = %d\n"
.align 8
.LC8:
.string "Cannot synchronize thread by process %d, status = %d\n"
.align 8
.LC9:
.string "Cannot copy data from gpu to host by process %d, status = %d\n"
.align 8
.LC10:
.string "Cannot free device input memory by process %d, status = %d\n"
.align 8
.LC11:
.string "Cannot free device output memory by process %d, status = %d\n"
.align 8
.LC12:
.string "Step %d result abs max diff by process %d = %f @ (%d,%d)\n"
.text
.globl _Z9pattern2diiPfS_ii
.type _Z9pattern2diiPfS_ii, @function
_Z9pattern2diiPfS_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rcx, 8(%rsp)
movl %r9d, 24(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
testl %edi, %edi
jle .L37
movl %edi, %ebx
movl %esi, %r12d
movq %rdx, %r13
movl %r8d, %r14d
testl %esi, %esi
jle .L37
movl %edi, %ebp
imull %esi, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L42
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
pushq %r15
.cfi_def_cfa_offset 152
pushq %r13
.cfi_def_cfa_offset 160
movl $1, %r9d
movl %r12d, %r8d
movl $1, %ecx
movl $1, %edx
movl %ebx, %esi
movl $1, %edi
call _Z13pattern2d_cpuiiiiiiPfS_
addq $16, %rsp
.cfi_def_cfa_offset 144
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L43
movq %rbp, %rdx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L44
movl $32, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
leal 29(%rbx), %eax
movl %ebx, %ecx
subl $2, %ecx
movl %ecx, 16(%rsp)
cmovns %ecx, %eax
sarl $5, %eax
movl %eax, 48(%rsp)
leal 13(%r12), %eax
movl %r12d, %esi
subl $2, %esi
movl %esi, 28(%rsp)
cmovns %esi, %eax
sarl $4, %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L25:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L46
call cudaThreadSynchronize@PLT
testl %eax, %eax
jne .L47
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl 28(%rsp), %eax
movl %eax, %edx
sarl $31, %edx
shrl $28, %edx
addl %edx, %eax
andl $15, %eax
subl %edx, %eax
movl %r12d, %ecx
subl %eax, %ecx
subl $2, %ecx
pushq 8(%rsp)
.cfi_def_cfa_offset 152
pushq %r13
.cfi_def_cfa_offset 160
movl $1, %r9d
movl %r12d, %r8d
movl $1, %edx
movl %ebx, %esi
movl $1, %edi
call _Z13pattern2d_cpuiiiiiiPfS_
movl 32(%rsp), %eax
movl %eax, %edx
sarl $31, %edx
shrl $27, %edx
addl %edx, %eax
andl $31, %eax
subl %edx, %eax
movl %ebx, %edi
subl %eax, %edi
subl $2, %edi
pushq 24(%rsp)
.cfi_def_cfa_offset 168
pushq %r13
.cfi_def_cfa_offset 176
movl $1, %r9d
movl %r12d, %r8d
movl $1, %ecx
movl $1, %edx
movl %ebx, %esi
call _Z13pattern2d_cpuiiiiiiPfS_
movq 40(%rsp), %r13
movss 0(%r13), %xmm0
subss (%r15), %xmm0
andps .LC1(%rip), %xmm0
movss %xmm0, 40(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 144
movq %rbp, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %rax, %rbp
movq %rax, %rdi
call __memset_chk@PLT
movslq %ebx, %r8
salq $2, %r8
movq %rbp, %rdi
movq %r13, %rdx
movq %r15, %rsi
movl $0, %ecx
movl $0, %r13d
movl $0, %ebp
movss .LC1(%rip), %xmm1
.L29:
movl $0, %eax
.L32:
movss (%rdx,%rax,4), %xmm0
subss (%rsi,%rax,4), %xmm0
andps %xmm1, %xmm0
movss 8(%rsp), %xmm2
comiss %xmm2, %xmm0
cmova %eax, %ebp
movaps %xmm0, %xmm3
maxss %xmm2, %xmm3
movss %xmm3, 8(%rsp)
cmova %ecx, %r13d
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpl %eax, %ebx
jg .L32
addl $1, %ecx
addq %r8, %rdi
addq %r8, %rdx
addq %r8, %rsi
cmpl %ecx, %r12d
jg .L29
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L49
movq %r15, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L50
movq 16(%rsp), %rdi
call free@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
movl %r13d, %r9d
movl %ebp, %r8d
movl %r14d, %ecx
movl 24(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L19
.L41:
movl %eax, %ebx
movl %eax, %r9d
movl %r14d, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl %ebx, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L43:
movl %eax, %ebx
movl %eax, %r9d
movl %r14d, %r8d
leaq .LC5(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L44:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L45:
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
movl $1, %r9d
movl %r12d, %r8d
movl $1, %ecx
movl $1, %edx
movl %ebx, %esi
movl $1, %edi
call _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L46:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L47:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L48:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L49:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L50:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L37:
movl $-1, %ebx
jmp .L19
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9pattern2diiPfS_ii, .-_Z9pattern2diiPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC13:
.string "_Z13pattern2d_gpuiiiiiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z13pattern2d_gpuiiiiiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* MSU CUDA Course Examples and Exercises.
*
* Copyright (c) 2011 Dmitry Mikushin
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising
* from the use of this software.
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it freely,
* without any restrictons.
*/
#include <cuda_runtime.h>
#include <malloc.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
// Maximum allowed results difference.
#define EPS 1e-04
// Grid block size (see comment in pattern2d below).
#define BLOCK_LENGTH 32
#define BLOCK_HEIGHT 16
#define IN(i,j) in[i + (j) * nx]
#define OUT(i,j) out[i + (j) * nx]
// GPU device kernel.
__global__ void pattern2d_gpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
// Compute absolute (i,j) indexes for
// the current GPU thread using grid mapping params.
int i = blockIdx.x * BLOCK_LENGTH + threadIdx.x + bx;
int j = blockIdx.y * BLOCK_HEIGHT + threadIdx.y + by;
// Compute one data point - a piece of
// work for the current GPU thread.
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// CPU control implementation.
void pattern2d_cpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
for (int j = by; j < ny - ey; j++)
for (int i = bx; i < nx - ex; i++)
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// Perform some dummy 2D field processing on GPU and CPU,
// and compare results.
int pattern2d(int nx, int ny, float* in, float* out, int pid, int step)
{
if ((nx <= 0) || (ny <= 0)) return -1;
long np = nx * ny;
size_t size = sizeof(float) * np;
// Create GPU data array and copy input data to it.
float* in_gpu;
cudaError_t status = cudaMalloc((void**)&in_gpu, size);
if (status != cudaSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc input memory on GPU by process", pid, status);
return status;
}
status = cudaMemcpy(in_gpu, in, size, cudaMemcpyHostToDevice);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot copy data from host to gpu by process %d, status = %d\n",
pid, status);
return status;
}
// Create CPU data output array and get
// control result using CPU function.
float* control = (float*)malloc(size);
memset(control, 0, size);
pattern2d_cpu(
1, nx, 1, 1, ny, 1, in, control);
// Configure GPU computational grid:
// nx = nblocks_x * block_length
// ny = nblocks_y * block_height
//
// NOTE: we have degree of freedom in
// selecting how real problem grid maps onto
// computational grid. Usually these params
// are tuned to get optimal performance.
//
// NOTE: chose of grid/block config is
// also limited by device properties:
// - Maximum number of threads per block (512)
// - Maximum sizes of each dimension of a block (512 x 512 x 64)
// - Maximum sizes of each dimension of a grid (65535 x 65535 x 1)
int nblocks_x = (nx - 2) / BLOCK_LENGTH;
int nblocks_y = (ny - 2) / BLOCK_HEIGHT;
// Perform the same processing on GPU,
// returning result to GPU array.
float* out_gpu;
status = cudaMalloc((void**)&out_gpu, size);
if (status != cudaSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc output memory on GPU by process", pid, status);
return status;
}
status = cudaMemset(out_gpu, 0, size);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot erase output memory on GPU by process %d, status = %d\n",
pid, status);
return status;
}
pattern2d_gpu<<<
dim3(nblocks_x, nblocks_y, 1),
dim3(BLOCK_LENGTH, BLOCK_HEIGHT, 1)>>>(
1, nx, 1, 1, ny, 1, in_gpu, out_gpu);
status = cudaGetLastError();
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot execute CUDA kernel by process %d, status = %d\n",
pid, status);
return status;
}
status = cudaThreadSynchronize();
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot synchronize thread by process %d, status = %d\n",
pid, status);
return status;
}
// Copy GPU result from GPU memory to CPU buffer.
status = cudaMemcpy(out, out_gpu, size, cudaMemcpyDeviceToHost);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot copy data from gpu to host by process %d, status = %d\n",
pid, status);
return status;
}
// Don't bother with processing the remainder
// on GPU. Do it on CPU instead.
pattern2d_cpu(
1, nx, 1,
ny - (ny - 2) % BLOCK_HEIGHT - 2, ny, 1,
in, out);
pattern2d_cpu(
nx - (nx - 2) % BLOCK_LENGTH - 2, nx, 1,
1, ny, 1,
in, out);
// Compare results and find the maximum abs difference.
int maxi = 0, maxj = 0;
float maxdiff = fabs(out[0] - control[0]);
float* diffs = (float*)malloc(size);
memset(diffs, 0, size);
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
{
float diff = fabs(
out[i + j * nx] -
control[i + j * nx]);
if (diff > maxdiff)
{
maxdiff = diff;
maxi = i; maxj = j;
}
diffs[i + j * nx] = diff;
}
// Release data arrays.
status = cudaFree(in_gpu);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot free device input memory by process %d, status = %d\n",
pid, status);
return status;
}
free(control);
status = cudaFree(out_gpu);
if (status != cudaSuccess)
{
fprintf(stderr, "Cannot free device output memory by process %d, status = %d\n",
pid, status);
return status;
}
free(diffs);
printf("Step %d result abs max diff by process %d = %f @ (%d,%d)\n",
step, pid, maxdiff, maxi, maxj);
return 0;
} | /*
* MSU CUDA Course Examples and Exercises.
*
* Copyright (c) 2011 Dmitry Mikushin
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising
* from the use of this software.
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it freely,
* without any restrictons.
*/
#include <hip/hip_runtime.h>
#include <malloc.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
// Maximum allowed results difference.
#define EPS 1e-04
// Grid block size (see comment in pattern2d below).
#define BLOCK_LENGTH 32
#define BLOCK_HEIGHT 16
#define IN(i,j) in[i + (j) * nx]
#define OUT(i,j) out[i + (j) * nx]
// GPU device kernel.
__global__ void pattern2d_gpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
// Compute absolute (i,j) indexes for
// the current GPU thread using grid mapping params.
int i = blockIdx.x * BLOCK_LENGTH + threadIdx.x + bx;
int j = blockIdx.y * BLOCK_HEIGHT + threadIdx.y + by;
// Compute one data point - a piece of
// work for the current GPU thread.
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// CPU control implementation.
void pattern2d_cpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
for (int j = by; j < ny - ey; j++)
for (int i = bx; i < nx - ex; i++)
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// Perform some dummy 2D field processing on GPU and CPU,
// and compare results.
int pattern2d(int nx, int ny, float* in, float* out, int pid, int step)
{
if ((nx <= 0) || (ny <= 0)) return -1;
long np = nx * ny;
size_t size = sizeof(float) * np;
// Create GPU data array and copy input data to it.
float* in_gpu;
hipError_t status = hipMalloc((void**)&in_gpu, size);
if (status != hipSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc input memory on GPU by process", pid, status);
return status;
}
status = hipMemcpy(in_gpu, in, size, hipMemcpyHostToDevice);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot copy data from host to gpu by process %d, status = %d\n",
pid, status);
return status;
}
// Create CPU data output array and get
// control result using CPU function.
float* control = (float*)malloc(size);
memset(control, 0, size);
pattern2d_cpu(
1, nx, 1, 1, ny, 1, in, control);
// Configure GPU computational grid:
// nx = nblocks_x * block_length
// ny = nblocks_y * block_height
//
// NOTE: we have degree of freedom in
// selecting how real problem grid maps onto
// computational grid. Usually these params
// are tuned to get optimal performance.
//
// NOTE: chose of grid/block config is
// also limited by device properties:
// - Maximum number of threads per block (512)
// - Maximum sizes of each dimension of a block (512 x 512 x 64)
// - Maximum sizes of each dimension of a grid (65535 x 65535 x 1)
int nblocks_x = (nx - 2) / BLOCK_LENGTH;
int nblocks_y = (ny - 2) / BLOCK_HEIGHT;
// Perform the same processing on GPU,
// returning result to GPU array.
float* out_gpu;
status = hipMalloc((void**)&out_gpu, size);
if (status != hipSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc output memory on GPU by process", pid, status);
return status;
}
status = hipMemset(out_gpu, 0, size);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot erase output memory on GPU by process %d, status = %d\n",
pid, status);
return status;
}
pattern2d_gpu<<<
dim3(nblocks_x, nblocks_y, 1),
dim3(BLOCK_LENGTH, BLOCK_HEIGHT, 1)>>>(
1, nx, 1, 1, ny, 1, in_gpu, out_gpu);
status = hipGetLastError();
if (status != hipSuccess)
{
fprintf(stderr, "Cannot execute CUDA kernel by process %d, status = %d\n",
pid, status);
return status;
}
status = hipDeviceSynchronize();
if (status != hipSuccess)
{
fprintf(stderr, "Cannot synchronize thread by process %d, status = %d\n",
pid, status);
return status;
}
// Copy GPU result from GPU memory to CPU buffer.
status = hipMemcpy(out, out_gpu, size, hipMemcpyDeviceToHost);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot copy data from gpu to host by process %d, status = %d\n",
pid, status);
return status;
}
// Don't bother with processing the remainder
// on GPU. Do it on CPU instead.
pattern2d_cpu(
1, nx, 1,
ny - (ny - 2) % BLOCK_HEIGHT - 2, ny, 1,
in, out);
pattern2d_cpu(
nx - (nx - 2) % BLOCK_LENGTH - 2, nx, 1,
1, ny, 1,
in, out);
// Compare results and find the maximum abs difference.
int maxi = 0, maxj = 0;
float maxdiff = fabs(out[0] - control[0]);
float* diffs = (float*)malloc(size);
memset(diffs, 0, size);
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
{
float diff = fabs(
out[i + j * nx] -
control[i + j * nx]);
if (diff > maxdiff)
{
maxdiff = diff;
maxi = i; maxj = j;
}
diffs[i + j * nx] = diff;
}
// Release data arrays.
status = hipFree(in_gpu);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot free device input memory by process %d, status = %d\n",
pid, status);
return status;
}
free(control);
status = hipFree(out_gpu);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot free device output memory by process %d, status = %d\n",
pid, status);
return status;
}
free(diffs);
printf("Step %d result abs max diff by process %d = %f @ (%d,%d)\n",
step, pid, maxdiff, maxi, maxj);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* MSU CUDA Course Examples and Exercises.
*
* Copyright (c) 2011 Dmitry Mikushin
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising
* from the use of this software.
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it freely,
* without any restrictons.
*/
#include <hip/hip_runtime.h>
#include <malloc.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
// Maximum allowed results difference.
#define EPS 1e-04
// Grid block size (see comment in pattern2d below).
#define BLOCK_LENGTH 32
#define BLOCK_HEIGHT 16
#define IN(i,j) in[i + (j) * nx]
#define OUT(i,j) out[i + (j) * nx]
// GPU device kernel.
__global__ void pattern2d_gpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
// Compute absolute (i,j) indexes for
// the current GPU thread using grid mapping params.
int i = blockIdx.x * BLOCK_LENGTH + threadIdx.x + bx;
int j = blockIdx.y * BLOCK_HEIGHT + threadIdx.y + by;
// Compute one data point - a piece of
// work for the current GPU thread.
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// CPU control implementation.
void pattern2d_cpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
for (int j = by; j < ny - ey; j++)
for (int i = bx; i < nx - ex; i++)
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// Perform some dummy 2D field processing on GPU and CPU,
// and compare results.
int pattern2d(int nx, int ny, float* in, float* out, int pid, int step)
{
if ((nx <= 0) || (ny <= 0)) return -1;
long np = nx * ny;
size_t size = sizeof(float) * np;
// Create GPU data array and copy input data to it.
float* in_gpu;
hipError_t status = hipMalloc((void**)&in_gpu, size);
if (status != hipSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc input memory on GPU by process", pid, status);
return status;
}
status = hipMemcpy(in_gpu, in, size, hipMemcpyHostToDevice);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot copy data from host to gpu by process %d, status = %d\n",
pid, status);
return status;
}
// Create CPU data output array and get
// control result using CPU function.
float* control = (float*)malloc(size);
memset(control, 0, size);
pattern2d_cpu(
1, nx, 1, 1, ny, 1, in, control);
// Configure GPU computational grid:
// nx = nblocks_x * block_length
// ny = nblocks_y * block_height
//
// NOTE: we have degree of freedom in
// selecting how real problem grid maps onto
// computational grid. Usually these params
// are tuned to get optimal performance.
//
// NOTE: chose of grid/block config is
// also limited by device properties:
// - Maximum number of threads per block (512)
// - Maximum sizes of each dimension of a block (512 x 512 x 64)
// - Maximum sizes of each dimension of a grid (65535 x 65535 x 1)
int nblocks_x = (nx - 2) / BLOCK_LENGTH;
int nblocks_y = (ny - 2) / BLOCK_HEIGHT;
// Perform the same processing on GPU,
// returning result to GPU array.
float* out_gpu;
status = hipMalloc((void**)&out_gpu, size);
if (status != hipSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc output memory on GPU by process", pid, status);
return status;
}
status = hipMemset(out_gpu, 0, size);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot erase output memory on GPU by process %d, status = %d\n",
pid, status);
return status;
}
pattern2d_gpu<<<
dim3(nblocks_x, nblocks_y, 1),
dim3(BLOCK_LENGTH, BLOCK_HEIGHT, 1)>>>(
1, nx, 1, 1, ny, 1, in_gpu, out_gpu);
status = hipGetLastError();
if (status != hipSuccess)
{
fprintf(stderr, "Cannot execute CUDA kernel by process %d, status = %d\n",
pid, status);
return status;
}
status = hipDeviceSynchronize();
if (status != hipSuccess)
{
fprintf(stderr, "Cannot synchronize thread by process %d, status = %d\n",
pid, status);
return status;
}
// Copy GPU result from GPU memory to CPU buffer.
status = hipMemcpy(out, out_gpu, size, hipMemcpyDeviceToHost);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot copy data from gpu to host by process %d, status = %d\n",
pid, status);
return status;
}
// Don't bother with processing the remainder
// on GPU. Do it on CPU instead.
pattern2d_cpu(
1, nx, 1,
ny - (ny - 2) % BLOCK_HEIGHT - 2, ny, 1,
in, out);
pattern2d_cpu(
nx - (nx - 2) % BLOCK_LENGTH - 2, nx, 1,
1, ny, 1,
in, out);
// Compare results and find the maximum abs difference.
int maxi = 0, maxj = 0;
float maxdiff = fabs(out[0] - control[0]);
float* diffs = (float*)malloc(size);
memset(diffs, 0, size);
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
{
float diff = fabs(
out[i + j * nx] -
control[i + j * nx]);
if (diff > maxdiff)
{
maxdiff = diff;
maxi = i; maxj = j;
}
diffs[i + j * nx] = diff;
}
// Release data arrays.
status = hipFree(in_gpu);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot free device input memory by process %d, status = %d\n",
pid, status);
return status;
}
free(control);
status = hipFree(out_gpu);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot free device output memory by process %d, status = %d\n",
pid, status);
return status;
}
free(diffs);
printf("Step %d result abs max diff by process %d = %f @ (%d,%d)\n",
step, pid, maxdiff, maxi, maxj);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13pattern2d_gpuiiiiiiPfS_
.globl _Z13pattern2d_gpuiiiiiiPfS_
.p2align 8
.type _Z13pattern2d_gpuiiiiiiPfS_,@function
_Z13pattern2d_gpuiiiiiiPfS_:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0xc
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s3, s14, 5
s_lshl_b32 s6, s15, 4
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, s4, s3, v1
v_add3_u32 v3, s2, s6, v2
s_load_b128 s[0:3], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, v3, s5, v[0:1]
v_add_nc_u32_e32 v2, -1, v3
v_add_nc_u32_e32 v5, -1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[3:4], null, v2, s5, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v7, 1, v1
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v9, s5, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s0, v0
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v1, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v7
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b32 v8, v[11:12], off
global_load_b32 v11, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v10, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(3)
v_add_f32_e32 v4, v8, v11
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v6
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v4, -2.0, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, v3, 0x40400000, v4
v_mul_f32_e64 v3, 0x4f800000, |v2|
v_cmp_gt_f32_e64 vcc_lo, 0xf800000, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, |v2|, v3, vcc_lo
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v3, v2
v_fma_f32 v7, -v5, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v6
v_cndmask_b32_e64 v3, v3, v4, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v7
v_cndmask_b32_e64 v3, v3, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13pattern2d_gpuiiiiiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13pattern2d_gpuiiiiiiPfS_, .Lfunc_end0-_Z13pattern2d_gpuiiiiiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13pattern2d_gpuiiiiiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13pattern2d_gpuiiiiiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* MSU CUDA Course Examples and Exercises.
*
* Copyright (c) 2011 Dmitry Mikushin
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising
* from the use of this software.
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it freely,
* without any restrictons.
*/
#include <hip/hip_runtime.h>
#include <malloc.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
// Maximum allowed results difference.
#define EPS 1e-04
// Grid block size (see comment in pattern2d below).
#define BLOCK_LENGTH 32
#define BLOCK_HEIGHT 16
#define IN(i,j) in[i + (j) * nx]
#define OUT(i,j) out[i + (j) * nx]
// GPU device kernel.
__global__ void pattern2d_gpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
// Compute absolute (i,j) indexes for
// the current GPU thread using grid mapping params.
int i = blockIdx.x * BLOCK_LENGTH + threadIdx.x + bx;
int j = blockIdx.y * BLOCK_HEIGHT + threadIdx.y + by;
// Compute one data point - a piece of
// work for the current GPU thread.
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// CPU control implementation.
void pattern2d_cpu(
int bx, int nx, int ex, int by, int ny, int ey,
float* in, float* out)
{
for (int j = by; j < ny - ey; j++)
for (int i = bx; i < nx - ex; i++)
OUT(i,j) = sqrtf(fabs(IN(i,j) + IN(i-1,j) + IN(i+1,j) -
2.0f * IN(i,j-1) + 3.0f * IN(i,j+1)));
}
// Perform some dummy 2D field processing on GPU and CPU,
// and compare results.
int pattern2d(int nx, int ny, float* in, float* out, int pid, int step)
{
if ((nx <= 0) || (ny <= 0)) return -1;
long np = nx * ny;
size_t size = sizeof(float) * np;
// Create GPU data array and copy input data to it.
float* in_gpu;
hipError_t status = hipMalloc((void**)&in_gpu, size);
if (status != hipSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc input memory on GPU by process", pid, status);
return status;
}
status = hipMemcpy(in_gpu, in, size, hipMemcpyHostToDevice);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot copy data from host to gpu by process %d, status = %d\n",
pid, status);
return status;
}
// Create CPU data output array and get
// control result using CPU function.
float* control = (float*)malloc(size);
memset(control, 0, size);
pattern2d_cpu(
1, nx, 1, 1, ny, 1, in, control);
// Configure GPU computational grid:
// nx = nblocks_x * block_length
// ny = nblocks_y * block_height
//
// NOTE: we have degree of freedom in
// selecting how real problem grid maps onto
// computational grid. Usually these params
// are tuned to get optimal performance.
//
// NOTE: chose of grid/block config is
// also limited by device properties:
// - Maximum number of threads per block (512)
// - Maximum sizes of each dimension of a block (512 x 512 x 64)
// - Maximum sizes of each dimension of a grid (65535 x 65535 x 1)
int nblocks_x = (nx - 2) / BLOCK_LENGTH;
int nblocks_y = (ny - 2) / BLOCK_HEIGHT;
// Perform the same processing on GPU,
// returning result to GPU array.
float* out_gpu;
status = hipMalloc((void**)&out_gpu, size);
if (status != hipSuccess)
{
fprintf(stderr, "%s %d, status = %d\nInsufficient GPU memory?\n",
"Cannot malloc output memory on GPU by process", pid, status);
return status;
}
status = hipMemset(out_gpu, 0, size);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot erase output memory on GPU by process %d, status = %d\n",
pid, status);
return status;
}
pattern2d_gpu<<<
dim3(nblocks_x, nblocks_y, 1),
dim3(BLOCK_LENGTH, BLOCK_HEIGHT, 1)>>>(
1, nx, 1, 1, ny, 1, in_gpu, out_gpu);
status = hipGetLastError();
if (status != hipSuccess)
{
fprintf(stderr, "Cannot execute CUDA kernel by process %d, status = %d\n",
pid, status);
return status;
}
status = hipDeviceSynchronize();
if (status != hipSuccess)
{
fprintf(stderr, "Cannot synchronize thread by process %d, status = %d\n",
pid, status);
return status;
}
// Copy GPU result from GPU memory to CPU buffer.
status = hipMemcpy(out, out_gpu, size, hipMemcpyDeviceToHost);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot copy data from gpu to host by process %d, status = %d\n",
pid, status);
return status;
}
// Don't bother with processing the remainder
// on GPU. Do it on CPU instead.
pattern2d_cpu(
1, nx, 1,
ny - (ny - 2) % BLOCK_HEIGHT - 2, ny, 1,
in, out);
pattern2d_cpu(
nx - (nx - 2) % BLOCK_LENGTH - 2, nx, 1,
1, ny, 1,
in, out);
// Compare results and find the maximum abs difference.
int maxi = 0, maxj = 0;
float maxdiff = fabs(out[0] - control[0]);
float* diffs = (float*)malloc(size);
memset(diffs, 0, size);
for (int j = 0; j < ny; j++)
for (int i = 0; i < nx; i++)
{
float diff = fabs(
out[i + j * nx] -
control[i + j * nx]);
if (diff > maxdiff)
{
maxdiff = diff;
maxi = i; maxj = j;
}
diffs[i + j * nx] = diff;
}
// Release data arrays.
status = hipFree(in_gpu);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot free device input memory by process %d, status = %d\n",
pid, status);
return status;
}
free(control);
status = hipFree(out_gpu);
if (status != hipSuccess)
{
fprintf(stderr, "Cannot free device output memory by process %d, status = %d\n",
pid, status);
return status;
}
free(diffs);
printf("Step %d result abs max diff by process %d = %f @ (%d,%d)\n",
step, pid, maxdiff, maxi, maxj);
return 0;
} | .text
.file "pattern2d.hip"
.globl _Z28__device_stub__pattern2d_gpuiiiiiiPfS_ # -- Begin function _Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.p2align 4, 0x90
.type _Z28__device_stub__pattern2d_gpuiiiiiiPfS_,@function
_Z28__device_stub__pattern2d_gpuiiiiiiPfS_: # @_Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13pattern2d_gpuiiiiiiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__pattern2d_gpuiiiiiiPfS_, .Lfunc_end0-_Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13pattern2d_cpuiiiiiiPfS_
.LCPI1_0:
.long 0x40400000 # float 3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z13pattern2d_cpuiiiiiiPfS_
.p2align 4, 0x90
.type _Z13pattern2d_cpuiiiiiiPfS_,@function
_Z13pattern2d_cpuiiiiiiPfS_: # @_Z13pattern2d_cpuiiiiiiPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edi killed $edi def $rdi
movq %rdi, 16(%rsp) # 8-byte Spill
subl %r9d, %r8d
cmpl %ecx, %r8d
jle .LBB1_4
# %bb.1: # %.preheader.lr.ph
movq 152(%rsp), %rax
movq 144(%rsp), %rdi
movl $4294967295, %r9d # imm = 0xFFFFFFFF
movslq %esi, %r10
subl %edx, %esi
movq 16(%rsp), %rdx # 8-byte Reload
movslq %edx, %r11
movq %r11, 40(%rsp) # 8-byte Spill
movl %esi, 12(%rsp) # 4-byte Spill
movslq %esi, %r13
movslq %ecx, %r11
movslq %r8d, %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
leaq 1(%r11), %rcx
imulq %r10, %rcx
leaq (%rdi,%rcx,4), %r15
leaq (,%r10,4), %rcx
movq %rcx, 24(%rsp) # 8-byte Spill
leaq -1(%r11), %rcx
imulq %r10, %rcx
leaq (%rdi,%rcx,4), %rbx
movq %r11, %rcx
imulq %r10, %rcx
leal (%r9,%rdx), %r14d
addl %ecx, %r14d
shlq $32, %r14
shlq $32, %r10
movq %r10, 48(%rsp) # 8-byte Spill
leaq (%rax,%rcx,4), %rdx
leaq (%rdi,%rcx,4), %r12
movss .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
xorps %xmm4, %xmm4
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_3: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq 64(%rsp), %r11 # 8-byte Reload
incq %r11
movq 24(%rsp), %rax # 8-byte Reload
addq %rax, %r15
addq %rax, %rbx
movq 56(%rsp), %r14 # 8-byte Reload
addq 48(%rsp), %r14 # 8-byte Folded Reload
addq %rax, %r12
addq %rax, %rdx
cmpq 32(%rsp), %r11 # 8-byte Folded Reload
jge .LBB1_4
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movq %r11, 64(%rsp) # 8-byte Spill
movq %r14, 56(%rsp) # 8-byte Spill
movq 40(%rsp), %rbp # 8-byte Reload
movq 16(%rsp), %rax # 8-byte Reload
cmpl %eax, 12(%rsp) # 4-byte Folded Reload
movq %rbx, 80(%rsp) # 8-byte Spill
movq %rdx, 72(%rsp) # 8-byte Spill
jg .LBB1_5
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # %call.sqrt
# in Loop: Header=BB1_5 Depth=2
movq %rdi, %rbx
callq sqrtf
xorps %xmm4, %xmm4
movaps .LCPI1_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 72(%rsp), %rdx # 8-byte Reload
movl $4294967295, %r9d # imm = 0xFFFFFFFF
movq %rbx, %rdi
movq 80(%rsp), %rbx # 8-byte Reload
.LBB1_8: # %.split
# in Loop: Header=BB1_5 Depth=2
movss %xmm0, (%rdx,%rbp,4)
incq %rbp
addq %r9, %r14
incq %r14
cmpq %r13, %rbp
jge .LBB1_3
.LBB1_5: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rbp,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %r14, %rax
sarq $30, %rax
addss (%rdi,%rax), %xmm1
addss 4(%r12,%rbp,4), %xmm1
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
subss %xmm0, %xmm1
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
andps %xmm3, %xmm0
ucomiss %xmm4, %xmm0
jb .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB1_8
.LBB1_4: # %._crit_edge36
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13pattern2d_cpuiiiiiiPfS_, .Lfunc_end1-_Z13pattern2d_cpuiiiiiiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9pattern2diiPfS_ii
.LCPI2_0:
.long 0x40400000 # float 3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z9pattern2diiPfS_ii
.p2align 4, 0x90
.type _Z9pattern2diiPfS_ii,@function
_Z9pattern2diiPfS_ii: # @_Z9pattern2diiPfS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 80(%rsp) # 8-byte Spill
movl $-1, %r12d
testl %edi, %edi
jle .LBB2_62
# %bb.1:
movl %esi, %r13d
testl %esi, %esi
jle .LBB2_62
# %bb.2:
movl %r9d, %ebp
movq %rcx, %r14
movl %edi, %r15d
movl %r8d, 4(%rsp) # 4-byte Spill
movl %r13d, %eax
imull %edi, %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 128(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_3
# %bb.5:
movq 128(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movq %r14, 104(%rsp) # 8-byte Spill
movl %ebp, 136(%rsp) # 4-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 168(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, 40(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq memset@PLT
leal -1(%r13), %ecx
movq %r15, 16(%rsp) # 8-byte Spill
movslq %r15d, %rax
movq %rax, 48(%rsp) # 8-byte Spill
movl %ecx, 140(%rsp) # 4-byte Spill
movslq %ecx, %rax
movq %rax, 120(%rsp) # 8-byte Spill
movq %r13, 32(%rsp) # 8-byte Spill
cmpl $3, %r13d
jl .LBB2_16
# %bb.8: # %.preheader.lr.ph.i
movq 80(%rsp), %rax # 8-byte Reload
movq 48(%rsp), %rcx # 8-byte Reload
leaq (%rax,%rcx,8), %r14
addq $4, %r14
leaq (,%rcx,4), %rdx
movq %rdx, 64(%rsp) # 8-byte Spill
leaq 4(%rax), %r15
leaq -2(%rcx), %rbx
leaq (%rax,%rcx,4), %r10
addq $8, %r10
movq %rcx, %r8
shlq $32, %r8
movq 168(%rsp), %rax # 8-byte Reload
leaq (%rax,%rcx,4), %r13
addq $4, %r13
movl $1, %ecx
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
xorps %xmm4, %xmm4
movq %r8, 56(%rsp) # 8-byte Spill
movq %r8, 8(%rsp) # 8-byte Spill
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_15: # %._crit_edge.i
# in Loop: Header=BB2_9 Depth=1
movq 24(%rsp), %rcx # 8-byte Reload
incq %rcx
movq 64(%rsp), %rax # 8-byte Reload
addq %rax, %r14
addq %rax, %r15
addq %rax, %r10
movq 8(%rsp), %r8 # 8-byte Reload
addq 56(%rsp), %r8 # 8-byte Folded Reload
movq %r8, 8(%rsp) # 8-byte Spill
addq %rax, %r13
cmpq 120(%rsp), %rcx # 8-byte Folded Reload
je .LBB2_16
.LBB2_9: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_11 Depth 2
movq %rcx, 24(%rsp) # 8-byte Spill
cmpl $3, 16(%rsp) # 4-byte Folded Reload
jl .LBB2_15
# %bb.10: # %.lr.ph.i
# in Loop: Header=BB2_9 Depth=1
movq 8(%rsp), %rbp # 8-byte Reload
xorl %r12d, %r12d
movq %r10, 72(%rsp) # 8-byte Spill
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_13: # %call.sqrt
# in Loop: Header=BB2_11 Depth=2
callq sqrtf
xorps %xmm4, %xmm4
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 72(%rsp), %r10 # 8-byte Reload
.LBB2_14: # %.split
# in Loop: Header=BB2_11 Depth=2
movss %xmm0, (%r13,%r12,4)
incq %r12
movabsq $4294967296, %rax # imm = 0x100000000
addq %rax, %rbp
cmpq %r12, %rbx
je .LBB2_15
.LBB2_11: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movss -4(%r10,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rbp, %rax
sarq $30, %rax
movq 80(%rsp), %rcx # 8-byte Reload
addss (%rcx,%rax), %xmm1
addss (%r10,%r12,4), %xmm1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
subss %xmm0, %xmm1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
andps %xmm3, %xmm0
ucomiss %xmm4, %xmm0
jb .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB2_14
.LBB2_16: # %_Z13pattern2d_cpuiiiiiiPfS_.exit
movq 16(%rsp), %rbx # 8-byte Reload
leal -2(%rbx), %eax
leal 29(%rbx), %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
movq 32(%rsp), %rcx # 8-byte Reload
leal -2(%rcx), %eax
leal 13(%rcx), %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
leaq 112(%rsp), %rdi
movq 40(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.18:
movq 112(%rsp), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB2_19
# %bb.21:
movl %r15d, %eax
sarl $5, %eax
movl %r13d, %ecx
sarl $4, %ecx
shlq $32, %rcx
movl %eax, %edi
orq %rcx, %rdi
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq 128(%rsp), %rax
movq 112(%rsp), %rcx
movl $1, 164(%rsp)
movl %ebx, 160(%rsp)
movl $1, 156(%rsp)
movl $1, 152(%rsp)
movq 32(%rsp), %rdx # 8-byte Reload
movl %edx, 148(%rsp)
movl $1, 144(%rsp)
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
leaq 164(%rsp), %rax
movq %rax, 240(%rsp)
leaq 160(%rsp), %rax
movq %rax, 248(%rsp)
leaq 156(%rsp), %rax
movq %rax, 256(%rsp)
leaq 152(%rsp), %rax
movq %rax, 264(%rsp)
leaq 148(%rsp), %rax
movq %rax, 272(%rsp)
leaq 144(%rsp), %rax
movq %rax, 280(%rsp)
leaq 232(%rsp), %rax
movq %rax, 288(%rsp)
leaq 224(%rsp), %rax
movq %rax, 296(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z13pattern2d_gpuiiiiiiPfS_, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_23:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.25:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_26
# %bb.27:
movq 112(%rsp), %rsi
movq 104(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_28
# %bb.29:
movq %r15, 40(%rsp) # 8-byte Spill
andl $-16, %r13d
negl %r13d
movq 32(%rsp), %rax # 8-byte Reload
leal (%rax,%r13), %ecx
addl $-2, %ecx
# kill: def $eax killed $eax killed $rax
subl %ecx, %eax
addl $-2, %eax
cmpl %eax, 140(%rsp) # 4-byte Folded Reload
jle .LBB2_38
# %bb.30: # %.preheader.lr.ph.i144
movq 16(%rsp), %rcx # 8-byte Reload
decl %ecx
movslq %ecx, %r15
movslq %eax, %rdi
leaq 1(%rdi), %rax
movq 48(%rsp), %rdx # 8-byte Reload
imulq %rdx, %rax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
addq $4, %r13
leaq (,%rdx,4), %rax
movq %rax, 64(%rsp) # 8-byte Spill
leaq -1(%rdi), %rax
imulq %rdx, %rax
leaq (%rcx,%rax,4), %r14
addq $4, %r14
decq %r15
movq %rdx, %r10
imulq %rdi, %r10
leaq (%rcx,%r10,4), %r11
addq $8, %r11
shlq $32, %rdx
movq %rdx, 56(%rsp) # 8-byte Spill
movq 104(%rsp), %rax # 8-byte Reload
leaq (%rax,%r10,4), %r12
addq $4, %r12
shlq $32, %r10
movq %r10, 24(%rsp) # 8-byte Spill
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
xorps %xmm4, %xmm4
jmp .LBB2_31
.p2align 4, 0x90
.LBB2_37: # %._crit_edge.i147
# in Loop: Header=BB2_31 Depth=1
movq 8(%rsp), %rdi # 8-byte Reload
incq %rdi
movq 64(%rsp), %rax # 8-byte Reload
addq %rax, %r13
addq %rax, %r14
addq %rax, %r11
movq 56(%rsp), %rcx # 8-byte Reload
addq %rcx, 24(%rsp) # 8-byte Folded Spill
addq %rax, %r12
cmpq 120(%rsp), %rdi # 8-byte Folded Reload
je .LBB2_38
.LBB2_31: # %.preheader.i145
# =>This Loop Header: Depth=1
# Child Loop BB2_33 Depth 2
movq %rdi, 8(%rsp) # 8-byte Spill
cmpl $3, 16(%rsp) # 4-byte Folded Reload
jl .LBB2_37
# %bb.32: # %.lr.ph.i149
# in Loop: Header=BB2_31 Depth=1
movq 24(%rsp), %rbp # 8-byte Reload
xorl %ebx, %ebx
movq %r11, 72(%rsp) # 8-byte Spill
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_35: # %call.sqrt273
# in Loop: Header=BB2_33 Depth=2
callq sqrtf
xorps %xmm4, %xmm4
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 72(%rsp), %r11 # 8-byte Reload
.LBB2_36: # %.split272
# in Loop: Header=BB2_33 Depth=2
movss %xmm0, (%r12,%rbx,4)
incq %rbx
movabsq $4294967296, %rax # imm = 0x100000000
addq %rax, %rbp
cmpq %rbx, %r15
je .LBB2_37
.LBB2_33: # Parent Loop BB2_31 Depth=1
# => This Inner Loop Header: Depth=2
movss -4(%r11,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rbp, %rax
sarq $30, %rax
movq 80(%rsp), %rcx # 8-byte Reload
addss (%rcx,%rax), %xmm1
addss (%r11,%rbx,4), %xmm1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
subss %xmm0, %xmm1
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
andps %xmm3, %xmm0
ucomiss %xmm4, %xmm0
jb .LBB2_35
# %bb.34: # in Loop: Header=BB2_33 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB2_36
.LBB2_38: # %_Z13pattern2d_cpuiiiiiiPfS_.exit153
cmpl $3, 32(%rsp) # 4-byte Folded Reload
jl .LBB2_47
# %bb.39: # %.preheader.lr.ph.i154
movq 40(%rsp), %rcx # 8-byte Reload
andl $-32, %ecx
negl %ecx
movq 16(%rsp), %rdx # 8-byte Reload
leal (%rdx,%rcx), %eax
addl $-2, %eax
movl %edx, %ecx
subl %eax, %ecx
movslq %ecx, %rax
addl $-2, %ecx
movl %ecx, 64(%rsp) # 4-byte Spill
leaq -2(%rax), %rcx
decl %edx
movl %edx, 56(%rsp) # 4-byte Spill
movslq %edx, %r13
subq %rcx, %r13
leaq -8(,%rax,4), %rcx
movq 48(%rsp), %rsi # 8-byte Reload
leaq (%rcx,%rsi,8), %r15
movq 80(%rsp), %rdx # 8-byte Reload
addq %rdx, %r15
leaq (,%rsi,4), %r9
movq %r9, 40(%rsp) # 8-byte Spill
leaq (%rdx,%rax,4), %r14
addq $-8, %r14
leaq (%rcx,%rsi,4), %r10
addq %rdx, %r10
addq %rsi, %rax
addq $-2, %rax
movabsq $4294967296, %rcx # imm = 0x100000000
addl %eax, %ecx
decl %ecx
shlq $32, %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
shlq $32, %rsi
movq %rsi, 48(%rsp) # 8-byte Spill
movq 104(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
movl $1, %esi
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
xorps %xmm4, %xmm4
jmp .LBB2_40
.p2align 4, 0x90
.LBB2_46: # %._crit_edge.i157
# in Loop: Header=BB2_40 Depth=1
movq 24(%rsp), %rsi # 8-byte Reload
incq %rsi
movq 40(%rsp), %rax # 8-byte Reload
addq %rax, %r15
addq %rax, %r14
addq %rax, %r10
movq 8(%rsp), %rcx # 8-byte Reload
addq 48(%rsp), %rcx # 8-byte Folded Reload
movq %rcx, 8(%rsp) # 8-byte Spill
addq %rax, %r12
cmpq 120(%rsp), %rsi # 8-byte Folded Reload
je .LBB2_47
.LBB2_40: # %.preheader.i155
# =>This Loop Header: Depth=1
# Child Loop BB2_42 Depth 2
movq %rsi, 24(%rsp) # 8-byte Spill
movl 56(%rsp), %eax # 4-byte Reload
cmpl 64(%rsp), %eax # 4-byte Folded Reload
jle .LBB2_46
# %bb.41: # %.lr.ph.i159
# in Loop: Header=BB2_40 Depth=1
movq 8(%rsp), %rbp # 8-byte Reload
xorl %ebx, %ebx
movq %r10, 72(%rsp) # 8-byte Spill
jmp .LBB2_42
.p2align 4, 0x90
.LBB2_44: # %call.sqrt275
# in Loop: Header=BB2_42 Depth=2
callq sqrtf
xorps %xmm4, %xmm4
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 72(%rsp), %r10 # 8-byte Reload
.LBB2_45: # %.split274
# in Loop: Header=BB2_42 Depth=2
movss %xmm0, (%r12,%rbx,4)
incq %rbx
movabsq $4294967296, %rax # imm = 0x100000000
addq %rax, %rbp
cmpq %rbx, %r13
je .LBB2_46
.LBB2_42: # Parent Loop BB2_40 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r10,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rbp, %rax
sarq $30, %rax
movq 80(%rsp), %rcx # 8-byte Reload
addss (%rcx,%rax), %xmm1
addss 4(%r10,%rbx,4), %xmm1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
subss %xmm0, %xmm1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
andps %xmm3, %xmm0
ucomiss %xmm4, %xmm0
jb .LBB2_44
# %bb.43: # in Loop: Header=BB2_42 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB2_45
.LBB2_47: # %_Z13pattern2d_cpuiiiiiiPfS_.exit163
movq 104(%rsp), %r10 # 8-byte Reload
movss (%r10), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 168(%rsp), %r15 # 8-byte Reload
subss (%r15), %xmm2
andps .LCPI2_1(%rip), %xmm2
movq 32(%rsp), %rax # 8-byte Reload
testl %eax, %eax
jle .LBB2_48
# %bb.49: # %.preheader.lr.ph
movl %eax, %eax
movq 16(%rsp), %r11 # 8-byte Reload
movl %r11d, %ecx
xorl %edx, %edx
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
xorl %esi, %esi
movaps %xmm2, %xmm1
xorl %ebp, %ebp
xorl %ebx, %ebx
movl 4(%rsp), %r14d # 4-byte Reload
jmp .LBB2_50
.p2align 4, 0x90
.LBB2_51: # in Loop: Header=BB2_50 Depth=1
movaps %xmm1, %xmm2
.LBB2_52: # %._crit_edge
# in Loop: Header=BB2_50 Depth=1
incq %rsi
addl %r11d, %edx
movaps %xmm2, %xmm1
cmpq %rax, %rsi
je .LBB2_53
.LBB2_50: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_58 Depth 2
testl %r11d, %r11d
jle .LBB2_51
# %bb.57: # %.lr.ph
# in Loop: Header=BB2_50 Depth=1
movl %edx, %r8d
leaq (%r15,%r8,4), %rdi
leaq (%r10,%r8,4), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_58: # Parent Loop BB2_50 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r8,%r9,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rdi,%r9,4), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
cmoval %r9d, %ebx
cmoval %esi, %ebp
maxss %xmm1, %xmm2
incq %r9
movaps %xmm2, %xmm1
cmpq %r9, %rcx
jne .LBB2_58
jmp .LBB2_52
.LBB2_48:
xorl %ebx, %ebx
xorl %ebp, %ebp
movl 4(%rsp), %r14d # 4-byte Reload
.LBB2_53: # %._crit_edge181
movaps %xmm2, 80(%rsp) # 16-byte Spill
movq 128(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_54
# %bb.59:
movq %r15, %rdi
callq free
movq 112(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_60
# %bb.61:
movaps 80(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movl 136(%rsp), %esi # 4-byte Reload
movl %r14d, %edx
movl %ebx, %ecx
movl %ebp, %r8d
movb $1, %al
callq printf
xorl %r12d, %r12d
jmp .LBB2_62
.LBB2_3:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
jmp .LBB2_4
.LBB2_6:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.2, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_17:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.3, %edx
.LBB2_4:
movl 4(%rsp), %ecx # 4-byte Reload
movl %r12d, %r8d
xorl %eax, %eax
callq fprintf
jmp .LBB2_62
.LBB2_19:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_24:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_26:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_28:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_54:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
jmp .LBB2_55
.LBB2_60:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
.LBB2_55:
movl %r14d, %edx
.LBB2_56:
movl %r12d, %ecx
xorl %eax, %eax
callq fprintf
.LBB2_62:
movl %r12d, %eax
addq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9pattern2diiPfS_ii, .Lfunc_end2-_Z9pattern2diiPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13pattern2d_gpuiiiiiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13pattern2d_gpuiiiiiiPfS_,@object # @_Z13pattern2d_gpuiiiiiiPfS_
.section .rodata,"a",@progbits
.globl _Z13pattern2d_gpuiiiiiiPfS_
.p2align 3, 0x0
_Z13pattern2d_gpuiiiiiiPfS_:
.quad _Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.size _Z13pattern2d_gpuiiiiiiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s %d, status = %d\nInsufficient GPU memory?\n"
.size .L.str, 45
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cannot malloc input memory on GPU by process"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cannot copy data from host to gpu by process %d, status = %d\n"
.size .L.str.2, 62
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cannot malloc output memory on GPU by process"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cannot erase output memory on GPU by process %d, status = %d\n"
.size .L.str.4, 62
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cannot execute CUDA kernel by process %d, status = %d\n"
.size .L.str.5, 55
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Cannot synchronize thread by process %d, status = %d\n"
.size .L.str.6, 54
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Cannot copy data from gpu to host by process %d, status = %d\n"
.size .L.str.7, 62
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Cannot free device input memory by process %d, status = %d\n"
.size .L.str.8, 60
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Cannot free device output memory by process %d, status = %d\n"
.size .L.str.9, 61
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Step %d result abs max diff by process %d = %f @ (%d,%d)\n"
.size .L.str.10, 58
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13pattern2d_gpuiiiiiiPfS_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13pattern2d_gpuiiiiiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13pattern2d_gpuiiiiiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ MOV R10, c[0x0][0x164] ; /* 0x00005900000a7a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0080*/ LEA R2, R2, R5, 0x4 ; /* 0x0000000502027211 */
/* 0x001fc400078e20ff */
/*0090*/ LEA R0, R0, R3, 0x5 ; /* 0x0000000300007211 */
/* 0x002fe400078e28ff */
/*00a0*/ IADD3 R3, R2, c[0x0][0x16c], RZ ; /* 0x00005b0002037a10 */
/* 0x000fe40007ffe0ff */
/*00b0*/ IADD3 R4, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc60007ffe0ff */
/*00c0*/ IMAD R5, R3.reuse, R10, -c[0x0][0x164] ; /* 0x8000590003057624 */
/* 0x040fe400078e020a */
/*00d0*/ IMAD R0, R3, c[0x0][0x164], R4 ; /* 0x0000590003007a24 */
/* 0x000fc600078e0204 */
/*00e0*/ IADD3 R6, R4, R5, RZ ; /* 0x0000000504067210 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e0207 */
/*0100*/ IMAD.WIDE R4, R6, R7, c[0x0][0x178] ; /* 0x00005e0006047625 */
/* 0x000fe200078e0207 */
/*0110*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0120*/ LEA R6, R10, R6, 0x1 ; /* 0x000000060a067211 */
/* 0x000fc600078e08ff */
/*0130*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0402097981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe400078e0207 */
/*0150*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f28000c1e1900 */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f62000c1e1900 */
/*0180*/ BSSY B0, 0x2b0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0190*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000000 */
/*01a0*/ FADD R8, R8, R11 ; /* 0x0000000b08087221 */
/* 0x008fe40000000000 */
/*01b0*/ FADD R9, R4, R4 ; /* 0x0000000404097221 */
/* 0x010fc80000000000 */
/*01c0*/ FADD R8, R8, -R9 ; /* 0x8000000908087221 */
/* 0x000fc80000000000 */
/*01d0*/ FFMA R8, R7, 3, R8 ; /* 0x4040000007087823 */
/* 0x020fc80000000008 */
/*01e0*/ FADD R10, |R8|, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fe20000000200 */
/*01f0*/ MUFU.RSQ R3, |R8| ; /* 0x4000000800037308 */
/* 0x0000680000001400 */
/*0200*/ IADD3 R9, R10, -0xd000000, RZ ; /* 0xf30000000a097810 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GT.U32.AND P0, PT, R9, 0x727fffff, PT ; /* 0x727fffff0900780c */
/* 0x000fda0003f04070 */
/*0220*/ @!P0 BRA 0x260 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R7, 0x250 ; /* 0x0000025000077802 */
/* 0x003fe40000000f00 */
/*0240*/ CALL.REL.NOINC 0x2f0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0250*/ BRA 0x2a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0260*/ FMUL.FTZ R5, |R8|, R3 ; /* 0x0000000308057220 */
/* 0x003fe40000410200 */
/*0270*/ FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000410000 */
/*0280*/ FFMA R8, -R5, R5, |R8| ; /* 0x0000000505087223 */
/* 0x000fc80000000508 */
/*0290*/ FFMA R5, R8, R3, R5 ; /* 0x0000000308057223 */
/* 0x000fe40000000005 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*02c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0203 */
/*02d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*0300*/ @!P0 MOV R2, R10 ; /* 0x0000000a00028202 */
/* 0x000fe20000000f00 */
/*0310*/ @!P0 BRA 0x420 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0320*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f1e000 */
/*0330*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0340*/ @!P0 BRA 0x420 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1c200 */
/*0360*/ @P0 FADD.FTZ R2, R10, 1 ; /* 0x3f8000000a020421 */
/* 0x000fe20000010000 */
/*0370*/ @P0 BRA 0x420 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0380*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1d200 */
/*0390*/ @P0 FFMA R3, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a030823 */
/* 0x000fc800000000ff */
/*03a0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*03b0*/ @P0 FMUL.FTZ R4, R3, R2 ; /* 0x0000000203040220 */
/* 0x001fe40000410000 */
/*03c0*/ @P0 FMUL.FTZ R6, R2, 0.5 ; /* 0x3f00000002060820 */
/* 0x000fe20000410000 */
/*03d0*/ @!P0 MOV R2, R10 ; /* 0x0000000a00028202 */
/* 0x000fe20000000f00 */
/*03e0*/ @P0 FADD.FTZ R5, -R4, -RZ ; /* 0x800000ff04050221 */
/* 0x000fc80000010100 */
/*03f0*/ @P0 FFMA R5, R4, R5, R3 ; /* 0x0000000504050223 */
/* 0x000fc80000000003 */
/*0400*/ @P0 FFMA R5, R5, R6, R4 ; /* 0x0000000605050223 */
/* 0x000fc80000000004 */
/*0410*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0420*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0430*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x000fe40000000f00 */
/*0440*/ MOV R2, R7 ; /* 0x0000000700027202 */
/* 0x000fc80000000f00 */
/*0450*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffba002007950 */
/* 0x000fea0003c3ffff */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13pattern2d_gpuiiiiiiPfS_
.globl _Z13pattern2d_gpuiiiiiiPfS_
.p2align 8
.type _Z13pattern2d_gpuiiiiiiPfS_,@function
_Z13pattern2d_gpuiiiiiiPfS_:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0xc
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s3, s14, 5
s_lshl_b32 s6, s15, 4
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, s4, s3, v1
v_add3_u32 v3, s2, s6, v2
s_load_b128 s[0:3], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, v3, s5, v[0:1]
v_add_nc_u32_e32 v2, -1, v3
v_add_nc_u32_e32 v5, -1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[3:4], null, v2, s5, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v7, 1, v1
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v9, s5, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s0, v0
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v1, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v7
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b32 v8, v[11:12], off
global_load_b32 v11, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v10, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(3)
v_add_f32_e32 v4, v8, v11
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v6
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v4, -2.0, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, v3, 0x40400000, v4
v_mul_f32_e64 v3, 0x4f800000, |v2|
v_cmp_gt_f32_e64 vcc_lo, 0xf800000, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, |v2|, v3, vcc_lo
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v3, v2
v_fma_f32 v7, -v5, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v6
v_cndmask_b32_e64 v3, v3, v4, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v7
v_cndmask_b32_e64 v3, v3, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13pattern2d_gpuiiiiiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13pattern2d_gpuiiiiiiPfS_, .Lfunc_end0-_Z13pattern2d_gpuiiiiiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13pattern2d_gpuiiiiiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13pattern2d_gpuiiiiiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a59a6_00000000-6_pattern2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13pattern2d_cpuiiiiiiPfS_
.type _Z13pattern2d_cpuiiiiiiPfS_, @function
_Z13pattern2d_cpuiiiiiiPfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %edi, %ebp
movl %ecx, %ebx
movq 56(%rsp), %rcx
movq 64(%rsp), %rdi
subl %r9d, %r8d
cmpl %r8d, %ebx
jge .L3
movl %esi, %r12d
movl %ebx, %r11d
imull %esi, %r11d
movl %esi, %r13d
subl %edx, %r13d
movslq %ebp, %r14
movl %r13d, %eax
subl %ebp, %eax
addq %r14, %rax
movq %rax, -8(%rsp)
leal (%rsi,%rsi), %r15d
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
jmp .L5
.L7:
movl %r11d, %r10d
subl %r12d, %r10d
movslq %r11d, %r9
leaq (%r9,%r14), %rax
salq $2, %rax
movq -8(%rsp), %rsi
addq %r9, %rsi
salq $2, %rsi
negq %r9
salq $2, %r9
movslq %r10d, %rdx
leaq (%r9,%rdx,4), %rdx
addq %rcx, %rdx
addl %r15d, %r10d
movslq %r10d, %r10
leaq (%r9,%r10,4), %r9
addq %rcx, %r9
.L6:
movss (%rcx,%rax), %xmm0
addss -4(%rcx,%rax), %xmm0
addss 4(%rcx,%rax), %xmm0
movss (%rdx,%rax), %xmm1
addss %xmm1, %xmm1
subss %xmm1, %xmm0
movaps %xmm3, %xmm1
mulss (%r9,%rax), %xmm1
addss %xmm1, %xmm0
andps %xmm2, %xmm0
sqrtss %xmm0, %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L6
.L8:
addl $1, %ebx
addl %r12d, %r11d
cmpl %r8d, %ebx
je .L3
.L5:
cmpl %r13d, %ebp
jl .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13pattern2d_cpuiiiiiiPfS_, .-_Z13pattern2d_cpuiiiiiiPfS_
.globl _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
.type _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_, @function
_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 208(%rsp), %rax
movq %rax, 16(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13pattern2d_gpuiiiiiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_, .-_Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
.globl _Z13pattern2d_gpuiiiiiiPfS_
.type _Z13pattern2d_gpuiiiiiiPfS_, @function
_Z13pattern2d_gpuiiiiiiPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13pattern2d_gpuiiiiiiPfS_, .-_Z13pattern2d_gpuiiiiiiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Cannot malloc input memory on GPU by process"
.align 8
.LC3:
.string "%s %d, status = %d\nInsufficient GPU memory?\n"
.align 8
.LC4:
.string "Cannot copy data from host to gpu by process %d, status = %d\n"
.align 8
.LC5:
.string "Cannot malloc output memory on GPU by process"
.align 8
.LC6:
.string "Cannot erase output memory on GPU by process %d, status = %d\n"
.align 8
.LC7:
.string "Cannot execute CUDA kernel by process %d, status = %d\n"
.align 8
.LC8:
.string "Cannot synchronize thread by process %d, status = %d\n"
.align 8
.LC9:
.string "Cannot copy data from gpu to host by process %d, status = %d\n"
.align 8
.LC10:
.string "Cannot free device input memory by process %d, status = %d\n"
.align 8
.LC11:
.string "Cannot free device output memory by process %d, status = %d\n"
.align 8
.LC12:
.string "Step %d result abs max diff by process %d = %f @ (%d,%d)\n"
.text
.globl _Z9pattern2diiPfS_ii
.type _Z9pattern2diiPfS_ii, @function
_Z9pattern2diiPfS_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rcx, 8(%rsp)
movl %r9d, 24(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
testl %edi, %edi
jle .L37
movl %edi, %ebx
movl %esi, %r12d
movq %rdx, %r13
movl %r8d, %r14d
testl %esi, %esi
jle .L37
movl %edi, %ebp
imull %esi, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L42
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
pushq %r15
.cfi_def_cfa_offset 152
pushq %r13
.cfi_def_cfa_offset 160
movl $1, %r9d
movl %r12d, %r8d
movl $1, %ecx
movl $1, %edx
movl %ebx, %esi
movl $1, %edi
call _Z13pattern2d_cpuiiiiiiPfS_
addq $16, %rsp
.cfi_def_cfa_offset 144
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L43
movq %rbp, %rdx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
testl %eax, %eax
jne .L44
movl $32, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
leal 29(%rbx), %eax
movl %ebx, %ecx
subl $2, %ecx
movl %ecx, 16(%rsp)
cmovns %ecx, %eax
sarl $5, %eax
movl %eax, 48(%rsp)
leal 13(%r12), %eax
movl %r12d, %esi
subl $2, %esi
movl %esi, 28(%rsp)
cmovns %esi, %eax
sarl $4, %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L25:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L46
call cudaThreadSynchronize@PLT
testl %eax, %eax
jne .L47
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl 28(%rsp), %eax
movl %eax, %edx
sarl $31, %edx
shrl $28, %edx
addl %edx, %eax
andl $15, %eax
subl %edx, %eax
movl %r12d, %ecx
subl %eax, %ecx
subl $2, %ecx
pushq 8(%rsp)
.cfi_def_cfa_offset 152
pushq %r13
.cfi_def_cfa_offset 160
movl $1, %r9d
movl %r12d, %r8d
movl $1, %edx
movl %ebx, %esi
movl $1, %edi
call _Z13pattern2d_cpuiiiiiiPfS_
movl 32(%rsp), %eax
movl %eax, %edx
sarl $31, %edx
shrl $27, %edx
addl %edx, %eax
andl $31, %eax
subl %edx, %eax
movl %ebx, %edi
subl %eax, %edi
subl $2, %edi
pushq 24(%rsp)
.cfi_def_cfa_offset 168
pushq %r13
.cfi_def_cfa_offset 176
movl $1, %r9d
movl %r12d, %r8d
movl $1, %ecx
movl $1, %edx
movl %ebx, %esi
call _Z13pattern2d_cpuiiiiiiPfS_
movq 40(%rsp), %r13
movss 0(%r13), %xmm0
subss (%r15), %xmm0
andps .LC1(%rip), %xmm0
movss %xmm0, 40(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 144
movq %rbp, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %rax, %rbp
movq %rax, %rdi
call __memset_chk@PLT
movslq %ebx, %r8
salq $2, %r8
movq %rbp, %rdi
movq %r13, %rdx
movq %r15, %rsi
movl $0, %ecx
movl $0, %r13d
movl $0, %ebp
movss .LC1(%rip), %xmm1
.L29:
movl $0, %eax
.L32:
movss (%rdx,%rax,4), %xmm0
subss (%rsi,%rax,4), %xmm0
andps %xmm1, %xmm0
movss 8(%rsp), %xmm2
comiss %xmm2, %xmm0
cmova %eax, %ebp
movaps %xmm0, %xmm3
maxss %xmm2, %xmm3
movss %xmm3, 8(%rsp)
cmova %ecx, %r13d
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpl %eax, %ebx
jg .L32
addl $1, %ecx
addq %r8, %rdi
addq %r8, %rdx
addq %r8, %rsi
cmpl %ecx, %r12d
jg .L29
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L49
movq %r15, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L50
movq 16(%rsp), %rdi
call free@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
movl %r13d, %r9d
movl %ebp, %r8d
movl %r14d, %ecx
movl 24(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L19
.L41:
movl %eax, %ebx
movl %eax, %r9d
movl %r14d, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl %ebx, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L43:
movl %eax, %ebx
movl %eax, %r9d
movl %r14d, %r8d
leaq .LC5(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L44:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L45:
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
movl $1, %r9d
movl %r12d, %r8d
movl $1, %ecx
movl $1, %edx
movl %ebx, %esi
movl $1, %edi
call _Z41__device_stub__Z13pattern2d_gpuiiiiiiPfS_iiiiiiPfS_
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L46:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L47:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L48:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L49:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L50:
movl %eax, %ebx
movl %eax, %r8d
movl %r14d, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L19
.L37:
movl $-1, %ebx
jmp .L19
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9pattern2diiPfS_ii, .-_Z9pattern2diiPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC13:
.string "_Z13pattern2d_gpuiiiiiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z13pattern2d_gpuiiiiiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pattern2d.hip"
.globl _Z28__device_stub__pattern2d_gpuiiiiiiPfS_ # -- Begin function _Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.p2align 4, 0x90
.type _Z28__device_stub__pattern2d_gpuiiiiiiPfS_,@function
_Z28__device_stub__pattern2d_gpuiiiiiiPfS_: # @_Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13pattern2d_gpuiiiiiiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__pattern2d_gpuiiiiiiPfS_, .Lfunc_end0-_Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13pattern2d_cpuiiiiiiPfS_
.LCPI1_0:
.long 0x40400000 # float 3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z13pattern2d_cpuiiiiiiPfS_
.p2align 4, 0x90
.type _Z13pattern2d_cpuiiiiiiPfS_,@function
_Z13pattern2d_cpuiiiiiiPfS_: # @_Z13pattern2d_cpuiiiiiiPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edi killed $edi def $rdi
movq %rdi, 16(%rsp) # 8-byte Spill
subl %r9d, %r8d
cmpl %ecx, %r8d
jle .LBB1_4
# %bb.1: # %.preheader.lr.ph
movq 152(%rsp), %rax
movq 144(%rsp), %rdi
movl $4294967295, %r9d # imm = 0xFFFFFFFF
movslq %esi, %r10
subl %edx, %esi
movq 16(%rsp), %rdx # 8-byte Reload
movslq %edx, %r11
movq %r11, 40(%rsp) # 8-byte Spill
movl %esi, 12(%rsp) # 4-byte Spill
movslq %esi, %r13
movslq %ecx, %r11
movslq %r8d, %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
leaq 1(%r11), %rcx
imulq %r10, %rcx
leaq (%rdi,%rcx,4), %r15
leaq (,%r10,4), %rcx
movq %rcx, 24(%rsp) # 8-byte Spill
leaq -1(%r11), %rcx
imulq %r10, %rcx
leaq (%rdi,%rcx,4), %rbx
movq %r11, %rcx
imulq %r10, %rcx
leal (%r9,%rdx), %r14d
addl %ecx, %r14d
shlq $32, %r14
shlq $32, %r10
movq %r10, 48(%rsp) # 8-byte Spill
leaq (%rax,%rcx,4), %rdx
leaq (%rdi,%rcx,4), %r12
movss .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
xorps %xmm4, %xmm4
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_3: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq 64(%rsp), %r11 # 8-byte Reload
incq %r11
movq 24(%rsp), %rax # 8-byte Reload
addq %rax, %r15
addq %rax, %rbx
movq 56(%rsp), %r14 # 8-byte Reload
addq 48(%rsp), %r14 # 8-byte Folded Reload
addq %rax, %r12
addq %rax, %rdx
cmpq 32(%rsp), %r11 # 8-byte Folded Reload
jge .LBB1_4
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movq %r11, 64(%rsp) # 8-byte Spill
movq %r14, 56(%rsp) # 8-byte Spill
movq 40(%rsp), %rbp # 8-byte Reload
movq 16(%rsp), %rax # 8-byte Reload
cmpl %eax, 12(%rsp) # 4-byte Folded Reload
movq %rbx, 80(%rsp) # 8-byte Spill
movq %rdx, 72(%rsp) # 8-byte Spill
jg .LBB1_5
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # %call.sqrt
# in Loop: Header=BB1_5 Depth=2
movq %rdi, %rbx
callq sqrtf
xorps %xmm4, %xmm4
movaps .LCPI1_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 72(%rsp), %rdx # 8-byte Reload
movl $4294967295, %r9d # imm = 0xFFFFFFFF
movq %rbx, %rdi
movq 80(%rsp), %rbx # 8-byte Reload
.LBB1_8: # %.split
# in Loop: Header=BB1_5 Depth=2
movss %xmm0, (%rdx,%rbp,4)
incq %rbp
addq %r9, %r14
incq %r14
cmpq %r13, %rbp
jge .LBB1_3
.LBB1_5: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rbp,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %r14, %rax
sarq $30, %rax
addss (%rdi,%rax), %xmm1
addss 4(%r12,%rbp,4), %xmm1
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
subss %xmm0, %xmm1
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
andps %xmm3, %xmm0
ucomiss %xmm4, %xmm0
jb .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB1_8
.LBB1_4: # %._crit_edge36
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13pattern2d_cpuiiiiiiPfS_, .Lfunc_end1-_Z13pattern2d_cpuiiiiiiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9pattern2diiPfS_ii
.LCPI2_0:
.long 0x40400000 # float 3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z9pattern2diiPfS_ii
.p2align 4, 0x90
.type _Z9pattern2diiPfS_ii,@function
_Z9pattern2diiPfS_ii: # @_Z9pattern2diiPfS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 80(%rsp) # 8-byte Spill
movl $-1, %r12d
testl %edi, %edi
jle .LBB2_62
# %bb.1:
movl %esi, %r13d
testl %esi, %esi
jle .LBB2_62
# %bb.2:
movl %r9d, %ebp
movq %rcx, %r14
movl %edi, %r15d
movl %r8d, 4(%rsp) # 4-byte Spill
movl %r13d, %eax
imull %edi, %eax
movslq %eax, %rbx
shlq $2, %rbx
leaq 128(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_3
# %bb.5:
movq 128(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movq %r14, 104(%rsp) # 8-byte Spill
movl %ebp, 136(%rsp) # 4-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 168(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, 40(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq memset@PLT
leal -1(%r13), %ecx
movq %r15, 16(%rsp) # 8-byte Spill
movslq %r15d, %rax
movq %rax, 48(%rsp) # 8-byte Spill
movl %ecx, 140(%rsp) # 4-byte Spill
movslq %ecx, %rax
movq %rax, 120(%rsp) # 8-byte Spill
movq %r13, 32(%rsp) # 8-byte Spill
cmpl $3, %r13d
jl .LBB2_16
# %bb.8: # %.preheader.lr.ph.i
movq 80(%rsp), %rax # 8-byte Reload
movq 48(%rsp), %rcx # 8-byte Reload
leaq (%rax,%rcx,8), %r14
addq $4, %r14
leaq (,%rcx,4), %rdx
movq %rdx, 64(%rsp) # 8-byte Spill
leaq 4(%rax), %r15
leaq -2(%rcx), %rbx
leaq (%rax,%rcx,4), %r10
addq $8, %r10
movq %rcx, %r8
shlq $32, %r8
movq 168(%rsp), %rax # 8-byte Reload
leaq (%rax,%rcx,4), %r13
addq $4, %r13
movl $1, %ecx
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
xorps %xmm4, %xmm4
movq %r8, 56(%rsp) # 8-byte Spill
movq %r8, 8(%rsp) # 8-byte Spill
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_15: # %._crit_edge.i
# in Loop: Header=BB2_9 Depth=1
movq 24(%rsp), %rcx # 8-byte Reload
incq %rcx
movq 64(%rsp), %rax # 8-byte Reload
addq %rax, %r14
addq %rax, %r15
addq %rax, %r10
movq 8(%rsp), %r8 # 8-byte Reload
addq 56(%rsp), %r8 # 8-byte Folded Reload
movq %r8, 8(%rsp) # 8-byte Spill
addq %rax, %r13
cmpq 120(%rsp), %rcx # 8-byte Folded Reload
je .LBB2_16
.LBB2_9: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_11 Depth 2
movq %rcx, 24(%rsp) # 8-byte Spill
cmpl $3, 16(%rsp) # 4-byte Folded Reload
jl .LBB2_15
# %bb.10: # %.lr.ph.i
# in Loop: Header=BB2_9 Depth=1
movq 8(%rsp), %rbp # 8-byte Reload
xorl %r12d, %r12d
movq %r10, 72(%rsp) # 8-byte Spill
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_13: # %call.sqrt
# in Loop: Header=BB2_11 Depth=2
callq sqrtf
xorps %xmm4, %xmm4
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 72(%rsp), %r10 # 8-byte Reload
.LBB2_14: # %.split
# in Loop: Header=BB2_11 Depth=2
movss %xmm0, (%r13,%r12,4)
incq %r12
movabsq $4294967296, %rax # imm = 0x100000000
addq %rax, %rbp
cmpq %r12, %rbx
je .LBB2_15
.LBB2_11: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movss -4(%r10,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rbp, %rax
sarq $30, %rax
movq 80(%rsp), %rcx # 8-byte Reload
addss (%rcx,%rax), %xmm1
addss (%r10,%r12,4), %xmm1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
subss %xmm0, %xmm1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
andps %xmm3, %xmm0
ucomiss %xmm4, %xmm0
jb .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB2_14
.LBB2_16: # %_Z13pattern2d_cpuiiiiiiPfS_.exit
movq 16(%rsp), %rbx # 8-byte Reload
leal -2(%rbx), %eax
leal 29(%rbx), %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
movq 32(%rsp), %rcx # 8-byte Reload
leal -2(%rcx), %eax
leal 13(%rcx), %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
leaq 112(%rsp), %rdi
movq 40(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.18:
movq 112(%rsp), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB2_19
# %bb.21:
movl %r15d, %eax
sarl $5, %eax
movl %r13d, %ecx
sarl $4, %ecx
shlq $32, %rcx
movl %eax, %edi
orq %rcx, %rdi
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq 128(%rsp), %rax
movq 112(%rsp), %rcx
movl $1, 164(%rsp)
movl %ebx, 160(%rsp)
movl $1, 156(%rsp)
movl $1, 152(%rsp)
movq 32(%rsp), %rdx # 8-byte Reload
movl %edx, 148(%rsp)
movl $1, 144(%rsp)
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
leaq 164(%rsp), %rax
movq %rax, 240(%rsp)
leaq 160(%rsp), %rax
movq %rax, 248(%rsp)
leaq 156(%rsp), %rax
movq %rax, 256(%rsp)
leaq 152(%rsp), %rax
movq %rax, 264(%rsp)
leaq 148(%rsp), %rax
movq %rax, 272(%rsp)
leaq 144(%rsp), %rax
movq %rax, 280(%rsp)
leaq 232(%rsp), %rax
movq %rax, 288(%rsp)
leaq 224(%rsp), %rax
movq %rax, 296(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z13pattern2d_gpuiiiiiiPfS_, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_23:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.25:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_26
# %bb.27:
movq 112(%rsp), %rsi
movq 104(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_28
# %bb.29:
movq %r15, 40(%rsp) # 8-byte Spill
andl $-16, %r13d
negl %r13d
movq 32(%rsp), %rax # 8-byte Reload
leal (%rax,%r13), %ecx
addl $-2, %ecx
# kill: def $eax killed $eax killed $rax
subl %ecx, %eax
addl $-2, %eax
cmpl %eax, 140(%rsp) # 4-byte Folded Reload
jle .LBB2_38
# %bb.30: # %.preheader.lr.ph.i144
movq 16(%rsp), %rcx # 8-byte Reload
decl %ecx
movslq %ecx, %r15
movslq %eax, %rdi
leaq 1(%rdi), %rax
movq 48(%rsp), %rdx # 8-byte Reload
imulq %rdx, %rax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
addq $4, %r13
leaq (,%rdx,4), %rax
movq %rax, 64(%rsp) # 8-byte Spill
leaq -1(%rdi), %rax
imulq %rdx, %rax
leaq (%rcx,%rax,4), %r14
addq $4, %r14
decq %r15
movq %rdx, %r10
imulq %rdi, %r10
leaq (%rcx,%r10,4), %r11
addq $8, %r11
shlq $32, %rdx
movq %rdx, 56(%rsp) # 8-byte Spill
movq 104(%rsp), %rax # 8-byte Reload
leaq (%rax,%r10,4), %r12
addq $4, %r12
shlq $32, %r10
movq %r10, 24(%rsp) # 8-byte Spill
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
xorps %xmm4, %xmm4
jmp .LBB2_31
.p2align 4, 0x90
.LBB2_37: # %._crit_edge.i147
# in Loop: Header=BB2_31 Depth=1
movq 8(%rsp), %rdi # 8-byte Reload
incq %rdi
movq 64(%rsp), %rax # 8-byte Reload
addq %rax, %r13
addq %rax, %r14
addq %rax, %r11
movq 56(%rsp), %rcx # 8-byte Reload
addq %rcx, 24(%rsp) # 8-byte Folded Spill
addq %rax, %r12
cmpq 120(%rsp), %rdi # 8-byte Folded Reload
je .LBB2_38
.LBB2_31: # %.preheader.i145
# =>This Loop Header: Depth=1
# Child Loop BB2_33 Depth 2
movq %rdi, 8(%rsp) # 8-byte Spill
cmpl $3, 16(%rsp) # 4-byte Folded Reload
jl .LBB2_37
# %bb.32: # %.lr.ph.i149
# in Loop: Header=BB2_31 Depth=1
movq 24(%rsp), %rbp # 8-byte Reload
xorl %ebx, %ebx
movq %r11, 72(%rsp) # 8-byte Spill
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_35: # %call.sqrt273
# in Loop: Header=BB2_33 Depth=2
callq sqrtf
xorps %xmm4, %xmm4
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 72(%rsp), %r11 # 8-byte Reload
.LBB2_36: # %.split272
# in Loop: Header=BB2_33 Depth=2
movss %xmm0, (%r12,%rbx,4)
incq %rbx
movabsq $4294967296, %rax # imm = 0x100000000
addq %rax, %rbp
cmpq %rbx, %r15
je .LBB2_37
.LBB2_33: # Parent Loop BB2_31 Depth=1
# => This Inner Loop Header: Depth=2
movss -4(%r11,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rbp, %rax
sarq $30, %rax
movq 80(%rsp), %rcx # 8-byte Reload
addss (%rcx,%rax), %xmm1
addss (%r11,%rbx,4), %xmm1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
subss %xmm0, %xmm1
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
andps %xmm3, %xmm0
ucomiss %xmm4, %xmm0
jb .LBB2_35
# %bb.34: # in Loop: Header=BB2_33 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB2_36
.LBB2_38: # %_Z13pattern2d_cpuiiiiiiPfS_.exit153
cmpl $3, 32(%rsp) # 4-byte Folded Reload
jl .LBB2_47
# %bb.39: # %.preheader.lr.ph.i154
movq 40(%rsp), %rcx # 8-byte Reload
andl $-32, %ecx
negl %ecx
movq 16(%rsp), %rdx # 8-byte Reload
leal (%rdx,%rcx), %eax
addl $-2, %eax
movl %edx, %ecx
subl %eax, %ecx
movslq %ecx, %rax
addl $-2, %ecx
movl %ecx, 64(%rsp) # 4-byte Spill
leaq -2(%rax), %rcx
decl %edx
movl %edx, 56(%rsp) # 4-byte Spill
movslq %edx, %r13
subq %rcx, %r13
leaq -8(,%rax,4), %rcx
movq 48(%rsp), %rsi # 8-byte Reload
leaq (%rcx,%rsi,8), %r15
movq 80(%rsp), %rdx # 8-byte Reload
addq %rdx, %r15
leaq (,%rsi,4), %r9
movq %r9, 40(%rsp) # 8-byte Spill
leaq (%rdx,%rax,4), %r14
addq $-8, %r14
leaq (%rcx,%rsi,4), %r10
addq %rdx, %r10
addq %rsi, %rax
addq $-2, %rax
movabsq $4294967296, %rcx # imm = 0x100000000
addl %eax, %ecx
decl %ecx
shlq $32, %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
shlq $32, %rsi
movq %rsi, 48(%rsp) # 8-byte Spill
movq 104(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
movl $1, %esi
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
xorps %xmm4, %xmm4
jmp .LBB2_40
.p2align 4, 0x90
.LBB2_46: # %._crit_edge.i157
# in Loop: Header=BB2_40 Depth=1
movq 24(%rsp), %rsi # 8-byte Reload
incq %rsi
movq 40(%rsp), %rax # 8-byte Reload
addq %rax, %r15
addq %rax, %r14
addq %rax, %r10
movq 8(%rsp), %rcx # 8-byte Reload
addq 48(%rsp), %rcx # 8-byte Folded Reload
movq %rcx, 8(%rsp) # 8-byte Spill
addq %rax, %r12
cmpq 120(%rsp), %rsi # 8-byte Folded Reload
je .LBB2_47
.LBB2_40: # %.preheader.i155
# =>This Loop Header: Depth=1
# Child Loop BB2_42 Depth 2
movq %rsi, 24(%rsp) # 8-byte Spill
movl 56(%rsp), %eax # 4-byte Reload
cmpl 64(%rsp), %eax # 4-byte Folded Reload
jle .LBB2_46
# %bb.41: # %.lr.ph.i159
# in Loop: Header=BB2_40 Depth=1
movq 8(%rsp), %rbp # 8-byte Reload
xorl %ebx, %ebx
movq %r10, 72(%rsp) # 8-byte Spill
jmp .LBB2_42
.p2align 4, 0x90
.LBB2_44: # %call.sqrt275
# in Loop: Header=BB2_42 Depth=2
callq sqrtf
xorps %xmm4, %xmm4
movaps .LCPI2_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI2_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 72(%rsp), %r10 # 8-byte Reload
.LBB2_45: # %.split274
# in Loop: Header=BB2_42 Depth=2
movss %xmm0, (%r12,%rbx,4)
incq %rbx
movabsq $4294967296, %rax # imm = 0x100000000
addq %rax, %rbp
cmpq %rbx, %r13
je .LBB2_46
.LBB2_42: # Parent Loop BB2_40 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r10,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rbp, %rax
sarq $30, %rax
movq 80(%rsp), %rcx # 8-byte Reload
addss (%rcx,%rax), %xmm1
addss 4(%r10,%rbx,4), %xmm1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
subss %xmm0, %xmm1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
andps %xmm3, %xmm0
ucomiss %xmm4, %xmm0
jb .LBB2_44
# %bb.43: # in Loop: Header=BB2_42 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB2_45
.LBB2_47: # %_Z13pattern2d_cpuiiiiiiPfS_.exit163
movq 104(%rsp), %r10 # 8-byte Reload
movss (%r10), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 168(%rsp), %r15 # 8-byte Reload
subss (%r15), %xmm2
andps .LCPI2_1(%rip), %xmm2
movq 32(%rsp), %rax # 8-byte Reload
testl %eax, %eax
jle .LBB2_48
# %bb.49: # %.preheader.lr.ph
movl %eax, %eax
movq 16(%rsp), %r11 # 8-byte Reload
movl %r11d, %ecx
xorl %edx, %edx
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
xorl %esi, %esi
movaps %xmm2, %xmm1
xorl %ebp, %ebp
xorl %ebx, %ebx
movl 4(%rsp), %r14d # 4-byte Reload
jmp .LBB2_50
.p2align 4, 0x90
.LBB2_51: # in Loop: Header=BB2_50 Depth=1
movaps %xmm1, %xmm2
.LBB2_52: # %._crit_edge
# in Loop: Header=BB2_50 Depth=1
incq %rsi
addl %r11d, %edx
movaps %xmm2, %xmm1
cmpq %rax, %rsi
je .LBB2_53
.LBB2_50: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_58 Depth 2
testl %r11d, %r11d
jle .LBB2_51
# %bb.57: # %.lr.ph
# in Loop: Header=BB2_50 Depth=1
movl %edx, %r8d
leaq (%r15,%r8,4), %rdi
leaq (%r10,%r8,4), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_58: # Parent Loop BB2_50 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r8,%r9,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rdi,%r9,4), %xmm2
andps %xmm0, %xmm2
ucomiss %xmm1, %xmm2
cmoval %r9d, %ebx
cmoval %esi, %ebp
maxss %xmm1, %xmm2
incq %r9
movaps %xmm2, %xmm1
cmpq %r9, %rcx
jne .LBB2_58
jmp .LBB2_52
.LBB2_48:
xorl %ebx, %ebx
xorl %ebp, %ebp
movl 4(%rsp), %r14d # 4-byte Reload
.LBB2_53: # %._crit_edge181
movaps %xmm2, 80(%rsp) # 16-byte Spill
movq 128(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_54
# %bb.59:
movq %r15, %rdi
callq free
movq 112(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_60
# %bb.61:
movaps 80(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movl 136(%rsp), %esi # 4-byte Reload
movl %r14d, %edx
movl %ebx, %ecx
movl %ebp, %r8d
movb $1, %al
callq printf
xorl %r12d, %r12d
jmp .LBB2_62
.LBB2_3:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.1, %edx
jmp .LBB2_4
.LBB2_6:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.2, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_17:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $.L.str.3, %edx
.LBB2_4:
movl 4(%rsp), %ecx # 4-byte Reload
movl %r12d, %r8d
xorl %eax, %eax
callq fprintf
jmp .LBB2_62
.LBB2_19:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_24:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_26:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_28:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
movl 4(%rsp), %edx # 4-byte Reload
jmp .LBB2_56
.LBB2_54:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
jmp .LBB2_55
.LBB2_60:
movl %eax, %r12d
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
.LBB2_55:
movl %r14d, %edx
.LBB2_56:
movl %r12d, %ecx
xorl %eax, %eax
callq fprintf
.LBB2_62:
movl %r12d, %eax
addq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9pattern2diiPfS_ii, .Lfunc_end2-_Z9pattern2diiPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13pattern2d_gpuiiiiiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13pattern2d_gpuiiiiiiPfS_,@object # @_Z13pattern2d_gpuiiiiiiPfS_
.section .rodata,"a",@progbits
.globl _Z13pattern2d_gpuiiiiiiPfS_
.p2align 3, 0x0
_Z13pattern2d_gpuiiiiiiPfS_:
.quad _Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.size _Z13pattern2d_gpuiiiiiiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s %d, status = %d\nInsufficient GPU memory?\n"
.size .L.str, 45
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cannot malloc input memory on GPU by process"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cannot copy data from host to gpu by process %d, status = %d\n"
.size .L.str.2, 62
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cannot malloc output memory on GPU by process"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cannot erase output memory on GPU by process %d, status = %d\n"
.size .L.str.4, 62
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cannot execute CUDA kernel by process %d, status = %d\n"
.size .L.str.5, 55
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Cannot synchronize thread by process %d, status = %d\n"
.size .L.str.6, 54
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Cannot copy data from gpu to host by process %d, status = %d\n"
.size .L.str.7, 62
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Cannot free device input memory by process %d, status = %d\n"
.size .L.str.8, 60
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Cannot free device output memory by process %d, status = %d\n"
.size .L.str.9, 61
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Step %d result abs max diff by process %d = %f @ (%d,%d)\n"
.size .L.str.10, 58
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13pattern2d_gpuiiiiiiPfS_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__pattern2d_gpuiiiiiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13pattern2d_gpuiiiiiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <cstdlib>
#include<chrono>
int main(void) {
double gammaEulera = 0.;
double N = 1000000;;
auto start = std::chrono::high_resolution_clock::now();
for (int i = 1; i < N; i++)
gammaEulera = gammaEulera + (1. / (double)i);
gammaEulera = gammaEulera - log(N);
auto finish = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> elapsed = finish - start;
printf("Przyblizona wartosc eulera CPU wynosi %f \n",gammaEulera );
printf("Czas wynosi %f",elapsed.count());
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <cstdlib>
#include<chrono>
int main(void) {
double gammaEulera = 0.;
double N = 1000000;;
auto start = std::chrono::high_resolution_clock::now();
for (int i = 1; i < N; i++)
gammaEulera = gammaEulera + (1. / (double)i);
gammaEulera = gammaEulera - log(N);
auto finish = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> elapsed = finish - start;
printf("Przyblizona wartosc eulera CPU wynosi %f \n",gammaEulera );
printf("Czas wynosi %f",elapsed.count());
return 0;
} | .file "tmpxft_0003cafb_00000000-6_euler-CPU.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Przyblizona wartosc eulera CPU wynosi %f \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Czas wynosi %f"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1, %eax
pxor %xmm0, %xmm0
movsd .LC1(%rip), %xmm3
.L4:
pxor %xmm2, %xmm2
cvtsi2sdl %eax, %xmm2
movapd %xmm3, %xmm1
divsd %xmm2, %xmm1
addsd %xmm1, %xmm0
addl $1, %eax
cmpl $1000000, %eax
jne .L4
subsd .LC2(%rip), %xmm0
movsd %xmm0, (%rsp)
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movapd %xmm0, %xmm4
divsd .LC3(%rip), %xmm4
movsd %xmm4, 8(%rsp)
movsd (%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3768:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long -1718616160
.long 1076601226
.align 8
.LC3:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <cstdlib>
#include<chrono>
int main(void) {
double gammaEulera = 0.;
double N = 1000000;;
auto start = std::chrono::high_resolution_clock::now();
for (int i = 1; i < N; i++)
gammaEulera = gammaEulera + (1. / (double)i);
gammaEulera = gammaEulera - log(N);
auto finish = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> elapsed = finish - start;
printf("Przyblizona wartosc eulera CPU wynosi %f \n",gammaEulera );
printf("Czas wynosi %f",elapsed.count());
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <cstdlib>
#include<chrono>
int main(void) {
double gammaEulera = 0.;
double N = 1000000;;
auto start = std::chrono::high_resolution_clock::now();
for (int i = 1; i < N; i++)
gammaEulera = gammaEulera + (1. / (double)i);
gammaEulera = gammaEulera - log(N);
auto finish = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> elapsed = finish - start;
printf("Przyblizona wartosc eulera CPU wynosi %f \n",gammaEulera );
printf("Czas wynosi %f",elapsed.count());
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <cstdlib>
#include<chrono>
int main(void) {
double gammaEulera = 0.;
double N = 1000000;;
auto start = std::chrono::high_resolution_clock::now();
for (int i = 1; i < N; i++)
gammaEulera = gammaEulera + (1. / (double)i);
gammaEulera = gammaEulera - log(N);
auto finish = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> elapsed = finish - start;
printf("Przyblizona wartosc eulera CPU wynosi %f \n",gammaEulera );
printf("Czas wynosi %f",elapsed.count());
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <cstdlib>
#include<chrono>
int main(void) {
double gammaEulera = 0.;
double N = 1000000;;
auto start = std::chrono::high_resolution_clock::now();
for (int i = 1; i < N; i++)
gammaEulera = gammaEulera + (1. / (double)i);
gammaEulera = gammaEulera - log(N);
auto finish = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> elapsed = finish - start;
printf("Przyblizona wartosc eulera CPU wynosi %f \n",gammaEulera );
printf("Czas wynosi %f",elapsed.count());
return 0;
} | .text
.file "euler-CPU.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0xc02ba18a998fffa0 # double -13.815510557964274
.LCPI0_2:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $999999, %ebp # imm = 0xF423F
callq _ZNSt6chrono3_V212system_clock3nowEv
movsd .LCPI0_0(%rip), %xmm3 # xmm3 = mem[0],zero
xorpd %xmm2, %xmm2
movq %rax, %rbx
movapd %xmm3, %xmm0
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movapd %xmm3, %xmm1
divsd %xmm0, %xmm1
addsd %xmm1, %xmm2
addsd %xmm3, %xmm0
decl %ebp
jne .LBB0_1
# %bb.2:
addsd .LCPI0_1(%rip), %xmm2
movsd %xmm2, 16(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_2(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $.L.str, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Przyblizona wartosc eulera CPU wynosi %f \n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Czas wynosi %f"
.size .L.str.1, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003cafb_00000000-6_euler-CPU.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Przyblizona wartosc eulera CPU wynosi %f \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Czas wynosi %f"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1, %eax
pxor %xmm0, %xmm0
movsd .LC1(%rip), %xmm3
.L4:
pxor %xmm2, %xmm2
cvtsi2sdl %eax, %xmm2
movapd %xmm3, %xmm1
divsd %xmm2, %xmm1
addsd %xmm1, %xmm0
addl $1, %eax
cmpl $1000000, %eax
jne .L4
subsd .LC2(%rip), %xmm0
movsd %xmm0, (%rsp)
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movapd %xmm0, %xmm4
divsd .LC3(%rip), %xmm4
movsd %xmm4, 8(%rsp)
movsd (%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3768:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long -1718616160
.long 1076601226
.align 8
.LC3:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "euler-CPU.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0xc02ba18a998fffa0 # double -13.815510557964274
.LCPI0_2:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $999999, %ebp # imm = 0xF423F
callq _ZNSt6chrono3_V212system_clock3nowEv
movsd .LCPI0_0(%rip), %xmm3 # xmm3 = mem[0],zero
xorpd %xmm2, %xmm2
movq %rax, %rbx
movapd %xmm3, %xmm0
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movapd %xmm3, %xmm1
divsd %xmm0, %xmm1
addsd %xmm1, %xmm2
addsd %xmm3, %xmm0
decl %ebp
jne .LBB0_1
# %bb.2:
addsd .LCPI0_1(%rip), %xmm2
movsd %xmm2, 16(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_2(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $.L.str, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Przyblizona wartosc eulera CPU wynosi %f \n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Czas wynosi %f"
.size .L.str.1, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernelBackprop1(float *delta_nabla_w,int w_off,float *activations,float *delta_nabla_b,int b_off) {
delta_nabla_w[w_off+(blockIdx.x*blockDim.x)+threadIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
//delta_nabla_w[w_off+(threadIdx.x*gridDim.x)+blockIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
} | code for sm_80
Function : _Z15kernelBackprop1PfiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IADD3 R4, R7, c[0x0][0x180], RZ ; /* 0x0000600007047a10 */
/* 0x001fcc0007ffe0ff */
/*0060*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x002fc800078e0009 */
/*0070*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe400078e0009 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fca00078e0200 */
/*00b0*/ IADD3 R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE.U32 R6, R0, R9, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0009 */
/*00d0*/ FMUL R9, R2, R5 ; /* 0x0000000502097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernelBackprop1(float *delta_nabla_w,int w_off,float *activations,float *delta_nabla_b,int b_off) {
delta_nabla_w[w_off+(blockIdx.x*blockDim.x)+threadIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
//delta_nabla_w[w_off+(threadIdx.x*gridDim.x)+blockIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
} | .file "tmpxft_00165639_00000000-6_kernelBackprop1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i
.type _Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i, @function
_Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movl %r8d, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15kernelBackprop1PfiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i, .-_Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i
.globl _Z15kernelBackprop1PfiS_S_i
.type _Z15kernelBackprop1PfiS_S_i, @function
_Z15kernelBackprop1PfiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15kernelBackprop1PfiS_S_i, .-_Z15kernelBackprop1PfiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15kernelBackprop1PfiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernelBackprop1PfiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernelBackprop1(float *delta_nabla_w,int w_off,float *activations,float *delta_nabla_b,int b_off) {
delta_nabla_w[w_off+(blockIdx.x*blockDim.x)+threadIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
//delta_nabla_w[w_off+(threadIdx.x*gridDim.x)+blockIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelBackprop1(float *delta_nabla_w,int w_off,float *activations,float *delta_nabla_b,int b_off) {
delta_nabla_w[w_off+(blockIdx.x*blockDim.x)+threadIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
//delta_nabla_w[w_off+(threadIdx.x*gridDim.x)+blockIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelBackprop1(float *delta_nabla_w,int w_off,float *activations,float *delta_nabla_b,int b_off) {
delta_nabla_w[w_off+(blockIdx.x*blockDim.x)+threadIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
//delta_nabla_w[w_off+(threadIdx.x*gridDim.x)+blockIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15kernelBackprop1PfiS_S_i
.globl _Z15kernelBackprop1PfiS_S_i
.p2align 8
.type _Z15kernelBackprop1PfiS_S_i,@function
_Z15kernelBackprop1PfiS_S_i:
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x34
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
s_load_b32 s4, s[0:1], 0x8
s_add_i32 s2, s15, s2
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_and_b32 s3, s8, 0xffff
s_mul_i32 s15, s15, s3
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, s15, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kernelBackprop1PfiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15kernelBackprop1PfiS_S_i, .Lfunc_end0-_Z15kernelBackprop1PfiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kernelBackprop1PfiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15kernelBackprop1PfiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelBackprop1(float *delta_nabla_w,int w_off,float *activations,float *delta_nabla_b,int b_off) {
delta_nabla_w[w_off+(blockIdx.x*blockDim.x)+threadIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
//delta_nabla_w[w_off+(threadIdx.x*gridDim.x)+blockIdx.x]=activations[threadIdx.x]*delta_nabla_b[b_off+blockIdx.x];
} | .text
.file "kernelBackprop1.hip"
.globl _Z30__device_stub__kernelBackprop1PfiS_S_i # -- Begin function _Z30__device_stub__kernelBackprop1PfiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__kernelBackprop1PfiS_S_i,@function
_Z30__device_stub__kernelBackprop1PfiS_S_i: # @_Z30__device_stub__kernelBackprop1PfiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15kernelBackprop1PfiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__kernelBackprop1PfiS_S_i, .Lfunc_end0-_Z30__device_stub__kernelBackprop1PfiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernelBackprop1PfiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15kernelBackprop1PfiS_S_i,@object # @_Z15kernelBackprop1PfiS_S_i
.section .rodata,"a",@progbits
.globl _Z15kernelBackprop1PfiS_S_i
.p2align 3, 0x0
_Z15kernelBackprop1PfiS_S_i:
.quad _Z30__device_stub__kernelBackprop1PfiS_S_i
.size _Z15kernelBackprop1PfiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15kernelBackprop1PfiS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__kernelBackprop1PfiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15kernelBackprop1PfiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15kernelBackprop1PfiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IADD3 R4, R7, c[0x0][0x180], RZ ; /* 0x0000600007047a10 */
/* 0x001fcc0007ffe0ff */
/*0060*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x002fc800078e0009 */
/*0070*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe400078e0009 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fca00078e0200 */
/*00b0*/ IADD3 R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE.U32 R6, R0, R9, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0009 */
/*00d0*/ FMUL R9, R2, R5 ; /* 0x0000000502097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15kernelBackprop1PfiS_S_i
.globl _Z15kernelBackprop1PfiS_S_i
.p2align 8
.type _Z15kernelBackprop1PfiS_S_i,@function
_Z15kernelBackprop1PfiS_S_i:
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x34
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
s_load_b32 s4, s[0:1], 0x8
s_add_i32 s2, s15, s2
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_and_b32 s3, s8, 0xffff
s_mul_i32 s15, s15, s3
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, s15, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kernelBackprop1PfiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15kernelBackprop1PfiS_S_i, .Lfunc_end0-_Z15kernelBackprop1PfiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kernelBackprop1PfiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15kernelBackprop1PfiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00165639_00000000-6_kernelBackprop1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i
.type _Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i, @function
_Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movl %r8d, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15kernelBackprop1PfiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i, .-_Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i
.globl _Z15kernelBackprop1PfiS_S_i
.type _Z15kernelBackprop1PfiS_S_i, @function
_Z15kernelBackprop1PfiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15kernelBackprop1PfiS_S_iPfiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15kernelBackprop1PfiS_S_i, .-_Z15kernelBackprop1PfiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15kernelBackprop1PfiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernelBackprop1PfiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelBackprop1.hip"
.globl _Z30__device_stub__kernelBackprop1PfiS_S_i # -- Begin function _Z30__device_stub__kernelBackprop1PfiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__kernelBackprop1PfiS_S_i,@function
_Z30__device_stub__kernelBackprop1PfiS_S_i: # @_Z30__device_stub__kernelBackprop1PfiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15kernelBackprop1PfiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__kernelBackprop1PfiS_S_i, .Lfunc_end0-_Z30__device_stub__kernelBackprop1PfiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernelBackprop1PfiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15kernelBackprop1PfiS_S_i,@object # @_Z15kernelBackprop1PfiS_S_i
.section .rodata,"a",@progbits
.globl _Z15kernelBackprop1PfiS_S_i
.p2align 3, 0x0
_Z15kernelBackprop1PfiS_S_i:
.quad _Z30__device_stub__kernelBackprop1PfiS_S_i
.size _Z15kernelBackprop1PfiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15kernelBackprop1PfiS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__kernelBackprop1PfiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15kernelBackprop1PfiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include "gMat.cuh"
#include <vector>
#include "mytime.h"
#include <functional>
#include <math.h>
#include <stdlib.h>
#include <string>
void manyMult(gMat& A, gMat& B, gMat& C,int iter,int mem){
for (int i=0; i!=iter; ++i){
prod(A,B,C,mem);
prod(A,C,B,mem);
}
}
void multstat(int mem, int row, int col){
std::cout << "multiplying " << row << " by "<< col <<" matrices.\n";
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop,0);
std::cout << "using "<< mem << " of "<<prop.sharedMemPerBlock << "shared memory\n";
int w=floor(sqrt(mem/2/sizeof(float)));
std::cout << "Tile sizes will be: "<< w<< " by "<< w << "\n";
std::cout << "This amounts to: " << w*w << " threads \n";
std::cout << ceil(row/ (float) w)*ceil(col/ (float) w) << " tiles will be used "<<std::endl;
}
int main(int argc, char *argv[]){
int w;
if ( argc >= 2) w=atoi(argv[1]);
else w=20;
int r=1000;
int c=1000;
gMat A=eye(r);
gMat B=randgMat(r,c);
gMat C=randgMat(r,c);
A.name="A";
B.name="B";
C.name="C";
int mem=2*w*w*sizeof(float);
auto mm=std::bind(manyMult,A,B,C,300,mem);
multstat(mem,r,c);
mm();
A.cleanup();
B.cleanup();
C.cleanup();
}
void test1(){
std::vector<float> adat={1,2,3,4};
std::vector<float> bdat={2,0,0,2,0,2};
std::vector<float> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};
gMat B{bdat,2,3};
gMat C{cdat,2,3};
std::cout <<"A:\n" << A << std::flush;
std::cout <<"B:\n" << B << std::flush;
int mem=8*sizeof(float);
prod(A,B,C,mem);
std::cout <<"C:\n" << C << std::flush;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include "gMat.cuh"
#include <vector>
#include "mytime.h"
#include <functional>
#include <math.h>
#include <stdlib.h>
#include <string>
void manyMult(gMat& A, gMat& B, gMat& C,int iter,int mem){
for (int i=0; i!=iter; ++i){
prod(A,B,C,mem);
prod(A,C,B,mem);
}
}
void multstat(int mem, int row, int col){
std::cout << "multiplying " << row << " by "<< col <<" matrices.\n";
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop,0);
std::cout << "using "<< mem << " of "<<prop.sharedMemPerBlock << "shared memory\n";
int w=floor(sqrt(mem/2/sizeof(float)));
std::cout << "Tile sizes will be: "<< w<< " by "<< w << "\n";
std::cout << "This amounts to: " << w*w << " threads \n";
std::cout << ceil(row/ (float) w)*ceil(col/ (float) w) << " tiles will be used "<<std::endl;
}
int main(int argc, char *argv[]){
int w;
if ( argc >= 2) w=atoi(argv[1]);
else w=20;
int r=1000;
int c=1000;
gMat A=eye(r);
gMat B=randgMat(r,c);
gMat C=randgMat(r,c);
A.name="A";
B.name="B";
C.name="C";
int mem=2*w*w*sizeof(float);
auto mm=std::bind(manyMult,A,B,C,300,mem);
multstat(mem,r,c);
mm();
A.cleanup();
B.cleanup();
C.cleanup();
}
void test1(){
std::vector<float> adat={1,2,3,4};
std::vector<float> bdat={2,0,0,2,0,2};
std::vector<float> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};
gMat B{bdat,2,3};
gMat C{cdat,2,3};
std::cout <<"A:\n" << A << std::flush;
std::cout <<"B:\n" << B << std::flush;
int mem=8*sizeof(float);
prod(A,B,C,mem);
std::cout <<"C:\n" << C << std::flush;
} | .file "tmpxft_001999a4_00000000-6_gMatTest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.globl _Z8manyMultR4gMatS0_S0_ii
.type _Z8manyMultR4gMatS0_S0_ii, @function
_Z8manyMultR4gMatS0_S0_ii:
.LFB5573:
.cfi_startproc
endbr64
testl %ecx, %ecx
je .L6
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %r8d, %r14d
movslq %ecx, %r15
movl $0, %ebx
.L3:
movl %r14d, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z4prodRK4gMatS1_RS_i@PLT
movl %r14d, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %rbp, %rdi
call _Z4prodRK4gMatS1_RS_i@PLT
addq $1, %rbx
cmpq %rbx, %r15
jne .L3
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE5573:
.size _Z8manyMultR4gMatS0_S0_ii, .-_Z8manyMultR4gMatS0_S0_ii
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5613:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5613:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "multiplying "
.LC1:
.string " by "
.LC2:
.string " matrices.\n"
.LC3:
.string "using "
.LC4:
.string " of "
.LC5:
.string "shared memory\n"
.LC9:
.string "Tile sizes will be: "
.LC10:
.string "\n"
.LC11:
.string "This amounts to: "
.LC12:
.string " threads \n"
.LC16:
.string " tiles will be used "
.text
.globl _Z8multstatiii
.type _Z8multstatiii, @function
_Z8multstatiii:
.LFB5574:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1040, %rsp
.cfi_def_cfa_offset 1088
movl %edi, %r12d
movl %esi, %ebp
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movl $12, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movl $4, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $11, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl $6, %edx
leaq .LC3(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movl $4, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 296(%rsp), %rsi
movq %r13, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movl $14, %edx
leaq .LC5(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %eax
shrl $31, %eax
addl %r12d, %eax
sarl %eax
cltq
shrq $2, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L26
sqrtsd %xmm0, %xmm0
.L16:
movapd %xmm0, %xmm3
movsd .LC18(%rip), %xmm1
movapd %xmm0, %xmm2
andpd %xmm1, %xmm2
movsd .LC7(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L17
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
andnpd %xmm0, %xmm1
movapd %xmm2, %xmm3
orpd %xmm1, %xmm3
.L17:
cvttsd2sil %xmm3, %r12d
movl $20, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movl $4, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC10(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $17, %edx
leaq .LC11(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
imull %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %edx
leaq .LC12(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm4, %xmm4
cvtsi2ssl %r12d, %xmm4
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
divss %xmm4, %xmm0
movaps %xmm0, %xmm1
movss .LC17(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC13(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L18
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC15(%rip), %xmm5
andps %xmm5, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L18:
movaps %xmm1, %xmm2
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
divss %xmm4, %xmm1
movaps %xmm1, %xmm0
movss .LC17(%rip), %xmm4
movaps %xmm1, %xmm3
andps %xmm4, %xmm3
movss .LC13(%rip), %xmm5
ucomiss %xmm3, %xmm5
jbe .L19
cvttss2sil %xmm1, %eax
pxor %xmm3, %xmm3
cvtsi2ssl %eax, %xmm3
cmpnless %xmm3, %xmm0
movss .LC15(%rip), %xmm5
andps %xmm5, %xmm0
addss %xmm3, %xmm0
andnps %xmm1, %xmm4
orps %xmm4, %xmm0
.L19:
mulss %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $20, %edx
leaq .LC16(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L28
cmpb $0, 56(%rbp)
je .L22
movzbl 67(%rbp), %esi
.L23:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call sqrt@PLT
jmp .L16
.L28:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L30
call _ZSt16__throw_bad_castv@PLT
.L30:
call __stack_chk_fail@PLT
.L22:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L23
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5574:
.size _Z8multstatiii, .-_Z8multstatiii
.section .text._ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED2Ev,"axG",@progbits,_ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED5Ev,comdat
.align 2
.weak _ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED2Ev
.type _ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED2Ev, @function
_ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED2Ev:
.LFB5604:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 120(%rdi), %rdi
leaq 136(%rbx), %rax
cmpq %rax, %rdi
je .L32
movq 136(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L32:
movq 72(%rbx), %rdi
leaq 88(%rbx), %rax
cmpq %rax, %rdi
je .L33
movq 88(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L33:
movq 24(%rbx), %rdi
leaq 40(%rbx), %rax
cmpq %rax, %rdi
je .L31
movq 40(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L31:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5604:
.size _ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED2Ev, .-_ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED2Ev
.weak _ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED1Ev
.set _ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED1Ev,_ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED2Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5636:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5636:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB5998:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L41
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L41:
ret
.cfi_endproc
.LFE5998:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .text._ZNSt12_Vector_baseIfSaIfEED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIfSaIfEED2Ev
.type _ZNSt12_Vector_baseIfSaIfEED2Ev, @function
_ZNSt12_Vector_baseIfSaIfEED2Ev:
.LFB6202:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L47
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L47:
ret
.cfi_endproc
.LFE6202:
.size _ZNSt12_Vector_baseIfSaIfEED2Ev, .-_ZNSt12_Vector_baseIfSaIfEED2Ev
.weak _ZNSt12_Vector_baseIfSaIfEED1Ev
.set _ZNSt12_Vector_baseIfSaIfEED1Ev,_ZNSt12_Vector_baseIfSaIfEED2Ev
.section .rodata.str1.1
.LC21:
.string "A:\n"
.LC22:
.string "B:\n"
.LC23:
.string "C:\n"
.text
.globl _Z5test1v
.type _Z5test1v, @function
_Z5test1v:
.LFB5610:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5610
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $288, %rsp
.cfi_def_cfa_offset 320
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbp
movq %rax, (%rsp)
leaq 16(%rax), %rax
movq %rax, 16(%rsp)
movabsq $4611686019492741120, %rcx
movq %rcx, 0(%rbp)
movabsq $4647714816524288000, %rbx
movq %rbx, 8(%rbp)
movq %rax, 8(%rsp)
movss .LC19(%rip), %xmm0
movss %xmm0, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movss %xmm0, 236(%rsp)
movl $0x00000000, 240(%rsp)
movss %xmm0, 244(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl $24, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbx
movq %rax, 32(%rsp)
leaq 24(%rax), %rax
movq %rax, 48(%rsp)
movdqa 224(%rsp), %xmm1
movups %xmm1, (%rbx)
movq 240(%rsp), %rdx
movq %rdx, 16(%rbx)
movq %rax, 40(%rsp)
movl $0x00000000, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movl $0x00000000, 236(%rsp)
movl $0x00000000, 240(%rsp)
movl $0x00000000, 244(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $24, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
jmp .L90
.L83:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L53:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L90:
movq %rax, %r12
movq %rax, 64(%rsp)
leaq 24(%rax), %rax
movq %rax, 80(%rsp)
movdqa 224(%rsp), %xmm2
movups %xmm2, (%r12)
movq 240(%rsp), %rdx
movq %rdx, 16(%r12)
movq %rax, 72(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $16, %edi
.LEHB4:
call _Znwm@PLT
.LEHE4:
jmp .L91
.L82:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L56:
movq %rsp, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L73
call __stack_chk_fail@PLT
.L91:
movq %rax, 96(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu 0(%rbp), %xmm3
movups %xmm3, (%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $0, %r8d
movl $2, %ecx
movl $2, %edx
.LEHB5:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE5:
jmp .L92
.L84:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L59:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L56
.L92:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L60
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L60:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB6:
call _Znwm@PLT
.LEHE6:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%rbx), %xmm4
movups %xmm4, (%rax)
movq 16(%rbx), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 176(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB7:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE7:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L61
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L61:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB8:
call _Znwm@PLT
.LEHE8:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%r12), %xmm5
movups %xmm5, (%rax)
movq 16(%r12), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 224(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB9:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE9:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L62
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L62:
movl $3, %edx
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB10:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 128(%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZlsRSoR4gMat@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $3, %edx
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 176(%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZlsRSoR4gMat@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 224(%rsp), %rdx
leaq 176(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $32, %ecx
call _Z4prodRK4gMatS1_RS_i@PLT
movl $3, %edx
leaq .LC23(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 224(%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZlsRSoR4gMat@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE10:
movq 240(%rsp), %rdi
leaq 256(%rsp), %rax
cmpq %rax, %rdi
je .L63
movq 256(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L63:
movq 192(%rsp), %rdi
leaq 208(%rsp), %rax
cmpq %rax, %rdi
je .L64
movq 208(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L64:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L65
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L65:
movl $24, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movl $24, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $16, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L93
addq $288, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L67:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L59
.L77:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L69:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L67
.L79:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L71:
leaq 192(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L69
.L81:
endbr64
movq %rax, %rbx
leaq 240(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L71
.L80:
endbr64
movq %rax, %rbx
jmp .L71
.L78:
endbr64
movq %rax, %rbx
jmp .L69
.L76:
endbr64
movq %rax, %rbx
jmp .L67
.L73:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5610:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA5610:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5610-.LLSDACSB5610
.LLSDACSB5610:
.uleb128 .LEHB0-.LFB5610
.uleb128 .LEHE0-.LEHB0
.uleb128 .L83-.LFB5610
.uleb128 0
.uleb128 .LEHB1-.LFB5610
.uleb128 .LEHE1-.LEHB1
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.uleb128 0
.uleb128 .LEHB2-.LFB5610
.uleb128 .LEHE2-.LEHB2
.uleb128 .L84-.LFB5610
.uleb128 0
.uleb128 .LEHB3-.LFB5610
.uleb128 .LEHE3-.LEHB3
.uleb128 0
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.uleb128 .LEHE4-.LEHB4
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.uleb128 0
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.uleb128 .LEHE5-.LEHB5
.uleb128 .L75-.LFB5610
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.uleb128 .LEHE6-.LEHB6
.uleb128 .L78-.LFB5610
.uleb128 0
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.uleb128 .LEHE7-.LEHB7
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.uleb128 .LEHE8-.LEHB8
.uleb128 .L80-.LFB5610
.uleb128 0
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.uleb128 .LEHE9-.LEHB9
.uleb128 .L79-.LFB5610
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.uleb128 .LEHE10-.LEHB10
.uleb128 .L81-.LFB5610
.uleb128 0
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.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE5610:
.text
.size _Z5test1v, .-_Z5test1v
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag:
.LFB6246:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L101
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L97
movzbl (%rsi), %eax
movb %al, (%rdi)
.L98:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L102
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L96:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L98
.L97:
testq %rdx, %rdx
je .L98
jmp .L96
.L102:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6246:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.section .rodata.str1.1
.LC24:
.string "A"
.LC25:
.string "B"
.LC26:
.string "C"
.text
.globl main
.type main, @function
main:
.LFB5575:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5575
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $320, %rsp
.cfi_def_cfa_offset 336
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
movl $20, %ebx
cmpl $1, %edi
jg .L126
.L104:
movq %rsp, %rdi
movl $1000, %esi
.LEHB12:
call _Z3eyei@PLT
.LEHE12:
leaq 48(%rsp), %rdi
movl $1000, %edx
movl $1000, %esi
.LEHB13:
call _Z8randgMatii@PLT
.LEHE13:
jmp .L127
.L126:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L104
.L127:
leaq 96(%rsp), %rdi
movl $1000, %edx
movl $1000, %esi
.LEHB14:
call _Z8randgMatii@PLT
.LEHE14:
leaq 16(%rsp), %rdi
leaq .LC24(%rip), %rsi
.LEHB15:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKc@PLT
leaq 64(%rsp), %rdi
leaq .LC25(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKc@PLT
leaq 112(%rsp), %rdi
leaq .LC26(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKc@PLT
imull %ebx, %ebx
sall $3, %ebx
leaq _Z8manyMultR4gMatS0_S0_ii(%rip), %rax
movq %rax, 144(%rsp)
movl %ebx, 152(%rsp)
movl $300, 156(%rsp)
movq 96(%rsp), %rax
movq %rax, 160(%rsp)
movl 104(%rsp), %eax
movl %eax, 168(%rsp)
movl 108(%rsp), %eax
movl %eax, 172(%rsp)
leaq 192(%rsp), %rax
movq %rax, 176(%rsp)
movq 112(%rsp), %rsi
movq %rsi, %rdx
addq 120(%rsp), %rdx
leaq 176(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.LEHE15:
movq 48(%rsp), %rax
movq %rax, 208(%rsp)
movl 56(%rsp), %eax
movl %eax, 216(%rsp)
movl 60(%rsp), %eax
movl %eax, 220(%rsp)
leaq 240(%rsp), %rax
movq %rax, 224(%rsp)
movq 64(%rsp), %rsi
movq %rsi, %rdx
addq 72(%rsp), %rdx
leaq 224(%rsp), %rdi
.LEHB16:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.LEHE16:
jmp .L128
.L121:
endbr64
movq %rax, %rbx
leaq 176(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L107:
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L111:
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L112:
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
je .L113
call __stack_chk_fail@PLT
.L128:
movq (%rsp), %rax
movq %rax, 256(%rsp)
movl 8(%rsp), %eax
movl %eax, 264(%rsp)
movl 12(%rsp), %eax
movl %eax, 268(%rsp)
leaq 288(%rsp), %rax
movq %rax, 272(%rsp)
movq 16(%rsp), %rsi
movq %rsi, %rdx
addq 24(%rsp), %rdx
leaq 272(%rsp), %rdi
.LEHB17:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.LEHE17:
jmp .L129
.L120:
endbr64
movq %rax, %rbx
leaq 224(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 176(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L107
.L129:
movl $1000, %edx
movl $1000, %esi
movl %ebx, %edi
.LEHB18:
call _Z8multstatiii
leaq 160(%rsp), %rdx
leaq 208(%rsp), %rsi
leaq 256(%rsp), %rdi
movl 152(%rsp), %r8d
movl 156(%rsp), %ecx
call *144(%rsp)
movq %rsp, %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 48(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 96(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
.LEHE18:
leaq 152(%rsp), %rdi
call _ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED2Ev
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L130
movl $0, %eax
addq $320, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L119:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 152(%rsp), %rdi
call _ZNSt11_Tuple_implILm0EJ4gMatS0_S0_iiEED2Ev
jmp .L107
.L118:
endbr64
movq %rax, %rbx
jmp .L107
.L117:
endbr64
movq %rax, %rbx
jmp .L111
.L116:
endbr64
movq %rax, %rbx
jmp .L112
.L113:
movq %rbx, %rdi
.LEHB19:
call _Unwind_Resume@PLT
.LEHE19:
.L130:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5575:
.section .gcc_except_table
.LLSDA5575:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5575-.LLSDACSB5575
.LLSDACSB5575:
.uleb128 .LEHB12-.LFB5575
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.uleb128 .LEHB13-.LFB5575
.uleb128 .LEHE13-.LEHB13
.uleb128 .L116-.LFB5575
.uleb128 0
.uleb128 .LEHB14-.LFB5575
.uleb128 .LEHE14-.LEHB14
.uleb128 .L117-.LFB5575
.uleb128 0
.uleb128 .LEHB15-.LFB5575
.uleb128 .LEHE15-.LEHB15
.uleb128 .L118-.LFB5575
.uleb128 0
.uleb128 .LEHB16-.LFB5575
.uleb128 .LEHE16-.LEHB16
.uleb128 .L121-.LFB5575
.uleb128 0
.uleb128 .LEHB17-.LFB5575
.uleb128 .LEHE17-.LEHB17
.uleb128 .L120-.LFB5575
.uleb128 0
.uleb128 .LEHB18-.LFB5575
.uleb128 .LEHE18-.LEHB18
.uleb128 .L119-.LFB5575
.uleb128 0
.uleb128 .LEHB19-.LFB5575
.uleb128 .LEHE19-.LEHB19
.uleb128 0
.uleb128 0
.LLSDACSE5575:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1127219200
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1258291200
.align 4
.LC15:
.long 1065353216
.set .LC17,.LC18+4
.section .rodata.cst8
.align 8
.LC18:
.long -1
.long 2147483647
.section .rodata.cst4
.align 4
.LC19:
.long 1073741824
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include "gMat.cuh"
#include <vector>
#include "mytime.h"
#include <functional>
#include <math.h>
#include <stdlib.h>
#include <string>
void manyMult(gMat& A, gMat& B, gMat& C,int iter,int mem){
for (int i=0; i!=iter; ++i){
prod(A,B,C,mem);
prod(A,C,B,mem);
}
}
void multstat(int mem, int row, int col){
std::cout << "multiplying " << row << " by "<< col <<" matrices.\n";
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop,0);
std::cout << "using "<< mem << " of "<<prop.sharedMemPerBlock << "shared memory\n";
int w=floor(sqrt(mem/2/sizeof(float)));
std::cout << "Tile sizes will be: "<< w<< " by "<< w << "\n";
std::cout << "This amounts to: " << w*w << " threads \n";
std::cout << ceil(row/ (float) w)*ceil(col/ (float) w) << " tiles will be used "<<std::endl;
}
int main(int argc, char *argv[]){
int w;
if ( argc >= 2) w=atoi(argv[1]);
else w=20;
int r=1000;
int c=1000;
gMat A=eye(r);
gMat B=randgMat(r,c);
gMat C=randgMat(r,c);
A.name="A";
B.name="B";
C.name="C";
int mem=2*w*w*sizeof(float);
auto mm=std::bind(manyMult,A,B,C,300,mem);
multstat(mem,r,c);
mm();
A.cleanup();
B.cleanup();
C.cleanup();
}
void test1(){
std::vector<float> adat={1,2,3,4};
std::vector<float> bdat={2,0,0,2,0,2};
std::vector<float> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};
gMat B{bdat,2,3};
gMat C{cdat,2,3};
std::cout <<"A:\n" << A << std::flush;
std::cout <<"B:\n" << B << std::flush;
int mem=8*sizeof(float);
prod(A,B,C,mem);
std::cout <<"C:\n" << C << std::flush;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include "gMat.cuh"
#include <vector>
#include "mytime.h"
#include <functional>
#include <math.h>
#include <stdlib.h>
#include <string>
void manyMult(gMat& A, gMat& B, gMat& C,int iter,int mem){
for (int i=0; i!=iter; ++i){
prod(A,B,C,mem);
prod(A,C,B,mem);
}
}
void multstat(int mem, int row, int col){
std::cout << "multiplying " << row << " by "<< col <<" matrices.\n";
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop,0);
std::cout << "using "<< mem << " of "<<prop.sharedMemPerBlock << "shared memory\n";
int w=floor(sqrt(mem/2/sizeof(float)));
std::cout << "Tile sizes will be: "<< w<< " by "<< w << "\n";
std::cout << "This amounts to: " << w*w << " threads \n";
std::cout << ceil(row/ (float) w)*ceil(col/ (float) w) << " tiles will be used "<<std::endl;
}
int main(int argc, char *argv[]){
int w;
if ( argc >= 2) w=atoi(argv[1]);
else w=20;
int r=1000;
int c=1000;
gMat A=eye(r);
gMat B=randgMat(r,c);
gMat C=randgMat(r,c);
A.name="A";
B.name="B";
C.name="C";
int mem=2*w*w*sizeof(float);
auto mm=std::bind(manyMult,A,B,C,300,mem);
multstat(mem,r,c);
mm();
A.cleanup();
B.cleanup();
C.cleanup();
}
void test1(){
std::vector<float> adat={1,2,3,4};
std::vector<float> bdat={2,0,0,2,0,2};
std::vector<float> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};
gMat B{bdat,2,3};
gMat C{cdat,2,3};
std::cout <<"A:\n" << A << std::flush;
std::cout <<"B:\n" << B << std::flush;
int mem=8*sizeof(float);
prod(A,B,C,mem);
std::cout <<"C:\n" << C << std::flush;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include "gMat.cuh"
#include <vector>
#include "mytime.h"
#include <functional>
#include <math.h>
#include <stdlib.h>
#include <string>
void manyMult(gMat& A, gMat& B, gMat& C,int iter,int mem){
for (int i=0; i!=iter; ++i){
prod(A,B,C,mem);
prod(A,C,B,mem);
}
}
void multstat(int mem, int row, int col){
std::cout << "multiplying " << row << " by "<< col <<" matrices.\n";
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop,0);
std::cout << "using "<< mem << " of "<<prop.sharedMemPerBlock << "shared memory\n";
int w=floor(sqrt(mem/2/sizeof(float)));
std::cout << "Tile sizes will be: "<< w<< " by "<< w << "\n";
std::cout << "This amounts to: " << w*w << " threads \n";
std::cout << ceil(row/ (float) w)*ceil(col/ (float) w) << " tiles will be used "<<std::endl;
}
int main(int argc, char *argv[]){
int w;
if ( argc >= 2) w=atoi(argv[1]);
else w=20;
int r=1000;
int c=1000;
gMat A=eye(r);
gMat B=randgMat(r,c);
gMat C=randgMat(r,c);
A.name="A";
B.name="B";
C.name="C";
int mem=2*w*w*sizeof(float);
auto mm=std::bind(manyMult,A,B,C,300,mem);
multstat(mem,r,c);
mm();
A.cleanup();
B.cleanup();
C.cleanup();
}
void test1(){
std::vector<float> adat={1,2,3,4};
std::vector<float> bdat={2,0,0,2,0,2};
std::vector<float> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};
gMat B{bdat,2,3};
gMat C{cdat,2,3};
std::cout <<"A:\n" << A << std::flush;
std::cout <<"B:\n" << B << std::flush;
int mem=8*sizeof(float);
prod(A,B,C,mem);
std::cout <<"C:\n" << C << std::flush;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
float *elements;
} Matrix;
/* Thread block size */
#define TILE_WIDTH 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const float* Md, const float* Nd, float* Pd, const int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
//Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; m++) {
// Coolaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; k++) Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
/**/
void test(const Matrix C);
/**/
int main(int argc, char* argv[])
{
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(float)*size*size;
h_A.width = size;
h_B.width = size;
h_C.width = size;
/* Allocate host memory */
h_A.elements = (float*)malloc(full_size);
h_B.elements = (float*)malloc(full_size);
h_C.elements = (float*)malloc(full_size);
/**/
for(i=0;i<size*size;++i){ scanf("%f", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%f", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;
d_B.width = size;
d_C.width = size;
cudaMalloc(&d_A.elements, full_size);
cudaMalloc(&d_B.elements, full_size);
cudaMalloc(&d_C.elements, full_size);
cudaEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
cudaMemcpy(d_A.elements, h_A.elements, full_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B.elements, h_B.elements, full_size, cudaMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A.elements, d_B.elements, d_C.elements,d_A.width);
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_C.elements, d_C.elements, full_size, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C)
{
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%4.1f ", C.elements[i*C.width+j]);
printf("\n");
}
} | code for sm_80
Function : _Z6MatMulPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ MOV R14, c[0x0][0x178] ; /* 0x00005e00000e7a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0080*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ea20000002100 */
/*0090*/ LEA R16, R3, R0, 0x1 ; /* 0x0000000003107211 */
/* 0x001fca00078e08ff */
/*00a0*/ @!P0 BRA 0x730 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*00b0*/ LEA.HI R2, R14, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e000e027a11 */
/* 0x000fe200078f08ff */
/*00c0*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*00d0*/ SHF.L.U32 R18, R0, 0x3, RZ ; /* 0x0000000300127819 */
/* 0x000fe200000006ff */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.R.S32.HI R22, RZ, 0x1, R2 ; /* 0x00000001ff167819 */
/* 0x000fe40000011402 */
/*0100*/ SHF.L.U32 R21, R14, 0x1, RZ ; /* 0x000000010e157819 */
/* 0x000fe200000006ff */
/*0110*/ IMAD R18, R13, 0x4, R18 ; /* 0x000000040d127824 */
/* 0x004fe200078e0212 */
/*0120*/ IADD3 R2, R22.reuse, -0x1, RZ ; /* 0xffffffff16027810 */
/* 0x040fe40007ffe0ff */
/*0130*/ LOP3.LUT R17, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316117812 */
/* 0x000fc400078ec0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0150*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f05270 */
/*0160*/ @!P1 BRA 0x560 ; /* 0x000003f000009947 */
/* 0x000fea0003800000 */
/*0170*/ MOV R20, 0x4 ; /* 0x0000000400147802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R15, R0, c[0x0][0x178], R13.reuse ; /* 0x00005e00000f7a24 */
/* 0x100fe200078e020d */
/*0190*/ IADD3 R22, -R22, R17, RZ ; /* 0x0000001116167210 */
/* 0x000fe20007ffe1ff */
/*01a0*/ IMAD R3, R16, c[0x0][0x178], R13 ; /* 0x00005e0010037a24 */
/* 0x000fe200078e020d */
/*01b0*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA R15, R12, R15, 0x1 ; /* 0x0000000f0c0f7211 */
/* 0x002fe200078e08ff */
/*01e0*/ IMAD.WIDE R2, R3, R20, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0214 */
/*01f0*/ IMAD.WIDE R4, R15, R20, c[0x0][0x168] ; /* 0x00005a000f047625 */
/* 0x000fe200078e0214 */
/*0200*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IMAD.WIDE R10, R21, 0x4, R4 ; /* 0x00000004150a7825 */
/* 0x000fc600078e0204 */
/*0230*/ STS [R18], R23 ; /* 0x0000001712007388 */
/* 0x004fe80000000800 */
/*0240*/ STS [R18+0x10], R25 ; /* 0x0000101912007388 */
/* 0x008fe80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS R8, [R13.X4+0x10] ; /* 0x000010000d087984 */
/* 0x000fe80000004800 */
/*0270*/ LDS R26, [R13.X4+0x18] ; /* 0x000018000d1a7984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ LDG.E R29, [R2.64+0x8] ; /* 0x00000804021d7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FFMA R6, R8, R6, R9 ; /* 0x0000000608067223 */
/* 0x001fc40000000009 */
/*02d0*/ IMAD.WIDE R8, R21, 0x4, R10 ; /* 0x0000000415087825 */
/* 0x000fe200078e020a */
/*02e0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R18+0x10], R28 ; /* 0x0000101c12007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R23, [R13.X4+0x10] ; /* 0x000010000d177984 */
/* 0x000fe80000004800 */
/*0320*/ LDS R24, [R13.X4+0x18] ; /* 0x000018000d187984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e280000008a00 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ LDG.E R25, [R2.64+0x10] ; /* 0x0000100402197981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ee2000c1e1900 */
/*0370*/ FFMA R27, R26, R7, R6 ; /* 0x000000071a1b7223 */
/* 0x000fc60000000006 */
/*0380*/ STS [R18], R25 ; /* 0x0000001912007388 */
/* 0x004fe80000000800 */
/*0390*/ STS [R18+0x10], R11 ; /* 0x0000100b12007388 */
/* 0x0083e80000000800 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03b0*/ IMAD.WIDE R10, R21, 0x4, R8 ; /* 0x00000004150a7825 */
/* 0x002fca00078e0208 */
/*03c0*/ LDS R25, [R13.X4+0x10] ; /* 0x000010000d197984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R26, [R13.X4+0x18] ; /* 0x000018000d1a7984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e680000008a00 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0400*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R29, [R2.64+0x18] ; /* 0x00001804021d7981 */
/* 0x000722000c1e1900 */
/*0420*/ FFMA R27, R23, R4, R27 ; /* 0x00000004171b7223 */
/* 0x001fe2000000001b */
/*0430*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fc40007ffe0ff */
/*0440*/ LEA R15, R14, R15, 0x3 ; /* 0x0000000f0e0f7211 */
/* 0x000fe200078e18ff */
/*0450*/ FFMA R5, R24, R5, R27 ; /* 0x0000000518057223 */
/* 0x000fc8000000001b */
/*0460*/ FFMA R5, R25, R6, R5 ; /* 0x0000000619057223 */
/* 0x002fe20000000005 */
/*0470*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x008fe20007f5e0ff */
/*0480*/ IMAD.IADD R6, R22, 0x1, R19 ; /* 0x0000000116067824 */
/* 0x000fe400078e0213 */
/*0490*/ FFMA R5, R26, R7, R5 ; /* 0x000000071a057223 */
/* 0x000fe20000000005 */
/*04a0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*04b0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*04c0*/ STS [R18+0x10], R10 ; /* 0x0000100a12007388 */
/* 0x004fe80000000800 */
/*04d0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x010fe80000000800 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04f0*/ LDS R23, [R13.X4+0x10] ; /* 0x000010000d177984 */
/* 0x000fe80000004800 */
/*0500*/ LDS.64 R8, [R0.X8] ; /* 0x0000000000087984 */
/* 0x000e280000008a00 */
/*0510*/ LDS R4, [R13.X4+0x18] ; /* 0x000018000d047984 */
/* 0x000e620000004800 */
/*0520*/ FFMA R5, R23, R8, R5 ; /* 0x0000000817057223 */
/* 0x001fc80000000005 */
/*0530*/ FFMA R9, R4, R9, R5 ; /* 0x0000000904097223 */
/* 0x002fe20000000005 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @P1 BRA 0x1f0 ; /* 0xfffffc9000001947 */
/* 0x000fea000383ffff */
/*0560*/ @!P0 BRA 0x730 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD R6, R16, c[0x0][0x178], R13 ; /* 0x00005e0010067a24 */
/* 0x000fe200078e020d */
/*0580*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fe20000000f00 */
/*0590*/ IMAD R2, R19, 0x2, R0 ; /* 0x0000000213027824 */
/* 0x000fc600078e0200 */
/*05a0*/ LEA R3, R19, R6, 0x1 ; /* 0x0000000613037211 */
/* 0x000fe200078e08ff */
/*05b0*/ IMAD R5, R2, c[0x0][0x178], R13 ; /* 0x00005e0002057a24 */
/* 0x000fc800078e020d */
/*05c0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*05d0*/ IMAD R5, R12, 0x2, R5 ; /* 0x000000020c057824 */
/* 0x002fe200078e0205 */
/*05e0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*05f0*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD.WIDE R2, R5, R4, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0204 */
/*0610*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000f */
/*0620*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000aa000c1e1900 */
/*0630*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x0002e2000c1e1900 */
/*0640*/ IADD3 R17, R17, -0x1, RZ ; /* 0xffffffff11117810 */
/* 0x000fc80007ffe0ff */
/*0650*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f05270 */
/*0660*/ IMAD.WIDE R2, R21, 0x4, R2 ; /* 0x0000000415027825 */
/* 0x001fe200078e0202 */
/*0670*/ IADD3 R6, P1, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x002fc80007f3e0ff */
/*0680*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0690*/ STS [R18+0x10], R11 ; /* 0x0000100b12007388 */
/* 0x004fe80000000800 */
/*06a0*/ STS [R18], R7 ; /* 0x0000000712007388 */
/* 0x008fe80000000800 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06c0*/ LDS R8, [R13.X4+0x10] ; /* 0x000010000d087984 */
/* 0x000fe80000004800 */
/*06d0*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e280000008a00 */
/*06e0*/ LDS R10, [R13.X4+0x18] ; /* 0x000018000d0a7984 */
/* 0x000e620000004800 */
/*06f0*/ FFMA R4, R8, R4, R9 ; /* 0x0000000408047223 */
/* 0x001fc80000000009 */
/*0700*/ FFMA R9, R10, R5, R4 ; /* 0x000000050a097223 */
/* 0x002fe20000000004 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ @P0 BRA 0x610 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0730*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0740*/ LEA R13, R12, R13, 0x1 ; /* 0x0000000d0c0d7211 */
/* 0x006fca00078e08ff */
/*0750*/ IMAD R2, R16, c[0x0][0x178], R13 ; /* 0x00005e0010027a24 */
/* 0x000fc800078e020d */
/*0760*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0770*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0780*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x790; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
float *elements;
} Matrix;
/* Thread block size */
#define TILE_WIDTH 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const float* Md, const float* Nd, float* Pd, const int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
//Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; m++) {
// Coolaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; k++) Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
/**/
void test(const Matrix C);
/**/
int main(int argc, char* argv[])
{
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(float)*size*size;
h_A.width = size;
h_B.width = size;
h_C.width = size;
/* Allocate host memory */
h_A.elements = (float*)malloc(full_size);
h_B.elements = (float*)malloc(full_size);
h_C.elements = (float*)malloc(full_size);
/**/
for(i=0;i<size*size;++i){ scanf("%f", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%f", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;
d_B.width = size;
d_C.width = size;
cudaMalloc(&d_A.elements, full_size);
cudaMalloc(&d_B.elements, full_size);
cudaMalloc(&d_C.elements, full_size);
cudaEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
cudaMemcpy(d_A.elements, h_A.elements, full_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B.elements, h_B.elements, full_size, cudaMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A.elements, d_B.elements, d_C.elements,d_A.width);
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_C.elements, d_C.elements, full_size, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C)
{
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%4.1f ", C.elements[i*C.width+j]);
printf("\n");
}
} | .file "tmpxft_001a5ccc_00000000-6_MMult2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%4.1f "
.LC1:
.string "\n"
.text
.globl _Z4test6Matrix
.type _Z4test6Matrix, @function
_Z4test6Matrix:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 4(%rsp)
testl %edi, %edi
jle .L3
movq %rsi, %r12
movslq %edi, %rdi
leaq 0(,%rdi,4), %r15
negq %rdi
leaq 0(,%rdi,4), %rax
movq %rax, 8(%rsp)
movq %r15, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
.L5:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 4(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z4test6Matrix, .-_Z4test6Matrix
.globl _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi
.type _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi, @function
_Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MatMulPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi, .-_Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi
.globl _Z6MatMulPKfS0_Pfi
.type _Z6MatMulPKfS0_Pfi, @function
_Z6MatMulPKfS0_Pfi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6MatMulPKfS0_Pfi, .-_Z6MatMulPKfS0_Pfi
.section .rodata.str1.1
.LC2:
.string "%d"
.LC3:
.string "%f"
.LC4:
.string "Elapsed time = %f (s)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, 32(%rsp)
leaq 32(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 32(%rsp), %r13d
movl %r13d, %eax
movq %rax, 24(%rsp)
movl %r13d, %r12d
imull %r13d, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 16(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movl %r13d, %eax
imull %r13d, %eax
testl %eax, %eax
jle .L23
movl $0, %ebx
leaq .LC3(%rip), %r15
.L19:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 32(%rsp), %eax
movl %eax, %edx
imull %eax, %edx
addq $4, %rbp
cmpl %ebx, %edx
jg .L19
testl %edx, %edx
jle .L18
movq 8(%rsp), %rbp
movl $0, %ebx
leaq .LC3(%rip), %r15
.L20:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 32(%rsp), %eax
addq $4, %rbp
movl %eax, %edx
imull %eax, %edx
cmpl %ebx, %edx
jg .L20
.L18:
movl %eax, 80(%rsp)
movl %eax, 96(%rsp)
movl %eax, 112(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
shrl %r13d
movl %r13d, 68(%rsp)
movl %r13d, 72(%rsp)
movl $2, 56(%rsp)
movl $2, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
movl $2, %ecx
movq %r12, %rdx
movq 120(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl 24(%rsp), %edi
movq %r14, %rsi
call _Z4test6Matrix
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %r13d, %eax
jmp .L18
.L27:
movl 80(%rsp), %ecx
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6MatMulPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatMulPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
float *elements;
} Matrix;
/* Thread block size */
#define TILE_WIDTH 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const float* Md, const float* Nd, float* Pd, const int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
//Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; m++) {
// Coolaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; k++) Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
/**/
void test(const Matrix C);
/**/
int main(int argc, char* argv[])
{
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(float)*size*size;
h_A.width = size;
h_B.width = size;
h_C.width = size;
/* Allocate host memory */
h_A.elements = (float*)malloc(full_size);
h_B.elements = (float*)malloc(full_size);
h_C.elements = (float*)malloc(full_size);
/**/
for(i=0;i<size*size;++i){ scanf("%f", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%f", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;
d_B.width = size;
d_C.width = size;
cudaMalloc(&d_A.elements, full_size);
cudaMalloc(&d_B.elements, full_size);
cudaMalloc(&d_C.elements, full_size);
cudaEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
cudaMemcpy(d_A.elements, h_A.elements, full_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B.elements, h_B.elements, full_size, cudaMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A.elements, d_B.elements, d_C.elements,d_A.width);
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_C.elements, d_C.elements, full_size, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C)
{
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%4.1f ", C.elements[i*C.width+j]);
printf("\n");
}
} | #include <stdio.h>
#include <hip/hip_runtime.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
float *elements;
} Matrix;
/* Thread block size */
#define TILE_WIDTH 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const float* Md, const float* Nd, float* Pd, const int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
//Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; m++) {
// Coolaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; k++) Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
/**/
void test(const Matrix C);
/**/
int main(int argc, char* argv[])
{
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(float)*size*size;
h_A.width = size;
h_B.width = size;
h_C.width = size;
/* Allocate host memory */
h_A.elements = (float*)malloc(full_size);
h_B.elements = (float*)malloc(full_size);
h_C.elements = (float*)malloc(full_size);
/**/
for(i=0;i<size*size;++i){ scanf("%f", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%f", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;
d_B.width = size;
d_C.width = size;
hipMalloc(&d_A.elements, full_size);
hipMalloc(&d_B.elements, full_size);
hipMalloc(&d_C.elements, full_size);
hipEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
hipMemcpy(d_A.elements, h_A.elements, full_size, hipMemcpyHostToDevice);
hipMemcpy(d_B.elements, h_B.elements, full_size, hipMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A.elements, d_B.elements, d_C.elements,d_A.width);
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_C.elements, d_C.elements, full_size, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C)
{
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%4.1f ", C.elements[i*C.width+j]);
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
float *elements;
} Matrix;
/* Thread block size */
#define TILE_WIDTH 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const float* Md, const float* Nd, float* Pd, const int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
//Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; m++) {
// Coolaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; k++) Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
/**/
void test(const Matrix C);
/**/
int main(int argc, char* argv[])
{
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(float)*size*size;
h_A.width = size;
h_B.width = size;
h_C.width = size;
/* Allocate host memory */
h_A.elements = (float*)malloc(full_size);
h_B.elements = (float*)malloc(full_size);
h_C.elements = (float*)malloc(full_size);
/**/
for(i=0;i<size*size;++i){ scanf("%f", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%f", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;
d_B.width = size;
d_C.width = size;
hipMalloc(&d_A.elements, full_size);
hipMalloc(&d_B.elements, full_size);
hipMalloc(&d_C.elements, full_size);
hipEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
hipMemcpy(d_A.elements, h_A.elements, full_size, hipMemcpyHostToDevice);
hipMemcpy(d_B.elements, h_B.elements, full_size, hipMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A.elements, d_B.elements, d_C.elements,d_A.width);
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_C.elements, d_C.elements, full_size, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C)
{
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%4.1f ", C.elements[i*C.width+j]);
printf("\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatMulPKfS0_Pfi
.globl _Z6MatMulPKfS0_Pfi
.p2align 8
.type _Z6MatMulPKfS0_Pfi,@function
_Z6MatMulPKfS0_Pfi:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 1, v5
v_lshl_add_u32 v0, s14, 1, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 3, v5
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 16, v8
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 8, v9
s_cmp_lg_u32 s9, 4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatMulPKfS0_Pfi
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatMulPKfS0_Pfi, .Lfunc_end0-_Z6MatMulPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatMulPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6MatMulPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/* Matrices are stored in row-major order: */
/* M(row, col) = (M.width*row +col); */
typedef struct{
/* suppose we use only square matrices */
int width;
float *elements;
} Matrix;
/* Thread block size */
#define TILE_WIDTH 2
/***********************/
/* TODO, write KERNEL */
/***********************/
__global__ void MatMul(const float* Md, const float* Nd, float* Pd, const int Width)
{
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the Pd element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
//Loop over the Md and Nd tiles required to compute the Pd element
for (int m = 0; m < Width/TILE_WIDTH; m++) {
// Coolaborative loading of Md and Nd tiles into shared memory
Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)];
Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; k++) Pvalue += Mds[ty][k] * Nds[k][tx];
__syncthreads();
}
Pd[Row*Width+Col] = Pvalue;
}
/**/
void test(const Matrix C);
/**/
int main(int argc, char* argv[])
{
int i;
/* init matrices */
Matrix h_A, h_B, h_C;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/*******************/
/** READING INPUT **/
/*******************/
int size = 0; //dimension of matrices
scanf("%d", &size);
int full_size = sizeof(float)*size*size;
h_A.width = size;
h_B.width = size;
h_C.width = size;
/* Allocate host memory */
h_A.elements = (float*)malloc(full_size);
h_B.elements = (float*)malloc(full_size);
h_C.elements = (float*)malloc(full_size);
/**/
for(i=0;i<size*size;++i){ scanf("%f", &h_A.elements[i]);}
for(i=0;i<size*size;++i){ scanf("%f", &h_B.elements[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device */
/* memory for A,B,C */
/*************************/
Matrix d_A, d_B, d_C;
d_A.width = size;
d_B.width = size;
d_C.width = size;
hipMalloc(&d_A.elements, full_size);
hipMalloc(&d_B.elements, full_size);
hipMalloc(&d_C.elements, full_size);
hipEventRecord(start,0);
/***********************************/
/* copy vectors A&B to device */
/***********************************/
hipMemcpy(d_A.elements, h_A.elements, full_size, hipMemcpyHostToDevice);
hipMemcpy(d_B.elements, h_B.elements, full_size, hipMemcpyHostToDevice);
/*********************/
/* call kernel */
/*********************/
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(h_B.width/dimBlock.x, h_A.width/dimBlock.y);
MatMul<<<dimGrid,dimBlock>>>(d_A.elements, d_B.elements, d_C.elements,d_A.width);
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_C.elements, d_C.elements, full_size, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
fprintf(stderr,"Elapsed time = %f (s)\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
/*******************************************/
/** Testing output, don't change anything! */
/*******************************************/
test(h_C);
/* free device memory */
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
/* free host memory */
free(h_A.elements);
free(h_B.elements);
free(h_C.elements);
return 0;
}
//function to test the input, don't change anything!
void test(const Matrix C)
{
int i,j;
//int size = C.width*C.width;
for(i=0;i<C.width;++i)
{
for(j=0;j<C.width;++j) printf("%4.1f ", C.elements[i*C.width+j]);
printf("\n");
}
} | .text
.file "MMult2.hip"
.globl _Z21__device_stub__MatMulPKfS0_Pfi # -- Begin function _Z21__device_stub__MatMulPKfS0_Pfi
.p2align 4, 0x90
.type _Z21__device_stub__MatMulPKfS0_Pfi,@function
_Z21__device_stub__MatMulPKfS0_Pfi: # @_Z21__device_stub__MatMulPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatMulPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__MatMulPKfS0_Pfi, .Lfunc_end0-_Z21__device_stub__MatMulPKfS0_Pfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %ebp
movl %ebp, %eax
imull %ebp, %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r15
cmpl $0, 12(%rsp)
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r14, %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movl 12(%rsp), %eax
imull %eax, %eax
addq $4, %r13
cmpq %rax, %rbx
jb .LBB1_2
.LBB1_3: # %.preheader
movl 12(%rsp), %eax
testl %eax, %eax
je .LBB1_6
# %bb.4: # %.lr.ph40.preheader
movq 24(%rsp), %r13 # 8-byte Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph40
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movl 12(%rsp), %eax
movl %eax, %ecx
imull %ecx, %ecx
addq $4, %r13
cmpq %rcx, %rbx
jb .LBB1_5
.LBB1_6: # %._crit_edge
movl %eax, 48(%rsp)
movl %eax, 80(%rsp)
movl %eax, 64(%rsp)
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq %r14, 96(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 88(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
shrl %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 56(%rsp), %rax
movq 88(%rsp), %rcx
movq 72(%rsp), %rdx
movl 48(%rsp), %esi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 44(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z6MatMulPKfS0_Pfi, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 72(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movq stderr(%rip), %rdi
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %ebp, %ebp
jle .LBB1_13
# %bb.9: # %.preheader.lr.ph.i
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_10: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
movl %r12d, %eax
leaq (%r15,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB1_11
# %bb.12: # %._crit_edge.i
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebp, %r12d
cmpq %rbp, %r13
jne .LBB1_10
.LBB1_13: # %_Z4test6Matrix.exit
movq 56(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z4test6Matrix # -- Begin function _Z4test6Matrix
.p2align 4, 0x90
.type _Z4test6Matrix,@function
_Z4test6Matrix: # @_Z4test6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB2_2
.LBB2_5: # %._crit_edge12
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z4test6Matrix, .Lfunc_end2-_Z4test6Matrix
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatMulPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatMulPKfS0_Pfi,@object # @_Z6MatMulPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z6MatMulPKfS0_Pfi
.p2align 3, 0x0
_Z6MatMulPKfS0_Pfi:
.quad _Z21__device_stub__MatMulPKfS0_Pfi
.size _Z6MatMulPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Elapsed time = %f (s)\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%4.1f "
.size .L.str.3, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatMulPKfS0_Pfi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatMulPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatMulPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6MatMulPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ MOV R14, c[0x0][0x178] ; /* 0x00005e00000e7a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0080*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ea20000002100 */
/*0090*/ LEA R16, R3, R0, 0x1 ; /* 0x0000000003107211 */
/* 0x001fca00078e08ff */
/*00a0*/ @!P0 BRA 0x730 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*00b0*/ LEA.HI R2, R14, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e000e027a11 */
/* 0x000fe200078f08ff */
/*00c0*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*00d0*/ SHF.L.U32 R18, R0, 0x3, RZ ; /* 0x0000000300127819 */
/* 0x000fe200000006ff */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.R.S32.HI R22, RZ, 0x1, R2 ; /* 0x00000001ff167819 */
/* 0x000fe40000011402 */
/*0100*/ SHF.L.U32 R21, R14, 0x1, RZ ; /* 0x000000010e157819 */
/* 0x000fe200000006ff */
/*0110*/ IMAD R18, R13, 0x4, R18 ; /* 0x000000040d127824 */
/* 0x004fe200078e0212 */
/*0120*/ IADD3 R2, R22.reuse, -0x1, RZ ; /* 0xffffffff16027810 */
/* 0x040fe40007ffe0ff */
/*0130*/ LOP3.LUT R17, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316117812 */
/* 0x000fc400078ec0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0150*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f05270 */
/*0160*/ @!P1 BRA 0x560 ; /* 0x000003f000009947 */
/* 0x000fea0003800000 */
/*0170*/ MOV R20, 0x4 ; /* 0x0000000400147802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R15, R0, c[0x0][0x178], R13.reuse ; /* 0x00005e00000f7a24 */
/* 0x100fe200078e020d */
/*0190*/ IADD3 R22, -R22, R17, RZ ; /* 0x0000001116167210 */
/* 0x000fe20007ffe1ff */
/*01a0*/ IMAD R3, R16, c[0x0][0x178], R13 ; /* 0x00005e0010037a24 */
/* 0x000fe200078e020d */
/*01b0*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA R15, R12, R15, 0x1 ; /* 0x0000000f0c0f7211 */
/* 0x002fe200078e08ff */
/*01e0*/ IMAD.WIDE R2, R3, R20, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0214 */
/*01f0*/ IMAD.WIDE R4, R15, R20, c[0x0][0x168] ; /* 0x00005a000f047625 */
/* 0x000fe200078e0214 */
/*0200*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IMAD.WIDE R10, R21, 0x4, R4 ; /* 0x00000004150a7825 */
/* 0x000fc600078e0204 */
/*0230*/ STS [R18], R23 ; /* 0x0000001712007388 */
/* 0x004fe80000000800 */
/*0240*/ STS [R18+0x10], R25 ; /* 0x0000101912007388 */
/* 0x008fe80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS R8, [R13.X4+0x10] ; /* 0x000010000d087984 */
/* 0x000fe80000004800 */
/*0270*/ LDS R26, [R13.X4+0x18] ; /* 0x000018000d1a7984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ LDG.E R29, [R2.64+0x8] ; /* 0x00000804021d7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FFMA R6, R8, R6, R9 ; /* 0x0000000608067223 */
/* 0x001fc40000000009 */
/*02d0*/ IMAD.WIDE R8, R21, 0x4, R10 ; /* 0x0000000415087825 */
/* 0x000fe200078e020a */
/*02e0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R18+0x10], R28 ; /* 0x0000101c12007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R23, [R13.X4+0x10] ; /* 0x000010000d177984 */
/* 0x000fe80000004800 */
/*0320*/ LDS R24, [R13.X4+0x18] ; /* 0x000018000d187984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e280000008a00 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ LDG.E R25, [R2.64+0x10] ; /* 0x0000100402197981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ee2000c1e1900 */
/*0370*/ FFMA R27, R26, R7, R6 ; /* 0x000000071a1b7223 */
/* 0x000fc60000000006 */
/*0380*/ STS [R18], R25 ; /* 0x0000001912007388 */
/* 0x004fe80000000800 */
/*0390*/ STS [R18+0x10], R11 ; /* 0x0000100b12007388 */
/* 0x0083e80000000800 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03b0*/ IMAD.WIDE R10, R21, 0x4, R8 ; /* 0x00000004150a7825 */
/* 0x002fca00078e0208 */
/*03c0*/ LDS R25, [R13.X4+0x10] ; /* 0x000010000d197984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R26, [R13.X4+0x18] ; /* 0x000018000d1a7984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e680000008a00 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0400*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R29, [R2.64+0x18] ; /* 0x00001804021d7981 */
/* 0x000722000c1e1900 */
/*0420*/ FFMA R27, R23, R4, R27 ; /* 0x00000004171b7223 */
/* 0x001fe2000000001b */
/*0430*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fc40007ffe0ff */
/*0440*/ LEA R15, R14, R15, 0x3 ; /* 0x0000000f0e0f7211 */
/* 0x000fe200078e18ff */
/*0450*/ FFMA R5, R24, R5, R27 ; /* 0x0000000518057223 */
/* 0x000fc8000000001b */
/*0460*/ FFMA R5, R25, R6, R5 ; /* 0x0000000619057223 */
/* 0x002fe20000000005 */
/*0470*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x008fe20007f5e0ff */
/*0480*/ IMAD.IADD R6, R22, 0x1, R19 ; /* 0x0000000116067824 */
/* 0x000fe400078e0213 */
/*0490*/ FFMA R5, R26, R7, R5 ; /* 0x000000071a057223 */
/* 0x000fe20000000005 */
/*04a0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*04b0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*04c0*/ STS [R18+0x10], R10 ; /* 0x0000100a12007388 */
/* 0x004fe80000000800 */
/*04d0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x010fe80000000800 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04f0*/ LDS R23, [R13.X4+0x10] ; /* 0x000010000d177984 */
/* 0x000fe80000004800 */
/*0500*/ LDS.64 R8, [R0.X8] ; /* 0x0000000000087984 */
/* 0x000e280000008a00 */
/*0510*/ LDS R4, [R13.X4+0x18] ; /* 0x000018000d047984 */
/* 0x000e620000004800 */
/*0520*/ FFMA R5, R23, R8, R5 ; /* 0x0000000817057223 */
/* 0x001fc80000000005 */
/*0530*/ FFMA R9, R4, R9, R5 ; /* 0x0000000904097223 */
/* 0x002fe20000000005 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @P1 BRA 0x1f0 ; /* 0xfffffc9000001947 */
/* 0x000fea000383ffff */
/*0560*/ @!P0 BRA 0x730 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD R6, R16, c[0x0][0x178], R13 ; /* 0x00005e0010067a24 */
/* 0x000fe200078e020d */
/*0580*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fe20000000f00 */
/*0590*/ IMAD R2, R19, 0x2, R0 ; /* 0x0000000213027824 */
/* 0x000fc600078e0200 */
/*05a0*/ LEA R3, R19, R6, 0x1 ; /* 0x0000000613037211 */
/* 0x000fe200078e08ff */
/*05b0*/ IMAD R5, R2, c[0x0][0x178], R13 ; /* 0x00005e0002057a24 */
/* 0x000fc800078e020d */
/*05c0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*05d0*/ IMAD R5, R12, 0x2, R5 ; /* 0x000000020c057824 */
/* 0x002fe200078e0205 */
/*05e0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*05f0*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD.WIDE R2, R5, R4, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0204 */
/*0610*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000f */
/*0620*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000aa000c1e1900 */
/*0630*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x0002e2000c1e1900 */
/*0640*/ IADD3 R17, R17, -0x1, RZ ; /* 0xffffffff11117810 */
/* 0x000fc80007ffe0ff */
/*0650*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f05270 */
/*0660*/ IMAD.WIDE R2, R21, 0x4, R2 ; /* 0x0000000415027825 */
/* 0x001fe200078e0202 */
/*0670*/ IADD3 R6, P1, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x002fc80007f3e0ff */
/*0680*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0690*/ STS [R18+0x10], R11 ; /* 0x0000100b12007388 */
/* 0x004fe80000000800 */
/*06a0*/ STS [R18], R7 ; /* 0x0000000712007388 */
/* 0x008fe80000000800 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06c0*/ LDS R8, [R13.X4+0x10] ; /* 0x000010000d087984 */
/* 0x000fe80000004800 */
/*06d0*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e280000008a00 */
/*06e0*/ LDS R10, [R13.X4+0x18] ; /* 0x000018000d0a7984 */
/* 0x000e620000004800 */
/*06f0*/ FFMA R4, R8, R4, R9 ; /* 0x0000000408047223 */
/* 0x001fc80000000009 */
/*0700*/ FFMA R9, R10, R5, R4 ; /* 0x000000050a097223 */
/* 0x002fe20000000004 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ @P0 BRA 0x610 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0730*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0740*/ LEA R13, R12, R13, 0x1 ; /* 0x0000000d0c0d7211 */
/* 0x006fca00078e08ff */
/*0750*/ IMAD R2, R16, c[0x0][0x178], R13 ; /* 0x00005e0010027a24 */
/* 0x000fc800078e020d */
/*0760*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0770*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0780*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x790; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatMulPKfS0_Pfi
.globl _Z6MatMulPKfS0_Pfi
.p2align 8
.type _Z6MatMulPKfS0_Pfi,@function
_Z6MatMulPKfS0_Pfi:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 1, v5
v_lshl_add_u32 v0, s14, 1, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 3, v5
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 16, v8
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 8, v9
s_cmp_lg_u32 s9, 4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatMulPKfS0_Pfi
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatMulPKfS0_Pfi, .Lfunc_end0-_Z6MatMulPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatMulPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6MatMulPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a5ccc_00000000-6_MMult2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%4.1f "
.LC1:
.string "\n"
.text
.globl _Z4test6Matrix
.type _Z4test6Matrix, @function
_Z4test6Matrix:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 4(%rsp)
testl %edi, %edi
jle .L3
movq %rsi, %r12
movslq %edi, %rdi
leaq 0(,%rdi,4), %r15
negq %rdi
leaq 0(,%rdi,4), %rax
movq %rax, 8(%rsp)
movq %r15, %rbp
movl $0, %r14d
leaq .LC0(%rip), %r13
.L5:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 4(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z4test6Matrix, .-_Z4test6Matrix
.globl _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi
.type _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi, @function
_Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MatMulPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi, .-_Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi
.globl _Z6MatMulPKfS0_Pfi
.type _Z6MatMulPKfS0_Pfi, @function
_Z6MatMulPKfS0_Pfi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6MatMulPKfS0_Pfi, .-_Z6MatMulPKfS0_Pfi
.section .rodata.str1.1
.LC2:
.string "%d"
.LC3:
.string "%f"
.LC4:
.string "Elapsed time = %f (s)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, 32(%rsp)
leaq 32(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 32(%rsp), %r13d
movl %r13d, %eax
movq %rax, 24(%rsp)
movl %r13d, %r12d
imull %r13d, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 16(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movl %r13d, %eax
imull %r13d, %eax
testl %eax, %eax
jle .L23
movl $0, %ebx
leaq .LC3(%rip), %r15
.L19:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 32(%rsp), %eax
movl %eax, %edx
imull %eax, %edx
addq $4, %rbp
cmpl %ebx, %edx
jg .L19
testl %edx, %edx
jle .L18
movq 8(%rsp), %rbp
movl $0, %ebx
leaq .LC3(%rip), %r15
.L20:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 32(%rsp), %eax
addq $4, %rbp
movl %eax, %edx
imull %eax, %edx
cmpl %ebx, %edx
jg .L20
.L18:
movl %eax, 80(%rsp)
movl %eax, 96(%rsp)
movl %eax, 112(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
shrl %r13d
movl %r13d, 68(%rsp)
movl %r13d, 72(%rsp)
movl $2, 56(%rsp)
movl $2, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
movl $2, %ecx
movq %r12, %rdx
movq 120(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl 24(%rsp), %edi
movq %r14, %rsi
call _Z4test6Matrix
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %r13d, %eax
jmp .L18
.L27:
movl 80(%rsp), %ecx
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z32__device_stub__Z6MatMulPKfS0_PfiPKfS0_Pfi
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6MatMulPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatMulPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MMult2.hip"
.globl _Z21__device_stub__MatMulPKfS0_Pfi # -- Begin function _Z21__device_stub__MatMulPKfS0_Pfi
.p2align 4, 0x90
.type _Z21__device_stub__MatMulPKfS0_Pfi,@function
_Z21__device_stub__MatMulPKfS0_Pfi: # @_Z21__device_stub__MatMulPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatMulPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__MatMulPKfS0_Pfi, .Lfunc_end0-_Z21__device_stub__MatMulPKfS0_Pfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %ebp
movl %ebp, %eax
imull %ebp, %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r15
cmpl $0, 12(%rsp)
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r14, %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movl 12(%rsp), %eax
imull %eax, %eax
addq $4, %r13
cmpq %rax, %rbx
jb .LBB1_2
.LBB1_3: # %.preheader
movl 12(%rsp), %eax
testl %eax, %eax
je .LBB1_6
# %bb.4: # %.lr.ph40.preheader
movq 24(%rsp), %r13 # 8-byte Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph40
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movl 12(%rsp), %eax
movl %eax, %ecx
imull %ecx, %ecx
addq $4, %r13
cmpq %rcx, %rbx
jb .LBB1_5
.LBB1_6: # %._crit_edge
movl %eax, 48(%rsp)
movl %eax, 80(%rsp)
movl %eax, 64(%rsp)
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq %r14, 96(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 88(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
shrl %eax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 56(%rsp), %rax
movq 88(%rsp), %rcx
movq 72(%rsp), %rdx
movl 48(%rsp), %esi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 44(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z6MatMulPKfS0_Pfi, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 72(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movq stderr(%rip), %rdi
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movb $1, %al
callq fprintf
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %ebp, %ebp
jle .LBB1_13
# %bb.9: # %.preheader.lr.ph.i
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_10: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
movl %r12d, %eax
leaq (%r15,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB1_11
# %bb.12: # %._crit_edge.i
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebp, %r12d
cmpq %rbp, %r13
jne .LBB1_10
.LBB1_13: # %_Z4test6Matrix.exit
movq 56(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z4test6Matrix # -- Begin function _Z4test6Matrix
.p2align 4, 0x90
.type _Z4test6Matrix,@function
_Z4test6Matrix: # @_Z4test6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB2_2
.LBB2_5: # %._crit_edge12
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z4test6Matrix, .Lfunc_end2-_Z4test6Matrix
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatMulPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatMulPKfS0_Pfi,@object # @_Z6MatMulPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z6MatMulPKfS0_Pfi
.p2align 3, 0x0
_Z6MatMulPKfS0_Pfi:
.quad _Z21__device_stub__MatMulPKfS0_Pfi
.size _Z6MatMulPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Elapsed time = %f (s)\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%4.1f "
.size .L.str.3, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatMulPKfS0_Pfi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatMulPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatMulPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
//void setup_cuda(int ngpus, int argc, char **argv){
//insert from Bob' Born
// ;
//}
//void process_error( const cudaError_t &error, char *string=0, bool verbose=false ){
//insert from Bob's Born
// ;
//}
extern "C" void rtm_gpu_init(int nt, int nz, int nx, int zrec,
float * Vx0, float * Vz0, float * sigmaxx0, float * sigmazz0, float * sigmaxz0, //(nz, nx, nt)
// float * Vx, float * Vz, float * sigmaxx, float * sigmazz, float * sigmaxz, //(nt, nx)
float * m1_x,float * m1_z,float * aux_m2_c, float * aux_m3_c, float * aux_m2m3_c)
{
//set cuda devices and put all data onto gpu memory
cudaError_t cuda_ret;
cudaError_t err;
//Set Device
fprintf(stderr,"GPU init. \n");
cuda_ret = cudaSetDevice(0);
if(cuda_ret != cudaSuccess){
fprintf(stderr, "Failed to set the cuda device !\n");
}
else{
fprintf(stderr, "cuda device set OK\n");
}
// init data
//cudaMalloc(&g_,sizeof()*nx*nz*nt);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
//void setup_cuda(int ngpus, int argc, char **argv){
//insert from Bob' Born
// ;
//}
//void process_error( const cudaError_t &error, char *string=0, bool verbose=false ){
//insert from Bob's Born
// ;
//}
extern "C" void rtm_gpu_init(int nt, int nz, int nx, int zrec,
float * Vx0, float * Vz0, float * sigmaxx0, float * sigmazz0, float * sigmaxz0, //(nz, nx, nt)
// float * Vx, float * Vz, float * sigmaxx, float * sigmazz, float * sigmaxz, //(nt, nx)
float * m1_x,float * m1_z,float * aux_m2_c, float * aux_m3_c, float * aux_m2m3_c)
{
//set cuda devices and put all data onto gpu memory
cudaError_t cuda_ret;
cudaError_t err;
//Set Device
fprintf(stderr,"GPU init. \n");
cuda_ret = cudaSetDevice(0);
if(cuda_ret != cudaSuccess){
fprintf(stderr, "Failed to set the cuda device !\n");
}
else{
fprintf(stderr, "cuda device set OK\n");
}
// init data
//cudaMalloc(&g_,sizeof()*nx*nz*nt);
} | .file "tmpxft_00121692_00000000-6_rtmlib-modC-gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPU init. \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to set the cuda device !\n"
.section .rodata.str1.1
.LC2:
.string "cuda device set OK\n"
.text
.globl rtm_gpu_init
.type rtm_gpu_init, @function
rtm_gpu_init:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
je .L4
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2057:
.size rtm_gpu_init, .-rtm_gpu_init
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
//void setup_cuda(int ngpus, int argc, char **argv){
//insert from Bob' Born
// ;
//}
//void process_error( const cudaError_t &error, char *string=0, bool verbose=false ){
//insert from Bob's Born
// ;
//}
extern "C" void rtm_gpu_init(int nt, int nz, int nx, int zrec,
float * Vx0, float * Vz0, float * sigmaxx0, float * sigmazz0, float * sigmaxz0, //(nz, nx, nt)
// float * Vx, float * Vz, float * sigmaxx, float * sigmazz, float * sigmaxz, //(nt, nx)
float * m1_x,float * m1_z,float * aux_m2_c, float * aux_m3_c, float * aux_m2m3_c)
{
//set cuda devices and put all data onto gpu memory
cudaError_t cuda_ret;
cudaError_t err;
//Set Device
fprintf(stderr,"GPU init. \n");
cuda_ret = cudaSetDevice(0);
if(cuda_ret != cudaSuccess){
fprintf(stderr, "Failed to set the cuda device !\n");
}
else{
fprintf(stderr, "cuda device set OK\n");
}
// init data
//cudaMalloc(&g_,sizeof()*nx*nz*nt);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
//void setup_cuda(int ngpus, int argc, char **argv){
//insert from Bob' Born
// ;
//}
//void process_error( const cudaError_t &error, char *string=0, bool verbose=false ){
//insert from Bob's Born
// ;
//}
extern "C" void rtm_gpu_init(int nt, int nz, int nx, int zrec,
float * Vx0, float * Vz0, float * sigmaxx0, float * sigmazz0, float * sigmaxz0, //(nz, nx, nt)
// float * Vx, float * Vz, float * sigmaxx, float * sigmazz, float * sigmaxz, //(nt, nx)
float * m1_x,float * m1_z,float * aux_m2_c, float * aux_m3_c, float * aux_m2m3_c)
{
//set cuda devices and put all data onto gpu memory
hipError_t cuda_ret;
hipError_t err;
//Set Device
fprintf(stderr,"GPU init. \n");
cuda_ret = hipSetDevice(0);
if(cuda_ret != hipSuccess){
fprintf(stderr, "Failed to set the cuda device !\n");
}
else{
fprintf(stderr, "cuda device set OK\n");
}
// init data
//cudaMalloc(&g_,sizeof()*nx*nz*nt);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//void setup_cuda(int ngpus, int argc, char **argv){
//insert from Bob' Born
// ;
//}
//void process_error( const cudaError_t &error, char *string=0, bool verbose=false ){
//insert from Bob's Born
// ;
//}
extern "C" void rtm_gpu_init(int nt, int nz, int nx, int zrec,
float * Vx0, float * Vz0, float * sigmaxx0, float * sigmazz0, float * sigmaxz0, //(nz, nx, nt)
// float * Vx, float * Vz, float * sigmaxx, float * sigmazz, float * sigmaxz, //(nt, nx)
float * m1_x,float * m1_z,float * aux_m2_c, float * aux_m3_c, float * aux_m2m3_c)
{
//set cuda devices and put all data onto gpu memory
hipError_t cuda_ret;
hipError_t err;
//Set Device
fprintf(stderr,"GPU init. \n");
cuda_ret = hipSetDevice(0);
if(cuda_ret != hipSuccess){
fprintf(stderr, "Failed to set the cuda device !\n");
}
else{
fprintf(stderr, "cuda device set OK\n");
}
// init data
//cudaMalloc(&g_,sizeof()*nx*nz*nt);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//void setup_cuda(int ngpus, int argc, char **argv){
//insert from Bob' Born
// ;
//}
//void process_error( const cudaError_t &error, char *string=0, bool verbose=false ){
//insert from Bob's Born
// ;
//}
extern "C" void rtm_gpu_init(int nt, int nz, int nx, int zrec,
float * Vx0, float * Vz0, float * sigmaxx0, float * sigmazz0, float * sigmaxz0, //(nz, nx, nt)
// float * Vx, float * Vz, float * sigmaxx, float * sigmazz, float * sigmaxz, //(nt, nx)
float * m1_x,float * m1_z,float * aux_m2_c, float * aux_m3_c, float * aux_m2m3_c)
{
//set cuda devices and put all data onto gpu memory
hipError_t cuda_ret;
hipError_t err;
//Set Device
fprintf(stderr,"GPU init. \n");
cuda_ret = hipSetDevice(0);
if(cuda_ret != hipSuccess){
fprintf(stderr, "Failed to set the cuda device !\n");
}
else{
fprintf(stderr, "cuda device set OK\n");
}
// init data
//cudaMalloc(&g_,sizeof()*nx*nz*nt);
} | .text
.file "rtmlib-modC-gpu.hip"
.globl rtm_gpu_init # -- Begin function rtm_gpu_init
.p2align 4, 0x90
.type rtm_gpu_init,@function
rtm_gpu_init: # @rtm_gpu_init
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $11, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq hipSetDevice
movq stderr(%rip), %rcx
testl %eax, %eax
jne .LBB0_1
# %bb.3:
movl $.L.str.2, %edi
movl $19, %esi
jmp .LBB0_2
.LBB0_1:
movl $.L.str.1, %edi
movl $32, %esi
.LBB0_2:
movl $1, %edx
popq %rax
.cfi_def_cfa_offset 8
jmp fwrite@PLT # TAILCALL
.Lfunc_end0:
.size rtm_gpu_init, .Lfunc_end0-rtm_gpu_init
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU init. \n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to set the cuda device !\n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cuda device set OK\n"
.size .L.str.2, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00121692_00000000-6_rtmlib-modC-gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPU init. \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to set the cuda device !\n"
.section .rodata.str1.1
.LC2:
.string "cuda device set OK\n"
.text
.globl rtm_gpu_init
.type rtm_gpu_init, @function
rtm_gpu_init:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
je .L4
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2057:
.size rtm_gpu_init, .-rtm_gpu_init
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rtmlib-modC-gpu.hip"
.globl rtm_gpu_init # -- Begin function rtm_gpu_init
.p2align 4, 0x90
.type rtm_gpu_init,@function
rtm_gpu_init: # @rtm_gpu_init
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $11, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq hipSetDevice
movq stderr(%rip), %rcx
testl %eax, %eax
jne .LBB0_1
# %bb.3:
movl $.L.str.2, %edi
movl $19, %esi
jmp .LBB0_2
.LBB0_1:
movl $.L.str.1, %edi
movl $32, %esi
.LBB0_2:
movl $1, %edx
popq %rax
.cfi_def_cfa_offset 8
jmp fwrite@PLT # TAILCALL
.Lfunc_end0:
.size rtm_gpu_init, .Lfunc_end0-rtm_gpu_init
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU init. \n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to set the cuda device !\n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cuda device set OK\n"
.size .L.str.2, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // have fun :-) | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // have fun :-) | .file "tmpxft_0019eaa9_00000000-6_cumulative_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // have fun :-) | #include <hip/hip_runtime.h>
// have fun :-) |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// have fun :-) | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// have fun :-) | .text
.file "cumulative_sum.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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