system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void fourier_transform(float *in, float *out, int height, int width, int blockConfig) {
// block elements and function variables
int my_x, k, t;
my_x = blockIdx.x * blockDim.x + threadIdx.x;
// iterate through each element, going from frequency to time domain
for (k = 0; k < height; k++) {
// difference, which will be used to subtract off
float realSum = 0.0;
// iterate through the input element
for (t = 0; t < width; t++) {
// calculate the angle and update the sum
float angle = 2 * M_PI * (my_x * height + t) * (my_x * width + k) / height;
realSum += in[my_x * height + t] * cos(angle);
}
// each output element will be the current sum for that index
out[my_x * height + k] = realSum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fourier_transform(float *in, float *out, int height, int width, int blockConfig) {
// block elements and function variables
int my_x, k, t;
my_x = blockIdx.x * blockDim.x + threadIdx.x;
// iterate through each element, going from frequency to time domain
for (k = 0; k < height; k++) {
// difference, which will be used to subtract off
float realSum = 0.0;
// iterate through the input element
for (t = 0; t < width; t++) {
// calculate the angle and update the sum
float angle = 2 * M_PI * (my_x * height + t) * (my_x * width + k) / height;
realSum += in[my_x * height + t] * cos(angle);
}
// each output element will be the current sum for that index
out[my_x * height + k] = realSum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fourier_transform(float *in, float *out, int height, int width, int blockConfig) {
// block elements and function variables
int my_x, k, t;
my_x = blockIdx.x * blockDim.x + threadIdx.x;
// iterate through each element, going from frequency to time domain
for (k = 0; k < height; k++) {
// difference, which will be used to subtract off
float realSum = 0.0;
// iterate through the input element
for (t = 0; t < width; t++) {
// calculate the angle and update the sum
float angle = 2 * M_PI * (my_x * height + t) * (my_x * width + k) / height;
realSum += in[my_x * height + t] * cos(angle);
}
// each output element will be the current sum for that index
out[my_x * height + k] = realSum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17fourier_transformPfS_iii
.globl _Z17fourier_transformPfS_iii
.p2align 8
.type _Z17fourier_transformPfS_iii,@function
_Z17fourier_transformPfS_iii:
s_load_b32 s6, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_11
v_cvt_f64_i32_e32 v[1:2], s6
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s7, s[0:1], 0x14
s_mov_b32 s8, 0
s_mov_b32 s5, 0x401921fb
s_mov_b32 s4, 0x54442d18
s_mov_b32 s10, 0x7fffff
s_mov_b32 s11, 0xb94c1982
s_mov_b32 s12, 0x37d75334
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_gt_i32 s7, 0
s_cselect_b32 s9, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v3, v5, s6
v_mul_lo_u32 v0, v5, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
s_branch .LBB0_4
.LBB0_2:
v_mov_b32_e32 v10, 0
.LBB0_3:
v_add_nc_u32_e32 v6, s8, v3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s8, s6
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_store_b32 v[6:7], v10, off
s_cbranch_scc0 .LBB0_11
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_2
v_dual_mov_b32 v11, v3 :: v_dual_add_nc_u32 v6, s8, v0
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, v5
v_mov_b32_e32 v8, v4
s_delay_alu instid0(VALU_DEP_3)
v_cvt_f64_i32_e32 v[6:7], v6
s_mov_b32 s13, s7
s_branch .LBB0_7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v16, v14, v14 :: v_dual_and_b32 v19, 1, v15
s_add_i32 s13, s13, -1
v_lshlrev_b32_e32 v15, 30, v15
s_cmp_lg_u32 s13, 0
v_fmaak_f32 v17, s11, v16, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v19
v_add_nc_u32_e32 v11, 1, v11
v_and_b32_e32 v15, 0x80000000, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v17, v16, v17, 0xbe2aaa9d
v_dual_fmaak_f32 v18, s12, v16, 0xbab64f3b :: v_dual_mul_f32 v17, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v18, v16, v18, 0x3d2aabf7
v_fmac_f32_e32 v14, v14, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v18, v16, v18, 0xbf000004
v_fma_f32 v16, v16, v18, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v14, -v14, v16, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v13, 0x1f8
v_xor_b32_e32 v14, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v13, 0x7fc00000, v14, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v10, v12, v13
s_cbranch_scc0 .LBB0_3
.LBB0_7:
v_cvt_f64_i32_e32 v[12:13], v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[12:13], s[4:5]
v_mul_f64 v[13:14], v[12:13], v[6:7]
global_load_b32 v12, v[8:9], off
v_div_scale_f64 v[15:16], null, v[1:2], v[1:2], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[17:18], v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_div_scale_f64 v[19:20], vcc_lo, v[13:14], v[1:2], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[21:22], v[19:20], v[17:18]
v_fma_f64 v[15:16], -v[15:16], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[21:22]
v_div_fixup_f64 v[13:14], v[15:16], v[1:2], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v13, v[13:14]
v_cmp_ngt_f32_e64 s0, 0x48000000, |v13|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s14, exec_lo, s1
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v16, 0 :: v_dual_and_b32 v21, 0x7fffffff, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_or_b32 v24, v21, s10, 0x800000
v_lshrrev_b32_e32 v21, 23, v21
v_mad_u64_u32 v[14:15], null, v24, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v22, 0xffffff88, v21
v_cmp_lt_u32_e32 vcc_lo, 63, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[17:18], null, v24, 0x3c439041, v[15:16]
v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v15, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v23, v23, v22
v_mad_u64_u32 v[18:19], null, v24, 0xdb629599, v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v23
v_cndmask_b32_e64 v25, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v15, v19 :: v_dual_cndmask_b32 v14, v18, v14
v_add_nc_u32_e32 v25, v25, v23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[19:20], null, v24, 0xf534ddc0, v[15:16]
v_cmp_lt_u32_e64 s1, 31, v25
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v15, v20
v_cndmask_b32_e32 v17, v19, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[20:21], null, v24, 0xfc2757d1, v[15:16]
v_cndmask_b32_e64 v14, v17, v14, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v15, v21
v_mad_u64_u32 v[21:22], null, v24, 0x4e441529, v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v15, v22
v_mad_u64_u32 v[22:23], null, v24, 0xa2f9836e, v[15:16]
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v16, v21, v19 :: v_dual_add_nc_u32 v15, v15, v25
v_dual_cndmask_b32 v22, v22, v20 :: v_dual_cndmask_b32 v21, v23, v21
v_cndmask_b32_e32 v20, v20, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v15
v_cndmask_b32_e64 v19, v22, v16, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v21, v21, v22, s0
v_cndmask_b32_e64 v16, v16, v20, s0
v_sub_nc_u32_e32 v22, 32, v15
v_cndmask_b32_e64 v20, v20, v17, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v21, v21, v19, s1
v_cndmask_b32_e64 v19, v19, v16, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v16, v16, v20, s1
v_cndmask_b32_e64 v14, v20, v14, s1
v_alignbit_b32 v23, v21, v19, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v18, v19, v16, v22
v_cndmask_b32_e32 v15, v23, v21, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v21, v16, v14, v22
v_cndmask_b32_e32 v17, v18, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v18, v15, 29, 1
v_cndmask_b32_e32 v16, v21, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v19, v15, v17, 30
v_sub_nc_u32_e32 v20, 0, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v17, v17, v16, 30
v_alignbit_b32 v14, v16, v14, 30
v_xor_b32_e32 v19, v19, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v16, v17, v20
v_xor_b32_e32 v14, v14, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v21, v19
v_min_u32_e32 v21, 32, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v17, 31, v21
v_lshlrev_b32_e32 v23, 23, v21
v_alignbit_b32 v19, v19, v16, v17
v_alignbit_b32 v14, v16, v14, v17
v_lshrrev_b32_e32 v17, 29, v15
v_lshrrev_b32_e32 v15, 30, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v19, v14, 9
v_lshlrev_b32_e32 v17, 31, v17
v_lshrrev_b32_e32 v19, 9, v19
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v15, v18, v15
v_clz_i32_u32_e32 v20, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v22, 0.5, v17
v_min_u32_e32 v20, 32, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v22, v22, v23
v_sub_nc_u32_e32 v24, 31, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v14, v16, v14, v24
v_or_b32_e32 v16, v19, v22
v_add_lshl_u32 v19, v20, v21, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v14, 9, v14
v_mul_f32_e32 v20, 0x3fc90fda, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v14, v14, v19
v_fma_f32 v19, v16, 0x3fc90fda, -v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, 0x33000000, v14
v_fmac_f32_e32 v19, 0x33a22168, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v14, v14, v17
v_fmac_f32_e32 v19, 0x3fc90fda, v14
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v14, v20, v19
.LBB0_9:
s_and_not1_saveexec_b32 s0, s14
s_cbranch_execz .LBB0_6
v_mul_f32_e64 v14, 0x3f22f983, |v13|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v15, v14
v_fma_f32 v14, v15, 0xbfc90fda, |v13|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v14, 0xb3a22168, v15
v_fmac_f32_e32 v14, 0xa7c234c4, v15
v_cvt_i32_f32_e32 v15, v15
s_branch .LBB0_6
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17fourier_transformPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17fourier_transformPfS_iii, .Lfunc_end0-_Z17fourier_transformPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17fourier_transformPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17fourier_transformPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fourier_transform(float *in, float *out, int height, int width, int blockConfig) {
// block elements and function variables
int my_x, k, t;
my_x = blockIdx.x * blockDim.x + threadIdx.x;
// iterate through each element, going from frequency to time domain
for (k = 0; k < height; k++) {
// difference, which will be used to subtract off
float realSum = 0.0;
// iterate through the input element
for (t = 0; t < width; t++) {
// calculate the angle and update the sum
float angle = 2 * M_PI * (my_x * height + t) * (my_x * width + k) / height;
realSum += in[my_x * height + t] * cos(angle);
}
// each output element will be the current sum for that index
out[my_x * height + k] = realSum;
}
} | .text
.file "fourier_transform.hip"
.globl _Z32__device_stub__fourier_transformPfS_iii # -- Begin function _Z32__device_stub__fourier_transformPfS_iii
.p2align 4, 0x90
.type _Z32__device_stub__fourier_transformPfS_iii,@function
_Z32__device_stub__fourier_transformPfS_iii: # @_Z32__device_stub__fourier_transformPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17fourier_transformPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__fourier_transformPfS_iii, .Lfunc_end0-_Z32__device_stub__fourier_transformPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17fourier_transformPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17fourier_transformPfS_iii,@object # @_Z17fourier_transformPfS_iii
.section .rodata,"a",@progbits
.globl _Z17fourier_transformPfS_iii
.p2align 3, 0x0
_Z17fourier_transformPfS_iii:
.quad _Z32__device_stub__fourier_transformPfS_iii
.size _Z17fourier_transformPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17fourier_transformPfS_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__fourier_transformPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17fourier_transformPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002886e_00000000-6_fourier_transform.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii
.type _Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii, @function
_Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17fourier_transformPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii, .-_Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii
.globl _Z17fourier_transformPfS_iii
.type _Z17fourier_transformPfS_iii, @function
_Z17fourier_transformPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17fourier_transformPfS_iii, .-_Z17fourier_transformPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17fourier_transformPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17fourier_transformPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fourier_transform.hip"
.globl _Z32__device_stub__fourier_transformPfS_iii # -- Begin function _Z32__device_stub__fourier_transformPfS_iii
.p2align 4, 0x90
.type _Z32__device_stub__fourier_transformPfS_iii,@function
_Z32__device_stub__fourier_transformPfS_iii: # @_Z32__device_stub__fourier_transformPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17fourier_transformPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__fourier_transformPfS_iii, .Lfunc_end0-_Z32__device_stub__fourier_transformPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17fourier_transformPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17fourier_transformPfS_iii,@object # @_Z17fourier_transformPfS_iii
.section .rodata,"a",@progbits
.globl _Z17fourier_transformPfS_iii
.p2align 3, 0x0
_Z17fourier_transformPfS_iii:
.quad _Z32__device_stub__fourier_transformPfS_iii
.size _Z17fourier_transformPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17fourier_transformPfS_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__fourier_transformPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17fourier_transformPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //This code is a modification of L1 cache benchmark from
//"Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking": https://arxiv.org/pdf/1804.06826.pdf
//This benchmark measures the latency of L1 cache
//This code have been tested on Volta V100 architecture
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define SHARED_MEM_SIZE_BYTE (48*1024) //size in bytes, max 96KB for v100
#define SHARED_MEM_SIZE (SHARED_MEM_SIZE_BYTE/8)
#define THREADS_NUM 32 //Launch only one thread to calcaulte the latency using a pointer-chasing array technique
#define WARP_SIZE 32
#define ITERS 2048 //iterate over the array ITERS times
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//TO DO: @Jason, please change the code to be similar to the L2/DRAM latency format
//Measure latency of ITERS reads.
__global__ void shared_lat(uint32_t *startClk, uint32_t *stopClk, uint64_t *dsink, uint32_t stride){
// thread index
uint32_t tid = threadIdx.x;
uint32_t bid = blockIdx.x;
uint32_t uid = bid*blockDim.x+tid;
uint32_t n_threads = blockDim.x * gridDim.x;
__shared__ uint64_t s[SHARED_MEM_SIZE]; //static shared memory
// one thread to initialize the pointer-chasing array
for (uint32_t i=uid; i<(SHARED_MEM_SIZE-stride); i+=n_threads)
s[i] = (i+stride)%SHARED_MEM_SIZE;
if(uid == 0){
//initalize pointer chaser
uint64_t p_chaser = 0;
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
// pointer-chasing ITERS times
// use ca modifier to cache the load in L1
for(uint32_t i=0; i<ITERS; ++i) {
p_chaser = s[p_chaser];
}
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[uid] = start;
stopClk[uid] = stop;
dsink[uid] = p_chaser;
}
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(sizeof(uint32_t));
uint64_t *dsink = (uint64_t*) malloc(sizeof(uint64_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
uint64_t *dsink_g;
gpuErrchk( cudaMalloc(&startClk_g, sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&dsink_g, sizeof(uint64_t)) );
shared_lat<<<1,THREADS_NUM>>>(startClk_g, stopClk_g, dsink_g, 1);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(dsink, dsink_g, sizeof(uint64_t), cudaMemcpyDeviceToHost) );
printf("Shared Memory Latency = %f cycles\n", (float)(stopClk[0]-startClk[0])/ITERS );
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
printf("start clk = %u \n", startClk[0]);
printf("stop clk = %u \n", stopClk[0]);
return 0;
} | code for sm_80
Function : _Z10shared_latPjS_Pmj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIADD3 UR4, -UR4, 0x1800, URZ ; /* 0x0000180004047890 */
/* 0x000fe2000fffe13f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe4000bf26070 */
/*0080*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f05270 */
/*0090*/ @P1 BRA 0x140 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe400078e00ff */
/*00b0*/ IADD3 R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE.U32 R2, R4, -0x55555555, RZ ; /* 0xaaaaaaab04027825 */
/* 0x000fca00078e00ff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0xc, R3 ; /* 0x0000000cff037819 */
/* 0x000fca0000011603 */
/*00e0*/ IMAD R2, R3, -0x1800, R4 ; /* 0xffffe80003027824 */
/* 0x000fe200078e0204 */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fce00000001ff */
/*0100*/ STS.64 [R0.X8], R2 ; /* 0x0000000200007388 */
/* 0x0001e40000008a00 */
/*0110*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x001fca00078e0200 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf26070 */
/*0130*/ @!P1 BRA 0xb0 ; /* 0xffffff7000009947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ CS2R.32 R0, SR_CLOCKLO ; /* 0x0000000000007805 */
/* 0x000fe40000005000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0180*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0190*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*01a0*/ IMAD.SHL.U32 R4, R4, 0x8, RZ ; /* 0x0000000804047824 */
/* 0x001fe200078e00ff */
/*01b0*/ IADD3 R2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.NE.AND P0, PT, R2, 0x800, PT ; /* 0x000008000200780c */
/* 0x000fe20003f05270 */
/*01d0*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*01e0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*01f0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0200*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0210*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0220*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0230*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0240*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0250*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0260*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0270*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0280*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0290*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*02a0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*02b0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*02c0*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*02d0*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*02e0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*02f0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0300*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0310*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0320*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0330*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0340*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0350*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*0360*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*0370*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0380*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0390*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*03a0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*03b0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*03c0*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*03d0*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*03e0*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*03f0*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0400*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0410*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*0420*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*0430*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0440*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0450*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0460*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0470*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0480*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0490*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*04a0*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*04b0*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*04c0*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*04d0*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*04e0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*04f0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0500*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0510*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0520*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0530*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0540*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0550*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0560*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0570*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0580*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0590*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*05a0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*05b0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*05c0*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*05d0*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*05e0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*05f0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0600*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0610*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0620*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0630*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0640*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0650*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*0660*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*0670*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0680*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0690*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*06a0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*06b0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*06c0*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*06d0*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*06e0*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*06f0*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0700*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0710*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*0720*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*0730*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0740*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0750*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0760*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0770*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0780*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0790*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*07a0*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*07b0*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*07c0*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*07d0*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*07e0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*07f0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0800*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0810*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0820*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0830*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0840*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0850*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0860*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0870*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0880*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0890*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*08a0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*08b0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*08c0*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*08d0*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*08e0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*08f0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0900*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0910*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0920*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0930*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0940*/ IMAD.SHL.U32 R9, R8, 0x8, RZ ; /* 0x0000000808097824 */
/* 0x001fcc00078e00ff */
/*0950*/ LDS R9, [R9] ; /* 0x0000000009097984 */
/* 0x000e240000000800 */
/*0960*/ SHF.L.U32 R3, R9, 0x3, RZ ; /* 0x0000000309037819 */
/* 0x001fcc00000006ff */
/*0970*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0980*/ IMAD.SHL.U32 R10, R3, 0x8, RZ ; /* 0x00000008030a7824 */
/* 0x001fcc00078e00ff */
/*0990*/ LDS R10, [R10] ; /* 0x000000000a0a7984 */
/* 0x000e240000000800 */
/*09a0*/ SHF.L.U32 R4, R10, 0x3, RZ ; /* 0x000000030a047819 */
/* 0x001fcc00000006ff */
/*09b0*/ LDS.64 R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e220000000a00 */
/*09c0*/ @P0 BRA 0x1a0 ; /* 0xfffff7d000000947 */
/* 0x000fea000383ffff */
/*09d0*/ CS2R.32 R11, SR_CLOCKLO ; /* 0x00000000000b7805 */
/* 0x000fe40000005000 */
/*09e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*09f0*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0a00*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fe200078e00ff */
/*0a10*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*0a20*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff087624 */
/* 0x000fe200078e00ff */
/*0a30*/ MOV R9, c[0x0][0x174] ; /* 0x00005d0000097a02 */
/* 0x000fe20000000f00 */
/*0a40*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0a50*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0a60*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x001fe2000c101b04 */
/*0a70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a80*/ BRA 0xa80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //This code is a modification of L1 cache benchmark from
//"Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking": https://arxiv.org/pdf/1804.06826.pdf
//This benchmark measures the latency of L1 cache
//This code have been tested on Volta V100 architecture
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define SHARED_MEM_SIZE_BYTE (48*1024) //size in bytes, max 96KB for v100
#define SHARED_MEM_SIZE (SHARED_MEM_SIZE_BYTE/8)
#define THREADS_NUM 32 //Launch only one thread to calcaulte the latency using a pointer-chasing array technique
#define WARP_SIZE 32
#define ITERS 2048 //iterate over the array ITERS times
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//TO DO: @Jason, please change the code to be similar to the L2/DRAM latency format
//Measure latency of ITERS reads.
__global__ void shared_lat(uint32_t *startClk, uint32_t *stopClk, uint64_t *dsink, uint32_t stride){
// thread index
uint32_t tid = threadIdx.x;
uint32_t bid = blockIdx.x;
uint32_t uid = bid*blockDim.x+tid;
uint32_t n_threads = blockDim.x * gridDim.x;
__shared__ uint64_t s[SHARED_MEM_SIZE]; //static shared memory
// one thread to initialize the pointer-chasing array
for (uint32_t i=uid; i<(SHARED_MEM_SIZE-stride); i+=n_threads)
s[i] = (i+stride)%SHARED_MEM_SIZE;
if(uid == 0){
//initalize pointer chaser
uint64_t p_chaser = 0;
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
// pointer-chasing ITERS times
// use ca modifier to cache the load in L1
for(uint32_t i=0; i<ITERS; ++i) {
p_chaser = s[p_chaser];
}
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[uid] = start;
stopClk[uid] = stop;
dsink[uid] = p_chaser;
}
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(sizeof(uint32_t));
uint64_t *dsink = (uint64_t*) malloc(sizeof(uint64_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
uint64_t *dsink_g;
gpuErrchk( cudaMalloc(&startClk_g, sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&dsink_g, sizeof(uint64_t)) );
shared_lat<<<1,THREADS_NUM>>>(startClk_g, stopClk_g, dsink_g, 1);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(dsink, dsink_g, sizeof(uint64_t), cudaMemcpyDeviceToHost) );
printf("Shared Memory Latency = %f cycles\n", (float)(stopClk[0]-startClk[0])/ITERS );
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
printf("start clk = %u \n", startClk[0]);
printf("stop clk = %u \n", stopClk[0]);
return 0;
} | .file "tmpxft_00137c55_00000000-6_shared_lat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj
.type _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj, @function
_Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10shared_latPjS_Pmj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj, .-_Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj
.globl _Z10shared_latPjS_Pmj
.type _Z10shared_latPjS_Pmj, @function
_Z10shared_latPjS_Pmj:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10shared_latPjS_Pmj, .-_Z10shared_latPjS_Pmj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/shared_lat/shared_lat.cu"
.align 8
.LC3:
.string "Shared Memory Latency = %f cycles\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Total Clk number = %u \n"
.LC5:
.string "start clk = %u \n"
.LC6:
.string "stop clk = %u \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $8, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $79, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $80, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $81, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $87, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $88, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl (%rbx), %eax
subl 0(%rbp), %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl (%rbx), %edx
subl 0(%rbp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%rbp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $1, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10shared_latPjS_Pmj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10shared_latPjS_Pmj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 973078528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //This code is a modification of L1 cache benchmark from
//"Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking": https://arxiv.org/pdf/1804.06826.pdf
//This benchmark measures the latency of L1 cache
//This code have been tested on Volta V100 architecture
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define SHARED_MEM_SIZE_BYTE (48*1024) //size in bytes, max 96KB for v100
#define SHARED_MEM_SIZE (SHARED_MEM_SIZE_BYTE/8)
#define THREADS_NUM 32 //Launch only one thread to calcaulte the latency using a pointer-chasing array technique
#define WARP_SIZE 32
#define ITERS 2048 //iterate over the array ITERS times
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//TO DO: @Jason, please change the code to be similar to the L2/DRAM latency format
//Measure latency of ITERS reads.
__global__ void shared_lat(uint32_t *startClk, uint32_t *stopClk, uint64_t *dsink, uint32_t stride){
// thread index
uint32_t tid = threadIdx.x;
uint32_t bid = blockIdx.x;
uint32_t uid = bid*blockDim.x+tid;
uint32_t n_threads = blockDim.x * gridDim.x;
__shared__ uint64_t s[SHARED_MEM_SIZE]; //static shared memory
// one thread to initialize the pointer-chasing array
for (uint32_t i=uid; i<(SHARED_MEM_SIZE-stride); i+=n_threads)
s[i] = (i+stride)%SHARED_MEM_SIZE;
if(uid == 0){
//initalize pointer chaser
uint64_t p_chaser = 0;
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
// pointer-chasing ITERS times
// use ca modifier to cache the load in L1
for(uint32_t i=0; i<ITERS; ++i) {
p_chaser = s[p_chaser];
}
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[uid] = start;
stopClk[uid] = stop;
dsink[uid] = p_chaser;
}
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(sizeof(uint32_t));
uint64_t *dsink = (uint64_t*) malloc(sizeof(uint64_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
uint64_t *dsink_g;
gpuErrchk( cudaMalloc(&startClk_g, sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&dsink_g, sizeof(uint64_t)) );
shared_lat<<<1,THREADS_NUM>>>(startClk_g, stopClk_g, dsink_g, 1);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(dsink, dsink_g, sizeof(uint64_t), cudaMemcpyDeviceToHost) );
printf("Shared Memory Latency = %f cycles\n", (float)(stopClk[0]-startClk[0])/ITERS );
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
printf("start clk = %u \n", startClk[0]);
printf("stop clk = %u \n", stopClk[0]);
return 0;
} | //This code is a modification of L1 cache benchmark from
//"Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking": https://arxiv.org/pdf/1804.06826.pdf
//This benchmark measures the latency of L1 cache
//This code have been tested on Volta V100 architecture
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define SHARED_MEM_SIZE_BYTE (48*1024) //size in bytes, max 96KB for v100
#define SHARED_MEM_SIZE (SHARED_MEM_SIZE_BYTE/8)
#define THREADS_NUM 32 //Launch only one thread to calcaulte the latency using a pointer-chasing array technique
#define WARP_SIZE 32
#define ITERS 2048 //iterate over the array ITERS times
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//TO DO: @Jason, please change the code to be similar to the L2/DRAM latency format
//Measure latency of ITERS reads.
__global__ void shared_lat(uint32_t *startClk, uint32_t *stopClk, uint64_t *dsink, uint32_t stride){
// thread index
uint32_t tid = threadIdx.x;
uint32_t bid = blockIdx.x;
uint32_t uid = bid*blockDim.x+tid;
uint32_t n_threads = blockDim.x * gridDim.x;
__shared__ uint64_t s[SHARED_MEM_SIZE]; //static shared memory
// one thread to initialize the pointer-chasing array
for (uint32_t i=uid; i<(SHARED_MEM_SIZE-stride); i+=n_threads)
s[i] = (i+stride)%SHARED_MEM_SIZE;
if(uid == 0){
//initalize pointer chaser
uint64_t p_chaser = 0;
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
// pointer-chasing ITERS times
// use ca modifier to cache the load in L1
for(uint32_t i=0; i<ITERS; ++i) {
p_chaser = s[p_chaser];
}
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[uid] = start;
stopClk[uid] = stop;
dsink[uid] = p_chaser;
}
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(sizeof(uint32_t));
uint64_t *dsink = (uint64_t*) malloc(sizeof(uint64_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
uint64_t *dsink_g;
gpuErrchk( hipMalloc(&startClk_g, sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&dsink_g, sizeof(uint64_t)) );
shared_lat<<<1,THREADS_NUM>>>(startClk_g, stopClk_g, dsink_g, 1);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(dsink, dsink_g, sizeof(uint64_t), hipMemcpyDeviceToHost) );
printf("Shared Memory Latency = %f cycles\n", (float)(stopClk[0]-startClk[0])/ITERS );
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
printf("start clk = %u \n", startClk[0]);
printf("stop clk = %u \n", stopClk[0]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //This code is a modification of L1 cache benchmark from
//"Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking": https://arxiv.org/pdf/1804.06826.pdf
//This benchmark measures the latency of L1 cache
//This code have been tested on Volta V100 architecture
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define SHARED_MEM_SIZE_BYTE (48*1024) //size in bytes, max 96KB for v100
#define SHARED_MEM_SIZE (SHARED_MEM_SIZE_BYTE/8)
#define THREADS_NUM 32 //Launch only one thread to calcaulte the latency using a pointer-chasing array technique
#define WARP_SIZE 32
#define ITERS 2048 //iterate over the array ITERS times
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//TO DO: @Jason, please change the code to be similar to the L2/DRAM latency format
//Measure latency of ITERS reads.
__global__ void shared_lat(uint32_t *startClk, uint32_t *stopClk, uint64_t *dsink, uint32_t stride){
// thread index
uint32_t tid = threadIdx.x;
uint32_t bid = blockIdx.x;
uint32_t uid = bid*blockDim.x+tid;
uint32_t n_threads = blockDim.x * gridDim.x;
__shared__ uint64_t s[SHARED_MEM_SIZE]; //static shared memory
// one thread to initialize the pointer-chasing array
for (uint32_t i=uid; i<(SHARED_MEM_SIZE-stride); i+=n_threads)
s[i] = (i+stride)%SHARED_MEM_SIZE;
if(uid == 0){
//initalize pointer chaser
uint64_t p_chaser = 0;
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
// pointer-chasing ITERS times
// use ca modifier to cache the load in L1
for(uint32_t i=0; i<ITERS; ++i) {
p_chaser = s[p_chaser];
}
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[uid] = start;
stopClk[uid] = stop;
dsink[uid] = p_chaser;
}
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(sizeof(uint32_t));
uint64_t *dsink = (uint64_t*) malloc(sizeof(uint64_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
uint64_t *dsink_g;
gpuErrchk( hipMalloc(&startClk_g, sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&dsink_g, sizeof(uint64_t)) );
shared_lat<<<1,THREADS_NUM>>>(startClk_g, stopClk_g, dsink_g, 1);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(dsink, dsink_g, sizeof(uint64_t), hipMemcpyDeviceToHost) );
printf("Shared Memory Latency = %f cycles\n", (float)(stopClk[0]-startClk[0])/ITERS );
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
printf("start clk = %u \n", startClk[0]);
printf("stop clk = %u \n", stopClk[0]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10shared_latPjS_Pmj
.globl _Z10shared_latPjS_Pmj
.p2align 8
.type _Z10shared_latPjS_Pmj,@function
_Z10shared_latPjS_Pmj:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s5, 0xffff
s_sub_i32 s5, 0x1800, s4
s_mul_i32 s15, s15, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s15, v0
v_cmpx_gt_u32_e64 s5, v2
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
v_add3_u32 v3, s15, s4, v0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 3, v2
s_mov_b32 s3, 0
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s7, s2, 3
.p2align 6
.LBB0_2:
v_mul_hi_u32 v0, v3, 0xaaaaaaab
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v0, 12, v0
v_mul_u32_u24_e32 v0, 0x1800, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, s4, v0
v_add3_u32 v0, v2, s8, v0
s_add_i32 s8, s8, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s8, v2
ds_store_b64 v4, v[0:1]
v_add_nc_u32_e32 v4, s7, v4
v_cmp_le_u32_e32 vcc_lo, s5, v5
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_7
mov.u32 s2, %clock
s_movk_i32 s3, 0x800
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v0, 3, v0
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
ds_load_b64 v[0:1], v0
s_cbranch_scc0 .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s2
mov.u32 s3, %clock
v_mov_b32_e32 v4, s3
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_store_b32 v2, v3, s[4:5]
global_store_b32 v2, v4, s[6:7]
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10shared_latPjS_Pmj
.amdhsa_group_segment_fixed_size 49152
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10shared_latPjS_Pmj, .Lfunc_end0-_Z10shared_latPjS_Pmj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 49152
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10shared_latPjS_Pmj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10shared_latPjS_Pmj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //This code is a modification of L1 cache benchmark from
//"Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking": https://arxiv.org/pdf/1804.06826.pdf
//This benchmark measures the latency of L1 cache
//This code have been tested on Volta V100 architecture
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define SHARED_MEM_SIZE_BYTE (48*1024) //size in bytes, max 96KB for v100
#define SHARED_MEM_SIZE (SHARED_MEM_SIZE_BYTE/8)
#define THREADS_NUM 32 //Launch only one thread to calcaulte the latency using a pointer-chasing array technique
#define WARP_SIZE 32
#define ITERS 2048 //iterate over the array ITERS times
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//TO DO: @Jason, please change the code to be similar to the L2/DRAM latency format
//Measure latency of ITERS reads.
__global__ void shared_lat(uint32_t *startClk, uint32_t *stopClk, uint64_t *dsink, uint32_t stride){
// thread index
uint32_t tid = threadIdx.x;
uint32_t bid = blockIdx.x;
uint32_t uid = bid*blockDim.x+tid;
uint32_t n_threads = blockDim.x * gridDim.x;
__shared__ uint64_t s[SHARED_MEM_SIZE]; //static shared memory
// one thread to initialize the pointer-chasing array
for (uint32_t i=uid; i<(SHARED_MEM_SIZE-stride); i+=n_threads)
s[i] = (i+stride)%SHARED_MEM_SIZE;
if(uid == 0){
//initalize pointer chaser
uint64_t p_chaser = 0;
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
// pointer-chasing ITERS times
// use ca modifier to cache the load in L1
for(uint32_t i=0; i<ITERS; ++i) {
p_chaser = s[p_chaser];
}
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[uid] = start;
stopClk[uid] = stop;
dsink[uid] = p_chaser;
}
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(sizeof(uint32_t));
uint64_t *dsink = (uint64_t*) malloc(sizeof(uint64_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
uint64_t *dsink_g;
gpuErrchk( hipMalloc(&startClk_g, sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&dsink_g, sizeof(uint64_t)) );
shared_lat<<<1,THREADS_NUM>>>(startClk_g, stopClk_g, dsink_g, 1);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(dsink, dsink_g, sizeof(uint64_t), hipMemcpyDeviceToHost) );
printf("Shared Memory Latency = %f cycles\n", (float)(stopClk[0]-startClk[0])/ITERS );
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
printf("start clk = %u \n", startClk[0]);
printf("stop clk = %u \n", stopClk[0]);
return 0;
} | .text
.file "shared_lat.hip"
.globl _Z25__device_stub__shared_latPjS_Pmj # -- Begin function _Z25__device_stub__shared_latPjS_Pmj
.p2align 4, 0x90
.type _Z25__device_stub__shared_latPjS_Pmj,@function
_Z25__device_stub__shared_latPjS_Pmj: # @_Z25__device_stub__shared_latPjS_Pmj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10shared_latPjS_Pmj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__shared_latPjS_Pmj, .Lfunc_end0-_Z25__device_stub__shared_latPjS_Pmj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3a000000 # float 4.8828125E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $8, %edi
callq malloc
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit12
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit14
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10shared_latPjS_Pmj, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit16
movq 32(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit18
movq 24(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit20
movq 16(%rsp), %rsi
movl $8, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit22
movl (%rbx), %eax
subl (%r14), %eax
cvtsi2ss %rax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl (%rbx), %esi
subl (%r14), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl (%r14), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $80, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $81, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10shared_latPjS_Pmj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10shared_latPjS_Pmj,@object # @_Z10shared_latPjS_Pmj
.section .rodata,"a",@progbits
.globl _Z10shared_latPjS_Pmj
.p2align 3, 0x0
_Z10shared_latPjS_Pmj:
.quad _Z25__device_stub__shared_latPjS_Pmj
.size _Z10shared_latPjS_Pmj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/shared_lat/shared_lat.hip"
.size .L.str, 163
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Shared Memory Latency = %f cycles\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total Clk number = %u \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "start clk = %u \n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "stop clk = %u \n"
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10shared_latPjS_Pmj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__shared_latPjS_Pmj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10shared_latPjS_Pmj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10shared_latPjS_Pmj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIADD3 UR4, -UR4, 0x1800, URZ ; /* 0x0000180004047890 */
/* 0x000fe2000fffe13f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe4000bf26070 */
/*0080*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f05270 */
/*0090*/ @P1 BRA 0x140 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe400078e00ff */
/*00b0*/ IADD3 R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x000fca0007ffe0ff */
/*00c0*/ IMAD.WIDE.U32 R2, R4, -0x55555555, RZ ; /* 0xaaaaaaab04027825 */
/* 0x000fca00078e00ff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0xc, R3 ; /* 0x0000000cff037819 */
/* 0x000fca0000011603 */
/*00e0*/ IMAD R2, R3, -0x1800, R4 ; /* 0xffffe80003027824 */
/* 0x000fe200078e0204 */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fce00000001ff */
/*0100*/ STS.64 [R0.X8], R2 ; /* 0x0000000200007388 */
/* 0x0001e40000008a00 */
/*0110*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x001fca00078e0200 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf26070 */
/*0130*/ @!P1 BRA 0xb0 ; /* 0xffffff7000009947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ CS2R.32 R0, SR_CLOCKLO ; /* 0x0000000000007805 */
/* 0x000fe40000005000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0180*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0190*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*01a0*/ IMAD.SHL.U32 R4, R4, 0x8, RZ ; /* 0x0000000804047824 */
/* 0x001fe200078e00ff */
/*01b0*/ IADD3 R2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.NE.AND P0, PT, R2, 0x800, PT ; /* 0x000008000200780c */
/* 0x000fe20003f05270 */
/*01d0*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*01e0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*01f0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0200*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0210*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0220*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0230*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0240*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0250*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0260*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0270*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0280*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0290*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*02a0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*02b0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*02c0*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*02d0*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*02e0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*02f0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0300*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0310*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0320*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0330*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0340*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0350*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*0360*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*0370*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0380*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0390*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*03a0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*03b0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*03c0*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*03d0*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*03e0*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*03f0*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0400*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0410*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*0420*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*0430*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0440*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0450*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0460*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0470*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0480*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0490*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*04a0*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*04b0*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*04c0*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*04d0*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*04e0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*04f0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0500*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0510*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0520*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0530*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0540*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0550*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0560*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0570*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0580*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0590*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*05a0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*05b0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*05c0*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*05d0*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*05e0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*05f0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0600*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0610*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0620*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0630*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0640*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0650*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*0660*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*0670*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0680*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0690*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*06a0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*06b0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*06c0*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*06d0*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*06e0*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*06f0*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0700*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0710*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*0720*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*0730*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0740*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0750*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0760*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0770*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0780*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0790*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*07a0*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*07b0*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*07c0*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*07d0*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*07e0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*07f0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0800*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*0810*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*0820*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*0830*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0840*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0850*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0860*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0870*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0880*/ IMAD.SHL.U32 R4, R8, 0x8, RZ ; /* 0x0000000808047824 */
/* 0x001fcc00078e00ff */
/*0890*/ LDS R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e240000000800 */
/*08a0*/ SHF.L.U32 R3, R4, 0x3, RZ ; /* 0x0000000304037819 */
/* 0x001fcc00000006ff */
/*08b0*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*08c0*/ IMAD.SHL.U32 R5, R3, 0x8, RZ ; /* 0x0000000803057824 */
/* 0x001fcc00078e00ff */
/*08d0*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*08e0*/ SHF.L.U32 R6, R5, 0x3, RZ ; /* 0x0000000305067819 */
/* 0x001fcc00000006ff */
/*08f0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0900*/ IMAD.SHL.U32 R7, R6, 0x8, RZ ; /* 0x0000000806077824 */
/* 0x001fcc00078e00ff */
/*0910*/ LDS R7, [R7] ; /* 0x0000000007077984 */
/* 0x000e240000000800 */
/*0920*/ SHF.L.U32 R8, R7, 0x3, RZ ; /* 0x0000000307087819 */
/* 0x001fcc00000006ff */
/*0930*/ LDS R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000800 */
/*0940*/ IMAD.SHL.U32 R9, R8, 0x8, RZ ; /* 0x0000000808097824 */
/* 0x001fcc00078e00ff */
/*0950*/ LDS R9, [R9] ; /* 0x0000000009097984 */
/* 0x000e240000000800 */
/*0960*/ SHF.L.U32 R3, R9, 0x3, RZ ; /* 0x0000000309037819 */
/* 0x001fcc00000006ff */
/*0970*/ LDS R3, [R3] ; /* 0x0000000003037984 */
/* 0x000e240000000800 */
/*0980*/ IMAD.SHL.U32 R10, R3, 0x8, RZ ; /* 0x00000008030a7824 */
/* 0x001fcc00078e00ff */
/*0990*/ LDS R10, [R10] ; /* 0x000000000a0a7984 */
/* 0x000e240000000800 */
/*09a0*/ SHF.L.U32 R4, R10, 0x3, RZ ; /* 0x000000030a047819 */
/* 0x001fcc00000006ff */
/*09b0*/ LDS.64 R4, [R4] ; /* 0x0000000004047984 */
/* 0x000e220000000a00 */
/*09c0*/ @P0 BRA 0x1a0 ; /* 0xfffff7d000000947 */
/* 0x000fea000383ffff */
/*09d0*/ CS2R.32 R11, SR_CLOCKLO ; /* 0x00000000000b7805 */
/* 0x000fe40000005000 */
/*09e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*09f0*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0a00*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fe200078e00ff */
/*0a10*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*0a20*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff087624 */
/* 0x000fe200078e00ff */
/*0a30*/ MOV R9, c[0x0][0x174] ; /* 0x00005d0000097a02 */
/* 0x000fe20000000f00 */
/*0a40*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0a50*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0a60*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x001fe2000c101b04 */
/*0a70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a80*/ BRA 0xa80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10shared_latPjS_Pmj
.globl _Z10shared_latPjS_Pmj
.p2align 8
.type _Z10shared_latPjS_Pmj,@function
_Z10shared_latPjS_Pmj:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s5, 0xffff
s_sub_i32 s5, 0x1800, s4
s_mul_i32 s15, s15, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s15, v0
v_cmpx_gt_u32_e64 s5, v2
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
v_add3_u32 v3, s15, s4, v0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 3, v2
s_mov_b32 s3, 0
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s7, s2, 3
.p2align 6
.LBB0_2:
v_mul_hi_u32 v0, v3, 0xaaaaaaab
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v0, 12, v0
v_mul_u32_u24_e32 v0, 0x1800, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, s4, v0
v_add3_u32 v0, v2, s8, v0
s_add_i32 s8, s8, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s8, v2
ds_store_b64 v4, v[0:1]
v_add_nc_u32_e32 v4, s7, v4
v_cmp_le_u32_e32 vcc_lo, s5, v5
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_7
mov.u32 s2, %clock
s_movk_i32 s3, 0x800
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v0, 3, v0
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
ds_load_b64 v[0:1], v0
s_cbranch_scc0 .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s2
mov.u32 s3, %clock
v_mov_b32_e32 v4, s3
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_store_b32 v2, v3, s[4:5]
global_store_b32 v2, v4, s[6:7]
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10shared_latPjS_Pmj
.amdhsa_group_segment_fixed_size 49152
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10shared_latPjS_Pmj, .Lfunc_end0-_Z10shared_latPjS_Pmj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 49152
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10shared_latPjS_Pmj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10shared_latPjS_Pmj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00137c55_00000000-6_shared_lat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj
.type _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj, @function
_Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10shared_latPjS_Pmj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj, .-_Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj
.globl _Z10shared_latPjS_Pmj
.type _Z10shared_latPjS_Pmj, @function
_Z10shared_latPjS_Pmj:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10shared_latPjS_Pmj, .-_Z10shared_latPjS_Pmj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/shared_lat/shared_lat.cu"
.align 8
.LC3:
.string "Shared Memory Latency = %f cycles\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Total Clk number = %u \n"
.LC5:
.string "start clk = %u \n"
.LC6:
.string "stop clk = %u \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $8, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $79, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $80, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $81, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $87, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $88, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl (%rbx), %eax
subl 0(%rbp), %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl (%rbx), %edx
subl 0(%rbp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%rbp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $1, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10shared_latPjS_PmjPjS_Pmj
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10shared_latPjS_Pmj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10shared_latPjS_Pmj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 973078528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "shared_lat.hip"
.globl _Z25__device_stub__shared_latPjS_Pmj # -- Begin function _Z25__device_stub__shared_latPjS_Pmj
.p2align 4, 0x90
.type _Z25__device_stub__shared_latPjS_Pmj,@function
_Z25__device_stub__shared_latPjS_Pmj: # @_Z25__device_stub__shared_latPjS_Pmj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10shared_latPjS_Pmj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__shared_latPjS_Pmj, .Lfunc_end0-_Z25__device_stub__shared_latPjS_Pmj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3a000000 # float 4.8828125E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $8, %edi
callq malloc
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit12
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit14
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10shared_latPjS_Pmj, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit16
movq 32(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit18
movq 24(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit20
movq 16(%rsp), %rsi
movl $8, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit22
movl (%rbx), %eax
subl (%r14), %eax
cvtsi2ss %rax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl (%rbx), %esi
subl (%r14), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl (%r14), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $80, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $81, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10shared_latPjS_Pmj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10shared_latPjS_Pmj,@object # @_Z10shared_latPjS_Pmj
.section .rodata,"a",@progbits
.globl _Z10shared_latPjS_Pmj
.p2align 3, 0x0
_Z10shared_latPjS_Pmj:
.quad _Z25__device_stub__shared_latPjS_Pmj
.size _Z10shared_latPjS_Pmj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/shared_lat/shared_lat.hip"
.size .L.str, 163
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Shared Memory Latency = %f cycles\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total Clk number = %u \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "start clk = %u \n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "stop clk = %u \n"
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10shared_latPjS_Pmj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__shared_latPjS_Pmj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10shared_latPjS_Pmj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
// both M and N must be evenly divisible by SIZE, M must be evenly divisible by CHKSIZE
#define SIZE 2
#define N 2
#define M 3
#define CHKSIZE 1
//naive kernel
__global__ void EuclideanDistancesNaive(float *A, float *B, float *C, int n,
int m) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
float result = 0.0f;
if ((idx < n) && (idy < m)) {
for (int i = 0; i < SIZE; i++) {
float temp = A[(idx * SIZE) + i] - B[(idy * SIZE) + i];
result += temp * temp;
}
C[(idx * m) + idy] = result;
}
}
//optimized kernel
__global__ void EuclideanDistancesFast(const float *A, const float *B, float *C,
const int n, const int m) {
// n, A, 4000 this kernel assumes A is column-major A(SIZE, n)
// m, B, 20000 this kernel assumes B is row-major B(m, SIZE)
// this kernel assumes C is column-major C(m,n)
// this kernel assumes number of threads per threadblock == SIZE
// CHKSIZE is the number of B vectors that will be compute per block
__shared__ float my_sB[CHKSIZE * SIZE]; // enough shared storage for CHKSIZE vectors of B
int bx = blockIdx.x; // one block per CHKSIZE rows of B (the larger input matrix)
while ((bx * CHKSIZE) < m) { // not used, this while loop could be used to extend a block to multiple chunks
int tx = threadIdx.x;
for (int i = 0; i < CHKSIZE; i++) // load vectors of B into shared memory
my_sB[(i * SIZE) + tx] = B[(((bx * CHKSIZE) + i) * SIZE) + tx];
__syncthreads();
while (tx < n) { //loop across all vectors in A
float result[CHKSIZE];
for (int i = 0; i < CHKSIZE; i++)
result[i] = 0.0f;
for (int i = 0; i < SIZE; i++) {
float Atemp = A[(n * i) + tx];
for (int j = 0; j < CHKSIZE; j++) { // compute all CHKSIZE B vectors with read of A
float temp = Atemp - my_sB[i + (j * SIZE)];
result[j] += temp * temp;
}
}
for (int i = 0; i < CHKSIZE; i++) // store CHKSIZE results
C[((i + (bx * CHKSIZE)) * n) + tx] = result[i];
tx += blockDim.x;
} // continue looping across vectors in A
__syncthreads(); // necessary to prevent warps from racing ahead, if block looping is used
bx += gridDim.x;
}
}
float comp_euclid_sq(const float *rA, const float *rB, const int size) {
float result = 0.0f;
float temp;
for (int i = 0; i < size; i++) {
temp = (rA[i] - rB[i]);
result += temp * temp;
}
return result;
}
int main_ed_gpu() {
float cpu_time = 0.0f, et1 = 0.0f, et2 = 0.0f, et_mem = 0.0f;
cudaEvent_t start1, start2, stop1, stop2, start_mem_copy, stop_mem_copy;
cudaEventCreate(&start1);
cudaEventCreate(&start2);
cudaEventCreate(&start_mem_copy);
cudaEventCreate(&stop1);
cudaEventCreate(&stop2);
cudaEventCreate(&stop_mem_copy);
int n = N; //MatrixA size : n * SIZE
int m = M; //MatrixB size : m * SIZE
srand((unsigned) time(0));
// Host Allocations
float *matrixA = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n * SIZE; i++)
matrixA[i] = (float) i + 1;
float *matrixB = (float *) malloc(m * SIZE * sizeof(float));
for (int i = 0; i < m * SIZE; i++)
matrixB[i] = (float) i + i;
const clock_t begin_time = clock();
float *results_kernel = (float *) malloc(n * m * sizeof(float));
float *cpu_results_kernel = (float *) malloc(n * m * sizeof(float));
for (int i = 0; i < n * m; i++)
cpu_results_kernel[i] = comp_euclid_sq(matrixA + ((i / m) * SIZE),
matrixB + (i % m) * SIZE, SIZE);
cpu_time = float( clock () - begin_time ) / 1000;
//Device Allocation
cudaEventRecord(start_mem_copy);
float *d_matrixA;
float *d_matrixB;
cudaMalloc((void **) &d_matrixA, n * SIZE * sizeof(float));
cudaMalloc((void **) &d_matrixB, m * SIZE * sizeof(float));
cudaMemcpy(d_matrixA, matrixA, n * SIZE * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(d_matrixB, matrixB, m * SIZE * sizeof(float),
cudaMemcpyHostToDevice);
cudaEventElapsedTime(&et_mem, start_mem_copy, stop_mem_copy);
float *d_results_kernel;
cudaMalloc((void **) &d_results_kernel, n * m * sizeof(float));
cudaFuncSetCacheConfig(EuclideanDistancesNaive, cudaFuncCachePreferL1);
dim3 threads3(8, 32); // 1024 threads per block (maximum)
dim3 blocks3(n / threads3.x, m / threads3.y); // assumes evenly divisible
cudaEventRecord(start1);
EuclideanDistancesNaive<<<blocks3, threads3>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
cudaEventRecord(stop1);
cudaMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
cudaMemcpyDeviceToHost);
// for (int i = 0; i < n * m; i++) {
// if (results_kernel[i] != cpu_results_kernel[i]) {
// printf("cpu/kernel3 mismatch at %d, cpu: %f, kernel3: %f\n", i,
// cpu_results_kernel[i], results_kernel[i]);
// return 1;
// }
// }
cudaMemset(d_results_kernel, 0, n * m * sizeof(float));
cudaEventSynchronize(stop1);
cudaEventElapsedTime(&et1, start1, stop1);
// transpose matrix A
float *matrixA_T = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n; i++)
for (int j = 0; j < SIZE; j++)
matrixA_T[(j * n) + i] = matrixA[(i * SIZE) + j];
cudaMemcpy(d_matrixA, matrixA_T, n * SIZE * sizeof(float),
cudaMemcpyHostToDevice);
cudaFuncSetCacheConfig(EuclideanDistancesFast, cudaFuncCachePreferL1);
dim3 threads4(SIZE); // one thread per vector element
dim3 blocks4(m / CHKSIZE);
cudaEventRecord(start2);
EuclideanDistancesFast<<<blocks4, threads4>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
cudaEventRecord(stop2);
cudaMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
cudaMemcpyDeviceToHost);
// test for correct transposed result C(m,n)
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
printf("%f ", results_kernel[(j * n) + i]);
if (results_kernel[(j * n) + i]
!= cpu_results_kernel[(i * m) + j]) {
printf("cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n",
i, j, cpu_results_kernel[(i * m) + j],
results_kernel[(j * n) + i]);
return 1;
}
}
printf("\n");
}
cudaEventSynchronize(stop2);
cudaEventElapsedTime(&et2, start2, stop2);
cudaFree(d_results_kernel);
printf("Success!\n");
printf("CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n",
cpu_time, et1, et2, et_mem);
free(matrixA);
free(matrixB);
free(results_kernel);
return 0;
} | code for sm_80
Function : _Z22EuclideanDistancesFastPKfS0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0070*/ LEA R2, R0, R15, 0x1 ; /* 0x0000000f00027211 */
/* 0x001fd200078e08ff */
/*0080*/ IMAD.WIDE R2, R2, R17, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0211 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ BSSY B0, 0x200 ; /* 0x0000014000007945 */
/* 0x000fe40003800000 */
/*00c0*/ STS [R15.X4], R2 ; /* 0x000000020f007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 BRA 0x1f0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*00f0*/ LDS.64 R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x001e220000000a00 */
/*0100*/ MOV R11, R15 ; /* 0x0000000f000b7202 */
/* 0x000fca0000000f00 */
/*0110*/ IMAD.WIDE R4, R11, R17, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fca00078e0211 */
/*0120*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001ea2000c1e1900 */
/*0130*/ IMAD.WIDE R6, R17, c[0x0][0x178], R4 ; /* 0x00005e0011067a25 */
/* 0x000fcc00078e0204 */
/*0140*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0150*/ IMAD R8, R0, c[0x0][0x178], R11 ; /* 0x00005e0000087a24 */
/* 0x000fe200078e020b */
/*0160*/ IADD3 R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b7a10 */
/* 0x000fc80007ffe0ff */
/*0170*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fe20003f06270 */
/*0180*/ FADD R9, -R2, R9 ; /* 0x0000000902097221 */
/* 0x005fc80000000100 */
/*0190*/ FFMA R10, R9, R9, RZ ; /* 0x00000009090a7223 */
/* 0x000fe400000000ff */
/*01a0*/ IMAD.WIDE R8, R8, R17, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fc800078e0211 */
/*01b0*/ FADD R13, R6, -R3 ; /* 0x80000003060d7221 */
/* 0x008fc80000000000 */
/*01c0*/ FFMA R13, R13, R13, R10 ; /* 0x0000000d0d0d7223 */
/* 0x000fca000000000a */
/*01d0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001e2000c101904 */
/*01e0*/ @!P0 BRA 0x110 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0200*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fe20007ffe0ff */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0220*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0230*/ @!P0 BRA 0x60 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z23EuclideanDistancesNaivePfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*00b0*/ SHF.L.U32 R4, R7, 0x1, RZ ; /* 0x0000000107047819 */
/* 0x000fe200000006ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ SHF.L.U32 R2, R0, 0x1, RZ ; /* 0x0000000100027819 */
/* 0x000fce00000006ff */
/*00e0*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020d */
/*00f0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e020d */
/*0100*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee2000c1e1900 */
/*0140*/ IMAD R7, R0, c[0x0][0x17c], R7 ; /* 0x00005f0000077a24 */
/* 0x000fc400078e0207 */
/*0150*/ FADD R6, -R6, R9 ; /* 0x0000000906067221 */
/* 0x004fc80000000100 */
/*0160*/ FFMA R0, R6, R6, RZ ; /* 0x0000000606007223 */
/* 0x000fe400000000ff */
/*0170*/ IMAD.WIDE R6, R7, R13, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fc800078e020d */
/*0180*/ FADD R11, -R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc80000000100 */
/*0190*/ FFMA R11, R11, R11, R0 ; /* 0x0000000b0b0b7223 */
/* 0x000fca0000000000 */
/*01a0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
// both M and N must be evenly divisible by SIZE, M must be evenly divisible by CHKSIZE
#define SIZE 2
#define N 2
#define M 3
#define CHKSIZE 1
//naive kernel
__global__ void EuclideanDistancesNaive(float *A, float *B, float *C, int n,
int m) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
float result = 0.0f;
if ((idx < n) && (idy < m)) {
for (int i = 0; i < SIZE; i++) {
float temp = A[(idx * SIZE) + i] - B[(idy * SIZE) + i];
result += temp * temp;
}
C[(idx * m) + idy] = result;
}
}
//optimized kernel
__global__ void EuclideanDistancesFast(const float *A, const float *B, float *C,
const int n, const int m) {
// n, A, 4000 this kernel assumes A is column-major A(SIZE, n)
// m, B, 20000 this kernel assumes B is row-major B(m, SIZE)
// this kernel assumes C is column-major C(m,n)
// this kernel assumes number of threads per threadblock == SIZE
// CHKSIZE is the number of B vectors that will be compute per block
__shared__ float my_sB[CHKSIZE * SIZE]; // enough shared storage for CHKSIZE vectors of B
int bx = blockIdx.x; // one block per CHKSIZE rows of B (the larger input matrix)
while ((bx * CHKSIZE) < m) { // not used, this while loop could be used to extend a block to multiple chunks
int tx = threadIdx.x;
for (int i = 0; i < CHKSIZE; i++) // load vectors of B into shared memory
my_sB[(i * SIZE) + tx] = B[(((bx * CHKSIZE) + i) * SIZE) + tx];
__syncthreads();
while (tx < n) { //loop across all vectors in A
float result[CHKSIZE];
for (int i = 0; i < CHKSIZE; i++)
result[i] = 0.0f;
for (int i = 0; i < SIZE; i++) {
float Atemp = A[(n * i) + tx];
for (int j = 0; j < CHKSIZE; j++) { // compute all CHKSIZE B vectors with read of A
float temp = Atemp - my_sB[i + (j * SIZE)];
result[j] += temp * temp;
}
}
for (int i = 0; i < CHKSIZE; i++) // store CHKSIZE results
C[((i + (bx * CHKSIZE)) * n) + tx] = result[i];
tx += blockDim.x;
} // continue looping across vectors in A
__syncthreads(); // necessary to prevent warps from racing ahead, if block looping is used
bx += gridDim.x;
}
}
float comp_euclid_sq(const float *rA, const float *rB, const int size) {
float result = 0.0f;
float temp;
for (int i = 0; i < size; i++) {
temp = (rA[i] - rB[i]);
result += temp * temp;
}
return result;
}
int main_ed_gpu() {
float cpu_time = 0.0f, et1 = 0.0f, et2 = 0.0f, et_mem = 0.0f;
cudaEvent_t start1, start2, stop1, stop2, start_mem_copy, stop_mem_copy;
cudaEventCreate(&start1);
cudaEventCreate(&start2);
cudaEventCreate(&start_mem_copy);
cudaEventCreate(&stop1);
cudaEventCreate(&stop2);
cudaEventCreate(&stop_mem_copy);
int n = N; //MatrixA size : n * SIZE
int m = M; //MatrixB size : m * SIZE
srand((unsigned) time(0));
// Host Allocations
float *matrixA = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n * SIZE; i++)
matrixA[i] = (float) i + 1;
float *matrixB = (float *) malloc(m * SIZE * sizeof(float));
for (int i = 0; i < m * SIZE; i++)
matrixB[i] = (float) i + i;
const clock_t begin_time = clock();
float *results_kernel = (float *) malloc(n * m * sizeof(float));
float *cpu_results_kernel = (float *) malloc(n * m * sizeof(float));
for (int i = 0; i < n * m; i++)
cpu_results_kernel[i] = comp_euclid_sq(matrixA + ((i / m) * SIZE),
matrixB + (i % m) * SIZE, SIZE);
cpu_time = float( clock () - begin_time ) / 1000;
//Device Allocation
cudaEventRecord(start_mem_copy);
float *d_matrixA;
float *d_matrixB;
cudaMalloc((void **) &d_matrixA, n * SIZE * sizeof(float));
cudaMalloc((void **) &d_matrixB, m * SIZE * sizeof(float));
cudaMemcpy(d_matrixA, matrixA, n * SIZE * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(d_matrixB, matrixB, m * SIZE * sizeof(float),
cudaMemcpyHostToDevice);
cudaEventElapsedTime(&et_mem, start_mem_copy, stop_mem_copy);
float *d_results_kernel;
cudaMalloc((void **) &d_results_kernel, n * m * sizeof(float));
cudaFuncSetCacheConfig(EuclideanDistancesNaive, cudaFuncCachePreferL1);
dim3 threads3(8, 32); // 1024 threads per block (maximum)
dim3 blocks3(n / threads3.x, m / threads3.y); // assumes evenly divisible
cudaEventRecord(start1);
EuclideanDistancesNaive<<<blocks3, threads3>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
cudaEventRecord(stop1);
cudaMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
cudaMemcpyDeviceToHost);
// for (int i = 0; i < n * m; i++) {
// if (results_kernel[i] != cpu_results_kernel[i]) {
// printf("cpu/kernel3 mismatch at %d, cpu: %f, kernel3: %f\n", i,
// cpu_results_kernel[i], results_kernel[i]);
// return 1;
// }
// }
cudaMemset(d_results_kernel, 0, n * m * sizeof(float));
cudaEventSynchronize(stop1);
cudaEventElapsedTime(&et1, start1, stop1);
// transpose matrix A
float *matrixA_T = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n; i++)
for (int j = 0; j < SIZE; j++)
matrixA_T[(j * n) + i] = matrixA[(i * SIZE) + j];
cudaMemcpy(d_matrixA, matrixA_T, n * SIZE * sizeof(float),
cudaMemcpyHostToDevice);
cudaFuncSetCacheConfig(EuclideanDistancesFast, cudaFuncCachePreferL1);
dim3 threads4(SIZE); // one thread per vector element
dim3 blocks4(m / CHKSIZE);
cudaEventRecord(start2);
EuclideanDistancesFast<<<blocks4, threads4>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
cudaEventRecord(stop2);
cudaMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
cudaMemcpyDeviceToHost);
// test for correct transposed result C(m,n)
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
printf("%f ", results_kernel[(j * n) + i]);
if (results_kernel[(j * n) + i]
!= cpu_results_kernel[(i * m) + j]) {
printf("cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n",
i, j, cpu_results_kernel[(i * m) + j],
results_kernel[(j * n) + i]);
return 1;
}
}
printf("\n");
}
cudaEventSynchronize(stop2);
cudaEventElapsedTime(&et2, start2, stop2);
cudaFree(d_results_kernel);
printf("Success!\n");
printf("CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n",
cpu_time, et1, et2, et_mem);
free(matrixA);
free(matrixB);
free(results_kernel);
return 0;
} | .file "tmpxft_000df931_00000000-6_euclidean_distance_fast.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14comp_euclid_sqPKfS0_i
.type _Z14comp_euclid_sqPKfS0_i, @function
_Z14comp_euclid_sqPKfS0_i:
.LFB3669:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L6
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
.L5:
movss (%rdi,%rax), %xmm0
subss (%rsi,%rax), %xmm0
mulss %xmm0, %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
movaps %xmm1, %xmm0
ret
.L6:
pxor %xmm1, %xmm1
jmp .L3
.cfi_endproc
.LFE3669:
.size _Z14comp_euclid_sqPKfS0_i, .-_Z14comp_euclid_sqPKfS0_i
.globl _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii
.type _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii, @function
_Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23EuclideanDistancesNaivePfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii, .-_Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii
.globl _Z23EuclideanDistancesNaivePfS_S_ii
.type _Z23EuclideanDistancesNaivePfS_S_ii, @function
_Z23EuclideanDistancesNaivePfS_S_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z23EuclideanDistancesNaivePfS_S_ii, .-_Z23EuclideanDistancesNaivePfS_S_ii
.globl _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii
.type _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii, @function
_Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22EuclideanDistancesFastPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii, .-_Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii
.globl _Z22EuclideanDistancesFastPKfS0_Pfii
.type _Z22EuclideanDistancesFastPKfS0_Pfii, @function
_Z22EuclideanDistancesFastPKfS0_Pfii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z22EuclideanDistancesFastPKfS0_Pfii, .-_Z22EuclideanDistancesFastPKfS0_Pfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "%f "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n"
.section .rodata.str1.1
.LC8:
.string "\n"
.LC9:
.string "Success!\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n"
.text
.globl _Z11main_ed_gpuv
.type _Z11main_ed_gpuv, @function
_Z11main_ed_gpuv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $0x00000000, 20(%rsp)
movl $0x00000000, 24(%rsp)
movl $0x00000000, 28(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
movl $0x3f800000, (%rax)
movl $0x40000000, 4(%rax)
movl $0x40400000, 8(%rax)
movl $0x40800000, 12(%rax)
movl $24, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L25:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $6, %rax
jne .L25
call clock@PLT
movq %rax, %r14
movl $24, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $24, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %ebx
.L26:
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax), %ecx
addl %ecx, %eax
movl %ebx, %edx
subl %eax, %edx
leal (%rdx,%rdx), %eax
cltq
leaq 0(%r13,%rax,4), %rsi
movslq %ecx, %rcx
leaq 0(%rbp,%rcx,4), %rdi
movl $2, %edx
call _Z14comp_euclid_sqPKfS0_i
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq $6, %rbx
jne .L26
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
movss %xmm0, 12(%rsp)
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16, %edx
movq %rbp, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $24, %edx
movq %r13, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 28(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 96(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
movl $2, %esi
leaq _Z23EuclideanDistancesNaivePfS_S_ii(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $1, 112(%rsp)
movl $0, 116(%rsp)
movl $0, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $8, 104(%rsp)
movl $32, 108(%rsp)
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L27:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $24, %edx
movq 96(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $24, %edx
movl $0, %esi
movq 96(%rsp), %rdi
call cudaMemset@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $16, %edi
call malloc@PLT
movq %rax, %rsi
movss 0(%rbp), %xmm0
movss %xmm0, (%rax)
movss 4(%rbp), %xmm0
movss %xmm0, 8(%rax)
movss 8(%rbp), %xmm0
movss %xmm0, 4(%rax)
movss 12(%rbp), %xmm0
movss %xmm0, 12(%rax)
movl $1, %ecx
movl $16, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %esi
leaq _Z22EuclideanDistancesFastPKfS0_Pfii(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $2, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $3, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 136(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 128(%rsp), %rdx
movq 140(%rsp), %rdi
movl 148(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $24, %edx
movq 96(%rsp), %rsi
movq (%rsp), %r14
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %r15d
.L29:
movl $0, %ebx
.L33:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,8), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss (%r14,%rbx,8), %xmm1
movss (%r12,%rbx,4), %xmm0
ucomiss %xmm0, %xmm1
jp .L36
jne .L36
addq $1, %rbx
cmpq $3, %rbx
jne .L33
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
addq $4, %r14
addq $12, %r12
cmpl $2, %r15d
jne .L29
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 24(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
pxor %xmm3, %xmm3
cvtss2sd 28(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtss2sd 24(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movl $0, %eax
.L24:
movq 152(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl $3, %r8d
movl $2, %ecx
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii
jmp .L27
.L42:
movl $3, %r8d
movl $2, %ecx
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii
jmp .L28
.L36:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movl %r15d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L24
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z11main_ed_gpuv, .-_Z11main_ed_gpuv
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z22EuclideanDistancesFastPKfS0_Pfii"
.align 8
.LC12:
.string "_Z23EuclideanDistancesNaivePfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z22EuclideanDistancesFastPKfS0_Pfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z23EuclideanDistancesNaivePfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
// both M and N must be evenly divisible by SIZE, M must be evenly divisible by CHKSIZE
#define SIZE 2
#define N 2
#define M 3
#define CHKSIZE 1
//naive kernel
__global__ void EuclideanDistancesNaive(float *A, float *B, float *C, int n,
int m) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
float result = 0.0f;
if ((idx < n) && (idy < m)) {
for (int i = 0; i < SIZE; i++) {
float temp = A[(idx * SIZE) + i] - B[(idy * SIZE) + i];
result += temp * temp;
}
C[(idx * m) + idy] = result;
}
}
//optimized kernel
__global__ void EuclideanDistancesFast(const float *A, const float *B, float *C,
const int n, const int m) {
// n, A, 4000 this kernel assumes A is column-major A(SIZE, n)
// m, B, 20000 this kernel assumes B is row-major B(m, SIZE)
// this kernel assumes C is column-major C(m,n)
// this kernel assumes number of threads per threadblock == SIZE
// CHKSIZE is the number of B vectors that will be compute per block
__shared__ float my_sB[CHKSIZE * SIZE]; // enough shared storage for CHKSIZE vectors of B
int bx = blockIdx.x; // one block per CHKSIZE rows of B (the larger input matrix)
while ((bx * CHKSIZE) < m) { // not used, this while loop could be used to extend a block to multiple chunks
int tx = threadIdx.x;
for (int i = 0; i < CHKSIZE; i++) // load vectors of B into shared memory
my_sB[(i * SIZE) + tx] = B[(((bx * CHKSIZE) + i) * SIZE) + tx];
__syncthreads();
while (tx < n) { //loop across all vectors in A
float result[CHKSIZE];
for (int i = 0; i < CHKSIZE; i++)
result[i] = 0.0f;
for (int i = 0; i < SIZE; i++) {
float Atemp = A[(n * i) + tx];
for (int j = 0; j < CHKSIZE; j++) { // compute all CHKSIZE B vectors with read of A
float temp = Atemp - my_sB[i + (j * SIZE)];
result[j] += temp * temp;
}
}
for (int i = 0; i < CHKSIZE; i++) // store CHKSIZE results
C[((i + (bx * CHKSIZE)) * n) + tx] = result[i];
tx += blockDim.x;
} // continue looping across vectors in A
__syncthreads(); // necessary to prevent warps from racing ahead, if block looping is used
bx += gridDim.x;
}
}
float comp_euclid_sq(const float *rA, const float *rB, const int size) {
float result = 0.0f;
float temp;
for (int i = 0; i < size; i++) {
temp = (rA[i] - rB[i]);
result += temp * temp;
}
return result;
}
int main_ed_gpu() {
float cpu_time = 0.0f, et1 = 0.0f, et2 = 0.0f, et_mem = 0.0f;
cudaEvent_t start1, start2, stop1, stop2, start_mem_copy, stop_mem_copy;
cudaEventCreate(&start1);
cudaEventCreate(&start2);
cudaEventCreate(&start_mem_copy);
cudaEventCreate(&stop1);
cudaEventCreate(&stop2);
cudaEventCreate(&stop_mem_copy);
int n = N; //MatrixA size : n * SIZE
int m = M; //MatrixB size : m * SIZE
srand((unsigned) time(0));
// Host Allocations
float *matrixA = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n * SIZE; i++)
matrixA[i] = (float) i + 1;
float *matrixB = (float *) malloc(m * SIZE * sizeof(float));
for (int i = 0; i < m * SIZE; i++)
matrixB[i] = (float) i + i;
const clock_t begin_time = clock();
float *results_kernel = (float *) malloc(n * m * sizeof(float));
float *cpu_results_kernel = (float *) malloc(n * m * sizeof(float));
for (int i = 0; i < n * m; i++)
cpu_results_kernel[i] = comp_euclid_sq(matrixA + ((i / m) * SIZE),
matrixB + (i % m) * SIZE, SIZE);
cpu_time = float( clock () - begin_time ) / 1000;
//Device Allocation
cudaEventRecord(start_mem_copy);
float *d_matrixA;
float *d_matrixB;
cudaMalloc((void **) &d_matrixA, n * SIZE * sizeof(float));
cudaMalloc((void **) &d_matrixB, m * SIZE * sizeof(float));
cudaMemcpy(d_matrixA, matrixA, n * SIZE * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(d_matrixB, matrixB, m * SIZE * sizeof(float),
cudaMemcpyHostToDevice);
cudaEventElapsedTime(&et_mem, start_mem_copy, stop_mem_copy);
float *d_results_kernel;
cudaMalloc((void **) &d_results_kernel, n * m * sizeof(float));
cudaFuncSetCacheConfig(EuclideanDistancesNaive, cudaFuncCachePreferL1);
dim3 threads3(8, 32); // 1024 threads per block (maximum)
dim3 blocks3(n / threads3.x, m / threads3.y); // assumes evenly divisible
cudaEventRecord(start1);
EuclideanDistancesNaive<<<blocks3, threads3>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
cudaEventRecord(stop1);
cudaMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
cudaMemcpyDeviceToHost);
// for (int i = 0; i < n * m; i++) {
// if (results_kernel[i] != cpu_results_kernel[i]) {
// printf("cpu/kernel3 mismatch at %d, cpu: %f, kernel3: %f\n", i,
// cpu_results_kernel[i], results_kernel[i]);
// return 1;
// }
// }
cudaMemset(d_results_kernel, 0, n * m * sizeof(float));
cudaEventSynchronize(stop1);
cudaEventElapsedTime(&et1, start1, stop1);
// transpose matrix A
float *matrixA_T = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n; i++)
for (int j = 0; j < SIZE; j++)
matrixA_T[(j * n) + i] = matrixA[(i * SIZE) + j];
cudaMemcpy(d_matrixA, matrixA_T, n * SIZE * sizeof(float),
cudaMemcpyHostToDevice);
cudaFuncSetCacheConfig(EuclideanDistancesFast, cudaFuncCachePreferL1);
dim3 threads4(SIZE); // one thread per vector element
dim3 blocks4(m / CHKSIZE);
cudaEventRecord(start2);
EuclideanDistancesFast<<<blocks4, threads4>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
cudaEventRecord(stop2);
cudaMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
cudaMemcpyDeviceToHost);
// test for correct transposed result C(m,n)
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
printf("%f ", results_kernel[(j * n) + i]);
if (results_kernel[(j * n) + i]
!= cpu_results_kernel[(i * m) + j]) {
printf("cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n",
i, j, cpu_results_kernel[(i * m) + j],
results_kernel[(j * n) + i]);
return 1;
}
}
printf("\n");
}
cudaEventSynchronize(stop2);
cudaEventElapsedTime(&et2, start2, stop2);
cudaFree(d_results_kernel);
printf("Success!\n");
printf("CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n",
cpu_time, et1, et2, et_mem);
free(matrixA);
free(matrixB);
free(results_kernel);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
// both M and N must be evenly divisible by SIZE, M must be evenly divisible by CHKSIZE
#define SIZE 2
#define N 2
#define M 3
#define CHKSIZE 1
//naive kernel
__global__ void EuclideanDistancesNaive(float *A, float *B, float *C, int n,
int m) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
float result = 0.0f;
if ((idx < n) && (idy < m)) {
for (int i = 0; i < SIZE; i++) {
float temp = A[(idx * SIZE) + i] - B[(idy * SIZE) + i];
result += temp * temp;
}
C[(idx * m) + idy] = result;
}
}
//optimized kernel
__global__ void EuclideanDistancesFast(const float *A, const float *B, float *C,
const int n, const int m) {
// n, A, 4000 this kernel assumes A is column-major A(SIZE, n)
// m, B, 20000 this kernel assumes B is row-major B(m, SIZE)
// this kernel assumes C is column-major C(m,n)
// this kernel assumes number of threads per threadblock == SIZE
// CHKSIZE is the number of B vectors that will be compute per block
__shared__ float my_sB[CHKSIZE * SIZE]; // enough shared storage for CHKSIZE vectors of B
int bx = blockIdx.x; // one block per CHKSIZE rows of B (the larger input matrix)
while ((bx * CHKSIZE) < m) { // not used, this while loop could be used to extend a block to multiple chunks
int tx = threadIdx.x;
for (int i = 0; i < CHKSIZE; i++) // load vectors of B into shared memory
my_sB[(i * SIZE) + tx] = B[(((bx * CHKSIZE) + i) * SIZE) + tx];
__syncthreads();
while (tx < n) { //loop across all vectors in A
float result[CHKSIZE];
for (int i = 0; i < CHKSIZE; i++)
result[i] = 0.0f;
for (int i = 0; i < SIZE; i++) {
float Atemp = A[(n * i) + tx];
for (int j = 0; j < CHKSIZE; j++) { // compute all CHKSIZE B vectors with read of A
float temp = Atemp - my_sB[i + (j * SIZE)];
result[j] += temp * temp;
}
}
for (int i = 0; i < CHKSIZE; i++) // store CHKSIZE results
C[((i + (bx * CHKSIZE)) * n) + tx] = result[i];
tx += blockDim.x;
} // continue looping across vectors in A
__syncthreads(); // necessary to prevent warps from racing ahead, if block looping is used
bx += gridDim.x;
}
}
float comp_euclid_sq(const float *rA, const float *rB, const int size) {
float result = 0.0f;
float temp;
for (int i = 0; i < size; i++) {
temp = (rA[i] - rB[i]);
result += temp * temp;
}
return result;
}
int main_ed_gpu() {
float cpu_time = 0.0f, et1 = 0.0f, et2 = 0.0f, et_mem = 0.0f;
hipEvent_t start1, start2, stop1, stop2, start_mem_copy, stop_mem_copy;
hipEventCreate(&start1);
hipEventCreate(&start2);
hipEventCreate(&start_mem_copy);
hipEventCreate(&stop1);
hipEventCreate(&stop2);
hipEventCreate(&stop_mem_copy);
int n = N; //MatrixA size : n * SIZE
int m = M; //MatrixB size : m * SIZE
srand((unsigned) time(0));
// Host Allocations
float *matrixA = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n * SIZE; i++)
matrixA[i] = (float) i + 1;
float *matrixB = (float *) malloc(m * SIZE * sizeof(float));
for (int i = 0; i < m * SIZE; i++)
matrixB[i] = (float) i + i;
const clock_t begin_time = clock();
float *results_kernel = (float *) malloc(n * m * sizeof(float));
float *cpu_results_kernel = (float *) malloc(n * m * sizeof(float));
for (int i = 0; i < n * m; i++)
cpu_results_kernel[i] = comp_euclid_sq(matrixA + ((i / m) * SIZE),
matrixB + (i % m) * SIZE, SIZE);
cpu_time = float( clock () - begin_time ) / 1000;
//Device Allocation
hipEventRecord(start_mem_copy);
float *d_matrixA;
float *d_matrixB;
hipMalloc((void **) &d_matrixA, n * SIZE * sizeof(float));
hipMalloc((void **) &d_matrixB, m * SIZE * sizeof(float));
hipMemcpy(d_matrixA, matrixA, n * SIZE * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(d_matrixB, matrixB, m * SIZE * sizeof(float),
hipMemcpyHostToDevice);
hipEventElapsedTime(&et_mem, start_mem_copy, stop_mem_copy);
float *d_results_kernel;
hipMalloc((void **) &d_results_kernel, n * m * sizeof(float));
hipFuncSetCacheConfig(reinterpret_cast<const void*>(EuclideanDistancesNaive), hipFuncCachePreferL1);
dim3 threads3(8, 32); // 1024 threads per block (maximum)
dim3 blocks3(n / threads3.x, m / threads3.y); // assumes evenly divisible
hipEventRecord(start1);
EuclideanDistancesNaive<<<blocks3, threads3>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
hipEventRecord(stop1);
hipMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
hipMemcpyDeviceToHost);
// for (int i = 0; i < n * m; i++) {
// if (results_kernel[i] != cpu_results_kernel[i]) {
// printf("cpu/kernel3 mismatch at %d, cpu: %f, kernel3: %f\n", i,
// cpu_results_kernel[i], results_kernel[i]);
// return 1;
// }
// }
hipMemset(d_results_kernel, 0, n * m * sizeof(float));
hipEventSynchronize(stop1);
hipEventElapsedTime(&et1, start1, stop1);
// transpose matrix A
float *matrixA_T = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n; i++)
for (int j = 0; j < SIZE; j++)
matrixA_T[(j * n) + i] = matrixA[(i * SIZE) + j];
hipMemcpy(d_matrixA, matrixA_T, n * SIZE * sizeof(float),
hipMemcpyHostToDevice);
hipFuncSetCacheConfig(reinterpret_cast<const void*>(EuclideanDistancesFast), hipFuncCachePreferL1);
dim3 threads4(SIZE); // one thread per vector element
dim3 blocks4(m / CHKSIZE);
hipEventRecord(start2);
EuclideanDistancesFast<<<blocks4, threads4>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
hipEventRecord(stop2);
hipMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
hipMemcpyDeviceToHost);
// test for correct transposed result C(m,n)
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
printf("%f ", results_kernel[(j * n) + i]);
if (results_kernel[(j * n) + i]
!= cpu_results_kernel[(i * m) + j]) {
printf("cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n",
i, j, cpu_results_kernel[(i * m) + j],
results_kernel[(j * n) + i]);
return 1;
}
}
printf("\n");
}
hipEventSynchronize(stop2);
hipEventElapsedTime(&et2, start2, stop2);
hipFree(d_results_kernel);
printf("Success!\n");
printf("CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n",
cpu_time, et1, et2, et_mem);
free(matrixA);
free(matrixB);
free(results_kernel);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
// both M and N must be evenly divisible by SIZE, M must be evenly divisible by CHKSIZE
#define SIZE 2
#define N 2
#define M 3
#define CHKSIZE 1
//naive kernel
__global__ void EuclideanDistancesNaive(float *A, float *B, float *C, int n,
int m) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
float result = 0.0f;
if ((idx < n) && (idy < m)) {
for (int i = 0; i < SIZE; i++) {
float temp = A[(idx * SIZE) + i] - B[(idy * SIZE) + i];
result += temp * temp;
}
C[(idx * m) + idy] = result;
}
}
//optimized kernel
__global__ void EuclideanDistancesFast(const float *A, const float *B, float *C,
const int n, const int m) {
// n, A, 4000 this kernel assumes A is column-major A(SIZE, n)
// m, B, 20000 this kernel assumes B is row-major B(m, SIZE)
// this kernel assumes C is column-major C(m,n)
// this kernel assumes number of threads per threadblock == SIZE
// CHKSIZE is the number of B vectors that will be compute per block
__shared__ float my_sB[CHKSIZE * SIZE]; // enough shared storage for CHKSIZE vectors of B
int bx = blockIdx.x; // one block per CHKSIZE rows of B (the larger input matrix)
while ((bx * CHKSIZE) < m) { // not used, this while loop could be used to extend a block to multiple chunks
int tx = threadIdx.x;
for (int i = 0; i < CHKSIZE; i++) // load vectors of B into shared memory
my_sB[(i * SIZE) + tx] = B[(((bx * CHKSIZE) + i) * SIZE) + tx];
__syncthreads();
while (tx < n) { //loop across all vectors in A
float result[CHKSIZE];
for (int i = 0; i < CHKSIZE; i++)
result[i] = 0.0f;
for (int i = 0; i < SIZE; i++) {
float Atemp = A[(n * i) + tx];
for (int j = 0; j < CHKSIZE; j++) { // compute all CHKSIZE B vectors with read of A
float temp = Atemp - my_sB[i + (j * SIZE)];
result[j] += temp * temp;
}
}
for (int i = 0; i < CHKSIZE; i++) // store CHKSIZE results
C[((i + (bx * CHKSIZE)) * n) + tx] = result[i];
tx += blockDim.x;
} // continue looping across vectors in A
__syncthreads(); // necessary to prevent warps from racing ahead, if block looping is used
bx += gridDim.x;
}
}
float comp_euclid_sq(const float *rA, const float *rB, const int size) {
float result = 0.0f;
float temp;
for (int i = 0; i < size; i++) {
temp = (rA[i] - rB[i]);
result += temp * temp;
}
return result;
}
int main_ed_gpu() {
float cpu_time = 0.0f, et1 = 0.0f, et2 = 0.0f, et_mem = 0.0f;
hipEvent_t start1, start2, stop1, stop2, start_mem_copy, stop_mem_copy;
hipEventCreate(&start1);
hipEventCreate(&start2);
hipEventCreate(&start_mem_copy);
hipEventCreate(&stop1);
hipEventCreate(&stop2);
hipEventCreate(&stop_mem_copy);
int n = N; //MatrixA size : n * SIZE
int m = M; //MatrixB size : m * SIZE
srand((unsigned) time(0));
// Host Allocations
float *matrixA = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n * SIZE; i++)
matrixA[i] = (float) i + 1;
float *matrixB = (float *) malloc(m * SIZE * sizeof(float));
for (int i = 0; i < m * SIZE; i++)
matrixB[i] = (float) i + i;
const clock_t begin_time = clock();
float *results_kernel = (float *) malloc(n * m * sizeof(float));
float *cpu_results_kernel = (float *) malloc(n * m * sizeof(float));
for (int i = 0; i < n * m; i++)
cpu_results_kernel[i] = comp_euclid_sq(matrixA + ((i / m) * SIZE),
matrixB + (i % m) * SIZE, SIZE);
cpu_time = float( clock () - begin_time ) / 1000;
//Device Allocation
hipEventRecord(start_mem_copy);
float *d_matrixA;
float *d_matrixB;
hipMalloc((void **) &d_matrixA, n * SIZE * sizeof(float));
hipMalloc((void **) &d_matrixB, m * SIZE * sizeof(float));
hipMemcpy(d_matrixA, matrixA, n * SIZE * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(d_matrixB, matrixB, m * SIZE * sizeof(float),
hipMemcpyHostToDevice);
hipEventElapsedTime(&et_mem, start_mem_copy, stop_mem_copy);
float *d_results_kernel;
hipMalloc((void **) &d_results_kernel, n * m * sizeof(float));
hipFuncSetCacheConfig(reinterpret_cast<const void*>(EuclideanDistancesNaive), hipFuncCachePreferL1);
dim3 threads3(8, 32); // 1024 threads per block (maximum)
dim3 blocks3(n / threads3.x, m / threads3.y); // assumes evenly divisible
hipEventRecord(start1);
EuclideanDistancesNaive<<<blocks3, threads3>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
hipEventRecord(stop1);
hipMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
hipMemcpyDeviceToHost);
// for (int i = 0; i < n * m; i++) {
// if (results_kernel[i] != cpu_results_kernel[i]) {
// printf("cpu/kernel3 mismatch at %d, cpu: %f, kernel3: %f\n", i,
// cpu_results_kernel[i], results_kernel[i]);
// return 1;
// }
// }
hipMemset(d_results_kernel, 0, n * m * sizeof(float));
hipEventSynchronize(stop1);
hipEventElapsedTime(&et1, start1, stop1);
// transpose matrix A
float *matrixA_T = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n; i++)
for (int j = 0; j < SIZE; j++)
matrixA_T[(j * n) + i] = matrixA[(i * SIZE) + j];
hipMemcpy(d_matrixA, matrixA_T, n * SIZE * sizeof(float),
hipMemcpyHostToDevice);
hipFuncSetCacheConfig(reinterpret_cast<const void*>(EuclideanDistancesFast), hipFuncCachePreferL1);
dim3 threads4(SIZE); // one thread per vector element
dim3 blocks4(m / CHKSIZE);
hipEventRecord(start2);
EuclideanDistancesFast<<<blocks4, threads4>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
hipEventRecord(stop2);
hipMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
hipMemcpyDeviceToHost);
// test for correct transposed result C(m,n)
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
printf("%f ", results_kernel[(j * n) + i]);
if (results_kernel[(j * n) + i]
!= cpu_results_kernel[(i * m) + j]) {
printf("cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n",
i, j, cpu_results_kernel[(i * m) + j],
results_kernel[(j * n) + i]);
return 1;
}
}
printf("\n");
}
hipEventSynchronize(stop2);
hipEventElapsedTime(&et2, start2, stop2);
hipFree(d_results_kernel);
printf("Success!\n");
printf("CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n",
cpu_time, et1, et2, et_mem);
free(matrixA);
free(matrixB);
free(results_kernel);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23EuclideanDistancesNaivePfS_S_ii
.globl _Z23EuclideanDistancesNaivePfS_S_ii
.p2align 8
.type _Z23EuclideanDistancesNaivePfS_S_ii,@function
_Z23EuclideanDistancesNaivePfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 1, v0
v_lshlrev_b32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v9, vcc_lo
s_mov_b64 s[4:5], 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v7, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
s_add_u32 s4, s4, 4
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[9:10], off
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s4, 4
s_waitcnt vmcnt(0)
v_sub_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v7, v7
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23EuclideanDistancesNaivePfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23EuclideanDistancesNaivePfS_S_ii, .Lfunc_end0-_Z23EuclideanDistancesNaivePfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22EuclideanDistancesFastPKfS0_Pfii
.globl _Z22EuclideanDistancesFastPKfS0_Pfii
.p2align 8
.type _Z22EuclideanDistancesFastPKfS0_Pfii,@function
_Z22EuclideanDistancesFastPKfS0_Pfii:
s_load_b32 s14, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s14
s_cbranch_scc1 .LBB1_8
s_clause 0x3
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s16, s[0:1], 0x20
v_lshlrev_b32_e32 v4, 2, v0
s_add_u32 s10, s0, 32
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[2:3], 2
s_branch .LBB1_3
.LBB1_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s15, s16, s15
s_waitcnt_vscnt null, 0x0
s_cmp_lt_i32 s15, s14
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_8
.LBB1_3:
v_lshl_add_u32 v1, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s6, v1
v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b32 s0, s[10:11], 0xc
v_mov_b32_e32 v1, v0
s_mul_i32 s17, s15, s2
s_mov_b32 s19, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s18, s0, 0xffff
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_5:
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
.LBB1_6:
global_load_b32 v6, v[2:3], off
v_mov_b32_e32 v7, s1
v_add_co_u32 v2, s0, v2, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s13, v3, s0
ds_load_b32 v7, v7
s_add_i32 s1, s1, 4
s_cmp_eq_u32 s1, 4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_f32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v6
s_cbranch_scc1 .LBB1_6
v_add_nc_u32_e32 v2, s17, v1
v_add_nc_u32_e32 v1, s18, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_le_i32_e64 s0, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_or_b32 s19, s0, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s1, s8, v2
v_add_co_ci_u32_e64 v3, s1, s9, v3, s1
global_store_b32 v[2:3], v5, off
s_and_not1_b32 exec_lo, exec_lo, s19
s_cbranch_execnz .LBB1_5
s_branch .LBB1_2
.LBB1_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22EuclideanDistancesFastPKfS0_Pfii
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z22EuclideanDistancesFastPKfS0_Pfii, .Lfunc_end1-_Z22EuclideanDistancesFastPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23EuclideanDistancesNaivePfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23EuclideanDistancesNaivePfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22EuclideanDistancesFastPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z22EuclideanDistancesFastPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
// both M and N must be evenly divisible by SIZE, M must be evenly divisible by CHKSIZE
#define SIZE 2
#define N 2
#define M 3
#define CHKSIZE 1
//naive kernel
__global__ void EuclideanDistancesNaive(float *A, float *B, float *C, int n,
int m) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
float result = 0.0f;
if ((idx < n) && (idy < m)) {
for (int i = 0; i < SIZE; i++) {
float temp = A[(idx * SIZE) + i] - B[(idy * SIZE) + i];
result += temp * temp;
}
C[(idx * m) + idy] = result;
}
}
//optimized kernel
__global__ void EuclideanDistancesFast(const float *A, const float *B, float *C,
const int n, const int m) {
// n, A, 4000 this kernel assumes A is column-major A(SIZE, n)
// m, B, 20000 this kernel assumes B is row-major B(m, SIZE)
// this kernel assumes C is column-major C(m,n)
// this kernel assumes number of threads per threadblock == SIZE
// CHKSIZE is the number of B vectors that will be compute per block
__shared__ float my_sB[CHKSIZE * SIZE]; // enough shared storage for CHKSIZE vectors of B
int bx = blockIdx.x; // one block per CHKSIZE rows of B (the larger input matrix)
while ((bx * CHKSIZE) < m) { // not used, this while loop could be used to extend a block to multiple chunks
int tx = threadIdx.x;
for (int i = 0; i < CHKSIZE; i++) // load vectors of B into shared memory
my_sB[(i * SIZE) + tx] = B[(((bx * CHKSIZE) + i) * SIZE) + tx];
__syncthreads();
while (tx < n) { //loop across all vectors in A
float result[CHKSIZE];
for (int i = 0; i < CHKSIZE; i++)
result[i] = 0.0f;
for (int i = 0; i < SIZE; i++) {
float Atemp = A[(n * i) + tx];
for (int j = 0; j < CHKSIZE; j++) { // compute all CHKSIZE B vectors with read of A
float temp = Atemp - my_sB[i + (j * SIZE)];
result[j] += temp * temp;
}
}
for (int i = 0; i < CHKSIZE; i++) // store CHKSIZE results
C[((i + (bx * CHKSIZE)) * n) + tx] = result[i];
tx += blockDim.x;
} // continue looping across vectors in A
__syncthreads(); // necessary to prevent warps from racing ahead, if block looping is used
bx += gridDim.x;
}
}
float comp_euclid_sq(const float *rA, const float *rB, const int size) {
float result = 0.0f;
float temp;
for (int i = 0; i < size; i++) {
temp = (rA[i] - rB[i]);
result += temp * temp;
}
return result;
}
int main_ed_gpu() {
float cpu_time = 0.0f, et1 = 0.0f, et2 = 0.0f, et_mem = 0.0f;
hipEvent_t start1, start2, stop1, stop2, start_mem_copy, stop_mem_copy;
hipEventCreate(&start1);
hipEventCreate(&start2);
hipEventCreate(&start_mem_copy);
hipEventCreate(&stop1);
hipEventCreate(&stop2);
hipEventCreate(&stop_mem_copy);
int n = N; //MatrixA size : n * SIZE
int m = M; //MatrixB size : m * SIZE
srand((unsigned) time(0));
// Host Allocations
float *matrixA = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n * SIZE; i++)
matrixA[i] = (float) i + 1;
float *matrixB = (float *) malloc(m * SIZE * sizeof(float));
for (int i = 0; i < m * SIZE; i++)
matrixB[i] = (float) i + i;
const clock_t begin_time = clock();
float *results_kernel = (float *) malloc(n * m * sizeof(float));
float *cpu_results_kernel = (float *) malloc(n * m * sizeof(float));
for (int i = 0; i < n * m; i++)
cpu_results_kernel[i] = comp_euclid_sq(matrixA + ((i / m) * SIZE),
matrixB + (i % m) * SIZE, SIZE);
cpu_time = float( clock () - begin_time ) / 1000;
//Device Allocation
hipEventRecord(start_mem_copy);
float *d_matrixA;
float *d_matrixB;
hipMalloc((void **) &d_matrixA, n * SIZE * sizeof(float));
hipMalloc((void **) &d_matrixB, m * SIZE * sizeof(float));
hipMemcpy(d_matrixA, matrixA, n * SIZE * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(d_matrixB, matrixB, m * SIZE * sizeof(float),
hipMemcpyHostToDevice);
hipEventElapsedTime(&et_mem, start_mem_copy, stop_mem_copy);
float *d_results_kernel;
hipMalloc((void **) &d_results_kernel, n * m * sizeof(float));
hipFuncSetCacheConfig(reinterpret_cast<const void*>(EuclideanDistancesNaive), hipFuncCachePreferL1);
dim3 threads3(8, 32); // 1024 threads per block (maximum)
dim3 blocks3(n / threads3.x, m / threads3.y); // assumes evenly divisible
hipEventRecord(start1);
EuclideanDistancesNaive<<<blocks3, threads3>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
hipEventRecord(stop1);
hipMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
hipMemcpyDeviceToHost);
// for (int i = 0; i < n * m; i++) {
// if (results_kernel[i] != cpu_results_kernel[i]) {
// printf("cpu/kernel3 mismatch at %d, cpu: %f, kernel3: %f\n", i,
// cpu_results_kernel[i], results_kernel[i]);
// return 1;
// }
// }
hipMemset(d_results_kernel, 0, n * m * sizeof(float));
hipEventSynchronize(stop1);
hipEventElapsedTime(&et1, start1, stop1);
// transpose matrix A
float *matrixA_T = (float *) malloc(n * SIZE * sizeof(float));
for (int i = 0; i < n; i++)
for (int j = 0; j < SIZE; j++)
matrixA_T[(j * n) + i] = matrixA[(i * SIZE) + j];
hipMemcpy(d_matrixA, matrixA_T, n * SIZE * sizeof(float),
hipMemcpyHostToDevice);
hipFuncSetCacheConfig(reinterpret_cast<const void*>(EuclideanDistancesFast), hipFuncCachePreferL1);
dim3 threads4(SIZE); // one thread per vector element
dim3 blocks4(m / CHKSIZE);
hipEventRecord(start2);
EuclideanDistancesFast<<<blocks4, threads4>>>(d_matrixA, d_matrixB,
d_results_kernel, n, m);
hipEventRecord(stop2);
hipMemcpy(results_kernel, d_results_kernel, n * m * sizeof(float),
hipMemcpyDeviceToHost);
// test for correct transposed result C(m,n)
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
printf("%f ", results_kernel[(j * n) + i]);
if (results_kernel[(j * n) + i]
!= cpu_results_kernel[(i * m) + j]) {
printf("cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n",
i, j, cpu_results_kernel[(i * m) + j],
results_kernel[(j * n) + i]);
return 1;
}
}
printf("\n");
}
hipEventSynchronize(stop2);
hipEventElapsedTime(&et2, start2, stop2);
hipFree(d_results_kernel);
printf("Success!\n");
printf("CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n",
cpu_time, et1, et2, et_mem);
free(matrixA);
free(matrixB);
free(results_kernel);
return 0;
} | .text
.file "euclidean_distance_fast.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii # -- Begin function _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.p2align 4, 0x90
.type _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii,@function
_Z38__device_stub__EuclideanDistancesNaivePfS_S_ii: # @_Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23EuclideanDistancesNaivePfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii, .Lfunc_end0-_Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii # -- Begin function _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.p2align 4, 0x90
.type _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii,@function
_Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii: # @_Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22EuclideanDistancesFastPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii, .Lfunc_end1-_Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.cfi_endproc
# -- End function
.globl _Z14comp_euclid_sqPKfS0_i # -- Begin function _Z14comp_euclid_sqPKfS0_i
.p2align 4, 0x90
.type _Z14comp_euclid_sqPKfS0_i,@function
_Z14comp_euclid_sqPKfS0_i: # @_Z14comp_euclid_sqPKfS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_1
# %bb.3: # %.lr.ph.preheader
movl %edx, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rsi,%rcx,4), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB2_4
# %bb.2: # %._crit_edge
retq
.LBB2_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end2:
.size _Z14comp_euclid_sqPKfS0_i, .Lfunc_end2-_Z14comp_euclid_sqPKfS0_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11main_ed_gpuv
.LCPI3_0:
.long 0x3f800000 # float 1
.LCPI3_1:
.long 0x447a0000 # float 1000
.text
.globl _Z11main_ed_gpuv
.p2align 4, 0x90
.type _Z11main_ed_gpuv,@function
_Z11main_ed_gpuv: # @_Z11main_ed_gpuv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 44(%rsp)
movl $0, 40(%rsp)
movl $0, 36(%rsp)
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 160(%rsp), %rdi
callq hipEventCreate
leaq 152(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 240(%rsp), %rdi
callq hipEventCreate
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $16, %edi
callq malloc
movq %rax, %rbx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %r14d, %xmm1
addss %xmm0, %xmm1
movss %xmm1, (%rbx,%r14,4)
incq %r14
cmpq $4, %r14
jne .LBB3_1
# %bb.2:
movl $24, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss %xmm0, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $6, %rax
jne .LBB3_3
# %bb.4:
callq clock
movq %rax, %r13
movl $24, %edi
callq malloc
movq %rax, %r15
movl $24, %edi
callq malloc
movq %rax, %r12
xorl %esi, %esi
movl $2863311531, %edi # imm = 0xAAAAAAAB
movabsq $-6148914691236517205, %r8 # imm = 0xAAAAAAAAAAAAAAAB
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_5: # =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl %ecx, %eax
imulq %rdi, %rax
shrq $33, %rax
addl %eax, %eax
leal (%rax,%rax,2), %eax
movl %esi, %edx
subl %eax, %edx
leaq (%r14,%rdx,4), %r9
movq %rcx, %rax
mulq %r8
andq $-2, %rdx
leaq (%rbx,%rdx,4), %rax
xorps %xmm0, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i
# Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%r9,%rdx,4), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
incq %rdx
cmpq $2, %rdx
jne .LBB3_6
# %bb.7: # %_Z14comp_euclid_sqPKfS0_i.exit
# in Loop: Header=BB3_5 Depth=1
movss %xmm0, (%r12,%rcx,4)
incq %rcx
addl $2, %esi
cmpq $6, %rcx
jne .LBB3_5
# %bb.8:
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
movq 152(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 48(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 56(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq 48(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movl $24, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 152(%rsp), %rsi
movq 240(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
leaq 24(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movl $_Z23EuclideanDistancesNaivePfS_S_ii, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953480, %rdx # imm = 0x2000000008
xorl %edi, %edi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 48(%rsp), %rax
movq 56(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $2, 20(%rsp)
movl $3, 16(%rsp)
leaq 144(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 128(%rsp), %rax
movq %rax, 192(%rsp)
leaq 20(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z23EuclideanDistancesNaivePfS_S_ii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI3_1(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
movq 72(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $24, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $24, %edx
xorl %esi, %esi
callq hipMemset
movq 72(%rsp), %rdi
callq hipEventSynchronize
movq 168(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 44(%rsp), %rdi
callq hipEventElapsedTime
movl $16, %edi
callq malloc
movq %rax, %rcx
movq %rbx, %rdx
.p2align 4, 0x90
.LBB3_11: # %.preheader145
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rcx,%rsi,8)
incq %rsi
cmpq $1, %rsi
je .LBB3_12
# %bb.13: # in Loop: Header=BB3_11 Depth=1
leaq 1(%r13), %rsi
addq $8, %rdx
addq $4, %rcx
testq %r13, %r13
movq %rsi, %r13
je .LBB3_11
# %bb.14:
movq 48(%rsp), %rdi
movl $16, %edx
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_Z22EuclideanDistancesFastPKfS0_Pfii, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
movq 160(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdx # imm = 0x100000002
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 48(%rsp), %rax
movq 56(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $2, 20(%rsp)
movl $3, 16(%rsp)
leaq 144(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 128(%rsp), %rax
movq %rax, 192(%rsp)
leaq 20(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z22EuclideanDistancesFastPKfS0_Pfii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
movq 64(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $24, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, 224(%rsp) # 8-byte Spill
xorl %ecx, %ecx
.LBB3_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
movq %rcx, 232(%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_18: # Parent Loop BB3_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rbp,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss (%r15,%rbp,8), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB3_19
jp .LBB3_19
# %bb.20: # in Loop: Header=BB3_18 Depth=2
incq %rbp
cmpq $3, %rbp
jne .LBB3_18
# %bb.21: # %.critedge
# in Loop: Header=BB3_17 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%r13), %rax
addq $12, %r12
addq $4, %r15
testq %r13, %r13
setne %cl
movq %rax, %r13
je .LBB3_17
jmp .LBB3_22
.LBB3_19:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %r13d, %esi
movl %ebp, %edx
movb $2, %al
callq printf
movl $1, %eax
testb $1, 232(%rsp) # 1-byte Folded Reload
je .LBB3_23
.LBB3_22: # %.critedge132
movq 64(%rsp), %rdi
callq hipEventSynchronize
movq 160(%rsp), %rsi
movq 64(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 44(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss 40(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movss 36(%rsp), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
movl $.L.str.4, %edi
movb $4, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 224(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
.LBB3_23:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11main_ed_gpuv, .Lfunc_end3-_Z11main_ed_gpuv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23EuclideanDistancesNaivePfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22EuclideanDistancesFastPKfS0_Pfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23EuclideanDistancesNaivePfS_S_ii,@object # @_Z23EuclideanDistancesNaivePfS_S_ii
.section .rodata,"a",@progbits
.globl _Z23EuclideanDistancesNaivePfS_S_ii
.p2align 3, 0x0
_Z23EuclideanDistancesNaivePfS_S_ii:
.quad _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.size _Z23EuclideanDistancesNaivePfS_S_ii, 8
.type _Z22EuclideanDistancesFastPKfS0_Pfii,@object # @_Z22EuclideanDistancesFastPKfS0_Pfii
.globl _Z22EuclideanDistancesFastPKfS0_Pfii
.p2align 3, 0x0
_Z22EuclideanDistancesFastPKfS0_Pfii:
.quad _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.size _Z22EuclideanDistancesFastPKfS0_Pfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n"
.size .L.str.1, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n"
.size .L.str.4, 63
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23EuclideanDistancesNaivePfS_S_ii"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22EuclideanDistancesFastPKfS0_Pfii"
.size .L__unnamed_2, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.addrsig_sym _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23EuclideanDistancesNaivePfS_S_ii
.addrsig_sym _Z22EuclideanDistancesFastPKfS0_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22EuclideanDistancesFastPKfS0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0070*/ LEA R2, R0, R15, 0x1 ; /* 0x0000000f00027211 */
/* 0x001fd200078e08ff */
/*0080*/ IMAD.WIDE R2, R2, R17, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0211 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ BSSY B0, 0x200 ; /* 0x0000014000007945 */
/* 0x000fe40003800000 */
/*00c0*/ STS [R15.X4], R2 ; /* 0x000000020f007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 BRA 0x1f0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*00f0*/ LDS.64 R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x001e220000000a00 */
/*0100*/ MOV R11, R15 ; /* 0x0000000f000b7202 */
/* 0x000fca0000000f00 */
/*0110*/ IMAD.WIDE R4, R11, R17, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fca00078e0211 */
/*0120*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001ea2000c1e1900 */
/*0130*/ IMAD.WIDE R6, R17, c[0x0][0x178], R4 ; /* 0x00005e0011067a25 */
/* 0x000fcc00078e0204 */
/*0140*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0150*/ IMAD R8, R0, c[0x0][0x178], R11 ; /* 0x00005e0000087a24 */
/* 0x000fe200078e020b */
/*0160*/ IADD3 R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b7a10 */
/* 0x000fc80007ffe0ff */
/*0170*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fe20003f06270 */
/*0180*/ FADD R9, -R2, R9 ; /* 0x0000000902097221 */
/* 0x005fc80000000100 */
/*0190*/ FFMA R10, R9, R9, RZ ; /* 0x00000009090a7223 */
/* 0x000fe400000000ff */
/*01a0*/ IMAD.WIDE R8, R8, R17, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fc800078e0211 */
/*01b0*/ FADD R13, R6, -R3 ; /* 0x80000003060d7221 */
/* 0x008fc80000000000 */
/*01c0*/ FFMA R13, R13, R13, R10 ; /* 0x0000000d0d0d7223 */
/* 0x000fca000000000a */
/*01d0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001e2000c101904 */
/*01e0*/ @!P0 BRA 0x110 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0200*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fe20007ffe0ff */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0220*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0230*/ @!P0 BRA 0x60 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z23EuclideanDistancesNaivePfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*00b0*/ SHF.L.U32 R4, R7, 0x1, RZ ; /* 0x0000000107047819 */
/* 0x000fe200000006ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ SHF.L.U32 R2, R0, 0x1, RZ ; /* 0x0000000100027819 */
/* 0x000fce00000006ff */
/*00e0*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020d */
/*00f0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e020d */
/*0100*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee2000c1e1900 */
/*0140*/ IMAD R7, R0, c[0x0][0x17c], R7 ; /* 0x00005f0000077a24 */
/* 0x000fc400078e0207 */
/*0150*/ FADD R6, -R6, R9 ; /* 0x0000000906067221 */
/* 0x004fc80000000100 */
/*0160*/ FFMA R0, R6, R6, RZ ; /* 0x0000000606007223 */
/* 0x000fe400000000ff */
/*0170*/ IMAD.WIDE R6, R7, R13, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fc800078e020d */
/*0180*/ FADD R11, -R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc80000000100 */
/*0190*/ FFMA R11, R11, R11, R0 ; /* 0x0000000b0b0b7223 */
/* 0x000fca0000000000 */
/*01a0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23EuclideanDistancesNaivePfS_S_ii
.globl _Z23EuclideanDistancesNaivePfS_S_ii
.p2align 8
.type _Z23EuclideanDistancesNaivePfS_S_ii,@function
_Z23EuclideanDistancesNaivePfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 1, v0
v_lshlrev_b32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v9, vcc_lo
s_mov_b64 s[4:5], 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v7, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
s_add_u32 s4, s4, 4
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[9:10], off
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s4, 4
s_waitcnt vmcnt(0)
v_sub_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v7, v7
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23EuclideanDistancesNaivePfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23EuclideanDistancesNaivePfS_S_ii, .Lfunc_end0-_Z23EuclideanDistancesNaivePfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22EuclideanDistancesFastPKfS0_Pfii
.globl _Z22EuclideanDistancesFastPKfS0_Pfii
.p2align 8
.type _Z22EuclideanDistancesFastPKfS0_Pfii,@function
_Z22EuclideanDistancesFastPKfS0_Pfii:
s_load_b32 s14, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s14
s_cbranch_scc1 .LBB1_8
s_clause 0x3
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s16, s[0:1], 0x20
v_lshlrev_b32_e32 v4, 2, v0
s_add_u32 s10, s0, 32
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[2:3], 2
s_branch .LBB1_3
.LBB1_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s15, s16, s15
s_waitcnt_vscnt null, 0x0
s_cmp_lt_i32 s15, s14
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_8
.LBB1_3:
v_lshl_add_u32 v1, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s6, v1
v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b32 s0, s[10:11], 0xc
v_mov_b32_e32 v1, v0
s_mul_i32 s17, s15, s2
s_mov_b32 s19, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s18, s0, 0xffff
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_5:
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
.LBB1_6:
global_load_b32 v6, v[2:3], off
v_mov_b32_e32 v7, s1
v_add_co_u32 v2, s0, v2, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s13, v3, s0
ds_load_b32 v7, v7
s_add_i32 s1, s1, 4
s_cmp_eq_u32 s1, 4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_f32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v6
s_cbranch_scc1 .LBB1_6
v_add_nc_u32_e32 v2, s17, v1
v_add_nc_u32_e32 v1, s18, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_le_i32_e64 s0, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_or_b32 s19, s0, s19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s1, s8, v2
v_add_co_ci_u32_e64 v3, s1, s9, v3, s1
global_store_b32 v[2:3], v5, off
s_and_not1_b32 exec_lo, exec_lo, s19
s_cbranch_execnz .LBB1_5
s_branch .LBB1_2
.LBB1_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22EuclideanDistancesFastPKfS0_Pfii
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z22EuclideanDistancesFastPKfS0_Pfii, .Lfunc_end1-_Z22EuclideanDistancesFastPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23EuclideanDistancesNaivePfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23EuclideanDistancesNaivePfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22EuclideanDistancesFastPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z22EuclideanDistancesFastPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000df931_00000000-6_euclidean_distance_fast.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14comp_euclid_sqPKfS0_i
.type _Z14comp_euclid_sqPKfS0_i, @function
_Z14comp_euclid_sqPKfS0_i:
.LFB3669:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L6
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
.L5:
movss (%rdi,%rax), %xmm0
subss (%rsi,%rax), %xmm0
mulss %xmm0, %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
movaps %xmm1, %xmm0
ret
.L6:
pxor %xmm1, %xmm1
jmp .L3
.cfi_endproc
.LFE3669:
.size _Z14comp_euclid_sqPKfS0_i, .-_Z14comp_euclid_sqPKfS0_i
.globl _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii
.type _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii, @function
_Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23EuclideanDistancesNaivePfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii, .-_Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii
.globl _Z23EuclideanDistancesNaivePfS_S_ii
.type _Z23EuclideanDistancesNaivePfS_S_ii, @function
_Z23EuclideanDistancesNaivePfS_S_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z23EuclideanDistancesNaivePfS_S_ii, .-_Z23EuclideanDistancesNaivePfS_S_ii
.globl _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii
.type _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii, @function
_Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22EuclideanDistancesFastPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii, .-_Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii
.globl _Z22EuclideanDistancesFastPKfS0_Pfii
.type _Z22EuclideanDistancesFastPKfS0_Pfii, @function
_Z22EuclideanDistancesFastPKfS0_Pfii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z22EuclideanDistancesFastPKfS0_Pfii, .-_Z22EuclideanDistancesFastPKfS0_Pfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "%f "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n"
.section .rodata.str1.1
.LC8:
.string "\n"
.LC9:
.string "Success!\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n"
.text
.globl _Z11main_ed_gpuv
.type _Z11main_ed_gpuv, @function
_Z11main_ed_gpuv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $0x00000000, 20(%rsp)
movl $0x00000000, 24(%rsp)
movl $0x00000000, 28(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
movl $0x3f800000, (%rax)
movl $0x40000000, 4(%rax)
movl $0x40400000, 8(%rax)
movl $0x40800000, 12(%rax)
movl $24, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L25:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $6, %rax
jne .L25
call clock@PLT
movq %rax, %r14
movl $24, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $24, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %ebx
.L26:
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax), %ecx
addl %ecx, %eax
movl %ebx, %edx
subl %eax, %edx
leal (%rdx,%rdx), %eax
cltq
leaq 0(%r13,%rax,4), %rsi
movslq %ecx, %rcx
leaq 0(%rbp,%rcx,4), %rdi
movl $2, %edx
call _Z14comp_euclid_sqPKfS0_i
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq $6, %rbx
jne .L26
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
movss %xmm0, 12(%rsp)
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16, %edx
movq %rbp, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $24, %edx
movq %r13, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 28(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 96(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
movl $2, %esi
leaq _Z23EuclideanDistancesNaivePfS_S_ii(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $1, 112(%rsp)
movl $0, 116(%rsp)
movl $0, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $8, 104(%rsp)
movl $32, 108(%rsp)
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L27:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $24, %edx
movq 96(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $24, %edx
movl $0, %esi
movq 96(%rsp), %rdi
call cudaMemset@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $16, %edi
call malloc@PLT
movq %rax, %rsi
movss 0(%rbp), %xmm0
movss %xmm0, (%rax)
movss 4(%rbp), %xmm0
movss %xmm0, 8(%rax)
movss 8(%rbp), %xmm0
movss %xmm0, 4(%rax)
movss 12(%rbp), %xmm0
movss %xmm0, 12(%rax)
movl $1, %ecx
movl $16, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %esi
leaq _Z22EuclideanDistancesFastPKfS0_Pfii(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $2, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $3, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 136(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 128(%rsp), %rdx
movq 140(%rsp), %rdi
movl 148(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $24, %edx
movq 96(%rsp), %rsi
movq (%rsp), %r14
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %r15d
.L29:
movl $0, %ebx
.L33:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,8), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss (%r14,%rbx,8), %xmm1
movss (%r12,%rbx,4), %xmm0
ucomiss %xmm0, %xmm1
jp .L36
jne .L36
addq $1, %rbx
cmpq $3, %rbx
jne .L33
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
addq $4, %r14
addq $12, %r12
cmpl $2, %r15d
jne .L29
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 24(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
pxor %xmm3, %xmm3
cvtss2sd 28(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtss2sd 24(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movl $0, %eax
.L24:
movq 152(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl $3, %r8d
movl $2, %ecx
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z49__device_stub__Z23EuclideanDistancesNaivePfS_S_iiPfS_S_ii
jmp .L27
.L42:
movl $3, %r8d
movl $2, %ecx
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z50__device_stub__Z22EuclideanDistancesFastPKfS0_PfiiPKfS0_Pfii
jmp .L28
.L36:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movl %r15d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L24
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z11main_ed_gpuv, .-_Z11main_ed_gpuv
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z22EuclideanDistancesFastPKfS0_Pfii"
.align 8
.LC12:
.string "_Z23EuclideanDistancesNaivePfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z22EuclideanDistancesFastPKfS0_Pfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z23EuclideanDistancesNaivePfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "euclidean_distance_fast.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii # -- Begin function _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.p2align 4, 0x90
.type _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii,@function
_Z38__device_stub__EuclideanDistancesNaivePfS_S_ii: # @_Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23EuclideanDistancesNaivePfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii, .Lfunc_end0-_Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii # -- Begin function _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.p2align 4, 0x90
.type _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii,@function
_Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii: # @_Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22EuclideanDistancesFastPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii, .Lfunc_end1-_Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.cfi_endproc
# -- End function
.globl _Z14comp_euclid_sqPKfS0_i # -- Begin function _Z14comp_euclid_sqPKfS0_i
.p2align 4, 0x90
.type _Z14comp_euclid_sqPKfS0_i,@function
_Z14comp_euclid_sqPKfS0_i: # @_Z14comp_euclid_sqPKfS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_1
# %bb.3: # %.lr.ph.preheader
movl %edx, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rsi,%rcx,4), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB2_4
# %bb.2: # %._crit_edge
retq
.LBB2_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end2:
.size _Z14comp_euclid_sqPKfS0_i, .Lfunc_end2-_Z14comp_euclid_sqPKfS0_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11main_ed_gpuv
.LCPI3_0:
.long 0x3f800000 # float 1
.LCPI3_1:
.long 0x447a0000 # float 1000
.text
.globl _Z11main_ed_gpuv
.p2align 4, 0x90
.type _Z11main_ed_gpuv,@function
_Z11main_ed_gpuv: # @_Z11main_ed_gpuv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 44(%rsp)
movl $0, 40(%rsp)
movl $0, 36(%rsp)
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 160(%rsp), %rdi
callq hipEventCreate
leaq 152(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 240(%rsp), %rdi
callq hipEventCreate
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $16, %edi
callq malloc
movq %rax, %rbx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %r14d, %xmm1
addss %xmm0, %xmm1
movss %xmm1, (%rbx,%r14,4)
incq %r14
cmpq $4, %r14
jne .LBB3_1
# %bb.2:
movl $24, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss %xmm0, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $6, %rax
jne .LBB3_3
# %bb.4:
callq clock
movq %rax, %r13
movl $24, %edi
callq malloc
movq %rax, %r15
movl $24, %edi
callq malloc
movq %rax, %r12
xorl %esi, %esi
movl $2863311531, %edi # imm = 0xAAAAAAAB
movabsq $-6148914691236517205, %r8 # imm = 0xAAAAAAAAAAAAAAAB
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_5: # =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl %ecx, %eax
imulq %rdi, %rax
shrq $33, %rax
addl %eax, %eax
leal (%rax,%rax,2), %eax
movl %esi, %edx
subl %eax, %edx
leaq (%r14,%rdx,4), %r9
movq %rcx, %rax
mulq %r8
andq $-2, %rdx
leaq (%rbx,%rdx,4), %rax
xorps %xmm0, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i
# Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%r9,%rdx,4), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
incq %rdx
cmpq $2, %rdx
jne .LBB3_6
# %bb.7: # %_Z14comp_euclid_sqPKfS0_i.exit
# in Loop: Header=BB3_5 Depth=1
movss %xmm0, (%r12,%rcx,4)
incq %rcx
addl $2, %esi
cmpq $6, %rcx
jne .LBB3_5
# %bb.8:
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
movq 152(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 48(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 56(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq 48(%rsp), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movl $24, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 152(%rsp), %rsi
movq 240(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
leaq 24(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movl $_Z23EuclideanDistancesNaivePfS_S_ii, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953480, %rdx # imm = 0x2000000008
xorl %edi, %edi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 48(%rsp), %rax
movq 56(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $2, 20(%rsp)
movl $3, 16(%rsp)
leaq 144(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 128(%rsp), %rax
movq %rax, 192(%rsp)
leaq 20(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z23EuclideanDistancesNaivePfS_S_ii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI3_1(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
movq 72(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $24, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $24, %edx
xorl %esi, %esi
callq hipMemset
movq 72(%rsp), %rdi
callq hipEventSynchronize
movq 168(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 44(%rsp), %rdi
callq hipEventElapsedTime
movl $16, %edi
callq malloc
movq %rax, %rcx
movq %rbx, %rdx
.p2align 4, 0x90
.LBB3_11: # %.preheader145
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rcx,%rsi,8)
incq %rsi
cmpq $1, %rsi
je .LBB3_12
# %bb.13: # in Loop: Header=BB3_11 Depth=1
leaq 1(%r13), %rsi
addq $8, %rdx
addq $4, %rcx
testq %r13, %r13
movq %rsi, %r13
je .LBB3_11
# %bb.14:
movq 48(%rsp), %rdi
movl $16, %edx
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_Z22EuclideanDistancesFastPKfS0_Pfii, %edi
movl $2, %esi
callq hipFuncSetCacheConfig
movq 160(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdx # imm = 0x100000002
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 48(%rsp), %rax
movq 56(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $2, 20(%rsp)
movl $3, 16(%rsp)
leaq 144(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 128(%rsp), %rax
movq %rax, 192(%rsp)
leaq 20(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z22EuclideanDistancesFastPKfS0_Pfii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
movq 64(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $24, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, 224(%rsp) # 8-byte Spill
xorl %ecx, %ecx
.LBB3_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
movq %rcx, 232(%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_18: # Parent Loop BB3_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rbp,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss (%r15,%rbp,8), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB3_19
jp .LBB3_19
# %bb.20: # in Loop: Header=BB3_18 Depth=2
incq %rbp
cmpq $3, %rbp
jne .LBB3_18
# %bb.21: # %.critedge
# in Loop: Header=BB3_17 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%r13), %rax
addq $12, %r12
addq $4, %r15
testq %r13, %r13
setne %cl
movq %rax, %r13
je .LBB3_17
jmp .LBB3_22
.LBB3_19:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %r13d, %esi
movl %ebp, %edx
movb $2, %al
callq printf
movl $1, %eax
testb $1, 232(%rsp) # 1-byte Folded Reload
je .LBB3_23
.LBB3_22: # %.critedge132
movq 64(%rsp), %rdi
callq hipEventSynchronize
movq 160(%rsp), %rsi
movq 64(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 44(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss 40(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movss 36(%rsp), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
movl $.L.str.4, %edi
movb $4, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 224(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
.LBB3_23:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11main_ed_gpuv, .Lfunc_end3-_Z11main_ed_gpuv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23EuclideanDistancesNaivePfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22EuclideanDistancesFastPKfS0_Pfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23EuclideanDistancesNaivePfS_S_ii,@object # @_Z23EuclideanDistancesNaivePfS_S_ii
.section .rodata,"a",@progbits
.globl _Z23EuclideanDistancesNaivePfS_S_ii
.p2align 3, 0x0
_Z23EuclideanDistancesNaivePfS_S_ii:
.quad _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.size _Z23EuclideanDistancesNaivePfS_S_ii, 8
.type _Z22EuclideanDistancesFastPKfS0_Pfii,@object # @_Z22EuclideanDistancesFastPKfS0_Pfii
.globl _Z22EuclideanDistancesFastPKfS0_Pfii
.p2align 3, 0x0
_Z22EuclideanDistancesFastPKfS0_Pfii:
.quad _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.size _Z22EuclideanDistancesFastPKfS0_Pfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cpu/kernel4 mismatch at %d,%d, cpu: %f, kernel4: %f\n"
.size .L.str.1, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU: %.fms, kernel1 : %.fms, kernel2 : %.fms, Mem copy: %.fms\n"
.size .L.str.4, 63
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23EuclideanDistancesNaivePfS_S_ii"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22EuclideanDistancesFastPKfS0_Pfii"
.size .L__unnamed_2, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__EuclideanDistancesNaivePfS_S_ii
.addrsig_sym _Z37__device_stub__EuclideanDistancesFastPKfS0_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23EuclideanDistancesNaivePfS_S_ii
.addrsig_sym _Z22EuclideanDistancesFastPKfS0_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ int evalDirt() {
return 4;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ int evalDirt() {
return 4;
} | .file "tmpxft_000af1d1_00000000-6_dirt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8evalDirtv
.type _Z8evalDirtv, @function
_Z8evalDirtv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8evalDirtv, .-_Z8evalDirtv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ int evalDirt() {
return 4;
} | #include <hip/hip_runtime.h>
__device__ int evalDirt() {
return 4;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ int evalDirt() {
return 4;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ int evalDirt() {
return 4;
} | .text
.file "dirt.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000af1d1_00000000-6_dirt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8evalDirtv
.type _Z8evalDirtv, @function
_Z8evalDirtv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8evalDirtv, .-_Z8evalDirtv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dirt.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2
__device__ void store_full(float*,float*,int);
__device__ void load_full(float*,float*,int);
__device__ void potrf_tile(float*,int,int);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,int,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);
__device__ void store_zeros(float*,int);
__device__ void store_zeros_diagonal(float*,int,int);
__device__ void store_zeros_last(float*,int);
__device__ void store_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID + N*N*blockIdx.x] = read_data[ID];
}
}
__syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID] = read_data[ID + N*N*blockIdx.x];
}
}
__syncthreads();
}
__device__ void potrf_tile(float* t_A,int i,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int k=0;k<TILE_SIZE;k++)
{
if(t_x==t_y && t_x==k)
{
t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x] = sqrtf(t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x]);
}
__syncthreads();
if(t_x<t_y && t_x == k)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]/= t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x];
}
__syncthreads();
if(k<t_y && k<t_x && t_x<=t_y)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]-= t_A[i*TILE_SIZE*(1+N) + t_x*N + k]*t_A[i*TILE_SIZE*(1+N) + t_y*N + k];
}
__syncthreads();
}
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int s=0;s<TILE_SIZE;s++)
{
if(t_x==s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]/= row_data[i*TILE_SIZE*(1+N) + t_x*(1+N)];
}
__syncthreads();
if(t_x > s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]-= row_data[(t_x + i*TILE_SIZE)*N + s]*row_data[(t_y + j*TILE_SIZE)*N + s];
}
__syncthreads();
}
}
__device__ void syrk_tile(float* row_data,int i,int j,int k,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
float valueToSubtract = 0.0;
for(int r=0;r<TILE_SIZE;r++)
{
valueToSubtract+= row_data[(t_x + k*TILE_SIZE)*N + i*TILE_SIZE + r]*row_data[(t_y + j*TILE_SIZE)*N + i*TILE_SIZE + r];
}
row_data[(t_y + j*TILE_SIZE)*N + t_x + k*TILE_SIZE]-= valueToSubtract;
__syncthreads();
}
__device__ void store_zeros(float* A,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i,j;
for(i=0;i<N/TILE_SIZE-1;i++)
{
for(j=i+1;j<N/TILE_SIZE;j++)
A[j*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_diagonal(float* A,int N,int b) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i;
for(i=0;i<N/TILE_SIZE-b;i+=2)
{
if(t_x>t_y)
A[i*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
if(t_x<t_y)
A[(i+1)*blockDim.x*(1+N) + (blockDim.x-t_x-1) + (blockDim.y-t_y-1)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_last(float* A,int N) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
if(t_x>t_y)
A[(N/TILE_SIZE-1)*blockDim.x*(1+N) + t_x + t_y*N] = 0.0;
__syncthreads();
}
__global__ void right_looking_launch_kernel(float* read_data,int N)
{
extern __shared__ float data[];
int i,j,k;
load_full(read_data,data,N);
for(i=0;i<N/TILE_SIZE;i++)
{
potrf_tile(data,i,N);
for(j=i+1;j<N/TILE_SIZE;j++)
{
trsm_tile(data,i,j,N);
for(k=i+1;k<=j;k++)
{
syrk_tile(data,i,j,k,N);
}
}
}
store_zeros(data,N);
if((N/TILE_SIZE)%2==0)
store_zeros_diagonal(data,N,0);
else
{
store_zeros_diagonal(data,N,1);
store_zeros_last(data,N);
}
store_full(data,read_data,N);
} | .file "tmpxft_0015b61b_00000000-6_right_looking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10store_fullPfS_i
.type _Z10store_fullPfS_i, @function
_Z10store_fullPfS_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10store_fullPfS_i, .-_Z10store_fullPfS_i
.globl _Z9load_fullPfS_i
.type _Z9load_fullPfS_i, @function
_Z9load_fullPfS_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z9load_fullPfS_i, .-_Z9load_fullPfS_i
.globl _Z10potrf_tilePfii
.type _Z10potrf_tilePfii, @function
_Z10potrf_tilePfii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10potrf_tilePfii, .-_Z10potrf_tilePfii
.globl _Z9trsm_tilePfiii
.type _Z9trsm_tilePfiii, @function
_Z9trsm_tilePfiii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z9trsm_tilePfiii, .-_Z9trsm_tilePfiii
.globl _Z9syrk_tilePfiiii
.type _Z9syrk_tilePfiiii, @function
_Z9syrk_tilePfiiii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z9syrk_tilePfiiii, .-_Z9syrk_tilePfiiii
.globl _Z11store_zerosPfi
.type _Z11store_zerosPfi, @function
_Z11store_zerosPfi:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z11store_zerosPfi, .-_Z11store_zerosPfi
.globl _Z20store_zeros_diagonalPfii
.type _Z20store_zeros_diagonalPfii, @function
_Z20store_zeros_diagonalPfii:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z20store_zeros_diagonalPfii, .-_Z20store_zeros_diagonalPfii
.globl _Z16store_zeros_lastPfi
.type _Z16store_zeros_lastPfi, @function
_Z16store_zeros_lastPfi:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z16store_zeros_lastPfi, .-_Z16store_zeros_lastPfi
.globl _Z48__device_stub__Z27right_looking_launch_kernelPfiPfi
.type _Z48__device_stub__Z27right_looking_launch_kernelPfiPfi, @function
_Z48__device_stub__Z27right_looking_launch_kernelPfiPfi:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z27right_looking_launch_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z48__device_stub__Z27right_looking_launch_kernelPfiPfi, .-_Z48__device_stub__Z27right_looking_launch_kernelPfiPfi
.globl _Z27right_looking_launch_kernelPfi
.type _Z27right_looking_launch_kernelPfi, @function
_Z27right_looking_launch_kernelPfi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z27right_looking_launch_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z27right_looking_launch_kernelPfi, .-_Z27right_looking_launch_kernelPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27right_looking_launch_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27right_looking_launch_kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2
__device__ void store_full(float*,float*,int);
__device__ void load_full(float*,float*,int);
__device__ void potrf_tile(float*,int,int);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,int,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);
__device__ void store_zeros(float*,int);
__device__ void store_zeros_diagonal(float*,int,int);
__device__ void store_zeros_last(float*,int);
__device__ void store_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID + N*N*blockIdx.x] = read_data[ID];
}
}
__syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID] = read_data[ID + N*N*blockIdx.x];
}
}
__syncthreads();
}
__device__ void potrf_tile(float* t_A,int i,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int k=0;k<TILE_SIZE;k++)
{
if(t_x==t_y && t_x==k)
{
t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x] = sqrtf(t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x]);
}
__syncthreads();
if(t_x<t_y && t_x == k)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]/= t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x];
}
__syncthreads();
if(k<t_y && k<t_x && t_x<=t_y)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]-= t_A[i*TILE_SIZE*(1+N) + t_x*N + k]*t_A[i*TILE_SIZE*(1+N) + t_y*N + k];
}
__syncthreads();
}
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int s=0;s<TILE_SIZE;s++)
{
if(t_x==s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]/= row_data[i*TILE_SIZE*(1+N) + t_x*(1+N)];
}
__syncthreads();
if(t_x > s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]-= row_data[(t_x + i*TILE_SIZE)*N + s]*row_data[(t_y + j*TILE_SIZE)*N + s];
}
__syncthreads();
}
}
__device__ void syrk_tile(float* row_data,int i,int j,int k,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
float valueToSubtract = 0.0;
for(int r=0;r<TILE_SIZE;r++)
{
valueToSubtract+= row_data[(t_x + k*TILE_SIZE)*N + i*TILE_SIZE + r]*row_data[(t_y + j*TILE_SIZE)*N + i*TILE_SIZE + r];
}
row_data[(t_y + j*TILE_SIZE)*N + t_x + k*TILE_SIZE]-= valueToSubtract;
__syncthreads();
}
__device__ void store_zeros(float* A,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i,j;
for(i=0;i<N/TILE_SIZE-1;i++)
{
for(j=i+1;j<N/TILE_SIZE;j++)
A[j*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_diagonal(float* A,int N,int b) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i;
for(i=0;i<N/TILE_SIZE-b;i+=2)
{
if(t_x>t_y)
A[i*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
if(t_x<t_y)
A[(i+1)*blockDim.x*(1+N) + (blockDim.x-t_x-1) + (blockDim.y-t_y-1)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_last(float* A,int N) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
if(t_x>t_y)
A[(N/TILE_SIZE-1)*blockDim.x*(1+N) + t_x + t_y*N] = 0.0;
__syncthreads();
}
__global__ void right_looking_launch_kernel(float* read_data,int N)
{
extern __shared__ float data[];
int i,j,k;
load_full(read_data,data,N);
for(i=0;i<N/TILE_SIZE;i++)
{
potrf_tile(data,i,N);
for(j=i+1;j<N/TILE_SIZE;j++)
{
trsm_tile(data,i,j,N);
for(k=i+1;k<=j;k++)
{
syrk_tile(data,i,j,k,N);
}
}
}
store_zeros(data,N);
if((N/TILE_SIZE)%2==0)
store_zeros_diagonal(data,N,0);
else
{
store_zeros_diagonal(data,N,1);
store_zeros_last(data,N);
}
store_full(data,read_data,N);
} | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2
__device__ void store_full(float*,float*,int);
__device__ void load_full(float*,float*,int);
__device__ void potrf_tile(float*,int,int);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,int,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);
__device__ void store_zeros(float*,int);
__device__ void store_zeros_diagonal(float*,int,int);
__device__ void store_zeros_last(float*,int);
__device__ void store_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID + N*N*blockIdx.x] = read_data[ID];
}
}
__syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID] = read_data[ID + N*N*blockIdx.x];
}
}
__syncthreads();
}
__device__ void potrf_tile(float* t_A,int i,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int k=0;k<TILE_SIZE;k++)
{
if(t_x==t_y && t_x==k)
{
t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x] = sqrtf(t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x]);
}
__syncthreads();
if(t_x<t_y && t_x == k)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]/= t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x];
}
__syncthreads();
if(k<t_y && k<t_x && t_x<=t_y)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]-= t_A[i*TILE_SIZE*(1+N) + t_x*N + k]*t_A[i*TILE_SIZE*(1+N) + t_y*N + k];
}
__syncthreads();
}
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int s=0;s<TILE_SIZE;s++)
{
if(t_x==s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]/= row_data[i*TILE_SIZE*(1+N) + t_x*(1+N)];
}
__syncthreads();
if(t_x > s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]-= row_data[(t_x + i*TILE_SIZE)*N + s]*row_data[(t_y + j*TILE_SIZE)*N + s];
}
__syncthreads();
}
}
__device__ void syrk_tile(float* row_data,int i,int j,int k,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
float valueToSubtract = 0.0;
for(int r=0;r<TILE_SIZE;r++)
{
valueToSubtract+= row_data[(t_x + k*TILE_SIZE)*N + i*TILE_SIZE + r]*row_data[(t_y + j*TILE_SIZE)*N + i*TILE_SIZE + r];
}
row_data[(t_y + j*TILE_SIZE)*N + t_x + k*TILE_SIZE]-= valueToSubtract;
__syncthreads();
}
__device__ void store_zeros(float* A,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i,j;
for(i=0;i<N/TILE_SIZE-1;i++)
{
for(j=i+1;j<N/TILE_SIZE;j++)
A[j*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_diagonal(float* A,int N,int b) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i;
for(i=0;i<N/TILE_SIZE-b;i+=2)
{
if(t_x>t_y)
A[i*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
if(t_x<t_y)
A[(i+1)*blockDim.x*(1+N) + (blockDim.x-t_x-1) + (blockDim.y-t_y-1)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_last(float* A,int N) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
if(t_x>t_y)
A[(N/TILE_SIZE-1)*blockDim.x*(1+N) + t_x + t_y*N] = 0.0;
__syncthreads();
}
__global__ void right_looking_launch_kernel(float* read_data,int N)
{
extern __shared__ float data[];
int i,j,k;
load_full(read_data,data,N);
for(i=0;i<N/TILE_SIZE;i++)
{
potrf_tile(data,i,N);
for(j=i+1;j<N/TILE_SIZE;j++)
{
trsm_tile(data,i,j,N);
for(k=i+1;k<=j;k++)
{
syrk_tile(data,i,j,k,N);
}
}
}
store_zeros(data,N);
if((N/TILE_SIZE)%2==0)
store_zeros_diagonal(data,N,0);
else
{
store_zeros_diagonal(data,N,1);
store_zeros_last(data,N);
}
store_full(data,read_data,N);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2
__device__ void store_full(float*,float*,int);
__device__ void load_full(float*,float*,int);
__device__ void potrf_tile(float*,int,int);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,int,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);
__device__ void store_zeros(float*,int);
__device__ void store_zeros_diagonal(float*,int,int);
__device__ void store_zeros_last(float*,int);
__device__ void store_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID + N*N*blockIdx.x] = read_data[ID];
}
}
__syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID] = read_data[ID + N*N*blockIdx.x];
}
}
__syncthreads();
}
__device__ void potrf_tile(float* t_A,int i,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int k=0;k<TILE_SIZE;k++)
{
if(t_x==t_y && t_x==k)
{
t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x] = sqrtf(t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x]);
}
__syncthreads();
if(t_x<t_y && t_x == k)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]/= t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x];
}
__syncthreads();
if(k<t_y && k<t_x && t_x<=t_y)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]-= t_A[i*TILE_SIZE*(1+N) + t_x*N + k]*t_A[i*TILE_SIZE*(1+N) + t_y*N + k];
}
__syncthreads();
}
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int s=0;s<TILE_SIZE;s++)
{
if(t_x==s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]/= row_data[i*TILE_SIZE*(1+N) + t_x*(1+N)];
}
__syncthreads();
if(t_x > s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]-= row_data[(t_x + i*TILE_SIZE)*N + s]*row_data[(t_y + j*TILE_SIZE)*N + s];
}
__syncthreads();
}
}
__device__ void syrk_tile(float* row_data,int i,int j,int k,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
float valueToSubtract = 0.0;
for(int r=0;r<TILE_SIZE;r++)
{
valueToSubtract+= row_data[(t_x + k*TILE_SIZE)*N + i*TILE_SIZE + r]*row_data[(t_y + j*TILE_SIZE)*N + i*TILE_SIZE + r];
}
row_data[(t_y + j*TILE_SIZE)*N + t_x + k*TILE_SIZE]-= valueToSubtract;
__syncthreads();
}
__device__ void store_zeros(float* A,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i,j;
for(i=0;i<N/TILE_SIZE-1;i++)
{
for(j=i+1;j<N/TILE_SIZE;j++)
A[j*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_diagonal(float* A,int N,int b) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i;
for(i=0;i<N/TILE_SIZE-b;i+=2)
{
if(t_x>t_y)
A[i*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
if(t_x<t_y)
A[(i+1)*blockDim.x*(1+N) + (blockDim.x-t_x-1) + (blockDim.y-t_y-1)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_last(float* A,int N) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
if(t_x>t_y)
A[(N/TILE_SIZE-1)*blockDim.x*(1+N) + t_x + t_y*N] = 0.0;
__syncthreads();
}
__global__ void right_looking_launch_kernel(float* read_data,int N)
{
extern __shared__ float data[];
int i,j,k;
load_full(read_data,data,N);
for(i=0;i<N/TILE_SIZE;i++)
{
potrf_tile(data,i,N);
for(j=i+1;j<N/TILE_SIZE;j++)
{
trsm_tile(data,i,j,N);
for(k=i+1;k<=j;k++)
{
syrk_tile(data,i,j,k,N);
}
}
}
store_zeros(data,N);
if((N/TILE_SIZE)%2==0)
store_zeros_diagonal(data,N,0);
else
{
store_zeros_diagonal(data,N,1);
store_zeros_last(data,N);
}
store_full(data,read_data,N);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27right_looking_launch_kernelPfi
.globl _Z27right_looking_launch_kernelPfi
.p2align 8
.type _Z27right_looking_launch_kernelPfi,@function
_Z27right_looking_launch_kernelPfi:
s_clause 0x1
s_load_b32 s9, s[0:1], 0x8
s_load_b64 s[6:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s9, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s9, s2
s_ashr_i32 s8, s2, 1
s_cmp_gt_i32 s9, 1
s_cselect_b32 s10, -1, 0
s_cmp_lt_i32 s9, 2
s_cbranch_scc1 .LBB0_5
v_mad_u64_u32 v[5:6], null, s15, s9, v[1:2]
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s2, 0
s_lshl_b32 s3, s9, 3
s_lshl_b32 s4, s9, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, v1, s9, v[4:5]
v_mad_u64_u32 v[2:3], null, s9, v5, v[4:5]
v_mov_b32_e32 v4, 0
v_lshl_add_u32 v5, v6, 2, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v6, v5
s_mov_b32 s5, s8
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, 2, v3
s_add_i32 s5, s5, -1
s_cmp_lg_u32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
ds_store_b32 v6, v7
v_add_nc_u32_e32 v6, 8, v6
s_cbranch_scc1 .LBB0_3
v_add_nc_u32_e32 v5, s3, v5
v_add_nc_u32_e32 v2, s4, v2
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, s8
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_cmp_lt_i32 s9, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_30
v_add_nc_u32_e32 v4, 2, v1
v_mul_lo_u32 v3, v1, s9
s_lshl_b32 s12, s9, 3
s_mov_b32 s4, 0
s_mov_b32 s11, 2
v_mul_lo_u32 v8, s9, v4
s_add_i32 s13, s9, 1
s_add_i32 s14, s12, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v6, v3, 2, 0
v_lshlrev_b32_e32 v12, 2, v3
v_lshl_add_u32 v8, v8, 2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v13, v8 :: v_dual_and_b32 v2, 0x3ff, v0
v_mul_lo_u32 v10, v2, s9
v_cmp_gt_u32_e32 vcc_lo, v2, v1
v_cmp_eq_u32_e64 s2, v2, v1
v_cmp_lt_u32_e64 s3, v2, v1
v_min_u32_e32 v4, v1, v2
v_lshlrev_b32_e32 v11, 2, v2
s_xor_b32 s16, vcc_lo, -1
v_lshl_add_u32 v7, v10, 2, 0
v_add_nc_u32_e32 v5, 2, v2
v_lshlrev_b32_e32 v10, 2, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v14, v7
v_mul_lo_u32 v9, s9, v5
v_lshl_add_u32 v5, v2, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v9, v9, 2, 0
s_branch .LBB0_8
.LBB0_7:
v_add_nc_u32_e32 v6, s14, v6
v_add_nc_u32_e32 v14, s14, v14
v_add_nc_u32_e32 v13, s12, v13
v_add_nc_u32_e32 v7, s12, v7
v_add_nc_u32_e32 v8, s14, v8
v_add_nc_u32_e32 v9, s14, v9
s_add_i32 s11, s11, 1
s_cmp_eq_u32 s4, s8
s_cbranch_scc1 .LBB0_30
.LBB0_8:
s_lshl_b32 s18, s4, 1
s_mov_b32 s17, s4
s_mul_i32 s4, s18, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v19, v6 :: v_dual_add_nc_u32 v18, s4, v3
v_mov_b32_e32 v15, v14
s_lshl_b32 s5, s4, 2
s_mov_b32 s19, 0
s_add_i32 s4, s5, 0
v_lshl_add_u32 v18, v18, 2, v5
v_add3_u32 v16, s4, v10, v11
v_add3_u32 v17, s4, v12, v11
s_branch .LBB0_10
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v19, 4, v19
v_add_nc_u32_e32 v15, 4, v15
s_add_i32 s19, s19, 1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s19, 1
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_16
.LBB0_10:
v_cmp_eq_u32_e32 vcc_lo, s19, v2
s_and_b32 s4, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s20, s4
s_cbranch_execz .LBB0_12
ds_load_b32 v20, v16
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v21, 0x4f800000, v20
v_cmp_gt_f32_e64 s4, 0xf800000, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v20, v20, v21, s4
v_sqrt_f32_e32 v21, v20
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v22, -1, v21
v_add_nc_u32_e32 v23, 1, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v24, -v22, v21, v20
v_fma_f32 v25, -v23, v21, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s5, 0, v24
v_cndmask_b32_e64 v21, v21, v22, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s5, 0, v25
v_cndmask_b32_e64 v21, v21, v23, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v22, 0x37800000, v21
v_cndmask_b32_e64 v21, v21, v22, s4
v_cmp_class_f32_e64 s4, v20, 0x260
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v20, v21, v20, s4
ds_store_b32 v16, v20
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s20
s_and_b32 s5, s3, vcc_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_14
ds_load_b32 v20, v16
ds_load_b32 v21, v17
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v22, null, v20, v20, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v23, v22
s_waitcnt_depctr 0xfff
v_fma_f32 v24, -v22, v23, 1.0
v_fmac_f32_e32 v23, v24, v23
v_div_scale_f32 v24, vcc_lo, v21, v20, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v25, v24, v23
v_fma_f32 v26, -v22, v25, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v25, v26, v23
v_fma_f32 v22, -v22, v25, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v22, v22, v23, v25
v_div_fixup_f32 v20, v22, v20, v21
ds_store_b32 v17, v20
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_lt_u32_e32 vcc_lo, s19, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s5, s16, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_9
ds_load_b32 v20, v15
ds_load_b32 v21, v19
ds_load_b32 v22, v18
s_waitcnt lgkmcnt(0)
v_fma_f32 v20, -v20, v21, v22
ds_store_b32 v18, v20
s_branch .LBB0_9
.LBB0_16:
s_add_i32 s4, s17, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s4, s8
s_cbranch_scc1 .LBB0_7
v_dual_mov_b32 v16, v8 :: v_dual_add_nc_u32 v15, s18, v2
v_mov_b32_e32 v18, v13
s_mov_b32 s5, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v15, s13
v_lshl_add_u32 v15, s18, 2, v5
s_mov_b32 s18, s4
v_lshl_add_u32 v17, v17, 2, 0
s_branch .LBB0_19
.LBB0_18:
v_add_nc_u32_e32 v18, s12, v18
v_add_nc_u32_e32 v16, s12, v16
s_add_i32 s18, s18, 1
s_add_i32 s5, s5, 1
s_cmp_ge_i32 s18, s8
s_cbranch_scc1 .LBB0_7
.LBB0_19:
v_lshl_add_u32 v19, s18, 1, v1
v_mov_b32_e32 v20, v7
v_mov_b32_e32 v22, v18
s_mov_b32 s19, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v19, v19, s9
v_lshl_add_u32 v21, v19, 2, v15
s_branch .LBB0_21
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s20
v_add_nc_u32_e32 v22, 4, v22
v_add_nc_u32_e32 v20, 4, v20
s_add_i32 s19, s19, 1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s19, 1
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_25
.LBB0_21:
s_mov_b32 s20, exec_lo
v_cmpx_eq_u32_e64 s19, v2
s_cbranch_execz .LBB0_23
ds_load_b32 v23, v17
ds_load_b32 v24, v21
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v25, null, v23, v23, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v26, v25
s_waitcnt_depctr 0xfff
v_fma_f32 v27, -v25, v26, 1.0
v_fmac_f32_e32 v26, v27, v26
v_div_scale_f32 v27, vcc_lo, v24, v23, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v28, v27, v26
v_fma_f32 v29, -v25, v28, v27
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v28, v29, v26
v_fma_f32 v25, -v25, v28, v27
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v25, v25, v26, v28
v_div_fixup_f32 v23, v25, v23, v24
ds_store_b32 v21, v23
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s20
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s20, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_lt_u32_e64 s19, v2
s_cbranch_execz .LBB0_20
ds_load_b32 v23, v20
ds_load_b32 v24, v22
ds_load_b32 v25, v21
s_waitcnt lgkmcnt(0)
v_fma_f32 v23, -v23, v24, v25
ds_store_b32 v21, v23
s_branch .LBB0_20
.LBB0_25:
s_cmp_ge_u32 s17, s18
s_cbranch_scc1 .LBB0_18
v_dual_mov_b32 v20, v9 :: v_dual_lshlrev_b32 v19, 2, v19
s_mov_b32 s19, s4
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v19, 0, v19, v11
.p2align 6
.LBB0_27:
v_mov_b32_e32 v21, 0
s_mov_b32 s20, 0
.LBB0_28:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v22, s20, v20
v_add_nc_u32_e32 v23, s20, v16
s_add_i32 s20, s20, 4
ds_load_b32 v22, v22
ds_load_b32 v23, v23
s_cmp_eq_u32 s20, 4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v21, v22, v23
s_cbranch_scc1 .LBB0_28
v_lshl_add_u32 v22, s19, 3, v19
s_add_i32 s19, s19, 1
v_add_nc_u32_e32 v20, s12, v20
s_cmp_lg_u32 s19, s5
ds_load_b32 v23, v22
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v21, v23, v21
ds_store_b32 v22, v21
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_27
s_branch .LBB0_18
.LBB0_30:
s_cmp_lt_i32 s9, 4
s_mov_b32 s4, 4
s_cbranch_scc1 .LBB0_36
v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x3ff, v0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_max_i32 s5, s8, 2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
s_add_i32 s5, s5, -2
s_mov_b32 s12, 0
s_lshl_b32 s11, s9, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_33
.p2align 6
.LBB0_32:
s_add_i32 s4, s4, 4
s_cmp_eq_u32 s13, s5
s_cbranch_scc1 .LBB0_36
.LBB0_33:
s_mov_b32 s13, s12
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s12, s8
s_cbranch_scc1 .LBB0_32
s_load_b32 s14, s[2:3], 0xc
s_waitcnt lgkmcnt(0)
s_lshr_b32 s16, s14, 16
s_and_b32 s14, s14, 0xffff
v_mad_u64_u32 v[4:5], null, s13, s16, v[1:2]
s_mul_i32 s16, s4, s14
s_lshl_b32 s14, s14, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s11, v4
v_add3_u32 v4, v4, s16, v2
s_mov_b32 s16, s12
.LBB0_35:
ds_store_b32 v4, v3
v_add_nc_u32_e32 v4, s14, v4
s_add_i32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s16, s8
s_cbranch_scc0 .LBB0_35
s_branch .LBB0_32
.LBB0_36:
s_set_inst_prefetch_distance 0x2
s_bitcmp1_b32 s8, 0
v_and_b32_e32 v2, 0x3ff, v0
s_cselect_b32 s2, -1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 vcc_lo, exec_lo, s2
s_mov_b32 s2, -1
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_47
s_cmp_lt_i32 s9, 4
s_cbranch_scc1 .LBB0_44
v_not_b32_e32 v6, v2
s_add_i32 s3, s8, -1
v_lshl_add_u32 v3, v2, 2, 0
v_cmp_gt_u32_e32 vcc_lo, v2, v1
s_add_u32 s4, s0, 16
v_cmp_lt_u32_e64 s2, v2, v1
v_not_b32_e32 v4, v1
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v6, 2, v6
s_addc_u32 s5, s1, 0
s_lshl_b32 s13, s9, 1
s_mov_b32 s11, 0
s_add_i32 s12, s9, 1
s_add_i32 s13, s13, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_40
.p2align 6
.LBB0_39:
s_or_b32 exec_lo, exec_lo, s14
s_add_i32 s11, s11, 2
s_add_i32 s12, s12, s13
s_cmp_lt_i32 s11, s3
s_cbranch_scc0 .LBB0_44
.LBB0_40:
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_42
s_load_b32 s16, s[4:5], 0xc
s_waitcnt lgkmcnt(0)
s_lshr_b32 s17, s16, 16
s_and_b32 s16, s16, 0xffff
v_mad_u64_u32 v[7:8], null, s11, s17, v[1:2]
s_mul_i32 s16, s11, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b32 s16, s16, 2
v_mul_lo_u32 v7, v7, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v7, 2, v7
v_add3_u32 v7, v3, s16, v7
ds_store_b32 v7, v5
.LBB0_42:
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_39
s_load_b32 s16, s[4:5], 0xc
s_waitcnt lgkmcnt(0)
s_lshr_b32 s17, s16, 16
s_and_b32 s16, s16, 0xffff
v_add_nc_u32_e32 v7, s17, v4
s_mul_i32 s17, s12, s16
s_lshl_b32 s16, s16, 2
s_lshl_b32 s17, s17, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_add_i32 s17, s17, 0
v_mul_lo_u32 v7, v7, s9
s_add_i32 s17, s17, s16
v_lshlrev_b32_e32 v7, 2, v7
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v7, s17, v6, v7
ds_store_b32 v7, v5
s_branch .LBB0_39
.LBB0_44:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 v2, v1
s_cbranch_execz .LBB0_46
s_load_b32 s3, s[0:1], 0x1c
v_mul_lo_u32 v3, v1, s9
s_add_i32 s4, s8, -1
s_add_i32 s5, s9, 1
v_lshlrev_b32_e32 v4, 2, v2
s_mul_i32 s4, s4, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v3, 2, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_mul_i32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s3, s4, 2
s_add_i32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v3, s3, v4, v3
v_mov_b32_e32 v4, 0
ds_store_b32 v3, v4
.LBB0_46:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_mov_b32 s2, 0
s_barrier
.LBB0_47:
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB0_56
s_cmp_lt_i32 s9, 2
s_cbranch_scc1 .LBB0_55
v_not_b32_e32 v5, v2
v_lshl_add_u32 v3, v2, 2, 0
v_cmp_gt_u32_e32 vcc_lo, v2, v1
s_add_u32 s2, s0, 16
v_cmp_lt_u32_e64 s0, v2, v1
v_not_b32_e32 v2, v1
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v5, 2, v5
s_addc_u32 s3, s1, 0
s_lshl_b32 s5, s9, 1
s_mov_b32 s4, 0
s_add_i32 s1, s9, 1
s_add_i32 s5, s5, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_51
.p2align 6
.LBB0_50:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s4, s4, 2
s_add_i32 s1, s1, s5
s_cmp_lt_i32 s4, s8
s_cbranch_scc0 .LBB0_55
.LBB0_51:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_53
s_load_b32 s12, s[2:3], 0xc
s_waitcnt lgkmcnt(0)
s_lshr_b32 s13, s12, 16
s_and_b32 s12, s12, 0xffff
v_mad_u64_u32 v[6:7], null, s4, s13, v[1:2]
s_mul_i32 s12, s4, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b32 s12, s12, 2
v_mul_lo_u32 v6, v6, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 2, v6
v_add3_u32 v6, v3, s12, v6
ds_store_b32 v6, v4
.LBB0_53:
s_or_b32 exec_lo, exec_lo, s11
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_50
s_load_b32 s12, s[2:3], 0xc
s_waitcnt lgkmcnt(0)
s_lshr_b32 s13, s12, 16
s_and_b32 s12, s12, 0xffff
v_add_nc_u32_e32 v6, s13, v2
s_mul_i32 s13, s1, s12
s_lshl_b32 s12, s12, 2
s_lshl_b32 s13, s13, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_add_i32 s13, s13, 0
v_mul_lo_u32 v6, v6, s9
s_add_i32 s13, s13, s12
v_lshlrev_b32_e32 v6, 2, v6
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v6, s13, v5, v6
ds_store_b32 v6, v4
s_branch .LBB0_50
.LBB0_55:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_barrier
.LBB0_56:
s_and_not1_b32 vcc_lo, exec_lo, s10
buffer_gl0_inv
s_cbranch_vccnz .LBB0_61
v_and_b32_e32 v2, 0x3ff, v0
s_lshl_b32 s0, s9, 1
s_mov_b32 s1, 0
s_lshl_b32 s2, s9, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s9, v[1:2]
v_mad_u64_u32 v[4:5], null, v1, s9, v[2:3]
v_mad_u64_u32 v[0:1], null, s9, v3, v[2:3]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v3, v4, 2, 0
.p2align 6
.LBB0_58:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v1, v0
s_mov_b32 s3, s8
.LBB0_59:
ds_load_b32 v7, v4
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, 2, v1
v_add_nc_u32_e32 v4, 8, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
s_cmp_lg_u32 s3, 0
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[5:6], v7, off
s_cbranch_scc1 .LBB0_59
v_add_nc_u32_e32 v0, s0, v0
v_add_nc_u32_e32 v3, s2, v3
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, s8
s_cbranch_scc1 .LBB0_58
.LBB0_61:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27right_looking_launch_kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27right_looking_launch_kernelPfi, .Lfunc_end0-_Z27right_looking_launch_kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27right_looking_launch_kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z27right_looking_launch_kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
#define TILE_SIZE 2
__device__ void store_full(float*,float*,int);
__device__ void load_full(float*,float*,int);
__device__ void potrf_tile(float*,int,int);
__device__ void trsm_tile(float*,int,int,int);
__device__ void syrk_tile(float*,int,int,int,int);
__global__ void right_looking_launch_kernel(float*,int);
__device__ void store_zeros(float*,int);
__device__ void store_zeros_diagonal(float*,int,int);
__device__ void store_zeros_last(float*,int);
__device__ void store_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID + N*N*blockIdx.x] = read_data[ID];
}
}
__syncthreads();
}
__device__ void load_full(float* read_data,float* write_data,int N)
{
int i,j,ID;
for(i=0;i<N/TILE_SIZE;i++)
{
for(j=0;j<N/TILE_SIZE;j++)
{
ID = (i*TILE_SIZE + threadIdx.y)*N + j*TILE_SIZE + threadIdx.x;
write_data[ID] = read_data[ID + N*N*blockIdx.x];
}
}
__syncthreads();
}
__device__ void potrf_tile(float* t_A,int i,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int k=0;k<TILE_SIZE;k++)
{
if(t_x==t_y && t_x==k)
{
t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x] = sqrtf(t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x]);
}
__syncthreads();
if(t_x<t_y && t_x == k)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]/= t_A[i*TILE_SIZE*(1+N) + t_x*N + t_x];
}
__syncthreads();
if(k<t_y && k<t_x && t_x<=t_y)
{
t_A[i*TILE_SIZE*(1+N) + t_y*N + t_x]-= t_A[i*TILE_SIZE*(1+N) + t_x*N + k]*t_A[i*TILE_SIZE*(1+N) + t_y*N + k];
}
__syncthreads();
}
}
__device__ void trsm_tile(float *row_data,int i,int j,int N)
{
int t_x = threadIdx.x;
int t_y = threadIdx.y;
for(int s=0;s<TILE_SIZE;s++)
{
if(t_x==s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]/= row_data[i*TILE_SIZE*(1+N) + t_x*(1+N)];
}
__syncthreads();
if(t_x > s)
{
row_data[(t_y + j*TILE_SIZE)*N + t_x + i*TILE_SIZE]-= row_data[(t_x + i*TILE_SIZE)*N + s]*row_data[(t_y + j*TILE_SIZE)*N + s];
}
__syncthreads();
}
}
__device__ void syrk_tile(float* row_data,int i,int j,int k,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
float valueToSubtract = 0.0;
for(int r=0;r<TILE_SIZE;r++)
{
valueToSubtract+= row_data[(t_x + k*TILE_SIZE)*N + i*TILE_SIZE + r]*row_data[(t_y + j*TILE_SIZE)*N + i*TILE_SIZE + r];
}
row_data[(t_y + j*TILE_SIZE)*N + t_x + k*TILE_SIZE]-= valueToSubtract;
__syncthreads();
}
__device__ void store_zeros(float* A,int N)
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i,j;
for(i=0;i<N/TILE_SIZE-1;i++)
{
for(j=i+1;j<N/TILE_SIZE;j++)
A[j*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_diagonal(float* A,int N,int b) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
int i;
for(i=0;i<N/TILE_SIZE-b;i+=2)
{
if(t_x>t_y)
A[i*blockDim.x + t_x + (i*blockDim.y + t_y)*N] = 0.0;
if(t_x<t_y)
A[(i+1)*blockDim.x*(1+N) + (blockDim.x-t_x-1) + (blockDim.y-t_y-1)*N] = 0.0;
}
__syncthreads();
}
__device__ void store_zeros_last(float* A,int N) // Will only work if (N/TILE_SIZE) is even
{
int t_y = threadIdx.y;
int t_x = threadIdx.x;
if(t_x>t_y)
A[(N/TILE_SIZE-1)*blockDim.x*(1+N) + t_x + t_y*N] = 0.0;
__syncthreads();
}
__global__ void right_looking_launch_kernel(float* read_data,int N)
{
extern __shared__ float data[];
int i,j,k;
load_full(read_data,data,N);
for(i=0;i<N/TILE_SIZE;i++)
{
potrf_tile(data,i,N);
for(j=i+1;j<N/TILE_SIZE;j++)
{
trsm_tile(data,i,j,N);
for(k=i+1;k<=j;k++)
{
syrk_tile(data,i,j,k,N);
}
}
}
store_zeros(data,N);
if((N/TILE_SIZE)%2==0)
store_zeros_diagonal(data,N,0);
else
{
store_zeros_diagonal(data,N,1);
store_zeros_last(data,N);
}
store_full(data,read_data,N);
} | .text
.file "right_looking.hip"
.globl _Z42__device_stub__right_looking_launch_kernelPfi # -- Begin function _Z42__device_stub__right_looking_launch_kernelPfi
.p2align 4, 0x90
.type _Z42__device_stub__right_looking_launch_kernelPfi,@function
_Z42__device_stub__right_looking_launch_kernelPfi: # @_Z42__device_stub__right_looking_launch_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z27right_looking_launch_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z42__device_stub__right_looking_launch_kernelPfi, .Lfunc_end0-_Z42__device_stub__right_looking_launch_kernelPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27right_looking_launch_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27right_looking_launch_kernelPfi,@object # @_Z27right_looking_launch_kernelPfi
.section .rodata,"a",@progbits
.globl _Z27right_looking_launch_kernelPfi
.p2align 3, 0x0
_Z27right_looking_launch_kernelPfi:
.quad _Z42__device_stub__right_looking_launch_kernelPfi
.size _Z27right_looking_launch_kernelPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27right_looking_launch_kernelPfi"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__right_looking_launch_kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27right_looking_launch_kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015b61b_00000000-6_right_looking.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10store_fullPfS_i
.type _Z10store_fullPfS_i, @function
_Z10store_fullPfS_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10store_fullPfS_i, .-_Z10store_fullPfS_i
.globl _Z9load_fullPfS_i
.type _Z9load_fullPfS_i, @function
_Z9load_fullPfS_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z9load_fullPfS_i, .-_Z9load_fullPfS_i
.globl _Z10potrf_tilePfii
.type _Z10potrf_tilePfii, @function
_Z10potrf_tilePfii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10potrf_tilePfii, .-_Z10potrf_tilePfii
.globl _Z9trsm_tilePfiii
.type _Z9trsm_tilePfiii, @function
_Z9trsm_tilePfiii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z9trsm_tilePfiii, .-_Z9trsm_tilePfiii
.globl _Z9syrk_tilePfiiii
.type _Z9syrk_tilePfiiii, @function
_Z9syrk_tilePfiiii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z9syrk_tilePfiiii, .-_Z9syrk_tilePfiiii
.globl _Z11store_zerosPfi
.type _Z11store_zerosPfi, @function
_Z11store_zerosPfi:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z11store_zerosPfi, .-_Z11store_zerosPfi
.globl _Z20store_zeros_diagonalPfii
.type _Z20store_zeros_diagonalPfii, @function
_Z20store_zeros_diagonalPfii:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z20store_zeros_diagonalPfii, .-_Z20store_zeros_diagonalPfii
.globl _Z16store_zeros_lastPfi
.type _Z16store_zeros_lastPfi, @function
_Z16store_zeros_lastPfi:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z16store_zeros_lastPfi, .-_Z16store_zeros_lastPfi
.globl _Z48__device_stub__Z27right_looking_launch_kernelPfiPfi
.type _Z48__device_stub__Z27right_looking_launch_kernelPfiPfi, @function
_Z48__device_stub__Z27right_looking_launch_kernelPfiPfi:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z27right_looking_launch_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z48__device_stub__Z27right_looking_launch_kernelPfiPfi, .-_Z48__device_stub__Z27right_looking_launch_kernelPfiPfi
.globl _Z27right_looking_launch_kernelPfi
.type _Z27right_looking_launch_kernelPfi, @function
_Z27right_looking_launch_kernelPfi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z27right_looking_launch_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z27right_looking_launch_kernelPfi, .-_Z27right_looking_launch_kernelPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27right_looking_launch_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27right_looking_launch_kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "right_looking.hip"
.globl _Z42__device_stub__right_looking_launch_kernelPfi # -- Begin function _Z42__device_stub__right_looking_launch_kernelPfi
.p2align 4, 0x90
.type _Z42__device_stub__right_looking_launch_kernelPfi,@function
_Z42__device_stub__right_looking_launch_kernelPfi: # @_Z42__device_stub__right_looking_launch_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z27right_looking_launch_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z42__device_stub__right_looking_launch_kernelPfi, .Lfunc_end0-_Z42__device_stub__right_looking_launch_kernelPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27right_looking_launch_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27right_looking_launch_kernelPfi,@object # @_Z27right_looking_launch_kernelPfi
.section .rodata,"a",@progbits
.globl _Z27right_looking_launch_kernelPfi
.p2align 3, 0x0
_Z27right_looking_launch_kernelPfi:
.quad _Z42__device_stub__right_looking_launch_kernelPfi
.size _Z27right_looking_launch_kernelPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27right_looking_launch_kernelPfi"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__right_looking_launch_kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27right_looking_launch_kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 256
__global__ void bitreverse(unsigned int *data){
unsigned int *idata = data;
unsigned int x = idata[threadIdx.x];
x = ((0xf0f0f0f0 & x) >> 4) | ((0x0f0f0f0f & x) << 4);
x = ((0xcccccccc & x) >> 2) | ((0x33333333 & x) << 2);
x = ((0xaaaaaaaa & x) >> 1) | ((0x55555555 & x) << 1);
idata[threadIdx.x] = x;
}
int main(void){
unsigned int *d = NULL; int i;
unsigned int idata[N], odata[N];
for (i = 0; i < N; i++)
idata[i] = (unsigned int)i;
cudaMalloc((void**)&d, sizeof(int)*N);
cudaMemcpy(d, idata, sizeof(int)*N,cudaMemcpyHostToDevice);
bitreverse<<<1, N>>>(d);
cudaMemcpy(odata, d, sizeof(int)*N,cudaMemcpyHostToDevice);
for (i = 0; i < N; i++)
printf("%u -> %u\n", idata[i], odata[i]);
cudaFree((void*)d);
return 0;
} | code for sm_80
Function : _Z10bitreversePj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IMAD.SHL.U32 R4, R0.reuse, 0x10, RZ ; /* 0x0000001000047824 */
/* 0x044fe200078e00ff */
/*0070*/ LOP3.LUT R0, R0, 0xf0f0f0f0, RZ, 0xc0, !PT ; /* 0xf0f0f0f000007812 */
/* 0x000fc800078ec0ff */
/*0080*/ LOP3.LUT R5, R4, 0xf0f0f0f0, RZ, 0xc0, !PT ; /* 0xf0f0f0f004057812 */
/* 0x000fc800078ec0ff */
/*0090*/ LEA.HI R0, R0, R5, RZ, 0x1c ; /* 0x0000000500007211 */
/* 0x000fca00078fe0ff */
/*00a0*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*00b0*/ LOP3.LUT R0, R0, 0xcccccccc, RZ, 0xc0, !PT ; /* 0xcccccccc00007812 */
/* 0x000fc800078ec0ff */
/*00c0*/ LOP3.LUT R5, R4, 0xcccccccc, RZ, 0xc0, !PT ; /* 0xcccccccc04057812 */
/* 0x000fc800078ec0ff */
/*00d0*/ LEA.HI R0, R0, R5, RZ, 0x1e ; /* 0x0000000500007211 */
/* 0x000fca00078ff0ff */
/*00e0*/ IMAD.SHL.U32 R4, R0.reuse, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x040fe200078e00ff */
/*00f0*/ LOP3.LUT R0, R0, 0xaaaaaaaa, RZ, 0xc0, !PT ; /* 0xaaaaaaaa00007812 */
/* 0x000fc800078ec0ff */
/*0100*/ LOP3.LUT R5, R4, 0xaaaaaaaa, RZ, 0xc0, !PT ; /* 0xaaaaaaaa04057812 */
/* 0x000fc800078ec0ff */
/*0110*/ LEA.HI R5, R0, R5, RZ, 0x1f ; /* 0x0000000500057211 */
/* 0x000fca00078ff8ff */
/*0120*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 256
__global__ void bitreverse(unsigned int *data){
unsigned int *idata = data;
unsigned int x = idata[threadIdx.x];
x = ((0xf0f0f0f0 & x) >> 4) | ((0x0f0f0f0f & x) << 4);
x = ((0xcccccccc & x) >> 2) | ((0x33333333 & x) << 2);
x = ((0xaaaaaaaa & x) >> 1) | ((0x55555555 & x) << 1);
idata[threadIdx.x] = x;
}
int main(void){
unsigned int *d = NULL; int i;
unsigned int idata[N], odata[N];
for (i = 0; i < N; i++)
idata[i] = (unsigned int)i;
cudaMalloc((void**)&d, sizeof(int)*N);
cudaMemcpy(d, idata, sizeof(int)*N,cudaMemcpyHostToDevice);
bitreverse<<<1, N>>>(d);
cudaMemcpy(odata, d, sizeof(int)*N,cudaMemcpyHostToDevice);
for (i = 0; i < N; i++)
printf("%u -> %u\n", idata[i], odata[i]);
cudaFree((void*)d);
return 0;
} | .file "tmpxft_000bcc46_00000000-6_bitreverse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10bitreversePjPj
.type _Z30__device_stub__Z10bitreversePjPj, @function
_Z30__device_stub__Z10bitreversePjPj:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10bitreversePj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10bitreversePjPj, .-_Z30__device_stub__Z10bitreversePjPj
.globl _Z10bitreversePj
.type _Z10bitreversePj, @function
_Z10bitreversePj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10bitreversePjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10bitreversePj, .-_Z10bitreversePj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%u -> %u\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $2104, %rsp
.cfi_def_cfa_offset 2128
movq %fs:40, %rax
movq %rax, 2088(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
.L12:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L12
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 1056(%rsp), %rdi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 1056(%rsp,%rbx), %ecx
movl 32(%rsp,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $1024, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 2088(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $2104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z30__device_stub__Z10bitreversePjPj
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10bitreversePj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bitreversePj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 256
__global__ void bitreverse(unsigned int *data){
unsigned int *idata = data;
unsigned int x = idata[threadIdx.x];
x = ((0xf0f0f0f0 & x) >> 4) | ((0x0f0f0f0f & x) << 4);
x = ((0xcccccccc & x) >> 2) | ((0x33333333 & x) << 2);
x = ((0xaaaaaaaa & x) >> 1) | ((0x55555555 & x) << 1);
idata[threadIdx.x] = x;
}
int main(void){
unsigned int *d = NULL; int i;
unsigned int idata[N], odata[N];
for (i = 0; i < N; i++)
idata[i] = (unsigned int)i;
cudaMalloc((void**)&d, sizeof(int)*N);
cudaMemcpy(d, idata, sizeof(int)*N,cudaMemcpyHostToDevice);
bitreverse<<<1, N>>>(d);
cudaMemcpy(odata, d, sizeof(int)*N,cudaMemcpyHostToDevice);
for (i = 0; i < N; i++)
printf("%u -> %u\n", idata[i], odata[i]);
cudaFree((void*)d);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 256
__global__ void bitreverse(unsigned int *data){
unsigned int *idata = data;
unsigned int x = idata[threadIdx.x];
x = ((0xf0f0f0f0 & x) >> 4) | ((0x0f0f0f0f & x) << 4);
x = ((0xcccccccc & x) >> 2) | ((0x33333333 & x) << 2);
x = ((0xaaaaaaaa & x) >> 1) | ((0x55555555 & x) << 1);
idata[threadIdx.x] = x;
}
int main(void){
unsigned int *d = NULL; int i;
unsigned int idata[N], odata[N];
for (i = 0; i < N; i++)
idata[i] = (unsigned int)i;
hipMalloc((void**)&d, sizeof(int)*N);
hipMemcpy(d, idata, sizeof(int)*N,hipMemcpyHostToDevice);
bitreverse<<<1, N>>>(d);
hipMemcpy(odata, d, sizeof(int)*N,hipMemcpyHostToDevice);
for (i = 0; i < N; i++)
printf("%u -> %u\n", idata[i], odata[i]);
hipFree((void*)d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 256
__global__ void bitreverse(unsigned int *data){
unsigned int *idata = data;
unsigned int x = idata[threadIdx.x];
x = ((0xf0f0f0f0 & x) >> 4) | ((0x0f0f0f0f & x) << 4);
x = ((0xcccccccc & x) >> 2) | ((0x33333333 & x) << 2);
x = ((0xaaaaaaaa & x) >> 1) | ((0x55555555 & x) << 1);
idata[threadIdx.x] = x;
}
int main(void){
unsigned int *d = NULL; int i;
unsigned int idata[N], odata[N];
for (i = 0; i < N; i++)
idata[i] = (unsigned int)i;
hipMalloc((void**)&d, sizeof(int)*N);
hipMemcpy(d, idata, sizeof(int)*N,hipMemcpyHostToDevice);
bitreverse<<<1, N>>>(d);
hipMemcpy(odata, d, sizeof(int)*N,hipMemcpyHostToDevice);
for (i = 0; i < N; i++)
printf("%u -> %u\n", idata[i], odata[i]);
hipFree((void*)d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bitreversePj
.globl _Z10bitreversePj
.p2align 8
.type _Z10bitreversePj,@function
_Z10bitreversePj:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_lshrrev_b32_e32 v2, 4, v1
v_lshlrev_b32_e32 v1, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0xf0f0f0f, v2, v1
v_lshrrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0x33333333, v2, v1
v_lshrrev_b32_e32 v2, 1, v1
v_lshlrev_b32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_bfi_b32 v1, 0x55555555, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bitreversePj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bitreversePj, .Lfunc_end0-_Z10bitreversePj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bitreversePj
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z10bitreversePj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 256
__global__ void bitreverse(unsigned int *data){
unsigned int *idata = data;
unsigned int x = idata[threadIdx.x];
x = ((0xf0f0f0f0 & x) >> 4) | ((0x0f0f0f0f & x) << 4);
x = ((0xcccccccc & x) >> 2) | ((0x33333333 & x) << 2);
x = ((0xaaaaaaaa & x) >> 1) | ((0x55555555 & x) << 1);
idata[threadIdx.x] = x;
}
int main(void){
unsigned int *d = NULL; int i;
unsigned int idata[N], odata[N];
for (i = 0; i < N; i++)
idata[i] = (unsigned int)i;
hipMalloc((void**)&d, sizeof(int)*N);
hipMemcpy(d, idata, sizeof(int)*N,hipMemcpyHostToDevice);
bitreverse<<<1, N>>>(d);
hipMemcpy(odata, d, sizeof(int)*N,hipMemcpyHostToDevice);
for (i = 0; i < N; i++)
printf("%u -> %u\n", idata[i], odata[i]);
hipFree((void*)d);
return 0;
} | .text
.file "bitreverse.hip"
.globl _Z25__device_stub__bitreversePj # -- Begin function _Z25__device_stub__bitreversePj
.p2align 4, 0x90
.type _Z25__device_stub__bitreversePj,@function
_Z25__device_stub__bitreversePj: # @_Z25__device_stub__bitreversePj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10bitreversePj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__bitreversePj, .Lfunc_end0-_Z25__device_stub__bitreversePj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2112, %rsp # imm = 0x840
.cfi_def_cfa_offset 2128
.cfi_offset %rbx, -16
movq $0, 8(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 1088(%rsp,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 1088(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10bitreversePj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 1088(%rsp,%rbx,4), %esi
movl 64(%rsp,%rbx,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $2112, %rsp # imm = 0x840
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bitreversePj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bitreversePj,@object # @_Z10bitreversePj
.section .rodata,"a",@progbits
.globl _Z10bitreversePj
.p2align 3, 0x0
_Z10bitreversePj:
.quad _Z25__device_stub__bitreversePj
.size _Z10bitreversePj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%u -> %u\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bitreversePj"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bitreversePj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bitreversePj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10bitreversePj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IMAD.SHL.U32 R4, R0.reuse, 0x10, RZ ; /* 0x0000001000047824 */
/* 0x044fe200078e00ff */
/*0070*/ LOP3.LUT R0, R0, 0xf0f0f0f0, RZ, 0xc0, !PT ; /* 0xf0f0f0f000007812 */
/* 0x000fc800078ec0ff */
/*0080*/ LOP3.LUT R5, R4, 0xf0f0f0f0, RZ, 0xc0, !PT ; /* 0xf0f0f0f004057812 */
/* 0x000fc800078ec0ff */
/*0090*/ LEA.HI R0, R0, R5, RZ, 0x1c ; /* 0x0000000500007211 */
/* 0x000fca00078fe0ff */
/*00a0*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*00b0*/ LOP3.LUT R0, R0, 0xcccccccc, RZ, 0xc0, !PT ; /* 0xcccccccc00007812 */
/* 0x000fc800078ec0ff */
/*00c0*/ LOP3.LUT R5, R4, 0xcccccccc, RZ, 0xc0, !PT ; /* 0xcccccccc04057812 */
/* 0x000fc800078ec0ff */
/*00d0*/ LEA.HI R0, R0, R5, RZ, 0x1e ; /* 0x0000000500007211 */
/* 0x000fca00078ff0ff */
/*00e0*/ IMAD.SHL.U32 R4, R0.reuse, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x040fe200078e00ff */
/*00f0*/ LOP3.LUT R0, R0, 0xaaaaaaaa, RZ, 0xc0, !PT ; /* 0xaaaaaaaa00007812 */
/* 0x000fc800078ec0ff */
/*0100*/ LOP3.LUT R5, R4, 0xaaaaaaaa, RZ, 0xc0, !PT ; /* 0xaaaaaaaa04057812 */
/* 0x000fc800078ec0ff */
/*0110*/ LEA.HI R5, R0, R5, RZ, 0x1f ; /* 0x0000000500057211 */
/* 0x000fca00078ff8ff */
/*0120*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bitreversePj
.globl _Z10bitreversePj
.p2align 8
.type _Z10bitreversePj,@function
_Z10bitreversePj:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_lshrrev_b32_e32 v2, 4, v1
v_lshlrev_b32_e32 v1, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0xf0f0f0f, v2, v1
v_lshrrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0x33333333, v2, v1
v_lshrrev_b32_e32 v2, 1, v1
v_lshlrev_b32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_bfi_b32 v1, 0x55555555, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bitreversePj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bitreversePj, .Lfunc_end0-_Z10bitreversePj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bitreversePj
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z10bitreversePj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bcc46_00000000-6_bitreverse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10bitreversePjPj
.type _Z30__device_stub__Z10bitreversePjPj, @function
_Z30__device_stub__Z10bitreversePjPj:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10bitreversePj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10bitreversePjPj, .-_Z30__device_stub__Z10bitreversePjPj
.globl _Z10bitreversePj
.type _Z10bitreversePj, @function
_Z10bitreversePj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10bitreversePjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10bitreversePj, .-_Z10bitreversePj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%u -> %u\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $2104, %rsp
.cfi_def_cfa_offset 2128
movq %fs:40, %rax
movq %rax, 2088(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
.L12:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L12
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 1056(%rsp), %rdi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 1056(%rsp,%rbx), %ecx
movl 32(%rsp,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $1024, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 2088(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $2104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z30__device_stub__Z10bitreversePjPj
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10bitreversePj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bitreversePj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitreverse.hip"
.globl _Z25__device_stub__bitreversePj # -- Begin function _Z25__device_stub__bitreversePj
.p2align 4, 0x90
.type _Z25__device_stub__bitreversePj,@function
_Z25__device_stub__bitreversePj: # @_Z25__device_stub__bitreversePj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10bitreversePj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__bitreversePj, .Lfunc_end0-_Z25__device_stub__bitreversePj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2112, %rsp # imm = 0x840
.cfi_def_cfa_offset 2128
.cfi_offset %rbx, -16
movq $0, 8(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 1088(%rsp,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 1088(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10bitreversePj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 1088(%rsp,%rbx,4), %esi
movl 64(%rsp,%rbx,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $2112, %rsp # imm = 0x840
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bitreversePj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bitreversePj,@object # @_Z10bitreversePj
.section .rodata,"a",@progbits
.globl _Z10bitreversePj
.p2align 3, 0x0
_Z10bitreversePj:
.quad _Z25__device_stub__bitreversePj
.size _Z10bitreversePj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%u -> %u\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bitreversePj"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bitreversePj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bitreversePj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <device_launch_parameters.h>
#include <cuda_runtime_api.h>
#include <cstdio>
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__device__ int mod(int a, int b) {
return a >= 0 ? a%b : ( b - abs ( a%b ) ) % b;
}
__global__ void update(int *A, int *B, int height, int width) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < height*width) {
int aliveNeighbours = 0;
const int h = index / width;
const int w = index % width;
/*The neighbours of the cell are checked*/
for (int i = -1; i < 2; ++i) {
for (int j = -1; j < 2; ++j) {
aliveNeighbours += ( (i | j) && A[mod(h+i,height)*width + mod(w+j,width)]);
}
}
B[index] = (A[index] == 0 && (aliveNeighbours == 3 || aliveNeighbours == 6))
|| A[index] == 1 && (aliveNeighbours == 2 || aliveNeighbours == 3);
}
}
void setUp(int height, int width) {
// Allocate memory for each vector on GPU
cudaMalloc((void **) &d_a, height*width*sizeof(int));
cudaMalloc((void **) &d_b, height*width*sizeof(int));
}
void destroy() {
// Release device memory
cudaFree(d_a);
cudaFree(d_b);
}
void updateCuda(int *A, int *B, int height, int width) {
// Size, in bytes, of each vector
size_t bytes = height*width*sizeof(int);
// Copy host vectors to device
cudaMemcpy(d_a, A, bytes, cudaMemcpyHostToDevice);
int blockSize, gridSize, n;
// // Tamaño de la matriz.
// n = height*width;
//
// // Tamaño del bloque. Elegir entre 32 y 31.
// //blockSize = 32;
// blockSize = 32;
//
// // Number of thread blocks in grid
// gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
update<<< width*height, 1 >>>(d_a, d_b, height, width);
// Copy array back to host
cudaMemcpy( B, d_b, bytes, cudaMemcpyDeviceToHost );
} | .file "tmpxft_000207cd_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3modii
.type _Z3modii, @function
_Z3modii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z3modii, .-_Z3modii
.globl _Z5setUpii
.type _Z5setUpii, @function
_Z5setUpii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
imull %esi, %edi
movslq %edi, %rbx
salq $2, %rbx
movq %rbx, %rsi
leaq d_a(%rip), %rdi
call cudaMalloc@PLT
movq %rbx, %rsi
leaq d_b(%rip), %rdi
call cudaMalloc@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5setUpii, .-_Z5setUpii
.globl _Z7destroyv
.type _Z7destroyv, @function
_Z7destroyv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq d_a(%rip), %rdi
call cudaFree@PLT
movq d_b(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7destroyv, .-_Z7destroyv
.globl _Z29__device_stub__Z6updatePiS_iiPiS_ii
.type _Z29__device_stub__Z6updatePiS_iiPiS_ii, @function
_Z29__device_stub__Z6updatePiS_iiPiS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6updatePiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z6updatePiS_iiPiS_ii, .-_Z29__device_stub__Z6updatePiS_iiPiS_ii
.globl _Z6updatePiS_ii
.type _Z6updatePiS_ii, @function
_Z6updatePiS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6updatePiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z6updatePiS_ii, .-_Z6updatePiS_ii
.globl _Z10updateCudaPiS_ii
.type _Z10updateCudaPiS_ii, @function
_Z10updateCudaPiS_ii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r13
movl %edx, %ebp
movl %ecx, %r12d
movl %edx, %r14d
imull %ecx, %r14d
movslq %r14d, %rbx
salq $2, %rbx
movl $1, %ecx
movq %rbx, %rdx
movq %rdi, %rsi
movq d_a(%rip), %rdi
call cudaMemcpy@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl %r14d, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L18:
movl $2, %ecx
movq %rbx, %rdx
movq d_b(%rip), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %r12d, %ecx
movl %ebp, %edx
movq d_b(%rip), %rsi
movq d_a(%rip), %rdi
call _Z29__device_stub__Z6updatePiS_iiPiS_ii
jmp .L18
.cfi_endproc
.LFE2060:
.size _Z10updateCudaPiS_ii, .-_Z10updateCudaPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6updatePiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_b
.bss
.align 8
.type d_b, @object
.size d_b, 8
d_b:
.zero 8
.globl d_a
.align 8
.type d_a, @object
.size d_a, 8
d_a:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <device_launch_parameters.h>
#include <cuda_runtime_api.h>
#include <cstdio>
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__device__ int mod(int a, int b) {
return a >= 0 ? a%b : ( b - abs ( a%b ) ) % b;
}
__global__ void update(int *A, int *B, int height, int width) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < height*width) {
int aliveNeighbours = 0;
const int h = index / width;
const int w = index % width;
/*The neighbours of the cell are checked*/
for (int i = -1; i < 2; ++i) {
for (int j = -1; j < 2; ++j) {
aliveNeighbours += ( (i | j) && A[mod(h+i,height)*width + mod(w+j,width)]);
}
}
B[index] = (A[index] == 0 && (aliveNeighbours == 3 || aliveNeighbours == 6))
|| A[index] == 1 && (aliveNeighbours == 2 || aliveNeighbours == 3);
}
}
void setUp(int height, int width) {
// Allocate memory for each vector on GPU
cudaMalloc((void **) &d_a, height*width*sizeof(int));
cudaMalloc((void **) &d_b, height*width*sizeof(int));
}
void destroy() {
// Release device memory
cudaFree(d_a);
cudaFree(d_b);
}
void updateCuda(int *A, int *B, int height, int width) {
// Size, in bytes, of each vector
size_t bytes = height*width*sizeof(int);
// Copy host vectors to device
cudaMemcpy(d_a, A, bytes, cudaMemcpyHostToDevice);
int blockSize, gridSize, n;
// // Tamaño de la matriz.
// n = height*width;
//
// // Tamaño del bloque. Elegir entre 32 y 31.
// //blockSize = 32;
// blockSize = 32;
//
// // Number of thread blocks in grid
// gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
update<<< width*height, 1 >>>(d_a, d_b, height, width);
// Copy array back to host
cudaMemcpy( B, d_b, bytes, cudaMemcpyDeviceToHost );
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cstdio>
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__device__ int mod(int a, int b) {
return a >= 0 ? a%b : ( b - abs ( a%b ) ) % b;
}
__global__ void update(int *A, int *B, int height, int width) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < height*width) {
int aliveNeighbours = 0;
const int h = index / width;
const int w = index % width;
/*The neighbours of the cell are checked*/
for (int i = -1; i < 2; ++i) {
for (int j = -1; j < 2; ++j) {
aliveNeighbours += ( (i | j) && A[mod(h+i,height)*width + mod(w+j,width)]);
}
}
B[index] = (A[index] == 0 && (aliveNeighbours == 3 || aliveNeighbours == 6))
|| A[index] == 1 && (aliveNeighbours == 2 || aliveNeighbours == 3);
}
}
void setUp(int height, int width) {
// Allocate memory for each vector on GPU
hipMalloc((void **) &d_a, height*width*sizeof(int));
hipMalloc((void **) &d_b, height*width*sizeof(int));
}
void destroy() {
// Release device memory
hipFree(d_a);
hipFree(d_b);
}
void updateCuda(int *A, int *B, int height, int width) {
// Size, in bytes, of each vector
size_t bytes = height*width*sizeof(int);
// Copy host vectors to device
hipMemcpy(d_a, A, bytes, hipMemcpyHostToDevice);
int blockSize, gridSize, n;
// // Tamaño de la matriz.
// n = height*width;
//
// // Tamaño del bloque. Elegir entre 32 y 31.
// //blockSize = 32;
// blockSize = 32;
//
// // Number of thread blocks in grid
// gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
update<<< width*height, 1 >>>(d_a, d_b, height, width);
// Copy array back to host
hipMemcpy( B, d_b, bytes, hipMemcpyDeviceToHost );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cstdio>
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__device__ int mod(int a, int b) {
return a >= 0 ? a%b : ( b - abs ( a%b ) ) % b;
}
__global__ void update(int *A, int *B, int height, int width) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < height*width) {
int aliveNeighbours = 0;
const int h = index / width;
const int w = index % width;
/*The neighbours of the cell are checked*/
for (int i = -1; i < 2; ++i) {
for (int j = -1; j < 2; ++j) {
aliveNeighbours += ( (i | j) && A[mod(h+i,height)*width + mod(w+j,width)]);
}
}
B[index] = (A[index] == 0 && (aliveNeighbours == 3 || aliveNeighbours == 6))
|| A[index] == 1 && (aliveNeighbours == 2 || aliveNeighbours == 3);
}
}
void setUp(int height, int width) {
// Allocate memory for each vector on GPU
hipMalloc((void **) &d_a, height*width*sizeof(int));
hipMalloc((void **) &d_b, height*width*sizeof(int));
}
void destroy() {
// Release device memory
hipFree(d_a);
hipFree(d_b);
}
void updateCuda(int *A, int *B, int height, int width) {
// Size, in bytes, of each vector
size_t bytes = height*width*sizeof(int);
// Copy host vectors to device
hipMemcpy(d_a, A, bytes, hipMemcpyHostToDevice);
int blockSize, gridSize, n;
// // Tamaño de la matriz.
// n = height*width;
//
// // Tamaño del bloque. Elegir entre 32 y 31.
// //blockSize = 32;
// blockSize = 32;
//
// // Number of thread blocks in grid
// gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
update<<< width*height, 1 >>>(d_a, d_b, height, width);
// Copy array back to host
hipMemcpy( B, d_b, bytes, hipMemcpyDeviceToHost );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6updatePiS_ii
.globl _Z6updatePiS_ii
.p2align 8
.type _Z6updatePiS_ii,@function
_Z6updatePiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_27
s_ashr_i32 s2, s5, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s3, s5, s2
s_mov_b32 s9, -1
s_xor_b32 s3, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s6, 0, s3
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s6, v0
s_ashr_i32 s6, s4, 31
s_add_i32 s7, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_xor_b32 s8, s7, s6
s_load_b64 s[6:7], s[0:1], 0x0
v_cvt_f32_u32_e32 v6, s8
v_mul_hi_u32 v2, v0, v2
s_sub_i32 s2, 0, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v6, v6
v_add_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x4f7ffffe, v6
v_mul_lo_u32 v5, v0, s3
v_sub_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s3, v4
v_cmp_le_u32_e32 vcc_lo, s3, v4
v_dual_cndmask_b32 v4, v4, v7 :: v_dual_add_nc_u32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v0
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_cvt_u32_f32_e32 v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
v_mul_lo_u32 v4, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v0, v3
v_mov_b32_e32 v0, 0
v_mul_hi_u32 v7, v5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, v3, s5
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v1, v6
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 2
s_cbranch_scc1 .LBB0_12
.LBB0_3:
v_add_nc_u32_e32 v6, s9, v3
s_mov_b32 s10, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_cmp_gt_i32_e32 vcc_lo, 0, v6
v_add_nc_u32_e32 v8, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v8, v8, v7
v_mul_hi_u32 v9, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v9, s8
v_sub_nc_u32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1)
v_subrev_nc_u32_e32 v9, s8, v8
s_branch .LBB0_6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s11
v_ashrrev_i32_e32 v12, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v11
v_add_nc_u32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, v11, v13
v_xor_b32_e32 v14, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v15, v11, v13
v_mad_u64_u32 v[10:11], null, v14, v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, v15, v2
v_mul_lo_u32 v11, v11, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, v10, s3
v_sub_nc_u32_e32 v11, v14, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v15, v10
v_subrev_nc_u32_e32 v14, s8, v11
v_cmp_le_u32_e64 s2, s8, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v15, s3, v10
v_cndmask_b32_e64 v11, v11, v14, s2
v_cmp_le_u32_e64 s2, s3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v14, s8, v11
v_cndmask_b32_e64 v10, v10, v15, s2
v_cmp_le_u32_e64 s2, s8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v15, s3, v10
v_cndmask_b32_e64 v11, v11, v14, s2
v_cmp_le_u32_e64 s2, s3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v11, v11, v12
v_cndmask_b32_e64 v10, v10, v15, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v14, v11, v12
v_xor_b32_e32 v10, v10, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v10, v13
v_mad_u64_u32 v[11:12], null, v14, s5, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[10:11], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s2, s6, v10
v_add_co_ci_u32_e64 v11, s2, s7, v11, s2
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s2, 0, v10
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v10, 0, 1, s2
s_add_i32 s10, s10, 1
s_cmp_eq_u32 s10, 2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v10
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_or_b32 s2, s10, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_11
v_mov_b32_e32 v10, v6
s_and_saveexec_b32 s11, vcc_lo
v_cmp_le_u32_e64 s2, s8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, v8, v9, s2
v_subrev_nc_u32_e32 v11, s8, v10
v_cmp_le_u32_e64 s2, s8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, v10, v11, s2
v_xor_b32_e32 v10, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v10, v7
v_sub_nc_u32_e32 v11, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v10, v10, v11
v_sub_nc_u32_e32 v10, s4, v10
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v11, s10, v4
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0, v11
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v11, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v12, v4, s10, v11
v_xor_b32_e32 v12, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v13, v12, v2
v_mul_lo_u32 v13, v13, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v12, v12, v13
v_subrev_nc_u32_e32 v13, s3, v12
v_cmp_le_u32_e64 s2, s3, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v12, v12, v13, s2
v_subrev_nc_u32_e32 v13, s3, v12
v_cmp_le_u32_e64 s2, s3, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v12, v12, v13, s2
v_xor_b32_e32 v12, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v12, v11
v_sub_nc_u32_e32 v12, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v11, v11, v12
v_sub_nc_u32_e32 v11, s5, v11
s_branch .LBB0_4
.LBB0_11:
s_mov_b32 s2, 0
s_branch .LBB0_5
.LBB0_12:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v4, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v4
s_xor_b32 s3, exec_lo, s3
v_cmp_eq_u32_e32 vcc_lo, 1, v4
s_mov_b32 s4, 0
s_and_b32 s2, vcc_lo, exec_lo
s_or_saveexec_b32 s3, s3
v_mov_b32_e32 v3, s4
s_xor_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_24
v_mov_b32_e32 v3, 0
s_mov_b32 s5, s2
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_23
v_mov_b32_e32 v3, 0
s_mov_b32 s5, 0
s_mov_b32 s6, exec_lo
v_cmpx_lt_i32_e32 5, v0
s_xor_b32 s6, exec_lo, s6
v_cmp_ne_u32_e32 vcc_lo, 6, v0
v_mov_b32_e32 v3, 1
s_and_b32 s5, vcc_lo, exec_lo
s_and_not1_saveexec_b32 s6, s6
v_cmp_ne_u32_e32 vcc_lo, 3, v0
v_mov_b32_e32 v3, 1
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_or_b32 exec_lo, exec_lo, s6
s_mov_b32 s6, s2
s_and_saveexec_b32 s7, s5
v_cmp_eq_u32_e32 vcc_lo, 1, v4
v_mov_b32_e32 v3, 0
s_and_not1_b32 s5, s2, exec_lo
s_and_b32 s6, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s5, s6
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s5, s2, exec_lo
s_and_b32 s6, s6, exec_lo
s_or_b32 s5, s5, s6
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s4, s5, exec_lo
s_or_b32 s2, s2, s4
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
v_and_b32_e32 v0, -2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 2, v0
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_27:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updatePiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6updatePiS_ii, .Lfunc_end0-_Z6updatePiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updatePiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6updatePiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cstdio>
// Device input vectors
int *d_a;
//Device output vector
int *d_b;
__device__ int mod(int a, int b) {
return a >= 0 ? a%b : ( b - abs ( a%b ) ) % b;
}
__global__ void update(int *A, int *B, int height, int width) {
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < height*width) {
int aliveNeighbours = 0;
const int h = index / width;
const int w = index % width;
/*The neighbours of the cell are checked*/
for (int i = -1; i < 2; ++i) {
for (int j = -1; j < 2; ++j) {
aliveNeighbours += ( (i | j) && A[mod(h+i,height)*width + mod(w+j,width)]);
}
}
B[index] = (A[index] == 0 && (aliveNeighbours == 3 || aliveNeighbours == 6))
|| A[index] == 1 && (aliveNeighbours == 2 || aliveNeighbours == 3);
}
}
void setUp(int height, int width) {
// Allocate memory for each vector on GPU
hipMalloc((void **) &d_a, height*width*sizeof(int));
hipMalloc((void **) &d_b, height*width*sizeof(int));
}
void destroy() {
// Release device memory
hipFree(d_a);
hipFree(d_b);
}
void updateCuda(int *A, int *B, int height, int width) {
// Size, in bytes, of each vector
size_t bytes = height*width*sizeof(int);
// Copy host vectors to device
hipMemcpy(d_a, A, bytes, hipMemcpyHostToDevice);
int blockSize, gridSize, n;
// // Tamaño de la matriz.
// n = height*width;
//
// // Tamaño del bloque. Elegir entre 32 y 31.
// //blockSize = 32;
// blockSize = 32;
//
// // Number of thread blocks in grid
// gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
update<<< width*height, 1 >>>(d_a, d_b, height, width);
// Copy array back to host
hipMemcpy( B, d_b, bytes, hipMemcpyDeviceToHost );
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__updatePiS_ii # -- Begin function _Z21__device_stub__updatePiS_ii
.p2align 4, 0x90
.type _Z21__device_stub__updatePiS_ii,@function
_Z21__device_stub__updatePiS_ii: # @_Z21__device_stub__updatePiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__updatePiS_ii, .Lfunc_end0-_Z21__device_stub__updatePiS_ii
.cfi_endproc
# -- End function
.globl _Z5setUpii # -- Begin function _Z5setUpii
.p2align 4, 0x90
.type _Z5setUpii,@function
_Z5setUpii: # @_Z5setUpii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
imull %esi, %edi
movslq %edi, %rbx
shlq $2, %rbx
movl $d_a, %edi
movq %rbx, %rsi
callq hipMalloc
movl $d_b, %edi
movq %rbx, %rsi
popq %rbx
.cfi_def_cfa_offset 8
jmp hipMalloc # TAILCALL
.Lfunc_end1:
.size _Z5setUpii, .Lfunc_end1-_Z5setUpii
.cfi_endproc
# -- End function
.globl _Z7destroyv # -- Begin function _Z7destroyv
.p2align 4, 0x90
.type _Z7destroyv,@function
_Z7destroyv: # @_Z7destroyv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq d_a(%rip), %rdi
callq hipFree
movq d_b(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end2:
.size _Z7destroyv, .Lfunc_end2-_Z7destroyv
.cfi_endproc
# -- End function
.globl _Z10updateCudaPiS_ii # -- Begin function _Z10updateCudaPiS_ii
.p2align 4, 0x90
.type _Z10updateCudaPiS_ii,@function
_Z10updateCudaPiS_ii: # @_Z10updateCudaPiS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %rsi
movl %ecx, %r12d
imull %edx, %r12d
movslq %r12d, %r14
shlq $2, %r14
movq d_a(%rip), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $1, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq d_a(%rip), %rax
movq d_b(%rip), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq d_b(%rip), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10updateCudaPiS_ii, .Lfunc_end3-_Z10updateCudaPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_a,@object # @d_a
.bss
.globl d_a
.p2align 3, 0x0
d_a:
.quad 0
.size d_a, 8
.type d_b,@object # @d_b
.globl d_b
.p2align 3, 0x0
d_b:
.quad 0
.size d_b, 8
.type _Z6updatePiS_ii,@object # @_Z6updatePiS_ii
.section .rodata,"a",@progbits
.globl _Z6updatePiS_ii
.p2align 3, 0x0
_Z6updatePiS_ii:
.quad _Z21__device_stub__updatePiS_ii
.size _Z6updatePiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6updatePiS_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__updatePiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_a
.addrsig_sym d_b
.addrsig_sym _Z6updatePiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000207cd_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3modii
.type _Z3modii, @function
_Z3modii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z3modii, .-_Z3modii
.globl _Z5setUpii
.type _Z5setUpii, @function
_Z5setUpii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
imull %esi, %edi
movslq %edi, %rbx
salq $2, %rbx
movq %rbx, %rsi
leaq d_a(%rip), %rdi
call cudaMalloc@PLT
movq %rbx, %rsi
leaq d_b(%rip), %rdi
call cudaMalloc@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5setUpii, .-_Z5setUpii
.globl _Z7destroyv
.type _Z7destroyv, @function
_Z7destroyv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq d_a(%rip), %rdi
call cudaFree@PLT
movq d_b(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7destroyv, .-_Z7destroyv
.globl _Z29__device_stub__Z6updatePiS_iiPiS_ii
.type _Z29__device_stub__Z6updatePiS_iiPiS_ii, @function
_Z29__device_stub__Z6updatePiS_iiPiS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6updatePiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z6updatePiS_iiPiS_ii, .-_Z29__device_stub__Z6updatePiS_iiPiS_ii
.globl _Z6updatePiS_ii
.type _Z6updatePiS_ii, @function
_Z6updatePiS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6updatePiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z6updatePiS_ii, .-_Z6updatePiS_ii
.globl _Z10updateCudaPiS_ii
.type _Z10updateCudaPiS_ii, @function
_Z10updateCudaPiS_ii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r13
movl %edx, %ebp
movl %ecx, %r12d
movl %edx, %r14d
imull %ecx, %r14d
movslq %r14d, %rbx
salq $2, %rbx
movl $1, %ecx
movq %rbx, %rdx
movq %rdi, %rsi
movq d_a(%rip), %rdi
call cudaMemcpy@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl %r14d, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L18:
movl $2, %ecx
movq %rbx, %rdx
movq d_b(%rip), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %r12d, %ecx
movl %ebp, %edx
movq d_b(%rip), %rsi
movq d_a(%rip), %rdi
call _Z29__device_stub__Z6updatePiS_iiPiS_ii
jmp .L18
.cfi_endproc
.LFE2060:
.size _Z10updateCudaPiS_ii, .-_Z10updateCudaPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6updatePiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_b
.bss
.align 8
.type d_b, @object
.size d_b, 8
d_b:
.zero 8
.globl d_a
.align 8
.type d_a, @object
.size d_a, 8
d_a:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__updatePiS_ii # -- Begin function _Z21__device_stub__updatePiS_ii
.p2align 4, 0x90
.type _Z21__device_stub__updatePiS_ii,@function
_Z21__device_stub__updatePiS_ii: # @_Z21__device_stub__updatePiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__updatePiS_ii, .Lfunc_end0-_Z21__device_stub__updatePiS_ii
.cfi_endproc
# -- End function
.globl _Z5setUpii # -- Begin function _Z5setUpii
.p2align 4, 0x90
.type _Z5setUpii,@function
_Z5setUpii: # @_Z5setUpii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
imull %esi, %edi
movslq %edi, %rbx
shlq $2, %rbx
movl $d_a, %edi
movq %rbx, %rsi
callq hipMalloc
movl $d_b, %edi
movq %rbx, %rsi
popq %rbx
.cfi_def_cfa_offset 8
jmp hipMalloc # TAILCALL
.Lfunc_end1:
.size _Z5setUpii, .Lfunc_end1-_Z5setUpii
.cfi_endproc
# -- End function
.globl _Z7destroyv # -- Begin function _Z7destroyv
.p2align 4, 0x90
.type _Z7destroyv,@function
_Z7destroyv: # @_Z7destroyv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq d_a(%rip), %rdi
callq hipFree
movq d_b(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end2:
.size _Z7destroyv, .Lfunc_end2-_Z7destroyv
.cfi_endproc
# -- End function
.globl _Z10updateCudaPiS_ii # -- Begin function _Z10updateCudaPiS_ii
.p2align 4, 0x90
.type _Z10updateCudaPiS_ii,@function
_Z10updateCudaPiS_ii: # @_Z10updateCudaPiS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %rsi
movl %ecx, %r12d
imull %edx, %r12d
movslq %r12d, %r14
shlq $2, %r14
movq d_a(%rip), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $1, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq d_a(%rip), %rax
movq d_b(%rip), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq d_b(%rip), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10updateCudaPiS_ii, .Lfunc_end3-_Z10updateCudaPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_a,@object # @d_a
.bss
.globl d_a
.p2align 3, 0x0
d_a:
.quad 0
.size d_a, 8
.type d_b,@object # @d_b
.globl d_b
.p2align 3, 0x0
d_b:
.quad 0
.size d_b, 8
.type _Z6updatePiS_ii,@object # @_Z6updatePiS_ii
.section .rodata,"a",@progbits
.globl _Z6updatePiS_ii
.p2align 3, 0x0
_Z6updatePiS_ii:
.quad _Z21__device_stub__updatePiS_ii
.size _Z6updatePiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6updatePiS_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__updatePiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_a
.addrsig_sym d_b
.addrsig_sym _Z6updatePiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h> /* printf, scanf, puts, NULL */
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
#include <iostream>
// From: https://a248.e.akamai.net/f/862/5658/3/developer.download.nvidia.com/assets/cuda/files/reduction.pdf
template<unsigned int blockSize>
__device__ void warpReduce(volatile double *sdata, unsigned int tid){
if (blockSize >= 64) { sdata[tid] += sdata[tid + 32] ; }
if (blockSize >= 32) { sdata[tid] += sdata[tid + 16] ; }
if (blockSize >= 16) { sdata[tid] += sdata[tid + 8]; }
if (blockSize >= 8) { sdata[tid] += sdata[tid + 4]; }
if (blockSize >= 4) {sdata[tid] += sdata[tid + 2]; }
if (blockSize >= 2) {sdata[tid] += sdata[tid + 1]; }
}
template <unsigned int blockSize> __global__ void reduce6( double *g_idata,
double *g_odata, unsigned int n) {
extern __shared__ double sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockSize*2) + tid ;
unsigned int gridSize = blockSize*2*gridDim.x;
sdata[tid] = 0;
while (i < n) {
sdata[tid] += g_idata[i] + g_idata[i + blockSize]; i += gridSize;
}
__syncthreads();
if ( blockSize >= 512) { if ( tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if ( blockSize >= 256) { if ( tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if ( blockSize >= 128) { if ( tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) {
warpReduce<blockSize>(sdata,tid);
}
__syncthreads();
if (tid == 0) {g_odata[blockIdx.x] = sdata[0]; }
}
int main() {
for (int t = 0; t <= 4; t++) {
for (int iter = 1; iter <= 15; iter++) {
for (int bl = 1; bl <= 4; bl*=2) {
printf("Iter %d, Blocks %d",t,bl);
int blocks = 32*bl;
int threads = 1024;
int arraySize = 3200*1024*iter;
int smemSize = threads * sizeof(double);
int arrayBytes = arraySize * sizeof(double);
printf("=====\n");
printf("Input Size = %d\n",arraySize);
double *h_in, *h_out; // host arrays
h_in = (double*) malloc(arrayBytes);
double *d_in, *d_out; //device arrays
h_out = (double*) malloc(smemSize);
for (int i = 0; i < threads; i++) h_out[i] = 0;
double result = 0;
for (int i = 0; i < arraySize; i++) {
h_in[i] = i;
result += i;
}
cudaEvent_t start, stop, startT, stopT;
float time,full;
cudaEventCreate(&start);
cudaEventCreate(&startT);
cudaEventCreate(&stop);
cudaEventCreate(&stopT);
//allocate memory on device and copy
cudaEventRecord(startT,0);
cudaMalloc((void**)&d_in, arrayBytes);
cudaMalloc((void**)&d_out, smemSize);
cudaMemcpy(d_in, h_in, arrayBytes, cudaMemcpyHostToDevice);
cudaEventRecord(start,0);
reduce6<512><<<blocks,threads,smemSize>>>(d_in,d_out,arraySize);
cudaDeviceSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaMemcpy(h_out, d_out, smemSize, cudaMemcpyDeviceToHost);
double res = 0;
for (int i = 0; i < blocks;i++){
res += h_out[i];
}
cudaEventRecord(stopT,0);
cudaEventSynchronize(stopT);
std::cout << "Device Result is: " << h_out[0] << std::endl;
std::cout << "Host Result is: " << result << std::endl;
std::cout << "Result is: " << res << std::endl;
printf("Result correct? %s\n", res == result ? "true" : "false");
cudaEventElapsedTime(&time, start, stop);
cudaEventElapsedTime(&full, startT, stopT);
printf ("Time for the kernel: %f ms\n", time);
printf ("Time Full: %f ms\n", full);
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_out);
}
}
}
} | code for sm_80
Function : _Z7reduce6ILj512EEvPdS0_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0050*/ STS.64 [R0.X8], RZ ; /* 0x000000ff00007388 */
/* 0x0011e20000008a00 */
/*0060*/ IMAD R2, R3, 0x400, R0 ; /* 0x0000040003027824 */
/* 0x002fca00078e0200 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0080*/ @P0 BRA 0x190 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0090*/ BSSY B1, 0x180 ; /* 0x000000e000017945 */
/* 0x001fe20003800000 */
/*00a0*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe4000001ff00 */
/*00b0*/ IADD3 R8, R2, 0x200, RZ ; /* 0x0000020002087810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE.U32 R8, R8, R7, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e0007 */
/*00e0*/ IMAD.WIDE.U32 R6, R2, R7, c[0x0][0x160] ; /* 0x0000580002067625 */
/* 0x000fe400078e0007 */
/*00f0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x001fca0000000f00 */
/*0120*/ IMAD R2, R11, 0x400, R2 ; /* 0x000004000b027824 */
/* 0x000fca00078e0202 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe20003f06070 */
/*0140*/ DADD R10, R8, R6 ; /* 0x00000000080a7229 */
/* 0x004e0c0000000006 */
/*0150*/ DADD R4, R10, R4 ; /* 0x000000000a047229 */
/* 0x00304c0000000004 */
/*0160*/ @!P0 BRA 0xb0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x0023e40000008a00 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R0.reuse, 0xff, PT ; /* 0x000000ff0000780c */
/* 0x040fe40003f04070 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R0.reuse, 0x7f, PT ; /* 0x0000007f0000780c */
/* 0x040fe40003f24070 */
/*01d0*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f45270 */
/*01e0*/ BSSY B0, 0x4a0 ; /* 0x000002b000007945 */
/* 0x000ff00003800000 */
/*01f0*/ @!P0 LDS.64 R4, [R0.X8] ; /* 0x0000000000048984 */
/* 0x002fe80000008a00 */
/*0200*/ @!P0 LDS.64 R6, [R0.X8+0x800] ; /* 0x0008000000068984 */
/* 0x000e240000008a00 */
/*0210*/ @!P0 DADD R4, R4, R6 ; /* 0x0000000004048229 */
/* 0x001e0e0000000006 */
/*0220*/ @!P0 STS.64 [R0.X8], R4 ; /* 0x0000000400008388 */
/* 0x001fe80000008a00 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.GT.U32.AND P0, PT, R0, 0x3f, PT ; /* 0x0000003f0000780c */
/* 0x000fca0003f04070 */
/*0250*/ @!P1 LDS.64 R6, [R0.X8] ; /* 0x0000000000069984 */
/* 0x000fe80000008a00 */
/*0260*/ @!P1 LDS.64 R8, [R0.X8+0x400] ; /* 0x0004000000089984 */
/* 0x000e240000008a00 */
/*0270*/ @!P1 DADD R6, R6, R8 ; /* 0x0000000006069229 */
/* 0x001e0e0000000008 */
/*0280*/ @!P1 STS.64 [R0.X8], R6 ; /* 0x0000000600009388 */
/* 0x001fe80000008a00 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GT.U32.AND P1, PT, R0, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x000fca0003f24070 */
/*02b0*/ @!P0 LDS.64 R8, [R0.X8] ; /* 0x0000000000088984 */
/* 0x000fe80000008a00 */
/*02c0*/ @!P0 LDS.64 R10, [R0.X8+0x200] ; /* 0x00020000000a8984 */
/* 0x000e240000008a00 */
/*02d0*/ @!P0 DADD R8, R8, R10 ; /* 0x0000000008088229 */
/* 0x001e0e000000000a */
/*02e0*/ @!P0 STS.64 [R0.X8], R8 ; /* 0x0000000800008388 */
/* 0x0011e80000008a00 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ @P1 BRA 0x490 ; /* 0x0000018000001947 */
/* 0x000fea0003800000 */
/*0310*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000fe80000008a00 */
/*0320*/ LDS.64 R6, [R0.X8+0x100] ; /* 0x0001000000067984 */
/* 0x000e640000008a00 */
/*0330*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x002e4e0000000006 */
/*0340*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x002fe80000008a00 */
/*0350*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000fe80000008a00 */
/*0360*/ LDS.64 R8, [R0.X8+0x80] ; /* 0x0000800000087984 */
/* 0x001e240000008a00 */
/*0370*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x001e0e0000000008 */
/*0380*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x001fe80000008a00 */
/*0390*/ LDS.64 R8, [R0.X8] ; /* 0x0000000000087984 */
/* 0x000fe80000008a00 */
/*03a0*/ LDS.64 R10, [R0.X8+0x40] ; /* 0x00004000000a7984 */
/* 0x000e240000008a00 */
/*03b0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x001e0e000000000a */
/*03c0*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x001fe80000008a00 */
/*03d0*/ LDS.64 R10, [R0.X8] ; /* 0x00000000000a7984 */
/* 0x000fe80000008a00 */
/*03e0*/ LDS.64 R12, [R0.X8+0x20] ; /* 0x00002000000c7984 */
/* 0x000e240000008a00 */
/*03f0*/ DADD R10, R10, R12 ; /* 0x000000000a0a7229 */
/* 0x001e0e000000000c */
/*0400*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x001fe80000008a00 */
/*0410*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000fe80000008a00 */
/*0420*/ LDS.64 R12, [R0.X8+0x10] ; /* 0x00001000000c7984 */
/* 0x000e240000008a00 */
/*0430*/ DADD R4, R4, R12 ; /* 0x0000000004047229 */
/* 0x001e0e000000000c */
/*0440*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x001fe80000008a00 */
/*0450*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000fe80000008a00 */
/*0460*/ LDS.64 R12, [R0.X8+0x8] ; /* 0x00000800000c7984 */
/* 0x000e240000008a00 */
/*0470*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x001e0e000000000c */
/*0480*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x0011e80000008a00 */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04b0*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*04c0*/ LDS.64 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000a00 */
/*04d0*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*04e0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0002 */
/*04f0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b04 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h> /* printf, scanf, puts, NULL */
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
#include <iostream>
// From: https://a248.e.akamai.net/f/862/5658/3/developer.download.nvidia.com/assets/cuda/files/reduction.pdf
template<unsigned int blockSize>
__device__ void warpReduce(volatile double *sdata, unsigned int tid){
if (blockSize >= 64) { sdata[tid] += sdata[tid + 32] ; }
if (blockSize >= 32) { sdata[tid] += sdata[tid + 16] ; }
if (blockSize >= 16) { sdata[tid] += sdata[tid + 8]; }
if (blockSize >= 8) { sdata[tid] += sdata[tid + 4]; }
if (blockSize >= 4) {sdata[tid] += sdata[tid + 2]; }
if (blockSize >= 2) {sdata[tid] += sdata[tid + 1]; }
}
template <unsigned int blockSize> __global__ void reduce6( double *g_idata,
double *g_odata, unsigned int n) {
extern __shared__ double sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockSize*2) + tid ;
unsigned int gridSize = blockSize*2*gridDim.x;
sdata[tid] = 0;
while (i < n) {
sdata[tid] += g_idata[i] + g_idata[i + blockSize]; i += gridSize;
}
__syncthreads();
if ( blockSize >= 512) { if ( tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if ( blockSize >= 256) { if ( tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if ( blockSize >= 128) { if ( tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) {
warpReduce<blockSize>(sdata,tid);
}
__syncthreads();
if (tid == 0) {g_odata[blockIdx.x] = sdata[0]; }
}
int main() {
for (int t = 0; t <= 4; t++) {
for (int iter = 1; iter <= 15; iter++) {
for (int bl = 1; bl <= 4; bl*=2) {
printf("Iter %d, Blocks %d",t,bl);
int blocks = 32*bl;
int threads = 1024;
int arraySize = 3200*1024*iter;
int smemSize = threads * sizeof(double);
int arrayBytes = arraySize * sizeof(double);
printf("=====\n");
printf("Input Size = %d\n",arraySize);
double *h_in, *h_out; // host arrays
h_in = (double*) malloc(arrayBytes);
double *d_in, *d_out; //device arrays
h_out = (double*) malloc(smemSize);
for (int i = 0; i < threads; i++) h_out[i] = 0;
double result = 0;
for (int i = 0; i < arraySize; i++) {
h_in[i] = i;
result += i;
}
cudaEvent_t start, stop, startT, stopT;
float time,full;
cudaEventCreate(&start);
cudaEventCreate(&startT);
cudaEventCreate(&stop);
cudaEventCreate(&stopT);
//allocate memory on device and copy
cudaEventRecord(startT,0);
cudaMalloc((void**)&d_in, arrayBytes);
cudaMalloc((void**)&d_out, smemSize);
cudaMemcpy(d_in, h_in, arrayBytes, cudaMemcpyHostToDevice);
cudaEventRecord(start,0);
reduce6<512><<<blocks,threads,smemSize>>>(d_in,d_out,arraySize);
cudaDeviceSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaMemcpy(h_out, d_out, smemSize, cudaMemcpyDeviceToHost);
double res = 0;
for (int i = 0; i < blocks;i++){
res += h_out[i];
}
cudaEventRecord(stopT,0);
cudaEventSynchronize(stopT);
std::cout << "Device Result is: " << h_out[0] << std::endl;
std::cout << "Host Result is: " << result << std::endl;
std::cout << "Result is: " << res << std::endl;
printf("Result correct? %s\n", res == result ? "true" : "false");
cudaEventElapsedTime(&time, start, stop);
cudaEventElapsedTime(&full, startT, stopT);
printf ("Time for the kernel: %f ms\n", time);
printf ("Time Full: %f ms\n", full);
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_out);
}
}
}
} | .file "tmpxft_000c4427_00000000-6_reduce.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j, @function
_ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j:
.LFB3697:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7reduce6ILj512EEvPdS0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j, .-_ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j
.section .text._Z7reduce6ILj512EEvPdS0_j,"axG",@progbits,_Z7reduce6ILj512EEvPdS0_j,comdat
.weak _Z7reduce6ILj512EEvPdS0_j
.type _Z7reduce6ILj512EEvPdS0_j, @function
_Z7reduce6ILj512EEvPdS0_j:
.LFB4000:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4000:
.size _Z7reduce6ILj512EEvPdS0_j, .-_Z7reduce6ILj512EEvPdS0_j
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "true"
.LC2:
.string "false"
.LC3:
.string "Iter %d, Blocks %d"
.LC4:
.string "=====\n"
.LC5:
.string "Input Size = %d\n"
.LC6:
.string "Device Result is: "
.LC7:
.string "Host Result is: "
.LC8:
.string "Result is: "
.LC9:
.string "Result correct? %s\n"
.LC10:
.string "Time for the kernel: %f ms\n"
.LC11:
.string "Time Full: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, %r8d
jmp .L12
.L38:
movq $0x000000000, 8(%rsp)
jmp .L14
.L51:
movl 28(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j
jmp .L16
.L39:
movq $0x000000000, (%rsp)
jmp .L17
.L52:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L21:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
jmp .L22
.L53:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L25:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
jmp .L26
.L54:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L29:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
jmp .L30
.L40:
leaq .LC2(%rip), %rdx
.L31:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 92(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 80(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
addl %r14d, %r14d
cmpl $4, %r14d
jg .L50
.L33:
movl %r14d, %ecx
movl 24(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r15d
sall $5, %r15d
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call malloc@PLT
movq %rax, %rbp
movl $8192, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leaq 8192(%rax), %rdx
.L13:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L13
testl %r12d, %r12d
jle .L38
movl $0, %eax
movq $0x000000000, 8(%rsp)
.L15:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $1, %rax
cmpl %eax, %r12d
jg .L15
.L14:
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
leaq 32(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq 16(%rsp), %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl %r15d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $8192, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $8192, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L39
leal -1(%r15), %eax
leaq 8(%r13,%rax,8), %rax
movq $0x000000000, (%rsp)
.L18:
movsd (%rsp), %xmm1
addsd (%rbx), %xmm1
movsd %xmm1, (%rsp)
addq $8, %rbx
cmpq %rax, %rbx
jne .L18
.L17:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $18, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 0(%r13), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L52
cmpb $0, 56(%r15)
je .L21
movzbl 67(%r15), %eax
.L22:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $16, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L25
movzbl 67(%r15), %eax
.L26:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $11, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L54
cmpb $0, 56(%r15)
je .L29
movzbl 67(%r15), %eax
.L30:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movsd 8(%rsp), %xmm3
movsd (%rsp), %xmm4
ucomisd %xmm4, %xmm3
jp .L40
leaq .LC1(%rip), %rdx
je .L31
jmp .L40
.L50:
movl 28(%rsp), %r9d
movq 16(%rsp), %rcx
addl $3276800, %r9d
addq $26214400, %rcx
cmpl $52428800, %r9d
je .L34
.L36:
movl %r9d, %r12d
movl $1, %r14d
movl %r9d, 28(%rsp)
movq %rcx, 16(%rsp)
jmp .L33
.L34:
movl 24(%rsp), %r8d
addl $1, %r8d
cmpl $5, %r8d
je .L35
.L12:
movl $26214400, %ecx
movl $3276800, %r9d
movl %r8d, 24(%rsp)
jmp .L36
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z7reduce6ILj512EEvPdS0_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce6ILj512EEvPdS0_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h> /* printf, scanf, puts, NULL */
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
#include <iostream>
// From: https://a248.e.akamai.net/f/862/5658/3/developer.download.nvidia.com/assets/cuda/files/reduction.pdf
template<unsigned int blockSize>
__device__ void warpReduce(volatile double *sdata, unsigned int tid){
if (blockSize >= 64) { sdata[tid] += sdata[tid + 32] ; }
if (blockSize >= 32) { sdata[tid] += sdata[tid + 16] ; }
if (blockSize >= 16) { sdata[tid] += sdata[tid + 8]; }
if (blockSize >= 8) { sdata[tid] += sdata[tid + 4]; }
if (blockSize >= 4) {sdata[tid] += sdata[tid + 2]; }
if (blockSize >= 2) {sdata[tid] += sdata[tid + 1]; }
}
template <unsigned int blockSize> __global__ void reduce6( double *g_idata,
double *g_odata, unsigned int n) {
extern __shared__ double sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockSize*2) + tid ;
unsigned int gridSize = blockSize*2*gridDim.x;
sdata[tid] = 0;
while (i < n) {
sdata[tid] += g_idata[i] + g_idata[i + blockSize]; i += gridSize;
}
__syncthreads();
if ( blockSize >= 512) { if ( tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if ( blockSize >= 256) { if ( tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if ( blockSize >= 128) { if ( tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) {
warpReduce<blockSize>(sdata,tid);
}
__syncthreads();
if (tid == 0) {g_odata[blockIdx.x] = sdata[0]; }
}
int main() {
for (int t = 0; t <= 4; t++) {
for (int iter = 1; iter <= 15; iter++) {
for (int bl = 1; bl <= 4; bl*=2) {
printf("Iter %d, Blocks %d",t,bl);
int blocks = 32*bl;
int threads = 1024;
int arraySize = 3200*1024*iter;
int smemSize = threads * sizeof(double);
int arrayBytes = arraySize * sizeof(double);
printf("=====\n");
printf("Input Size = %d\n",arraySize);
double *h_in, *h_out; // host arrays
h_in = (double*) malloc(arrayBytes);
double *d_in, *d_out; //device arrays
h_out = (double*) malloc(smemSize);
for (int i = 0; i < threads; i++) h_out[i] = 0;
double result = 0;
for (int i = 0; i < arraySize; i++) {
h_in[i] = i;
result += i;
}
cudaEvent_t start, stop, startT, stopT;
float time,full;
cudaEventCreate(&start);
cudaEventCreate(&startT);
cudaEventCreate(&stop);
cudaEventCreate(&stopT);
//allocate memory on device and copy
cudaEventRecord(startT,0);
cudaMalloc((void**)&d_in, arrayBytes);
cudaMalloc((void**)&d_out, smemSize);
cudaMemcpy(d_in, h_in, arrayBytes, cudaMemcpyHostToDevice);
cudaEventRecord(start,0);
reduce6<512><<<blocks,threads,smemSize>>>(d_in,d_out,arraySize);
cudaDeviceSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaMemcpy(h_out, d_out, smemSize, cudaMemcpyDeviceToHost);
double res = 0;
for (int i = 0; i < blocks;i++){
res += h_out[i];
}
cudaEventRecord(stopT,0);
cudaEventSynchronize(stopT);
std::cout << "Device Result is: " << h_out[0] << std::endl;
std::cout << "Host Result is: " << result << std::endl;
std::cout << "Result is: " << res << std::endl;
printf("Result correct? %s\n", res == result ? "true" : "false");
cudaEventElapsedTime(&time, start, stop);
cudaEventElapsedTime(&full, startT, stopT);
printf ("Time for the kernel: %f ms\n", time);
printf ("Time Full: %f ms\n", full);
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_out);
}
}
}
} | #include <hip/hip_runtime.h>
#include <stdio.h> /* printf, scanf, puts, NULL */
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
#include <iostream>
// From: https://a248.e.akamai.net/f/862/5658/3/developer.download.nvidia.com/assets/cuda/files/reduction.pdf
template<unsigned int blockSize>
__device__ void warpReduce(volatile double *sdata, unsigned int tid){
if (blockSize >= 64) { sdata[tid] += sdata[tid + 32] ; }
if (blockSize >= 32) { sdata[tid] += sdata[tid + 16] ; }
if (blockSize >= 16) { sdata[tid] += sdata[tid + 8]; }
if (blockSize >= 8) { sdata[tid] += sdata[tid + 4]; }
if (blockSize >= 4) {sdata[tid] += sdata[tid + 2]; }
if (blockSize >= 2) {sdata[tid] += sdata[tid + 1]; }
}
template <unsigned int blockSize> __global__ void reduce6( double *g_idata,
double *g_odata, unsigned int n) {
extern __shared__ double sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockSize*2) + tid ;
unsigned int gridSize = blockSize*2*gridDim.x;
sdata[tid] = 0;
while (i < n) {
sdata[tid] += g_idata[i] + g_idata[i + blockSize]; i += gridSize;
}
__syncthreads();
if ( blockSize >= 512) { if ( tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if ( blockSize >= 256) { if ( tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if ( blockSize >= 128) { if ( tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) {
warpReduce<blockSize>(sdata,tid);
}
__syncthreads();
if (tid == 0) {g_odata[blockIdx.x] = sdata[0]; }
}
int main() {
for (int t = 0; t <= 4; t++) {
for (int iter = 1; iter <= 15; iter++) {
for (int bl = 1; bl <= 4; bl*=2) {
printf("Iter %d, Blocks %d",t,bl);
int blocks = 32*bl;
int threads = 1024;
int arraySize = 3200*1024*iter;
int smemSize = threads * sizeof(double);
int arrayBytes = arraySize * sizeof(double);
printf("=====\n");
printf("Input Size = %d\n",arraySize);
double *h_in, *h_out; // host arrays
h_in = (double*) malloc(arrayBytes);
double *d_in, *d_out; //device arrays
h_out = (double*) malloc(smemSize);
for (int i = 0; i < threads; i++) h_out[i] = 0;
double result = 0;
for (int i = 0; i < arraySize; i++) {
h_in[i] = i;
result += i;
}
hipEvent_t start, stop, startT, stopT;
float time,full;
hipEventCreate(&start);
hipEventCreate(&startT);
hipEventCreate(&stop);
hipEventCreate(&stopT);
//allocate memory on device and copy
hipEventRecord(startT,0);
hipMalloc((void**)&d_in, arrayBytes);
hipMalloc((void**)&d_out, smemSize);
hipMemcpy(d_in, h_in, arrayBytes, hipMemcpyHostToDevice);
hipEventRecord(start,0);
reduce6<512><<<blocks,threads,smemSize>>>(d_in,d_out,arraySize);
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipMemcpy(h_out, d_out, smemSize, hipMemcpyDeviceToHost);
double res = 0;
for (int i = 0; i < blocks;i++){
res += h_out[i];
}
hipEventRecord(stopT,0);
hipEventSynchronize(stopT);
std::cout << "Device Result is: " << h_out[0] << std::endl;
std::cout << "Host Result is: " << result << std::endl;
std::cout << "Result is: " << res << std::endl;
printf("Result correct? %s\n", res == result ? "true" : "false");
hipEventElapsedTime(&time, start, stop);
hipEventElapsedTime(&full, startT, stopT);
printf ("Time for the kernel: %f ms\n", time);
printf ("Time Full: %f ms\n", full);
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_out);
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h> /* printf, scanf, puts, NULL */
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
#include <iostream>
// From: https://a248.e.akamai.net/f/862/5658/3/developer.download.nvidia.com/assets/cuda/files/reduction.pdf
template<unsigned int blockSize>
__device__ void warpReduce(volatile double *sdata, unsigned int tid){
if (blockSize >= 64) { sdata[tid] += sdata[tid + 32] ; }
if (blockSize >= 32) { sdata[tid] += sdata[tid + 16] ; }
if (blockSize >= 16) { sdata[tid] += sdata[tid + 8]; }
if (blockSize >= 8) { sdata[tid] += sdata[tid + 4]; }
if (blockSize >= 4) {sdata[tid] += sdata[tid + 2]; }
if (blockSize >= 2) {sdata[tid] += sdata[tid + 1]; }
}
template <unsigned int blockSize> __global__ void reduce6( double *g_idata,
double *g_odata, unsigned int n) {
extern __shared__ double sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockSize*2) + tid ;
unsigned int gridSize = blockSize*2*gridDim.x;
sdata[tid] = 0;
while (i < n) {
sdata[tid] += g_idata[i] + g_idata[i + blockSize]; i += gridSize;
}
__syncthreads();
if ( blockSize >= 512) { if ( tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if ( blockSize >= 256) { if ( tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if ( blockSize >= 128) { if ( tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) {
warpReduce<blockSize>(sdata,tid);
}
__syncthreads();
if (tid == 0) {g_odata[blockIdx.x] = sdata[0]; }
}
int main() {
for (int t = 0; t <= 4; t++) {
for (int iter = 1; iter <= 15; iter++) {
for (int bl = 1; bl <= 4; bl*=2) {
printf("Iter %d, Blocks %d",t,bl);
int blocks = 32*bl;
int threads = 1024;
int arraySize = 3200*1024*iter;
int smemSize = threads * sizeof(double);
int arrayBytes = arraySize * sizeof(double);
printf("=====\n");
printf("Input Size = %d\n",arraySize);
double *h_in, *h_out; // host arrays
h_in = (double*) malloc(arrayBytes);
double *d_in, *d_out; //device arrays
h_out = (double*) malloc(smemSize);
for (int i = 0; i < threads; i++) h_out[i] = 0;
double result = 0;
for (int i = 0; i < arraySize; i++) {
h_in[i] = i;
result += i;
}
hipEvent_t start, stop, startT, stopT;
float time,full;
hipEventCreate(&start);
hipEventCreate(&startT);
hipEventCreate(&stop);
hipEventCreate(&stopT);
//allocate memory on device and copy
hipEventRecord(startT,0);
hipMalloc((void**)&d_in, arrayBytes);
hipMalloc((void**)&d_out, smemSize);
hipMemcpy(d_in, h_in, arrayBytes, hipMemcpyHostToDevice);
hipEventRecord(start,0);
reduce6<512><<<blocks,threads,smemSize>>>(d_in,d_out,arraySize);
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipMemcpy(h_out, d_out, smemSize, hipMemcpyDeviceToHost);
double res = 0;
for (int i = 0; i < blocks;i++){
res += h_out[i];
}
hipEventRecord(stopT,0);
hipEventSynchronize(stopT);
std::cout << "Device Result is: " << h_out[0] << std::endl;
std::cout << "Host Result is: " << result << std::endl;
std::cout << "Result is: " << res << std::endl;
printf("Result correct? %s\n", res == result ? "true" : "false");
hipEventElapsedTime(&time, start, stop);
hipEventElapsedTime(&full, startT, stopT);
printf ("Time for the kernel: %f ms\n", time);
printf ("Time Full: %f ms\n", full);
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_out);
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z7reduce6ILj512EEvPdS0_j,"axG",@progbits,_Z7reduce6ILj512EEvPdS0_j,comdat
.protected _Z7reduce6ILj512EEvPdS0_j
.globl _Z7reduce6ILj512EEvPdS0_j
.p2align 8
.type _Z7reduce6ILj512EEvPdS0_j,@function
_Z7reduce6ILj512EEvPdS0_j:
s_load_b32 s5, s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s4, s15
v_lshl_add_u32 v5, v0, 3, 0
v_lshl_or_b32 v1, s4, 10, v0
s_mov_b32 s7, 0
v_mov_b32_e32 v3, v2
s_mov_b32 s6, exec_lo
ds_store_b64 v5, v[2:3]
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s8, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
ds_load_b64 v[3:4], v5
s_waitcnt lgkmcnt(0)
s_lshl_b32 s8, s8, 10
.p2align 6
.LBB0_2:
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v6, 0x200, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 3, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
v_mov_b32_e32 v7, v2
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[6:7], v[6:7], off
v_cmp_le_u32_e32 vcc_lo, s5, v1
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[6:7]
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s7
ds_store_b64 v5, v[3:4]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v1, v0, 3, 0
ds_load_b64 v[1:2], v1 offset:2048
ds_load_b64 v[3:4], v5
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], v[1:2], v[3:4]
ds_store_b64 v5, v[1:2]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v1, v0, 3, 0
ds_load_b64 v[1:2], v1 offset:1024
ds_load_b64 v[3:4], v5
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], v[1:2], v[3:4]
ds_store_b64 v5, v[1:2]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_10
v_lshl_add_u32 v1, v0, 3, 0
ds_load_b64 v[1:2], v1 offset:512
ds_load_b64 v[3:4], v5
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], v[1:2], v[3:4]
ds_store_b64 v5, v[1:2]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_12
v_lshl_add_u32 v7, v0, 3, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 0x100, v7
v_cmp_ne_u32_e64 s2, -1, v7
v_cmp_ne_u32_e32 vcc_lo, -1, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, v7, s2
v_cndmask_b32_e32 v3, 0, v2, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, s2
flat_load_b64 v[3:4], v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 0x80, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 64, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 32, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 16, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 8, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_14
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s5, 0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[2:3], s[4:5], 3
ds_load_b64 v[0:1], v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce6ILj512EEvPdS0_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z7reduce6ILj512EEvPdS0_j,"axG",@progbits,_Z7reduce6ILj512EEvPdS0_j,comdat
.Lfunc_end0:
.size _Z7reduce6ILj512EEvPdS0_j, .Lfunc_end0-_Z7reduce6ILj512EEvPdS0_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym sdata
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce6ILj512EEvPdS0_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce6ILj512EEvPdS0_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h> /* printf, scanf, puts, NULL */
#include <stdlib.h> /* srand, rand */
#include <time.h> /* time */
#include <iostream>
// From: https://a248.e.akamai.net/f/862/5658/3/developer.download.nvidia.com/assets/cuda/files/reduction.pdf
template<unsigned int blockSize>
__device__ void warpReduce(volatile double *sdata, unsigned int tid){
if (blockSize >= 64) { sdata[tid] += sdata[tid + 32] ; }
if (blockSize >= 32) { sdata[tid] += sdata[tid + 16] ; }
if (blockSize >= 16) { sdata[tid] += sdata[tid + 8]; }
if (blockSize >= 8) { sdata[tid] += sdata[tid + 4]; }
if (blockSize >= 4) {sdata[tid] += sdata[tid + 2]; }
if (blockSize >= 2) {sdata[tid] += sdata[tid + 1]; }
}
template <unsigned int blockSize> __global__ void reduce6( double *g_idata,
double *g_odata, unsigned int n) {
extern __shared__ double sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockSize*2) + tid ;
unsigned int gridSize = blockSize*2*gridDim.x;
sdata[tid] = 0;
while (i < n) {
sdata[tid] += g_idata[i] + g_idata[i + blockSize]; i += gridSize;
}
__syncthreads();
if ( blockSize >= 512) { if ( tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if ( blockSize >= 256) { if ( tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if ( blockSize >= 128) { if ( tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) {
warpReduce<blockSize>(sdata,tid);
}
__syncthreads();
if (tid == 0) {g_odata[blockIdx.x] = sdata[0]; }
}
int main() {
for (int t = 0; t <= 4; t++) {
for (int iter = 1; iter <= 15; iter++) {
for (int bl = 1; bl <= 4; bl*=2) {
printf("Iter %d, Blocks %d",t,bl);
int blocks = 32*bl;
int threads = 1024;
int arraySize = 3200*1024*iter;
int smemSize = threads * sizeof(double);
int arrayBytes = arraySize * sizeof(double);
printf("=====\n");
printf("Input Size = %d\n",arraySize);
double *h_in, *h_out; // host arrays
h_in = (double*) malloc(arrayBytes);
double *d_in, *d_out; //device arrays
h_out = (double*) malloc(smemSize);
for (int i = 0; i < threads; i++) h_out[i] = 0;
double result = 0;
for (int i = 0; i < arraySize; i++) {
h_in[i] = i;
result += i;
}
hipEvent_t start, stop, startT, stopT;
float time,full;
hipEventCreate(&start);
hipEventCreate(&startT);
hipEventCreate(&stop);
hipEventCreate(&stopT);
//allocate memory on device and copy
hipEventRecord(startT,0);
hipMalloc((void**)&d_in, arrayBytes);
hipMalloc((void**)&d_out, smemSize);
hipMemcpy(d_in, h_in, arrayBytes, hipMemcpyHostToDevice);
hipEventRecord(start,0);
reduce6<512><<<blocks,threads,smemSize>>>(d_in,d_out,arraySize);
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipMemcpy(h_out, d_out, smemSize, hipMemcpyDeviceToHost);
double res = 0;
for (int i = 0; i < blocks;i++){
res += h_out[i];
}
hipEventRecord(stopT,0);
hipEventSynchronize(stopT);
std::cout << "Device Result is: " << h_out[0] << std::endl;
std::cout << "Host Result is: " << result << std::endl;
std::cout << "Result is: " << res << std::endl;
printf("Result correct? %s\n", res == result ? "true" : "false");
hipEventElapsedTime(&time, start, stop);
hipEventElapsedTime(&full, startT, stopT);
printf ("Time for the kernel: %f ms\n", time);
printf ("Time Full: %f ms\n", full);
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_out);
}
}
}
} | .text
.file "reduce.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rax # imm = 0x100000000
addq $1024, %rax # imm = 0x400
movq %rax, 144(%rsp) # 8-byte Spill
movl $0, 8(%rsp) # 4-byte Folded Spill
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_12: # in Loop: Header=BB0_1 Depth=1
movl 8(%rsp), %eax # 4-byte Reload
incl %eax
movl %eax, 8(%rsp) # 4-byte Spill
cmpl $5, %eax
je .LBB0_13
.LBB0_1: # %.preheader75
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
# Child Loop BB0_3 Depth 3
# Child Loop BB0_4 Depth 4
# Child Loop BB0_8 Depth 4
movl $3276800, %r13d # imm = 0x320000
movl $1, %eax
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_24: # in Loop: Header=BB0_2 Depth=2
movq 136(%rsp), %rax # 8-byte Reload
incq %rax
addq $3276800, %r13 # imm = 0x320000
cmpq $16, %rax
je .LBB0_12
.LBB0_2: # %.preheader74
# Parent Loop BB0_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_3 Depth 3
# Child Loop BB0_4 Depth 4
# Child Loop BB0_8 Depth 4
imull $3276800, %eax, %ecx # imm = 0x320000
movl %ecx, 12(%rsp) # 4-byte Spill
movq %rax, 136(%rsp) # 8-byte Spill
imulq $26214400, %rax, %rax # imm = 0x1900000
movq %rax, 72(%rsp) # 8-byte Spill
movl $1, %r12d
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_22: # in Loop: Header=BB0_3 Depth=3
movq %r14, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit70
# in Loop: Header=BB0_3 Depth=3
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
ucomisd 88(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %esi
movl $.L.str.8, %eax
cmovneq %rax, %rsi
cmovpq %rax, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 104(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
leal (%r12,%r12), %eax
cmpl $3, %r12d
movl %eax, %r12d
jae .LBB0_24
.LBB0_3: # %.preheader.preheader
# Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB0_4 Depth 4
# Child Loop BB0_8 Depth 4
movl $.L.str, %edi
movl 8(%rsp), %esi # 4-byte Reload
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movl 12(%rsp), %esi # 4-byte Reload
xorl %eax, %eax
callq printf
movq 72(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r15
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
xorpd %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_4: # %.preheader
# Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# Parent Loop BB0_3 Depth=3
# => This Inner Loop Header: Depth=4
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r15,%rax,8)
addsd %xmm0, %xmm1
incq %rax
cmpq %rax, %r13
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=3
movsd %xmm1, 88(%rsp) # 8-byte Spill
movl %r12d, %r14d
shll $5, %r14d
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 40(%rsp), %rdi
movq 72(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
movl $8192, %esi # imm = 0x2000
leaq 32(%rsp), %rdi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movl $8192, %r8d # imm = 0x2000
movq %r14, %rdi
movl $1, %esi
movq 144(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_7
# %bb.6: # in Loop: Header=BB0_3 Depth=3
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 52(%rsp)
leaq 192(%rsp), %rax
movq %rax, 112(%rsp)
leaq 184(%rsp), %rax
movq %rax, 120(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
movl $_Z7reduce6ILj512EEvPdS0_j, %edi
leaq 112(%rsp), %r9
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_7: # in Loop: Header=BB0_3 Depth=3
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl %r12d, %eax
shlq $8, %rax
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_8: # Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# Parent Loop BB0_3 Depth=3
# => This Inner Loop Header: Depth=4
addsd (%rbx,%rcx), %xmm0
addq $8, %rcx
cmpq %rcx, %rax
jne .LBB0_8
# %bb.9: # in Loop: Header=BB0_3 Depth=3
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_25
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_3 Depth=3
cmpb $0, 56(%r14)
je .LBB0_14
# %bb.11: # in Loop: Header=BB0_3 Depth=3
movzbl 67(%r14), %ecx
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_14: # in Loop: Header=BB0_3 Depth=3
movq %r14, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB0_3 Depth=3
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_25
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
# in Loop: Header=BB0_3 Depth=3
cmpb $0, 56(%r14)
je .LBB0_18
# %bb.17: # in Loop: Header=BB0_3 Depth=3
movzbl 67(%r14), %ecx
jmp .LBB0_19
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_3 Depth=3
movq %r14, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB0_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit65
# in Loop: Header=BB0_3 Depth=3
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_25
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
# in Loop: Header=BB0_3 Depth=3
cmpb $0, 56(%r14)
je .LBB0_22
# %bb.21: # in Loop: Header=BB0_3 Depth=3
movzbl 67(%r14), %ecx
jmp .LBB0_23
.LBB0_13:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_25:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z22__device_stub__reduce6ILj512EEvPdS0_j,"axG",@progbits,_Z22__device_stub__reduce6ILj512EEvPdS0_j,comdat
.weak _Z22__device_stub__reduce6ILj512EEvPdS0_j # -- Begin function _Z22__device_stub__reduce6ILj512EEvPdS0_j
.p2align 4, 0x90
.type _Z22__device_stub__reduce6ILj512EEvPdS0_j,@function
_Z22__device_stub__reduce6ILj512EEvPdS0_j: # @_Z22__device_stub__reduce6ILj512EEvPdS0_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce6ILj512EEvPdS0_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__reduce6ILj512EEvPdS0_j, .Lfunc_end1-_Z22__device_stub__reduce6ILj512EEvPdS0_j
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce6ILj512EEvPdS0_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Iter %d, Blocks %d"
.size .L.str, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Input Size = %d\n"
.size .L.str.2, 17
.type _Z7reduce6ILj512EEvPdS0_j,@object # @_Z7reduce6ILj512EEvPdS0_j
.section .rodata._Z7reduce6ILj512EEvPdS0_j,"aG",@progbits,_Z7reduce6ILj512EEvPdS0_j,comdat
.weak _Z7reduce6ILj512EEvPdS0_j
.p2align 3, 0x0
_Z7reduce6ILj512EEvPdS0_j:
.quad _Z22__device_stub__reduce6ILj512EEvPdS0_j
.size _Z7reduce6ILj512EEvPdS0_j, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Device Result is: "
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Host Result is: "
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Result is: "
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Result correct? %s\n"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "true"
.size .L.str.7, 5
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "false"
.size .L.str.8, 6
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Time for the kernel: %f ms\n"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Time Full: %f ms\n"
.size .L.str.10, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reduce6ILj512EEvPdS0_j"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "====="
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce6ILj512EEvPdS0_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce6ILj512EEvPdS0_j
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7reduce6ILj512EEvPdS0_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0050*/ STS.64 [R0.X8], RZ ; /* 0x000000ff00007388 */
/* 0x0011e20000008a00 */
/*0060*/ IMAD R2, R3, 0x400, R0 ; /* 0x0000040003027824 */
/* 0x002fca00078e0200 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0080*/ @P0 BRA 0x190 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0090*/ BSSY B1, 0x180 ; /* 0x000000e000017945 */
/* 0x001fe20003800000 */
/*00a0*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe4000001ff00 */
/*00b0*/ IADD3 R8, R2, 0x200, RZ ; /* 0x0000020002087810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE.U32 R8, R8, R7, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e0007 */
/*00e0*/ IMAD.WIDE.U32 R6, R2, R7, c[0x0][0x160] ; /* 0x0000580002067625 */
/* 0x000fe400078e0007 */
/*00f0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x001fca0000000f00 */
/*0120*/ IMAD R2, R11, 0x400, R2 ; /* 0x000004000b027824 */
/* 0x000fca00078e0202 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe20003f06070 */
/*0140*/ DADD R10, R8, R6 ; /* 0x00000000080a7229 */
/* 0x004e0c0000000006 */
/*0150*/ DADD R4, R10, R4 ; /* 0x000000000a047229 */
/* 0x00304c0000000004 */
/*0160*/ @!P0 BRA 0xb0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x0023e40000008a00 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R0.reuse, 0xff, PT ; /* 0x000000ff0000780c */
/* 0x040fe40003f04070 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R0.reuse, 0x7f, PT ; /* 0x0000007f0000780c */
/* 0x040fe40003f24070 */
/*01d0*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f45270 */
/*01e0*/ BSSY B0, 0x4a0 ; /* 0x000002b000007945 */
/* 0x000ff00003800000 */
/*01f0*/ @!P0 LDS.64 R4, [R0.X8] ; /* 0x0000000000048984 */
/* 0x002fe80000008a00 */
/*0200*/ @!P0 LDS.64 R6, [R0.X8+0x800] ; /* 0x0008000000068984 */
/* 0x000e240000008a00 */
/*0210*/ @!P0 DADD R4, R4, R6 ; /* 0x0000000004048229 */
/* 0x001e0e0000000006 */
/*0220*/ @!P0 STS.64 [R0.X8], R4 ; /* 0x0000000400008388 */
/* 0x001fe80000008a00 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.GT.U32.AND P0, PT, R0, 0x3f, PT ; /* 0x0000003f0000780c */
/* 0x000fca0003f04070 */
/*0250*/ @!P1 LDS.64 R6, [R0.X8] ; /* 0x0000000000069984 */
/* 0x000fe80000008a00 */
/*0260*/ @!P1 LDS.64 R8, [R0.X8+0x400] ; /* 0x0004000000089984 */
/* 0x000e240000008a00 */
/*0270*/ @!P1 DADD R6, R6, R8 ; /* 0x0000000006069229 */
/* 0x001e0e0000000008 */
/*0280*/ @!P1 STS.64 [R0.X8], R6 ; /* 0x0000000600009388 */
/* 0x001fe80000008a00 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GT.U32.AND P1, PT, R0, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x000fca0003f24070 */
/*02b0*/ @!P0 LDS.64 R8, [R0.X8] ; /* 0x0000000000088984 */
/* 0x000fe80000008a00 */
/*02c0*/ @!P0 LDS.64 R10, [R0.X8+0x200] ; /* 0x00020000000a8984 */
/* 0x000e240000008a00 */
/*02d0*/ @!P0 DADD R8, R8, R10 ; /* 0x0000000008088229 */
/* 0x001e0e000000000a */
/*02e0*/ @!P0 STS.64 [R0.X8], R8 ; /* 0x0000000800008388 */
/* 0x0011e80000008a00 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ @P1 BRA 0x490 ; /* 0x0000018000001947 */
/* 0x000fea0003800000 */
/*0310*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000fe80000008a00 */
/*0320*/ LDS.64 R6, [R0.X8+0x100] ; /* 0x0001000000067984 */
/* 0x000e640000008a00 */
/*0330*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x002e4e0000000006 */
/*0340*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x002fe80000008a00 */
/*0350*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000fe80000008a00 */
/*0360*/ LDS.64 R8, [R0.X8+0x80] ; /* 0x0000800000087984 */
/* 0x001e240000008a00 */
/*0370*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x001e0e0000000008 */
/*0380*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x001fe80000008a00 */
/*0390*/ LDS.64 R8, [R0.X8] ; /* 0x0000000000087984 */
/* 0x000fe80000008a00 */
/*03a0*/ LDS.64 R10, [R0.X8+0x40] ; /* 0x00004000000a7984 */
/* 0x000e240000008a00 */
/*03b0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x001e0e000000000a */
/*03c0*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x001fe80000008a00 */
/*03d0*/ LDS.64 R10, [R0.X8] ; /* 0x00000000000a7984 */
/* 0x000fe80000008a00 */
/*03e0*/ LDS.64 R12, [R0.X8+0x20] ; /* 0x00002000000c7984 */
/* 0x000e240000008a00 */
/*03f0*/ DADD R10, R10, R12 ; /* 0x000000000a0a7229 */
/* 0x001e0e000000000c */
/*0400*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x001fe80000008a00 */
/*0410*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000fe80000008a00 */
/*0420*/ LDS.64 R12, [R0.X8+0x10] ; /* 0x00001000000c7984 */
/* 0x000e240000008a00 */
/*0430*/ DADD R4, R4, R12 ; /* 0x0000000004047229 */
/* 0x001e0e000000000c */
/*0440*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x001fe80000008a00 */
/*0450*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000fe80000008a00 */
/*0460*/ LDS.64 R12, [R0.X8+0x8] ; /* 0x00000800000c7984 */
/* 0x000e240000008a00 */
/*0470*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x001e0e000000000c */
/*0480*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x0011e80000008a00 */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04b0*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*04c0*/ LDS.64 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000a00 */
/*04d0*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*04e0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0002 */
/*04f0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b04 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z7reduce6ILj512EEvPdS0_j,"axG",@progbits,_Z7reduce6ILj512EEvPdS0_j,comdat
.protected _Z7reduce6ILj512EEvPdS0_j
.globl _Z7reduce6ILj512EEvPdS0_j
.p2align 8
.type _Z7reduce6ILj512EEvPdS0_j,@function
_Z7reduce6ILj512EEvPdS0_j:
s_load_b32 s5, s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s4, s15
v_lshl_add_u32 v5, v0, 3, 0
v_lshl_or_b32 v1, s4, 10, v0
s_mov_b32 s7, 0
v_mov_b32_e32 v3, v2
s_mov_b32 s6, exec_lo
ds_store_b64 v5, v[2:3]
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s8, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
ds_load_b64 v[3:4], v5
s_waitcnt lgkmcnt(0)
s_lshl_b32 s8, s8, 10
.p2align 6
.LBB0_2:
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v6, 0x200, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 3, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
v_mov_b32_e32 v7, v2
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[6:7], v[6:7], off
v_cmp_le_u32_e32 vcc_lo, s5, v1
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[6:7]
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s7
ds_store_b64 v5, v[3:4]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v1, v0, 3, 0
ds_load_b64 v[1:2], v1 offset:2048
ds_load_b64 v[3:4], v5
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], v[1:2], v[3:4]
ds_store_b64 v5, v[1:2]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v1, v0, 3, 0
ds_load_b64 v[1:2], v1 offset:1024
ds_load_b64 v[3:4], v5
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], v[1:2], v[3:4]
ds_store_b64 v5, v[1:2]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_10
v_lshl_add_u32 v1, v0, 3, 0
ds_load_b64 v[1:2], v1 offset:512
ds_load_b64 v[3:4], v5
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], v[1:2], v[3:4]
ds_store_b64 v5, v[1:2]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_12
v_lshl_add_u32 v7, v0, 3, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 0x100, v7
v_cmp_ne_u32_e64 s2, -1, v7
v_cmp_ne_u32_e32 vcc_lo, -1, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, v7, s2
v_cndmask_b32_e32 v3, 0, v2, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, s2
flat_load_b64 v[3:4], v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 0x80, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 64, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 32, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 16, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_nc_u32_e32 v5, 8, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s7, vcc_lo
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[5:6], v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[3:4], v[5:6]
flat_store_b64 v[1:2], v[3:4] dlc
s_waitcnt_vscnt null, 0x0
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_14
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s5, 0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[2:3], s[4:5], 3
ds_load_b64 v[0:1], v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce6ILj512EEvPdS0_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z7reduce6ILj512EEvPdS0_j,"axG",@progbits,_Z7reduce6ILj512EEvPdS0_j,comdat
.Lfunc_end0:
.size _Z7reduce6ILj512EEvPdS0_j, .Lfunc_end0-_Z7reduce6ILj512EEvPdS0_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym sdata
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce6ILj512EEvPdS0_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce6ILj512EEvPdS0_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c4427_00000000-6_reduce.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j, @function
_ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j:
.LFB3697:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7reduce6ILj512EEvPdS0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j, .-_ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j
.section .text._Z7reduce6ILj512EEvPdS0_j,"axG",@progbits,_Z7reduce6ILj512EEvPdS0_j,comdat
.weak _Z7reduce6ILj512EEvPdS0_j
.type _Z7reduce6ILj512EEvPdS0_j, @function
_Z7reduce6ILj512EEvPdS0_j:
.LFB4000:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4000:
.size _Z7reduce6ILj512EEvPdS0_j, .-_Z7reduce6ILj512EEvPdS0_j
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "true"
.LC2:
.string "false"
.LC3:
.string "Iter %d, Blocks %d"
.LC4:
.string "=====\n"
.LC5:
.string "Input Size = %d\n"
.LC6:
.string "Device Result is: "
.LC7:
.string "Host Result is: "
.LC8:
.string "Result is: "
.LC9:
.string "Result correct? %s\n"
.LC10:
.string "Time for the kernel: %f ms\n"
.LC11:
.string "Time Full: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, %r8d
jmp .L12
.L38:
movq $0x000000000, 8(%rsp)
jmp .L14
.L51:
movl 28(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _ZL39__device_stub__Z7reduce6ILj512EEvPdS0_jPdS_j
jmp .L16
.L39:
movq $0x000000000, (%rsp)
jmp .L17
.L52:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L21:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
jmp .L22
.L53:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L25:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
jmp .L26
.L54:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L29:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
jmp .L30
.L40:
leaq .LC2(%rip), %rdx
.L31:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 92(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 80(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
addl %r14d, %r14d
cmpl $4, %r14d
jg .L50
.L33:
movl %r14d, %ecx
movl 24(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r15d
sall $5, %r15d
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call malloc@PLT
movq %rax, %rbp
movl $8192, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leaq 8192(%rax), %rdx
.L13:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L13
testl %r12d, %r12d
jle .L38
movl $0, %eax
movq $0x000000000, 8(%rsp)
.L15:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $1, %rax
cmpl %eax, %r12d
jg .L15
.L14:
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
leaq 32(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq 16(%rsp), %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl %r15d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $8192, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $8192, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L39
leal -1(%r15), %eax
leaq 8(%r13,%rax,8), %rax
movq $0x000000000, (%rsp)
.L18:
movsd (%rsp), %xmm1
addsd (%rbx), %xmm1
movsd %xmm1, (%rsp)
addq $8, %rbx
cmpq %rax, %rbx
jne .L18
.L17:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $18, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 0(%r13), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L52
cmpb $0, 56(%r15)
je .L21
movzbl 67(%r15), %eax
.L22:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $16, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L25
movzbl 67(%r15), %eax
.L26:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $11, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L54
cmpb $0, 56(%r15)
je .L29
movzbl 67(%r15), %eax
.L30:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movsd 8(%rsp), %xmm3
movsd (%rsp), %xmm4
ucomisd %xmm4, %xmm3
jp .L40
leaq .LC1(%rip), %rdx
je .L31
jmp .L40
.L50:
movl 28(%rsp), %r9d
movq 16(%rsp), %rcx
addl $3276800, %r9d
addq $26214400, %rcx
cmpl $52428800, %r9d
je .L34
.L36:
movl %r9d, %r12d
movl $1, %r14d
movl %r9d, 28(%rsp)
movq %rcx, 16(%rsp)
jmp .L33
.L34:
movl 24(%rsp), %r8d
addl $1, %r8d
cmpl $5, %r8d
je .L35
.L12:
movl $26214400, %ecx
movl $3276800, %r9d
movl %r8d, 24(%rsp)
jmp .L36
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z7reduce6ILj512EEvPdS0_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce6ILj512EEvPdS0_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rax # imm = 0x100000000
addq $1024, %rax # imm = 0x400
movq %rax, 144(%rsp) # 8-byte Spill
movl $0, 8(%rsp) # 4-byte Folded Spill
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_12: # in Loop: Header=BB0_1 Depth=1
movl 8(%rsp), %eax # 4-byte Reload
incl %eax
movl %eax, 8(%rsp) # 4-byte Spill
cmpl $5, %eax
je .LBB0_13
.LBB0_1: # %.preheader75
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
# Child Loop BB0_3 Depth 3
# Child Loop BB0_4 Depth 4
# Child Loop BB0_8 Depth 4
movl $3276800, %r13d # imm = 0x320000
movl $1, %eax
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_24: # in Loop: Header=BB0_2 Depth=2
movq 136(%rsp), %rax # 8-byte Reload
incq %rax
addq $3276800, %r13 # imm = 0x320000
cmpq $16, %rax
je .LBB0_12
.LBB0_2: # %.preheader74
# Parent Loop BB0_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_3 Depth 3
# Child Loop BB0_4 Depth 4
# Child Loop BB0_8 Depth 4
imull $3276800, %eax, %ecx # imm = 0x320000
movl %ecx, 12(%rsp) # 4-byte Spill
movq %rax, 136(%rsp) # 8-byte Spill
imulq $26214400, %rax, %rax # imm = 0x1900000
movq %rax, 72(%rsp) # 8-byte Spill
movl $1, %r12d
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_22: # in Loop: Header=BB0_3 Depth=3
movq %r14, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit70
# in Loop: Header=BB0_3 Depth=3
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
ucomisd 88(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %esi
movl $.L.str.8, %eax
cmovneq %rax, %rsi
cmovpq %rax, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 104(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
leal (%r12,%r12), %eax
cmpl $3, %r12d
movl %eax, %r12d
jae .LBB0_24
.LBB0_3: # %.preheader.preheader
# Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB0_4 Depth 4
# Child Loop BB0_8 Depth 4
movl $.L.str, %edi
movl 8(%rsp), %esi # 4-byte Reload
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movl 12(%rsp), %esi # 4-byte Reload
xorl %eax, %eax
callq printf
movq 72(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r15
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
xorpd %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_4: # %.preheader
# Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# Parent Loop BB0_3 Depth=3
# => This Inner Loop Header: Depth=4
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r15,%rax,8)
addsd %xmm0, %xmm1
incq %rax
cmpq %rax, %r13
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=3
movsd %xmm1, 88(%rsp) # 8-byte Spill
movl %r12d, %r14d
shll $5, %r14d
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 40(%rsp), %rdi
movq 72(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
movl $8192, %esi # imm = 0x2000
leaq 32(%rsp), %rdi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movl $8192, %r8d # imm = 0x2000
movq %r14, %rdi
movl $1, %esi
movq 144(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_7
# %bb.6: # in Loop: Header=BB0_3 Depth=3
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 52(%rsp)
leaq 192(%rsp), %rax
movq %rax, 112(%rsp)
leaq 184(%rsp), %rax
movq %rax, 120(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
movl $_Z7reduce6ILj512EEvPdS0_j, %edi
leaq 112(%rsp), %r9
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_7: # in Loop: Header=BB0_3 Depth=3
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl %r12d, %eax
shlq $8, %rax
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_8: # Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# Parent Loop BB0_3 Depth=3
# => This Inner Loop Header: Depth=4
addsd (%rbx,%rcx), %xmm0
addq $8, %rcx
cmpq %rcx, %rax
jne .LBB0_8
# %bb.9: # in Loop: Header=BB0_3 Depth=3
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_25
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_3 Depth=3
cmpb $0, 56(%r14)
je .LBB0_14
# %bb.11: # in Loop: Header=BB0_3 Depth=3
movzbl 67(%r14), %ecx
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_14: # in Loop: Header=BB0_3 Depth=3
movq %r14, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB0_3 Depth=3
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_25
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
# in Loop: Header=BB0_3 Depth=3
cmpb $0, 56(%r14)
je .LBB0_18
# %bb.17: # in Loop: Header=BB0_3 Depth=3
movzbl 67(%r14), %ecx
jmp .LBB0_19
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_3 Depth=3
movq %r14, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB0_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit65
# in Loop: Header=BB0_3 Depth=3
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_25
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
# in Loop: Header=BB0_3 Depth=3
cmpb $0, 56(%r14)
je .LBB0_22
# %bb.21: # in Loop: Header=BB0_3 Depth=3
movzbl 67(%r14), %ecx
jmp .LBB0_23
.LBB0_13:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_25:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z22__device_stub__reduce6ILj512EEvPdS0_j,"axG",@progbits,_Z22__device_stub__reduce6ILj512EEvPdS0_j,comdat
.weak _Z22__device_stub__reduce6ILj512EEvPdS0_j # -- Begin function _Z22__device_stub__reduce6ILj512EEvPdS0_j
.p2align 4, 0x90
.type _Z22__device_stub__reduce6ILj512EEvPdS0_j,@function
_Z22__device_stub__reduce6ILj512EEvPdS0_j: # @_Z22__device_stub__reduce6ILj512EEvPdS0_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce6ILj512EEvPdS0_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__reduce6ILj512EEvPdS0_j, .Lfunc_end1-_Z22__device_stub__reduce6ILj512EEvPdS0_j
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce6ILj512EEvPdS0_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Iter %d, Blocks %d"
.size .L.str, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Input Size = %d\n"
.size .L.str.2, 17
.type _Z7reduce6ILj512EEvPdS0_j,@object # @_Z7reduce6ILj512EEvPdS0_j
.section .rodata._Z7reduce6ILj512EEvPdS0_j,"aG",@progbits,_Z7reduce6ILj512EEvPdS0_j,comdat
.weak _Z7reduce6ILj512EEvPdS0_j
.p2align 3, 0x0
_Z7reduce6ILj512EEvPdS0_j:
.quad _Z22__device_stub__reduce6ILj512EEvPdS0_j
.size _Z7reduce6ILj512EEvPdS0_j, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Device Result is: "
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Host Result is: "
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Result is: "
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Result correct? %s\n"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "true"
.size .L.str.7, 5
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "false"
.size .L.str.8, 6
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Time for the kernel: %f ms\n"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Time Full: %f ms\n"
.size .L.str.10, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reduce6ILj512EEvPdS0_j"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "====="
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce6ILj512EEvPdS0_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce6ILj512EEvPdS0_j
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reduceNeighboredLess(int *g_idata, int *g_odata, unsigned int n)
{
// set the thread id.
unsigned int tid = threadIdx.x;
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
// convert global data pointer to the local pointer of this block.
int *idata = g_idata + blockIdx.x * blockDim.x;
// boundary check.
if (idx >= n) return;
for (int stride = 1; stride < blockDim.x; stride *= 2)
{
// convert tid into local array index.
int index = 2 * stride * tid;
if (index < blockDim.x)
{
idata[index] += idata[index + stride];
}
// synchronize within threadblock.
__syncthreads();
}
// write result for this block to global mem.
if (tid == 0)
{
g_odata[blockIdx.x] = idata[0];
}
} | code for sm_80
Function : _Z20reduceNeighboredLessPiS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R2, R8, c[0x0][0x0], RZ ; /* 0x0000000008027a24 */
/* 0x001fc800078e02ff */
/*0040*/ IMAD.IADD R0, R2, 0x1, R11 ; /* 0x0000000102007824 */
/* 0x002fca00078e020b */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06070 */
/*00b0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0003 */
/*00c0*/ @!P0 BRA 0x1f0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x000fd400000001ff */
/*00e0*/ IMAD.SHL.U32 R10, R0, 0x2, RZ ; /* 0x00000002000a7824 */
/* 0x000fe200078e00ff */
/*00f0*/ BSSY B0, 0x1b0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0100*/ IMAD R7, R10, R11, RZ ; /* 0x0000000b0a077224 */
/* 0x001fca00078e02ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 BRA 0x1a0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R5, R7.reuse, R0, RZ ; /* 0x0000000007057210 */
/* 0x040fe20007ffe0ff */
/*0140*/ IMAD.WIDE R6, R7, 0x4, R2 ; /* 0x0000000407067825 */
/* 0x000fc800078e0202 */
/*0150*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fe200078e0202 */
/*0160*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000eaa000c1e1900 */
/*0170*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IMAD.IADD R9, R0, 0x1, R5 ; /* 0x0000000100097824 */
/* 0x004fca00078e0205 */
/*0190*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101904 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fe40003f06070 */
/*01d0*/ MOV R0, R10 ; /* 0x0000000a00007202 */
/* 0x000fd60000000f00 */
/*01e0*/ @!P0 BRA 0xe0 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*01f0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f05270 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0220*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0230*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fca00078e0005 */
/*0240*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reduceNeighboredLess(int *g_idata, int *g_odata, unsigned int n)
{
// set the thread id.
unsigned int tid = threadIdx.x;
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
// convert global data pointer to the local pointer of this block.
int *idata = g_idata + blockIdx.x * blockDim.x;
// boundary check.
if (idx >= n) return;
for (int stride = 1; stride < blockDim.x; stride *= 2)
{
// convert tid into local array index.
int index = 2 * stride * tid;
if (index < blockDim.x)
{
idata[index] += idata[index + stride];
}
// synchronize within threadblock.
__syncthreads();
}
// write result for this block to global mem.
if (tid == 0)
{
g_odata[blockIdx.x] = idata[0];
}
} | .file "tmpxft_00196245_00000000-6_reduceNeighboredLess.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j
.type _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j, @function
_Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20reduceNeighboredLessPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j, .-_Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j
.globl _Z20reduceNeighboredLessPiS_j
.type _Z20reduceNeighboredLessPiS_j, @function
_Z20reduceNeighboredLessPiS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20reduceNeighboredLessPiS_j, .-_Z20reduceNeighboredLessPiS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20reduceNeighboredLessPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20reduceNeighboredLessPiS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reduceNeighboredLess(int *g_idata, int *g_odata, unsigned int n)
{
// set the thread id.
unsigned int tid = threadIdx.x;
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
// convert global data pointer to the local pointer of this block.
int *idata = g_idata + blockIdx.x * blockDim.x;
// boundary check.
if (idx >= n) return;
for (int stride = 1; stride < blockDim.x; stride *= 2)
{
// convert tid into local array index.
int index = 2 * stride * tid;
if (index < blockDim.x)
{
idata[index] += idata[index + stride];
}
// synchronize within threadblock.
__syncthreads();
}
// write result for this block to global mem.
if (tid == 0)
{
g_odata[blockIdx.x] = idata[0];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduceNeighboredLess(int *g_idata, int *g_odata, unsigned int n)
{
// set the thread id.
unsigned int tid = threadIdx.x;
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
// convert global data pointer to the local pointer of this block.
int *idata = g_idata + blockIdx.x * blockDim.x;
// boundary check.
if (idx >= n) return;
for (int stride = 1; stride < blockDim.x; stride *= 2)
{
// convert tid into local array index.
int index = 2 * stride * tid;
if (index < blockDim.x)
{
idata[index] += idata[index + stride];
}
// synchronize within threadblock.
__syncthreads();
}
// write result for this block to global mem.
if (tid == 0)
{
g_odata[blockIdx.x] = idata[0];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduceNeighboredLess(int *g_idata, int *g_odata, unsigned int n)
{
// set the thread id.
unsigned int tid = threadIdx.x;
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
// convert global data pointer to the local pointer of this block.
int *idata = g_idata + blockIdx.x * blockDim.x;
// boundary check.
if (idx >= n) return;
for (int stride = 1; stride < blockDim.x; stride *= 2)
{
// convert tid into local array index.
int index = 2 * stride * tid;
if (index < blockDim.x)
{
idata[index] += idata[index + stride];
}
// synchronize within threadblock.
__syncthreads();
}
// write result for this block to global mem.
if (tid == 0)
{
g_odata[blockIdx.x] = idata[0];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20reduceNeighboredLessPiS_j
.globl _Z20reduceNeighboredLessPiS_j
.p2align 8
.type _Z20reduceNeighboredLessPiS_j,@function
_Z20reduceNeighboredLessPiS_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s15, s3
v_add_nc_u32_e32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s5, 0
s_mov_b32 s2, s15
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s6, s4
s_addc_u32 s5, s7, s5
s_cmp_lt_u32 s3, 2
s_cbranch_scc1 .LBB0_6
s_mov_b32 s8, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_ge_u32 s6, s3
s_mov_b32 s8, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_lshl_b32 s6, s8, 1
s_mov_b32 s7, exec_lo
v_mul_lo_u32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
global_load_b32 v1, v0, s[4:5]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20reduceNeighboredLessPiS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20reduceNeighboredLessPiS_j, .Lfunc_end0-_Z20reduceNeighboredLessPiS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20reduceNeighboredLessPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20reduceNeighboredLessPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduceNeighboredLess(int *g_idata, int *g_odata, unsigned int n)
{
// set the thread id.
unsigned int tid = threadIdx.x;
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
// convert global data pointer to the local pointer of this block.
int *idata = g_idata + blockIdx.x * blockDim.x;
// boundary check.
if (idx >= n) return;
for (int stride = 1; stride < blockDim.x; stride *= 2)
{
// convert tid into local array index.
int index = 2 * stride * tid;
if (index < blockDim.x)
{
idata[index] += idata[index + stride];
}
// synchronize within threadblock.
__syncthreads();
}
// write result for this block to global mem.
if (tid == 0)
{
g_odata[blockIdx.x] = idata[0];
}
} | .text
.file "reduceNeighboredLess.hip"
.globl _Z35__device_stub__reduceNeighboredLessPiS_j # -- Begin function _Z35__device_stub__reduceNeighboredLessPiS_j
.p2align 4, 0x90
.type _Z35__device_stub__reduceNeighboredLessPiS_j,@function
_Z35__device_stub__reduceNeighboredLessPiS_j: # @_Z35__device_stub__reduceNeighboredLessPiS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20reduceNeighboredLessPiS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__reduceNeighboredLessPiS_j, .Lfunc_end0-_Z35__device_stub__reduceNeighboredLessPiS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20reduceNeighboredLessPiS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20reduceNeighboredLessPiS_j,@object # @_Z20reduceNeighboredLessPiS_j
.section .rodata,"a",@progbits
.globl _Z20reduceNeighboredLessPiS_j
.p2align 3, 0x0
_Z20reduceNeighboredLessPiS_j:
.quad _Z35__device_stub__reduceNeighboredLessPiS_j
.size _Z20reduceNeighboredLessPiS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20reduceNeighboredLessPiS_j"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__reduceNeighboredLessPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20reduceNeighboredLessPiS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20reduceNeighboredLessPiS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R2, R8, c[0x0][0x0], RZ ; /* 0x0000000008027a24 */
/* 0x001fc800078e02ff */
/*0040*/ IMAD.IADD R0, R2, 0x1, R11 ; /* 0x0000000102007824 */
/* 0x002fca00078e020b */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06070 */
/*00b0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0003 */
/*00c0*/ @!P0 BRA 0x1f0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x000fd400000001ff */
/*00e0*/ IMAD.SHL.U32 R10, R0, 0x2, RZ ; /* 0x00000002000a7824 */
/* 0x000fe200078e00ff */
/*00f0*/ BSSY B0, 0x1b0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0100*/ IMAD R7, R10, R11, RZ ; /* 0x0000000b0a077224 */
/* 0x001fca00078e02ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 BRA 0x1a0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R5, R7.reuse, R0, RZ ; /* 0x0000000007057210 */
/* 0x040fe20007ffe0ff */
/*0140*/ IMAD.WIDE R6, R7, 0x4, R2 ; /* 0x0000000407067825 */
/* 0x000fc800078e0202 */
/*0150*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fe200078e0202 */
/*0160*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000eaa000c1e1900 */
/*0170*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IMAD.IADD R9, R0, 0x1, R5 ; /* 0x0000000100097824 */
/* 0x004fca00078e0205 */
/*0190*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101904 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fe40003f06070 */
/*01d0*/ MOV R0, R10 ; /* 0x0000000a00007202 */
/* 0x000fd60000000f00 */
/*01e0*/ @!P0 BRA 0xe0 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*01f0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f05270 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0220*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0230*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fca00078e0005 */
/*0240*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20reduceNeighboredLessPiS_j
.globl _Z20reduceNeighboredLessPiS_j
.p2align 8
.type _Z20reduceNeighboredLessPiS_j,@function
_Z20reduceNeighboredLessPiS_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s15, s3
v_add_nc_u32_e32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s5, 0
s_mov_b32 s2, s15
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s6, s4
s_addc_u32 s5, s7, s5
s_cmp_lt_u32 s3, 2
s_cbranch_scc1 .LBB0_6
s_mov_b32 s8, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_ge_u32 s6, s3
s_mov_b32 s8, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_lshl_b32 s6, s8, 1
s_mov_b32 s7, exec_lo
v_mul_lo_u32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
global_load_b32 v1, v0, s[4:5]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20reduceNeighboredLessPiS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20reduceNeighboredLessPiS_j, .Lfunc_end0-_Z20reduceNeighboredLessPiS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20reduceNeighboredLessPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20reduceNeighboredLessPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00196245_00000000-6_reduceNeighboredLess.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j
.type _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j, @function
_Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20reduceNeighboredLessPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j, .-_Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j
.globl _Z20reduceNeighboredLessPiS_j
.type _Z20reduceNeighboredLessPiS_j, @function
_Z20reduceNeighboredLessPiS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20reduceNeighboredLessPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20reduceNeighboredLessPiS_j, .-_Z20reduceNeighboredLessPiS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20reduceNeighboredLessPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20reduceNeighboredLessPiS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduceNeighboredLess.hip"
.globl _Z35__device_stub__reduceNeighboredLessPiS_j # -- Begin function _Z35__device_stub__reduceNeighboredLessPiS_j
.p2align 4, 0x90
.type _Z35__device_stub__reduceNeighboredLessPiS_j,@function
_Z35__device_stub__reduceNeighboredLessPiS_j: # @_Z35__device_stub__reduceNeighboredLessPiS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20reduceNeighboredLessPiS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__reduceNeighboredLessPiS_j, .Lfunc_end0-_Z35__device_stub__reduceNeighboredLessPiS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20reduceNeighboredLessPiS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20reduceNeighboredLessPiS_j,@object # @_Z20reduceNeighboredLessPiS_j
.section .rodata,"a",@progbits
.globl _Z20reduceNeighboredLessPiS_j
.p2align 3, 0x0
_Z20reduceNeighboredLessPiS_j:
.quad _Z35__device_stub__reduceNeighboredLessPiS_j
.size _Z20reduceNeighboredLessPiS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20reduceNeighboredLessPiS_j"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__reduceNeighboredLessPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20reduceNeighboredLessPiS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <iostream>
__global__ void add(int *d_a,int *d_b,int *d_c,int n)
{
int idx = threadIdx.x;
d_c[idx] = d_a[idx] + d_b[idx];
}
int main()
{
int n = 0;
int blag = 1;//标志位
do{
std::cout << "请输入数组的长度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的数组长度为为正数,请重新输入:" << std::endl;
}else
{
blag = 0;
}
}while(blag);
/******申请主机内存******/
int * h_a = (int*)malloc(sizeof(int) * n);
int * h_b = (int*)malloc(sizeof(int) * n);
int * h_c = (int*)malloc(sizeof(int) * n);
/******主机内存赋值********/
for(int i = 0; i < n; ++i)
{
h_a[i] = i + 1;
h_b[i] = i + 3;
}
/******申请设备内存**********/
int *d_a,*d_b,*d_c;
cudaMalloc((void**)&d_a,sizeof(int) * n);
cudaMalloc((void**)&d_b,sizeof(int) * n);
cudaMalloc((void**)&d_c,sizeof(int) * n);
/******主机内存数据复制到设备内存********/
cudaMemcpy(d_a,h_a,sizeof(int) * n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,sizeof(int) * n,cudaMemcpyHostToDevice);
/*****启动核函数********/
add<<<1,n>>>(d_a,d_b,d_c,n);
/*****设备内存数据复制到主机内存*********/
cudaMemcpy(h_c,d_c,sizeof(int) * n,cudaMemcpyDeviceToHost);
for(int i = 0; i < n; ++i)
{
std::cout << "h_c[" << i << "] = " << h_c[i] << " ";
}
std::cout << std::endl;
/*******释放设备内存*****/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
/*****释放主机内存*****/
free(h_a);
free(h_b);
free(h_c);
std::cout << "运行结束!" << std::endl;
return 0;
} | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <iostream>
__global__ void add(int *d_a,int *d_b,int *d_c,int n)
{
int idx = threadIdx.x;
d_c[idx] = d_a[idx] + d_b[idx];
}
int main()
{
int n = 0;
int blag = 1;//标志位
do{
std::cout << "请输入数组的长度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的数组长度为为正数,请重新输入:" << std::endl;
}else
{
blag = 0;
}
}while(blag);
/******申请主机内存******/
int * h_a = (int*)malloc(sizeof(int) * n);
int * h_b = (int*)malloc(sizeof(int) * n);
int * h_c = (int*)malloc(sizeof(int) * n);
/******主机内存赋值********/
for(int i = 0; i < n; ++i)
{
h_a[i] = i + 1;
h_b[i] = i + 3;
}
/******申请设备内存**********/
int *d_a,*d_b,*d_c;
cudaMalloc((void**)&d_a,sizeof(int) * n);
cudaMalloc((void**)&d_b,sizeof(int) * n);
cudaMalloc((void**)&d_c,sizeof(int) * n);
/******主机内存数据复制到设备内存********/
cudaMemcpy(d_a,h_a,sizeof(int) * n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,sizeof(int) * n,cudaMemcpyHostToDevice);
/*****启动核函数********/
add<<<1,n>>>(d_a,d_b,d_c,n);
/*****设备内存数据复制到主机内存*********/
cudaMemcpy(h_c,d_c,sizeof(int) * n,cudaMemcpyDeviceToHost);
for(int i = 0; i < n; ++i)
{
std::cout << "h_c[" << i << "] = " << h_c[i] << " ";
}
std::cout << std::endl;
/*******释放设备内存*****/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
/*****释放主机内存*****/
free(h_a);
free(h_b);
free(h_c);
std::cout << "运行结束!" << std::endl;
return 0;
} | .file "tmpxft_00019623_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\350\257\267\350\276\223\345\205\245\346\225\260\347\273\204\347\232\204\351\225\277\345\272\246:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\344\275\240\350\276\223\345\205\245\347\232\204\346\225\260\347\273\204\351\225\277\345\272\246\344\270\272\344\270\272\346\255\243\346\225\260,\350\257\267\351\207\215\346\226\260\350\276\223\345\205\245:"
.section .rodata.str1.1
.LC2:
.string "h_c["
.LC3:
.string "] = "
.LC4:
.string " "
.LC5:
.string "\350\277\220\350\241\214\347\273\223\346\235\237!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq .LC0(%rip), %r12
leaq _ZSt4cout(%rip), %rbx
leaq _ZSt3cin(%rip), %r13
leaq .LC1(%rip), %r14
jmp .L21
.L33:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
call _ZSt16__throw_bad_castv@PLT
.L31:
call __stack_chk_fail@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L34:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L19:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L20:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L21:
movl $25, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L33
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 4(%rsp), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jg .L16
movl $53, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L34
cmpb $0, 56(%rbp)
je .L19
movzbl 67(%rbp), %esi
jmp .L20
.L35:
movl 4(%rsp), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L23
.L16:
movslq %eax, %rbx
leaq 0(,%rbx,4), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movl $1, %eax
.L22:
movl %eax, -4(%r15,%rax,4)
leal 2(%rax), %edx
movl %edx, -4(%r14,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rbx
jne .L22
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L23:
movslq 4(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $0, 4(%rsp)
jle .L24
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
.L25:
movl $4, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $4, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%r13,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L25
.L24:
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <iostream>
__global__ void add(int *d_a,int *d_b,int *d_c,int n)
{
int idx = threadIdx.x;
d_c[idx] = d_a[idx] + d_b[idx];
}
int main()
{
int n = 0;
int blag = 1;//标志位
do{
std::cout << "请输入数组的长度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的数组长度为为正数,请重新输入:" << std::endl;
}else
{
blag = 0;
}
}while(blag);
/******申请主机内存******/
int * h_a = (int*)malloc(sizeof(int) * n);
int * h_b = (int*)malloc(sizeof(int) * n);
int * h_c = (int*)malloc(sizeof(int) * n);
/******主机内存赋值********/
for(int i = 0; i < n; ++i)
{
h_a[i] = i + 1;
h_b[i] = i + 3;
}
/******申请设备内存**********/
int *d_a,*d_b,*d_c;
cudaMalloc((void**)&d_a,sizeof(int) * n);
cudaMalloc((void**)&d_b,sizeof(int) * n);
cudaMalloc((void**)&d_c,sizeof(int) * n);
/******主机内存数据复制到设备内存********/
cudaMemcpy(d_a,h_a,sizeof(int) * n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,sizeof(int) * n,cudaMemcpyHostToDevice);
/*****启动核函数********/
add<<<1,n>>>(d_a,d_b,d_c,n);
/*****设备内存数据复制到主机内存*********/
cudaMemcpy(h_c,d_c,sizeof(int) * n,cudaMemcpyDeviceToHost);
for(int i = 0; i < n; ++i)
{
std::cout << "h_c[" << i << "] = " << h_c[i] << " ";
}
std::cout << std::endl;
/*******释放设备内存*****/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
/*****释放主机内存*****/
free(h_a);
free(h_b);
free(h_c);
std::cout << "运行结束!" << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void add(int *d_a,int *d_b,int *d_c,int n)
{
int idx = threadIdx.x;
d_c[idx] = d_a[idx] + d_b[idx];
}
int main()
{
int n = 0;
int blag = 1;//标志位
do{
std::cout << "请输入数组的长度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的数组长度为为正数,请重新输入:" << std::endl;
}else
{
blag = 0;
}
}while(blag);
/******申请主机内存******/
int * h_a = (int*)malloc(sizeof(int) * n);
int * h_b = (int*)malloc(sizeof(int) * n);
int * h_c = (int*)malloc(sizeof(int) * n);
/******主机内存赋值********/
for(int i = 0; i < n; ++i)
{
h_a[i] = i + 1;
h_b[i] = i + 3;
}
/******申请设备内存**********/
int *d_a,*d_b,*d_c;
hipMalloc((void**)&d_a,sizeof(int) * n);
hipMalloc((void**)&d_b,sizeof(int) * n);
hipMalloc((void**)&d_c,sizeof(int) * n);
/******主机内存数据复制到设备内存********/
hipMemcpy(d_a,h_a,sizeof(int) * n,hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,sizeof(int) * n,hipMemcpyHostToDevice);
/*****启动核函数********/
add<<<1,n>>>(d_a,d_b,d_c,n);
/*****设备内存数据复制到主机内存*********/
hipMemcpy(h_c,d_c,sizeof(int) * n,hipMemcpyDeviceToHost);
for(int i = 0; i < n; ++i)
{
std::cout << "h_c[" << i << "] = " << h_c[i] << " ";
}
std::cout << std::endl;
/*******释放设备内存*****/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
/*****释放主机内存*****/
free(h_a);
free(h_b);
free(h_c);
std::cout << "运行结束!" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void add(int *d_a,int *d_b,int *d_c,int n)
{
int idx = threadIdx.x;
d_c[idx] = d_a[idx] + d_b[idx];
}
int main()
{
int n = 0;
int blag = 1;//标志位
do{
std::cout << "请输入数组的长度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的数组长度为为正数,请重新输入:" << std::endl;
}else
{
blag = 0;
}
}while(blag);
/******申请主机内存******/
int * h_a = (int*)malloc(sizeof(int) * n);
int * h_b = (int*)malloc(sizeof(int) * n);
int * h_c = (int*)malloc(sizeof(int) * n);
/******主机内存赋值********/
for(int i = 0; i < n; ++i)
{
h_a[i] = i + 1;
h_b[i] = i + 3;
}
/******申请设备内存**********/
int *d_a,*d_b,*d_c;
hipMalloc((void**)&d_a,sizeof(int) * n);
hipMalloc((void**)&d_b,sizeof(int) * n);
hipMalloc((void**)&d_c,sizeof(int) * n);
/******主机内存数据复制到设备内存********/
hipMemcpy(d_a,h_a,sizeof(int) * n,hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,sizeof(int) * n,hipMemcpyHostToDevice);
/*****启动核函数********/
add<<<1,n>>>(d_a,d_b,d_c,n);
/*****设备内存数据复制到主机内存*********/
hipMemcpy(h_c,d_c,sizeof(int) * n,hipMemcpyDeviceToHost);
for(int i = 0; i < n; ++i)
{
std::cout << "h_c[" << i << "] = " << h_c[i] << " ";
}
std::cout << std::endl;
/*******释放设备内存*****/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
/*****释放主机内存*****/
free(h_a);
free(h_b);
free(h_c);
std::cout << "运行结束!" << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void add(int *d_a,int *d_b,int *d_c,int n)
{
int idx = threadIdx.x;
d_c[idx] = d_a[idx] + d_b[idx];
}
int main()
{
int n = 0;
int blag = 1;//标志位
do{
std::cout << "请输入数组的长度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的数组长度为为正数,请重新输入:" << std::endl;
}else
{
blag = 0;
}
}while(blag);
/******申请主机内存******/
int * h_a = (int*)malloc(sizeof(int) * n);
int * h_b = (int*)malloc(sizeof(int) * n);
int * h_c = (int*)malloc(sizeof(int) * n);
/******主机内存赋值********/
for(int i = 0; i < n; ++i)
{
h_a[i] = i + 1;
h_b[i] = i + 3;
}
/******申请设备内存**********/
int *d_a,*d_b,*d_c;
hipMalloc((void**)&d_a,sizeof(int) * n);
hipMalloc((void**)&d_b,sizeof(int) * n);
hipMalloc((void**)&d_c,sizeof(int) * n);
/******主机内存数据复制到设备内存********/
hipMemcpy(d_a,h_a,sizeof(int) * n,hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,sizeof(int) * n,hipMemcpyHostToDevice);
/*****启动核函数********/
add<<<1,n>>>(d_a,d_b,d_c,n);
/*****设备内存数据复制到主机内存*********/
hipMemcpy(h_c,d_c,sizeof(int) * n,hipMemcpyDeviceToHost);
for(int i = 0; i < n; ++i)
{
std::cout << "h_c[" << i << "] = " << h_c[i] << " ";
}
std::cout << std::endl;
/*******释放设备内存*****/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
/*****释放主机内存*****/
free(h_a);
free(h_b);
free(h_c);
std::cout << "运行结束!" << std::endl;
return 0;
} | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 4(%rsp)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.1:
leaq 4(%rsp), %rbx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit27
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_11
.LBB1_2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# =>This Inner Loop Header: Depth=1
cmpb $0, 56(%r14)
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
movl 4(%rsp), %r13d
testl %r13d, %r13d
jg .LBB1_12
# %bb.6: # in Loop: Header=BB1_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $53, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i24
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_10
.LBB1_12: # %.critedge
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
leal 3(%rax), %edx
movl %edx, (%r14,%rax,4)
movq %rcx, %rax
cmpq %rcx, %r13
jne .LBB1_13
# %bb.14:
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp)
jle .LBB1_19
# %bb.17: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_18: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15,%r12,4), %esi
movq %r13, %rdi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
movslq 4(%rsp), %rax
cmpq %rax, %r12
jl .LBB1_18
.LBB1_19: # %._crit_edge48
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_11
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
cmpb $0, 56(%r12)
je .LBB1_22
# %bb.21:
movzbl 67(%r12), %eax
jmp .LBB1_23
.LBB1_22:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i34
cmpb $0, 56(%rbx)
je .LBB1_26
# %bb.25:
movzbl 67(%rbx), %eax
jmp .LBB1_27
.LBB1_26:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit37
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11: # %._crit_edge
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\350\257\267\350\276\223\345\205\245\346\225\260\347\273\204\347\232\204\351\225\277\345\272\246:"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\344\275\240\350\276\223\345\205\245\347\232\204\346\225\260\347\273\204\351\225\277\345\272\246\344\270\272\344\270\272\346\255\243\346\225\260,\350\257\267\351\207\215\346\226\260\350\276\223\345\205\245:"
.size .L.str.1, 54
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "h_c["
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "] = "
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\350\277\220\350\241\214\347\273\223\346\235\237!"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00019623_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\350\257\267\350\276\223\345\205\245\346\225\260\347\273\204\347\232\204\351\225\277\345\272\246:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\344\275\240\350\276\223\345\205\245\347\232\204\346\225\260\347\273\204\351\225\277\345\272\246\344\270\272\344\270\272\346\255\243\346\225\260,\350\257\267\351\207\215\346\226\260\350\276\223\345\205\245:"
.section .rodata.str1.1
.LC2:
.string "h_c["
.LC3:
.string "] = "
.LC4:
.string " "
.LC5:
.string "\350\277\220\350\241\214\347\273\223\346\235\237!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq .LC0(%rip), %r12
leaq _ZSt4cout(%rip), %rbx
leaq _ZSt3cin(%rip), %r13
leaq .LC1(%rip), %r14
jmp .L21
.L33:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
call _ZSt16__throw_bad_castv@PLT
.L31:
call __stack_chk_fail@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L34:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
call _ZSt16__throw_bad_castv@PLT
.L32:
call __stack_chk_fail@PLT
.L19:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L20:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L21:
movl $25, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L33
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 4(%rsp), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jg .L16
movl $53, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L34
cmpb $0, 56(%rbp)
je .L19
movzbl 67(%rbp), %esi
jmp .L20
.L35:
movl 4(%rsp), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L23
.L16:
movslq %eax, %rbx
leaq 0(,%rbx,4), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movl $1, %eax
.L22:
movl %eax, -4(%r15,%rax,4)
leal 2(%rax), %edx
movl %edx, -4(%r14,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rbx
jne .L22
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L23:
movslq 4(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $0, 4(%rsp)
jle .L24
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
.L25:
movl $4, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $4, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%r13,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L25
.L24:
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 4(%rsp)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.1:
leaq 4(%rsp), %rbx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit27
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_11
.LBB1_2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# =>This Inner Loop Header: Depth=1
cmpb $0, 56(%r14)
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
movl 4(%rsp), %r13d
testl %r13d, %r13d
jg .LBB1_12
# %bb.6: # in Loop: Header=BB1_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $53, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i24
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_10
.LBB1_12: # %.critedge
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
leal 3(%rax), %edx
movl %edx, (%r14,%rax,4)
movq %rcx, %rax
cmpq %rcx, %r13
jne .LBB1_13
# %bb.14:
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp)
jle .LBB1_19
# %bb.17: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_18: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15,%r12,4), %esi
movq %r13, %rdi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
movslq 4(%rsp), %rax
cmpq %rax, %r12
jl .LBB1_18
.LBB1_19: # %._crit_edge48
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_11
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
cmpb $0, 56(%r12)
je .LBB1_22
# %bb.21:
movzbl 67(%r12), %eax
jmp .LBB1_23
.LBB1_22:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i34
cmpb $0, 56(%rbx)
je .LBB1_26
# %bb.25:
movzbl 67(%rbx), %eax
jmp .LBB1_27
.LBB1_26:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit37
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11: # %._crit_edge
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\350\257\267\350\276\223\345\205\245\346\225\260\347\273\204\347\232\204\351\225\277\345\272\246:"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\344\275\240\350\276\223\345\205\245\347\232\204\346\225\260\347\273\204\351\225\277\345\272\246\344\270\272\344\270\272\346\255\243\346\225\260,\350\257\267\351\207\215\346\226\260\350\276\223\345\205\245:"
.size .L.str.1, 54
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "h_c["
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "] = "
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\350\277\220\350\241\214\347\273\223\346\235\237!"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cassert>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <numeric>
#include <vector>
using namespace std;
#define TILE_SIZE 64
#define MAX_MASK_WIDTH 5
__constant__ float c_M[MAX_MASK_WIDTH];
__global__
void convolution1(const float* N, const float* M, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width/2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j]*M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution2(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width / 2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution3(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float Nds[TILE_SIZE + MAX_MASK_WIDTH - 1];
// load N from global memory into shared memory
int n = mask_width/2;
if (threadIdx.x >= blockDim.x - n) {
int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x;
Nds[threadIdx.x - (blockDim.x - n)] = (halo_index_left < 0) ? 0 : N[halo_index_left];
}
Nds[n + threadIdx.x] = N[i];
if (threadIdx.x < n) {
int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x;
Nds[n + blockDim.x + threadIdx.x] = (halo_index_right >= width) ? 0 : N[halo_index_right];
}
__syncthreads();
float Pvalue = 0.0f;
for (int j = 0; j < mask_width; ++j) {
Pvalue += Nds[threadIdx.x + j]*c_M[j];
}
P[i] = Pvalue;
}
int main(int argc, char* argv[])
{
// Query GPU properties
cudaDeviceProp dev_prop;
cudaGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int size = atoi(argv[1]);
// creating vector on host side
vector<float> h_N(size, 1.0f);
std::iota(h_N.begin(), h_N.end(), 0.0f);
// Copy vector on device side
float* d_N;
cudaMalloc((void**)&d_N, size*sizeof(float));
cudaMemcpy((void*)d_N, (void*)h_N.data(), size*sizeof(float), cudaMemcpyHostToDevice);
// Create mask and send to devide
vector<float> h_M = { 1.0f, 1.0f, 2.0f, 1.0f, 1.0f };
int mask_width = h_M.size();
assert(mask_width < MAX_MASK_WIDTH);
cudaMemcpyToSymbol(c_M, (void*)h_M.data(), mask_width*sizeof(float));
// Allocate space for solution on device
float* d_P;
cudaMalloc((void**)&d_P, size*sizeof(float));
// call Kernel
int blockDim = TILE_SIZE;
int gridDim = ceil(size/(float)blockDim);
int version = atoi(argv[2]);
if(version == 1)
convolution2<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else if(version == 2)
convolution3<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else
cout << "Wrong inputs!" << endl;
// Recover vector from device to host
vector<float> h_P(size);
cudaMemcpy((void*)h_P.data(), (void*)d_P, size*sizeof(float), cudaMemcpyDeviceToHost);
// Finalize storage
cudaFree(d_N);
cudaFree(d_P);
cout << "Closing..." << endl;
return 0;
} | .file "tmpxft_0014b803_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii
.type _Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii, @function
_Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii:
.LFB4096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12convolution1PKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4096:
.size _Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii, .-_Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii
.globl _Z12convolution1PKfS0_Pfii
.type _Z12convolution1PKfS0_Pfii, @function
_Z12convolution1PKfS0_Pfii:
.LFB4097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4097:
.size _Z12convolution1PKfS0_Pfii, .-_Z12convolution1PKfS0_Pfii
.globl _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii
.type _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii, @function
_Z37__device_stub__Z12convolution2PKfPfiiPKfPfii:
.LFB4098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12convolution2PKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4098:
.size _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii, .-_Z37__device_stub__Z12convolution2PKfPfiiPKfPfii
.globl _Z12convolution2PKfPfii
.type _Z12convolution2PKfPfii, @function
_Z12convolution2PKfPfii:
.LFB4099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4099:
.size _Z12convolution2PKfPfii, .-_Z12convolution2PKfPfii
.globl _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii
.type _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii, @function
_Z37__device_stub__Z12convolution3PKfPfiiPKfPfii:
.LFB4100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12convolution3PKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4100:
.size _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii, .-_Z37__device_stub__Z12convolution3PKfPfiiPKfPfii
.globl _Z12convolution3PKfPfii
.type _Z12convolution3PKfPfii, @function
_Z12convolution3PKfPfii:
.LFB4101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4101:
.size _Z12convolution3PKfPfii, .-_Z12convolution3PKfPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12convolution3PKfPfii"
.LC1:
.string "_Z12convolution2PKfPfii"
.LC2:
.string "_Z12convolution1PKfS0_Pfii"
.LC3:
.string "c_M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12convolution3PKfPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12convolution2PKfPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12convolution1PKfS0_Pfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3c_M(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4418:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE4418:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "---------------------------------------------"
.align 8
.LC6:
.string " GPU PROPERTIES "
.section .rodata.str1.1
.LC7:
.string "Device Name: "
.LC8:
.string "Memory Clock Rate: "
.LC10:
.string " GHz"
.LC11:
.string "Memory Bandwidth: "
.LC12:
.string " GB/s"
.LC13:
.string "Number of SM: "
.LC14:
.string "Max Threads per SM: "
.LC15:
.string "Registers per Block: "
.LC16:
.string "Shared Memory per Block: "
.LC17:
.string " B"
.section .rodata.str1.8
.align 8
.LC18:
.string "Total Global Memory per Block: "
.section .rodata.str1.1
.LC20:
.string " GB"
.section .rodata.str1.8
.align 8
.LC21:
.string "cannot create std::vector larger than max_size()"
.section .rodata.str1.1
.LC27:
.string "Wrong inputs!"
.LC28:
.string "Closing..."
.text
.globl main
.type main, @function
main:
.LFB4071:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4071
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1208, %rsp
.cfi_def_cfa_offset 1264
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, 1192(%rsp)
xorl %eax, %eax
leaq 160(%rsp), %rbp
movl $0, %esi
movq %rbp, %rdi
.LEHB0:
call cudaGetDeviceProperties_v2@PLT
leaq .LC5(%rip), %r12
movq %r12, %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdl 768(%rsp), %xmm0
divsd .LC9(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdl 768(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 772(%rsp), %eax
leal 7(%rax), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $3, %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
mulsd %xmm1, %xmm0
divsd .LC9(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 548(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 784(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 464(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 456(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 448(%rsp), %rdx
testq %rdx, %rdx
js .L36
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
.L37:
divsd .LC19(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r15d
movslq %eax, %r13
movq %r13, %rax
shrq $61, %rax
jne .L66
testq %r13, %r13
je .L40
leaq 0(,%r13,4), %rbx
movq %rbx, %rdi
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
movq %rax, 32(%rsp)
leaq (%rax,%rbx), %rdx
movq %rdx, 48(%rsp)
movss .LC22(%rip), %xmm0
.L41:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L41
movq %rdx, 40(%rsp)
movq %r12, %rax
pxor %xmm0, %xmm0
movss .LC22(%rip), %xmm1
.L42:
movss %xmm0, (%rax)
addss %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L42
.L56:
movq %rsp, %rdi
movq %rbx, %rsi
.LEHB1:
call cudaMalloc@PLT
.LEHE1:
jmp .L67
.L36:
movq %rdx, %rax
shrq %rax
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L37
.L66:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L68
leaq .LC21(%rip), %rdi
.LEHB2:
call _ZSt20__throw_length_errorPKc@PLT
.LEHE2:
.L68:
call __stack_chk_fail@PLT
.L67:
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
.LEHB3:
call cudaMemcpy@PLT
movss .LC22(%rip), %xmm0
movss %xmm0, 128(%rsp)
movss %xmm0, 132(%rsp)
movl $0x40000000, 136(%rsp)
movss %xmm0, 140(%rsp)
movss %xmm0, 144(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $20, %edi
call _Znwm@PLT
.LEHE3:
movq %rax, %rsi
movq %rax, 64(%rsp)
leaq 20(%rax), %rax
movq %rax, 80(%rsp)
movdqa 128(%rsp), %xmm5
movups %xmm5, (%rsi)
movl 144(%rsp), %edx
movl %edx, 16(%rsi)
movq %rax, 72(%rsp)
movl $1, %r8d
movl $0, %ecx
movl $20, %edx
leaq _ZL3c_M(%rip), %rdi
.LEHB4:
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC24(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC29(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC25(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L43
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC22(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L43:
cvttss2sil %xmm3, %ebp
movq 16(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl $1, %eax
je .L69
cmpl $2, %eax
je .L70
leaq .LC27(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L71
.L69:
movl $64, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %ebp, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L46
movl %r15d, %ecx
movl $5, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii
jmp .L46
.L70:
movl $64, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %ebp, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L46:
movq $0, 104(%rsp)
movq $0, 112(%rsp)
testq %r13, %r13
je .L49
movq %rbx, %rdi
call _Znwm@PLT
jmp .L73
.L72:
movl %r15d, %ecx
movl $5, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii
jmp .L46
.L71:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE4:
jmp .L46
.L73:
movq %rax, %rdi
movq %rax, 96(%rsp)
leaq (%rax,%rbx), %rax
movq %rax, 112(%rsp)
movl $0x00000000, (%rdi)
leaq 4(%rdi), %rdx
cmpq $1, %r13
je .L50
cmpq %rdx, %rax
je .L50
.L51:
movl $0x00000000, (%rdx)
addq $4, %rdx
cmpq %rdx, %rax
jne .L51
movq %rax, %rdx
jmp .L50
.L75:
movq (%rsp), %rdi
.LEHB5:
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC28(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE5:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 32(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L74
movl $0, %eax
addq $1208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L53:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L54:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 1192(%rsp), %rax
subq %fs:40, %rax
je .L55
call __stack_chk_fail@PLT
.L59:
endbr64
movq %rax, %rbx
jmp .L53
.L58:
endbr64
movq %rax, %rbx
jmp .L54
.L55:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L49:
movq $0, 96(%rsp)
movq %rbx, 112(%rsp)
movl $0, %edi
movl $0, %edx
.L50:
movq %rdx, 104(%rsp)
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
.LEHB7:
call cudaMemcpy@PLT
.LEHE7:
jmp .L75
.L40:
movq $0, 32(%rsp)
movq $0, 48(%rsp)
movq $0, 40(%rsp)
movq %r13, %rbx
movl $0, %r12d
jmp .L56
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4071:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4071:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4071-.LLSDACSB4071
.LLSDACSB4071:
.uleb128 .LEHB0-.LFB4071
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4071
.uleb128 .LEHE1-.LEHB1
.uleb128 .L58-.LFB4071
.uleb128 0
.uleb128 .LEHB2-.LFB4071
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4071
.uleb128 .LEHE3-.LEHB3
.uleb128 .L58-.LFB4071
.uleb128 0
.uleb128 .LEHB4-.LFB4071
.uleb128 .LEHE4-.LEHB4
.uleb128 .L59-.LFB4071
.uleb128 0
.uleb128 .LEHB5-.LFB4071
.uleb128 .LEHE5-.LEHB5
.uleb128 .L60-.LFB4071
.uleb128 0
.uleb128 .LEHB6-.LFB4071
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4071
.uleb128 .LEHE7-.LEHB7
.uleb128 .L60-.LFB4071
.uleb128 0
.LLSDACSE4071:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3c_M
.comm _ZL3c_M,20,16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.align 8
.LC19:
.long 0
.long 1104006501
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC22:
.long 1065353216
.align 4
.LC24:
.long 1015021568
.align 4
.LC25:
.long 1258291200
.align 4
.LC29:
.long 2147483647
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cassert>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <numeric>
#include <vector>
using namespace std;
#define TILE_SIZE 64
#define MAX_MASK_WIDTH 5
__constant__ float c_M[MAX_MASK_WIDTH];
__global__
void convolution1(const float* N, const float* M, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width/2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j]*M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution2(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width / 2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution3(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float Nds[TILE_SIZE + MAX_MASK_WIDTH - 1];
// load N from global memory into shared memory
int n = mask_width/2;
if (threadIdx.x >= blockDim.x - n) {
int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x;
Nds[threadIdx.x - (blockDim.x - n)] = (halo_index_left < 0) ? 0 : N[halo_index_left];
}
Nds[n + threadIdx.x] = N[i];
if (threadIdx.x < n) {
int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x;
Nds[n + blockDim.x + threadIdx.x] = (halo_index_right >= width) ? 0 : N[halo_index_right];
}
__syncthreads();
float Pvalue = 0.0f;
for (int j = 0; j < mask_width; ++j) {
Pvalue += Nds[threadIdx.x + j]*c_M[j];
}
P[i] = Pvalue;
}
int main(int argc, char* argv[])
{
// Query GPU properties
cudaDeviceProp dev_prop;
cudaGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int size = atoi(argv[1]);
// creating vector on host side
vector<float> h_N(size, 1.0f);
std::iota(h_N.begin(), h_N.end(), 0.0f);
// Copy vector on device side
float* d_N;
cudaMalloc((void**)&d_N, size*sizeof(float));
cudaMemcpy((void*)d_N, (void*)h_N.data(), size*sizeof(float), cudaMemcpyHostToDevice);
// Create mask and send to devide
vector<float> h_M = { 1.0f, 1.0f, 2.0f, 1.0f, 1.0f };
int mask_width = h_M.size();
assert(mask_width < MAX_MASK_WIDTH);
cudaMemcpyToSymbol(c_M, (void*)h_M.data(), mask_width*sizeof(float));
// Allocate space for solution on device
float* d_P;
cudaMalloc((void**)&d_P, size*sizeof(float));
// call Kernel
int blockDim = TILE_SIZE;
int gridDim = ceil(size/(float)blockDim);
int version = atoi(argv[2]);
if(version == 1)
convolution2<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else if(version == 2)
convolution3<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else
cout << "Wrong inputs!" << endl;
// Recover vector from device to host
vector<float> h_P(size);
cudaMemcpy((void*)h_P.data(), (void*)d_P, size*sizeof(float), cudaMemcpyDeviceToHost);
// Finalize storage
cudaFree(d_N);
cudaFree(d_P);
cout << "Closing..." << endl;
return 0;
} | #include <cassert>
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <vector>
using namespace std;
#define TILE_SIZE 64
#define MAX_MASK_WIDTH 5
__constant__ float c_M[MAX_MASK_WIDTH];
__global__
void convolution1(const float* N, const float* M, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width/2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j]*M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution2(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width / 2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution3(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float Nds[TILE_SIZE + MAX_MASK_WIDTH - 1];
// load N from global memory into shared memory
int n = mask_width/2;
if (threadIdx.x >= blockDim.x - n) {
int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x;
Nds[threadIdx.x - (blockDim.x - n)] = (halo_index_left < 0) ? 0 : N[halo_index_left];
}
Nds[n + threadIdx.x] = N[i];
if (threadIdx.x < n) {
int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x;
Nds[n + blockDim.x + threadIdx.x] = (halo_index_right >= width) ? 0 : N[halo_index_right];
}
__syncthreads();
float Pvalue = 0.0f;
for (int j = 0; j < mask_width; ++j) {
Pvalue += Nds[threadIdx.x + j]*c_M[j];
}
P[i] = Pvalue;
}
int main(int argc, char* argv[])
{
// Query GPU properties
hipDeviceProp_t dev_prop;
hipGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int size = atoi(argv[1]);
// creating vector on host side
vector<float> h_N(size, 1.0f);
std::iota(h_N.begin(), h_N.end(), 0.0f);
// Copy vector on device side
float* d_N;
hipMalloc((void**)&d_N, size*sizeof(float));
hipMemcpy((void*)d_N, (void*)h_N.data(), size*sizeof(float), hipMemcpyHostToDevice);
// Create mask and send to devide
vector<float> h_M = { 1.0f, 1.0f, 2.0f, 1.0f, 1.0f };
int mask_width = h_M.size();
assert(mask_width < MAX_MASK_WIDTH);
hipMemcpyToSymbol(HIP_SYMBOL(c_M), (void*)h_M.data(), mask_width*sizeof(float));
// Allocate space for solution on device
float* d_P;
hipMalloc((void**)&d_P, size*sizeof(float));
// call Kernel
int blockDim = TILE_SIZE;
int gridDim = ceil(size/(float)blockDim);
int version = atoi(argv[2]);
if(version == 1)
convolution2<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else if(version == 2)
convolution3<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else
cout << "Wrong inputs!" << endl;
// Recover vector from device to host
vector<float> h_P(size);
hipMemcpy((void*)h_P.data(), (void*)d_P, size*sizeof(float), hipMemcpyDeviceToHost);
// Finalize storage
hipFree(d_N);
hipFree(d_P);
cout << "Closing..." << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cassert>
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <vector>
using namespace std;
#define TILE_SIZE 64
#define MAX_MASK_WIDTH 5
__constant__ float c_M[MAX_MASK_WIDTH];
__global__
void convolution1(const float* N, const float* M, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width/2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j]*M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution2(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width / 2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution3(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float Nds[TILE_SIZE + MAX_MASK_WIDTH - 1];
// load N from global memory into shared memory
int n = mask_width/2;
if (threadIdx.x >= blockDim.x - n) {
int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x;
Nds[threadIdx.x - (blockDim.x - n)] = (halo_index_left < 0) ? 0 : N[halo_index_left];
}
Nds[n + threadIdx.x] = N[i];
if (threadIdx.x < n) {
int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x;
Nds[n + blockDim.x + threadIdx.x] = (halo_index_right >= width) ? 0 : N[halo_index_right];
}
__syncthreads();
float Pvalue = 0.0f;
for (int j = 0; j < mask_width; ++j) {
Pvalue += Nds[threadIdx.x + j]*c_M[j];
}
P[i] = Pvalue;
}
int main(int argc, char* argv[])
{
// Query GPU properties
hipDeviceProp_t dev_prop;
hipGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int size = atoi(argv[1]);
// creating vector on host side
vector<float> h_N(size, 1.0f);
std::iota(h_N.begin(), h_N.end(), 0.0f);
// Copy vector on device side
float* d_N;
hipMalloc((void**)&d_N, size*sizeof(float));
hipMemcpy((void*)d_N, (void*)h_N.data(), size*sizeof(float), hipMemcpyHostToDevice);
// Create mask and send to devide
vector<float> h_M = { 1.0f, 1.0f, 2.0f, 1.0f, 1.0f };
int mask_width = h_M.size();
assert(mask_width < MAX_MASK_WIDTH);
hipMemcpyToSymbol(HIP_SYMBOL(c_M), (void*)h_M.data(), mask_width*sizeof(float));
// Allocate space for solution on device
float* d_P;
hipMalloc((void**)&d_P, size*sizeof(float));
// call Kernel
int blockDim = TILE_SIZE;
int gridDim = ceil(size/(float)blockDim);
int version = atoi(argv[2]);
if(version == 1)
convolution2<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else if(version == 2)
convolution3<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else
cout << "Wrong inputs!" << endl;
// Recover vector from device to host
vector<float> h_P(size);
hipMemcpy((void*)h_P.data(), (void*)d_P, size*sizeof(float), hipMemcpyDeviceToHost);
// Finalize storage
hipFree(d_N);
hipFree(d_P);
cout << "Closing..." << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12convolution1PKfS0_Pfii
.globl _Z12convolution1PKfS0_Pfii
.p2align 8
.type _Z12convolution1PKfS0_Pfii,@function
_Z12convolution1PKfS0_Pfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lt_i32 s3, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x1c
s_lshr_b32 s2, s3, 31
v_mov_b32_e32 v3, 0
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 1
v_subrev_nc_u32_e32 v2, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v0, v3
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s3, s3, -1
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s8, v2
s_and_b32 s9, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_load_b32 s9, s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s9, v4
s_branch .LBB0_2
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12convolution1PKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12convolution1PKfS0_Pfii, .Lfunc_end0-_Z12convolution1PKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12convolution2PKfPfii
.globl _Z12convolution2PKfPfii
.p2align 8
.type _Z12convolution2PKfPfii,@function
_Z12convolution2PKfPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lt_i32 s3, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_cbranch_scc1 .LBB1_5
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x14
s_lshr_b32 s2, s3, 31
v_mov_b32_e32 v3, 0
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 1
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, c_M@rel32@lo+4
s_addc_u32 s7, s7, c_M@rel32@hi+12
v_subrev_nc_u32_e32 v2, s2, v1
v_mov_b32_e32 v0, v3
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s3, s3, -1
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB1_6
.LBB1_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s8, v2
s_and_b32 s9, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB1_2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_load_b32 s9, s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s9, v4
s_branch .LBB1_2
.LBB1_5:
v_mov_b32_e32 v0, 0
.LBB1_6:
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12convolution2PKfPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12convolution2PKfPfii, .Lfunc_end1-_Z12convolution2PKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12convolution3PKfPfii
.globl _Z12convolution3PKfPfii
.p2align 8
.type _Z12convolution3PKfPfii,@function
_Z12convolution3PKfPfii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s4, 31
s_and_b32 s5, s5, 0xffff
s_add_i32 s6, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s6, 1
s_sub_i32 s7, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s7, v0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB2_4
s_add_i32 s8, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s8, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s8, exec_lo
v_cmpx_lt_i32_e32 -1, v1
s_cbranch_execz .LBB2_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s5, v1
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s7
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_add_lshl_u32 v4, s6, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB2_8
s_load_b32 s8, s[0:1], 0x14
s_add_i32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
v_mov_b32_e32 v4, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v3
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB2_7
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v4, v[3:4], off
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_add_lshl_u32 v3, s5, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_i32 s4, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_11
v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v3, 2, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, c_M@rel32@lo+4
s_addc_u32 s3, s3, c_M@rel32@hi+12
.LBB2_10:
ds_load_b32 v4, v3
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, -1
v_add_nc_u32_e32 v3, 4, v3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v4
s_cbranch_scc0 .LBB2_10
s_branch .LBB2_12
.LBB2_11:
v_mov_b32_e32 v0, 0
.LBB2_12:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12convolution3PKfPfii
.amdhsa_group_segment_fixed_size 272
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z12convolution3PKfPfii, .Lfunc_end2-_Z12convolution3PKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_M
.type c_M,@object
.section .bss,"aw",@nobits
.globl c_M
.p2align 4, 0x0
c_M:
.zero 20
.size c_M, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_M
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12convolution1PKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12convolution1PKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12convolution2PKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12convolution2PKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 272
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12convolution3PKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12convolution3PKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cassert>
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <vector>
using namespace std;
#define TILE_SIZE 64
#define MAX_MASK_WIDTH 5
__constant__ float c_M[MAX_MASK_WIDTH];
__global__
void convolution1(const float* N, const float* M, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width/2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j]*M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution2(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
float Pvalue = 0.0f;
int N_start_point = i - (mask_width / 2);
for (int j = 0; j < mask_width; ++j) {
if (N_start_point + j >= 0 && N_start_point + j < width) {
Pvalue += N[N_start_point + j] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__
void convolution3(const float* N, float* P, int mask_width, int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float Nds[TILE_SIZE + MAX_MASK_WIDTH - 1];
// load N from global memory into shared memory
int n = mask_width/2;
if (threadIdx.x >= blockDim.x - n) {
int halo_index_left = (blockIdx.x - 1)*blockDim.x + threadIdx.x;
Nds[threadIdx.x - (blockDim.x - n)] = (halo_index_left < 0) ? 0 : N[halo_index_left];
}
Nds[n + threadIdx.x] = N[i];
if (threadIdx.x < n) {
int halo_index_right = (blockIdx.x + 1)*blockDim.x + threadIdx.x;
Nds[n + blockDim.x + threadIdx.x] = (halo_index_right >= width) ? 0 : N[halo_index_right];
}
__syncthreads();
float Pvalue = 0.0f;
for (int j = 0; j < mask_width; ++j) {
Pvalue += Nds[threadIdx.x + j]*c_M[j];
}
P[i] = Pvalue;
}
int main(int argc, char* argv[])
{
// Query GPU properties
hipDeviceProp_t dev_prop;
hipGetDeviceProperties(&dev_prop, 0);
cout << "---------------------------------------------" << endl;
cout << " GPU PROPERTIES " << endl;
cout << "---------------------------------------------" << endl;
cout << "Device Name: " << dev_prop.name << endl;
cout << "Memory Clock Rate: " << dev_prop.memoryClockRate/1.0e6 << " GHz" << endl;
cout << "Memory Bandwidth: " << 2.0*dev_prop.memoryClockRate*(dev_prop.memoryBusWidth/8)/1.0e6 << " GB/s" << endl;
cout << "Number of SM: " << dev_prop.multiProcessorCount << endl;
cout << "Max Threads per SM: " << dev_prop.maxThreadsPerMultiProcessor << endl;
cout << "Registers per Block: " << dev_prop.regsPerBlock << endl;
cout << "Shared Memory per Block: " << dev_prop.sharedMemPerBlock << " B" << endl;
cout << "Total Global Memory per Block: " << dev_prop.totalGlobalMem/1.0e9 << " GB" << endl;
cout << endl;
int size = atoi(argv[1]);
// creating vector on host side
vector<float> h_N(size, 1.0f);
std::iota(h_N.begin(), h_N.end(), 0.0f);
// Copy vector on device side
float* d_N;
hipMalloc((void**)&d_N, size*sizeof(float));
hipMemcpy((void*)d_N, (void*)h_N.data(), size*sizeof(float), hipMemcpyHostToDevice);
// Create mask and send to devide
vector<float> h_M = { 1.0f, 1.0f, 2.0f, 1.0f, 1.0f };
int mask_width = h_M.size();
assert(mask_width < MAX_MASK_WIDTH);
hipMemcpyToSymbol(HIP_SYMBOL(c_M), (void*)h_M.data(), mask_width*sizeof(float));
// Allocate space for solution on device
float* d_P;
hipMalloc((void**)&d_P, size*sizeof(float));
// call Kernel
int blockDim = TILE_SIZE;
int gridDim = ceil(size/(float)blockDim);
int version = atoi(argv[2]);
if(version == 1)
convolution2<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else if(version == 2)
convolution3<<<gridDim, blockDim>>>(d_N, d_P, mask_width, size);
else
cout << "Wrong inputs!" << endl;
// Recover vector from device to host
vector<float> h_P(size);
hipMemcpy((void*)h_P.data(), (void*)d_P, size*sizeof(float), hipMemcpyDeviceToHost);
// Finalize storage
hipFree(d_N);
hipFree(d_P);
cout << "Closing..." << endl;
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__convolution1PKfS0_Pfii # -- Begin function _Z27__device_stub__convolution1PKfS0_Pfii
.p2align 4, 0x90
.type _Z27__device_stub__convolution1PKfS0_Pfii,@function
_Z27__device_stub__convolution1PKfS0_Pfii: # @_Z27__device_stub__convolution1PKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12convolution1PKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__convolution1PKfS0_Pfii, .Lfunc_end0-_Z27__device_stub__convolution1PKfS0_Pfii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__convolution2PKfPfii # -- Begin function _Z27__device_stub__convolution2PKfPfii
.p2align 4, 0x90
.type _Z27__device_stub__convolution2PKfPfii,@function
_Z27__device_stub__convolution2PKfPfii: # @_Z27__device_stub__convolution2PKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12convolution2PKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__convolution2PKfPfii, .Lfunc_end1-_Z27__device_stub__convolution2PKfPfii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__convolution3PKfPfii # -- Begin function _Z27__device_stub__convolution3PKfPfii
.p2align 4, 0x90
.type _Z27__device_stub__convolution3PKfPfii,@function
_Z27__device_stub__convolution3PKfPfii: # @_Z27__device_stub__convolution3PKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12convolution3PKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z27__device_stub__convolution3PKfPfii, .Lfunc_end2-_Z27__device_stub__convolution3PKfPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_3:
.quad 0x41cdcd6500000000 # double 1.0E+9
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI3_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_4:
.long 0x3f800000 # float 1
.LCPI3_5:
.long 0x3c800000 # float 0.015625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 1664
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_119
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB3_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB3_4
.LBB3_3:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_120
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i91
cmpb $0, 56(%r14)
je .LBB3_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB3_8
.LBB3_7:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit94
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_121
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i96
cmpb $0, 56(%r14)
je .LBB3_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB3_12
.LBB3_11:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit99
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %r14
movq %r14, %rdi
callq strlen
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_122
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i101
cmpb $0, 56(%r14)
je .LBB3_15
# %bb.14:
movzbl 67(%r14), %eax
jmp .LBB3_16
.LBB3_15:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit104
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2sdl 744(%rsp), %xmm0
divsd .LCPI3_0(%rip), %xmm0
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_123
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i106
cmpb $0, 56(%r15)
je .LBB3_19
# %bb.18:
movzbl 67(%r15), %eax
jmp .LBB3_20
.LBB3_19:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit109
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2sdl 744(%rsp), %xmm1
movl 748(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
addsd %xmm1, %xmm1
mulsd %xmm1, %xmm0
divsd .LCPI3_0(%rip), %xmm0
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_124
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i111
cmpb $0, 56(%r15)
je .LBB3_23
# %bb.22:
movzbl 67(%r15), %eax
jmp .LBB3_24
.LBB3_23:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit114
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 524(%rsp), %esi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB3_125
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i116
cmpb $0, 56(%r14)
je .LBB3_27
# %bb.26:
movzbl 67(%r14), %ecx
jmp .LBB3_28
.LBB3_27:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit119
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 760(%rsp), %esi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB3_126
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i121
cmpb $0, 56(%r14)
je .LBB3_31
# %bb.30:
movzbl 67(%r14), %ecx
jmp .LBB3_32
.LBB3_31:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit124
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 440(%rsp), %esi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB3_127
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i126
cmpb $0, 56(%r14)
je .LBB3_35
# %bb.34:
movzbl 67(%r14), %ecx
jmp .LBB3_36
.LBB3_35:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit129
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 432(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.11, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_128
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i131
cmpb $0, 56(%r15)
je .LBB3_39
# %bb.38:
movzbl 67(%r15), %eax
jmp .LBB3_40
.LBB3_39:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit134
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 424(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI3_1(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI3_2(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI3_3(%rip), %xmm0
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.13, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_129
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i136
cmpb $0, 56(%r15)
je .LBB3_43
# %bb.42:
movzbl 67(%r15), %eax
jmp .LBB3_44
.LBB3_43:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit139
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_130
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i141
cmpb $0, 56(%r14)
je .LBB3_47
# %bb.46:
movzbl 67(%r14), %eax
jmp .LBB3_48
.LBB3_47:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit144
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%r12), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movslq %r13d, %r15
movq %r15, %rax
shrq $61, %rax
jne .LBB3_131
# %bb.49: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i
movq %r13, %rbp
shlq $32, %rbp
je .LBB3_50
# %bb.51: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i
movq %rbp, %rdi
sarq $30, %rdi
.cfi_escape 0x2e, 0x00
callq _Znwm
movq %rax, %r14
jmp .LBB3_52
.LBB3_50:
xorl %r14d, %r14d
.LBB3_52: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movq %r14, %rax
testq %rbp, %rbp
je .LBB3_55
# %bb.53: # %.lr.ph.i.i.i.i.i.i.i.i.i.preheader
leaq (%r14,%r15,4), %rax
shlq $2, %r15
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_54: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rcx) # imm = 0x3F800000
addq $4, %rcx
cmpq %rcx, %r15
jne .LBB3_54
.LBB3_55: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit
movq %r12, %r15
cmpq %rax, %r14
je .LBB3_58
# %bb.56: # %.lr.ph.i.preheader
xorpd %xmm0, %xmm0
movss .LCPI3_4(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %r14, %rcx
.p2align 4, 0x90
.LBB3_57: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rcx)
addss %xmm1, %xmm0
addq $4, %rcx
cmpq %rax, %rcx
jne .LBB3_57
.LBB3_58: # %_ZSt4iotaIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEEfEvT_S7_T0_.exit
movq %rbp, %r12
sarq $30, %r12
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp1:
# %bb.59:
movq 16(%rsp), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp3:
# %bb.60:
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl $20, %edi
callq _Znwm
.Ltmp6:
# %bb.61: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit
movq %rax, %rbx
movups .Lconstinit(%rip), %xmm0
movups %xmm0, (%rax)
movl $1065353216, 16(%rax) # imm = 0x3F800000
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $c_M, %edi
movl $20, %edx
movq %rax, %rsi
xorl %ecx, %ecx
movl $1, %r8d
movq %rax, 88(%rsp) # 8-byte Spill
callq hipMemcpyToSymbol
.Ltmp9:
# %bb.62: # %_Z17hipMemcpyToSymbolIA5_fE10hipError_tRKT_PKvmm13hipMemcpyKind.exit
.Ltmp11:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp12:
# %bb.63:
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
mulss .LCPI3_5(%rip), %xmm0
.cfi_escape 0x2e, 0x00
callq ceilf@PLT
cvttss2si %xmm0, %ebx
movq 16(%r15), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $2, %eax
je .LBB3_73
# %bb.64:
cmpl $1, %eax
jne .LBB3_77
# %bb.65:
movl %ebx, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
.Ltmp20:
.cfi_escape 0x2e, 0x00
movabsq $4294967360, %rdx # imm = 0x100000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp21:
# %bb.66:
testl %eax, %eax
jne .LBB3_87
# %bb.67:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $5, 4(%rsp)
movl %r13d, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp23:
# %bb.68: # %.noexc51
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp24:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z12convolution2PKfPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp25:
jmp .LBB3_87
.LBB3_73:
movl %ebx, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movabsq $4294967360, %rdx # imm = 0x100000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp15:
# %bb.74:
testl %eax, %eax
jne .LBB3_87
# %bb.75:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $5, 4(%rsp)
movl %r13d, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp17:
# %bb.76: # %.noexc59
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp18:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z12convolution3PKfPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp19:
jmp .LBB3_87
.LBB3_77:
.Ltmp26:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp27:
# %bb.78: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_79
# %bb.81: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i146
cmpb $0, 56(%rbx)
je .LBB3_83
# %bb.82:
movzbl 67(%rbx), %eax
jmp .LBB3_85
.LBB3_83:
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp29:
# %bb.84: # %.noexc150
movq (%rbx), %rax
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp31:
.LBB3_85: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp32:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp33:
# %bb.86: # %.noexc152
.Ltmp34:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp35:
.LBB3_87: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i63
testq %rbp, %rbp
je .LBB3_88
# %bb.89: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i65
.Ltmp36:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Znwm
.Ltmp37:
# %bb.90:
movq %rax, %rbx
testq %rbp, %rbp
jne .LBB3_92
jmp .LBB3_94
.LBB3_88:
xorl %ebx, %ebx
testq %rbp, %rbp
je .LBB3_94
.LBB3_92:
movl $0, (%rbx)
movabsq $4294967296, %rax # imm = 0x100000000
cmpq %rax, %rbp
je .LBB3_94
# %bb.93: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i.i.i
leaq 4(%rbx), %rdi
leaq -4(%r12), %rdx
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq memset@PLT
.LBB3_94: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit
movq 8(%rsp), %rsi
.Ltmp39:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp40:
# %bb.95:
movq 16(%rsp), %rdi
.Ltmp41:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp42:
# %bb.96:
movq 8(%rsp), %rdi
.Ltmp43:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp44:
# %bb.97:
.Ltmp45:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp46:
# %bb.98: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit70
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_99
# %bb.101: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i156
cmpb $0, 56(%r12)
je .LBB3_103
# %bb.102:
movzbl 67(%r12), %eax
jmp .LBB3_105
.LBB3_103:
.Ltmp47:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp48:
# %bb.104: # %.noexc161
movq (%r12), %rax
.Ltmp49:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp50:
.LBB3_105: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i158
.Ltmp51:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp52:
# %bb.106: # %.noexc163
.Ltmp53:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp54:
# %bb.107: # %_ZNSolsEPFRSoS_E.exit72
testq %rbx, %rbx
je .LBB3_109
# %bb.108:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB3_109: # %_ZNSt6vectorIfSaIfEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq 88(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
testq %r14, %r14
je .LBB3_111
# %bb.110:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB3_111: # %_ZNSt6vectorIfSaIfEED2Ev.exit79
xorl %eax, %eax
addq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_119:
.cfi_def_cfa_offset 1664
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_120:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_121:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_122:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_123:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_124:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_125:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_126:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_127:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_128:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_129:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_130:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB3_131: # %.noexc
.cfi_escape 0x2e, 0x00
movl $.L.str.16, %edi
callq _ZSt20__throw_length_errorPKc
.LBB3_99:
.Ltmp55:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp56:
# %bb.100: # %.noexc160
.LBB3_79:
.Ltmp58:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp59:
# %bb.80: # %.noexc149
.LBB3_112:
.Ltmp38:
movq %rax, %r12
jmp .LBB3_115
.LBB3_71:
.Ltmp13:
movq %rax, %r12
jmp .LBB3_115
.LBB3_70:
.Ltmp10:
movq %rax, %r12
jmp .LBB3_115
.LBB3_132: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit.i
.Ltmp7:
movq %rax, %r12
jmp .LBB3_116
.LBB3_69:
.Ltmp4:
movq %rax, %r12
jmp .LBB3_116
.LBB3_72:
.Ltmp60:
movq %rax, %r12
jmp .LBB3_115
.LBB3_113:
.Ltmp57:
movq %rax, %r12
testq %rbx, %rbx
je .LBB3_115
# %bb.114:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB3_115: # %_ZNSt6vectorIfSaIfEED2Ev.exit85
.cfi_escape 0x2e, 0x00
movq 88(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.LBB3_116:
testq %r14, %r14
je .LBB3_118
# %bb.117:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB3_118: # %_ZNSt6vectorIfSaIfEED2Ev.exit88
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp20-.Ltmp12 # Call between .Ltmp12 and .Ltmp20
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp35-.Ltmp20 # Call between .Ltmp20 and .Ltmp35
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp39-.Ltmp37 # Call between .Ltmp37 and .Ltmp39
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp54-.Ltmp39 # Call between .Ltmp39 and .Ltmp54
.uleb128 .Ltmp57-.Lfunc_begin0 # jumps to .Ltmp57
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp55-.Ltmp54 # Call between .Ltmp54 and .Ltmp55
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp55-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp56-.Ltmp55 # Call between .Ltmp55 and .Ltmp56
.uleb128 .Ltmp57-.Lfunc_begin0 # jumps to .Ltmp57
.byte 0 # On action: cleanup
.uleb128 .Ltmp58-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp59-.Ltmp58 # Call between .Ltmp58 and .Ltmp59
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Lfunc_end3-.Ltmp59 # Call between .Ltmp59 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12convolution1PKfS0_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12convolution2PKfPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12convolution3PKfPfii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_M, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_M,@object # @c_M
.local c_M
.comm c_M,20,16
.type _Z12convolution1PKfS0_Pfii,@object # @_Z12convolution1PKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z12convolution1PKfS0_Pfii
.p2align 3, 0x0
_Z12convolution1PKfS0_Pfii:
.quad _Z27__device_stub__convolution1PKfS0_Pfii
.size _Z12convolution1PKfS0_Pfii, 8
.type _Z12convolution2PKfPfii,@object # @_Z12convolution2PKfPfii
.globl _Z12convolution2PKfPfii
.p2align 3, 0x0
_Z12convolution2PKfPfii:
.quad _Z27__device_stub__convolution2PKfPfii
.size _Z12convolution2PKfPfii, 8
.type _Z12convolution3PKfPfii,@object # @_Z12convolution3PKfPfii
.globl _Z12convolution3PKfPfii
.p2align 3, 0x0
_Z12convolution3PKfPfii:
.quad _Z27__device_stub__convolution3PKfPfii
.size _Z12convolution3PKfPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "---------------------------------------------"
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " GPU PROPERTIES "
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device Name: "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Memory Clock Rate: "
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " GHz"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Memory Bandwidth: "
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " GB/s"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Number of SM: "
.size .L.str.7, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Max Threads per SM: "
.size .L.str.8, 21
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Registers per Block: "
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Shared Memory per Block: "
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " B"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total Global Memory per Block: "
.size .L.str.12, 32
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " GB"
.size .L.str.13, 4
.type .Lconstinit,@object # @constinit
.section .rodata,"a",@progbits
.p2align 2, 0x0
.Lconstinit:
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.size .Lconstinit, 20
.type .L.str.14,@object # @.str.14
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.14:
.asciz "Wrong inputs!"
.size .L.str.14, 14
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Closing..."
.size .L.str.15, 11
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "cannot create std::vector larger than max_size()"
.size .L.str.16, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12convolution1PKfS0_Pfii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12convolution2PKfPfii"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12convolution3PKfPfii"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "c_M"
.size .L__unnamed_4, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__convolution1PKfS0_Pfii
.addrsig_sym _Z27__device_stub__convolution2PKfPfii
.addrsig_sym _Z27__device_stub__convolution3PKfPfii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym c_M
.addrsig_sym _Z12convolution1PKfS0_Pfii
.addrsig_sym _Z12convolution2PKfPfii
.addrsig_sym _Z12convolution3PKfPfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void g_One_Bgrad(float* _delta, float* bgrad, int rows, int cols, int channels)
{
extern __shared__ float _sum[];
int channel = blockIdx.x;
int col = blockIdx.y;
int row = threadIdx.x;
float delta = _delta[channel * rows * cols + row * cols + col];
_sum[row] = delta;
__syncthreads();
int len = rows;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
if(threadIdx.x == 0)
{
bgrad[channel * cols + col] = _sum[0] / rows;
}
} | code for sm_80
Function : _Z11g_One_BgradPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e280000002100 */
/*0050*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R5, R3, c[0x0][0x170], R7 ; /* 0x00005c0003057a24 */
/* 0x001fc800078e0207 */
/*0070*/ IMAD R5, R5, c[0x0][0x174], R0 ; /* 0x00005d0005057a24 */
/* 0x002fc800078e0200 */
/*0080*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0204 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*00c0*/ ISETP.NE.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f25270 */
/*00d0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x0041e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00f0*/ @!P1 BRA 0x200 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.SHL.U32 R2, R7, 0x4, RZ ; /* 0x0000000407027824 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fca00078e00ff */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fe20000011404 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0140*/ ISETP.GE.U32.AND P1, PT, R7, R5, PT ; /* 0x000000050700720c */
/* 0x000fda0003f26070 */
/*0150*/ @!P1 LEA R5, R4.reuse, 0x2, 0x1 ; /* 0x0000000204059811 */
/* 0x040fe400078e08ff */
/*0160*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0170*/ @!P1 LOP3.LUT R5, R5, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc05059812 */
/* 0x000fe400078ec0ff */
/*0180*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fe20000011404 */
/*0190*/ @!P1 LDS R6, [R7.X4] ; /* 0x0000000007069984 */
/* 0x000fe40000004800 */
/*01a0*/ @!P1 IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102059824 */
/* 0x000fcc00078e0205 */
/*01b0*/ @!P1 LDS R5, [R5] ; /* 0x0000000005059984 */
/* 0x000e240000000800 */
/*01c0*/ @!P1 FADD R6, R6, R5 ; /* 0x0000000506069221 */
/* 0x001fca0000000000 */
/*01d0*/ @!P1 STS [R7.X4], R6 ; /* 0x0000000607009388 */
/* 0x0001e20000004800 */
/*01e0*/ ISETP.NE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f25270 */
/*01f0*/ @P1 BRA 0x120 ; /* 0xffffff2000001947 */
/* 0x001fea000383ffff */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e220000000800 */
/*0230*/ I2F R5, c[0x0][0x170] ; /* 0x00005c0000057b06 */
/* 0x000e700000201400 */
/*0240*/ MUFU.RCP R2, R5 ; /* 0x0000000500027308 */
/* 0x002e640000001000 */
/*0250*/ FFMA R7, -R5, R2, 1 ; /* 0x3f80000005077423 */
/* 0x002fc80000000102 */
/*0260*/ FFMA R7, R2, R7, R2 ; /* 0x0000000702077223 */
/* 0x000fe40000000002 */
/*0270*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x001e240000000000 */
/*0280*/ FFMA R2, R4, R7, RZ ; /* 0x0000000704027223 */
/* 0x000fc800000000ff */
/*0290*/ FFMA R6, -R5, R2, R4 ; /* 0x0000000205067223 */
/* 0x000fc80000000104 */
/*02a0*/ FFMA R7, R7, R6, R2 ; /* 0x0000000607077223 */
/* 0x000fe20000000002 */
/*02b0*/ @!P0 BRA 0x2e0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*02c0*/ MOV R2, 0x2e0 ; /* 0x000002e000027802 */
/* 0x000fe40000000f00 */
/*02d0*/ CALL.REL.NOINC 0x330 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*0300*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0310*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ SHF.R.U32.HI R7, RZ, 0x17, R5.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011605 */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, R4.reuse ; /* 0x000000ffff087224 */
/* 0x100fe200078e0004 */
/*0350*/ SHF.R.U32.HI R6, RZ, 0x17, R4 ; /* 0x00000017ff067819 */
/* 0x000fe20000011604 */
/*0360*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0370*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe400078ec0ff */
/*0380*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0390*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc40007ffe0ff */
/*03b0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*03c0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*03d0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*03e0*/ @!P0 BRA 0x560 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*03f0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0400*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0410*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0420*/ @P0 BRA 0x940 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0430*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0440*/ @!P0 BRA 0x920 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0450*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0460*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0470*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0480*/ @!P1 BRA !P2, 0x920 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0490*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*04a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*04b0*/ @P1 BRA 0x900 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*04c0*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*04d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04e0*/ @P0 BRA 0x8d0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*04f0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0500*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0510*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0520*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0530*/ @!P0 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004088823 */
/* 0x000fe400000000ff */
/*0540*/ @!P1 FFMA R9, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005099823 */
/* 0x000fe200000000ff */
/*0550*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0560*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe400078eb8ff */
/*0570*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0580*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*0590*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*05a0*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*05b0*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*05c0*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*05d0*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*05e0*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*05f0*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0600*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*0610*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*0620*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*0630*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*0640*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*0650*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0660*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0670*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0680*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0690*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*06a0*/ @!P0 BRA 0x8b0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*06b0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*06c0*/ @P0 BRA 0x880 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*06e0*/ @P0 BRA 0x950 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0700*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0710*/ @!P0 BRA 0x950 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0720*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0730*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0740*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0750*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0760*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0770*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0780*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0790*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*07a0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*07b0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*07c0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*07d0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*07e0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*07f0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0800*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0810*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0820*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0830*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0840*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0850*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0860*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0870*/ BRA 0x950 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0890*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*08a0*/ BRA 0x950 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*08b0*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe200078e0204 */
/*08c0*/ BRA 0x950 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08d0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*08e0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*08f0*/ BRA 0x950 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*0910*/ BRA 0x950 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0920*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0930*/ BRA 0x950 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0940*/ FADD.FTZ R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x000fc80000010000 */
/*0950*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0970*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0980*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff67004007950 */
/* 0x000fea0003c3ffff */
/*0990*/ BRA 0x990; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void g_One_Bgrad(float* _delta, float* bgrad, int rows, int cols, int channels)
{
extern __shared__ float _sum[];
int channel = blockIdx.x;
int col = blockIdx.y;
int row = threadIdx.x;
float delta = _delta[channel * rows * cols + row * cols + col];
_sum[row] = delta;
__syncthreads();
int len = rows;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
if(threadIdx.x == 0)
{
bgrad[channel * cols + col] = _sum[0] / rows;
}
} | .file "tmpxft_00153560_00000000-6_g_One_Bgrad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii
.type _Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii, @function
_Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11g_One_BgradPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii, .-_Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii
.globl _Z11g_One_BgradPfS_iii
.type _Z11g_One_BgradPfS_iii, @function
_Z11g_One_BgradPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11g_One_BgradPfS_iii, .-_Z11g_One_BgradPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11g_One_BgradPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11g_One_BgradPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void g_One_Bgrad(float* _delta, float* bgrad, int rows, int cols, int channels)
{
extern __shared__ float _sum[];
int channel = blockIdx.x;
int col = blockIdx.y;
int row = threadIdx.x;
float delta = _delta[channel * rows * cols + row * cols + col];
_sum[row] = delta;
__syncthreads();
int len = rows;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
if(threadIdx.x == 0)
{
bgrad[channel * cols + col] = _sum[0] / rows;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void g_One_Bgrad(float* _delta, float* bgrad, int rows, int cols, int channels)
{
extern __shared__ float _sum[];
int channel = blockIdx.x;
int col = blockIdx.y;
int row = threadIdx.x;
float delta = _delta[channel * rows * cols + row * cols + col];
_sum[row] = delta;
__syncthreads();
int len = rows;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
if(threadIdx.x == 0)
{
bgrad[channel * cols + col] = _sum[0] / rows;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void g_One_Bgrad(float* _delta, float* bgrad, int rows, int cols, int channels)
{
extern __shared__ float _sum[];
int channel = blockIdx.x;
int col = blockIdx.y;
int row = threadIdx.x;
float delta = _delta[channel * rows * cols + row * cols + col];
_sum[row] = delta;
__syncthreads();
int len = rows;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
if(threadIdx.x == 0)
{
bgrad[channel * cols + col] = _sum[0] / rows;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11g_One_BgradPfS_iii
.globl _Z11g_One_BgradPfS_iii
.p2align 8
.type _Z11g_One_BgradPfS_iii,@function
_Z11g_One_BgradPfS_iii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s14, s4, v[0:1]
s_cmp_eq_u32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s5, s[2:3]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_mov_b32 s3, s4
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lg_u32 s3, 1
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_ashr_i32 s6, s3, 1
s_add_i32 s3, s3, 1
v_cmp_gt_u32_e32 vcc_lo, s6, v0
s_ashr_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
v_cvt_f32_i32_e32 v1, s4
s_load_b64 s[0:1], s[0:1], 0x8
s_mul_i32 s3, s14, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s3, s2
ds_load_b32 v0, v0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_div_scale_f32 v2, null, v1, v1, v0
v_div_scale_f32 v5, vcc_lo, v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v5, v3
v_fma_f32 v6, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v3
v_fma_f32 v2, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v4
v_div_fixup_f32 v0, v2, v1, v0
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11g_One_BgradPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11g_One_BgradPfS_iii, .Lfunc_end0-_Z11g_One_BgradPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11g_One_BgradPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11g_One_BgradPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void g_One_Bgrad(float* _delta, float* bgrad, int rows, int cols, int channels)
{
extern __shared__ float _sum[];
int channel = blockIdx.x;
int col = blockIdx.y;
int row = threadIdx.x;
float delta = _delta[channel * rows * cols + row * cols + col];
_sum[row] = delta;
__syncthreads();
int len = rows;
while(len != 1)
{
__syncthreads();
int skip = (len + 1) >> 1;
if(threadIdx.x < (len >> 1))
{
_sum[threadIdx.x] += _sum[threadIdx.x + skip];
}
len = (len + 1) >> 1;
}
__syncthreads();
if(threadIdx.x == 0)
{
bgrad[channel * cols + col] = _sum[0] / rows;
}
} | .text
.file "g_One_Bgrad.hip"
.globl _Z26__device_stub__g_One_BgradPfS_iii # -- Begin function _Z26__device_stub__g_One_BgradPfS_iii
.p2align 4, 0x90
.type _Z26__device_stub__g_One_BgradPfS_iii,@function
_Z26__device_stub__g_One_BgradPfS_iii: # @_Z26__device_stub__g_One_BgradPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11g_One_BgradPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__g_One_BgradPfS_iii, .Lfunc_end0-_Z26__device_stub__g_One_BgradPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11g_One_BgradPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11g_One_BgradPfS_iii,@object # @_Z11g_One_BgradPfS_iii
.section .rodata,"a",@progbits
.globl _Z11g_One_BgradPfS_iii
.p2align 3, 0x0
_Z11g_One_BgradPfS_iii:
.quad _Z26__device_stub__g_One_BgradPfS_iii
.size _Z11g_One_BgradPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11g_One_BgradPfS_iii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__g_One_BgradPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11g_One_BgradPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11g_One_BgradPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e280000002100 */
/*0050*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002600 */
/*0060*/ IMAD R5, R3, c[0x0][0x170], R7 ; /* 0x00005c0003057a24 */
/* 0x001fc800078e0207 */
/*0070*/ IMAD R5, R5, c[0x0][0x174], R0 ; /* 0x00005d0005057a24 */
/* 0x002fc800078e0200 */
/*0080*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0204 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*00c0*/ ISETP.NE.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f25270 */
/*00d0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x0041e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00f0*/ @!P1 BRA 0x200 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.SHL.U32 R2, R7, 0x4, RZ ; /* 0x0000000407027824 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fca00078e00ff */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fe20000011404 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0140*/ ISETP.GE.U32.AND P1, PT, R7, R5, PT ; /* 0x000000050700720c */
/* 0x000fda0003f26070 */
/*0150*/ @!P1 LEA R5, R4.reuse, 0x2, 0x1 ; /* 0x0000000204059811 */
/* 0x040fe400078e08ff */
/*0160*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0170*/ @!P1 LOP3.LUT R5, R5, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc05059812 */
/* 0x000fe400078ec0ff */
/*0180*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fe20000011404 */
/*0190*/ @!P1 LDS R6, [R7.X4] ; /* 0x0000000007069984 */
/* 0x000fe40000004800 */
/*01a0*/ @!P1 IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102059824 */
/* 0x000fcc00078e0205 */
/*01b0*/ @!P1 LDS R5, [R5] ; /* 0x0000000005059984 */
/* 0x000e240000000800 */
/*01c0*/ @!P1 FADD R6, R6, R5 ; /* 0x0000000506069221 */
/* 0x001fca0000000000 */
/*01d0*/ @!P1 STS [R7.X4], R6 ; /* 0x0000000607009388 */
/* 0x0001e20000004800 */
/*01e0*/ ISETP.NE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f25270 */
/*01f0*/ @P1 BRA 0x120 ; /* 0xffffff2000001947 */
/* 0x001fea000383ffff */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ LDS R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e220000000800 */
/*0230*/ I2F R5, c[0x0][0x170] ; /* 0x00005c0000057b06 */
/* 0x000e700000201400 */
/*0240*/ MUFU.RCP R2, R5 ; /* 0x0000000500027308 */
/* 0x002e640000001000 */
/*0250*/ FFMA R7, -R5, R2, 1 ; /* 0x3f80000005077423 */
/* 0x002fc80000000102 */
/*0260*/ FFMA R7, R2, R7, R2 ; /* 0x0000000702077223 */
/* 0x000fe40000000002 */
/*0270*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x001e240000000000 */
/*0280*/ FFMA R2, R4, R7, RZ ; /* 0x0000000704027223 */
/* 0x000fc800000000ff */
/*0290*/ FFMA R6, -R5, R2, R4 ; /* 0x0000000205067223 */
/* 0x000fc80000000104 */
/*02a0*/ FFMA R7, R7, R6, R2 ; /* 0x0000000607077223 */
/* 0x000fe20000000002 */
/*02b0*/ @!P0 BRA 0x2e0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*02c0*/ MOV R2, 0x2e0 ; /* 0x000002e000027802 */
/* 0x000fe40000000f00 */
/*02d0*/ CALL.REL.NOINC 0x330 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fc800078e0200 */
/*0300*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0310*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ SHF.R.U32.HI R7, RZ, 0x17, R5.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011605 */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, R4.reuse ; /* 0x000000ffff087224 */
/* 0x100fe200078e0004 */
/*0350*/ SHF.R.U32.HI R6, RZ, 0x17, R4 ; /* 0x00000017ff067819 */
/* 0x000fe20000011604 */
/*0360*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0370*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe400078ec0ff */
/*0380*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0390*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc40007ffe0ff */
/*03b0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*03c0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*03d0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*03e0*/ @!P0 BRA 0x560 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*03f0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0400*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0410*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0420*/ @P0 BRA 0x940 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0430*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0440*/ @!P0 BRA 0x920 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0450*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0460*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0470*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0480*/ @!P1 BRA !P2, 0x920 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0490*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*04a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*04b0*/ @P1 BRA 0x900 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*04c0*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*04d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04e0*/ @P0 BRA 0x8d0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*04f0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0500*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0510*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0520*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0530*/ @!P0 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004088823 */
/* 0x000fe400000000ff */
/*0540*/ @!P1 FFMA R9, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005099823 */
/* 0x000fe200000000ff */
/*0550*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0560*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe400078eb8ff */
/*0570*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0580*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*0590*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*05a0*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*05b0*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*05c0*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*05d0*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*05e0*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*05f0*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0600*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*0610*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*0620*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*0630*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*0640*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*0650*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0660*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0670*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*0680*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0690*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*06a0*/ @!P0 BRA 0x8b0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*06b0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*06c0*/ @P0 BRA 0x880 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*06e0*/ @P0 BRA 0x950 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0700*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0710*/ @!P0 BRA 0x950 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0720*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0730*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0740*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0750*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0760*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0770*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*0780*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0790*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*07a0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*07b0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*07c0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*07d0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*07e0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*07f0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0800*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0810*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0820*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0830*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0840*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0850*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0860*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0870*/ BRA 0x950 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0890*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*08a0*/ BRA 0x950 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*08b0*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe200078e0204 */
/*08c0*/ BRA 0x950 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08d0*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*08e0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*08f0*/ BRA 0x950 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*0910*/ BRA 0x950 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0920*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0930*/ BRA 0x950 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0940*/ FADD.FTZ R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x000fc80000010000 */
/*0950*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0970*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0980*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff67004007950 */
/* 0x000fea0003c3ffff */
/*0990*/ BRA 0x990; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11g_One_BgradPfS_iii
.globl _Z11g_One_BgradPfS_iii
.p2align 8
.type _Z11g_One_BgradPfS_iii,@function
_Z11g_One_BgradPfS_iii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s14, s4, v[0:1]
s_cmp_eq_u32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s5, s[2:3]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_mov_b32 s3, s4
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lg_u32 s3, 1
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_ashr_i32 s6, s3, 1
s_add_i32 s3, s3, 1
v_cmp_gt_u32_e32 vcc_lo, s6, v0
s_ashr_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
v_cvt_f32_i32_e32 v1, s4
s_load_b64 s[0:1], s[0:1], 0x8
s_mul_i32 s3, s14, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s3, s2
ds_load_b32 v0, v0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_div_scale_f32 v2, null, v1, v1, v0
v_div_scale_f32 v5, vcc_lo, v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v5, v3
v_fma_f32 v6, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v3
v_fma_f32 v2, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v4
v_div_fixup_f32 v0, v2, v1, v0
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11g_One_BgradPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11g_One_BgradPfS_iii, .Lfunc_end0-_Z11g_One_BgradPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11g_One_BgradPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11g_One_BgradPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00153560_00000000-6_g_One_Bgrad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii
.type _Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii, @function
_Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11g_One_BgradPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii, .-_Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii
.globl _Z11g_One_BgradPfS_iii
.type _Z11g_One_BgradPfS_iii, @function
_Z11g_One_BgradPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11g_One_BgradPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11g_One_BgradPfS_iii, .-_Z11g_One_BgradPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11g_One_BgradPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11g_One_BgradPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "g_One_Bgrad.hip"
.globl _Z26__device_stub__g_One_BgradPfS_iii # -- Begin function _Z26__device_stub__g_One_BgradPfS_iii
.p2align 4, 0x90
.type _Z26__device_stub__g_One_BgradPfS_iii,@function
_Z26__device_stub__g_One_BgradPfS_iii: # @_Z26__device_stub__g_One_BgradPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11g_One_BgradPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__g_One_BgradPfS_iii, .Lfunc_end0-_Z26__device_stub__g_One_BgradPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11g_One_BgradPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11g_One_BgradPfS_iii,@object # @_Z11g_One_BgradPfS_iii
.section .rodata,"a",@progbits
.globl _Z11g_One_BgradPfS_iii
.p2align 3, 0x0
_Z11g_One_BgradPfS_iii:
.quad _Z26__device_stub__g_One_BgradPfS_iii
.size _Z11g_One_BgradPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11g_One_BgradPfS_iii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__g_One_BgradPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11g_One_BgradPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef _GENSPARSEMAT_
#define _GENSPARSEMAT_
void GenSparseMat(float *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : input vector / flattened matrix
sparseVec : sparse vector
idxVec : every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : number of non-zero elements in ith row
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < rows; ++i) {
nPost = 0;
for(j = 0; j < clms; ++j) {
if(conVec[i + clms * j]) { /* i --> j */
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
}
nPostNeurons[i] = nPost;
}
idxVec[0] = 0;
for(i = 1; i < rows; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
void GenSparseFeedForwardMat(float *conVec, int nff, int nNeurons, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : nff*nNeurons-by-1 - input vector / flattened matrix
sparseVec : - sparse vector
idxVec : nff-by-1 - every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : nff-by-1 - number of 2/3 neurons reciving connections from
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < nff; ++i) {
nPost = 0;
for(j = 0; j < nNeurons; ++j) {
if(conVec[i + j * nff]) {
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
nPostNeurons[i] = nPost;
}
}
idxVec[0] = 0;
for(i = 1; i < nff; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef _GENSPARSEMAT_
#define _GENSPARSEMAT_
void GenSparseMat(float *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : input vector / flattened matrix
sparseVec : sparse vector
idxVec : every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : number of non-zero elements in ith row
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < rows; ++i) {
nPost = 0;
for(j = 0; j < clms; ++j) {
if(conVec[i + clms * j]) { /* i --> j */
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
}
nPostNeurons[i] = nPost;
}
idxVec[0] = 0;
for(i = 1; i < rows; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
void GenSparseFeedForwardMat(float *conVec, int nff, int nNeurons, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : nff*nNeurons-by-1 - input vector / flattened matrix
sparseVec : - sparse vector
idxVec : nff-by-1 - every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : nff-by-1 - number of 2/3 neurons reciving connections from
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < nff; ++i) {
nPost = 0;
for(j = 0; j < nNeurons; ++j) {
if(conVec[i + j * nff]) {
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
nPostNeurons[i] = nPost;
}
}
idxVec[0] = 0;
for(i = 1; i < nff; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
#endif | .file "tmpxft_000afbb4_00000000-6_GenSparseMat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12GenSparseMatPfiiPiS0_S0_
.type _Z12GenSparseMatPfiiPiS0_S0_, @function
_Z12GenSparseMatPfiiPiS0_S0_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %r8, %rbx
movq %r9, %rbp
movslq %esi, %r9
testq %r9, %r9
je .L4
movq %rdi, %r12
movq %rcx, %r11
movslq %edx, %rdi
leaq 0(,%rdi,4), %r10
movl $0, %ecx
movl $0, %r8d
pxor %xmm0, %xmm0
jmp .L5
.L14:
movl %edx, (%r11,%rcx,4)
addq $1, %rcx
addq $1, %rsi
.L6:
addq $1, %rdx
addq %r10, %rax
cmpq %rdi, %rdx
je .L10
.L8:
ucomiss (%rax), %xmm0
jp .L14
je .L6
jmp .L14
.L10:
movl %esi, 0(%rbp,%r8,4)
addq $1, %r8
addq $4, %r12
cmpq %r9, %r8
je .L9
.L5:
movq %r12, %rax
movl $0, %esi
movl $0, %edx
testq %rdi, %rdi
jne .L8
movq %rdi, %rsi
jmp .L10
.L9:
movl $0, (%rbx)
cmpq $1, %r9
jbe .L3
movl $1, %eax
.L12:
movl -4(%rbp,%rax,4), %edx
addl -4(%rbx,%rax,4), %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq %r9, %rax
jne .L12
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movl $0, (%r8)
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z12GenSparseMatPfiiPiS0_S0_, .-_Z12GenSparseMatPfiiPiS0_S0_
.globl _Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.type _Z23GenSparseFeedForwardMatPfiiPiS0_S0_, @function
_Z23GenSparseFeedForwardMatPfiiPiS0_S0_:
.LFB2028:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %r8, %rbp
movslq %esi, %r8
testq %r8, %r8
je .L20
movq %rdi, %r13
movl %edx, %r12d
movq %rcx, %rbx
movq %r9, %rdi
leaq 0(,%r8,4), %r11
movl $0, %esi
movl $0, %r14d
movslq %edx, %r10
pxor %xmm0, %xmm0
jmp .L21
.L30:
movl %edx, (%rbx,%rsi,4)
addq $1, %rsi
addq $1, %rcx
.L22:
movl %ecx, (%rdi)
addq $1, %rdx
addq %r11, %rax
cmpq %r10, %rdx
je .L26
.L24:
ucomiss (%rax), %xmm0
jp .L30
je .L22
jmp .L30
.L26:
addq $1, %r14
addq $4, %rdi
addq $4, %r13
cmpq %r8, %r14
je .L25
.L21:
movq %r13, %rax
movl $0, %ecx
movl $0, %edx
testl %r12d, %r12d
jne .L24
jmp .L26
.L25:
movl $0, 0(%rbp)
cmpq $1, %r8
jbe .L19
movl $1, %eax
.L28:
movl -4(%r9,%rax,4), %edx
addl -4(%rbp,%rax,4), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %r8, %rax
jne .L28
.L19:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl $0, 0(%rbp)
jmp .L19
.cfi_endproc
.LFE2028:
.size _Z23GenSparseFeedForwardMatPfiiPiS0_S0_, .-_Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef _GENSPARSEMAT_
#define _GENSPARSEMAT_
void GenSparseMat(float *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : input vector / flattened matrix
sparseVec : sparse vector
idxVec : every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : number of non-zero elements in ith row
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < rows; ++i) {
nPost = 0;
for(j = 0; j < clms; ++j) {
if(conVec[i + clms * j]) { /* i --> j */
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
}
nPostNeurons[i] = nPost;
}
idxVec[0] = 0;
for(i = 1; i < rows; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
void GenSparseFeedForwardMat(float *conVec, int nff, int nNeurons, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : nff*nNeurons-by-1 - input vector / flattened matrix
sparseVec : - sparse vector
idxVec : nff-by-1 - every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : nff-by-1 - number of 2/3 neurons reciving connections from
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < nff; ++i) {
nPost = 0;
for(j = 0; j < nNeurons; ++j) {
if(conVec[i + j * nff]) {
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
nPostNeurons[i] = nPost;
}
}
idxVec[0] = 0;
for(i = 1; i < nff; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
#endif | #ifndef _GENSPARSEMAT_
#define _GENSPARSEMAT_
void GenSparseMat(float *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : input vector / flattened matrix
sparseVec : sparse vector
idxVec : every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : number of non-zero elements in ith row
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < rows; ++i) {
nPost = 0;
for(j = 0; j < clms; ++j) {
if(conVec[i + clms * j]) { /* i --> j */
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
}
nPostNeurons[i] = nPost;
}
idxVec[0] = 0;
for(i = 1; i < rows; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
void GenSparseFeedForwardMat(float *conVec, int nff, int nNeurons, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : nff*nNeurons-by-1 - input vector / flattened matrix
sparseVec : - sparse vector
idxVec : nff-by-1 - every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : nff-by-1 - number of 2/3 neurons reciving connections from
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < nff; ++i) {
nPost = 0;
for(j = 0; j < nNeurons; ++j) {
if(conVec[i + j * nff]) {
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
nPostNeurons[i] = nPost;
}
}
idxVec[0] = 0;
for(i = 1; i < nff; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef _GENSPARSEMAT_
#define _GENSPARSEMAT_
void GenSparseMat(float *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : input vector / flattened matrix
sparseVec : sparse vector
idxVec : every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : number of non-zero elements in ith row
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < rows; ++i) {
nPost = 0;
for(j = 0; j < clms; ++j) {
if(conVec[i + clms * j]) { /* i --> j */
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
}
nPostNeurons[i] = nPost;
}
idxVec[0] = 0;
for(i = 1; i < rows; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
void GenSparseFeedForwardMat(float *conVec, int nff, int nNeurons, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : nff*nNeurons-by-1 - input vector / flattened matrix
sparseVec : - sparse vector
idxVec : nff-by-1 - every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : nff-by-1 - number of 2/3 neurons reciving connections from
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < nff; ++i) {
nPost = 0;
for(j = 0; j < nNeurons; ++j) {
if(conVec[i + j * nff]) {
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
nPostNeurons[i] = nPost;
}
}
idxVec[0] = 0;
for(i = 1; i < nff; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef _GENSPARSEMAT_
#define _GENSPARSEMAT_
void GenSparseMat(float *conVec, int rows, int clms, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : input vector / flattened matrix
sparseVec : sparse vector
idxVec : every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : number of non-zero elements in ith row
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < rows; ++i) {
nPost = 0;
for(j = 0; j < clms; ++j) {
if(conVec[i + clms * j]) { /* i --> j */
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
}
nPostNeurons[i] = nPost;
}
idxVec[0] = 0;
for(i = 1; i < rows; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
void GenSparseFeedForwardMat(float *conVec, int nff, int nNeurons, int* sparseVec, int* idxVec, int* nPostNeurons ) {
/* generate sparse representation
conVec : nff*nNeurons-by-1 - input vector / flattened matrix
sparseVec : - sparse vector
idxVec : nff-by-1 - every element is the starting index in sparseVec for ith row in matrix conVec
nPostNeurons : nff-by-1 - number of 2/3 neurons reciving connections from
*/
unsigned long long int i, j, counter = 0, nPost;
for(i = 0; i < nff; ++i) {
nPost = 0;
for(j = 0; j < nNeurons; ++j) {
if(conVec[i + j * nff]) {
sparseVec[counter] = j;
counter += 1;
nPost += 1;
}
nPostNeurons[i] = nPost;
}
}
idxVec[0] = 0;
for(i = 1; i < nff; ++i) {
idxVec[i] = idxVec[i-1] + nPostNeurons[i-1];
}
}
#endif | .text
.file "GenSparseMat.hip"
.globl _Z12GenSparseMatPfiiPiS0_S0_ # -- Begin function _Z12GenSparseMatPfiiPiS0_S0_
.p2align 4, 0x90
.type _Z12GenSparseMatPfiiPiS0_S0_,@function
_Z12GenSparseMatPfiiPiS0_S0_: # @_Z12GenSparseMatPfiiPiS0_S0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq %esi, %rax
testl %eax, %eax
je .LBB0_9
# %bb.1: # %.preheader.lr.ph
movslq %edx, %r10
leaq (,%r10,4), %r11
xorl %ebx, %ebx
xorps %xmm0, %xmm0
xorl %r14d, %r14d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
xorl %r15d, %r15d
.LBB0_8: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl %r15d, (%r9,%r14,4)
incq %r14
addq $4, %rdi
cmpq %rax, %r14
je .LBB0_9
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_5 Depth 2
testl %edx, %edx
je .LBB0_3
# %bb.4: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movq %rdi, %r12
xorl %r15d, %r15d
xorl %r13d, %r13d
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_5 Depth=2
incq %r13
addq %r11, %r12
cmpq %r13, %r10
je .LBB0_8
.LBB0_5: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB0_6
jnp .LBB0_7
.LBB0_6: # in Loop: Header=BB0_5 Depth=2
movl %r13d, (%rcx,%rbx,4)
incq %rbx
incq %r15
jmp .LBB0_7
.LBB0_9: # %._crit_edge40
movl $0, (%r8)
cmpl $2, %esi
jb .LBB0_12
# %bb.10: # %.lr.ph44.preheader
movl (%r8), %ecx
decq %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_11: # %.lr.ph44
# =>This Inner Loop Header: Depth=1
addl (%r9,%rdx,4), %ecx
movl %ecx, 4(%r8,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB0_11
.LBB0_12: # %._crit_edge45
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12GenSparseMatPfiiPiS0_S0_, .Lfunc_end0-_Z12GenSparseMatPfiiPiS0_S0_
.cfi_endproc
# -- End function
.globl _Z23GenSparseFeedForwardMatPfiiPiS0_S0_ # -- Begin function _Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.p2align 4, 0x90
.type _Z23GenSparseFeedForwardMatPfiiPiS0_S0_,@function
_Z23GenSparseFeedForwardMatPfiiPiS0_S0_: # @_Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq %esi, %rax
testl %eax, %eax
je .LBB1_8
# %bb.1: # %.preheader.lr.ph
movslq %edx, %r10
leaq (,%rax,4), %r11
xorl %ebx, %ebx
xorps %xmm0, %xmm0
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r14
addq $4, %rdi
cmpq %rax, %r14
je .LBB1_8
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
je .LBB1_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movq %rdi, %r15
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movl %r12d, (%r9,%r14,4)
incq %r13
addq %r11, %r15
cmpq %r13, %r10
je .LBB1_7
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB1_5
jnp .LBB1_6
.LBB1_5: # in Loop: Header=BB1_4 Depth=2
movl %r13d, (%rcx,%rbx,4)
incq %rbx
incq %r12
jmp .LBB1_6
.LBB1_8: # %._crit_edge39
movl $0, (%r8)
cmpl $2, %esi
jb .LBB1_11
# %bb.9: # %.lr.ph43.preheader
movl (%r8), %ecx
decq %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph43
# =>This Inner Loop Header: Depth=1
addl (%r9,%rdx,4), %ecx
movl %ecx, 4(%r8,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB1_10
.LBB1_11: # %._crit_edge44
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z23GenSparseFeedForwardMatPfiiPiS0_S0_, .Lfunc_end1-_Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000afbb4_00000000-6_GenSparseMat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12GenSparseMatPfiiPiS0_S0_
.type _Z12GenSparseMatPfiiPiS0_S0_, @function
_Z12GenSparseMatPfiiPiS0_S0_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %r8, %rbx
movq %r9, %rbp
movslq %esi, %r9
testq %r9, %r9
je .L4
movq %rdi, %r12
movq %rcx, %r11
movslq %edx, %rdi
leaq 0(,%rdi,4), %r10
movl $0, %ecx
movl $0, %r8d
pxor %xmm0, %xmm0
jmp .L5
.L14:
movl %edx, (%r11,%rcx,4)
addq $1, %rcx
addq $1, %rsi
.L6:
addq $1, %rdx
addq %r10, %rax
cmpq %rdi, %rdx
je .L10
.L8:
ucomiss (%rax), %xmm0
jp .L14
je .L6
jmp .L14
.L10:
movl %esi, 0(%rbp,%r8,4)
addq $1, %r8
addq $4, %r12
cmpq %r9, %r8
je .L9
.L5:
movq %r12, %rax
movl $0, %esi
movl $0, %edx
testq %rdi, %rdi
jne .L8
movq %rdi, %rsi
jmp .L10
.L9:
movl $0, (%rbx)
cmpq $1, %r9
jbe .L3
movl $1, %eax
.L12:
movl -4(%rbp,%rax,4), %edx
addl -4(%rbx,%rax,4), %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq %r9, %rax
jne .L12
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movl $0, (%r8)
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z12GenSparseMatPfiiPiS0_S0_, .-_Z12GenSparseMatPfiiPiS0_S0_
.globl _Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.type _Z23GenSparseFeedForwardMatPfiiPiS0_S0_, @function
_Z23GenSparseFeedForwardMatPfiiPiS0_S0_:
.LFB2028:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %r8, %rbp
movslq %esi, %r8
testq %r8, %r8
je .L20
movq %rdi, %r13
movl %edx, %r12d
movq %rcx, %rbx
movq %r9, %rdi
leaq 0(,%r8,4), %r11
movl $0, %esi
movl $0, %r14d
movslq %edx, %r10
pxor %xmm0, %xmm0
jmp .L21
.L30:
movl %edx, (%rbx,%rsi,4)
addq $1, %rsi
addq $1, %rcx
.L22:
movl %ecx, (%rdi)
addq $1, %rdx
addq %r11, %rax
cmpq %r10, %rdx
je .L26
.L24:
ucomiss (%rax), %xmm0
jp .L30
je .L22
jmp .L30
.L26:
addq $1, %r14
addq $4, %rdi
addq $4, %r13
cmpq %r8, %r14
je .L25
.L21:
movq %r13, %rax
movl $0, %ecx
movl $0, %edx
testl %r12d, %r12d
jne .L24
jmp .L26
.L25:
movl $0, 0(%rbp)
cmpq $1, %r8
jbe .L19
movl $1, %eax
.L28:
movl -4(%r9,%rax,4), %edx
addl -4(%rbp,%rax,4), %edx
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %r8, %rax
jne .L28
.L19:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl $0, 0(%rbp)
jmp .L19
.cfi_endproc
.LFE2028:
.size _Z23GenSparseFeedForwardMatPfiiPiS0_S0_, .-_Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GenSparseMat.hip"
.globl _Z12GenSparseMatPfiiPiS0_S0_ # -- Begin function _Z12GenSparseMatPfiiPiS0_S0_
.p2align 4, 0x90
.type _Z12GenSparseMatPfiiPiS0_S0_,@function
_Z12GenSparseMatPfiiPiS0_S0_: # @_Z12GenSparseMatPfiiPiS0_S0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq %esi, %rax
testl %eax, %eax
je .LBB0_9
# %bb.1: # %.preheader.lr.ph
movslq %edx, %r10
leaq (,%r10,4), %r11
xorl %ebx, %ebx
xorps %xmm0, %xmm0
xorl %r14d, %r14d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
xorl %r15d, %r15d
.LBB0_8: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl %r15d, (%r9,%r14,4)
incq %r14
addq $4, %rdi
cmpq %rax, %r14
je .LBB0_9
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_5 Depth 2
testl %edx, %edx
je .LBB0_3
# %bb.4: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movq %rdi, %r12
xorl %r15d, %r15d
xorl %r13d, %r13d
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_5 Depth=2
incq %r13
addq %r11, %r12
cmpq %r13, %r10
je .LBB0_8
.LBB0_5: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB0_6
jnp .LBB0_7
.LBB0_6: # in Loop: Header=BB0_5 Depth=2
movl %r13d, (%rcx,%rbx,4)
incq %rbx
incq %r15
jmp .LBB0_7
.LBB0_9: # %._crit_edge40
movl $0, (%r8)
cmpl $2, %esi
jb .LBB0_12
# %bb.10: # %.lr.ph44.preheader
movl (%r8), %ecx
decq %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_11: # %.lr.ph44
# =>This Inner Loop Header: Depth=1
addl (%r9,%rdx,4), %ecx
movl %ecx, 4(%r8,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB0_11
.LBB0_12: # %._crit_edge45
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12GenSparseMatPfiiPiS0_S0_, .Lfunc_end0-_Z12GenSparseMatPfiiPiS0_S0_
.cfi_endproc
# -- End function
.globl _Z23GenSparseFeedForwardMatPfiiPiS0_S0_ # -- Begin function _Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.p2align 4, 0x90
.type _Z23GenSparseFeedForwardMatPfiiPiS0_S0_,@function
_Z23GenSparseFeedForwardMatPfiiPiS0_S0_: # @_Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq %esi, %rax
testl %eax, %eax
je .LBB1_8
# %bb.1: # %.preheader.lr.ph
movslq %edx, %r10
leaq (,%rax,4), %r11
xorl %ebx, %ebx
xorps %xmm0, %xmm0
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r14
addq $4, %rdi
cmpq %rax, %r14
je .LBB1_8
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
je .LBB1_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movq %rdi, %r15
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movl %r12d, (%r9,%r14,4)
incq %r13
addq %r11, %r15
cmpq %r13, %r10
je .LBB1_7
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB1_5
jnp .LBB1_6
.LBB1_5: # in Loop: Header=BB1_4 Depth=2
movl %r13d, (%rcx,%rbx,4)
incq %rbx
incq %r12
jmp .LBB1_6
.LBB1_8: # %._crit_edge39
movl $0, (%r8)
cmpl $2, %esi
jb .LBB1_11
# %bb.9: # %.lr.ph43.preheader
movl (%r8), %ecx
decq %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph43
# =>This Inner Loop Header: Depth=1
addl (%r9,%rdx,4), %ecx
movl %ecx, 4(%r8,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB1_10
.LBB1_11: # %._crit_edge44
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z23GenSparseFeedForwardMatPfiiPiS0_S0_, .Lfunc_end1-_Z23GenSparseFeedForwardMatPfiiPiS0_S0_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*******************************************************************************
GPU OPTIMIZED MONTE CARLO (GOMC) 2.75
Copyright (C) 2022 GOMC Group
A copy of the MIT License can be found in License.txt
along with this program, also can be found at <https://opensource.org/licenses/MIT>.
********************************************************************************/
#include "CUDAMemoryManager.cuh"
#ifdef GOMC_CUDA
long long CUDAMemoryManager::totalAllocatedBytes = 0;
std::unordered_map<void *, std::pair<unsigned int, std::string> > CUDAMemoryManager::allocatedPointers;
cudaError_t CUDAMemoryManager::mallocMemory(void **address, unsigned int size, std::string var_name)
{
cudaError_t ret = cudaMalloc(address, size);
allocatedPointers[*address] = make_pair(size, var_name);
totalAllocatedBytes += size;
if (size == 0) {
std::cout << "Warning! You are trying to allocate " << var_name << " with a size of zero bytes!\n";
}
return ret;
}
cudaError_t CUDAMemoryManager::freeMemory(void *address, std::string var_name)
{
if(allocatedPointers.find(address) != allocatedPointers.end()) {
totalAllocatedBytes -= allocatedPointers[address].first;
allocatedPointers.erase(address);
} else if (address != nullptr) {
std::cout << "Warning! You are trying to free " << var_name << " but it has already been freed\n"
<< "\tor was never allocated!\n";
}
return cudaFree(address);
}
bool CUDAMemoryManager::isFreed()
{
bool ret = allocatedPointers.size() == 0;
while(allocatedPointers.size() != 0) {
auto it = allocatedPointers.begin();
std::cout << "You forgot to free memory " << it->second.second
<< " with " << it->second.first << " bytes allocated!\n";
std::cout << "I am going to free it for you!\n";
freeMemory(it->first, it->second.second);
}
return ret;
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*******************************************************************************
GPU OPTIMIZED MONTE CARLO (GOMC) 2.75
Copyright (C) 2022 GOMC Group
A copy of the MIT License can be found in License.txt
along with this program, also can be found at <https://opensource.org/licenses/MIT>.
********************************************************************************/
#include "CUDAMemoryManager.cuh"
#ifdef GOMC_CUDA
long long CUDAMemoryManager::totalAllocatedBytes = 0;
std::unordered_map<void *, std::pair<unsigned int, std::string> > CUDAMemoryManager::allocatedPointers;
cudaError_t CUDAMemoryManager::mallocMemory(void **address, unsigned int size, std::string var_name)
{
cudaError_t ret = cudaMalloc(address, size);
allocatedPointers[*address] = make_pair(size, var_name);
totalAllocatedBytes += size;
if (size == 0) {
std::cout << "Warning! You are trying to allocate " << var_name << " with a size of zero bytes!\n";
}
return ret;
}
cudaError_t CUDAMemoryManager::freeMemory(void *address, std::string var_name)
{
if(allocatedPointers.find(address) != allocatedPointers.end()) {
totalAllocatedBytes -= allocatedPointers[address].first;
allocatedPointers.erase(address);
} else if (address != nullptr) {
std::cout << "Warning! You are trying to free " << var_name << " but it has already been freed\n"
<< "\tor was never allocated!\n";
}
return cudaFree(address);
}
bool CUDAMemoryManager::isFreed()
{
bool ret = allocatedPointers.size() == 0;
while(allocatedPointers.size() != 0) {
auto it = allocatedPointers.begin();
std::cout << "You forgot to free memory " << it->second.second
<< " with " << it->second.first << " bytes allocated!\n";
std::cout << "I am going to free it for you!\n";
freeMemory(it->first, it->second.second);
}
return ret;
}
#endif | .file "tmpxft_00187404_00000000-6_CUDAMemoryManager.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*******************************************************************************
GPU OPTIMIZED MONTE CARLO (GOMC) 2.75
Copyright (C) 2022 GOMC Group
A copy of the MIT License can be found in License.txt
along with this program, also can be found at <https://opensource.org/licenses/MIT>.
********************************************************************************/
#include "CUDAMemoryManager.cuh"
#ifdef GOMC_CUDA
long long CUDAMemoryManager::totalAllocatedBytes = 0;
std::unordered_map<void *, std::pair<unsigned int, std::string> > CUDAMemoryManager::allocatedPointers;
cudaError_t CUDAMemoryManager::mallocMemory(void **address, unsigned int size, std::string var_name)
{
cudaError_t ret = cudaMalloc(address, size);
allocatedPointers[*address] = make_pair(size, var_name);
totalAllocatedBytes += size;
if (size == 0) {
std::cout << "Warning! You are trying to allocate " << var_name << " with a size of zero bytes!\n";
}
return ret;
}
cudaError_t CUDAMemoryManager::freeMemory(void *address, std::string var_name)
{
if(allocatedPointers.find(address) != allocatedPointers.end()) {
totalAllocatedBytes -= allocatedPointers[address].first;
allocatedPointers.erase(address);
} else if (address != nullptr) {
std::cout << "Warning! You are trying to free " << var_name << " but it has already been freed\n"
<< "\tor was never allocated!\n";
}
return cudaFree(address);
}
bool CUDAMemoryManager::isFreed()
{
bool ret = allocatedPointers.size() == 0;
while(allocatedPointers.size() != 0) {
auto it = allocatedPointers.begin();
std::cout << "You forgot to free memory " << it->second.second
<< " with " << it->second.first << " bytes allocated!\n";
std::cout << "I am going to free it for you!\n";
freeMemory(it->first, it->second.second);
}
return ret;
}
#endif | /*******************************************************************************
GPU OPTIMIZED MONTE CARLO (GOMC) 2.75
Copyright (C) 2022 GOMC Group
A copy of the MIT License can be found in License.txt
along with this program, also can be found at <https://opensource.org/licenses/MIT>.
********************************************************************************/
#pragma once
#ifdef GOMC_CUDA
#include <hip/hip_runtime.h>
#include <unordered_map>
#include <iostream>
#define CUMALLOC(address,size) CUDAMemoryManager::mallocMemory(address,size,#address)
#define CUFREE(address) CUDAMemoryManager::freeMemory(address,#address)
class CUDAMemoryManager
{
public:
static hipError_t mallocMemory(void **address, unsigned int size, std::string var_name);
static hipError_t freeMemory(void *address, std::string var_name);
static bool isFreed();
private:
static long long totalAllocatedBytes;
static std::unordered_map<void *, std::pair<unsigned int, std::string> > allocatedPointers;
};
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*******************************************************************************
GPU OPTIMIZED MONTE CARLO (GOMC) 2.75
Copyright (C) 2022 GOMC Group
A copy of the MIT License can be found in License.txt
along with this program, also can be found at <https://opensource.org/licenses/MIT>.
********************************************************************************/
#pragma once
#ifdef GOMC_CUDA
#include <hip/hip_runtime.h>
#include <unordered_map>
#include <iostream>
#define CUMALLOC(address,size) CUDAMemoryManager::mallocMemory(address,size,#address)
#define CUFREE(address) CUDAMemoryManager::freeMemory(address,#address)
class CUDAMemoryManager
{
public:
static hipError_t mallocMemory(void **address, unsigned int size, std::string var_name);
static hipError_t freeMemory(void *address, std::string var_name);
static bool isFreed();
private:
static long long totalAllocatedBytes;
static std::unordered_map<void *, std::pair<unsigned int, std::string> > allocatedPointers;
};
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*******************************************************************************
GPU OPTIMIZED MONTE CARLO (GOMC) 2.75
Copyright (C) 2022 GOMC Group
A copy of the MIT License can be found in License.txt
along with this program, also can be found at <https://opensource.org/licenses/MIT>.
********************************************************************************/
#pragma once
#ifdef GOMC_CUDA
#include <hip/hip_runtime.h>
#include <unordered_map>
#include <iostream>
#define CUMALLOC(address,size) CUDAMemoryManager::mallocMemory(address,size,#address)
#define CUFREE(address) CUDAMemoryManager::freeMemory(address,#address)
class CUDAMemoryManager
{
public:
static hipError_t mallocMemory(void **address, unsigned int size, std::string var_name);
static hipError_t freeMemory(void *address, std::string var_name);
static bool isFreed();
private:
static long long totalAllocatedBytes;
static std::unordered_map<void *, std::pair<unsigned int, std::string> > allocatedPointers;
};
#endif | .text
.file "CUDAMemoryManager.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187404_00000000-6_CUDAMemoryManager.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDAMemoryManager.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void VecAdd(double* A,double* B,double* C)
{
// extern __shared__ float sdata[];
int i=threadIdx.x;
C[i]=A[i]+B[i];
} | code for sm_80
Function : _Z6VecAddPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fc800078e0209 */
/*0050*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*0090*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */
/* 0x004e0e0000000004 */
/*00a0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void VecAdd(double* A,double* B,double* C)
{
// extern __shared__ float sdata[];
int i=threadIdx.x;
C[i]=A[i]+B[i];
} | .file "tmpxft_000f5fc6_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6VecAddPdS_S_PdS_S_
.type _Z29__device_stub__Z6VecAddPdS_S_PdS_S_, @function
_Z29__device_stub__Z6VecAddPdS_S_PdS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6VecAddPdS_S_PdS_S_, .-_Z29__device_stub__Z6VecAddPdS_S_PdS_S_
.globl _Z6VecAddPdS_S_
.type _Z6VecAddPdS_S_, @function
_Z6VecAddPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPdS_S_, .-_Z6VecAddPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void VecAdd(double* A,double* B,double* C)
{
// extern __shared__ float sdata[];
int i=threadIdx.x;
C[i]=A[i]+B[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(double* A,double* B,double* C)
{
// extern __shared__ float sdata[];
int i=threadIdx.x;
C[i]=A[i]+B[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(double* A,double* B,double* C)
{
// extern __shared__ float sdata[];
int i=threadIdx.x;
C[i]=A[i]+B[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPdS_S_
.globl _Z6VecAddPdS_S_
.p2align 8
.type _Z6VecAddPdS_S_,@function
_Z6VecAddPdS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[4:5]
global_load_b64 v[2:3], v4, s[6:7]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPdS_S_, .Lfunc_end0-_Z6VecAddPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(double* A,double* B,double* C)
{
// extern __shared__ float sdata[];
int i=threadIdx.x;
C[i]=A[i]+B[i];
} | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPdS_S_ # -- Begin function _Z21__device_stub__VecAddPdS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPdS_S_,@function
_Z21__device_stub__VecAddPdS_S_: # @_Z21__device_stub__VecAddPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPdS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPdS_S_,@object # @_Z6VecAddPdS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPdS_S_
.p2align 3, 0x0
_Z6VecAddPdS_S_:
.quad _Z21__device_stub__VecAddPdS_S_
.size _Z6VecAddPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPdS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fc800078e0209 */
/*0050*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*0090*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */
/* 0x004e0e0000000004 */
/*00a0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPdS_S_
.globl _Z6VecAddPdS_S_
.p2align 8
.type _Z6VecAddPdS_S_,@function
_Z6VecAddPdS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[4:5]
global_load_b64 v[2:3], v4, s[6:7]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPdS_S_, .Lfunc_end0-_Z6VecAddPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f5fc6_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6VecAddPdS_S_PdS_S_
.type _Z29__device_stub__Z6VecAddPdS_S_PdS_S_, @function
_Z29__device_stub__Z6VecAddPdS_S_PdS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6VecAddPdS_S_PdS_S_, .-_Z29__device_stub__Z6VecAddPdS_S_PdS_S_
.globl _Z6VecAddPdS_S_
.type _Z6VecAddPdS_S_, @function
_Z6VecAddPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPdS_S_, .-_Z6VecAddPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPdS_S_ # -- Begin function _Z21__device_stub__VecAddPdS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPdS_S_,@function
_Z21__device_stub__VecAddPdS_S_: # @_Z21__device_stub__VecAddPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPdS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPdS_S_,@object # @_Z6VecAddPdS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPdS_S_
.p2align 3, 0x0
_Z6VecAddPdS_S_:
.quad _Z21__device_stub__VecAddPdS_S_
.size _Z6VecAddPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPdS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include <cuda.h>
#include <sys/time.h>
__global__ void compute(int* x,int* y,int n){
int col=threadIdx.x+blockIdx.x*blockDim.x;
int row=threadIdx.y+blockIdx.y*blockDim.y;
int num=col+row*n;
int neighbor=0;
//cell in the middle has eight neighbors,
//a cell in a corner has only three neighbors,
//a cell on an edge has five neighbors.
if(col<n && row<n){
//corner 3
//In order to move to corner,
//it should move either diagonal or move left/right and move up/down
//top left corner
if(col==0 && row==0){
neighbor+=x[num+1]; //move right
neighbor+=x[num+n]; //move bottom
neighbor+=x[num+n+1]; //bottom right
}
//bottom left corner
else if(col==0 && row==n-1){
neighbor+=x[num+1]; //move right
neighbor+=x[num-n]; //move up
neighbor+=x[num-n+1]; //top right
}
//bottom right
else if(col==n-1 && row==n-1){
neighbor+=x[num-1]; //move left
neighbor+=x[num-n]; //move up
neighbor+=x[num-n-1]; //top left
}
//edge 5
//In order to move to edge
// it should just move to left/right/up/down (including corner)
//top edge
else if(row==0 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num+n-1]; //bottom left -- corner
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right -- corner
}
//bottom edge
else if(row==n-1 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left -- corner
}
//Left edge
else if(col==0 && row>0 && row<n-1){
neighbor+=x[num+1]; //right
neighbor+=x[num-n]; //Top
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n+1]; //Bottom right-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//cell in the middle has eight neighbors,
else{
neighbor+=x[num-1];//left
neighbor+=x[num+1]; //right
neighbor+=x[num-n-1];//top left
neighbor+=x[num-n]; //top
neighbor+=x[num-n+1]; //top right
neighbor+=x[num+n-1]; //bottom left
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right
}
//Die : 0
//Live: 1
//A live cell with zero or one live neighbor dies from loneliness.
if(x[num]==1 && (neighbor ==0 || neighbor ==1))
y[num]=0;
//A live cell with four or more live neighbors dies due to overpopulation.
else if(x[num]==1 && neighbor>=4)
y[num]=0;
//A dead cell with two or three live neighbors becomes alive.
else if(x[num]==1 && (neighbor==2 || neighbor==3))
y[num]=1;
//Otherwise, a cell's state stays unchanged
else
y[num] = x[num];
}
}
int main(void){
int i,j,k;
int row= 6;
int col= 4;
int start[row][col];
int Round[row][col];
dim3 threadsPerBlock(32,32);
dim3 numBlocks(row/threadsPerBlock.x,col/threadsPerBlock.x);
int* x;
int* y;
int generation =1;// maximum generation/iteration
float milliseconds=0;
cudaEvent_t t_start,t_stop;
cudaEventCreate(&t_start);
cudaEventCreate(&t_stop);
//Initilazie the matrix of the x Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
start[i][j]=rand()%2;
//Initilazie the matrix of the y Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
Round[i][j]=0;
cudaMalloc((void **) &x,sizeof(int)*row*col);
cudaMemcpy(x,start,sizeof(int)*row*col,cudaMemcpyHostToDevice);
printf("Start\n");
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(start[i][j]){
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
for(k=0;k<= generation;k++)
{
cudaEventRecord(t_start);
compute<<<numBlocks,threadsPerBlock>>>(y,y,row);
cudaEventRecord(t_stop);
cudaMalloc((void **) &y,sizeof(int)*row*col);
cudaMemcpy(Round,y,sizeof(int)*row*col,cudaMemcpyDeviceToHost);
printf("\n Round %d \n",k);
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(Round[i][j])
{
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
cudaEventElapsedTime(&milliseconds,t_start,t_stop);
printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
}
return 0;
} | code for sm_80
Function : _Z7computePiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R17, R17, c[0x0][0x4], R0 ; /* 0x0000010011117a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x170], PT ; /* 0x00005c0011007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R10, c[0x0][0x170], P0 ; /* 0x00005c000a007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ LOP3.LUT P0, RZ, R10, R17, RZ, 0xfc, !PT ; /* 0x000000110aff7212 */
/* 0x000fe2000780fcff */
/*00b0*/ IMAD R0, R17, c[0x0][0x170], R10 ; /* 0x00005c0011007a24 */
/* 0x000fe200078e020a */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x660 ; /* 0x0000057000007945 */
/* 0x000fe40003800000 */
/*00f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe20000011400 */
/*0100*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e020b */
/*0110*/ @!P0 BRA 0x610 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff137624 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.EQ.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f22270 */
/*0140*/ IADD3 R19, R19, -0x1, RZ ; /* 0xffffffff13137810 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.NE.AND P0, PT, R17, R19, PT ; /* 0x000000131100720c */
/* 0x000fda0003f05270 */
/*0160*/ @!P0 BRA P1, 0x5c0 ; /* 0x0000045000008947 */
/* 0x000fea0000800000 */
/*0170*/ ISETP.EQ.AND P2, PT, R10.reuse, R19.reuse, PT ; /* 0x000000130a00720c */
/* 0x0c0fe40003f42270 */
/*0180*/ ISETP.NE.AND P1, PT, R10, R19, PT ; /* 0x000000130a00720c */
/* 0x000fd60003f25270 */
/*0190*/ @!P0 BRA P2, 0x550 ; /* 0x000003b000008947 */
/* 0x000fea0001000000 */
/*01a0*/ ISETP.GT.AND P2, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x040fe40003f44270 */
/*01b0*/ ISETP.LT.AND P3, PT, R10, R19, PT ; /* 0x000000130a00720c */
/* 0x000fe40003f61270 */
/*01c0*/ ISETP.EQ.AND P2, PT, R17, RZ, P2 ; /* 0x000000ff1100720c */
/* 0x000fe40001742270 */
/*01d0*/ IADD3 R8, R0, c[0x0][0x170], RZ ; /* 0x00005c0000087a10 */
/* 0x000fc80007ffe0ff */
/*01e0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fca0007ffe0ff */
/*01f0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e020b */
/*0200*/ @P2 BRA P3, 0x4e0 ; /* 0x000002d000002947 */
/* 0x000fea0001800000 */
/*0210*/ ISETP.GT.AND P0, PT, R10.reuse, RZ, !P0 ; /* 0x000000ff0a00720c */
/* 0x040fe20004704270 */
/*0220*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0230*/ ISETP.LT.AND P2, PT, R10, R19, PT ; /* 0x000000130a00720c */
/* 0x000fe20003f41270 */
/*0240*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fcc000f8e333f */
/*0250*/ IADD3 R6, R0, UR4, RZ ; /* 0x0000000400067c10 */
/* 0x000fe2000fffe0ff */
/*0260*/ IMAD.U32 R13, RZ, RZ, UR4 ; /* 0x00000004ff0d7e24 */
/* 0x000fc8000f8e00ff */
/*0270*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e020b */
/*0280*/ @P0 BRA P2, 0x470 ; /* 0x000001e000000947 */
/* 0x000fea0001000000 */
/*0290*/ ISETP.GT.AND P0, PT, R17.reuse, RZ, PT ; /* 0x000000ff1100720c */
/* 0x040fe40003f04270 */
/*02a0*/ ISETP.LT.AND P2, PT, R17, R19, PT ; /* 0x000000131100720c */
/* 0x000fe40003f41270 */
/*02b0*/ ISETP.EQ.AND P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fe40000702270 */
/*02c0*/ IADD3 R14, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000e7a10 */
/* 0x000fca0007ffe0ff */
/*02d0*/ IMAD.WIDE R14, R14, R11, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e020b */
/*02e0*/ @P0 BRA P2, 0x400 ; /* 0x0000011000000947 */
/* 0x000fea0001000000 */
/*02f0*/ ISETP.GT.AND P1, PT, R17.reuse, RZ, !P1 ; /* 0x000000ff1100720c */
/* 0x040fe20004f24270 */
/*0300*/ LDG.E R16, [R2.64+-0x4] ; /* 0xfffffc0602107981 */
/* 0x000ea6000c1e1900 */
/*0310*/ ISETP.LT.AND P1, PT, R17, R19, P1 ; /* 0x000000131100720c */
/* 0x000fe20000f21270 */
/*0320*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee8000c1e1900 */
/*0330*/ LDG.E R17, [R6.64] ; /* 0x0000000606117981 */
/* 0x000eb0000c1e1900 */
/*0340*/ @!P1 LDG.E R13, [R2.64+0x4] ; /* 0x00000406020d9981 */
/* 0x000ea8000c1e1900 */
/*0350*/ @!P1 LDG.E R10, [R6.64+0x8] ; /* 0x00000806060a9981 */
/* 0x000ee8000c1e1900 */
/*0360*/ @!P1 LDG.E R5, [R4.64] ; /* 0x0000000604059981 */
/* 0x000f22000c1e1900 */
/*0370*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c9224 */
/* 0x000fc400078e0008 */
/*0380*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e0008 */
/*0390*/ @!P1 IADD3 R13, R17, R13, R16 ; /* 0x0000000d110d9210 */
/* 0x004fc80007ffe010 */
/*03a0*/ @!P1 IADD3 R10, R10, R13, R14 ; /* 0x0000000d0a0a9210 */
/* 0x008fe20007ffe00e */
/*03b0*/ @!P1 IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d9424 */
/* 0x000fe400078e00ff */
/*03c0*/ @P1 IMAD.MOV.U32 R13, RZ, RZ, -0x1 ; /* 0xffffffffff0d1424 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P1 IMAD.IADD R10, R10, 0x1, R5 ; /* 0x000000010a0a9824 */
/* 0x010fe200078e0205 */
/*03e0*/ @P1 IADD3 R10, R17, R14, R16 ; /* 0x0000000e110a1210 */
/* 0x000fe20007ffe010 */
/*03f0*/ BRA 0x650 ; /* 0x0000025000007947 */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R10, [R14.64] ; /* 0x000000060e0a7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R6, [R6.64+0x8] ; /* 0x0000080606067981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040602057981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fc400078e00ff */
/*0440*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0450*/ IADD3 R10, R6, R10, R5 ; /* 0x0000000a060a7210 */
/* 0x004fe20007ffe005 */
/*0460*/ BRA 0x650 ; /* 0x000001e000007947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R6, [R6.64+0x8] ; /* 0x0000080606067981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R5, [R2.64+-0x4] ; /* 0xfffffc0602057981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R12, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000c7a10 */
/* 0x000fe20007ffe0ff */
/*04b0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0000 */
/*04c0*/ IADD3 R10, R6, R10, R5 ; /* 0x0000000a060a7210 */
/* 0x004fe20007ffe005 */
/*04d0*/ BRA 0x650 ; /* 0x0000017000007947 */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x000ea8000c1e1900 */
/*0500*/ LDG.E R7, [R2.64+-0x4] ; /* 0xfffffc0602077981 */
/* 0x000ea2000c1e1900 */
/*0510*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fc400078e00ff */
/*0520*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0530*/ IADD3 R10, R4, R10, R7 ; /* 0x0000000a040a7210 */
/* 0x004fe20007ffe007 */
/*0540*/ BRA 0x650 ; /* 0x0000010000007947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E R10, [R2.64+-0x4] ; /* 0xfffffc06020a7981 */
/* 0x000162000c1e1900 */
/*0560*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0570*/ IADD3 R12, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000c7a10 */
/* 0x000fe20007ffe0ff */
/*0580*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*0590*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0000 */
/*05a0*/ IMAD.U32 R13, RZ, RZ, UR4 ; /* 0x00000004ff0d7e24 */
/* 0x000fe2000f8e00ff */
/*05b0*/ BRA 0x650 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*05c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x000162000c1e1900 */
/*05d0*/ IADD3 R8, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000087a10 */
/* 0x000fe20007ffe0ff */
/*05e0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0600*/ BRA 0x650 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0610*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x000162000c1e1900 */
/*0620*/ IADD3 R8, R0, c[0x0][0x170], RZ ; /* 0x00005c0000087a10 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0650*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0660*/ IMAD.IADD R6, R13, 0x1, R8 ; /* 0x000000010d067824 */
/* 0x000fe200078e0208 */
/*0670*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IMAD.WIDE R4, R12, R11, c[0x0][0x160] ; /* 0x000058000c047625 */
/* 0x000fc800078e020b */
/*0690*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e020b */
/*06a0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ee8000c1e1900 */
/*06b0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ee2000c1e1900 */
/*06c0*/ LEA R8, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000087a11 */
/* 0x000fc800078210ff */
/*06d0*/ LEA.HI.X R9, R0, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b0000097a11 */
/* 0x000fe400008f1409 */
/*06e0*/ ISETP.NE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x004fe40003f05270 */
/*06f0*/ IADD3 R10, R6, R5, R10 ; /* 0x00000005060a7210 */
/* 0x028fc80007ffe00a */
/*0700*/ ISETP.LT.U32.AND P2, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fda0003f41070 */
/*0710*/ @!P0 BRA P2, 0x7d0 ; /* 0x000000b000008947 */
/* 0x000fea0001000000 */
/*0720*/ ISETP.GT.AND P1, PT, R10, 0x3, PT ; /* 0x000000030a00780c */
/* 0x000fda0003f24270 */
/*0730*/ @!P0 BRA P1, 0x7b0 ; /* 0x0000007000008947 */
/* 0x000fea0000800000 */
/*0740*/ LOP3.LUT R0, R10, 0x1, RZ, 0xfc, !PT ; /* 0x000000010a007812 */
/* 0x000fc800078efcff */
/*0750*/ ISETP.EQ.AND P0, PT, R0, 0x3, !P0 ; /* 0x000000030000780c */
/* 0x000fda0004702270 */
/*0760*/ @!P0 STG.E [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101906 */
/*0770*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x001fca00078e00ff */
/*0790*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101906 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101906 */
/*07c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07d0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101906 */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include <cuda.h>
#include <sys/time.h>
__global__ void compute(int* x,int* y,int n){
int col=threadIdx.x+blockIdx.x*blockDim.x;
int row=threadIdx.y+blockIdx.y*blockDim.y;
int num=col+row*n;
int neighbor=0;
//cell in the middle has eight neighbors,
//a cell in a corner has only three neighbors,
//a cell on an edge has five neighbors.
if(col<n && row<n){
//corner 3
//In order to move to corner,
//it should move either diagonal or move left/right and move up/down
//top left corner
if(col==0 && row==0){
neighbor+=x[num+1]; //move right
neighbor+=x[num+n]; //move bottom
neighbor+=x[num+n+1]; //bottom right
}
//bottom left corner
else if(col==0 && row==n-1){
neighbor+=x[num+1]; //move right
neighbor+=x[num-n]; //move up
neighbor+=x[num-n+1]; //top right
}
//bottom right
else if(col==n-1 && row==n-1){
neighbor+=x[num-1]; //move left
neighbor+=x[num-n]; //move up
neighbor+=x[num-n-1]; //top left
}
//edge 5
//In order to move to edge
// it should just move to left/right/up/down (including corner)
//top edge
else if(row==0 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num+n-1]; //bottom left -- corner
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right -- corner
}
//bottom edge
else if(row==n-1 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left -- corner
}
//Left edge
else if(col==0 && row>0 && row<n-1){
neighbor+=x[num+1]; //right
neighbor+=x[num-n]; //Top
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n+1]; //Bottom right-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//cell in the middle has eight neighbors,
else{
neighbor+=x[num-1];//left
neighbor+=x[num+1]; //right
neighbor+=x[num-n-1];//top left
neighbor+=x[num-n]; //top
neighbor+=x[num-n+1]; //top right
neighbor+=x[num+n-1]; //bottom left
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right
}
//Die : 0
//Live: 1
//A live cell with zero or one live neighbor dies from loneliness.
if(x[num]==1 && (neighbor ==0 || neighbor ==1))
y[num]=0;
//A live cell with four or more live neighbors dies due to overpopulation.
else if(x[num]==1 && neighbor>=4)
y[num]=0;
//A dead cell with two or three live neighbors becomes alive.
else if(x[num]==1 && (neighbor==2 || neighbor==3))
y[num]=1;
//Otherwise, a cell's state stays unchanged
else
y[num] = x[num];
}
}
int main(void){
int i,j,k;
int row= 6;
int col= 4;
int start[row][col];
int Round[row][col];
dim3 threadsPerBlock(32,32);
dim3 numBlocks(row/threadsPerBlock.x,col/threadsPerBlock.x);
int* x;
int* y;
int generation =1;// maximum generation/iteration
float milliseconds=0;
cudaEvent_t t_start,t_stop;
cudaEventCreate(&t_start);
cudaEventCreate(&t_stop);
//Initilazie the matrix of the x Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
start[i][j]=rand()%2;
//Initilazie the matrix of the y Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
Round[i][j]=0;
cudaMalloc((void **) &x,sizeof(int)*row*col);
cudaMemcpy(x,start,sizeof(int)*row*col,cudaMemcpyHostToDevice);
printf("Start\n");
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(start[i][j]){
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
for(k=0;k<= generation;k++)
{
cudaEventRecord(t_start);
compute<<<numBlocks,threadsPerBlock>>>(y,y,row);
cudaEventRecord(t_stop);
cudaMalloc((void **) &y,sizeof(int)*row*col);
cudaMemcpy(Round,y,sizeof(int)*row*col,cudaMemcpyDeviceToHost);
printf("\n Round %d \n",k);
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(Round[i][j])
{
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
cudaEventElapsedTime(&milliseconds,t_start,t_stop);
printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
}
return 0;
} | .file "tmpxft_000edb03_00000000-6_game.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7computePiS_iPiS_i
.type _Z29__device_stub__Z7computePiS_iPiS_i, @function
_Z29__device_stub__Z7computePiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7computePiS_iPiS_i, .-_Z29__device_stub__Z7computePiS_iPiS_i
.globl _Z7computePiS_i
.type _Z7computePiS_i, @function
_Z7computePiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7computePiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7computePiS_i, .-_Z7computePiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Start\n"
.LC2:
.string "-------\n"
.LC3:
.string " 0"
.LC4:
.string " 1"
.LC5:
.string "\n"
.LC6:
.string "\n Round %d \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Time taken for this computation = %f milliseconds\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $296, %rsp
.cfi_def_cfa_offset 352
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $0, 68(%rsp)
movl $0, 72(%rsp)
movl $1, 76(%rsp)
movl $0x00000000, 20(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 96(%rsp), %rbp
leaq 192(%rsp), %r14
movq %rbp, %r12
jmp .L12
.L36:
addq $16, %r12
cmpq %r14, %r12
je .L35
.L12:
leaq -16(%r12), %rbx
.L13:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
jmp .L36
.L35:
leaq 176(%rsp), %rax
movq %rax, 8(%rsp)
leaq 272(%rsp), %rdx
.L14:
movl $0, (%rax)
movl $0, 4(%rax)
movl $0, 8(%rax)
movl $0, 12(%rax)
addq $16, %rax
cmpq %rdx, %rax
jne .L14
leaq 24(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $96, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %r13
leaq .LC3(%rip), %r12
leaq .LC5(%rip), %r15
jmp .L15
.L16:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L17:
addq $4, %rbx
cmpq %rbp, %rbx
je .L37
.L18:
cmpl $0, (%rbx)
je .L16
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L37:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
cmpq %r14, %rbp
je .L27
.L15:
leaq -16(%rbp), %rbx
jmp .L18
.L27:
movl $0, 4(%rsp)
leaq .LC4(%rip), %r13
leaq .LC3(%rip), %r12
jmp .L19
.L40:
movq 32(%rsp), %rdi
movl $6, %edx
movq %rdi, %rsi
call _Z29__device_stub__Z7computePiS_iPiS_i
jmp .L20
.L22:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L23:
addq $4, %rbx
cmpq %rbx, %rbp
je .L38
.L24:
cmpl $0, (%rbx)
je .L22
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L38:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
cmpq %r15, %rbp
je .L25
.L21:
leaq -16(%rbp), %rbx
jmp .L24
.L25:
leaq 20(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, 4(%rsp)
movl 4(%rsp), %eax
cmpl $2, %eax
je .L39
.L19:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 56(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L20:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 32(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 176(%rsp), %rdi
movl $2, %ecx
movl $96, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 16(%rax), %rbp
leaq 112(%rax), %r15
leaq .LC5(%rip), %r14
jmp .L21
.L39:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7computePiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include <cuda.h>
#include <sys/time.h>
__global__ void compute(int* x,int* y,int n){
int col=threadIdx.x+blockIdx.x*blockDim.x;
int row=threadIdx.y+blockIdx.y*blockDim.y;
int num=col+row*n;
int neighbor=0;
//cell in the middle has eight neighbors,
//a cell in a corner has only three neighbors,
//a cell on an edge has five neighbors.
if(col<n && row<n){
//corner 3
//In order to move to corner,
//it should move either diagonal or move left/right and move up/down
//top left corner
if(col==0 && row==0){
neighbor+=x[num+1]; //move right
neighbor+=x[num+n]; //move bottom
neighbor+=x[num+n+1]; //bottom right
}
//bottom left corner
else if(col==0 && row==n-1){
neighbor+=x[num+1]; //move right
neighbor+=x[num-n]; //move up
neighbor+=x[num-n+1]; //top right
}
//bottom right
else if(col==n-1 && row==n-1){
neighbor+=x[num-1]; //move left
neighbor+=x[num-n]; //move up
neighbor+=x[num-n-1]; //top left
}
//edge 5
//In order to move to edge
// it should just move to left/right/up/down (including corner)
//top edge
else if(row==0 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num+n-1]; //bottom left -- corner
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right -- corner
}
//bottom edge
else if(row==n-1 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left -- corner
}
//Left edge
else if(col==0 && row>0 && row<n-1){
neighbor+=x[num+1]; //right
neighbor+=x[num-n]; //Top
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n+1]; //Bottom right-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//cell in the middle has eight neighbors,
else{
neighbor+=x[num-1];//left
neighbor+=x[num+1]; //right
neighbor+=x[num-n-1];//top left
neighbor+=x[num-n]; //top
neighbor+=x[num-n+1]; //top right
neighbor+=x[num+n-1]; //bottom left
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right
}
//Die : 0
//Live: 1
//A live cell with zero or one live neighbor dies from loneliness.
if(x[num]==1 && (neighbor ==0 || neighbor ==1))
y[num]=0;
//A live cell with four or more live neighbors dies due to overpopulation.
else if(x[num]==1 && neighbor>=4)
y[num]=0;
//A dead cell with two or three live neighbors becomes alive.
else if(x[num]==1 && (neighbor==2 || neighbor==3))
y[num]=1;
//Otherwise, a cell's state stays unchanged
else
y[num] = x[num];
}
}
int main(void){
int i,j,k;
int row= 6;
int col= 4;
int start[row][col];
int Round[row][col];
dim3 threadsPerBlock(32,32);
dim3 numBlocks(row/threadsPerBlock.x,col/threadsPerBlock.x);
int* x;
int* y;
int generation =1;// maximum generation/iteration
float milliseconds=0;
cudaEvent_t t_start,t_stop;
cudaEventCreate(&t_start);
cudaEventCreate(&t_stop);
//Initilazie the matrix of the x Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
start[i][j]=rand()%2;
//Initilazie the matrix of the y Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
Round[i][j]=0;
cudaMalloc((void **) &x,sizeof(int)*row*col);
cudaMemcpy(x,start,sizeof(int)*row*col,cudaMemcpyHostToDevice);
printf("Start\n");
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(start[i][j]){
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
for(k=0;k<= generation;k++)
{
cudaEventRecord(t_start);
compute<<<numBlocks,threadsPerBlock>>>(y,y,row);
cudaEventRecord(t_stop);
cudaMalloc((void **) &y,sizeof(int)*row*col);
cudaMemcpy(Round,y,sizeof(int)*row*col,cudaMemcpyDeviceToHost);
printf("\n Round %d \n",k);
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(Round[i][j])
{
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
cudaEventElapsedTime(&milliseconds,t_start,t_stop);
printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
}
return 0;
} | #include<stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
__global__ void compute(int* x,int* y,int n){
int col=threadIdx.x+blockIdx.x*blockDim.x;
int row=threadIdx.y+blockIdx.y*blockDim.y;
int num=col+row*n;
int neighbor=0;
//cell in the middle has eight neighbors,
//a cell in a corner has only three neighbors,
//a cell on an edge has five neighbors.
if(col<n && row<n){
//corner 3
//In order to move to corner,
//it should move either diagonal or move left/right and move up/down
//top left corner
if(col==0 && row==0){
neighbor+=x[num+1]; //move right
neighbor+=x[num+n]; //move bottom
neighbor+=x[num+n+1]; //bottom right
}
//bottom left corner
else if(col==0 && row==n-1){
neighbor+=x[num+1]; //move right
neighbor+=x[num-n]; //move up
neighbor+=x[num-n+1]; //top right
}
//bottom right
else if(col==n-1 && row==n-1){
neighbor+=x[num-1]; //move left
neighbor+=x[num-n]; //move up
neighbor+=x[num-n-1]; //top left
}
//edge 5
//In order to move to edge
// it should just move to left/right/up/down (including corner)
//top edge
else if(row==0 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num+n-1]; //bottom left -- corner
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right -- corner
}
//bottom edge
else if(row==n-1 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left -- corner
}
//Left edge
else if(col==0 && row>0 && row<n-1){
neighbor+=x[num+1]; //right
neighbor+=x[num-n]; //Top
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n+1]; //Bottom right-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//cell in the middle has eight neighbors,
else{
neighbor+=x[num-1];//left
neighbor+=x[num+1]; //right
neighbor+=x[num-n-1];//top left
neighbor+=x[num-n]; //top
neighbor+=x[num-n+1]; //top right
neighbor+=x[num+n-1]; //bottom left
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right
}
//Die : 0
//Live: 1
//A live cell with zero or one live neighbor dies from loneliness.
if(x[num]==1 && (neighbor ==0 || neighbor ==1))
y[num]=0;
//A live cell with four or more live neighbors dies due to overpopulation.
else if(x[num]==1 && neighbor>=4)
y[num]=0;
//A dead cell with two or three live neighbors becomes alive.
else if(x[num]==1 && (neighbor==2 || neighbor==3))
y[num]=1;
//Otherwise, a cell's state stays unchanged
else
y[num] = x[num];
}
}
int main(void){
int i,j,k;
int row= 6;
int col= 4;
int start[row][col];
int Round[row][col];
dim3 threadsPerBlock(32,32);
dim3 numBlocks(row/threadsPerBlock.x,col/threadsPerBlock.x);
int* x;
int* y;
int generation =1;// maximum generation/iteration
float milliseconds=0;
hipEvent_t t_start,t_stop;
hipEventCreate(&t_start);
hipEventCreate(&t_stop);
//Initilazie the matrix of the x Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
start[i][j]=rand()%2;
//Initilazie the matrix of the y Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
Round[i][j]=0;
hipMalloc((void **) &x,sizeof(int)*row*col);
hipMemcpy(x,start,sizeof(int)*row*col,hipMemcpyHostToDevice);
printf("Start\n");
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(start[i][j]){
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
for(k=0;k<= generation;k++)
{
hipEventRecord(t_start);
compute<<<numBlocks,threadsPerBlock>>>(y,y,row);
hipEventRecord(t_stop);
hipMalloc((void **) &y,sizeof(int)*row*col);
hipMemcpy(Round,y,sizeof(int)*row*col,hipMemcpyDeviceToHost);
printf("\n Round %d \n",k);
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(Round[i][j])
{
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
hipEventElapsedTime(&milliseconds,t_start,t_stop);
printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
__global__ void compute(int* x,int* y,int n){
int col=threadIdx.x+blockIdx.x*blockDim.x;
int row=threadIdx.y+blockIdx.y*blockDim.y;
int num=col+row*n;
int neighbor=0;
//cell in the middle has eight neighbors,
//a cell in a corner has only three neighbors,
//a cell on an edge has five neighbors.
if(col<n && row<n){
//corner 3
//In order to move to corner,
//it should move either diagonal or move left/right and move up/down
//top left corner
if(col==0 && row==0){
neighbor+=x[num+1]; //move right
neighbor+=x[num+n]; //move bottom
neighbor+=x[num+n+1]; //bottom right
}
//bottom left corner
else if(col==0 && row==n-1){
neighbor+=x[num+1]; //move right
neighbor+=x[num-n]; //move up
neighbor+=x[num-n+1]; //top right
}
//bottom right
else if(col==n-1 && row==n-1){
neighbor+=x[num-1]; //move left
neighbor+=x[num-n]; //move up
neighbor+=x[num-n-1]; //top left
}
//edge 5
//In order to move to edge
// it should just move to left/right/up/down (including corner)
//top edge
else if(row==0 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num+n-1]; //bottom left -- corner
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right -- corner
}
//bottom edge
else if(row==n-1 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left -- corner
}
//Left edge
else if(col==0 && row>0 && row<n-1){
neighbor+=x[num+1]; //right
neighbor+=x[num-n]; //Top
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n+1]; //Bottom right-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//cell in the middle has eight neighbors,
else{
neighbor+=x[num-1];//left
neighbor+=x[num+1]; //right
neighbor+=x[num-n-1];//top left
neighbor+=x[num-n]; //top
neighbor+=x[num-n+1]; //top right
neighbor+=x[num+n-1]; //bottom left
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right
}
//Die : 0
//Live: 1
//A live cell with zero or one live neighbor dies from loneliness.
if(x[num]==1 && (neighbor ==0 || neighbor ==1))
y[num]=0;
//A live cell with four or more live neighbors dies due to overpopulation.
else if(x[num]==1 && neighbor>=4)
y[num]=0;
//A dead cell with two or three live neighbors becomes alive.
else if(x[num]==1 && (neighbor==2 || neighbor==3))
y[num]=1;
//Otherwise, a cell's state stays unchanged
else
y[num] = x[num];
}
}
int main(void){
int i,j,k;
int row= 6;
int col= 4;
int start[row][col];
int Round[row][col];
dim3 threadsPerBlock(32,32);
dim3 numBlocks(row/threadsPerBlock.x,col/threadsPerBlock.x);
int* x;
int* y;
int generation =1;// maximum generation/iteration
float milliseconds=0;
hipEvent_t t_start,t_stop;
hipEventCreate(&t_start);
hipEventCreate(&t_stop);
//Initilazie the matrix of the x Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
start[i][j]=rand()%2;
//Initilazie the matrix of the y Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
Round[i][j]=0;
hipMalloc((void **) &x,sizeof(int)*row*col);
hipMemcpy(x,start,sizeof(int)*row*col,hipMemcpyHostToDevice);
printf("Start\n");
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(start[i][j]){
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
for(k=0;k<= generation;k++)
{
hipEventRecord(t_start);
compute<<<numBlocks,threadsPerBlock>>>(y,y,row);
hipEventRecord(t_stop);
hipMalloc((void **) &y,sizeof(int)*row*col);
hipMemcpy(Round,y,sizeof(int)*row*col,hipMemcpyDeviceToHost);
printf("\n Round %d \n",k);
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(Round[i][j])
{
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
hipEventElapsedTime(&milliseconds,t_start,t_stop);
printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePiS_i
.globl _Z7computePiS_i
.p2align 8
.type _Z7computePiS_i,@function
_Z7computePiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[6:7], null, s14, s3, v[1:2]
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v6, v4
v_cmpx_gt_i32_e64 s7, v0
s_cbranch_execz .LBB0_41
s_load_b64 s[8:9], s[0:1], 0x0
v_or_b32_e32 v2, v4, v6
v_mad_u64_u32 v[0:1], null, v4, s7, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s10, exec_lo, s2
s_cbranch_execz .LBB0_27
s_add_i32 s13, s7, -1
v_cmp_eq_u32_e64 s2, 0, v6
v_cmp_eq_u32_e64 s3, s13, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s2, s3
s_xor_b32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_xor_b32 s11, exec_lo, s5
s_cbranch_execz .LBB0_24
v_cmp_eq_u32_e32 vcc_lo, s13, v6
s_and_b32 s4, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, -1
s_and_saveexec_b32 s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s12, exec_lo, s5
s_cbranch_execz .LBB0_21
v_cmp_eq_u32_e64 s6, 0, v4
v_cmp_lt_i32_e64 s4, 0, v6
v_cmp_gt_i32_e64 s5, s13, v6
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s6, s4, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, -1
s_and_saveexec_b32 s14, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s14
s_cbranch_execz .LBB0_18
s_and_b32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s5, s3
s_xor_b32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_xor_b32 s5, exec_lo, s4
s_cbranch_execz .LBB0_15
v_cmp_lt_i32_e64 s3, 0, v4
v_cmp_gt_i32_e64 s4, s13, v4
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, -1
s_and_saveexec_b32 s13, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s13, exec_lo, s13
s_cbranch_execz .LBB0_12
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s2, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v5, s2, s9, v2, s2
s_and_b32 s2, vcc_lo, s3
s_and_b32 s2, s4, s2
global_load_b32 v1, v[4:5], off offset:-4
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_xor_b32 s2, exec_lo, s3
s_cbranch_execz .LBB0_9
v_subrev_nc_u32_e32 v2, s7, v0
v_add_nc_u32_e32 v6, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_clause 0x1
global_load_b32 v8, v[4:5], off offset:4
global_load_b32 v9, v[2:3], off offset:-4
v_add_co_u32 v4, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v7, vcc_lo
s_clause 0x2
global_load_b64 v[2:3], v[2:3], off
global_load_b32 v6, v[4:5], off offset:-4
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(3)
v_add3_u32 v1, v8, v1, v9
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add3_u32 v1, v1, v2, v3
v_add_co_u32 v2, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_add3_u32 v7, v1, v6, v7
.LBB0_9:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_11
v_subrev_nc_u32_e32 v2, s7, v0
v_add_nc_u32_e32 v4, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
global_load_b32 v2, v[2:3], off offset:-4
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v1, v6, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v7, v1, v2, v7
v_add_co_u32 v2, vcc_lo, v4, -4
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v5, vcc_lo
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_12:
s_and_not1_saveexec_b32 s2, s13
s_cbranch_execz .LBB0_14
v_subrev_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, s7, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_clause 0x2
global_load_b32 v5, v[5:6], off offset:4
global_load_b64 v[1:2], v[1:2], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v1, v1, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v7, v1, v2, v6
v_add_co_u32 v2, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_15:
s_and_not1_saveexec_b32 s2, s5
s_cbranch_execz .LBB0_17
v_subrev_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
s_clause 0x2
global_load_b32 v7, v[3:4], off offset:-4
global_load_b32 v3, v[3:4], off offset:4
global_load_b64 v[1:2], v[5:6], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v3, v3, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v7, v3, v2, v1
v_add_co_u32 v2, vcc_lo, v5, -4
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v6, vcc_lo
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_18:
s_and_not1_saveexec_b32 s2, s6
s_cbranch_execz .LBB0_20
v_add_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
s_clause 0x3
global_load_b32 v1, v[3:4], off offset:-4
global_load_b32 v2, v[3:4], off offset:4
global_load_b32 v3, v[5:6], off offset:-4
global_load_b32 v4, v[5:6], off
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v1, v2, v1
v_add_co_u32 v2, vcc_lo, v5, 4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v7, v1, v3, v4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_21:
s_and_not1_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_23
v_subrev_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off offset:-4
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v2, v1
v_add_co_u32 v2, vcc_lo, v5, -4
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v6, vcc_lo
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_24:
s_and_not1_saveexec_b32 s2, s11
s_cbranch_execz .LBB0_26
v_subrev_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off offset:4
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v2, v1
v_add_co_u32 v2, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_27:
s_or_saveexec_b32 s2, s10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_29
v_add_nc_u32_e32 v2, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off offset:4
global_load_b32 v5, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v5, v4
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b32 v3, v[2:3], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v3, v7, v3
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s0, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s1, 1, v3
s_or_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_39
v_cmp_gt_i32_e64 s0, 4, v3
s_xor_b32 s5, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s5, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s0
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_36
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_and_b32_e32 v3, -2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 2, v3
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
s_or_b32 s0, s5, vcc_lo
s_and_saveexec_b32 s5, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s5
s_cbranch_execz .LBB0_33
global_store_b32 v[0:1], v2, off
.LBB0_33:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_35
v_mov_b32_e32 v2, 1
global_store_b32 v[0:1], v2, off
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_36:
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execz .LBB0_38
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_38:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_39:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_41
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_41:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePiS_i, .Lfunc_end0-_Z7computePiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
__global__ void compute(int* x,int* y,int n){
int col=threadIdx.x+blockIdx.x*blockDim.x;
int row=threadIdx.y+blockIdx.y*blockDim.y;
int num=col+row*n;
int neighbor=0;
//cell in the middle has eight neighbors,
//a cell in a corner has only three neighbors,
//a cell on an edge has five neighbors.
if(col<n && row<n){
//corner 3
//In order to move to corner,
//it should move either diagonal or move left/right and move up/down
//top left corner
if(col==0 && row==0){
neighbor+=x[num+1]; //move right
neighbor+=x[num+n]; //move bottom
neighbor+=x[num+n+1]; //bottom right
}
//bottom left corner
else if(col==0 && row==n-1){
neighbor+=x[num+1]; //move right
neighbor+=x[num-n]; //move up
neighbor+=x[num-n+1]; //top right
}
//bottom right
else if(col==n-1 && row==n-1){
neighbor+=x[num-1]; //move left
neighbor+=x[num-n]; //move up
neighbor+=x[num-n-1]; //top left
}
//edge 5
//In order to move to edge
// it should just move to left/right/up/down (including corner)
//top edge
else if(row==0 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num+n-1]; //bottom left -- corner
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right -- corner
}
//bottom edge
else if(row==n-1 && col>0 && col<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num+1]; //right
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left -- corner
}
//Left edge
else if(col==0 && row>0 && row<n-1){
neighbor+=x[num+1]; //right
neighbor+=x[num-n]; //Top
neighbor+=x[num-n+1]; //Top right-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n+1]; //Bottom right-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//Right edge
else if(col==n-1 && row>0 && row<n-1){
neighbor+=x[num-1]; //left
neighbor+=x[num-n]; //Top
neighbor+=x[num-n-1]; //Top left-- corner
neighbor+=x[num+n]; //Bottom
neighbor+=x[num+n-1]; //Bottom left-- corner
}
//cell in the middle has eight neighbors,
else{
neighbor+=x[num-1];//left
neighbor+=x[num+1]; //right
neighbor+=x[num-n-1];//top left
neighbor+=x[num-n]; //top
neighbor+=x[num-n+1]; //top right
neighbor+=x[num+n-1]; //bottom left
neighbor+=x[num+n]; //bottom
neighbor+=x[num+n+1]; //bottom right
}
//Die : 0
//Live: 1
//A live cell with zero or one live neighbor dies from loneliness.
if(x[num]==1 && (neighbor ==0 || neighbor ==1))
y[num]=0;
//A live cell with four or more live neighbors dies due to overpopulation.
else if(x[num]==1 && neighbor>=4)
y[num]=0;
//A dead cell with two or three live neighbors becomes alive.
else if(x[num]==1 && (neighbor==2 || neighbor==3))
y[num]=1;
//Otherwise, a cell's state stays unchanged
else
y[num] = x[num];
}
}
int main(void){
int i,j,k;
int row= 6;
int col= 4;
int start[row][col];
int Round[row][col];
dim3 threadsPerBlock(32,32);
dim3 numBlocks(row/threadsPerBlock.x,col/threadsPerBlock.x);
int* x;
int* y;
int generation =1;// maximum generation/iteration
float milliseconds=0;
hipEvent_t t_start,t_stop;
hipEventCreate(&t_start);
hipEventCreate(&t_stop);
//Initilazie the matrix of the x Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
start[i][j]=rand()%2;
//Initilazie the matrix of the y Generated cell
for(i=0;i<row;i++)
for(j=0;j<col;j++)
Round[i][j]=0;
hipMalloc((void **) &x,sizeof(int)*row*col);
hipMemcpy(x,start,sizeof(int)*row*col,hipMemcpyHostToDevice);
printf("Start\n");
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(start[i][j]){
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
for(k=0;k<= generation;k++)
{
hipEventRecord(t_start);
compute<<<numBlocks,threadsPerBlock>>>(y,y,row);
hipEventRecord(t_stop);
hipMalloc((void **) &y,sizeof(int)*row*col);
hipMemcpy(Round,y,sizeof(int)*row*col,hipMemcpyDeviceToHost);
printf("\n Round %d \n",k);
printf("-------\n");
for(i=0;i<row;i++)
{
for(j=0;j<col;j++)
{
if(Round[i][j])
{
printf(" 0");
}
else{
printf(" 1");
}
}
printf("\n");
}
hipEventElapsedTime(&milliseconds,t_start,t_stop);
printf("Time taken for this computation = %f milliseconds\n\n",milliseconds);
}
return 0;
} | .text
.file "game.hip"
.globl _Z22__device_stub__computePiS_i # -- Begin function _Z22__device_stub__computePiS_i
.p2align 4, 0x90
.type _Z22__device_stub__computePiS_i,@function
_Z22__device_stub__computePiS_i: # @_Z22__device_stub__computePiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__computePiS_i, .Lfunc_end0-_Z22__device_stub__computePiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 8(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 240(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader74
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $4, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $16, %rbx
cmpq $6, %r14
jne .LBB1_1
# %bb.4: # %.preheader72.preheader
xorps %xmm0, %xmm0
movaps %xmm0, 224(%rsp)
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
leaq 40(%rsp), %rdi
movl $96, %esi
callq hipMalloc
movq 40(%rsp), %rdi
leaq 240(%rsp), %rbx
movl $96, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $16, %rbx
cmpq $6, %r14
je .LBB1_10
.LBB1_5: # %.preheader71
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r15d, %r15d
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_6 Depth=2
xorl %eax, %eax
callq printf
incq %r15
cmpq $4, %r15
je .LBB1_9
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
cmpl $0, (%rbx,%r15,4)
movl $.L.str.3, %edi
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=2
movl $.L.str.2, %edi
jmp .LBB1_8
.LBB1_10: # %.preheader70
leaq 144(%rsp), %rbp
leaq 8(%rsp), %r12
xorl %r13d, %r13d
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_11 Depth=1
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r12, %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leal 1(%r13), %eax
testl %r13d, %r13d
movl %eax, %r13d
jne .LBB1_20
.LBB1_11: # =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
# Child Loop BB1_15 Depth 3
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
xorl %edi, %edi
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movq 32(%rsp), %rax
movq %rax, 104(%rsp)
movq %rax, 96(%rsp)
movl $6, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z7computePiS_i, %edi
leaq 112(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13: # in Loop: Header=BB1_11 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $96, %esi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rsi
movl $96, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq %rbp, %r15
xorl %ebx, %ebx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_18: # in Loop: Header=BB1_14 Depth=2
movl $10, %edi
callq putchar@PLT
incq %rbx
addq $16, %r15
cmpq $6, %rbx
je .LBB1_19
.LBB1_14: # %.preheader
# Parent Loop BB1_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_15 Depth 3
xorl %r14d, %r14d
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_15 Depth=3
xorl %eax, %eax
callq printf
incq %r14
cmpq $4, %r14
je .LBB1_18
.LBB1_15: # Parent Loop BB1_11 Depth=1
# Parent Loop BB1_14 Depth=2
# => This Inner Loop Header: Depth=3
cmpl $0, (%r15,%r14,4)
movl $.L.str.3, %edi
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_15 Depth=3
movl $.L.str.2, %edi
jmp .LBB1_17
.LBB1_20:
xorl %eax, %eax
addq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePiS_i,@object # @_Z7computePiS_i
.section .rodata,"a",@progbits
.globl _Z7computePiS_i
.p2align 3, 0x0
_Z7computePiS_i:
.quad _Z22__device_stub__computePiS_i
.size _Z7computePiS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " 0"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " 1"
.size .L.str.3, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n Round %d \n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time taken for this computation = %f milliseconds\n\n"
.size .L.str.6, 52
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePiS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Start"
.size .Lstr, 6
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "-------"
.size .Lstr.2, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computePiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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