system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7computePiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R17, R17, c[0x0][0x4], R0 ; /* 0x0000010011117a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x170], PT ; /* 0x00005c0011007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R10, c[0x0][0x170], P0 ; /* 0x00005c000a007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ LOP3.LUT P0, RZ, R10, R17, RZ, 0xfc, !PT ; /* 0x000000110aff7212 */
/* 0x000fe2000780fcff */
/*00b0*/ IMAD R0, R17, c[0x0][0x170], R10 ; /* 0x00005c0011007a24 */
/* 0x000fe200078e020a */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x660 ; /* 0x0000057000007945 */
/* 0x000fe40003800000 */
/*00f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe20000011400 */
/*0100*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e020b */
/*0110*/ @!P0 BRA 0x610 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff137624 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.EQ.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f22270 */
/*0140*/ IADD3 R19, R19, -0x1, RZ ; /* 0xffffffff13137810 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.NE.AND P0, PT, R17, R19, PT ; /* 0x000000131100720c */
/* 0x000fda0003f05270 */
/*0160*/ @!P0 BRA P1, 0x5c0 ; /* 0x0000045000008947 */
/* 0x000fea0000800000 */
/*0170*/ ISETP.EQ.AND P2, PT, R10.reuse, R19.reuse, PT ; /* 0x000000130a00720c */
/* 0x0c0fe40003f42270 */
/*0180*/ ISETP.NE.AND P1, PT, R10, R19, PT ; /* 0x000000130a00720c */
/* 0x000fd60003f25270 */
/*0190*/ @!P0 BRA P2, 0x550 ; /* 0x000003b000008947 */
/* 0x000fea0001000000 */
/*01a0*/ ISETP.GT.AND P2, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x040fe40003f44270 */
/*01b0*/ ISETP.LT.AND P3, PT, R10, R19, PT ; /* 0x000000130a00720c */
/* 0x000fe40003f61270 */
/*01c0*/ ISETP.EQ.AND P2, PT, R17, RZ, P2 ; /* 0x000000ff1100720c */
/* 0x000fe40001742270 */
/*01d0*/ IADD3 R8, R0, c[0x0][0x170], RZ ; /* 0x00005c0000087a10 */
/* 0x000fc80007ffe0ff */
/*01e0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fca0007ffe0ff */
/*01f0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e020b */
/*0200*/ @P2 BRA P3, 0x4e0 ; /* 0x000002d000002947 */
/* 0x000fea0001800000 */
/*0210*/ ISETP.GT.AND P0, PT, R10.reuse, RZ, !P0 ; /* 0x000000ff0a00720c */
/* 0x040fe20004704270 */
/*0220*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0230*/ ISETP.LT.AND P2, PT, R10, R19, PT ; /* 0x000000130a00720c */
/* 0x000fe20003f41270 */
/*0240*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fcc000f8e333f */
/*0250*/ IADD3 R6, R0, UR4, RZ ; /* 0x0000000400067c10 */
/* 0x000fe2000fffe0ff */
/*0260*/ IMAD.U32 R13, RZ, RZ, UR4 ; /* 0x00000004ff0d7e24 */
/* 0x000fc8000f8e00ff */
/*0270*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e020b */
/*0280*/ @P0 BRA P2, 0x470 ; /* 0x000001e000000947 */
/* 0x000fea0001000000 */
/*0290*/ ISETP.GT.AND P0, PT, R17.reuse, RZ, PT ; /* 0x000000ff1100720c */
/* 0x040fe40003f04270 */
/*02a0*/ ISETP.LT.AND P2, PT, R17, R19, PT ; /* 0x000000131100720c */
/* 0x000fe40003f41270 */
/*02b0*/ ISETP.EQ.AND P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fe40000702270 */
/*02c0*/ IADD3 R14, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000e7a10 */
/* 0x000fca0007ffe0ff */
/*02d0*/ IMAD.WIDE R14, R14, R11, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e020b */
/*02e0*/ @P0 BRA P2, 0x400 ; /* 0x0000011000000947 */
/* 0x000fea0001000000 */
/*02f0*/ ISETP.GT.AND P1, PT, R17.reuse, RZ, !P1 ; /* 0x000000ff1100720c */
/* 0x040fe20004f24270 */
/*0300*/ LDG.E R16, [R2.64+-0x4] ; /* 0xfffffc0602107981 */
/* 0x000ea6000c1e1900 */
/*0310*/ ISETP.LT.AND P1, PT, R17, R19, P1 ; /* 0x000000131100720c */
/* 0x000fe20000f21270 */
/*0320*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee8000c1e1900 */
/*0330*/ LDG.E R17, [R6.64] ; /* 0x0000000606117981 */
/* 0x000eb0000c1e1900 */
/*0340*/ @!P1 LDG.E R13, [R2.64+0x4] ; /* 0x00000406020d9981 */
/* 0x000ea8000c1e1900 */
/*0350*/ @!P1 LDG.E R10, [R6.64+0x8] ; /* 0x00000806060a9981 */
/* 0x000ee8000c1e1900 */
/*0360*/ @!P1 LDG.E R5, [R4.64] ; /* 0x0000000604059981 */
/* 0x000f22000c1e1900 */
/*0370*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c9224 */
/* 0x000fc400078e0008 */
/*0380*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e0008 */
/*0390*/ @!P1 IADD3 R13, R17, R13, R16 ; /* 0x0000000d110d9210 */
/* 0x004fc80007ffe010 */
/*03a0*/ @!P1 IADD3 R10, R10, R13, R14 ; /* 0x0000000d0a0a9210 */
/* 0x008fe20007ffe00e */
/*03b0*/ @!P1 IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d9424 */
/* 0x000fe400078e00ff */
/*03c0*/ @P1 IMAD.MOV.U32 R13, RZ, RZ, -0x1 ; /* 0xffffffffff0d1424 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P1 IMAD.IADD R10, R10, 0x1, R5 ; /* 0x000000010a0a9824 */
/* 0x010fe200078e0205 */
/*03e0*/ @P1 IADD3 R10, R17, R14, R16 ; /* 0x0000000e110a1210 */
/* 0x000fe20007ffe010 */
/*03f0*/ BRA 0x650 ; /* 0x0000025000007947 */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R10, [R14.64] ; /* 0x000000060e0a7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R6, [R6.64+0x8] ; /* 0x0000080606067981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040602057981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fc400078e00ff */
/*0440*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0450*/ IADD3 R10, R6, R10, R5 ; /* 0x0000000a060a7210 */
/* 0x004fe20007ffe005 */
/*0460*/ BRA 0x650 ; /* 0x000001e000007947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R6, [R6.64+0x8] ; /* 0x0000080606067981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R5, [R2.64+-0x4] ; /* 0xfffffc0602057981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R12, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000c7a10 */
/* 0x000fe20007ffe0ff */
/*04b0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0000 */
/*04c0*/ IADD3 R10, R6, R10, R5 ; /* 0x0000000a060a7210 */
/* 0x004fe20007ffe005 */
/*04d0*/ BRA 0x650 ; /* 0x0000017000007947 */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x000ea8000c1e1900 */
/*0500*/ LDG.E R7, [R2.64+-0x4] ; /* 0xfffffc0602077981 */
/* 0x000ea2000c1e1900 */
/*0510*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fc400078e00ff */
/*0520*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0530*/ IADD3 R10, R4, R10, R7 ; /* 0x0000000a040a7210 */
/* 0x004fe20007ffe007 */
/*0540*/ BRA 0x650 ; /* 0x0000010000007947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E R10, [R2.64+-0x4] ; /* 0xfffffc06020a7981 */
/* 0x000162000c1e1900 */
/*0560*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0570*/ IADD3 R12, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000c7a10 */
/* 0x000fe20007ffe0ff */
/*0580*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*0590*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0000 */
/*05a0*/ IMAD.U32 R13, RZ, RZ, UR4 ; /* 0x00000004ff0d7e24 */
/* 0x000fe2000f8e00ff */
/*05b0*/ BRA 0x650 ; /* 0x0000009000007947 */
/* 0x000fea0003800000 */
/*05c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x000162000c1e1900 */
/*05d0*/ IADD3 R8, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000087a10 */
/* 0x000fe20007ffe0ff */
/*05e0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0600*/ BRA 0x650 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0610*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x000162000c1e1900 */
/*0620*/ IADD3 R8, R0, c[0x0][0x170], RZ ; /* 0x00005c0000087a10 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0650*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0660*/ IMAD.IADD R6, R13, 0x1, R8 ; /* 0x000000010d067824 */
/* 0x000fe200078e0208 */
/*0670*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IMAD.WIDE R4, R12, R11, c[0x0][0x160] ; /* 0x000058000c047625 */
/* 0x000fc800078e020b */
/*0690*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe400078e020b */
/*06a0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ee8000c1e1900 */
/*06b0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ee2000c1e1900 */
/*06c0*/ LEA R8, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000087a11 */
/* 0x000fc800078210ff */
/*06d0*/ LEA.HI.X R9, R0, c[0x0][0x16c], R9, 0x2, P1 ; /* 0x00005b0000097a11 */
/* 0x000fe400008f1409 */
/*06e0*/ ISETP.NE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x004fe40003f05270 */
/*06f0*/ IADD3 R10, R6, R5, R10 ; /* 0x00000005060a7210 */
/* 0x028fc80007ffe00a */
/*0700*/ ISETP.LT.U32.AND P2, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fda0003f41070 */
/*0710*/ @!P0 BRA P2, 0x7d0 ; /* 0x000000b000008947 */
/* 0x000fea0001000000 */
/*0720*/ ISETP.GT.AND P1, PT, R10, 0x3, PT ; /* 0x000000030a00780c */
/* 0x000fda0003f24270 */
/*0730*/ @!P0 BRA P1, 0x7b0 ; /* 0x0000007000008947 */
/* 0x000fea0000800000 */
/*0740*/ LOP3.LUT R0, R10, 0x1, RZ, 0xfc, !PT ; /* 0x000000010a007812 */
/* 0x000fc800078efcff */
/*0750*/ ISETP.EQ.AND P0, PT, R0, 0x3, !P0 ; /* 0x000000030000780c */
/* 0x000fda0004702270 */
/*0760*/ @!P0 STG.E [R8.64], R3 ; /* 0x0000000308008986 */
/* 0x0001e2000c101906 */
/*0770*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x001fca00078e00ff */
/*0790*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101906 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101906 */
/*07c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07d0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101906 */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePiS_i
.globl _Z7computePiS_i
.p2align 8
.type _Z7computePiS_i,@function
_Z7computePiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[6:7], null, s14, s3, v[1:2]
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v6, v4
v_cmpx_gt_i32_e64 s7, v0
s_cbranch_execz .LBB0_41
s_load_b64 s[8:9], s[0:1], 0x0
v_or_b32_e32 v2, v4, v6
v_mad_u64_u32 v[0:1], null, v4, s7, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s10, exec_lo, s2
s_cbranch_execz .LBB0_27
s_add_i32 s13, s7, -1
v_cmp_eq_u32_e64 s2, 0, v6
v_cmp_eq_u32_e64 s3, s13, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s2, s3
s_xor_b32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_xor_b32 s11, exec_lo, s5
s_cbranch_execz .LBB0_24
v_cmp_eq_u32_e32 vcc_lo, s13, v6
s_and_b32 s4, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, -1
s_and_saveexec_b32 s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s12, exec_lo, s5
s_cbranch_execz .LBB0_21
v_cmp_eq_u32_e64 s6, 0, v4
v_cmp_lt_i32_e64 s4, 0, v6
v_cmp_gt_i32_e64 s5, s13, v6
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s6, s4, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, -1
s_and_saveexec_b32 s14, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s14
s_cbranch_execz .LBB0_18
s_and_b32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s5, s3
s_xor_b32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_xor_b32 s5, exec_lo, s4
s_cbranch_execz .LBB0_15
v_cmp_lt_i32_e64 s3, 0, v4
v_cmp_gt_i32_e64 s4, s13, v4
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, -1
s_and_saveexec_b32 s13, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s13, exec_lo, s13
s_cbranch_execz .LBB0_12
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s2, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v5, s2, s9, v2, s2
s_and_b32 s2, vcc_lo, s3
s_and_b32 s2, s4, s2
global_load_b32 v1, v[4:5], off offset:-4
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_xor_b32 s2, exec_lo, s3
s_cbranch_execz .LBB0_9
v_subrev_nc_u32_e32 v2, s7, v0
v_add_nc_u32_e32 v6, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_clause 0x1
global_load_b32 v8, v[4:5], off offset:4
global_load_b32 v9, v[2:3], off offset:-4
v_add_co_u32 v4, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v7, vcc_lo
s_clause 0x2
global_load_b64 v[2:3], v[2:3], off
global_load_b32 v6, v[4:5], off offset:-4
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(3)
v_add3_u32 v1, v8, v1, v9
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add3_u32 v1, v1, v2, v3
v_add_co_u32 v2, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_add3_u32 v7, v1, v6, v7
.LBB0_9:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_11
v_subrev_nc_u32_e32 v2, s7, v0
v_add_nc_u32_e32 v4, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
global_load_b32 v2, v[2:3], off offset:-4
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v1, v6, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v7, v1, v2, v7
v_add_co_u32 v2, vcc_lo, v4, -4
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v5, vcc_lo
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_12:
s_and_not1_saveexec_b32 s2, s13
s_cbranch_execz .LBB0_14
v_subrev_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, s7, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_clause 0x2
global_load_b32 v5, v[5:6], off offset:4
global_load_b64 v[1:2], v[1:2], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v1, v1, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v7, v1, v2, v6
v_add_co_u32 v2, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_15:
s_and_not1_saveexec_b32 s2, s5
s_cbranch_execz .LBB0_17
v_subrev_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
s_clause 0x2
global_load_b32 v7, v[3:4], off offset:-4
global_load_b32 v3, v[3:4], off offset:4
global_load_b64 v[1:2], v[5:6], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v3, v3, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v7, v3, v2, v1
v_add_co_u32 v2, vcc_lo, v5, -4
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v6, vcc_lo
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_18:
s_and_not1_saveexec_b32 s2, s6
s_cbranch_execz .LBB0_20
v_add_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
s_clause 0x3
global_load_b32 v1, v[3:4], off offset:-4
global_load_b32 v2, v[3:4], off offset:4
global_load_b32 v3, v[5:6], off offset:-4
global_load_b32 v4, v[5:6], off
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v1, v2, v1
v_add_co_u32 v2, vcc_lo, v5, 4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v7, v1, v3, v4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_21:
s_and_not1_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_23
v_subrev_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off offset:-4
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v2, v1
v_add_co_u32 v2, vcc_lo, v5, -4
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v6, vcc_lo
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_24:
s_and_not1_saveexec_b32 s2, s11
s_cbranch_execz .LBB0_26
v_subrev_nc_u32_e32 v2, s7, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off offset:4
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v2, v1
v_add_co_u32 v2, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v6, vcc_lo
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_27:
s_or_saveexec_b32 s2, s10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_29
v_add_nc_u32_e32 v2, s7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off offset:4
global_load_b32 v5, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v5, v4
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b32 v3, v[2:3], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v3, v7, v3
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s0, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s1, 1, v3
s_or_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_39
v_cmp_gt_i32_e64 s0, 4, v3
s_xor_b32 s5, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s5, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s0
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_36
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_and_b32_e32 v3, -2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 2, v3
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
s_or_b32 s0, s5, vcc_lo
s_and_saveexec_b32 s5, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s5
s_cbranch_execz .LBB0_33
global_store_b32 v[0:1], v2, off
.LBB0_33:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_35
v_mov_b32_e32 v2, 1
global_store_b32 v[0:1], v2, off
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_36:
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execz .LBB0_38
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_38:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_39:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_41
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_41:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePiS_i, .Lfunc_end0-_Z7computePiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000edb03_00000000-6_game.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7computePiS_iPiS_i
.type _Z29__device_stub__Z7computePiS_iPiS_i, @function
_Z29__device_stub__Z7computePiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7computePiS_iPiS_i, .-_Z29__device_stub__Z7computePiS_iPiS_i
.globl _Z7computePiS_i
.type _Z7computePiS_i, @function
_Z7computePiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7computePiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7computePiS_i, .-_Z7computePiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Start\n"
.LC2:
.string "-------\n"
.LC3:
.string " 0"
.LC4:
.string " 1"
.LC5:
.string "\n"
.LC6:
.string "\n Round %d \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Time taken for this computation = %f milliseconds\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $296, %rsp
.cfi_def_cfa_offset 352
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $0, 68(%rsp)
movl $0, 72(%rsp)
movl $1, 76(%rsp)
movl $0x00000000, 20(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 96(%rsp), %rbp
leaq 192(%rsp), %r14
movq %rbp, %r12
jmp .L12
.L36:
addq $16, %r12
cmpq %r14, %r12
je .L35
.L12:
leaq -16(%r12), %rbx
.L13:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
jmp .L36
.L35:
leaq 176(%rsp), %rax
movq %rax, 8(%rsp)
leaq 272(%rsp), %rdx
.L14:
movl $0, (%rax)
movl $0, 4(%rax)
movl $0, 8(%rax)
movl $0, 12(%rax)
addq $16, %rax
cmpq %rdx, %rax
jne .L14
leaq 24(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $96, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %r13
leaq .LC3(%rip), %r12
leaq .LC5(%rip), %r15
jmp .L15
.L16:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L17:
addq $4, %rbx
cmpq %rbp, %rbx
je .L37
.L18:
cmpl $0, (%rbx)
je .L16
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L37:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
cmpq %r14, %rbp
je .L27
.L15:
leaq -16(%rbp), %rbx
jmp .L18
.L27:
movl $0, 4(%rsp)
leaq .LC4(%rip), %r13
leaq .LC3(%rip), %r12
jmp .L19
.L40:
movq 32(%rsp), %rdi
movl $6, %edx
movq %rdi, %rsi
call _Z29__device_stub__Z7computePiS_iPiS_i
jmp .L20
.L22:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L23:
addq $4, %rbx
cmpq %rbx, %rbp
je .L38
.L24:
cmpl $0, (%rbx)
je .L22
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L38:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
cmpq %r15, %rbp
je .L25
.L21:
leaq -16(%rbp), %rbx
jmp .L24
.L25:
leaq 20(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, 4(%rsp)
movl 4(%rsp), %eax
cmpl $2, %eax
je .L39
.L19:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 56(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L20:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 32(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 176(%rsp), %rdi
movl $2, %ecx
movl $96, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
leaq 16(%rax), %rbp
leaq 112(%rax), %r15
leaq .LC5(%rip), %r14
jmp .L21
.L39:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7computePiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "game.hip"
.globl _Z22__device_stub__computePiS_i # -- Begin function _Z22__device_stub__computePiS_i
.p2align 4, 0x90
.type _Z22__device_stub__computePiS_i,@function
_Z22__device_stub__computePiS_i: # @_Z22__device_stub__computePiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__computePiS_i, .Lfunc_end0-_Z22__device_stub__computePiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 8(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 240(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader74
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $4, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $16, %rbx
cmpq $6, %r14
jne .LBB1_1
# %bb.4: # %.preheader72.preheader
xorps %xmm0, %xmm0
movaps %xmm0, 224(%rsp)
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
leaq 40(%rsp), %rdi
movl $96, %esi
callq hipMalloc
movq 40(%rsp), %rdi
leaq 240(%rsp), %rbx
movl $96, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $16, %rbx
cmpq $6, %r14
je .LBB1_10
.LBB1_5: # %.preheader71
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %r15d, %r15d
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_6 Depth=2
xorl %eax, %eax
callq printf
incq %r15
cmpq $4, %r15
je .LBB1_9
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
cmpl $0, (%rbx,%r15,4)
movl $.L.str.3, %edi
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=2
movl $.L.str.2, %edi
jmp .LBB1_8
.LBB1_10: # %.preheader70
leaq 144(%rsp), %rbp
leaq 8(%rsp), %r12
xorl %r13d, %r13d
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_11 Depth=1
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r12, %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leal 1(%r13), %eax
testl %r13d, %r13d
movl %eax, %r13d
jne .LBB1_20
.LBB1_11: # =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
# Child Loop BB1_15 Depth 3
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
xorl %edi, %edi
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movq 32(%rsp), %rax
movq %rax, 104(%rsp)
movq %rax, 96(%rsp)
movl $6, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z7computePiS_i, %edi
leaq 112(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13: # in Loop: Header=BB1_11 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $96, %esi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rsi
movl $96, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq %rbp, %r15
xorl %ebx, %ebx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_18: # in Loop: Header=BB1_14 Depth=2
movl $10, %edi
callq putchar@PLT
incq %rbx
addq $16, %r15
cmpq $6, %rbx
je .LBB1_19
.LBB1_14: # %.preheader
# Parent Loop BB1_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_15 Depth 3
xorl %r14d, %r14d
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_15 Depth=3
xorl %eax, %eax
callq printf
incq %r14
cmpq $4, %r14
je .LBB1_18
.LBB1_15: # Parent Loop BB1_11 Depth=1
# Parent Loop BB1_14 Depth=2
# => This Inner Loop Header: Depth=3
cmpl $0, (%r15,%r14,4)
movl $.L.str.3, %edi
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_15 Depth=3
movl $.L.str.2, %edi
jmp .LBB1_17
.LBB1_20:
xorl %eax, %eax
addq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePiS_i,@object # @_Z7computePiS_i
.section .rodata,"a",@progbits
.globl _Z7computePiS_i
.p2align 3, 0x0
_Z7computePiS_i:
.quad _Z22__device_stub__computePiS_i
.size _Z7computePiS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " 0"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " 1"
.size .L.str.3, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n Round %d \n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time taken for this computation = %f milliseconds\n\n"
.size .L.str.6, 52
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePiS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Start"
.size .Lstr, 6
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "-------"
.size .Lstr.2, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computePiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define W 500
#define H 500
#define TX 32
#define TY 32
__device__
unsigned char clip(int n){
return n > 255 ? 255: (n < 0 ? 0:n);
}
__global__
void distanceKernel(uchar4 *d_out, int w,int h, int2 pos){
const int c = blockIdx.x*blockDim.x + threadIdx.x;
const int r = blockIdx.y*blockDim.y + threadIdx.y;
const int i = r*w + c;
if ((c >= w)||(r >= h)) return;
const int d = sqrtf((c - pos.x)*(c - pos.x) + (r - pos.y)*(r - pos.y));
const unsigned char intensity = clip(255 - d);
d_out[i].x = intensity;
d_out[i].y = intensity;
d_out[i].z = 0;
d_out[i].z = 255;
}
int main(){
uchar4 *out = (uchar4 *)calloc(W*H, sizeof(uchar4));
uchar4 *d_out;
cudaMalloc(&d_out, W*H*sizeof(uchar4));
const int2 pos = {0, 0};
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
cudaMemcpy(out, d_out, W*H*sizeof(uchar4), cudaMemcpyDeviceToHost);
cudaFree(d_out);
free(out);
return 0;
} | code for sm_80
Function : _Z14distanceKernelP6uchar4ii4int2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, R0, -c[0x0][0x174], RZ ; /* 0x80005d0000047a10 */
/* 0x000fe20007ffe0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R2, R3, -c[0x0][0x170], RZ ; /* 0x80005c0003027a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ BSSY B0, 0x1e0 ; /* 0x0000010000007945 */
/* 0x000fe40003800000 */
/*00e0*/ IMAD R5, R4, R4, RZ ; /* 0x0000000404057224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD R5, R2, R2, R5 ; /* 0x0000000202057224 */
/* 0x000fcc00078e0205 */
/*0100*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e240000201400 */
/*0110*/ IADD3 R4, R5, -0xd000000, RZ ; /* 0xf300000005047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ MUFU.RSQ R2, R5 ; /* 0x0000000500027308 */
/* 0x0000620000001400 */
/*0130*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0140*/ @!P0 BRA 0x190 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0150*/ MOV R8, 0x170 ; /* 0x0000017000087802 */
/* 0x003fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000013000007944 */
/* 0x000fea0003c00000 */
/*0170*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R4, R5, R2 ; /* 0x0000000205047220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R2, R2, 0.5 ; /* 0x3f00000002027820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R5, -R4, R4, R5 ; /* 0x0000000404057223 */
/* 0x000fc80000000105 */
/*01c0*/ FFMA R4, R5, R2, R4 ; /* 0x0000000205047223 */
/* 0x000fe40000000004 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e22000020f100 */
/*01f0*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fe200078e0203 */
/*0200*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.5199184417724609375e-05 ; /* 0x000000ffff077435 */
/* 0x000fe200000001ff */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R2, -R4, 0xff, RZ ; /* 0x000000ff04027810 */
/* 0x001fc80007ffe1ff */
/*0230*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fc80007800200 */
/*0240*/ IMNMX R0, R2, 0xff, PT ; /* 0x000000ff02007817 */
/* 0x000fe20003800200 */
/*0250*/ IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0206 */
/*0260*/ PRMT R5, R0, 0x7604, R0 ; /* 0x0000760400057816 */
/* 0x000fe40000000000 */
/*0270*/ STG.E.U8 [R2.64+0x2], R7 ; /* 0x0000020702007986 */
/* 0x000fe8000c101104 */
/*0280*/ STG.E.U16 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101504 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*02b0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fe200078e0005 */
/*02c0*/ @!P0 BRA 0x3d0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*02d0*/ FSETP.GEU.FTZ.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fda0003f1e000 */
/*02e0*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*02f0*/ @!P0 BRA 0x3d0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f1c200 */
/*0310*/ @P0 FADD.FTZ R2, R5, 1 ; /* 0x3f80000005020421 */
/* 0x000fe20000010000 */
/*0320*/ @P0 BRA 0x3d0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f1d200 */
/*0340*/ @P0 FFMA R4, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005040823 */
/* 0x000fc800000000ff */
/*0350*/ @P0 MUFU.RSQ R7, R4 ; /* 0x0000000400070308 */
/* 0x000e240000001400 */
/*0360*/ @P0 FMUL.FTZ R9, R4, R7 ; /* 0x0000000704090220 */
/* 0x001fe40000410000 */
/*0370*/ @P0 FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007070820 */
/* 0x000fe40000410000 */
/*0380*/ @P0 FADD.FTZ R2, -R9, -RZ ; /* 0x800000ff09020221 */
/* 0x000fc80000010100 */
/*0390*/ @P0 FFMA R6, R9, R2, R4 ; /* 0x0000000209060223 */
/* 0x000fe40000000004 */
/*03a0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fe400078e0005 */
/*03b0*/ @P0 FFMA R6, R6, R7, R9 ; /* 0x0000000706060223 */
/* 0x000fc80000000009 */
/*03c0*/ @P0 FMUL.FTZ R2, R6, 2.3283064365386962891e-10 ; /* 0x2f80000006020820 */
/* 0x000fe40000410000 */
/*03d0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*03e0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fca0000000f00 */
/*03f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffc0004007950 */
/* 0x000fea0003c3ffff */
/*0400*/ BRA 0x400; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define W 500
#define H 500
#define TX 32
#define TY 32
__device__
unsigned char clip(int n){
return n > 255 ? 255: (n < 0 ? 0:n);
}
__global__
void distanceKernel(uchar4 *d_out, int w,int h, int2 pos){
const int c = blockIdx.x*blockDim.x + threadIdx.x;
const int r = blockIdx.y*blockDim.y + threadIdx.y;
const int i = r*w + c;
if ((c >= w)||(r >= h)) return;
const int d = sqrtf((c - pos.x)*(c - pos.x) + (r - pos.y)*(r - pos.y));
const unsigned char intensity = clip(255 - d);
d_out[i].x = intensity;
d_out[i].y = intensity;
d_out[i].z = 0;
d_out[i].z = 255;
}
int main(){
uchar4 *out = (uchar4 *)calloc(W*H, sizeof(uchar4));
uchar4 *d_out;
cudaMalloc(&d_out, W*H*sizeof(uchar4));
const int2 pos = {0, 0};
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
cudaMemcpy(out, d_out, W*H*sizeof(uchar4), cudaMemcpyDeviceToHost);
cudaFree(d_out);
free(out);
return 0;
} | .file "tmpxft_0003dc87_00000000-6_kernel_4_4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4clipi
.type _Z4clipi, @function
_Z4clipi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4clipi, .-_Z4clipi
.globl _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2
.type _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2, @function
_Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movq %rcx, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelP6uchar4ii4int2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2, .-_Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2
.globl _Z14distanceKernelP6uchar4ii4int2
.type _Z14distanceKernelP6uchar4ii4int2, @function
_Z14distanceKernelP6uchar4ii4int2:
.LFB2054:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rcx, 8(%rsp)
leaq 8(%rsp), %rcx
call _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z14distanceKernelP6uchar4ii4int2, .-_Z14distanceKernelP6uchar4ii4int2
.globl main
.type main, @function
main:
.LFB2028:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $250000, %edi
call calloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
movl $2, %ecx
movl $1000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $0, 8(%rsp)
movl $0, 12(%rsp)
leaq 8(%rsp), %rcx
movl $500, %edx
movl $500, %esi
movq (%rsp), %rdi
call _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14distanceKernelP6uchar4ii4int2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelP6uchar4ii4int2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define W 500
#define H 500
#define TX 32
#define TY 32
__device__
unsigned char clip(int n){
return n > 255 ? 255: (n < 0 ? 0:n);
}
__global__
void distanceKernel(uchar4 *d_out, int w,int h, int2 pos){
const int c = blockIdx.x*blockDim.x + threadIdx.x;
const int r = blockIdx.y*blockDim.y + threadIdx.y;
const int i = r*w + c;
if ((c >= w)||(r >= h)) return;
const int d = sqrtf((c - pos.x)*(c - pos.x) + (r - pos.y)*(r - pos.y));
const unsigned char intensity = clip(255 - d);
d_out[i].x = intensity;
d_out[i].y = intensity;
d_out[i].z = 0;
d_out[i].z = 255;
}
int main(){
uchar4 *out = (uchar4 *)calloc(W*H, sizeof(uchar4));
uchar4 *d_out;
cudaMalloc(&d_out, W*H*sizeof(uchar4));
const int2 pos = {0, 0};
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
cudaMemcpy(out, d_out, W*H*sizeof(uchar4), cudaMemcpyDeviceToHost);
cudaFree(d_out);
free(out);
return 0;
} | #include <hip/hip_runtime.h>
#define W 500
#define H 500
#define TX 32
#define TY 32
__device__
unsigned char clip(int n){
return n > 255 ? 255: (n < 0 ? 0:n);
}
__global__
void distanceKernel(uchar4 *d_out, int w,int h, int2 pos){
const int c = blockIdx.x*blockDim.x + threadIdx.x;
const int r = blockIdx.y*blockDim.y + threadIdx.y;
const int i = r*w + c;
if ((c >= w)||(r >= h)) return;
const int d = sqrtf((c - pos.x)*(c - pos.x) + (r - pos.y)*(r - pos.y));
const unsigned char intensity = clip(255 - d);
d_out[i].x = intensity;
d_out[i].y = intensity;
d_out[i].z = 0;
d_out[i].z = 255;
}
int main(){
uchar4 *out = (uchar4 *)calloc(W*H, sizeof(uchar4));
uchar4 *d_out;
hipMalloc(&d_out, W*H*sizeof(uchar4));
const int2 pos = {0, 0};
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
hipMemcpy(out, d_out, W*H*sizeof(uchar4), hipMemcpyDeviceToHost);
hipFree(d_out);
free(out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define W 500
#define H 500
#define TX 32
#define TY 32
__device__
unsigned char clip(int n){
return n > 255 ? 255: (n < 0 ? 0:n);
}
__global__
void distanceKernel(uchar4 *d_out, int w,int h, int2 pos){
const int c = blockIdx.x*blockDim.x + threadIdx.x;
const int r = blockIdx.y*blockDim.y + threadIdx.y;
const int i = r*w + c;
if ((c >= w)||(r >= h)) return;
const int d = sqrtf((c - pos.x)*(c - pos.x) + (r - pos.y)*(r - pos.y));
const unsigned char intensity = clip(255 - d);
d_out[i].x = intensity;
d_out[i].y = intensity;
d_out[i].z = 0;
d_out[i].z = 255;
}
int main(){
uchar4 *out = (uchar4 *)calloc(W*H, sizeof(uchar4));
uchar4 *d_out;
hipMalloc(&d_out, W*H*sizeof(uchar4));
const int2 pos = {0, 0};
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
hipMemcpy(out, d_out, W*H*sizeof(uchar4), hipMemcpyDeviceToHost);
hipFree(d_out);
free(out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.globl _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.p2align 8
.type _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE,@function
_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v2, s3, v1
v_subrev_nc_u32_e32 v5, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, v2
v_mad_u64_u32 v[3:4], null, v5, v5, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v3
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v2, v3, vcc_lo
v_sqrt_f32_e32 v2, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v2, v4
v_fma_f32 v7, -v5, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v2, v2, v3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v7
v_cndmask_b32_e64 v5, v2, v5, s2
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, 0x37800000, v5
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v5, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v4, v0
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mov_b32_e32 v3, 0xff
v_sub_nc_u32_e32 v2, 0xff, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_med3_i32 v2, v2, 0, 0xff
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v3, off offset:2
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, .Lfunc_end0-_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define W 500
#define H 500
#define TX 32
#define TY 32
__device__
unsigned char clip(int n){
return n > 255 ? 255: (n < 0 ? 0:n);
}
__global__
void distanceKernel(uchar4 *d_out, int w,int h, int2 pos){
const int c = blockIdx.x*blockDim.x + threadIdx.x;
const int r = blockIdx.y*blockDim.y + threadIdx.y;
const int i = r*w + c;
if ((c >= w)||(r >= h)) return;
const int d = sqrtf((c - pos.x)*(c - pos.x) + (r - pos.y)*(r - pos.y));
const unsigned char intensity = clip(255 - d);
d_out[i].x = intensity;
d_out[i].y = intensity;
d_out[i].z = 0;
d_out[i].z = 255;
}
int main(){
uchar4 *out = (uchar4 *)calloc(W*H, sizeof(uchar4));
uchar4 *d_out;
hipMalloc(&d_out, W*H*sizeof(uchar4));
const int2 pos = {0, 0};
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
hipMemcpy(out, d_out, W*H*sizeof(uchar4), hipMemcpyDeviceToHost);
hipFree(d_out);
free(out);
return 0;
} | .text
.file "kernel_4_4.hip"
.globl _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE # -- Begin function _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE,@function
_Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE: # @_Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rcx, 72(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, .Lfunc_end0-_Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $250000, %edi # imm = 0x3D090
movl $4, %esi
callq calloc
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq $0, 72(%rsp)
movq %rax, 64(%rsp)
movl $500, 12(%rsp) # imm = 0x1F4
movl $500, 8(%rsp) # imm = 0x1F4
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE,@object # @_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.section .rodata,"a",@progbits
.globl _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.p2align 3, 0x0
_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE:
.quad _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.size _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14distanceKernelP6uchar4ii4int2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, R0, -c[0x0][0x174], RZ ; /* 0x80005d0000047a10 */
/* 0x000fe20007ffe0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IADD3 R2, R3, -c[0x0][0x170], RZ ; /* 0x80005c0003027a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ BSSY B0, 0x1e0 ; /* 0x0000010000007945 */
/* 0x000fe40003800000 */
/*00e0*/ IMAD R5, R4, R4, RZ ; /* 0x0000000404057224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD R5, R2, R2, R5 ; /* 0x0000000202057224 */
/* 0x000fcc00078e0205 */
/*0100*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e240000201400 */
/*0110*/ IADD3 R4, R5, -0xd000000, RZ ; /* 0xf300000005047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ MUFU.RSQ R2, R5 ; /* 0x0000000500027308 */
/* 0x0000620000001400 */
/*0130*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0140*/ @!P0 BRA 0x190 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0150*/ MOV R8, 0x170 ; /* 0x0000017000087802 */
/* 0x003fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000013000007944 */
/* 0x000fea0003c00000 */
/*0170*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R4, R5, R2 ; /* 0x0000000205047220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R2, R2, 0.5 ; /* 0x3f00000002027820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R5, -R4, R4, R5 ; /* 0x0000000404057223 */
/* 0x000fc80000000105 */
/*01c0*/ FFMA R4, R5, R2, R4 ; /* 0x0000000205047223 */
/* 0x000fe40000000004 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e22000020f100 */
/*01f0*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fe200078e0203 */
/*0200*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.5199184417724609375e-05 ; /* 0x000000ffff077435 */
/* 0x000fe200000001ff */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R2, -R4, 0xff, RZ ; /* 0x000000ff04027810 */
/* 0x001fc80007ffe1ff */
/*0230*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fc80007800200 */
/*0240*/ IMNMX R0, R2, 0xff, PT ; /* 0x000000ff02007817 */
/* 0x000fe20003800200 */
/*0250*/ IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0206 */
/*0260*/ PRMT R5, R0, 0x7604, R0 ; /* 0x0000760400057816 */
/* 0x000fe40000000000 */
/*0270*/ STG.E.U8 [R2.64+0x2], R7 ; /* 0x0000020702007986 */
/* 0x000fe8000c101104 */
/*0280*/ STG.E.U16 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101504 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*02b0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fe200078e0005 */
/*02c0*/ @!P0 BRA 0x3d0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*02d0*/ FSETP.GEU.FTZ.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fda0003f1e000 */
/*02e0*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*02f0*/ @!P0 BRA 0x3d0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f1c200 */
/*0310*/ @P0 FADD.FTZ R2, R5, 1 ; /* 0x3f80000005020421 */
/* 0x000fe20000010000 */
/*0320*/ @P0 BRA 0x3d0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f1d200 */
/*0340*/ @P0 FFMA R4, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005040823 */
/* 0x000fc800000000ff */
/*0350*/ @P0 MUFU.RSQ R7, R4 ; /* 0x0000000400070308 */
/* 0x000e240000001400 */
/*0360*/ @P0 FMUL.FTZ R9, R4, R7 ; /* 0x0000000704090220 */
/* 0x001fe40000410000 */
/*0370*/ @P0 FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007070820 */
/* 0x000fe40000410000 */
/*0380*/ @P0 FADD.FTZ R2, -R9, -RZ ; /* 0x800000ff09020221 */
/* 0x000fc80000010100 */
/*0390*/ @P0 FFMA R6, R9, R2, R4 ; /* 0x0000000209060223 */
/* 0x000fe40000000004 */
/*03a0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fe400078e0005 */
/*03b0*/ @P0 FFMA R6, R6, R7, R9 ; /* 0x0000000706060223 */
/* 0x000fc80000000009 */
/*03c0*/ @P0 FMUL.FTZ R2, R6, 2.3283064365386962891e-10 ; /* 0x2f80000006020820 */
/* 0x000fe40000410000 */
/*03d0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*03e0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fca0000000f00 */
/*03f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffc0004007950 */
/* 0x000fea0003c3ffff */
/*0400*/ BRA 0x400; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.globl _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.p2align 8
.type _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE,@function
_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v2, s3, v1
v_subrev_nc_u32_e32 v5, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, v2
v_mad_u64_u32 v[3:4], null, v5, v5, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v3
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v2, v3, vcc_lo
v_sqrt_f32_e32 v2, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v2, v4
v_fma_f32 v7, -v5, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v2, v2, v3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v7
v_cndmask_b32_e64 v5, v2, v5, s2
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, 0x37800000, v5
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v5, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v4, v0
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mov_b32_e32 v3, 0xff
v_sub_nc_u32_e32 v2, 0xff, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_med3_i32 v2, v2, 0, 0xff
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v3, off offset:2
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, .Lfunc_end0-_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003dc87_00000000-6_kernel_4_4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4clipi
.type _Z4clipi, @function
_Z4clipi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4clipi, .-_Z4clipi
.globl _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2
.type _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2, @function
_Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movq %rcx, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelP6uchar4ii4int2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2, .-_Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2
.globl _Z14distanceKernelP6uchar4ii4int2
.type _Z14distanceKernelP6uchar4ii4int2, @function
_Z14distanceKernelP6uchar4ii4int2:
.LFB2054:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rcx, 8(%rsp)
leaq 8(%rsp), %rcx
call _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z14distanceKernelP6uchar4ii4int2, .-_Z14distanceKernelP6uchar4ii4int2
.globl main
.type main, @function
main:
.LFB2028:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $250000, %edi
call calloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
movl $2, %ecx
movl $1000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $0, 8(%rsp)
movl $0, 12(%rsp)
leaq 8(%rsp), %rcx
movl $500, %edx
movl $500, %esi
movq (%rsp), %rdi
call _Z47__device_stub__Z14distanceKernelP6uchar4ii4int2P6uchar4iiR4int2
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14distanceKernelP6uchar4ii4int2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelP6uchar4ii4int2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_4_4.hip"
.globl _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE # -- Begin function _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE,@function
_Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE: # @_Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rcx, 72(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, .Lfunc_end0-_Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $250000, %edi # imm = 0x3D090
movl $4, %esi
callq calloc
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq $0, 72(%rsp)
movq %rax, 64(%rsp)
movl $500, 12(%rsp) # imm = 0x1F4
movl $500, 8(%rsp) # imm = 0x1F4
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE,@object # @_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.section .rodata,"a",@progbits
.globl _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.p2align 3, 0x0
_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE:
.quad _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.size _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelP15HIP_vector_typeIhLj4EEiiS_IiLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = a[i] + b[i];
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c;
double *d_a, *d_b, *d_c;
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++)
{
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
cudaMalloc((void**)&d_a, sz_in_bytes);
cudaMalloc((void**)&d_b, 0);
cudaMalloc((void**)&d_c, sz_in_bytes);
cudaMemcpy(d_a, h_a, sz_in_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sz_in_bytes, cudaMemcpyHostToDevice);
dim3 dimBlock(64, 1, 1);
dim3 dimGrid(10, 1, 1);
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
cudaMemcpy(h_c, d_c, sz_in_bytes, cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// Verifying
double err = 0, norm = 0;
for(int i = 0 ; i < N ; i++)
{
double err_loc = fabs(h_c[i] - (h_a[i]+h_b[i]));
err += err_loc;
norm += fabs(h_c[i]);
}
if (err/norm < 1.e-16)
{
printf("SUCCESS (Relative error : %.3e)\n", err/norm);
}
else
{
printf("ERROR (Relative error : %.3e)\n", err/norm);
}
free(h_a);
free(h_b);
free(h_c);
return 0;
} | code for sm_80
Function : _Z6kernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0209 */
/*0070*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00b0*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */
/* 0x004e0e0000000004 */
/*00c0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = a[i] + b[i];
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c;
double *d_a, *d_b, *d_c;
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++)
{
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
cudaMalloc((void**)&d_a, sz_in_bytes);
cudaMalloc((void**)&d_b, 0);
cudaMalloc((void**)&d_c, sz_in_bytes);
cudaMemcpy(d_a, h_a, sz_in_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sz_in_bytes, cudaMemcpyHostToDevice);
dim3 dimBlock(64, 1, 1);
dim3 dimGrid(10, 1, 1);
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
cudaMemcpy(h_c, d_c, sz_in_bytes, cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// Verifying
double err = 0, norm = 0;
for(int i = 0 ; i < N ; i++)
{
double err_loc = fabs(h_c[i] - (h_a[i]+h_b[i]));
err += err_loc;
norm += fabs(h_c[i]);
}
if (err/norm < 1.e-16)
{
printf("SUCCESS (Relative error : %.3e)\n", err/norm);
}
else
{
printf("ERROR (Relative error : %.3e)\n", err/norm);
}
free(h_a);
free(h_b);
free(h_c);
return 0;
} | .file "tmpxft_0007d8b2_00000000-6_err1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6kernelPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
.globl _Z6kernelPdS_S_i
.type _Z6kernelPdS_S_i, @function
_Z6kernelPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPdS_S_i, .-_Z6kernelPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "SUCCESS (Relative error : %.3e)\n"
.align 8
.LC5:
.string "ERROR (Relative error : %.3e)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8000, %edi
call malloc@PLT
movq %rax, %rbp
movl $8000, %edi
call malloc@PLT
movq %rax, %rbx
movl $8000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movapd %xmm0, %xmm2
addsd %xmm1, %xmm2
movapd %xmm1, %xmm3
divsd %xmm2, %xmm3
movsd %xmm3, 0(%rbp,%rax,8)
subsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $0, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 32(%rsp)
movl $1, 36(%rsp)
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
movl $2, %ecx
movl $8000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
pxor %xmm4, %xmm4
movapd %xmm4, %xmm0
movq .LC2(%rip), %xmm5
.L14:
movsd (%r12,%rax), %xmm1
movsd 0(%rbp,%rax), %xmm3
addsd (%rbx,%rax), %xmm3
movapd %xmm1, %xmm2
subsd %xmm3, %xmm2
andpd %xmm5, %xmm2
addsd %xmm2, %xmm0
andpd %xmm5, %xmm1
addsd %xmm1, %xmm4
addq $8, %rax
cmpq $8000, %rax
jne .L14
divsd %xmm4, %xmm0
movsd .LC3(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L22
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L17:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $1000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
jmp .L13
.L22:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L17
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "_Z6kernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC3:
.long -1747416644
.long 1016910514
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = a[i] + b[i];
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c;
double *d_a, *d_b, *d_c;
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++)
{
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
cudaMalloc((void**)&d_a, sz_in_bytes);
cudaMalloc((void**)&d_b, 0);
cudaMalloc((void**)&d_c, sz_in_bytes);
cudaMemcpy(d_a, h_a, sz_in_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sz_in_bytes, cudaMemcpyHostToDevice);
dim3 dimBlock(64, 1, 1);
dim3 dimGrid(10, 1, 1);
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
cudaMemcpy(h_c, d_c, sz_in_bytes, cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// Verifying
double err = 0, norm = 0;
for(int i = 0 ; i < N ; i++)
{
double err_loc = fabs(h_c[i] - (h_a[i]+h_b[i]));
err += err_loc;
norm += fabs(h_c[i]);
}
if (err/norm < 1.e-16)
{
printf("SUCCESS (Relative error : %.3e)\n", err/norm);
}
else
{
printf("ERROR (Relative error : %.3e)\n", err/norm);
}
free(h_a);
free(h_b);
free(h_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = a[i] + b[i];
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c;
double *d_a, *d_b, *d_c;
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++)
{
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
hipMalloc((void**)&d_a, sz_in_bytes);
hipMalloc((void**)&d_b, 0);
hipMalloc((void**)&d_c, sz_in_bytes);
hipMemcpy(d_a, h_a, sz_in_bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sz_in_bytes, hipMemcpyHostToDevice);
dim3 dimBlock(64, 1, 1);
dim3 dimGrid(10, 1, 1);
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
hipMemcpy(h_c, d_c, sz_in_bytes, hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// Verifying
double err = 0, norm = 0;
for(int i = 0 ; i < N ; i++)
{
double err_loc = fabs(h_c[i] - (h_a[i]+h_b[i]));
err += err_loc;
norm += fabs(h_c[i]);
}
if (err/norm < 1.e-16)
{
printf("SUCCESS (Relative error : %.3e)\n", err/norm);
}
else
{
printf("ERROR (Relative error : %.3e)\n", err/norm);
}
free(h_a);
free(h_b);
free(h_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = a[i] + b[i];
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c;
double *d_a, *d_b, *d_c;
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++)
{
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
hipMalloc((void**)&d_a, sz_in_bytes);
hipMalloc((void**)&d_b, 0);
hipMalloc((void**)&d_c, sz_in_bytes);
hipMemcpy(d_a, h_a, sz_in_bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sz_in_bytes, hipMemcpyHostToDevice);
dim3 dimBlock(64, 1, 1);
dim3 dimGrid(10, 1, 1);
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
hipMemcpy(h_c, d_c, sz_in_bytes, hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// Verifying
double err = 0, norm = 0;
for(int i = 0 ; i < N ; i++)
{
double err_loc = fabs(h_c[i] - (h_a[i]+h_b[i]));
err += err_loc;
norm += fabs(h_c[i]);
}
if (err/norm < 1.e-16)
{
printf("SUCCESS (Relative error : %.3e)\n", err/norm);
}
else
{
printf("ERROR (Relative error : %.3e)\n", err/norm);
}
free(h_a);
free(h_b);
free(h_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPdS_S_i
.globl _Z6kernelPdS_S_i
.p2align 8
.type _Z6kernelPdS_S_i,@function
_Z6kernelPdS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPdS_S_i, .Lfunc_end0-_Z6kernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
c[i] = a[i] + b[i];
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c;
double *d_a, *d_b, *d_c;
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++)
{
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
hipMalloc((void**)&d_a, sz_in_bytes);
hipMalloc((void**)&d_b, 0);
hipMalloc((void**)&d_c, sz_in_bytes);
hipMemcpy(d_a, h_a, sz_in_bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sz_in_bytes, hipMemcpyHostToDevice);
dim3 dimBlock(64, 1, 1);
dim3 dimGrid(10, 1, 1);
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
hipMemcpy(h_c, d_c, sz_in_bytes, hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// Verifying
double err = 0, norm = 0;
for(int i = 0 ; i < N ; i++)
{
double err_loc = fabs(h_c[i] - (h_a[i]+h_b[i]));
err += err_loc;
norm += fabs(h_c[i]);
}
if (err/norm < 1.e-16)
{
printf("SUCCESS (Relative error : %.3e)\n", err/norm);
}
else
{
printf("ERROR (Relative error : %.3e)\n", err/norm);
}
free(h_a);
free(h_b);
free(h_c);
return 0;
} | .text
.file "err1.hip"
.globl _Z21__device_stub__kernelPdS_S_i # -- Begin function _Z21__device_stub__kernelPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdS_S_i,@function
_Z21__device_stub__kernelPdS_S_i: # @_Z21__device_stub__kernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdS_S_i, .Lfunc_end0-_Z21__device_stub__kernelPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.LCPI1_1:
.quad 0xbff0000000000000 # double -1
.LCPI1_3:
.quad 0x3c9cd2b297d889bc # double 9.9999999999999997E-17
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %rbx
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r14
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r15
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %eax, %xmm2
movapd %xmm2, %xmm3
addsd %xmm0, %xmm3
movapd %xmm0, %xmm4
divsd %xmm3, %xmm4
movsd %xmm4, (%rbx,%rax,8)
addsd %xmm1, %xmm2
divsd %xmm3, %xmm2
movsd %xmm2, (%r14,%rax,8)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movq 24(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 54(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6kernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorpd %xmm1, %xmm1
xorl %eax, %eax
movapd .LCPI1_2(%rip), %xmm2 # xmm2 = [NaN,NaN]
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movsd (%r15,%rax,8), %xmm3 # xmm3 = mem[0],zero
movsd (%rbx,%rax,8), %xmm4 # xmm4 = mem[0],zero
addsd (%r14,%rax,8), %xmm4
movapd %xmm3, %xmm5
subsd %xmm4, %xmm5
andpd %xmm2, %xmm5
addsd %xmm5, %xmm0
andpd %xmm2, %xmm3
addsd %xmm3, %xmm1
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_5
# %bb.6:
divsd %xmm1, %xmm0
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
movl $.L.str, %eax
movl $.L.str.1, %edi
cmovaq %rax, %rdi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdS_S_i,@object # @_Z6kernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6kernelPdS_S_i
.p2align 3, 0x0
_Z6kernelPdS_S_i:
.quad _Z21__device_stub__kernelPdS_S_i
.size _Z6kernelPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "SUCCESS (Relative error : %.3e)\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR (Relative error : %.3e)\n"
.size .L.str.1, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0209 */
/*0070*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00b0*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */
/* 0x004e0e0000000004 */
/*00c0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPdS_S_i
.globl _Z6kernelPdS_S_i
.p2align 8
.type _Z6kernelPdS_S_i,@function
_Z6kernelPdS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPdS_S_i, .Lfunc_end0-_Z6kernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007d8b2_00000000-6_err1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6kernelPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
.globl _Z6kernelPdS_S_i
.type _Z6kernelPdS_S_i, @function
_Z6kernelPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPdS_S_i, .-_Z6kernelPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "SUCCESS (Relative error : %.3e)\n"
.align 8
.LC5:
.string "ERROR (Relative error : %.3e)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8000, %edi
call malloc@PLT
movq %rax, %rbp
movl $8000, %edi
call malloc@PLT
movq %rax, %rbx
movl $8000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movapd %xmm0, %xmm2
addsd %xmm1, %xmm2
movapd %xmm1, %xmm3
divsd %xmm2, %xmm3
movsd %xmm3, 0(%rbp,%rax,8)
subsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $0, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 32(%rsp)
movl $1, 36(%rsp)
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L13:
movl $2, %ecx
movl $8000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
pxor %xmm4, %xmm4
movapd %xmm4, %xmm0
movq .LC2(%rip), %xmm5
.L14:
movsd (%r12,%rax), %xmm1
movsd 0(%rbp,%rax), %xmm3
addsd (%rbx,%rax), %xmm3
movapd %xmm1, %xmm2
subsd %xmm3, %xmm2
andpd %xmm5, %xmm2
addsd %xmm2, %xmm0
andpd %xmm5, %xmm1
addsd %xmm1, %xmm4
addq $8, %rax
cmpq $8000, %rax
jne .L14
divsd %xmm4, %xmm0
movsd .LC3(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L22
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L17:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $1000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
jmp .L13
.L22:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L17
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "_Z6kernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC3:
.long -1747416644
.long 1016910514
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "err1.hip"
.globl _Z21__device_stub__kernelPdS_S_i # -- Begin function _Z21__device_stub__kernelPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdS_S_i,@function
_Z21__device_stub__kernelPdS_S_i: # @_Z21__device_stub__kernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdS_S_i, .Lfunc_end0-_Z21__device_stub__kernelPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.LCPI1_1:
.quad 0xbff0000000000000 # double -1
.LCPI1_3:
.quad 0x3c9cd2b297d889bc # double 9.9999999999999997E-17
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %rbx
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r14
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r15
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %eax, %xmm2
movapd %xmm2, %xmm3
addsd %xmm0, %xmm3
movapd %xmm0, %xmm4
divsd %xmm3, %xmm4
movsd %xmm4, (%rbx,%rax,8)
addsd %xmm1, %xmm2
divsd %xmm3, %xmm2
movsd %xmm2, (%r14,%rax,8)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movq 24(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 54(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6kernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorpd %xmm1, %xmm1
xorl %eax, %eax
movapd .LCPI1_2(%rip), %xmm2 # xmm2 = [NaN,NaN]
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movsd (%r15,%rax,8), %xmm3 # xmm3 = mem[0],zero
movsd (%rbx,%rax,8), %xmm4 # xmm4 = mem[0],zero
addsd (%r14,%rax,8), %xmm4
movapd %xmm3, %xmm5
subsd %xmm4, %xmm5
andpd %xmm2, %xmm5
addsd %xmm5, %xmm0
andpd %xmm2, %xmm3
addsd %xmm3, %xmm1
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_5
# %bb.6:
divsd %xmm1, %xmm0
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
movl $.L.str, %eax
movl $.L.str.1, %edi
cmovaq %rax, %rdi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdS_S_i,@object # @_Z6kernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6kernelPdS_S_i
.p2align 3, 0x0
_Z6kernelPdS_S_i:
.quad _Z21__device_stub__kernelPdS_S_i
.size _Z6kernelPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "SUCCESS (Relative error : %.3e)\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR (Relative error : %.3e)\n"
.size .L.str.1, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kInRangeExc(float* gData, float lower, float upper, float* target, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = idx; i < numElements; i += blockDim.x * gridDim.x)
target[i] = gData[i] > lower && gData[i] < upper;
} | code for sm_80
Function : _Z11kInRangeExcPfffS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0005 */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*00d0*/ FSETP.GEU.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0b */
/* 0x004fc80003f0e000 */
/*00e0*/ FSETP.GT.AND P0, PT, R2, c[0x0][0x168], !P0 ; /* 0x00005a0002007a0b */
/* 0x000fc80004704000 */
/*00f0*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fe40004000000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0110*/ I2F.U32 R7, R6 ; /* 0x0000000600077306 */
/* 0x000e240000201000 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011f2000c101904 */
/*0130*/ @!P0 BRA 0x70 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kInRangeExc(float* gData, float lower, float upper, float* target, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = idx; i < numElements; i += blockDim.x * gridDim.x)
target[i] = gData[i] > lower && gData[i] < upper;
} | .file "tmpxft_0006eda9_00000000-6_kInRangeExc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j
.type _Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j, @function
_Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kInRangeExcPfffS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j, .-_Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j
.globl _Z11kInRangeExcPfffS_j
.type _Z11kInRangeExcPfffS_j, @function
_Z11kInRangeExcPfffS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kInRangeExcPfffS_j, .-_Z11kInRangeExcPfffS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kInRangeExcPfffS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kInRangeExcPfffS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kInRangeExc(float* gData, float lower, float upper, float* target, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = idx; i < numElements; i += blockDim.x * gridDim.x)
target[i] = gData[i] > lower && gData[i] < upper;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kInRangeExc(float* gData, float lower, float upper, float* target, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = idx; i < numElements; i += blockDim.x * gridDim.x)
target[i] = gData[i] > lower && gData[i] < upper;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kInRangeExc(float* gData, float lower, float upper, float* target, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = idx; i < numElements; i += blockDim.x * gridDim.x)
target[i] = gData[i] > lower && gData[i] < upper;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kInRangeExcPfffS_j
.globl _Z11kInRangeExcPfffS_j
.p2align 8
.type _Z11kInRangeExcPfffS_j,@function
_Z11kInRangeExcPfffS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s10, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s11
s_mov_b32 s11, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
v_add_co_u32 v5, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v1
v_add_co_u32 v3, s2, s6, v3
global_load_b32 v0, v[5:6], off
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e64 s0, s4, v0
v_cmp_gt_f32_e64 s1, s5, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, s1
s_or_b32 s11, vcc_lo, s11
v_cndmask_b32_e64 v0, 0, 1.0, s0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kInRangeExcPfffS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kInRangeExcPfffS_j, .Lfunc_end0-_Z11kInRangeExcPfffS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kInRangeExcPfffS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kInRangeExcPfffS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kInRangeExc(float* gData, float lower, float upper, float* target, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = idx; i < numElements; i += blockDim.x * gridDim.x)
target[i] = gData[i] > lower && gData[i] < upper;
} | .text
.file "kInRangeExc.hip"
.globl _Z26__device_stub__kInRangeExcPfffS_j # -- Begin function _Z26__device_stub__kInRangeExcPfffS_j
.p2align 4, 0x90
.type _Z26__device_stub__kInRangeExcPfffS_j,@function
_Z26__device_stub__kInRangeExcPfffS_j: # @_Z26__device_stub__kInRangeExcPfffS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kInRangeExcPfffS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__kInRangeExcPfffS_j, .Lfunc_end0-_Z26__device_stub__kInRangeExcPfffS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kInRangeExcPfffS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kInRangeExcPfffS_j,@object # @_Z11kInRangeExcPfffS_j
.section .rodata,"a",@progbits
.globl _Z11kInRangeExcPfffS_j
.p2align 3, 0x0
_Z11kInRangeExcPfffS_j:
.quad _Z26__device_stub__kInRangeExcPfffS_j
.size _Z11kInRangeExcPfffS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kInRangeExcPfffS_j"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kInRangeExcPfffS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kInRangeExcPfffS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11kInRangeExcPfffS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0005 */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*00d0*/ FSETP.GEU.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0b */
/* 0x004fc80003f0e000 */
/*00e0*/ FSETP.GT.AND P0, PT, R2, c[0x0][0x168], !P0 ; /* 0x00005a0002007a0b */
/* 0x000fc80004704000 */
/*00f0*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fe40004000000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0110*/ I2F.U32 R7, R6 ; /* 0x0000000600077306 */
/* 0x000e240000201000 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011f2000c101904 */
/*0130*/ @!P0 BRA 0x70 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kInRangeExcPfffS_j
.globl _Z11kInRangeExcPfffS_j
.p2align 8
.type _Z11kInRangeExcPfffS_j,@function
_Z11kInRangeExcPfffS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s10, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s11
s_mov_b32 s11, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
v_add_co_u32 v5, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v1
v_add_co_u32 v3, s2, s6, v3
global_load_b32 v0, v[5:6], off
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e64 s0, s4, v0
v_cmp_gt_f32_e64 s1, s5, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, s1
s_or_b32 s11, vcc_lo, s11
v_cndmask_b32_e64 v0, 0, 1.0, s0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kInRangeExcPfffS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kInRangeExcPfffS_j, .Lfunc_end0-_Z11kInRangeExcPfffS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kInRangeExcPfffS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kInRangeExcPfffS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006eda9_00000000-6_kInRangeExc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j
.type _Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j, @function
_Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kInRangeExcPfffS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j, .-_Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j
.globl _Z11kInRangeExcPfffS_j
.type _Z11kInRangeExcPfffS_j, @function
_Z11kInRangeExcPfffS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11kInRangeExcPfffS_jPfffS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kInRangeExcPfffS_j, .-_Z11kInRangeExcPfffS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kInRangeExcPfffS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kInRangeExcPfffS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kInRangeExc.hip"
.globl _Z26__device_stub__kInRangeExcPfffS_j # -- Begin function _Z26__device_stub__kInRangeExcPfffS_j
.p2align 4, 0x90
.type _Z26__device_stub__kInRangeExcPfffS_j,@function
_Z26__device_stub__kInRangeExcPfffS_j: # @_Z26__device_stub__kInRangeExcPfffS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kInRangeExcPfffS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__kInRangeExcPfffS_j, .Lfunc_end0-_Z26__device_stub__kInRangeExcPfffS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kInRangeExcPfffS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kInRangeExcPfffS_j,@object # @_Z11kInRangeExcPfffS_j
.section .rodata,"a",@progbits
.globl _Z11kInRangeExcPfffS_j
.p2align 3, 0x0
_Z11kInRangeExcPfffS_j:
.quad _Z26__device_stub__kInRangeExcPfffS_j
.size _Z11kInRangeExcPfffS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kInRangeExcPfffS_j"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kInRangeExcPfffS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kInRangeExcPfffS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ void kNMLUpdate1_kernel( int numAtoms, int paddedNumAtoms, float tau, float dt, float kT, float4 *posq, float4 *posqP, float4 *velm, long long *force, const float4 *__restrict__ random, unsigned int randomIndex ) {
/* Update the velocity.*/
const float vscale = exp( -dt / tau );
const float fscale = ( 1.0f - vscale ) * tau;
const float noisescale = sqrt( kT * ( 1 - vscale * vscale ) );
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float4 n = random[randomIndex + blockIdx.x * blockDim.x + threadIdx.x];
const float4 randomNoise = make_float4( n.x * noisescale, n.y * noisescale, n.z * noisescale, n.w * noisescale );
const float sqrtInvMass = sqrt( velm[atom].w );
float4 v = velm[atom];
float fx = ( float )force[atom] / ( float )0x100000000;
float fy = ( float )force[atom + 1 * paddedNumAtoms] / ( float )0x100000000;
float fz = ( float )force[atom + 2 * paddedNumAtoms] / ( float )0x100000000;
v.x = ( vscale * v.x ) + ( fscale * fx * v.w ) + ( randomNoise.x * sqrtInvMass );
v.y = ( vscale * v.y ) + ( fscale * fy * v.w ) + ( randomNoise.y * sqrtInvMass );
v.z = ( vscale * v.z ) + ( fscale * fz * v.w ) + ( randomNoise.z * sqrtInvMass );
velm[atom] = v;
}
}
extern "C" __global__ void kNMLUpdate2_kernel( int numAtoms, int numModes, float4 *velm, float4 *modes, float *modeWeights ) {
extern __shared__ float dotBuffer[];
for( int mode = blockIdx.x; mode < numModes; mode += gridDim.x ) {
/* Compute the projection of the mass weighted velocity onto one normal mode vector. */
float dot = 0.0f;
for( int atom = threadIdx.x; atom < numAtoms; atom += blockDim.x ) {
const int modePos = mode * numAtoms + atom;
const float scale = 1.0f / sqrt( velm[atom].w );
float4 v = velm[atom];
float4 m = modes[modePos];
dot += scale * ( v.x * m.x + v.y * m.y + v.z * m.z );
}
dotBuffer[threadIdx.x] = dot;
__syncthreads();
if( threadIdx.x == 0 ) {
float sum = 0;
for( int i = 0; i < blockDim.x; i++ ) {
sum += dotBuffer[i];
}
modeWeights[mode] = sum;
}
}
}
extern "C" __global__ void kNMLUpdate3_kernel( int numAtoms, int numModes, float dt, float4 *posq, float4 *velm, float4 *modes, float *modeWeights, float4 *noiseVal ) {
/* Load the weights into shared memory. */
extern __shared__ float weightBuffer[];
for( int mode = threadIdx.x; mode < numModes; mode += blockDim.x ) {
weightBuffer[mode] = modeWeights[mode];
}
__syncthreads();
/* Compute the projected velocities and update the atom positions. */
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float invMass = velm[atom].w, scale = sqrt( invMass );
float3 v = make_float3( 0.0f, 0.0f, 0.0f );
for( int mode = 0; mode < numModes; mode++ ) {
float4 m = modes[mode * numAtoms + atom];
float weight = weightBuffer[mode];
v.x += m.x * weight;
v.y += m.y * weight;
v.z += m.z * weight;
}
v.x *= scale;
v.y *= scale;
v.z *= scale;
velm[atom] = make_float4( v.x, v.y, v.z, invMass );
float4 pos = posq[atom];
/* Add Step */
pos.x += dt * v.x;
pos.y += dt * v.y;
pos.z += dt * v.z;
#ifdef FAST_NOISE
/* Remove Noise */
pos.x -= noiseVal[atom].x;
pos.y -= noiseVal[atom].y;
pos.z -= noiseVal[atom].z;
#endif
posq[atom] = pos;
}
} | .file "tmpxft_0015eaea_00000000-6_NMLupdates_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j
.type _Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j, @function
_Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movss %xmm0, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 52(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movq 256(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 216(%rsp)
leaq 264(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq kNMLUpdate1_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j, .-_Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j
.globl kNMLUpdate1_kernel
.type kNMLUpdate1_kernel, @function
kNMLUpdate1_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kNMLUpdate1_kernel, .-kNMLUpdate1_kernel
.globl _Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf
.type _Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf, @function
_Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq kNMLUpdate2_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf, .-_Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf
.globl kNMLUpdate2_kernel
.type kNMLUpdate2_kernel, @function
kNMLUpdate2_kernel:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size kNMLUpdate2_kernel, .-kNMLUpdate2_kernel
.globl _Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_
.type _Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_, @function
_Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_:
.LFB2055:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movss %xmm0, 52(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq kNMLUpdate3_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_, .-_Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_
.globl kNMLUpdate3_kernel
.type kNMLUpdate3_kernel, @function
kNMLUpdate3_kernel:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size kNMLUpdate3_kernel, .-kNMLUpdate3_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kNMLUpdate3_kernel"
.LC1:
.string "kNMLUpdate2_kernel"
.LC2:
.string "kNMLUpdate1_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kNMLUpdate3_kernel(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq kNMLUpdate2_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq kNMLUpdate1_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ void kNMLUpdate1_kernel( int numAtoms, int paddedNumAtoms, float tau, float dt, float kT, float4 *posq, float4 *posqP, float4 *velm, long long *force, const float4 *__restrict__ random, unsigned int randomIndex ) {
/* Update the velocity.*/
const float vscale = exp( -dt / tau );
const float fscale = ( 1.0f - vscale ) * tau;
const float noisescale = sqrt( kT * ( 1 - vscale * vscale ) );
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float4 n = random[randomIndex + blockIdx.x * blockDim.x + threadIdx.x];
const float4 randomNoise = make_float4( n.x * noisescale, n.y * noisescale, n.z * noisescale, n.w * noisescale );
const float sqrtInvMass = sqrt( velm[atom].w );
float4 v = velm[atom];
float fx = ( float )force[atom] / ( float )0x100000000;
float fy = ( float )force[atom + 1 * paddedNumAtoms] / ( float )0x100000000;
float fz = ( float )force[atom + 2 * paddedNumAtoms] / ( float )0x100000000;
v.x = ( vscale * v.x ) + ( fscale * fx * v.w ) + ( randomNoise.x * sqrtInvMass );
v.y = ( vscale * v.y ) + ( fscale * fy * v.w ) + ( randomNoise.y * sqrtInvMass );
v.z = ( vscale * v.z ) + ( fscale * fz * v.w ) + ( randomNoise.z * sqrtInvMass );
velm[atom] = v;
}
}
extern "C" __global__ void kNMLUpdate2_kernel( int numAtoms, int numModes, float4 *velm, float4 *modes, float *modeWeights ) {
extern __shared__ float dotBuffer[];
for( int mode = blockIdx.x; mode < numModes; mode += gridDim.x ) {
/* Compute the projection of the mass weighted velocity onto one normal mode vector. */
float dot = 0.0f;
for( int atom = threadIdx.x; atom < numAtoms; atom += blockDim.x ) {
const int modePos = mode * numAtoms + atom;
const float scale = 1.0f / sqrt( velm[atom].w );
float4 v = velm[atom];
float4 m = modes[modePos];
dot += scale * ( v.x * m.x + v.y * m.y + v.z * m.z );
}
dotBuffer[threadIdx.x] = dot;
__syncthreads();
if( threadIdx.x == 0 ) {
float sum = 0;
for( int i = 0; i < blockDim.x; i++ ) {
sum += dotBuffer[i];
}
modeWeights[mode] = sum;
}
}
}
extern "C" __global__ void kNMLUpdate3_kernel( int numAtoms, int numModes, float dt, float4 *posq, float4 *velm, float4 *modes, float *modeWeights, float4 *noiseVal ) {
/* Load the weights into shared memory. */
extern __shared__ float weightBuffer[];
for( int mode = threadIdx.x; mode < numModes; mode += blockDim.x ) {
weightBuffer[mode] = modeWeights[mode];
}
__syncthreads();
/* Compute the projected velocities and update the atom positions. */
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float invMass = velm[atom].w, scale = sqrt( invMass );
float3 v = make_float3( 0.0f, 0.0f, 0.0f );
for( int mode = 0; mode < numModes; mode++ ) {
float4 m = modes[mode * numAtoms + atom];
float weight = weightBuffer[mode];
v.x += m.x * weight;
v.y += m.y * weight;
v.z += m.z * weight;
}
v.x *= scale;
v.y *= scale;
v.z *= scale;
velm[atom] = make_float4( v.x, v.y, v.z, invMass );
float4 pos = posq[atom];
/* Add Step */
pos.x += dt * v.x;
pos.y += dt * v.y;
pos.z += dt * v.z;
#ifdef FAST_NOISE
/* Remove Noise */
pos.x -= noiseVal[atom].x;
pos.y -= noiseVal[atom].y;
pos.z -= noiseVal[atom].z;
#endif
posq[atom] = pos;
}
} | #include <hip/hip_runtime.h>
extern "C" __global__ void kNMLUpdate1_kernel( int numAtoms, int paddedNumAtoms, float tau, float dt, float kT, float4 *posq, float4 *posqP, float4 *velm, long long *force, const float4 *__restrict__ random, unsigned int randomIndex ) {
/* Update the velocity.*/
const float vscale = exp( -dt / tau );
const float fscale = ( 1.0f - vscale ) * tau;
const float noisescale = sqrt( kT * ( 1 - vscale * vscale ) );
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float4 n = random[randomIndex + blockIdx.x * blockDim.x + threadIdx.x];
const float4 randomNoise = make_float4( n.x * noisescale, n.y * noisescale, n.z * noisescale, n.w * noisescale );
const float sqrtInvMass = sqrt( velm[atom].w );
float4 v = velm[atom];
float fx = ( float )force[atom] / ( float )0x100000000;
float fy = ( float )force[atom + 1 * paddedNumAtoms] / ( float )0x100000000;
float fz = ( float )force[atom + 2 * paddedNumAtoms] / ( float )0x100000000;
v.x = ( vscale * v.x ) + ( fscale * fx * v.w ) + ( randomNoise.x * sqrtInvMass );
v.y = ( vscale * v.y ) + ( fscale * fy * v.w ) + ( randomNoise.y * sqrtInvMass );
v.z = ( vscale * v.z ) + ( fscale * fz * v.w ) + ( randomNoise.z * sqrtInvMass );
velm[atom] = v;
}
}
extern "C" __global__ void kNMLUpdate2_kernel( int numAtoms, int numModes, float4 *velm, float4 *modes, float *modeWeights ) {
extern __shared__ float dotBuffer[];
for( int mode = blockIdx.x; mode < numModes; mode += gridDim.x ) {
/* Compute the projection of the mass weighted velocity onto one normal mode vector. */
float dot = 0.0f;
for( int atom = threadIdx.x; atom < numAtoms; atom += blockDim.x ) {
const int modePos = mode * numAtoms + atom;
const float scale = 1.0f / sqrt( velm[atom].w );
float4 v = velm[atom];
float4 m = modes[modePos];
dot += scale * ( v.x * m.x + v.y * m.y + v.z * m.z );
}
dotBuffer[threadIdx.x] = dot;
__syncthreads();
if( threadIdx.x == 0 ) {
float sum = 0;
for( int i = 0; i < blockDim.x; i++ ) {
sum += dotBuffer[i];
}
modeWeights[mode] = sum;
}
}
}
extern "C" __global__ void kNMLUpdate3_kernel( int numAtoms, int numModes, float dt, float4 *posq, float4 *velm, float4 *modes, float *modeWeights, float4 *noiseVal ) {
/* Load the weights into shared memory. */
extern __shared__ float weightBuffer[];
for( int mode = threadIdx.x; mode < numModes; mode += blockDim.x ) {
weightBuffer[mode] = modeWeights[mode];
}
__syncthreads();
/* Compute the projected velocities and update the atom positions. */
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float invMass = velm[atom].w, scale = sqrt( invMass );
float3 v = make_float3( 0.0f, 0.0f, 0.0f );
for( int mode = 0; mode < numModes; mode++ ) {
float4 m = modes[mode * numAtoms + atom];
float weight = weightBuffer[mode];
v.x += m.x * weight;
v.y += m.y * weight;
v.z += m.z * weight;
}
v.x *= scale;
v.y *= scale;
v.z *= scale;
velm[atom] = make_float4( v.x, v.y, v.z, invMass );
float4 pos = posq[atom];
/* Add Step */
pos.x += dt * v.x;
pos.y += dt * v.y;
pos.z += dt * v.z;
#ifdef FAST_NOISE
/* Remove Noise */
pos.x -= noiseVal[atom].x;
pos.y -= noiseVal[atom].y;
pos.z -= noiseVal[atom].z;
#endif
posq[atom] = pos;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void kNMLUpdate1_kernel( int numAtoms, int paddedNumAtoms, float tau, float dt, float kT, float4 *posq, float4 *posqP, float4 *velm, long long *force, const float4 *__restrict__ random, unsigned int randomIndex ) {
/* Update the velocity.*/
const float vscale = exp( -dt / tau );
const float fscale = ( 1.0f - vscale ) * tau;
const float noisescale = sqrt( kT * ( 1 - vscale * vscale ) );
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float4 n = random[randomIndex + blockIdx.x * blockDim.x + threadIdx.x];
const float4 randomNoise = make_float4( n.x * noisescale, n.y * noisescale, n.z * noisescale, n.w * noisescale );
const float sqrtInvMass = sqrt( velm[atom].w );
float4 v = velm[atom];
float fx = ( float )force[atom] / ( float )0x100000000;
float fy = ( float )force[atom + 1 * paddedNumAtoms] / ( float )0x100000000;
float fz = ( float )force[atom + 2 * paddedNumAtoms] / ( float )0x100000000;
v.x = ( vscale * v.x ) + ( fscale * fx * v.w ) + ( randomNoise.x * sqrtInvMass );
v.y = ( vscale * v.y ) + ( fscale * fy * v.w ) + ( randomNoise.y * sqrtInvMass );
v.z = ( vscale * v.z ) + ( fscale * fz * v.w ) + ( randomNoise.z * sqrtInvMass );
velm[atom] = v;
}
}
extern "C" __global__ void kNMLUpdate2_kernel( int numAtoms, int numModes, float4 *velm, float4 *modes, float *modeWeights ) {
extern __shared__ float dotBuffer[];
for( int mode = blockIdx.x; mode < numModes; mode += gridDim.x ) {
/* Compute the projection of the mass weighted velocity onto one normal mode vector. */
float dot = 0.0f;
for( int atom = threadIdx.x; atom < numAtoms; atom += blockDim.x ) {
const int modePos = mode * numAtoms + atom;
const float scale = 1.0f / sqrt( velm[atom].w );
float4 v = velm[atom];
float4 m = modes[modePos];
dot += scale * ( v.x * m.x + v.y * m.y + v.z * m.z );
}
dotBuffer[threadIdx.x] = dot;
__syncthreads();
if( threadIdx.x == 0 ) {
float sum = 0;
for( int i = 0; i < blockDim.x; i++ ) {
sum += dotBuffer[i];
}
modeWeights[mode] = sum;
}
}
}
extern "C" __global__ void kNMLUpdate3_kernel( int numAtoms, int numModes, float dt, float4 *posq, float4 *velm, float4 *modes, float *modeWeights, float4 *noiseVal ) {
/* Load the weights into shared memory. */
extern __shared__ float weightBuffer[];
for( int mode = threadIdx.x; mode < numModes; mode += blockDim.x ) {
weightBuffer[mode] = modeWeights[mode];
}
__syncthreads();
/* Compute the projected velocities and update the atom positions. */
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float invMass = velm[atom].w, scale = sqrt( invMass );
float3 v = make_float3( 0.0f, 0.0f, 0.0f );
for( int mode = 0; mode < numModes; mode++ ) {
float4 m = modes[mode * numAtoms + atom];
float weight = weightBuffer[mode];
v.x += m.x * weight;
v.y += m.y * weight;
v.z += m.z * weight;
}
v.x *= scale;
v.y *= scale;
v.z *= scale;
velm[atom] = make_float4( v.x, v.y, v.z, invMass );
float4 pos = posq[atom];
/* Add Step */
pos.x += dt * v.x;
pos.y += dt * v.y;
pos.z += dt * v.z;
#ifdef FAST_NOISE
/* Remove Noise */
pos.x -= noiseVal[atom].x;
pos.y -= noiseVal[atom].y;
pos.z -= noiseVal[atom].z;
#endif
posq[atom] = pos;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kNMLUpdate1_kernel
.globl kNMLUpdate1_kernel
.p2align 8
.type kNMLUpdate1_kernel,@function
kNMLUpdate1_kernel:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x54
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 0x48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
s_mul_i32 s15, s15, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v0
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s6, s[0:1], 0x40
s_load_b64 s[4:5], s[0:1], 0x38
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add3_u32 v2, s6, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 4, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b96 v[4:6], v[2:3], off
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x4
s_load_b128 s[8:11], s[0:1], 0x28
s_load_b32 s3, s[2:3], 0x0
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v0, null, s5, s5, -s6
v_div_scale_f32 v7, vcc_lo, -s6, s5, -s6
s_lshl_b32 s2, s4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v0
s_mul_i32 s3, s3, s13
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v0, v2, 1.0
v_fmac_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v7, v2
v_fma_f32 v8, -v0, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v8, v2
v_fma_f32 v0, -v0, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v0, v0, v2, v3
v_div_fixup_f32 v0, v0, s5, -s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x3fb8aa3b, v0
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
v_fma_f32 v3, v0, 0x3fb8aa3b, -v2
v_rndne_f32_e32 v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v3, v0, 0x32a5705f, v3 :: v_dual_sub_f32 v2, v2, v7
v_add_f32_e32 v2, v2, v3
v_cvt_i32_f32_e32 v3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_ldexp_f32 v2, v2, v3
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, 0x7f800000, v2, vcc_lo
v_fma_f32 v2, -v0, v0, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, s7, v2
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v3
v_add_nc_u32_e32 v8, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v3, v2
v_fma_f32 v10, -v8, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v3, v3, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v10
v_cndmask_b32_e64 v3, v3, v8, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, v2, v5
v_sub_f32_e32 v7, 1.0, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v3, s5, v7 :: v_dual_mul_f32 v4, v2, v4
v_mul_f32_e32 v6, v2, v6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v7, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 4, v[1:2]
v_lshlrev_b64 v[12:13], 3, v[1:2]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v16, vcc_lo, s10, v12
v_add_co_ci_u32_e32 v17, vcc_lo, s11, v13, vcc_lo
v_lshlrev_b64 v[18:19], 3, v[7:8]
global_load_b128 v[7:10], v[14:15], off
global_load_b64 v[16:17], v[16:17], off
v_add_co_u32 v18, vcc_lo, s10, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo
s_waitcnt vmcnt(1)
v_dual_mul_f32 v2, 0x4f800000, v10 :: v_dual_add_nc_u32 v11, s2, v1
s_waitcnt vmcnt(0)
v_xor_b32_e32 v13, v16, v17
v_cls_i32_e32 v20, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v12, 31, v11
v_ashrrev_i32_e32 v13, 31, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v20, -1, v20
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, 32, v13
v_add_co_u32 v11, vcc_lo, s10, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
s_clause 0x1
global_load_b64 v[18:19], v[18:19], off
global_load_b64 v[11:12], v[11:12], off
v_min_u32_e32 v13, v20, v13
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[16:17], v13, v[16:17]
v_cndmask_b32_e32 v2, v10, v2, vcc_lo
v_sub_nc_u32_e32 v13, 32, v13
v_min_u32_e32 v16, 1, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sqrt_f32_e32 v25, v2
v_or_b32_e32 v16, v17, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v16, v16
v_ldexp_f32 v13, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, 0x2f800000, v13
v_mul_f32_e32 v13, v3, v13
s_waitcnt vmcnt(1)
v_xor_b32_e32 v21, v18, v19
s_waitcnt vmcnt(0)
v_xor_b32_e32 v22, v11, v12
v_cls_i32_e32 v23, v19
v_cls_i32_e32 v24, v12
v_ashrrev_i32_e32 v21, 31, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v22, 31, v22
v_add_nc_u32_e32 v23, -1, v23
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v24, -1, v24
v_add_nc_u32_e32 v21, 32, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v22, 32, v22
v_min_u32_e32 v20, v23, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v21, v24, v22
v_lshlrev_b64 v[18:19], v20, v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], v21, v[11:12]
v_min_u32_e32 v18, 1, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v11, 1, v11
v_or_b32_e32 v17, v19, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_or_b32_e32 v11, v12, v11
v_sub_nc_u32_e32 v12, 32, v20
v_sub_nc_u32_e32 v18, 32, v21
v_cvt_f32_i32_e32 v17, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v11, v11
v_ldexp_f32 v12, v17, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v11, v11, v18
v_dual_mul_f32 v12, 0x2f800000, v12 :: v_dual_mul_f32 v11, 0x2f800000, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v12, v3, v12 :: v_dual_add_nc_u32 v23, 1, v25
v_mul_f32_e32 v18, v3, v11
v_add_nc_u32_e32 v22, -1, v25
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_mul_f32 v12, v10, v12 :: v_dual_add_nc_u32 v1, s3, v1
v_fma_f32 v26, -v23, v25, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v12, v0, v8 :: v_dual_mul_f32 v11, v10, v13
v_mul_f32_e32 v13, v10, v18
v_fma_f32 v24, -v22, v25, v2
v_fmac_f32_e32 v13, v0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v24
v_cndmask_b32_e64 v19, v25, v22, s0
v_cmp_lt_f32_e64 s0, 0, v26
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v16, v19, v23, s0
v_mul_f32_e32 v17, 0x37800000, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v16, v17, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v16, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v6, v2
v_dual_fmac_f32 v12, v5, v2 :: v_dual_fmac_f32 v11, v0, v7
s_or_b32 s1, vcc_lo, s1
v_fmac_f32_e32 v11, v4, v2
global_store_b96 v[14:15], v[11:13], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kNMLUpdate1_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kNMLUpdate1_kernel, .Lfunc_end0-kNMLUpdate1_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.protected kNMLUpdate2_kernel
.globl kNMLUpdate2_kernel
.p2align 8
.type kNMLUpdate2_kernel,@function
kNMLUpdate2_kernel:
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_12
s_mov_b32 s8, s15
s_clause 0x3
s_load_b32 s14, s[0:1], 0x0
s_load_b32 s15, s[0:1], 0x20
s_load_b64 s[10:11], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x8
s_add_u32 s12, s0, 32
v_lshl_add_u32 v3, v0, 2, 0
v_cmp_eq_u32_e64 s0, 0, v0
v_mov_b32_e32 v4, 0
s_addc_u32 s13, s1, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s14, v0
s_mul_i32 s16, s8, s14
s_mul_i32 s17, s15, s14
s_branch .LBB1_4
.LBB1_2:
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[18:19], s[8:9], 2
s_add_u32 s18, s10, s18
s_addc_u32 s19, s11, s19
global_store_b32 v4, v1, s[18:19]
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s8, s15, s8
s_add_i32 s16, s16, s17
s_cmp_ge_i32 s8, s3
s_cbranch_scc1 .LBB1_12
.LBB1_4:
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB1_8
s_load_b32 s1, s[12:13], 0xc
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s1, 0xffff
.LBB1_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[6:7], 4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b128 v[6:9], v[6:7], off
v_add_nc_u32_e32 v10, s16, v1
v_add_nc_u32_e32 v1, s19, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 4, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b96 v[10:12], v[10:11], off
s_waitcnt vmcnt(1)
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
s_waitcnt vmcnt(0)
v_dual_mul_f32 v7, v7, v11 :: v_dual_mul_f32 v2, 0x4f800000, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v6, v10
v_dual_cndmask_b32 v2, v9, v2 :: v_dual_fmac_f32 v7, v8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v9, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v13, -1, v9
v_add_nc_u32_e32 v14, 1, v9
v_fma_f32 v15, -v13, v9, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v14, v9, v2
v_cmp_ge_f32_e64 s1, 0, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v13, s1
v_cmp_lt_f32_e64 s1, 0, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v9, v9, v14, s1
v_mul_f32_e32 v13, 0x37800000, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v9, v9, v13, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v9, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v9, null, v2, v2, 1.0
v_div_scale_f32 v15, vcc_lo, 1.0, v2, 1.0
v_rcp_f32_e32 v13, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v9, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v9, v14, v15
v_fmac_f32_e32 v14, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v9, v14, v15
v_div_fmas_f32 v6, v9, v13, v14
v_cmp_le_i32_e32 vcc_lo, s14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v6, v2, 1.0
s_or_b32 s18, vcc_lo, s18
v_fmac_f32_e32 v5, v2, v7
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execnz .LBB1_6
s_or_b32 exec_lo, exec_lo, s18
.LBB1_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_3
s_load_b32 s9, s[12:13], 0xc
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s18, s9, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s18
s_cbranch_vccnz .LBB1_2
s_and_b32 s9, 0xffff, s9
s_mov_b32 s18, 0
.LBB1_11:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s18
s_add_i32 s9, s9, -1
s_add_i32 s18, s18, 4
s_cmp_eq_u32 s9, 0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
s_cbranch_scc0 .LBB1_11
s_branch .LBB1_2
.LBB1_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kNMLUpdate2_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size kNMLUpdate2_kernel, .Lfunc_end1-kNMLUpdate2_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.protected kNMLUpdate3_kernel
.globl kNMLUpdate3_kernel
.p2align 8
.type kNMLUpdate3_kernel,@function
kNMLUpdate3_kernel:
s_load_b32 s10, s[0:1], 0x4
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB2_3
s_clause 0x1
s_load_b32 s5, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x28
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s7, s5, 2
.LBB2_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v1
global_load_b32 v2, v[4:5], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
v_add_nc_u32_e32 v3, s7, v3
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s3, s[0:1], 0x44
s_load_b32 s2, s[0:1], 0x0
s_add_u32 s4, s0, 56
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s3, 0xffff
s_mov_b32 s3, exec_lo
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v4
s_cbranch_execz .LBB2_9
s_load_b64 s[14:15], s[0:1], 0x20
s_load_b32 s9, s[4:5], 0x0
s_clause 0x1
s_load_b32 s11, s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x10
s_cmp_gt_i32 s10, 0
s_mov_b32 s1, 0
s_cselect_b32 s12, -1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s13, s14, 4
s_addc_u32 s14, s15, 0
s_ashr_i32 s3, s2, 31
s_mul_i32 s15, s9, s8
s_lshl_b64 s[8:9], s[2:3], 4
s_branch .LBB2_6
.LBB2_5:
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
v_add_nc_u32_e32 v4, s15, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v3, v0, vcc_lo
v_sqrt_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v11, -1, v1
v_add_nc_u32_e32 v12, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v11, v1, v0
v_fma_f32 v14, -v12, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v13
v_cndmask_b32_e64 v1, v1, v11, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v14
v_cndmask_b32_e64 v1, v1, v12, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, 0x37800000, v1
v_cndmask_b32_e32 v1, v1, v11, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v11, v1, v0, vcc_lo
v_mul_f32_e32 v1, v11, v9
v_add_co_u32 v9, vcc_lo, s4, v7
v_mul_f32_e32 v0, v11, v10
v_mul_f32_e32 v2, v11, v2
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s2, v4
global_store_b128 v[5:6], v[0:3], off
global_load_b96 v[5:7], v[9:10], off
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_fma_f32 v5, s11, v0, v5
v_fma_f32 v6, s11, v1, v6
v_fmac_f32_e32 v7, s11, v2
global_store_b96 v[9:10], v[5:7], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB2_9
.LBB2_6:
v_ashrrev_i32_e32 v5, 31, v4
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 4, v[4:5]
v_add_co_u32 v5, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v8, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s12
global_load_b32 v3, v[5:6], off offset:12
s_cbranch_vccnz .LBB2_5
v_add_co_u32 v0, vcc_lo, s13, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s14, v8, vcc_lo
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v10, 0
s_mov_b32 s0, 0
s_mov_b32 s3, s10
.p2align 6
.LBB2_8:
s_clause 0x1
global_load_b32 v13, v[0:1], off offset:-4
global_load_b64 v[11:12], v[0:1], off
v_mov_b32_e32 v14, s0
v_add_co_u32 v0, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
ds_load_b32 v14, v14
s_add_i32 s3, s3, -1
s_add_i32 s0, s0, 4
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(1) lgkmcnt(0)
v_fmac_f32_e32 v10, v13, v14
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v9, v11, v14
v_fmac_f32_e32 v2, v12, v14
s_cbranch_scc0 .LBB2_8
s_branch .LBB2_5
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kNMLUpdate3_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size kNMLUpdate3_kernel, .Lfunc_end2-kNMLUpdate3_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kNMLUpdate1_kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kNMLUpdate1_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kNMLUpdate2_kernel
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: kNMLUpdate2_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
- .offset: 176
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kNMLUpdate3_kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kNMLUpdate3_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void kNMLUpdate1_kernel( int numAtoms, int paddedNumAtoms, float tau, float dt, float kT, float4 *posq, float4 *posqP, float4 *velm, long long *force, const float4 *__restrict__ random, unsigned int randomIndex ) {
/* Update the velocity.*/
const float vscale = exp( -dt / tau );
const float fscale = ( 1.0f - vscale ) * tau;
const float noisescale = sqrt( kT * ( 1 - vscale * vscale ) );
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float4 n = random[randomIndex + blockIdx.x * blockDim.x + threadIdx.x];
const float4 randomNoise = make_float4( n.x * noisescale, n.y * noisescale, n.z * noisescale, n.w * noisescale );
const float sqrtInvMass = sqrt( velm[atom].w );
float4 v = velm[atom];
float fx = ( float )force[atom] / ( float )0x100000000;
float fy = ( float )force[atom + 1 * paddedNumAtoms] / ( float )0x100000000;
float fz = ( float )force[atom + 2 * paddedNumAtoms] / ( float )0x100000000;
v.x = ( vscale * v.x ) + ( fscale * fx * v.w ) + ( randomNoise.x * sqrtInvMass );
v.y = ( vscale * v.y ) + ( fscale * fy * v.w ) + ( randomNoise.y * sqrtInvMass );
v.z = ( vscale * v.z ) + ( fscale * fz * v.w ) + ( randomNoise.z * sqrtInvMass );
velm[atom] = v;
}
}
extern "C" __global__ void kNMLUpdate2_kernel( int numAtoms, int numModes, float4 *velm, float4 *modes, float *modeWeights ) {
extern __shared__ float dotBuffer[];
for( int mode = blockIdx.x; mode < numModes; mode += gridDim.x ) {
/* Compute the projection of the mass weighted velocity onto one normal mode vector. */
float dot = 0.0f;
for( int atom = threadIdx.x; atom < numAtoms; atom += blockDim.x ) {
const int modePos = mode * numAtoms + atom;
const float scale = 1.0f / sqrt( velm[atom].w );
float4 v = velm[atom];
float4 m = modes[modePos];
dot += scale * ( v.x * m.x + v.y * m.y + v.z * m.z );
}
dotBuffer[threadIdx.x] = dot;
__syncthreads();
if( threadIdx.x == 0 ) {
float sum = 0;
for( int i = 0; i < blockDim.x; i++ ) {
sum += dotBuffer[i];
}
modeWeights[mode] = sum;
}
}
}
extern "C" __global__ void kNMLUpdate3_kernel( int numAtoms, int numModes, float dt, float4 *posq, float4 *velm, float4 *modes, float *modeWeights, float4 *noiseVal ) {
/* Load the weights into shared memory. */
extern __shared__ float weightBuffer[];
for( int mode = threadIdx.x; mode < numModes; mode += blockDim.x ) {
weightBuffer[mode] = modeWeights[mode];
}
__syncthreads();
/* Compute the projected velocities and update the atom positions. */
for( int atom = threadIdx.x + blockIdx.x * blockDim.x; atom < numAtoms; atom += blockDim.x * gridDim.x ) {
const float invMass = velm[atom].w, scale = sqrt( invMass );
float3 v = make_float3( 0.0f, 0.0f, 0.0f );
for( int mode = 0; mode < numModes; mode++ ) {
float4 m = modes[mode * numAtoms + atom];
float weight = weightBuffer[mode];
v.x += m.x * weight;
v.y += m.y * weight;
v.z += m.z * weight;
}
v.x *= scale;
v.y *= scale;
v.z *= scale;
velm[atom] = make_float4( v.x, v.y, v.z, invMass );
float4 pos = posq[atom];
/* Add Step */
pos.x += dt * v.x;
pos.y += dt * v.y;
pos.z += dt * v.z;
#ifdef FAST_NOISE
/* Remove Noise */
pos.x -= noiseVal[atom].x;
pos.y -= noiseVal[atom].y;
pos.z -= noiseVal[atom].z;
#endif
posq[atom] = pos;
}
} | .text
.file "NMLupdates_kernel.hip"
.globl __device_stub__kNMLUpdate1_kernel # -- Begin function __device_stub__kNMLUpdate1_kernel
.p2align 4, 0x90
.type __device_stub__kNMLUpdate1_kernel,@function
__device_stub__kNMLUpdate1_kernel: # @__device_stub__kNMLUpdate1_kernel
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 208(%rsp), %rax
movq %rax, 184(%rsp)
leaq 216(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $kNMLUpdate1_kernel, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size __device_stub__kNMLUpdate1_kernel, .Lfunc_end0-__device_stub__kNMLUpdate1_kernel
.cfi_endproc
# -- End function
.globl __device_stub__kNMLUpdate2_kernel # -- Begin function __device_stub__kNMLUpdate2_kernel
.p2align 4, 0x90
.type __device_stub__kNMLUpdate2_kernel,@function
__device_stub__kNMLUpdate2_kernel: # @__device_stub__kNMLUpdate2_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $kNMLUpdate2_kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__kNMLUpdate2_kernel, .Lfunc_end1-__device_stub__kNMLUpdate2_kernel
.cfi_endproc
# -- End function
.globl __device_stub__kNMLUpdate3_kernel # -- Begin function __device_stub__kNMLUpdate3_kernel
.p2align 4, 0x90
.type __device_stub__kNMLUpdate3_kernel,@function
__device_stub__kNMLUpdate3_kernel: # @__device_stub__kNMLUpdate3_kernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $kNMLUpdate3_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size __device_stub__kNMLUpdate3_kernel, .Lfunc_end2-__device_stub__kNMLUpdate3_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kNMLUpdate1_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kNMLUpdate2_kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kNMLUpdate3_kernel, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type kNMLUpdate1_kernel,@object # @kNMLUpdate1_kernel
.section .rodata,"a",@progbits
.globl kNMLUpdate1_kernel
.p2align 3, 0x0
kNMLUpdate1_kernel:
.quad __device_stub__kNMLUpdate1_kernel
.size kNMLUpdate1_kernel, 8
.type kNMLUpdate2_kernel,@object # @kNMLUpdate2_kernel
.globl kNMLUpdate2_kernel
.p2align 3, 0x0
kNMLUpdate2_kernel:
.quad __device_stub__kNMLUpdate2_kernel
.size kNMLUpdate2_kernel, 8
.type kNMLUpdate3_kernel,@object # @kNMLUpdate3_kernel
.globl kNMLUpdate3_kernel
.p2align 3, 0x0
kNMLUpdate3_kernel:
.quad __device_stub__kNMLUpdate3_kernel
.size kNMLUpdate3_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kNMLUpdate1_kernel"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kNMLUpdate2_kernel"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "kNMLUpdate3_kernel"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kNMLUpdate1_kernel
.addrsig_sym __device_stub__kNMLUpdate2_kernel
.addrsig_sym __device_stub__kNMLUpdate3_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kNMLUpdate1_kernel
.addrsig_sym kNMLUpdate2_kernel
.addrsig_sym kNMLUpdate3_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015eaea_00000000-6_NMLupdates_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j
.type _Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j, @function
_Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movss %xmm0, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 52(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 44(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movq 256(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 216(%rsp)
leaq 264(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq kNMLUpdate1_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j, .-_Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j
.globl kNMLUpdate1_kernel
.type kNMLUpdate1_kernel, @function
kNMLUpdate1_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z62__device_stub__Z18kNMLUpdate1_kerneliifffP6float4S0_S0_PxPKS_jiifffP6float4S0_S0_PxPKS_j
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kNMLUpdate1_kernel, .-kNMLUpdate1_kernel
.globl _Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf
.type _Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf, @function
_Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq kNMLUpdate2_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf, .-_Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf
.globl kNMLUpdate2_kernel
.type kNMLUpdate2_kernel, @function
kNMLUpdate2_kernel:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z18kNMLUpdate2_kerneliiP6float4S0_PfiiP6float4S0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size kNMLUpdate2_kernel, .-kNMLUpdate2_kernel
.globl _Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_
.type _Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_, @function
_Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_:
.LFB2055:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movss %xmm0, 52(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq kNMLUpdate3_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_, .-_Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_
.globl kNMLUpdate3_kernel
.type kNMLUpdate3_kernel, @function
kNMLUpdate3_kernel:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z58__device_stub__Z18kNMLUpdate3_kerneliifP6float4S0_S0_PfS0_iifP6float4S0_S0_PfS0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size kNMLUpdate3_kernel, .-kNMLUpdate3_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kNMLUpdate3_kernel"
.LC1:
.string "kNMLUpdate2_kernel"
.LC2:
.string "kNMLUpdate1_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kNMLUpdate3_kernel(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq kNMLUpdate2_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq kNMLUpdate1_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NMLupdates_kernel.hip"
.globl __device_stub__kNMLUpdate1_kernel # -- Begin function __device_stub__kNMLUpdate1_kernel
.p2align 4, 0x90
.type __device_stub__kNMLUpdate1_kernel,@function
__device_stub__kNMLUpdate1_kernel: # @__device_stub__kNMLUpdate1_kernel
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 208(%rsp), %rax
movq %rax, 184(%rsp)
leaq 216(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $kNMLUpdate1_kernel, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size __device_stub__kNMLUpdate1_kernel, .Lfunc_end0-__device_stub__kNMLUpdate1_kernel
.cfi_endproc
# -- End function
.globl __device_stub__kNMLUpdate2_kernel # -- Begin function __device_stub__kNMLUpdate2_kernel
.p2align 4, 0x90
.type __device_stub__kNMLUpdate2_kernel,@function
__device_stub__kNMLUpdate2_kernel: # @__device_stub__kNMLUpdate2_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $kNMLUpdate2_kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__kNMLUpdate2_kernel, .Lfunc_end1-__device_stub__kNMLUpdate2_kernel
.cfi_endproc
# -- End function
.globl __device_stub__kNMLUpdate3_kernel # -- Begin function __device_stub__kNMLUpdate3_kernel
.p2align 4, 0x90
.type __device_stub__kNMLUpdate3_kernel,@function
__device_stub__kNMLUpdate3_kernel: # @__device_stub__kNMLUpdate3_kernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $kNMLUpdate3_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size __device_stub__kNMLUpdate3_kernel, .Lfunc_end2-__device_stub__kNMLUpdate3_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kNMLUpdate1_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kNMLUpdate2_kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kNMLUpdate3_kernel, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type kNMLUpdate1_kernel,@object # @kNMLUpdate1_kernel
.section .rodata,"a",@progbits
.globl kNMLUpdate1_kernel
.p2align 3, 0x0
kNMLUpdate1_kernel:
.quad __device_stub__kNMLUpdate1_kernel
.size kNMLUpdate1_kernel, 8
.type kNMLUpdate2_kernel,@object # @kNMLUpdate2_kernel
.globl kNMLUpdate2_kernel
.p2align 3, 0x0
kNMLUpdate2_kernel:
.quad __device_stub__kNMLUpdate2_kernel
.size kNMLUpdate2_kernel, 8
.type kNMLUpdate3_kernel,@object # @kNMLUpdate3_kernel
.globl kNMLUpdate3_kernel
.p2align 3, 0x0
kNMLUpdate3_kernel:
.quad __device_stub__kNMLUpdate3_kernel
.size kNMLUpdate3_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kNMLUpdate1_kernel"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kNMLUpdate2_kernel"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "kNMLUpdate3_kernel"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kNMLUpdate1_kernel
.addrsig_sym __device_stub__kNMLUpdate2_kernel
.addrsig_sym __device_stub__kNMLUpdate3_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kNMLUpdate1_kernel
.addrsig_sym kNMLUpdate2_kernel
.addrsig_sym kNMLUpdate3_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void glcm_calculation_135(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=0;i<nx-1;i++){
if(blockIdx.x==i && idx >i*nx){
k=max*A[idx]+A[idx+(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | code for sm_80
Function : _Z20glcm_calculation_135PiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0b7624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e240000002200 */
/*0040*/ ISETP.GE.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe40003f06270 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe400078e0202 */
/*0080*/ IMAD R6, R0, c[0x0][0x0], R5 ; /* 0x0000000000067a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R6, R3, c[0x0][0x170], R6 ; /* 0x00005c0003067a24 */
/* 0x000fe200078e0206 */
/*00a0*/ @!P0 BRA 0x720 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R11.reuse, -0x2, RZ ; /* 0xfffffffe0b027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ IADD3 R7, R11, -0x1, RZ ; /* 0xffffffff0b077810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0100*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0110*/ IMAD.IADD R4, R6, 0x1, R7 ; /* 0x0000000106047824 */
/* 0x000fe200078e0207 */
/*0120*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fc600078ec0ff */
/*0130*/ IMAD.WIDE.U32 R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0005 */
/*0140*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0005 */
/*0150*/ @!P0 BRA 0x5b0 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R8, 0x1 ; /* 0x0000000100087802 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.SHL.U32 R9, R11.reuse, 0x2, RZ ; /* 0x000000020b097824 */
/* 0x040fe200078e00ff */
/*0180*/ MOV R15, c[0x0][0x170] ; /* 0x00005c00000f7a02 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD R11, R11, 0x3, RZ ; /* 0x000000030b0b7824 */
/* 0x000fe200078e02ff */
/*01a0*/ IADD3 R8, R7, -c[0x0][0x170], R8 ; /* 0x80005c0007087a10 */
/* 0x000fe20007ffe008 */
/*01b0*/ IMAD.MOV R12, RZ, RZ, -R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a00 */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01d0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e00ff */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe20003f04070 */
/*01f0*/ BSSY B0, 0x2a0 ; /* 0x000000a000007945 */
/* 0x000fe60003800000 */
/*0200*/ ISETP.NE.OR P0, PT, R12, RZ, !P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0004705670 */
/*0210*/ @P0 BRA 0x290 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0220*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R17, [R4.64] ; /* 0x0000000604117981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R19, RZ, RZ, 0x1 ; /* 0x00000001ff137424 */
/* 0x000fe400078e00ff */
/*0260*/ IMAD R17, R10, c[0x0][0x178], R17 ; /* 0x00005e000a117a24 */
/* 0x004fc800078e0211 */
/*0270*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fca00078e0210 */
/*0280*/ RED.E.ADD.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0001e4000c10e186 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R6, R15, PT ; /* 0x0000000f0600720c */
/* 0x000fe20003f04070 */
/*02c0*/ BSSY B0, 0x370 ; /* 0x000000a000007945 */
/* 0x000fe80003800000 */
/*02d0*/ ISETP.NE.OR P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x000fda000c705670 */
/*02e0*/ @P0 BRA 0x360 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R17, [R4.64] ; /* 0x0000000604117981 */
/* 0x001ea2000c1e1900 */
/*0310*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*0320*/ IMAD.MOV.U32 R19, RZ, RZ, 0x1 ; /* 0x00000001ff137424 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD R17, R10, c[0x0][0x178], R17 ; /* 0x00005e000a117a24 */
/* 0x004fce00078e0211 */
/*0340*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fca00078e0210 */
/*0350*/ RED.E.ADD.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0001e4000c10e186 */
/*0360*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0370*/ UIADD3 UR5, UR4, 0x2, URZ ; /* 0x0000000204057890 */
/* 0x000fe2000fffe03f */
/*0380*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fe20003f04070 */
/*0390*/ BSSY B0, 0x440 ; /* 0x000000a000007945 */
/* 0x000fe80003800000 */
/*03a0*/ ISETP.NE.OR P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x000fda000c705670 */
/*03b0*/ @P0 BRA 0x430 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R17, [R4.64] ; /* 0x0000000604117981 */
/* 0x001ea2000c1e1900 */
/*03e0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe200078e00ff */
/*03f0*/ MOV R19, 0x1 ; /* 0x0000000100137802 */
/* 0x000fe20000000f00 */
/*0400*/ IMAD R17, R10, c[0x0][0x178], R17 ; /* 0x00005e000a117a24 */
/* 0x004fc800078e0211 */
/*0410*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fca00078e0210 */
/*0420*/ RED.E.ADD.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0001e4000c10e186 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fe2000fffe03f */
/*0450*/ ISETP.GT.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fe20003f04070 */
/*0460*/ BSSY B0, 0x510 ; /* 0x000000a000007945 */
/* 0x000fe80003800000 */
/*0470*/ ISETP.NE.OR P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x000fda000c705670 */
/*0480*/ @P0 BRA 0x500 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0490*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R17, [R4.64] ; /* 0x0000000604117981 */
/* 0x001ea2000c1e1900 */
/*04b0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe400078e00ff */
/*04c0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x1 ; /* 0x00000001ff137424 */
/* 0x000fe400078e00ff */
/*04d0*/ IMAD R17, R10, c[0x0][0x178], R17 ; /* 0x00005e000a117a24 */
/* 0x004fc800078e0211 */
/*04e0*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fca00078e0210 */
/*04f0*/ RED.E.ADD.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0001e4000c10e186 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0520*/ MOV R10, c[0x0][0x170] ; /* 0x00005c00000a7a02 */
/* 0x000fe40000000f00 */
/*0530*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe0ff */
/*0540*/ LEA R9, R10.reuse, R9, 0x2 ; /* 0x000000090a097211 */
/* 0x040fe200078e10ff */
/*0550*/ IMAD R15, R10, 0x4, R15 ; /* 0x000000040a0f7824 */
/* 0x000fe200078e020f */
/*0560*/ IADD3 R14, R8, UR4, RZ ; /* 0x00000004080e7c10 */
/* 0x000fe2000fffe0ff */
/*0570*/ IMAD R11, R10.reuse, 0x4, R11 ; /* 0x000000040a0b7824 */
/* 0x040fe200078e020b */
/*0580*/ LEA R13, R10, R13, 0x2 ; /* 0x0000000d0a0d7211 */
/* 0x000fe400078e10ff */
/*0590*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fda0003f05270 */
/*05a0*/ @P0 BRA 0x1e0 ; /* 0xfffffc3000000947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 BRA 0x720 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R0, -R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fe2000fffe1ff */
/*05e0*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*05f0*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fcc000f8e023f */
/*0600*/ ISETP.GT.U32.AND P0, PT, R6, UR5, PT ; /* 0x0000000506007c0c */
/* 0x000fe2000bf04070 */
/*0610*/ BSSY B0, 0x6d0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0620*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0630*/ ISETP.NE.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fda0004705670 */
/*0640*/ @P0 BRA 0x6c0 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*0650*/ LDG.E R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0680*/ HFMA2.MMA R13, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0d7435 */
/* 0x000fe200000001ff */
/*0690*/ IMAD R8, R8, c[0x0][0x178], R9 ; /* 0x00005e0008087a24 */
/* 0x004fc800078e0209 */
/*06a0*/ IMAD.WIDE R8, R8, R11, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020b */
/*06b0*/ RED.E.ADD.STRONG.GPU [R8.64], R13 ; /* 0x0000000d0800798e */
/* 0x0003e4000c10e186 */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*06e0*/ ULDC UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000800 */
/*06f0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0700*/ UIADD3 UR5, UR5, UR8, URZ ; /* 0x0000000805057290 */
/* 0x000fd4000fffe03f */
/*0710*/ @P0 BRA 0x600 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void glcm_calculation_135(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=0;i<nx-1;i++){
if(blockIdx.x==i && idx >i*nx){
k=max*A[idx]+A[idx+(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | .file "tmpxft_000847a3_00000000-6_glcm_calculation_135.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii
.type _Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii, @function
_Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20glcm_calculation_135PiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii, .-_Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii
.globl _Z20glcm_calculation_135PiS_iii
.type _Z20glcm_calculation_135PiS_iii, @function
_Z20glcm_calculation_135PiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20glcm_calculation_135PiS_iii, .-_Z20glcm_calculation_135PiS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20glcm_calculation_135PiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20glcm_calculation_135PiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void glcm_calculation_135(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=0;i<nx-1;i++){
if(blockIdx.x==i && idx >i*nx){
k=max*A[idx]+A[idx+(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void glcm_calculation_135(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=0;i<nx-1;i++){
if(blockIdx.x==i && idx >i*nx){
k=max*A[idx]+A[idx+(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void glcm_calculation_135(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=0;i<nx-1;i++){
if(blockIdx.x==i && idx >i*nx){
k=max*A[idx]+A[idx+(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20glcm_calculation_135PiS_iii
.globl _Z20glcm_calculation_135PiS_iii
.p2align 8
.type _Z20glcm_calculation_135PiS_iii,@function
_Z20glcm_calculation_135PiS_iii:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b32 s3, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mov_b32_e32 v1, 0
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s3, s14, s3
s_load_b32 s0, s[0:1], 0x18
s_mov_b32 s1, 0
v_mov_b32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s2
v_add3_u32 v0, s3, v0, v2
s_sub_i32 s3, 0, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v2, s2, -1, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v7, vcc_lo
v_mov_b32_e32 v5, 1
s_mov_b32 s4, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s4, s4, 1
s_add_i32 s1, s1, s2
s_cmp_lg_u32 s2, s4
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_add_i32 s5, s3, s4
v_cmp_lt_u32_e32 vcc_lo, s1, v0
s_cmp_eq_u32 s5, 1
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, s5, vcc_lo
s_and_saveexec_b32 s5, s8
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v9, v[1:2], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, s0, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[6:7], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_atomic_add_u32 v[6:7], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20glcm_calculation_135PiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20glcm_calculation_135PiS_iii, .Lfunc_end0-_Z20glcm_calculation_135PiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20glcm_calculation_135PiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20glcm_calculation_135PiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void glcm_calculation_135(int *A,int *glcm, const int nx, const int ny,int max){
int ix = threadIdx.x + blockIdx.x* blockDim.x;
int iy = threadIdx.y + blockIdx.y* blockDim.y;
unsigned int idx =iy*nx+ix;
int i;
int k=0;
for(i=0;i<nx-1;i++){
if(blockIdx.x==i && idx >i*nx){
k=max*A[idx]+A[idx+(nx-1)];
atomicAdd(&glcm[k],1);
}
}
__syncthreads();
} | .text
.file "glcm_calculation_135.hip"
.globl _Z35__device_stub__glcm_calculation_135PiS_iii # -- Begin function _Z35__device_stub__glcm_calculation_135PiS_iii
.p2align 4, 0x90
.type _Z35__device_stub__glcm_calculation_135PiS_iii,@function
_Z35__device_stub__glcm_calculation_135PiS_iii: # @_Z35__device_stub__glcm_calculation_135PiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20glcm_calculation_135PiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__glcm_calculation_135PiS_iii, .Lfunc_end0-_Z35__device_stub__glcm_calculation_135PiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20glcm_calculation_135PiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20glcm_calculation_135PiS_iii,@object # @_Z20glcm_calculation_135PiS_iii
.section .rodata,"a",@progbits
.globl _Z20glcm_calculation_135PiS_iii
.p2align 3, 0x0
_Z20glcm_calculation_135PiS_iii:
.quad _Z35__device_stub__glcm_calculation_135PiS_iii
.size _Z20glcm_calculation_135PiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20glcm_calculation_135PiS_iii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__glcm_calculation_135PiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20glcm_calculation_135PiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20glcm_calculation_135PiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0b7624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e240000002200 */
/*0040*/ ISETP.GE.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe40003f06270 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fe400078e0202 */
/*0080*/ IMAD R6, R0, c[0x0][0x0], R5 ; /* 0x0000000000067a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R6, R3, c[0x0][0x170], R6 ; /* 0x00005c0003067a24 */
/* 0x000fe200078e0206 */
/*00a0*/ @!P0 BRA 0x720 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R11.reuse, -0x2, RZ ; /* 0xfffffffe0b027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ IADD3 R7, R11, -0x1, RZ ; /* 0xffffffff0b077810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0100*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0110*/ IMAD.IADD R4, R6, 0x1, R7 ; /* 0x0000000106047824 */
/* 0x000fe200078e0207 */
/*0120*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fc600078ec0ff */
/*0130*/ IMAD.WIDE.U32 R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0005 */
/*0140*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0005 */
/*0150*/ @!P0 BRA 0x5b0 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R8, 0x1 ; /* 0x0000000100087802 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.SHL.U32 R9, R11.reuse, 0x2, RZ ; /* 0x000000020b097824 */
/* 0x040fe200078e00ff */
/*0180*/ MOV R15, c[0x0][0x170] ; /* 0x00005c00000f7a02 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD R11, R11, 0x3, RZ ; /* 0x000000030b0b7824 */
/* 0x000fe200078e02ff */
/*01a0*/ IADD3 R8, R7, -c[0x0][0x170], R8 ; /* 0x80005c0007087a10 */
/* 0x000fe20007ffe008 */
/*01b0*/ IMAD.MOV R12, RZ, RZ, -R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a00 */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01d0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e00ff */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fe20003f04070 */
/*01f0*/ BSSY B0, 0x2a0 ; /* 0x000000a000007945 */
/* 0x000fe60003800000 */
/*0200*/ ISETP.NE.OR P0, PT, R12, RZ, !P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0004705670 */
/*0210*/ @P0 BRA 0x290 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0220*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R17, [R4.64] ; /* 0x0000000604117981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R19, RZ, RZ, 0x1 ; /* 0x00000001ff137424 */
/* 0x000fe400078e00ff */
/*0260*/ IMAD R17, R10, c[0x0][0x178], R17 ; /* 0x00005e000a117a24 */
/* 0x004fc800078e0211 */
/*0270*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fca00078e0210 */
/*0280*/ RED.E.ADD.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0001e4000c10e186 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R6, R15, PT ; /* 0x0000000f0600720c */
/* 0x000fe20003f04070 */
/*02c0*/ BSSY B0, 0x370 ; /* 0x000000a000007945 */
/* 0x000fe80003800000 */
/*02d0*/ ISETP.NE.OR P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x000fda000c705670 */
/*02e0*/ @P0 BRA 0x360 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R17, [R4.64] ; /* 0x0000000604117981 */
/* 0x001ea2000c1e1900 */
/*0310*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*0320*/ IMAD.MOV.U32 R19, RZ, RZ, 0x1 ; /* 0x00000001ff137424 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD R17, R10, c[0x0][0x178], R17 ; /* 0x00005e000a117a24 */
/* 0x004fce00078e0211 */
/*0340*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fca00078e0210 */
/*0350*/ RED.E.ADD.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0001e4000c10e186 */
/*0360*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0370*/ UIADD3 UR5, UR4, 0x2, URZ ; /* 0x0000000204057890 */
/* 0x000fe2000fffe03f */
/*0380*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fe20003f04070 */
/*0390*/ BSSY B0, 0x440 ; /* 0x000000a000007945 */
/* 0x000fe80003800000 */
/*03a0*/ ISETP.NE.OR P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x000fda000c705670 */
/*03b0*/ @P0 BRA 0x430 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R17, [R4.64] ; /* 0x0000000604117981 */
/* 0x001ea2000c1e1900 */
/*03e0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe200078e00ff */
/*03f0*/ MOV R19, 0x1 ; /* 0x0000000100137802 */
/* 0x000fe20000000f00 */
/*0400*/ IMAD R17, R10, c[0x0][0x178], R17 ; /* 0x00005e000a117a24 */
/* 0x004fc800078e0211 */
/*0410*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fca00078e0210 */
/*0420*/ RED.E.ADD.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0001e4000c10e186 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fe2000fffe03f */
/*0450*/ ISETP.GT.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fe20003f04070 */
/*0460*/ BSSY B0, 0x510 ; /* 0x000000a000007945 */
/* 0x000fe80003800000 */
/*0470*/ ISETP.NE.OR P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x000fda000c705670 */
/*0480*/ @P0 BRA 0x500 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0490*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R17, [R4.64] ; /* 0x0000000604117981 */
/* 0x001ea2000c1e1900 */
/*04b0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff107424 */
/* 0x000fe400078e00ff */
/*04c0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x1 ; /* 0x00000001ff137424 */
/* 0x000fe400078e00ff */
/*04d0*/ IMAD R17, R10, c[0x0][0x178], R17 ; /* 0x00005e000a117a24 */
/* 0x004fc800078e0211 */
/*04e0*/ IMAD.WIDE R16, R17, R16, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fca00078e0210 */
/*04f0*/ RED.E.ADD.STRONG.GPU [R16.64], R19 ; /* 0x000000131000798e */
/* 0x0001e4000c10e186 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0520*/ MOV R10, c[0x0][0x170] ; /* 0x00005c00000a7a02 */
/* 0x000fe40000000f00 */
/*0530*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe0ff */
/*0540*/ LEA R9, R10.reuse, R9, 0x2 ; /* 0x000000090a097211 */
/* 0x040fe200078e10ff */
/*0550*/ IMAD R15, R10, 0x4, R15 ; /* 0x000000040a0f7824 */
/* 0x000fe200078e020f */
/*0560*/ IADD3 R14, R8, UR4, RZ ; /* 0x00000004080e7c10 */
/* 0x000fe2000fffe0ff */
/*0570*/ IMAD R11, R10.reuse, 0x4, R11 ; /* 0x000000040a0b7824 */
/* 0x040fe200078e020b */
/*0580*/ LEA R13, R10, R13, 0x2 ; /* 0x0000000d0a0d7211 */
/* 0x000fe400078e10ff */
/*0590*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fda0003f05270 */
/*05a0*/ @P0 BRA 0x1e0 ; /* 0xfffffc3000000947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 BRA 0x720 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R0, -R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fe2000fffe1ff */
/*05e0*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*05f0*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fcc000f8e023f */
/*0600*/ ISETP.GT.U32.AND P0, PT, R6, UR5, PT ; /* 0x0000000506007c0c */
/* 0x000fe2000bf04070 */
/*0610*/ BSSY B0, 0x6d0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0620*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0630*/ ISETP.NE.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fda0004705670 */
/*0640*/ @P0 BRA 0x6c0 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*0650*/ LDG.E R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0680*/ HFMA2.MMA R13, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0d7435 */
/* 0x000fe200000001ff */
/*0690*/ IMAD R8, R8, c[0x0][0x178], R9 ; /* 0x00005e0008087a24 */
/* 0x004fc800078e0209 */
/*06a0*/ IMAD.WIDE R8, R8, R11, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020b */
/*06b0*/ RED.E.ADD.STRONG.GPU [R8.64], R13 ; /* 0x0000000d0800798e */
/* 0x0003e4000c10e186 */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*06e0*/ ULDC UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000800 */
/*06f0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0700*/ UIADD3 UR5, UR5, UR8, URZ ; /* 0x0000000805057290 */
/* 0x000fd4000fffe03f */
/*0710*/ @P0 BRA 0x600 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20glcm_calculation_135PiS_iii
.globl _Z20glcm_calculation_135PiS_iii
.p2align 8
.type _Z20glcm_calculation_135PiS_iii,@function
_Z20glcm_calculation_135PiS_iii:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b32 s3, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mov_b32_e32 v1, 0
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s3, s14, s3
s_load_b32 s0, s[0:1], 0x18
s_mov_b32 s1, 0
v_mov_b32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s2
v_add3_u32 v0, s3, v0, v2
s_sub_i32 s3, 0, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v2, s2, -1, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v7, vcc_lo
v_mov_b32_e32 v5, 1
s_mov_b32 s4, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s4, s4, 1
s_add_i32 s1, s1, s2
s_cmp_lg_u32 s2, s4
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_add_i32 s5, s3, s4
v_cmp_lt_u32_e32 vcc_lo, s1, v0
s_cmp_eq_u32 s5, 1
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, s5, vcc_lo
s_and_saveexec_b32 s5, s8
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v9, v[1:2], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, s0, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[6:7], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_atomic_add_u32 v[6:7], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20glcm_calculation_135PiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20glcm_calculation_135PiS_iii, .Lfunc_end0-_Z20glcm_calculation_135PiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20glcm_calculation_135PiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20glcm_calculation_135PiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000847a3_00000000-6_glcm_calculation_135.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii
.type _Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii, @function
_Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20glcm_calculation_135PiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii, .-_Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii
.globl _Z20glcm_calculation_135PiS_iii
.type _Z20glcm_calculation_135PiS_iii, @function
_Z20glcm_calculation_135PiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20glcm_calculation_135PiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20glcm_calculation_135PiS_iii, .-_Z20glcm_calculation_135PiS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20glcm_calculation_135PiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20glcm_calculation_135PiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "glcm_calculation_135.hip"
.globl _Z35__device_stub__glcm_calculation_135PiS_iii # -- Begin function _Z35__device_stub__glcm_calculation_135PiS_iii
.p2align 4, 0x90
.type _Z35__device_stub__glcm_calculation_135PiS_iii,@function
_Z35__device_stub__glcm_calculation_135PiS_iii: # @_Z35__device_stub__glcm_calculation_135PiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20glcm_calculation_135PiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__glcm_calculation_135PiS_iii, .Lfunc_end0-_Z35__device_stub__glcm_calculation_135PiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20glcm_calculation_135PiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20glcm_calculation_135PiS_iii,@object # @_Z20glcm_calculation_135PiS_iii
.section .rodata,"a",@progbits
.globl _Z20glcm_calculation_135PiS_iii
.p2align 3, 0x0
_Z20glcm_calculation_135PiS_iii:
.quad _Z35__device_stub__glcm_calculation_135PiS_iii
.size _Z20glcm_calculation_135PiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20glcm_calculation_135PiS_iii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__glcm_calculation_135PiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20glcm_calculation_135PiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #import <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
void error(char const *str)
{
fprintf(stderr, "%s\n", str);
exit(1);
}
void cuda_check(cudaError_t err, char const *str)
{
if (err != cudaSuccess) {
fprintf(stderr, "%s: CUDA error %d (%s)\n",
str, err, cudaGetErrorString(err));
}
}
__host__ __device__
float4 operator+(const float4 &a, const float4 &b)
{
return make_float4(a.x + b.x, a.y + b.y, a.z + b.z, a.w + b.w);
}
__host__ __device__
float4 operator-(const float4 &a, const float4 &b)
{
return make_float4(a.x - b.x, a.y -b.y, a.z - b.z, a.w - b.w);
}
__global__
void init_vec(int nels, float4* __restrict__ d_vec1)
{
int Idx = threadIdx.x + blockIdx.x * blockDim.x;
int i= Idx*4;
d_vec1[Idx].x = i;
d_vec1[Idx].y = i+1;
d_vec1[Idx].z = i+2;
d_vec1[Idx].w = i+3;
}
__global__
void multi_vec2(int nels,int n_row1,int n_col1,int n_row2,int n_col2,float4* __restrict__ res_vec,
float* __restrict__ d_vec1,float* __restrict__ d_vec2)
{
int Idx = threadIdx.x + blockIdx.x * blockDim.x;
int i= Idx*4;
int r_res,c_res;
r_res=n_row1;
c_res=n_row2*n_col2;
if(i<(r_res*c_res)){
int c= ((int)(i/c_res))*n_row1 + ((int)(i%n_col1))%n_col1;
int j= ((int)(((int)(i%c_res))/n_row2) + (((int)(i%c_res))%n_row2)*n_col2);
res_vec[Idx].x=d_vec1[c]*d_vec2[j];
int c1= ((int)((i+1)/c_res))*n_row1 + ((int)((i+1)%n_col1))%n_col1;
int j1= ((int)(((int)((i+1)%c_res))/n_row2) + (((int)((i+1)%c_res))%n_row2)*n_col2);
res_vec[Idx].y=d_vec1[c1]*d_vec2[j1];
int c2= ((int)((i+2)/c_res))*n_row1 + ((int)((i+2)%n_col1))%n_col1;
int j2= ((int)(((int)((i+2)%c_res))/n_row2) + (((int)((i+2)%c_res))%n_row2)*n_col2);
res_vec[Idx].z=d_vec1[c2]*d_vec2[j2];
int c3= ((int)((i+3)/c_res))*n_row1 + ((int)((i+3)%n_col1))%n_col1;
int j3= ((int)(((int)((i+3)%c_res))/n_row2) + (((int)((i+3)%c_res))%n_row2)*n_col2);
res_vec[Idx].w=d_vec1[c3]*d_vec2[j3];
}
}
__global__
void multi_vec(int nels,int n_row1,int n_col1,int n_row2,int n_col2,float4* __restrict__ res_vec,
float4* __restrict__ d_vec1,float4* __restrict__ d_vec2)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int r_res,c_res;
r_res=n_row1;
c_res=n_row2*n_col2;
if(i<(r_res*c_res)){
int c= ((int)(i/c_res))*n_col1 + ((int)(i%n_col1))%n_col1;
int j= ((int)(((int)(i%c_res))/n_row2) + (((int)(i%c_res))%n_row2)*n_col2);
res_vec[i].x=d_vec1[c].x*d_vec2[j].x;
res_vec[i].y=d_vec1[c].y*d_vec2[j].y;
res_vec[i].z=d_vec1[c].z*d_vec2[j].z;
res_vec[i].w=d_vec1[c].w*d_vec2[j].w;
}
}
__global__
void scalareMatrice( float4* __restrict__ res_vec,float scalar,float4* __restrict__ d_vec)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
res_vec[i].x=d_vec[i].x*scalar;
res_vec[i].y=d_vec[i].y*scalar;
res_vec[i].z=d_vec[i].z*scalar;
res_vec[i].w=d_vec[i].w*scalar;
}
__global__
void reduction_row2(int nels,int l_elem,float4* res_vec, float4* d_vec1)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
const float4 noels = make_float4(0.0, 0.0, 0.0, 0.0);
const int nquarts = nels*4;
const int elem=nels/l_elem;
//int i=idx*l_elem;
int i0 = idx;
int i1 = idx + 1;
int i2 = idx + 2;
int i3 = idx + 3;
__syncthreads();
float4 r0;
if(l_elem >= 4){
r0=d_vec1[i0];
}
else r0= noels;
float4 r1;
if(l_elem >= 8){
r1=d_vec1[i1];
}
else r1= noels;
float4 r2;
if(l_elem >= 12){
r2=d_vec1[i2];
}
else r2= noels;
float4 r3;
if(l_elem >= 16){
r3=d_vec1[i3];
}
else r3= noels;
float4 v = (r0 + r1) + (r2 + r3);
if (idx < nels){
if(idx%4==0)
res_vec[idx].x = (v.x + v.y) + (v.z + v.w);
if(idx%4==1)
res_vec[idx].y = (v.x + v.y) + (v.z + v.w);
if(idx%4==2)
res_vec[idx].z = (v.x + v.y) + (v.z + v.w);
if(idx%4==3)
res_vec[idx].w = (v.x + v.y) + (v.z + v.w);
}
}
__global__
void reduction_row(int nels,int l_elem,float4* res_vec, float4* d_vec1)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
const float4 noels = make_float4(0.0, 0.0, 0.0, 0.0);
const int nquarts = nels*4;
const int elem=nels/l_elem;
int i=idx*(l_elem/4);
int i0 = i;
int i1 = i + 1;
int i2 = i + 2;
int i3 = i + 3;
__syncthreads();
float4 r0;
if(l_elem >= 4){
r0=d_vec1[i0];
}
else r0= noels;
float4 r1;
if(l_elem >= 8){
r1=d_vec1[i1];
}
else r1= noels;
float4 r2;
if(l_elem >= 12){
r2=d_vec1[i2];
}
else r2= noels;
float4 r3;
if(l_elem >= 16){
r3=d_vec1[i3];
}
else r3= noels;
float4 v = (r0 + r1) + (r2 + r3);
if (idx < nels){
int x= idx/4;
if(idx%4==0)
res_vec[x].x = (v.x + v.y) + (v.z + v.w);
if(idx%4==1)
res_vec[x].y = (v.x + v.y) + (v.z + v.w);
if(idx%4==2)
res_vec[x].z = (v.x + v.y) + (v.z + v.w);
if(idx%4==3)
res_vec[x].w = (v.x + v.y) + (v.z + v.w);
}
}
__global__
void transpose(int nrow,int ncols, float4* __restrict__ res_vec, float4* __restrict__ d_vec1)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int c =i%ncols;
int r=i/ncols;
int l_in = r*ncols + c;
int l_out = c * nrow + r;
res_vec[l_out].x = d_vec1[l_in].x;
res_vec[l_out].y = d_vec1[l_in].y;
res_vec[l_out].z = d_vec1[l_in].z;
res_vec[l_out].w = d_vec1[l_in].w;
}
__global__
void vecsum(int nels, float4* __restrict__ res_vec, float4* __restrict__ d_vec1, float4* __restrict__ d_vec2)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;;
res_vec[i] =d_vec1[i]+d_vec2[i];
}
__global__
void vecdif(int nels, float4* __restrict__ res_vec, float4* __restrict__ d_vec1, float4* __restrict__ d_vec2)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
res_vec[i] =d_vec1[i]-d_vec2[i];
}
void stampa(float* matrice,int m){
int i,j;
printf("\n");
for(i=0;i<m;i++){
printf("%f ",matrice[i]);
printf("\n");
}
}
int main(int argc, char *argv[]){
float4* matriceA;
float4* matriceB;
float4* matriceX;
float4* pk;
float4* trasposta;
float4* prodotto;
float4* somma;
float4* res;
float4* den;
float4* res0;
float4* res1;
float4* res2;
float4* red_den;
float* matrice;
float4* scalar;
float4* num;
float4* deno;
float ak;
int nels;
if (argc != 2) {
error("syntax: vecsum nels v");
}
int N = atoi(argv[1]);
if (N < 0) {
error("N < 0");
}
int M=1;
nels=N*N;
size_t memsize = nels*sizeof(float);
cudaError_t err;
err = cudaMalloc((void**)&matriceA, memsize);
cuda_check(err, "alloc matriceA");
err = cudaMalloc((void**)&matriceB, N*M*sizeof(float));
cuda_check(err, "alloc matriceB");
err = cudaMalloc((void**)&matriceX, N*sizeof(float));
cuda_check(err, "alloc matriceX");
err = cudaMallocHost(&matrice, N*N*sizeof(float));
cuda_check(err, "alloc matrice");
err = cudaMallocHost(&num, M*sizeof(float));
cuda_check(err, "alloc matrice");
err = cudaMallocHost(&deno, M*sizeof(float));
cuda_check(err, "alloc matrice");
err = cudaMalloc((void**)&somma,nels*M*sizeof(float));
cuda_check(err, "alloc somma");
err = cudaMalloc((void**)&res,M*N*N*sizeof(float));
cuda_check(err, "alloc res");
err = cudaMalloc((void**)&res0,N*M*N*sizeof(float));
cuda_check(err, "alloc res0");
err = cudaMalloc((void**)&prodotto,M*N*N*sizeof(float));
cuda_check(err, "alloc prodotto");
err = cudaMalloc((void**)&res1,M*N*sizeof(float));
cuda_check(err, "alloc res1");
err = cudaMalloc((void**)&res2,M*N*N*sizeof(float));
cuda_check(err, "alloc res2");
err = cudaMalloc((void**)&pk,M*N*sizeof(float));
cuda_check(err, "alloc pk");
err = cudaMalloc((void**)&trasposta,M*N*sizeof(float));
cuda_check(err, "alloc trasposta ");
err = cudaMalloc((void**)&den,M*N*sizeof(float));
cuda_check(err, "alloc den");
err = cudaMalloc((void**)&red_den,M*N*sizeof(float));
cuda_check(err, "alloc den");
err = cudaMalloc((void**)&scalar,M*N*sizeof(float));
cuda_check(err, "alloc scalar");
cudaEvent_t pre_init, post_init, pre_sum, post_sum,pre_prodotto,post_prodotto,
pre_transpose,post_transpose,pre_scalar_matrice,post_scalar_matrice,pre_vecsum,post_vecsum,
pre_vecdif,post_vecdif;
err = cudaEventCreate(&pre_init, 0);
cuda_check(err, "create pre_init");
err = cudaEventCreate(&pre_prodotto, 0);
cuda_check(err, "create pre_sum");
err = cudaEventCreate(&pre_transpose, 0);
cuda_check(err, "create pre_traspose");
err = cudaEventCreate(&pre_scalar_matrice, 0);
cuda_check(err, "create pre_scalar_matrice");
err = cudaEventCreate(&pre_vecdif, 0);
cuda_check(err, "create pre_vecdif");
err = cudaEventCreate(&pre_vecsum, 0);
cuda_check(err, "create pre_vecsum");
err = cudaEventCreate(&post_init, 0);
cuda_check(err, "create post_init");
err = cudaEventCreate(&post_prodotto, 0);
cuda_check(err, "create post_sum");
err = cudaEventCreate(&post_transpose, 0);
cuda_check(err, "create post_traspose");
err = cudaEventCreate(&post_scalar_matrice, 0);
cuda_check(err, "create post_scalar_matrice");
err = cudaEventCreate(&post_vecdif, 0);
cuda_check(err, "create post_vecdif");
err = cudaEventCreate(&post_vecsum, 0);
cuda_check(err, "create post_vecsum");
const int blockSize = 1024;
int numBlocks = (nels/4 + blockSize - 1)/blockSize;
cudaEventRecord(pre_init);
init_vec<<<blockSize,numBlocks>>>(nels, matriceA);
cudaEventRecord(post_init);
numBlocks = (M*N/4 + blockSize - 1)/blockSize;
init_vec<<<blockSize, numBlocks>>>(M*N, matriceB);
init_vec<<<blockSize, numBlocks>>>(M*N, matriceX);
int i;
//calcolo i parametri della riduzione
int THREAD_LOAD=0;
float n = N;
while (n > 1) {
n/=4;
if(n==1){
THREAD_LOAD=4;
}
}
n = N;
while (n > 1) {
n/=8;
if(n==1){
THREAD_LOAD=8;
}
}
n=N;
while (n > 1) {
n/=12;
if(n==1){
THREAD_LOAD=12;
}
}
n=N;
while (n > 1) {
n/=16;
if(n==1){
THREAD_LOAD=16;
}
}
if(THREAD_LOAD==0){
printf("Errore N deve essere una potenza di 4,8,12,16");
exit(0);
}
int j;
int c=N;
float* temp;
float runtime_red_ms;
int lr=0;
int log=N*N;
while(log>N){
++lr;
log=log/THREAD_LOAD;
}
cudaEvent_t pre_red[lr], post_red[lr];
//inizializzo gli eventi per la riduzione
for(i=0;i<lr;i++){
err = cudaEventCreate(&(pre_red[i]), 0);
cuda_check(err, "create pre_red");
err = cudaEventCreate(&(post_red[i]), 0);
cuda_check(err, "create post_red");
}
for(i=0;i<1;i++){
numBlocks = (nels/4 + blockSize - 1)/blockSize;
cudaEventRecord(pre_prodotto);
multi_vec<<<blockSize, numBlocks>>>(nels*M/4,N,N/4,N/4,M,somma,matriceA,matriceX);
cudaEventRecord(post_prodotto);
c=N*N;
int nels_red=0;
int cont=0;
while(c>N){
c/=THREAD_LOAD;
nels_red+=c;
numBlocks = (c + blockSize - 1)/blockSize;
cudaEventRecord(pre_red[cont]);
reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res0,somma);
cudaEventRecord(post_red[cont]);
err = cudaMemcpy(somma, res0, c*sizeof(float4), cudaMemcpyDeviceToDevice);
cuda_check(err, "cpy");
cont++;
}
printf("%d %d\n",lr,nels_red );
numBlocks = ((N*M)/4 + blockSize - 1)/blockSize;
cudaEventRecord(pre_vecdif);
vecdif<<<blockSize, numBlocks>>>(N*M,pk,matriceB,res0);
cudaEventRecord(post_vecdif);
numBlocks = (N*N/4 + blockSize - 1)/blockSize;
cudaEventRecord(pre_transpose);
transpose<<<blockSize, numBlocks>>>(N,M,trasposta,pk);
cudaEventRecord(post_transpose);
numBlocks = ((M*N)/4 + blockSize - 1)/blockSize;
multi_vec<<<blockSize, numBlocks>>>(N*M/4,M,N/4,N/4,M,prodotto,trasposta,pk);
c=N;
while (c>1) {
c/=THREAD_LOAD;
numBlocks = (c + blockSize - 1)/blockSize;
reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res1,prodotto);
err = cudaMemcpy(prodotto, res1, c*sizeof(float), cudaMemcpyDeviceToDevice);
cuda_check(err, "cpy");
}
numBlocks = ((M*N*N*M)/4 + blockSize - 1)/blockSize;
multi_vec2<<<blockSize, numBlocks>>>(M*N*N*M/4,M,N,N,N,res,(float*)trasposta,(float*)matriceA);
c=N*N;
while (c>N) {
c/=THREAD_LOAD;
numBlocks = (c + blockSize - 1)/blockSize;
reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res2,res);
err = cudaMemcpy(res, res2, c*sizeof(float), cudaMemcpyDeviceToDevice);
cuda_check(err, "cpy");
}
numBlocks = ((N*N)/4 + blockSize - 1)/blockSize;
multi_vec<<<blockSize, numBlocks>>>(N*N/4 ,M,N/4,N/4,M,den,res2,pk);
c=N;
while (c>1) {
c/=THREAD_LOAD;
numBlocks = (c + blockSize - 1)/blockSize;
reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,red_den,den);
err = cudaMemcpy(den, red_den, c*sizeof(float), cudaMemcpyDeviceToDevice);
cuda_check(err, "cpy");
}
err = cudaMemcpy(num, res1, 1*sizeof(float), cudaMemcpyDeviceToHost);
err = cudaMemcpy(deno, red_den, 1*sizeof(float), cudaMemcpyDeviceToHost);
ak=num[0].x/deno[0].x;
printf("%f\n",ak );
numBlocks = (N/4 + blockSize - 1)/blockSize;
cudaEventRecord(pre_scalar_matrice);
scalareMatrice<<<blockSize, numBlocks>>>(scalar,ak,pk);
cudaEventRecord(post_scalar_matrice);
numBlocks = ((N*M)/4 + blockSize - 1)/blockSize;
cudaEventRecord(pre_vecsum);
vecsum<<<blockSize, numBlocks>>>(N*M,matriceX,matriceX,scalar);
cudaEventRecord(post_vecsum);
err = cudaMemcpy(matrice, matriceX, M*N*sizeof(float), cudaMemcpyDeviceToHost);
cuda_check(err, "create mem");
stampa(matrice,M*N);
float runtime_init_ms, runtime_prodotto_ms, runtime_red_ms,runtime_transpose_ms,runtime_scalar_matrice_ms,
runtime_vecdif_ms,runtime_vecsum_ms,runtime_red_count_ms;
err = cudaEventElapsedTime(&runtime_init_ms, pre_init, post_init);
cuda_check(err, "elapsed time init");
err = cudaEventElapsedTime(&runtime_prodotto_ms, pre_prodotto, post_prodotto);
cuda_check(err, "elapsed time prodotto");
runtime_red_count_ms=0;
for(j=0;j<lr;j++){
err = cudaEventElapsedTime(&runtime_red_ms, pre_red[j], post_red[j]);
cuda_check(err, "elapsed time reduction");
runtime_red_count_ms+=runtime_red_ms;
}
err = cudaEventElapsedTime(&runtime_transpose_ms, pre_transpose, post_transpose);
cuda_check(err, "elapsed time traspose");
err = cudaEventElapsedTime(&runtime_scalar_matrice_ms, pre_scalar_matrice, post_scalar_matrice);
cuda_check(err, "elapsed time scalar_matrice");
err = cudaEventElapsedTime(&runtime_vecdif_ms, pre_vecdif, post_vecdif);
cuda_check(err, "elapsed time vecdif");
err = cudaEventElapsedTime(&runtime_vecsum_ms, pre_vecsum, post_vecsum);
cuda_check(err, "elapsed time vecsum");
printf("init: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_init_ms, nels/runtime_init_ms/1.0e6, memsize/runtime_init_ms/1.0e6);
printf("prodotto: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_prodotto_ms, nels/runtime_prodotto_ms/1.0e6, memsize/runtime_prodotto_ms/1.0e6);
printf("reduction: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_red_count_ms, nels_red/runtime_red_count_ms/1.0e6, (nels_red*sizeof(float))/runtime_red_count_ms/1.0e6);
printf("transpose: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_transpose_ms, N/runtime_transpose_ms/1.0e6, (N*sizeof(float))/runtime_transpose_ms/1.0e6);
printf("scalareMatrice: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_scalar_matrice_ms, N/runtime_scalar_matrice_ms/1.0e6, (N*sizeof(float))/runtime_scalar_matrice_ms/1.0e6);
printf("vecdif: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_vecdif_ms, N/runtime_vecdif_ms/1.0e6, (N*sizeof(float))/runtime_vecdif_ms/1.0e6);
printf("vecsum: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_vecsum_ms, N/runtime_vecsum_ms/1.0e6, (N*sizeof(float))/runtime_vecsum_ms/1.0e6);
}
cudaFree(matriceA);
cudaFreeHost(matrice);
cudaFree(somma);
cudaFree(res);
cudaFree(pk);
cudaFree(trasposta);
cudaFree(prodotto);
cudaFree(den);
cudaFree(res0);
cudaFree(res1);
cudaFree(res2);
cudaFree(red_den);
cudaFree(scalar);
cudaFree(matriceB);
cudaFree(matriceX);
cudaFreeHost(num);
cudaFreeHost(deno);
} | #import <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
void error(char const *str)
{
fprintf(stderr, "%s\n", str);
exit(1);
}
void cuda_check(hipError_t err, char const *str)
{
if (err != hipSuccess) {
fprintf(stderr, "%s: CUDA error %d (%s)\n",
str, err, hipGetErrorString(err));
}
}
__host__ __device__
float4 operator+(const float4 &a, const float4 &b)
{
return make_float4(a.x + b.x, a.y + b.y, a.z + b.z, a.w + b.w);
}
__host__ __device__
float4 operator-(const float4 &a, const float4 &b)
{
return make_float4(a.x - b.x, a.y -b.y, a.z - b.z, a.w - b.w);
}
__global__
void init_vec(int nels, float4* __restrict__ d_vec1)
{
int Idx = threadIdx.x + blockIdx.x * blockDim.x;
int i= Idx*4;
d_vec1[Idx].x = i;
d_vec1[Idx].y = i+1;
d_vec1[Idx].z = i+2;
d_vec1[Idx].w = i+3;
}
__global__
void multi_vec2(int nels,int n_row1,int n_col1,int n_row2,int n_col2,float4* __restrict__ res_vec,
float* __restrict__ d_vec1,float* __restrict__ d_vec2)
{
int Idx = threadIdx.x + blockIdx.x * blockDim.x;
int i= Idx*4;
int r_res,c_res;
r_res=n_row1;
c_res=n_row2*n_col2;
if(i<(r_res*c_res)){
int c= ((int)(i/c_res))*n_row1 + ((int)(i%n_col1))%n_col1;
int j= ((int)(((int)(i%c_res))/n_row2) + (((int)(i%c_res))%n_row2)*n_col2);
res_vec[Idx].x=d_vec1[c]*d_vec2[j];
int c1= ((int)((i+1)/c_res))*n_row1 + ((int)((i+1)%n_col1))%n_col1;
int j1= ((int)(((int)((i+1)%c_res))/n_row2) + (((int)((i+1)%c_res))%n_row2)*n_col2);
res_vec[Idx].y=d_vec1[c1]*d_vec2[j1];
int c2= ((int)((i+2)/c_res))*n_row1 + ((int)((i+2)%n_col1))%n_col1;
int j2= ((int)(((int)((i+2)%c_res))/n_row2) + (((int)((i+2)%c_res))%n_row2)*n_col2);
res_vec[Idx].z=d_vec1[c2]*d_vec2[j2];
int c3= ((int)((i+3)/c_res))*n_row1 + ((int)((i+3)%n_col1))%n_col1;
int j3= ((int)(((int)((i+3)%c_res))/n_row2) + (((int)((i+3)%c_res))%n_row2)*n_col2);
res_vec[Idx].w=d_vec1[c3]*d_vec2[j3];
}
}
__global__
void multi_vec(int nels,int n_row1,int n_col1,int n_row2,int n_col2,float4* __restrict__ res_vec,
float4* __restrict__ d_vec1,float4* __restrict__ d_vec2)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int r_res,c_res;
r_res=n_row1;
c_res=n_row2*n_col2;
if(i<(r_res*c_res)){
int c= ((int)(i/c_res))*n_col1 + ((int)(i%n_col1))%n_col1;
int j= ((int)(((int)(i%c_res))/n_row2) + (((int)(i%c_res))%n_row2)*n_col2);
res_vec[i].x=d_vec1[c].x*d_vec2[j].x;
res_vec[i].y=d_vec1[c].y*d_vec2[j].y;
res_vec[i].z=d_vec1[c].z*d_vec2[j].z;
res_vec[i].w=d_vec1[c].w*d_vec2[j].w;
}
}
__global__
void scalareMatrice( float4* __restrict__ res_vec,float scalar,float4* __restrict__ d_vec)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
res_vec[i].x=d_vec[i].x*scalar;
res_vec[i].y=d_vec[i].y*scalar;
res_vec[i].z=d_vec[i].z*scalar;
res_vec[i].w=d_vec[i].w*scalar;
}
__global__
void reduction_row2(int nels,int l_elem,float4* res_vec, float4* d_vec1)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
const float4 noels = make_float4(0.0, 0.0, 0.0, 0.0);
const int nquarts = nels*4;
const int elem=nels/l_elem;
//int i=idx*l_elem;
int i0 = idx;
int i1 = idx + 1;
int i2 = idx + 2;
int i3 = idx + 3;
__syncthreads();
float4 r0;
if(l_elem >= 4){
r0=d_vec1[i0];
}
else r0= noels;
float4 r1;
if(l_elem >= 8){
r1=d_vec1[i1];
}
else r1= noels;
float4 r2;
if(l_elem >= 12){
r2=d_vec1[i2];
}
else r2= noels;
float4 r3;
if(l_elem >= 16){
r3=d_vec1[i3];
}
else r3= noels;
float4 v = (r0 + r1) + (r2 + r3);
if (idx < nels){
if(idx%4==0)
res_vec[idx].x = (v.x + v.y) + (v.z + v.w);
if(idx%4==1)
res_vec[idx].y = (v.x + v.y) + (v.z + v.w);
if(idx%4==2)
res_vec[idx].z = (v.x + v.y) + (v.z + v.w);
if(idx%4==3)
res_vec[idx].w = (v.x + v.y) + (v.z + v.w);
}
}
__global__
void reduction_row(int nels,int l_elem,float4* res_vec, float4* d_vec1)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
const float4 noels = make_float4(0.0, 0.0, 0.0, 0.0);
const int nquarts = nels*4;
const int elem=nels/l_elem;
int i=idx*(l_elem/4);
int i0 = i;
int i1 = i + 1;
int i2 = i + 2;
int i3 = i + 3;
__syncthreads();
float4 r0;
if(l_elem >= 4){
r0=d_vec1[i0];
}
else r0= noels;
float4 r1;
if(l_elem >= 8){
r1=d_vec1[i1];
}
else r1= noels;
float4 r2;
if(l_elem >= 12){
r2=d_vec1[i2];
}
else r2= noels;
float4 r3;
if(l_elem >= 16){
r3=d_vec1[i3];
}
else r3= noels;
float4 v = (r0 + r1) + (r2 + r3);
if (idx < nels){
int x= idx/4;
if(idx%4==0)
res_vec[x].x = (v.x + v.y) + (v.z + v.w);
if(idx%4==1)
res_vec[x].y = (v.x + v.y) + (v.z + v.w);
if(idx%4==2)
res_vec[x].z = (v.x + v.y) + (v.z + v.w);
if(idx%4==3)
res_vec[x].w = (v.x + v.y) + (v.z + v.w);
}
}
__global__
void transpose(int nrow,int ncols, float4* __restrict__ res_vec, float4* __restrict__ d_vec1)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int c =i%ncols;
int r=i/ncols;
int l_in = r*ncols + c;
int l_out = c * nrow + r;
res_vec[l_out].x = d_vec1[l_in].x;
res_vec[l_out].y = d_vec1[l_in].y;
res_vec[l_out].z = d_vec1[l_in].z;
res_vec[l_out].w = d_vec1[l_in].w;
}
__global__
void vecsum(int nels, float4* __restrict__ res_vec, float4* __restrict__ d_vec1, float4* __restrict__ d_vec2)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;;
res_vec[i] =d_vec1[i]+d_vec2[i];
}
__global__
void vecdif(int nels, float4* __restrict__ res_vec, float4* __restrict__ d_vec1, float4* __restrict__ d_vec2)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
res_vec[i] =d_vec1[i]-d_vec2[i];
}
void stampa(float* matrice,int m){
int i,j;
printf("\n");
for(i=0;i<m;i++){
printf("%f ",matrice[i]);
printf("\n");
}
}
int main(int argc, char *argv[]){
float4* matriceA;
float4* matriceB;
float4* matriceX;
float4* pk;
float4* trasposta;
float4* prodotto;
float4* somma;
float4* res;
float4* den;
float4* res0;
float4* res1;
float4* res2;
float4* red_den;
float* matrice;
float4* scalar;
float4* num;
float4* deno;
float ak;
int nels;
if (argc != 2) {
error("syntax: vecsum nels v");
}
int N = atoi(argv[1]);
if (N < 0) {
error("N < 0");
}
int M=1;
nels=N*N;
size_t memsize = nels*sizeof(float);
hipError_t err;
err = hipMalloc((void**)&matriceA, memsize);
cuda_check(err, "alloc matriceA");
err = hipMalloc((void**)&matriceB, N*M*sizeof(float));
cuda_check(err, "alloc matriceB");
err = hipMalloc((void**)&matriceX, N*sizeof(float));
cuda_check(err, "alloc matriceX");
err = hipHostMalloc(&matrice, N*N*sizeof(float), hipHostMallocDefault);
cuda_check(err, "alloc matrice");
err = hipHostMalloc(&num, M*sizeof(float), hipHostMallocDefault);
cuda_check(err, "alloc matrice");
err = hipHostMalloc(&deno, M*sizeof(float), hipHostMallocDefault);
cuda_check(err, "alloc matrice");
err = hipMalloc((void**)&somma,nels*M*sizeof(float));
cuda_check(err, "alloc somma");
err = hipMalloc((void**)&res,M*N*N*sizeof(float));
cuda_check(err, "alloc res");
err = hipMalloc((void**)&res0,N*M*N*sizeof(float));
cuda_check(err, "alloc res0");
err = hipMalloc((void**)&prodotto,M*N*N*sizeof(float));
cuda_check(err, "alloc prodotto");
err = hipMalloc((void**)&res1,M*N*sizeof(float));
cuda_check(err, "alloc res1");
err = hipMalloc((void**)&res2,M*N*N*sizeof(float));
cuda_check(err, "alloc res2");
err = hipMalloc((void**)&pk,M*N*sizeof(float));
cuda_check(err, "alloc pk");
err = hipMalloc((void**)&trasposta,M*N*sizeof(float));
cuda_check(err, "alloc trasposta ");
err = hipMalloc((void**)&den,M*N*sizeof(float));
cuda_check(err, "alloc den");
err = hipMalloc((void**)&red_den,M*N*sizeof(float));
cuda_check(err, "alloc den");
err = hipMalloc((void**)&scalar,M*N*sizeof(float));
cuda_check(err, "alloc scalar");
hipEvent_t pre_init, post_init, pre_sum, post_sum,pre_prodotto,post_prodotto,
pre_transpose,post_transpose,pre_scalar_matrice,post_scalar_matrice,pre_vecsum,post_vecsum,
pre_vecdif,post_vecdif;
err = hipEventCreateWithFlags(&pre_init, 0);
cuda_check(err, "create pre_init");
err = hipEventCreateWithFlags(&pre_prodotto, 0);
cuda_check(err, "create pre_sum");
err = hipEventCreateWithFlags(&pre_transpose, 0);
cuda_check(err, "create pre_traspose");
err = hipEventCreateWithFlags(&pre_scalar_matrice, 0);
cuda_check(err, "create pre_scalar_matrice");
err = hipEventCreateWithFlags(&pre_vecdif, 0);
cuda_check(err, "create pre_vecdif");
err = hipEventCreateWithFlags(&pre_vecsum, 0);
cuda_check(err, "create pre_vecsum");
err = hipEventCreateWithFlags(&post_init, 0);
cuda_check(err, "create post_init");
err = hipEventCreateWithFlags(&post_prodotto, 0);
cuda_check(err, "create post_sum");
err = hipEventCreateWithFlags(&post_transpose, 0);
cuda_check(err, "create post_traspose");
err = hipEventCreateWithFlags(&post_scalar_matrice, 0);
cuda_check(err, "create post_scalar_matrice");
err = hipEventCreateWithFlags(&post_vecdif, 0);
cuda_check(err, "create post_vecdif");
err = hipEventCreateWithFlags(&post_vecsum, 0);
cuda_check(err, "create post_vecsum");
const int blockSize = 1024;
int numBlocks = (nels/4 + blockSize - 1)/blockSize;
hipEventRecord(pre_init);
init_vec<<<blockSize,numBlocks>>>(nels, matriceA);
hipEventRecord(post_init);
numBlocks = (M*N/4 + blockSize - 1)/blockSize;
init_vec<<<blockSize, numBlocks>>>(M*N, matriceB);
init_vec<<<blockSize, numBlocks>>>(M*N, matriceX);
int i;
//calcolo i parametri della riduzione
int THREAD_LOAD=0;
float n = N;
while (n > 1) {
n/=4;
if(n==1){
THREAD_LOAD=4;
}
}
n = N;
while (n > 1) {
n/=8;
if(n==1){
THREAD_LOAD=8;
}
}
n=N;
while (n > 1) {
n/=12;
if(n==1){
THREAD_LOAD=12;
}
}
n=N;
while (n > 1) {
n/=16;
if(n==1){
THREAD_LOAD=16;
}
}
if(THREAD_LOAD==0){
printf("Errore N deve essere una potenza di 4,8,12,16");
exit(0);
}
int j;
int c=N;
float* temp;
float runtime_red_ms;
int lr=0;
int log=N*N;
while(log>N){
++lr;
log=log/THREAD_LOAD;
}
hipEvent_t pre_red[lr], post_red[lr];
//inizializzo gli eventi per la riduzione
for(i=0;i<lr;i++){
err = hipEventCreateWithFlags(&(pre_red[i]), 0);
cuda_check(err, "create pre_red");
err = hipEventCreateWithFlags(&(post_red[i]), 0);
cuda_check(err, "create post_red");
}
for(i=0;i<1;i++){
numBlocks = (nels/4 + blockSize - 1)/blockSize;
hipEventRecord(pre_prodotto);
multi_vec<<<blockSize, numBlocks>>>(nels*M/4,N,N/4,N/4,M,somma,matriceA,matriceX);
hipEventRecord(post_prodotto);
c=N*N;
int nels_red=0;
int cont=0;
while(c>N){
c/=THREAD_LOAD;
nels_red+=c;
numBlocks = (c + blockSize - 1)/blockSize;
hipEventRecord(pre_red[cont]);
reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res0,somma);
hipEventRecord(post_red[cont]);
err = hipMemcpy(somma, res0, c*sizeof(float4), hipMemcpyDeviceToDevice);
cuda_check(err, "cpy");
cont++;
}
printf("%d %d\n",lr,nels_red );
numBlocks = ((N*M)/4 + blockSize - 1)/blockSize;
hipEventRecord(pre_vecdif);
vecdif<<<blockSize, numBlocks>>>(N*M,pk,matriceB,res0);
hipEventRecord(post_vecdif);
numBlocks = (N*N/4 + blockSize - 1)/blockSize;
hipEventRecord(pre_transpose);
transpose<<<blockSize, numBlocks>>>(N,M,trasposta,pk);
hipEventRecord(post_transpose);
numBlocks = ((M*N)/4 + blockSize - 1)/blockSize;
multi_vec<<<blockSize, numBlocks>>>(N*M/4,M,N/4,N/4,M,prodotto,trasposta,pk);
c=N;
while (c>1) {
c/=THREAD_LOAD;
numBlocks = (c + blockSize - 1)/blockSize;
reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res1,prodotto);
err = hipMemcpy(prodotto, res1, c*sizeof(float), hipMemcpyDeviceToDevice);
cuda_check(err, "cpy");
}
numBlocks = ((M*N*N*M)/4 + blockSize - 1)/blockSize;
multi_vec2<<<blockSize, numBlocks>>>(M*N*N*M/4,M,N,N,N,res,(float*)trasposta,(float*)matriceA);
c=N*N;
while (c>N) {
c/=THREAD_LOAD;
numBlocks = (c + blockSize - 1)/blockSize;
reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res2,res);
err = hipMemcpy(res, res2, c*sizeof(float), hipMemcpyDeviceToDevice);
cuda_check(err, "cpy");
}
numBlocks = ((N*N)/4 + blockSize - 1)/blockSize;
multi_vec<<<blockSize, numBlocks>>>(N*N/4 ,M,N/4,N/4,M,den,res2,pk);
c=N;
while (c>1) {
c/=THREAD_LOAD;
numBlocks = (c + blockSize - 1)/blockSize;
reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,red_den,den);
err = hipMemcpy(den, red_den, c*sizeof(float), hipMemcpyDeviceToDevice);
cuda_check(err, "cpy");
}
err = hipMemcpy(num, res1, 1*sizeof(float), hipMemcpyDeviceToHost);
err = hipMemcpy(deno, red_den, 1*sizeof(float), hipMemcpyDeviceToHost);
ak=num[0].x/deno[0].x;
printf("%f\n",ak );
numBlocks = (N/4 + blockSize - 1)/blockSize;
hipEventRecord(pre_scalar_matrice);
scalareMatrice<<<blockSize, numBlocks>>>(scalar,ak,pk);
hipEventRecord(post_scalar_matrice);
numBlocks = ((N*M)/4 + blockSize - 1)/blockSize;
hipEventRecord(pre_vecsum);
vecsum<<<blockSize, numBlocks>>>(N*M,matriceX,matriceX,scalar);
hipEventRecord(post_vecsum);
err = hipMemcpy(matrice, matriceX, M*N*sizeof(float), hipMemcpyDeviceToHost);
cuda_check(err, "create mem");
stampa(matrice,M*N);
float runtime_init_ms, runtime_prodotto_ms, runtime_red_ms,runtime_transpose_ms,runtime_scalar_matrice_ms,
runtime_vecdif_ms,runtime_vecsum_ms,runtime_red_count_ms;
err = hipEventElapsedTime(&runtime_init_ms, pre_init, post_init);
cuda_check(err, "elapsed time init");
err = hipEventElapsedTime(&runtime_prodotto_ms, pre_prodotto, post_prodotto);
cuda_check(err, "elapsed time prodotto");
runtime_red_count_ms=0;
for(j=0;j<lr;j++){
err = hipEventElapsedTime(&runtime_red_ms, pre_red[j], post_red[j]);
cuda_check(err, "elapsed time reduction");
runtime_red_count_ms+=runtime_red_ms;
}
err = hipEventElapsedTime(&runtime_transpose_ms, pre_transpose, post_transpose);
cuda_check(err, "elapsed time traspose");
err = hipEventElapsedTime(&runtime_scalar_matrice_ms, pre_scalar_matrice, post_scalar_matrice);
cuda_check(err, "elapsed time scalar_matrice");
err = hipEventElapsedTime(&runtime_vecdif_ms, pre_vecdif, post_vecdif);
cuda_check(err, "elapsed time vecdif");
err = hipEventElapsedTime(&runtime_vecsum_ms, pre_vecsum, post_vecsum);
cuda_check(err, "elapsed time vecsum");
printf("init: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_init_ms, nels/runtime_init_ms/1.0e6, memsize/runtime_init_ms/1.0e6);
printf("prodotto: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_prodotto_ms, nels/runtime_prodotto_ms/1.0e6, memsize/runtime_prodotto_ms/1.0e6);
printf("reduction: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_red_count_ms, nels_red/runtime_red_count_ms/1.0e6, (nels_red*sizeof(float))/runtime_red_count_ms/1.0e6);
printf("transpose: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_transpose_ms, N/runtime_transpose_ms/1.0e6, (N*sizeof(float))/runtime_transpose_ms/1.0e6);
printf("scalareMatrice: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_scalar_matrice_ms, N/runtime_scalar_matrice_ms/1.0e6, (N*sizeof(float))/runtime_scalar_matrice_ms/1.0e6);
printf("vecdif: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_vecdif_ms, N/runtime_vecdif_ms/1.0e6, (N*sizeof(float))/runtime_vecdif_ms/1.0e6);
printf("vecsum: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
runtime_vecsum_ms, N/runtime_vecsum_ms/1.0e6, (N*sizeof(float))/runtime_vecsum_ms/1.0e6);
}
hipFree(matriceA);
hipHostFree(matrice);
hipFree(somma);
hipFree(res);
hipFree(pk);
hipFree(trasposta);
hipFree(prodotto);
hipFree(den);
hipFree(res0);
hipFree(res1);
hipFree(res2);
hipFree(red_den);
hipFree(scalar);
hipFree(matriceB);
hipFree(matriceX);
hipHostFree(num);
hipHostFree(deno);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void one_channel_mul_kernel(float *data_l, float *data_r, float *result)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int threadId = 2 * (blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x);
int one_ch_index = 2 * ((threadIdx.y * blockDim.x) + threadIdx.x);
result[threadId] = data_l[threadId] * data_r[one_ch_index] - data_l[threadId + 1] * data_r[one_ch_index + 1];
result[threadId + 1] = data_l[threadId] * data_r[one_ch_index + 1] + data_l[threadId + 1] * data_r[one_ch_index];
} | code for sm_80
Function : _Z22one_channel_mul_kernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0030*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe20000000800 */
/*0050*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e660000002100 */
/*0070*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0080*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x002fe400078e0200 */
/*0090*/ IMAD R0, R2, c[0x0][0x4], RZ ; /* 0x0000010002007a24 */
/* 0x000fe200078e02ff */
/*00a0*/ UIMAD UR4, UR5, UR6, UR4 ; /* 0x00000006050472a4 */
/* 0x001fc4000f8e0204 */
/*00b0*/ SHF.L.U32 R4, R3, 0x1, RZ ; /* 0x0000000103047819 */
/* 0x000fc800000006ff */
/*00c0*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e0203 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e020b */
/*00f0*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fe400000006ff */
/*0100*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040404077981 */
/* 0x000ea6000c1e1900 */
/*0110*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e020b */
/*0120*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040402067981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee2000c1e1900 */
/*0150*/ FMUL R10, R6, R7 ; /* 0x00000007060a7220 */
/* 0x004fc40000400000 */
/*0160*/ IMAD.WIDE R6, R0, R11, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e020b */
/*0170*/ FFMA R9, R8, R9, -R10 ; /* 0x0000000908097223 */
/* 0x008fca000000080a */
/*0180*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe8000c101904 */
/*0190*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee8000c1e1900 */
/*01c0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ FMUL R8, R8, R13 ; /* 0x0000000d08087220 */
/* 0x004fc80000400000 */
/*01e0*/ FFMA R11, R0, R11, R8 ; /* 0x0000000b000b7223 */
/* 0x008fca0000000008 */
/*01f0*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x000fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void one_channel_mul_kernel(float *data_l, float *data_r, float *result)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int threadId = 2 * (blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x);
int one_ch_index = 2 * ((threadIdx.y * blockDim.x) + threadIdx.x);
result[threadId] = data_l[threadId] * data_r[one_ch_index] - data_l[threadId + 1] * data_r[one_ch_index + 1];
result[threadId + 1] = data_l[threadId] * data_r[one_ch_index + 1] + data_l[threadId + 1] * data_r[one_ch_index];
} | .file "tmpxft_0012831d_00000000-6_one_channel_mul_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_
.type _Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_, @function
_Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22one_channel_mul_kernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_, .-_Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_
.globl _Z22one_channel_mul_kernelPfS_S_
.type _Z22one_channel_mul_kernelPfS_S_, @function
_Z22one_channel_mul_kernelPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22one_channel_mul_kernelPfS_S_, .-_Z22one_channel_mul_kernelPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22one_channel_mul_kernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22one_channel_mul_kernelPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void one_channel_mul_kernel(float *data_l, float *data_r, float *result)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int threadId = 2 * (blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x);
int one_ch_index = 2 * ((threadIdx.y * blockDim.x) + threadIdx.x);
result[threadId] = data_l[threadId] * data_r[one_ch_index] - data_l[threadId + 1] * data_r[one_ch_index + 1];
result[threadId + 1] = data_l[threadId] * data_r[one_ch_index + 1] + data_l[threadId + 1] * data_r[one_ch_index];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void one_channel_mul_kernel(float *data_l, float *data_r, float *result)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int threadId = 2 * (blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x);
int one_ch_index = 2 * ((threadIdx.y * blockDim.x) + threadIdx.x);
result[threadId] = data_l[threadId] * data_r[one_ch_index] - data_l[threadId + 1] * data_r[one_ch_index + 1];
result[threadId + 1] = data_l[threadId] * data_r[one_ch_index + 1] + data_l[threadId + 1] * data_r[one_ch_index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void one_channel_mul_kernel(float *data_l, float *data_r, float *result)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int threadId = 2 * (blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x);
int one_ch_index = 2 * ((threadIdx.y * blockDim.x) + threadIdx.x);
result[threadId] = data_l[threadId] * data_r[one_ch_index] - data_l[threadId + 1] * data_r[one_ch_index + 1];
result[threadId + 1] = data_l[threadId] * data_r[one_ch_index + 1] + data_l[threadId + 1] * data_r[one_ch_index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22one_channel_mul_kernelPfS_S_
.globl _Z22one_channel_mul_kernelPfS_S_
.p2align 8
.type _Z22one_channel_mul_kernelPfS_S_,@function
_Z22one_channel_mul_kernelPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s4, s3, 0xffff
s_add_i32 s2, s2, s14
v_mad_u32_u24 v1, v0, s4, v1
s_lshr_b32 s3, s3, 16
s_mul_i32 s2, s2, s4
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s2, s2, s3
v_lshlrev_b32_e32 v8, 3, v1
v_add_lshl_u32 v0, v1, s2, 1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v9, 4, v8
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_b32 v10, v9, s[6:7]
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_b32 v11, v[4:5], off
global_load_b32 v12, v8, s[6:7]
global_load_b32 v13, v[6:7], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(2)
v_mul_f32_e32 v10, v11, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v10, v13, v12, -v10
global_store_b32 v[0:1], v10, off
global_load_b32 v0, v[4:5], off
global_load_b32 v1, v8, s[6:7]
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v9, s[6:7]
s_waitcnt vmcnt(2)
v_mul_f32_e32 v6, v0, v1
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v6, v4, v5
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22one_channel_mul_kernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22one_channel_mul_kernelPfS_S_, .Lfunc_end0-_Z22one_channel_mul_kernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22one_channel_mul_kernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22one_channel_mul_kernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void one_channel_mul_kernel(float *data_l, float *data_r, float *result)
{
int blockId = blockIdx.x + blockIdx.y * gridDim.x;
int threadId = 2 * (blockId * (blockDim.x * blockDim.y) + (threadIdx.y * blockDim.x) + threadIdx.x);
int one_ch_index = 2 * ((threadIdx.y * blockDim.x) + threadIdx.x);
result[threadId] = data_l[threadId] * data_r[one_ch_index] - data_l[threadId + 1] * data_r[one_ch_index + 1];
result[threadId + 1] = data_l[threadId] * data_r[one_ch_index + 1] + data_l[threadId + 1] * data_r[one_ch_index];
} | .text
.file "one_channel_mul_kernel.hip"
.globl _Z37__device_stub__one_channel_mul_kernelPfS_S_ # -- Begin function _Z37__device_stub__one_channel_mul_kernelPfS_S_
.p2align 4, 0x90
.type _Z37__device_stub__one_channel_mul_kernelPfS_S_,@function
_Z37__device_stub__one_channel_mul_kernelPfS_S_: # @_Z37__device_stub__one_channel_mul_kernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22one_channel_mul_kernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z37__device_stub__one_channel_mul_kernelPfS_S_, .Lfunc_end0-_Z37__device_stub__one_channel_mul_kernelPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22one_channel_mul_kernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22one_channel_mul_kernelPfS_S_,@object # @_Z22one_channel_mul_kernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z22one_channel_mul_kernelPfS_S_
.p2align 3, 0x0
_Z22one_channel_mul_kernelPfS_S_:
.quad _Z37__device_stub__one_channel_mul_kernelPfS_S_
.size _Z22one_channel_mul_kernelPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22one_channel_mul_kernelPfS_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__one_channel_mul_kernelPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22one_channel_mul_kernelPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22one_channel_mul_kernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0030*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe20000000800 */
/*0050*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e660000002100 */
/*0070*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0080*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x002fe400078e0200 */
/*0090*/ IMAD R0, R2, c[0x0][0x4], RZ ; /* 0x0000010002007a24 */
/* 0x000fe200078e02ff */
/*00a0*/ UIMAD UR4, UR5, UR6, UR4 ; /* 0x00000006050472a4 */
/* 0x001fc4000f8e0204 */
/*00b0*/ SHF.L.U32 R4, R3, 0x1, RZ ; /* 0x0000000103047819 */
/* 0x000fc800000006ff */
/*00c0*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e0203 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e020b */
/*00f0*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fe400000006ff */
/*0100*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040404077981 */
/* 0x000ea6000c1e1900 */
/*0110*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e020b */
/*0120*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040402067981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee2000c1e1900 */
/*0150*/ FMUL R10, R6, R7 ; /* 0x00000007060a7220 */
/* 0x004fc40000400000 */
/*0160*/ IMAD.WIDE R6, R0, R11, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e020b */
/*0170*/ FFMA R9, R8, R9, -R10 ; /* 0x0000000908097223 */
/* 0x008fca000000080a */
/*0180*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe8000c101904 */
/*0190*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee8000c1e1900 */
/*01c0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ FMUL R8, R8, R13 ; /* 0x0000000d08087220 */
/* 0x004fc80000400000 */
/*01e0*/ FFMA R11, R0, R11, R8 ; /* 0x0000000b000b7223 */
/* 0x008fca0000000008 */
/*01f0*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x000fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22one_channel_mul_kernelPfS_S_
.globl _Z22one_channel_mul_kernelPfS_S_
.p2align 8
.type _Z22one_channel_mul_kernelPfS_S_,@function
_Z22one_channel_mul_kernelPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s4, s3, 0xffff
s_add_i32 s2, s2, s14
v_mad_u32_u24 v1, v0, s4, v1
s_lshr_b32 s3, s3, 16
s_mul_i32 s2, s2, s4
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s2, s2, s3
v_lshlrev_b32_e32 v8, 3, v1
v_add_lshl_u32 v0, v1, s2, 1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v9, 4, v8
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_b32 v10, v9, s[6:7]
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_b32 v11, v[4:5], off
global_load_b32 v12, v8, s[6:7]
global_load_b32 v13, v[6:7], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(2)
v_mul_f32_e32 v10, v11, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v10, v13, v12, -v10
global_store_b32 v[0:1], v10, off
global_load_b32 v0, v[4:5], off
global_load_b32 v1, v8, s[6:7]
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v9, s[6:7]
s_waitcnt vmcnt(2)
v_mul_f32_e32 v6, v0, v1
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v6, v4, v5
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22one_channel_mul_kernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22one_channel_mul_kernelPfS_S_, .Lfunc_end0-_Z22one_channel_mul_kernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22one_channel_mul_kernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22one_channel_mul_kernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012831d_00000000-6_one_channel_mul_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_
.type _Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_, @function
_Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22one_channel_mul_kernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_, .-_Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_
.globl _Z22one_channel_mul_kernelPfS_S_
.type _Z22one_channel_mul_kernelPfS_S_, @function
_Z22one_channel_mul_kernelPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22one_channel_mul_kernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22one_channel_mul_kernelPfS_S_, .-_Z22one_channel_mul_kernelPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22one_channel_mul_kernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22one_channel_mul_kernelPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "one_channel_mul_kernel.hip"
.globl _Z37__device_stub__one_channel_mul_kernelPfS_S_ # -- Begin function _Z37__device_stub__one_channel_mul_kernelPfS_S_
.p2align 4, 0x90
.type _Z37__device_stub__one_channel_mul_kernelPfS_S_,@function
_Z37__device_stub__one_channel_mul_kernelPfS_S_: # @_Z37__device_stub__one_channel_mul_kernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22one_channel_mul_kernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z37__device_stub__one_channel_mul_kernelPfS_S_, .Lfunc_end0-_Z37__device_stub__one_channel_mul_kernelPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22one_channel_mul_kernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22one_channel_mul_kernelPfS_S_,@object # @_Z22one_channel_mul_kernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z22one_channel_mul_kernelPfS_S_
.p2align 3, 0x0
_Z22one_channel_mul_kernelPfS_S_:
.quad _Z37__device_stub__one_channel_mul_kernelPfS_S_
.size _Z22one_channel_mul_kernelPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22one_channel_mul_kernelPfS_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__one_channel_mul_kernelPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22one_channel_mul_kernelPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 2019-2020 Marc Martos. All rights reserved.
*/
//
//// System includes
//#include <iostream>
//#include <stdio.h>
//#include <assert.h>
//#include <math.h>
//
//// CUDA Runtime
//#include <cuda_runtime.h>
//
//// helper functions and utilities to work with CUDA
//#include <helper_functions.h>
//#include <helper_cuda.h>
//
//// Kernel function to add the elements of two arrays
//__global__
//void add(int n, float* x, float* y) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// y[i] = x[i] + y[i];
//}
//
//__global__
//void calcError(int n, float* y, float* err) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// *err = fmax(*err, fabs(y[i] - 3.0f));
//}
//
//int main(int argc, char** argv) {
// const int N = 1 << 20;
// float* x, * y;
// float s_x[N], s_y[N];
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&x, N * sizeof(float));
// cudaMallocManaged(&y, N * sizeof(float));
//
// // initialize x and y arrays on the host
// for (int i = 0; i < N; i++) {
// x[i] = 1.0f;
// y[i] = 2.0f;
// }
// int blockSize = 256;
// int numBlocks = (N + blockSize - 1) / blockSize;
// // Run kernel on 1M elements on the GPU
// //cudaMemcpy(x, s_x, N * sizeof(float), cudaMemcpyHostToDevice);
// add <<< numBlocks , blockSize >>> (N, x, y);
// //cudaMemcpy(s_x, x, N * sizeof(float), cudaMemcpyDeviceToHost);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// // Check for errors (all values should be 3.0f)
// float* maxError;
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&maxError, sizeof(float));
//
// // Run kernel on 1M elements on the GPU
// calcError <<< 8, 1024 >> > (N, y, maxError);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// std::cout << "Max error: " << *maxError << std::endl;
//
// // Free memory
// cudaFree(x);
// cudaFree(y);
// cudaFree(maxError);
//
// return EXIT_SUCCESS;
//} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 2019-2020 Marc Martos. All rights reserved.
*/
//
//// System includes
//#include <iostream>
//#include <stdio.h>
//#include <assert.h>
//#include <math.h>
//
//// CUDA Runtime
//#include <cuda_runtime.h>
//
//// helper functions and utilities to work with CUDA
//#include <helper_functions.h>
//#include <helper_cuda.h>
//
//// Kernel function to add the elements of two arrays
//__global__
//void add(int n, float* x, float* y) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// y[i] = x[i] + y[i];
//}
//
//__global__
//void calcError(int n, float* y, float* err) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// *err = fmax(*err, fabs(y[i] - 3.0f));
//}
//
//int main(int argc, char** argv) {
// const int N = 1 << 20;
// float* x, * y;
// float s_x[N], s_y[N];
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&x, N * sizeof(float));
// cudaMallocManaged(&y, N * sizeof(float));
//
// // initialize x and y arrays on the host
// for (int i = 0; i < N; i++) {
// x[i] = 1.0f;
// y[i] = 2.0f;
// }
// int blockSize = 256;
// int numBlocks = (N + blockSize - 1) / blockSize;
// // Run kernel on 1M elements on the GPU
// //cudaMemcpy(x, s_x, N * sizeof(float), cudaMemcpyHostToDevice);
// add <<< numBlocks , blockSize >>> (N, x, y);
// //cudaMemcpy(s_x, x, N * sizeof(float), cudaMemcpyDeviceToHost);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// // Check for errors (all values should be 3.0f)
// float* maxError;
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&maxError, sizeof(float));
//
// // Run kernel on 1M elements on the GPU
// calcError <<< 8, 1024 >> > (N, y, maxError);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// std::cout << "Max error: " << *maxError << std::endl;
//
// // Free memory
// cudaFree(x);
// cudaFree(y);
// cudaFree(maxError);
//
// return EXIT_SUCCESS;
//} | .file "tmpxft_00179534_00000000-6_Add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 2019-2020 Marc Martos. All rights reserved.
*/
//
//// System includes
//#include <iostream>
//#include <stdio.h>
//#include <assert.h>
//#include <math.h>
//
//// CUDA Runtime
//#include <cuda_runtime.h>
//
//// helper functions and utilities to work with CUDA
//#include <helper_functions.h>
//#include <helper_cuda.h>
//
//// Kernel function to add the elements of two arrays
//__global__
//void add(int n, float* x, float* y) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// y[i] = x[i] + y[i];
//}
//
//__global__
//void calcError(int n, float* y, float* err) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// *err = fmax(*err, fabs(y[i] - 3.0f));
//}
//
//int main(int argc, char** argv) {
// const int N = 1 << 20;
// float* x, * y;
// float s_x[N], s_y[N];
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&x, N * sizeof(float));
// cudaMallocManaged(&y, N * sizeof(float));
//
// // initialize x and y arrays on the host
// for (int i = 0; i < N; i++) {
// x[i] = 1.0f;
// y[i] = 2.0f;
// }
// int blockSize = 256;
// int numBlocks = (N + blockSize - 1) / blockSize;
// // Run kernel on 1M elements on the GPU
// //cudaMemcpy(x, s_x, N * sizeof(float), cudaMemcpyHostToDevice);
// add <<< numBlocks , blockSize >>> (N, x, y);
// //cudaMemcpy(s_x, x, N * sizeof(float), cudaMemcpyDeviceToHost);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// // Check for errors (all values should be 3.0f)
// float* maxError;
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&maxError, sizeof(float));
//
// // Run kernel on 1M elements on the GPU
// calcError <<< 8, 1024 >> > (N, y, maxError);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// std::cout << "Max error: " << *maxError << std::endl;
//
// // Free memory
// cudaFree(x);
// cudaFree(y);
// cudaFree(maxError);
//
// return EXIT_SUCCESS;
//} | #include <hip/hip_runtime.h>
/*
* Copyright 2019-2020 Marc Martos. All rights reserved.
*/
//
//// System includes
//#include <iostream>
//#include <stdio.h>
//#include <assert.h>
//#include <math.h>
//
//// CUDA Runtime
//#include <cuda_runtime.h>
//
//// helper functions and utilities to work with CUDA
//#include <helper_functions.h>
//#include <helper_cuda.h>
//
//// Kernel function to add the elements of two arrays
//__global__
//void add(int n, float* x, float* y) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// y[i] = x[i] + y[i];
//}
//
//__global__
//void calcError(int n, float* y, float* err) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// *err = fmax(*err, fabs(y[i] - 3.0f));
//}
//
//int main(int argc, char** argv) {
// const int N = 1 << 20;
// float* x, * y;
// float s_x[N], s_y[N];
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&x, N * sizeof(float));
// cudaMallocManaged(&y, N * sizeof(float));
//
// // initialize x and y arrays on the host
// for (int i = 0; i < N; i++) {
// x[i] = 1.0f;
// y[i] = 2.0f;
// }
// int blockSize = 256;
// int numBlocks = (N + blockSize - 1) / blockSize;
// // Run kernel on 1M elements on the GPU
// //cudaMemcpy(x, s_x, N * sizeof(float), cudaMemcpyHostToDevice);
// add <<< numBlocks , blockSize >>> (N, x, y);
// //cudaMemcpy(s_x, x, N * sizeof(float), cudaMemcpyDeviceToHost);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// // Check for errors (all values should be 3.0f)
// float* maxError;
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&maxError, sizeof(float));
//
// // Run kernel on 1M elements on the GPU
// calcError <<< 8, 1024 >> > (N, y, maxError);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// std::cout << "Max error: " << *maxError << std::endl;
//
// // Free memory
// cudaFree(x);
// cudaFree(y);
// cudaFree(maxError);
//
// return EXIT_SUCCESS;
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* Copyright 2019-2020 Marc Martos. All rights reserved.
*/
//
//// System includes
//#include <iostream>
//#include <stdio.h>
//#include <assert.h>
//#include <math.h>
//
//// CUDA Runtime
//#include <cuda_runtime.h>
//
//// helper functions and utilities to work with CUDA
//#include <helper_functions.h>
//#include <helper_cuda.h>
//
//// Kernel function to add the elements of two arrays
//__global__
//void add(int n, float* x, float* y) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// y[i] = x[i] + y[i];
//}
//
//__global__
//void calcError(int n, float* y, float* err) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// *err = fmax(*err, fabs(y[i] - 3.0f));
//}
//
//int main(int argc, char** argv) {
// const int N = 1 << 20;
// float* x, * y;
// float s_x[N], s_y[N];
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&x, N * sizeof(float));
// cudaMallocManaged(&y, N * sizeof(float));
//
// // initialize x and y arrays on the host
// for (int i = 0; i < N; i++) {
// x[i] = 1.0f;
// y[i] = 2.0f;
// }
// int blockSize = 256;
// int numBlocks = (N + blockSize - 1) / blockSize;
// // Run kernel on 1M elements on the GPU
// //cudaMemcpy(x, s_x, N * sizeof(float), cudaMemcpyHostToDevice);
// add <<< numBlocks , blockSize >>> (N, x, y);
// //cudaMemcpy(s_x, x, N * sizeof(float), cudaMemcpyDeviceToHost);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// // Check for errors (all values should be 3.0f)
// float* maxError;
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&maxError, sizeof(float));
//
// // Run kernel on 1M elements on the GPU
// calcError <<< 8, 1024 >> > (N, y, maxError);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// std::cout << "Max error: " << *maxError << std::endl;
//
// // Free memory
// cudaFree(x);
// cudaFree(y);
// cudaFree(maxError);
//
// return EXIT_SUCCESS;
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Copyright 2019-2020 Marc Martos. All rights reserved.
*/
//
//// System includes
//#include <iostream>
//#include <stdio.h>
//#include <assert.h>
//#include <math.h>
//
//// CUDA Runtime
//#include <cuda_runtime.h>
//
//// helper functions and utilities to work with CUDA
//#include <helper_functions.h>
//#include <helper_cuda.h>
//
//// Kernel function to add the elements of two arrays
//__global__
//void add(int n, float* x, float* y) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// y[i] = x[i] + y[i];
//}
//
//__global__
//void calcError(int n, float* y, float* err) {
// int index = blockIdx.x * blockDim.x + threadIdx.x;
// int stride = blockDim.x * gridDim.x;
// for (int i = index; i < n; i += stride)
// *err = fmax(*err, fabs(y[i] - 3.0f));
//}
//
//int main(int argc, char** argv) {
// const int N = 1 << 20;
// float* x, * y;
// float s_x[N], s_y[N];
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&x, N * sizeof(float));
// cudaMallocManaged(&y, N * sizeof(float));
//
// // initialize x and y arrays on the host
// for (int i = 0; i < N; i++) {
// x[i] = 1.0f;
// y[i] = 2.0f;
// }
// int blockSize = 256;
// int numBlocks = (N + blockSize - 1) / blockSize;
// // Run kernel on 1M elements on the GPU
// //cudaMemcpy(x, s_x, N * sizeof(float), cudaMemcpyHostToDevice);
// add <<< numBlocks , blockSize >>> (N, x, y);
// //cudaMemcpy(s_x, x, N * sizeof(float), cudaMemcpyDeviceToHost);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// // Check for errors (all values should be 3.0f)
// float* maxError;
//
// // Allocate Unified Memory accessible from CPU or GPU
// cudaMallocManaged(&maxError, sizeof(float));
//
// // Run kernel on 1M elements on the GPU
// calcError <<< 8, 1024 >> > (N, y, maxError);
//
// // Wait for GPU to finish before accessing on host
// cudaDeviceSynchronize();
//
// std::cout << "Max error: " << *maxError << std::endl;
//
// // Free memory
// cudaFree(x);
// cudaFree(y);
// cudaFree(maxError);
//
// return EXIT_SUCCESS;
//} | .text
.file "Add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00179534_00000000-6_Add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
//#include <helper_cuda.h>
#include <time.h>
#define BLOCK_SIZE 1024
#define NUMBER_OF_ELEMENTS 1024
__global__ void vectorAdd(const float *A, const float *B, float *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
C[i] = A[i] + B[i];
}
}
__global__ void total(float *input, float *output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float partialSum[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x, start = 2* blockIdx.x * BLOCK_SIZE;
if (start + t < len)
partialSum[t] = input[start + t];
else
partialSum[t] = 0;
if (start + BLOCK_SIZE + t < len)
partialSum[BLOCK_SIZE + t] = input[start + BLOCK_SIZE + t];
else
partialSum[BLOCK_SIZE + t] = 0;
//@@ Traverse the reduction tree
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
partialSum[t] += partialSum[t + stride];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
if (t == 0)
output[blockIdx.x] = partialSum[0];
}
int main(void)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
int numElements = NUMBER_OF_ELEMENTS;
int memorySizeIn=numElements*sizeof(float);
int memorySizeOut=sizeof(float);
printf("Calculating the sum of %d elements.\n", numElements);
printf("Allocating host vectors...\n");
// Allocate the host output vector
float *h_input = (float *)malloc(memorySizeIn);
// Allocate the host output vector
float *h_output = (float *)malloc(memorySizeIn);
// Verify that allocations succeeded
if (h_input == NULL || h_output == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Initialize the host input vector with random values
for (int i = 0; i < numElements; ++i)
{
h_input[i]=(float)rand()/(float)RAND_MAX;
// printf("%f ", h_input[i]);
}
printf("Allocating device vectors... \n");
float *d_input = NULL;
err = cudaMallocManaged((void **)&d_input, memorySizeIn);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device input vector!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device input vector allocated.\n");
float *d_output = NULL;
err = cudaMallocManaged((void **)&d_output, memorySizeIn);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device output vector!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device output vector allocated.\n");
printf("Copying input vector from the host memory to the CUDA device...\n");
err = cudaMemcpy(d_input, h_input, memorySizeIn, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy input vector from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Launch the Kernel
int threadsPerBlock = BLOCK_SIZE;
int blocksPerGrid = (numElements + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launching with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
float sumGPU = 0;
int k = 0;
int iter=0;
clock_t start=clock();
int inputElementsLeft = numElements;
while(inputElementsLeft > 0)
{
int currNumElements = inputElementsLeft;
if(inputElementsLeft > BLOCK_SIZE*2)
currNumElements = BLOCK_SIZE*2;
total<<<blocksPerGrid, threadsPerBlock>>>(d_input + k, d_output, currNumElements);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch the kernel in %d iteration (error code %s)!\n", iter, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = cudaMemcpy(h_output, d_output, memorySizeOut, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy output vector from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum = h_output[0];
sumGPU+=sum;
k+=currNumElements;
iter+=1;
inputElementsLeft-=currNumElements;
}
cudaDeviceSynchronize();
clock_t end=clock();
double time_elapsed_gpu=((double) (end - start))*1000 / CLOCKS_PER_SEC;
// Calculating the sum using CPU
float sumCPU=0;
for (int i=0; i<numElements; i++) {
sumCPU+=h_input[i];
}
printf("GPU sum is %f and CPU sum is %f.\n", sumGPU, sumCPU);
printf("Time elapsed for GPU computations: %lf ms.\n", time_elapsed_gpu);
// Free device memory
err = cudaFree(d_input);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free input vector (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_output);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free output vector (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
free(h_input);
free(h_output);
return 0;
} | code for sm_80
Function : _Z5totalPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ LEA R4, R0, R3, 0xb ; /* 0x0000000300047211 */
/* 0x001fc800078e58ff */
/*0050*/ IADD3 R6, R4.reuse, 0x400, RZ ; /* 0x0000040004067810 */
/* 0x040fe40007ffe0ff */
/*0060*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f26070 */
/*0070*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fd60003f46070 */
/*0080*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff059424 */
/* 0x000fe400078e00ff */
/*0090*/ @!P2 MOV R7, 0x4 ; /* 0x000000040007a802 */
/* 0x000fe40000000f00 */
/*00a0*/ @!P1 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004049625 */
/* 0x000fc800078e0005 */
/*00b0*/ @!P2 IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x000058000606a625 */
/* 0x000fe400078e0007 */
/*00c0*/ @!P1 LDG.E R4, [R4.64] ; /* 0x0000000404049981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000040606a981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x3ff, PT ; /* 0x000003ff0300780c */
/* 0x000fc60003f04070 */
/*00f0*/ @P1 STS [R3.X4], RZ ; /* 0x000000ff03001388 */
/* 0x000fe80000004800 */
/*0100*/ @P2 STS [R3.X4+0x1000], RZ ; /* 0x001000ff03002388 */
/* 0x000fe80000004800 */
/*0110*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x004fe20000004800 */
/*0120*/ ISETP.GT.U32.AND P1, PT, R3, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x000fc60003f24070 */
/*0130*/ @!P2 STS [R3.X4+0x1000], R6 ; /* 0x001000060300a388 */
/* 0x008fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0160*/ @!P0 LDS R9, [R3.X4+0x1000] ; /* 0x0010000003098984 */
/* 0x000e240000004800 */
/*0170*/ @!P0 FADD R2, R2, R9 ; /* 0x0000000902028221 */
/* 0x001fca0000000000 */
/*0180*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fca0003f04070 */
/*01b0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*01c0*/ @!P1 LDS R4, [R3.X4+0x800] ; /* 0x0008000003049984 */
/* 0x000e240000004800 */
/*01d0*/ @!P1 FADD R4, R5, R4 ; /* 0x0000000405049221 */
/* 0x001fca0000000000 */
/*01e0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ ISETP.GT.U32.AND P1, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fca0003f24070 */
/*0210*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0220*/ @!P0 LDS R6, [R3.X4+0x400] ; /* 0x0004000003068984 */
/* 0x000e240000004800 */
/*0230*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0240*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.GT.U32.AND P0, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fca0003f04070 */
/*0270*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0280*/ @!P1 LDS R5, [R3.X4+0x200] ; /* 0x0002000003059984 */
/* 0x000e240000004800 */
/*0290*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*02a0*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f24070 */
/*02d0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*02e0*/ @!P0 LDS R5, [R3.X4+0x100] ; /* 0x0001000003058984 */
/* 0x000e240000004800 */
/*02f0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*0300*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GT.U32.AND P0, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f04070 */
/*0330*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*0340*/ @!P1 LDS R6, [R3.X4+0x80] ; /* 0x0000800003069984 */
/* 0x000e240000004800 */
/*0350*/ @!P1 FADD R6, R5, R6 ; /* 0x0000000605069221 */
/* 0x001fca0000000000 */
/*0360*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x000fe80000004800 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ ISETP.GT.U32.AND P1, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f24070 */
/*0390*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*03a0*/ @!P0 LDS R5, [R3.X4+0x40] ; /* 0x0000400003058984 */
/* 0x000e240000004800 */
/*03b0*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*03c0*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f04070 */
/*03f0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*0400*/ @!P1 LDS R5, [R3.X4+0x20] ; /* 0x0000200003059984 */
/* 0x000e240000004800 */
/*0410*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0420*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0440*/ ISETP.GT.U32.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f24070 */
/*0450*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0460*/ @!P0 LDS R6, [R3.X4+0x10] ; /* 0x0000100003068984 */
/* 0x000e240000004800 */
/*0470*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0480*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04a0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f05270 */
/*04b0*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*04c0*/ @!P1 LDS R5, [R3.X4+0x8] ; /* 0x0000080003059984 */
/* 0x000e240000004800 */
/*04d0*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*04e0*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x0001e80000004800 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0510*/ LDS R2, [0x4] ; /* 0x00000400ff027984 */
/* 0x001fe80000000800 */
/*0520*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000e240000004800 */
/*0530*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x001fc40000000000 */
/*0540*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0550*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x000fe20000004800 */
/*0560*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc600078e0005 */
/*0570*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000e280000000800 */
/*0580*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0590*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9vectorAddPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
//#include <helper_cuda.h>
#include <time.h>
#define BLOCK_SIZE 1024
#define NUMBER_OF_ELEMENTS 1024
__global__ void vectorAdd(const float *A, const float *B, float *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
C[i] = A[i] + B[i];
}
}
__global__ void total(float *input, float *output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float partialSum[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x, start = 2* blockIdx.x * BLOCK_SIZE;
if (start + t < len)
partialSum[t] = input[start + t];
else
partialSum[t] = 0;
if (start + BLOCK_SIZE + t < len)
partialSum[BLOCK_SIZE + t] = input[start + BLOCK_SIZE + t];
else
partialSum[BLOCK_SIZE + t] = 0;
//@@ Traverse the reduction tree
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
partialSum[t] += partialSum[t + stride];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
if (t == 0)
output[blockIdx.x] = partialSum[0];
}
int main(void)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
int numElements = NUMBER_OF_ELEMENTS;
int memorySizeIn=numElements*sizeof(float);
int memorySizeOut=sizeof(float);
printf("Calculating the sum of %d elements.\n", numElements);
printf("Allocating host vectors...\n");
// Allocate the host output vector
float *h_input = (float *)malloc(memorySizeIn);
// Allocate the host output vector
float *h_output = (float *)malloc(memorySizeIn);
// Verify that allocations succeeded
if (h_input == NULL || h_output == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Initialize the host input vector with random values
for (int i = 0; i < numElements; ++i)
{
h_input[i]=(float)rand()/(float)RAND_MAX;
// printf("%f ", h_input[i]);
}
printf("Allocating device vectors... \n");
float *d_input = NULL;
err = cudaMallocManaged((void **)&d_input, memorySizeIn);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device input vector!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device input vector allocated.\n");
float *d_output = NULL;
err = cudaMallocManaged((void **)&d_output, memorySizeIn);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device output vector!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device output vector allocated.\n");
printf("Copying input vector from the host memory to the CUDA device...\n");
err = cudaMemcpy(d_input, h_input, memorySizeIn, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy input vector from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Launch the Kernel
int threadsPerBlock = BLOCK_SIZE;
int blocksPerGrid = (numElements + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launching with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
float sumGPU = 0;
int k = 0;
int iter=0;
clock_t start=clock();
int inputElementsLeft = numElements;
while(inputElementsLeft > 0)
{
int currNumElements = inputElementsLeft;
if(inputElementsLeft > BLOCK_SIZE*2)
currNumElements = BLOCK_SIZE*2;
total<<<blocksPerGrid, threadsPerBlock>>>(d_input + k, d_output, currNumElements);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch the kernel in %d iteration (error code %s)!\n", iter, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = cudaMemcpy(h_output, d_output, memorySizeOut, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy output vector from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum = h_output[0];
sumGPU+=sum;
k+=currNumElements;
iter+=1;
inputElementsLeft-=currNumElements;
}
cudaDeviceSynchronize();
clock_t end=clock();
double time_elapsed_gpu=((double) (end - start))*1000 / CLOCKS_PER_SEC;
// Calculating the sum using CPU
float sumCPU=0;
for (int i=0; i<numElements; i++) {
sumCPU+=h_input[i];
}
printf("GPU sum is %f and CPU sum is %f.\n", sumGPU, sumCPU);
printf("Time elapsed for GPU computations: %lf ms.\n", time_elapsed_gpu);
// Free device memory
err = cudaFree(d_input);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free input vector (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_output);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free output vector (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
free(h_input);
free(h_output);
return 0;
} | .file "tmpxft_0012dc6b_00000000-6_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
.type _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi, @function
_Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi, .-_Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
.globl _Z9vectorAddPKfS0_Pfi
.type _Z9vectorAddPKfS0_Pfi, @function
_Z9vectorAddPKfS0_Pfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9vectorAddPKfS0_Pfi, .-_Z9vectorAddPKfS0_Pfi
.globl _Z27__device_stub__Z5totalPfS_iPfS_i
.type _Z27__device_stub__Z5totalPfS_iPfS_i, @function
_Z27__device_stub__Z5totalPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5totalPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z5totalPfS_iPfS_i, .-_Z27__device_stub__Z5totalPfS_iPfS_i
.globl _Z5totalPfS_i
.type _Z5totalPfS_i, @function
_Z5totalPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5totalPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5totalPfS_i, .-_Z5totalPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Calculating the sum of %d elements.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Allocating host vectors...\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Failed to allocate host vectors!\n"
.section .rodata.str1.1
.LC4:
.string "Success.\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Allocating device vectors... \n"
.align 8
.LC7:
.string "Failed to allocate device input vector!\n"
.align 8
.LC8:
.string "Device input vector allocated.\n"
.align 8
.LC9:
.string "Failed to allocate device output vector!\n"
.align 8
.LC10:
.string "Device output vector allocated.\n"
.align 8
.LC11:
.string "Copying input vector from the host memory to the CUDA device...\n"
.align 8
.LC12:
.string "Failed to copy input vector from host to device (error code %s)!\n"
.align 8
.LC13:
.string "CUDA kernel launching with %d blocks of %d threads\n"
.align 8
.LC14:
.string "Failed to launch the kernel in %d iteration (error code %s)!\n"
.align 8
.LC15:
.string "Failed to copy output vector from device to host (error code %s)!\n"
.align 8
.LC16:
.string "GPU sum is %f and CPU sum is %f.\n"
.align 8
.LC19:
.string "Time elapsed for GPU computations: %lf ms.\n"
.align 8
.LC20:
.string "Failed to free input vector (error code %s)!\n"
.align 8
.LC21:
.string "Failed to free output vector (error code %s)!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1024, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, %r15
movl $4096, %edi
call malloc@PLT
testq %r15, %r15
je .L33
movq %rax, %r13
testq %rax, %rax
je .L33
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rbx
leaq 4096(%r15), %rbp
movq %r15, %r12
.L22:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC5(%rip), %xmm0
movss %xmm0, (%r12)
addq $4, %r12
cmpq %r12, %rbp
jne .L22
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4096, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L37
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4096, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L38
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %ecx
movl $1, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, 8(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movl $1024, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z5totalPfS_iPfS_i
.L26:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L40
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L41
movl 0(%r13), %r14d
call cudaDeviceSynchronize@PLT
call clock@PLT
movq %rax, %r12
pxor %xmm1, %xmm1
.L29:
addss (%rbx), %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
pxor %xmm0, %xmm0
movd %r14d, %xmm2
addss %xmm0, %xmm2
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %rax, %r12
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
mulsd .LC17(%rip), %xmm0
divsd .LC18(%rip), %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L42
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L43
movq %r15, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $0, %ecx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC22:
.string "_Z5totalPfS_i"
.LC23:
.string "_Z9vectorAddPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z5totalPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPKfS0_Pfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC17:
.long 0
.long 1083129856
.align 8
.LC18:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <cuda_runtime.h>
//#include <helper_cuda.h>
#include <time.h>
#define BLOCK_SIZE 1024
#define NUMBER_OF_ELEMENTS 1024
__global__ void vectorAdd(const float *A, const float *B, float *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
C[i] = A[i] + B[i];
}
}
__global__ void total(float *input, float *output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float partialSum[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x, start = 2* blockIdx.x * BLOCK_SIZE;
if (start + t < len)
partialSum[t] = input[start + t];
else
partialSum[t] = 0;
if (start + BLOCK_SIZE + t < len)
partialSum[BLOCK_SIZE + t] = input[start + BLOCK_SIZE + t];
else
partialSum[BLOCK_SIZE + t] = 0;
//@@ Traverse the reduction tree
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
partialSum[t] += partialSum[t + stride];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
if (t == 0)
output[blockIdx.x] = partialSum[0];
}
int main(void)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
int numElements = NUMBER_OF_ELEMENTS;
int memorySizeIn=numElements*sizeof(float);
int memorySizeOut=sizeof(float);
printf("Calculating the sum of %d elements.\n", numElements);
printf("Allocating host vectors...\n");
// Allocate the host output vector
float *h_input = (float *)malloc(memorySizeIn);
// Allocate the host output vector
float *h_output = (float *)malloc(memorySizeIn);
// Verify that allocations succeeded
if (h_input == NULL || h_output == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Initialize the host input vector with random values
for (int i = 0; i < numElements; ++i)
{
h_input[i]=(float)rand()/(float)RAND_MAX;
// printf("%f ", h_input[i]);
}
printf("Allocating device vectors... \n");
float *d_input = NULL;
err = cudaMallocManaged((void **)&d_input, memorySizeIn);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device input vector!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device input vector allocated.\n");
float *d_output = NULL;
err = cudaMallocManaged((void **)&d_output, memorySizeIn);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device output vector!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device output vector allocated.\n");
printf("Copying input vector from the host memory to the CUDA device...\n");
err = cudaMemcpy(d_input, h_input, memorySizeIn, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy input vector from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Launch the Kernel
int threadsPerBlock = BLOCK_SIZE;
int blocksPerGrid = (numElements + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launching with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
float sumGPU = 0;
int k = 0;
int iter=0;
clock_t start=clock();
int inputElementsLeft = numElements;
while(inputElementsLeft > 0)
{
int currNumElements = inputElementsLeft;
if(inputElementsLeft > BLOCK_SIZE*2)
currNumElements = BLOCK_SIZE*2;
total<<<blocksPerGrid, threadsPerBlock>>>(d_input + k, d_output, currNumElements);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch the kernel in %d iteration (error code %s)!\n", iter, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = cudaMemcpy(h_output, d_output, memorySizeOut, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy output vector from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum = h_output[0];
sumGPU+=sum;
k+=currNumElements;
iter+=1;
inputElementsLeft-=currNumElements;
}
cudaDeviceSynchronize();
clock_t end=clock();
double time_elapsed_gpu=((double) (end - start))*1000 / CLOCKS_PER_SEC;
// Calculating the sum using CPU
float sumCPU=0;
for (int i=0; i<numElements; i++) {
sumCPU+=h_input[i];
}
printf("GPU sum is %f and CPU sum is %f.\n", sumGPU, sumCPU);
printf("Time elapsed for GPU computations: %lf ms.\n", time_elapsed_gpu);
// Free device memory
err = cudaFree(d_input);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free input vector (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_output);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free output vector (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
free(h_input);
free(h_output);
return 0;
} | #include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
//#include <helper_cuda.h>
#include <time.h>
#define BLOCK_SIZE 1024
#define NUMBER_OF_ELEMENTS 1024
__global__ void vectorAdd(const float *A, const float *B, float *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
C[i] = A[i] + B[i];
}
}
__global__ void total(float *input, float *output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float partialSum[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x, start = 2* blockIdx.x * BLOCK_SIZE;
if (start + t < len)
partialSum[t] = input[start + t];
else
partialSum[t] = 0;
if (start + BLOCK_SIZE + t < len)
partialSum[BLOCK_SIZE + t] = input[start + BLOCK_SIZE + t];
else
partialSum[BLOCK_SIZE + t] = 0;
//@@ Traverse the reduction tree
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
partialSum[t] += partialSum[t + stride];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
if (t == 0)
output[blockIdx.x] = partialSum[0];
}
int main(void)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
int numElements = NUMBER_OF_ELEMENTS;
int memorySizeIn=numElements*sizeof(float);
int memorySizeOut=sizeof(float);
printf("Calculating the sum of %d elements.\n", numElements);
printf("Allocating host vectors...\n");
// Allocate the host output vector
float *h_input = (float *)malloc(memorySizeIn);
// Allocate the host output vector
float *h_output = (float *)malloc(memorySizeIn);
// Verify that allocations succeeded
if (h_input == NULL || h_output == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Initialize the host input vector with random values
for (int i = 0; i < numElements; ++i)
{
h_input[i]=(float)rand()/(float)RAND_MAX;
// printf("%f ", h_input[i]);
}
printf("Allocating device vectors... \n");
float *d_input = NULL;
err = hipMallocManaged((void **)&d_input, memorySizeIn);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device input vector!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device input vector allocated.\n");
float *d_output = NULL;
err = hipMallocManaged((void **)&d_output, memorySizeIn);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device output vector!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device output vector allocated.\n");
printf("Copying input vector from the host memory to the CUDA device...\n");
err = hipMemcpy(d_input, h_input, memorySizeIn, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy input vector from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Launch the Kernel
int threadsPerBlock = BLOCK_SIZE;
int blocksPerGrid = (numElements + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launching with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
float sumGPU = 0;
int k = 0;
int iter=0;
clock_t start=clock();
int inputElementsLeft = numElements;
while(inputElementsLeft > 0)
{
int currNumElements = inputElementsLeft;
if(inputElementsLeft > BLOCK_SIZE*2)
currNumElements = BLOCK_SIZE*2;
total<<<blocksPerGrid, threadsPerBlock>>>(d_input + k, d_output, currNumElements);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch the kernel in %d iteration (error code %s)!\n", iter, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = hipMemcpy(h_output, d_output, memorySizeOut, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy output vector from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum = h_output[0];
sumGPU+=sum;
k+=currNumElements;
iter+=1;
inputElementsLeft-=currNumElements;
}
hipDeviceSynchronize();
clock_t end=clock();
double time_elapsed_gpu=((double) (end - start))*1000 / CLOCKS_PER_SEC;
// Calculating the sum using CPU
float sumCPU=0;
for (int i=0; i<numElements; i++) {
sumCPU+=h_input[i];
}
printf("GPU sum is %f and CPU sum is %f.\n", sumGPU, sumCPU);
printf("Time elapsed for GPU computations: %lf ms.\n", time_elapsed_gpu);
// Free device memory
err = hipFree(d_input);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free input vector (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free output vector (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
free(h_input);
free(h_output);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
//#include <helper_cuda.h>
#include <time.h>
#define BLOCK_SIZE 1024
#define NUMBER_OF_ELEMENTS 1024
__global__ void vectorAdd(const float *A, const float *B, float *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
C[i] = A[i] + B[i];
}
}
__global__ void total(float *input, float *output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float partialSum[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x, start = 2* blockIdx.x * BLOCK_SIZE;
if (start + t < len)
partialSum[t] = input[start + t];
else
partialSum[t] = 0;
if (start + BLOCK_SIZE + t < len)
partialSum[BLOCK_SIZE + t] = input[start + BLOCK_SIZE + t];
else
partialSum[BLOCK_SIZE + t] = 0;
//@@ Traverse the reduction tree
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
partialSum[t] += partialSum[t + stride];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
if (t == 0)
output[blockIdx.x] = partialSum[0];
}
int main(void)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
int numElements = NUMBER_OF_ELEMENTS;
int memorySizeIn=numElements*sizeof(float);
int memorySizeOut=sizeof(float);
printf("Calculating the sum of %d elements.\n", numElements);
printf("Allocating host vectors...\n");
// Allocate the host output vector
float *h_input = (float *)malloc(memorySizeIn);
// Allocate the host output vector
float *h_output = (float *)malloc(memorySizeIn);
// Verify that allocations succeeded
if (h_input == NULL || h_output == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Initialize the host input vector with random values
for (int i = 0; i < numElements; ++i)
{
h_input[i]=(float)rand()/(float)RAND_MAX;
// printf("%f ", h_input[i]);
}
printf("Allocating device vectors... \n");
float *d_input = NULL;
err = hipMallocManaged((void **)&d_input, memorySizeIn);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device input vector!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device input vector allocated.\n");
float *d_output = NULL;
err = hipMallocManaged((void **)&d_output, memorySizeIn);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device output vector!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device output vector allocated.\n");
printf("Copying input vector from the host memory to the CUDA device...\n");
err = hipMemcpy(d_input, h_input, memorySizeIn, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy input vector from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Launch the Kernel
int threadsPerBlock = BLOCK_SIZE;
int blocksPerGrid = (numElements + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launching with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
float sumGPU = 0;
int k = 0;
int iter=0;
clock_t start=clock();
int inputElementsLeft = numElements;
while(inputElementsLeft > 0)
{
int currNumElements = inputElementsLeft;
if(inputElementsLeft > BLOCK_SIZE*2)
currNumElements = BLOCK_SIZE*2;
total<<<blocksPerGrid, threadsPerBlock>>>(d_input + k, d_output, currNumElements);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch the kernel in %d iteration (error code %s)!\n", iter, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = hipMemcpy(h_output, d_output, memorySizeOut, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy output vector from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum = h_output[0];
sumGPU+=sum;
k+=currNumElements;
iter+=1;
inputElementsLeft-=currNumElements;
}
hipDeviceSynchronize();
clock_t end=clock();
double time_elapsed_gpu=((double) (end - start))*1000 / CLOCKS_PER_SEC;
// Calculating the sum using CPU
float sumCPU=0;
for (int i=0; i<numElements; i++) {
sumCPU+=h_input[i];
}
printf("GPU sum is %f and CPU sum is %f.\n", sumGPU, sumCPU);
printf("Time elapsed for GPU computations: %lf ms.\n", time_elapsed_gpu);
// Free device memory
err = hipFree(d_input);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free input vector (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free output vector (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
free(h_input);
free(h_output);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPKfS0_Pfi
.globl _Z9vectorAddPKfS0_Pfi
.p2align 8
.type _Z9vectorAddPKfS0_Pfi,@function
_Z9vectorAddPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPKfS0_Pfi, .Lfunc_end0-_Z9vectorAddPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5totalPfS_i
.globl _Z5totalPfS_i
.p2align 8
.type _Z5totalPfS_i,@function
_Z5totalPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
v_mov_b32_e32 v4, 0
v_lshl_or_b32 v1, s2, 11, v0
v_mov_b32_e32 v2, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
v_or_b32_e32 v1, 0x400, v1
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_movk_i32 s3, 0x400
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB1_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v4, v[1:2], off
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4 offset:4096
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB1_8
.LBB1_6:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_5
v_add_lshl_u32 v1, s3, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB1_5
.LBB1_8:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_10
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5totalPfS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5totalPfS_i, .Lfunc_end1-_Z5totalPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5totalPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5totalPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
// For the CUDA runtime routines (prefixed with "cuda_")
#include <hip/hip_runtime.h>
//#include <helper_cuda.h>
#include <time.h>
#define BLOCK_SIZE 1024
#define NUMBER_OF_ELEMENTS 1024
__global__ void vectorAdd(const float *A, const float *B, float *C, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements)
{
C[i] = A[i] + B[i];
}
}
__global__ void total(float *input, float *output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float partialSum[2 * BLOCK_SIZE];
unsigned int t = threadIdx.x, start = 2* blockIdx.x * BLOCK_SIZE;
if (start + t < len)
partialSum[t] = input[start + t];
else
partialSum[t] = 0;
if (start + BLOCK_SIZE + t < len)
partialSum[BLOCK_SIZE + t] = input[start + BLOCK_SIZE + t];
else
partialSum[BLOCK_SIZE + t] = 0;
//@@ Traverse the reduction tree
for (unsigned int stride = BLOCK_SIZE; stride >= 1; stride >>= 1) {
__syncthreads();
if (t < stride)
partialSum[t] += partialSum[t + stride];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
if (t == 0)
output[blockIdx.x] = partialSum[0];
}
int main(void)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
int numElements = NUMBER_OF_ELEMENTS;
int memorySizeIn=numElements*sizeof(float);
int memorySizeOut=sizeof(float);
printf("Calculating the sum of %d elements.\n", numElements);
printf("Allocating host vectors...\n");
// Allocate the host output vector
float *h_input = (float *)malloc(memorySizeIn);
// Allocate the host output vector
float *h_output = (float *)malloc(memorySizeIn);
// Verify that allocations succeeded
if (h_input == NULL || h_output == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Initialize the host input vector with random values
for (int i = 0; i < numElements; ++i)
{
h_input[i]=(float)rand()/(float)RAND_MAX;
// printf("%f ", h_input[i]);
}
printf("Allocating device vectors... \n");
float *d_input = NULL;
err = hipMallocManaged((void **)&d_input, memorySizeIn);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device input vector!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device input vector allocated.\n");
float *d_output = NULL;
err = hipMallocManaged((void **)&d_output, memorySizeIn);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device output vector!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Device output vector allocated.\n");
printf("Copying input vector from the host memory to the CUDA device...\n");
err = hipMemcpy(d_input, h_input, memorySizeIn, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy input vector from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
else
printf("Success.\n");
// Launch the Kernel
int threadsPerBlock = BLOCK_SIZE;
int blocksPerGrid = (numElements + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launching with %d blocks of %d threads\n", blocksPerGrid, threadsPerBlock);
float sumGPU = 0;
int k = 0;
int iter=0;
clock_t start=clock();
int inputElementsLeft = numElements;
while(inputElementsLeft > 0)
{
int currNumElements = inputElementsLeft;
if(inputElementsLeft > BLOCK_SIZE*2)
currNumElements = BLOCK_SIZE*2;
total<<<blocksPerGrid, threadsPerBlock>>>(d_input + k, d_output, currNumElements);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch the kernel in %d iteration (error code %s)!\n", iter, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copy the device result vector in device memory to the host result vector
// in host memory.
err = hipMemcpy(h_output, d_output, memorySizeOut, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy output vector from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum = h_output[0];
sumGPU+=sum;
k+=currNumElements;
iter+=1;
inputElementsLeft-=currNumElements;
}
hipDeviceSynchronize();
clock_t end=clock();
double time_elapsed_gpu=((double) (end - start))*1000 / CLOCKS_PER_SEC;
// Calculating the sum using CPU
float sumCPU=0;
for (int i=0; i<numElements; i++) {
sumCPU+=h_input[i];
}
printf("GPU sum is %f and CPU sum is %f.\n", sumGPU, sumCPU);
printf("Time elapsed for GPU computations: %lf ms.\n", time_elapsed_gpu);
// Free device memory
err = hipFree(d_input);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free input vector (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free output vector (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Free host memory
free(h_input);
free(h_output);
return 0;
} | .text
.file "reduction.hip"
.globl _Z24__device_stub__vectorAddPKfS0_Pfi # -- Begin function _Z24__device_stub__vectorAddPKfS0_Pfi
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPKfS0_Pfi,@function
_Z24__device_stub__vectorAddPKfS0_Pfi: # @_Z24__device_stub__vectorAddPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPKfS0_Pfi, .Lfunc_end0-_Z24__device_stub__vectorAddPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__totalPfS_i # -- Begin function _Z20__device_stub__totalPfS_i
.p2align 4, 0x90
.type _Z20__device_stub__totalPfS_i,@function
_Z20__device_stub__totalPfS_i: # @_Z20__device_stub__totalPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5totalPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__totalPfS_i, .Lfunc_end1-_Z20__device_stub__totalPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x408f400000000000 # double 1000
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
testq %rbx, %rbx
je .LBB2_23
# %bb.1:
movq %rax, %r14
testq %rax, %rax
je .LBB2_23
# %bb.2:
movl $.Lstr.6, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_3
# %bb.4:
movl $.Lstr.2, %edi
callq puts@PLT
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_5
# %bb.7:
movl $.Lstr.3, %edi
callq puts@PLT
movq $0, (%rsp)
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_8
# %bb.9:
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_10
# %bb.11:
movl $.Lstr.6, %edi
callq puts@PLT
movl $.L.str.11, %edi
movl $1, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
callq clock
movq %rax, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1024, 28(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5totalPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.14:
movq (%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_15
# %bb.16:
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp) # 4-byte Spill
callq hipDeviceSynchronize
callq clock
subq %r15, %rax
cvtsi2sd %rax, %xmm2
mulsd .LCPI2_1(%rip), %xmm2
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_17: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm1
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_17
# %bb.18:
xorps %xmm0, %xmm0
movss 16(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
divsd .LCPI2_2(%rip), %xmm2
movsd %xmm2, 16(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.14, %edi
movb $2, %al
callq printf
movl $.L.str.15, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_19
# %bb.20:
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_21
# %bb.22:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_23:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_5:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB2_6
.LBB2_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB2_6
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB2_6
.LBB2_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movq %rbx, %rdi
xorl %edx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB2_6
.LBB2_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
jmp .LBB2_6
.LBB2_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.17, %esi
.LBB2_6:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5totalPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPKfS0_Pfi,@object # @_Z9vectorAddPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z9vectorAddPKfS0_Pfi
.p2align 3, 0x0
_Z9vectorAddPKfS0_Pfi:
.quad _Z24__device_stub__vectorAddPKfS0_Pfi
.size _Z9vectorAddPKfS0_Pfi, 8
.type _Z5totalPfS_i,@object # @_Z5totalPfS_i
.globl _Z5totalPfS_i
.p2align 3, 0x0
_Z5totalPfS_i:
.quad _Z20__device_stub__totalPfS_i
.size _Z5totalPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Calculating the sum of %d elements.\n"
.size .L.str, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.2, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device input vector!\n"
.size .L.str.5, 41
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device output vector!\n"
.size .L.str.7, 42
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to copy input vector from host to device (error code %s)!\n"
.size .L.str.10, 66
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "CUDA kernel launching with %d blocks of %d threads\n"
.size .L.str.11, 52
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to launch the kernel in %d iteration (error code %s)!\n"
.size .L.str.12, 62
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to copy output vector from device to host (error code %s)!\n"
.size .L.str.13, 67
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "GPU sum is %f and CPU sum is %f.\n"
.size .L.str.14, 34
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Time elapsed for GPU computations: %lf ms.\n"
.size .L.str.15, 44
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Failed to free input vector (error code %s)!\n"
.size .L.str.16, 46
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Failed to free output vector (error code %s)!\n"
.size .L.str.17, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vectorAddPKfS0_Pfi"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5totalPfS_i"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Allocating host vectors..."
.size .Lstr, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Allocating device vectors... "
.size .Lstr.2, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Device input vector allocated."
.size .Lstr.3, 31
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Device output vector allocated."
.size .Lstr.4, 32
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Copying input vector from the host memory to the CUDA device..."
.size .Lstr.5, 64
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Success."
.size .Lstr.6, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPKfS0_Pfi
.addrsig_sym _Z20__device_stub__totalPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPKfS0_Pfi
.addrsig_sym _Z5totalPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5totalPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ LEA R4, R0, R3, 0xb ; /* 0x0000000300047211 */
/* 0x001fc800078e58ff */
/*0050*/ IADD3 R6, R4.reuse, 0x400, RZ ; /* 0x0000040004067810 */
/* 0x040fe40007ffe0ff */
/*0060*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f26070 */
/*0070*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fd60003f46070 */
/*0080*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff059424 */
/* 0x000fe400078e00ff */
/*0090*/ @!P2 MOV R7, 0x4 ; /* 0x000000040007a802 */
/* 0x000fe40000000f00 */
/*00a0*/ @!P1 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004049625 */
/* 0x000fc800078e0005 */
/*00b0*/ @!P2 IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x000058000606a625 */
/* 0x000fe400078e0007 */
/*00c0*/ @!P1 LDG.E R4, [R4.64] ; /* 0x0000000404049981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000040606a981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x3ff, PT ; /* 0x000003ff0300780c */
/* 0x000fc60003f04070 */
/*00f0*/ @P1 STS [R3.X4], RZ ; /* 0x000000ff03001388 */
/* 0x000fe80000004800 */
/*0100*/ @P2 STS [R3.X4+0x1000], RZ ; /* 0x001000ff03002388 */
/* 0x000fe80000004800 */
/*0110*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x004fe20000004800 */
/*0120*/ ISETP.GT.U32.AND P1, PT, R3, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x000fc60003f24070 */
/*0130*/ @!P2 STS [R3.X4+0x1000], R6 ; /* 0x001000060300a388 */
/* 0x008fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0160*/ @!P0 LDS R9, [R3.X4+0x1000] ; /* 0x0010000003098984 */
/* 0x000e240000004800 */
/*0170*/ @!P0 FADD R2, R2, R9 ; /* 0x0000000902028221 */
/* 0x001fca0000000000 */
/*0180*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fca0003f04070 */
/*01b0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*01c0*/ @!P1 LDS R4, [R3.X4+0x800] ; /* 0x0008000003049984 */
/* 0x000e240000004800 */
/*01d0*/ @!P1 FADD R4, R5, R4 ; /* 0x0000000405049221 */
/* 0x001fca0000000000 */
/*01e0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ ISETP.GT.U32.AND P1, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fca0003f24070 */
/*0210*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0220*/ @!P0 LDS R6, [R3.X4+0x400] ; /* 0x0004000003068984 */
/* 0x000e240000004800 */
/*0230*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0240*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.GT.U32.AND P0, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fca0003f04070 */
/*0270*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0280*/ @!P1 LDS R5, [R3.X4+0x200] ; /* 0x0002000003059984 */
/* 0x000e240000004800 */
/*0290*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*02a0*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f24070 */
/*02d0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*02e0*/ @!P0 LDS R5, [R3.X4+0x100] ; /* 0x0001000003058984 */
/* 0x000e240000004800 */
/*02f0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*0300*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GT.U32.AND P0, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f04070 */
/*0330*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*0340*/ @!P1 LDS R6, [R3.X4+0x80] ; /* 0x0000800003069984 */
/* 0x000e240000004800 */
/*0350*/ @!P1 FADD R6, R5, R6 ; /* 0x0000000605069221 */
/* 0x001fca0000000000 */
/*0360*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x000fe80000004800 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ ISETP.GT.U32.AND P1, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f24070 */
/*0390*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*03a0*/ @!P0 LDS R5, [R3.X4+0x40] ; /* 0x0000400003058984 */
/* 0x000e240000004800 */
/*03b0*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*03c0*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f04070 */
/*03f0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*0400*/ @!P1 LDS R5, [R3.X4+0x20] ; /* 0x0000200003059984 */
/* 0x000e240000004800 */
/*0410*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0420*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0440*/ ISETP.GT.U32.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f24070 */
/*0450*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0460*/ @!P0 LDS R6, [R3.X4+0x10] ; /* 0x0000100003068984 */
/* 0x000e240000004800 */
/*0470*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0480*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04a0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f05270 */
/*04b0*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*04c0*/ @!P1 LDS R5, [R3.X4+0x8] ; /* 0x0000080003059984 */
/* 0x000e240000004800 */
/*04d0*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*04e0*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x0001e80000004800 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0510*/ LDS R2, [0x4] ; /* 0x00000400ff027984 */
/* 0x001fe80000000800 */
/*0520*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000e240000004800 */
/*0530*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x001fc40000000000 */
/*0540*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0550*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x000fe20000004800 */
/*0560*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc600078e0005 */
/*0570*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000e280000000800 */
/*0580*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0590*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9vectorAddPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPKfS0_Pfi
.globl _Z9vectorAddPKfS0_Pfi
.p2align 8
.type _Z9vectorAddPKfS0_Pfi,@function
_Z9vectorAddPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPKfS0_Pfi, .Lfunc_end0-_Z9vectorAddPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5totalPfS_i
.globl _Z5totalPfS_i
.p2align 8
.type _Z5totalPfS_i,@function
_Z5totalPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
v_mov_b32_e32 v4, 0
v_lshl_or_b32 v1, s2, 11, v0
v_mov_b32_e32 v2, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
v_or_b32_e32 v1, 0x400, v1
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_movk_i32 s3, 0x400
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB1_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v4, v[1:2], off
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4 offset:4096
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB1_8
.LBB1_6:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB1_5
v_add_lshl_u32 v1, s3, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_branch .LBB1_5
.LBB1_8:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_10
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5totalPfS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5totalPfS_i, .Lfunc_end1-_Z5totalPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5totalPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5totalPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012dc6b_00000000-6_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
.type _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi, @function
_Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi, .-_Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
.globl _Z9vectorAddPKfS0_Pfi
.type _Z9vectorAddPKfS0_Pfi, @function
_Z9vectorAddPKfS0_Pfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9vectorAddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9vectorAddPKfS0_Pfi, .-_Z9vectorAddPKfS0_Pfi
.globl _Z27__device_stub__Z5totalPfS_iPfS_i
.type _Z27__device_stub__Z5totalPfS_iPfS_i, @function
_Z27__device_stub__Z5totalPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5totalPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z5totalPfS_iPfS_i, .-_Z27__device_stub__Z5totalPfS_iPfS_i
.globl _Z5totalPfS_i
.type _Z5totalPfS_i, @function
_Z5totalPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5totalPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5totalPfS_i, .-_Z5totalPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Calculating the sum of %d elements.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Allocating host vectors...\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Failed to allocate host vectors!\n"
.section .rodata.str1.1
.LC4:
.string "Success.\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Allocating device vectors... \n"
.align 8
.LC7:
.string "Failed to allocate device input vector!\n"
.align 8
.LC8:
.string "Device input vector allocated.\n"
.align 8
.LC9:
.string "Failed to allocate device output vector!\n"
.align 8
.LC10:
.string "Device output vector allocated.\n"
.align 8
.LC11:
.string "Copying input vector from the host memory to the CUDA device...\n"
.align 8
.LC12:
.string "Failed to copy input vector from host to device (error code %s)!\n"
.align 8
.LC13:
.string "CUDA kernel launching with %d blocks of %d threads\n"
.align 8
.LC14:
.string "Failed to launch the kernel in %d iteration (error code %s)!\n"
.align 8
.LC15:
.string "Failed to copy output vector from device to host (error code %s)!\n"
.align 8
.LC16:
.string "GPU sum is %f and CPU sum is %f.\n"
.align 8
.LC19:
.string "Time elapsed for GPU computations: %lf ms.\n"
.align 8
.LC20:
.string "Failed to free input vector (error code %s)!\n"
.align 8
.LC21:
.string "Failed to free output vector (error code %s)!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1024, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4096, %edi
call malloc@PLT
movq %rax, %r15
movl $4096, %edi
call malloc@PLT
testq %r15, %r15
je .L33
movq %rax, %r13
testq %rax, %rax
je .L33
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rbx
leaq 4096(%r15), %rbp
movq %r15, %r12
.L22:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC5(%rip), %xmm0
movss %xmm0, (%r12)
addq $4, %r12
cmpq %r12, %rbp
jne .L22
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4096, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L37
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4096, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L38
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %ecx
movl $1, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, 8(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movl $1024, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z5totalPfS_iPfS_i
.L26:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L40
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L41
movl 0(%r13), %r14d
call cudaDeviceSynchronize@PLT
call clock@PLT
movq %rax, %r12
pxor %xmm1, %xmm1
.L29:
addss (%rbx), %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
pxor %xmm0, %xmm0
movd %r14d, %xmm2
addss %xmm0, %xmm2
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %rax, %r12
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
mulsd .LC17(%rip), %xmm0
divsd .LC18(%rip), %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L42
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L43
movq %r15, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $0, %ecx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC22:
.string "_Z5totalPfS_i"
.LC23:
.string "_Z9vectorAddPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z5totalPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPKfS0_Pfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC17:
.long 0
.long 1083129856
.align 8
.LC18:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction.hip"
.globl _Z24__device_stub__vectorAddPKfS0_Pfi # -- Begin function _Z24__device_stub__vectorAddPKfS0_Pfi
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPKfS0_Pfi,@function
_Z24__device_stub__vectorAddPKfS0_Pfi: # @_Z24__device_stub__vectorAddPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPKfS0_Pfi, .Lfunc_end0-_Z24__device_stub__vectorAddPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__totalPfS_i # -- Begin function _Z20__device_stub__totalPfS_i
.p2align 4, 0x90
.type _Z20__device_stub__totalPfS_i,@function
_Z20__device_stub__totalPfS_i: # @_Z20__device_stub__totalPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5totalPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__totalPfS_i, .Lfunc_end1-_Z20__device_stub__totalPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x408f400000000000 # double 1000
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
testq %rbx, %rbx
je .LBB2_23
# %bb.1:
movq %rax, %r14
testq %rax, %rax
je .LBB2_23
# %bb.2:
movl $.Lstr.6, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_3
# %bb.4:
movl $.Lstr.2, %edi
callq puts@PLT
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_5
# %bb.7:
movl $.Lstr.3, %edi
callq puts@PLT
movq $0, (%rsp)
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_8
# %bb.9:
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_10
# %bb.11:
movl $.Lstr.6, %edi
callq puts@PLT
movl $.L.str.11, %edi
movl $1, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
callq clock
movq %rax, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1024, 28(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5totalPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.14:
movq (%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_15
# %bb.16:
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp) # 4-byte Spill
callq hipDeviceSynchronize
callq clock
subq %r15, %rax
cvtsi2sd %rax, %xmm2
mulsd .LCPI2_1(%rip), %xmm2
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_17: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm1
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_17
# %bb.18:
xorps %xmm0, %xmm0
movss 16(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
divsd .LCPI2_2(%rip), %xmm2
movsd %xmm2, 16(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.14, %edi
movb $2, %al
callq printf
movl $.L.str.15, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_19
# %bb.20:
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_21
# %bb.22:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_23:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB2_5:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB2_6
.LBB2_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB2_6
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB2_6
.LBB2_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movq %rbx, %rdi
xorl %edx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB2_6
.LBB2_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
jmp .LBB2_6
.LBB2_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.17, %esi
.LBB2_6:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5totalPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPKfS0_Pfi,@object # @_Z9vectorAddPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z9vectorAddPKfS0_Pfi
.p2align 3, 0x0
_Z9vectorAddPKfS0_Pfi:
.quad _Z24__device_stub__vectorAddPKfS0_Pfi
.size _Z9vectorAddPKfS0_Pfi, 8
.type _Z5totalPfS_i,@object # @_Z5totalPfS_i
.globl _Z5totalPfS_i
.p2align 3, 0x0
_Z5totalPfS_i:
.quad _Z20__device_stub__totalPfS_i
.size _Z5totalPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Calculating the sum of %d elements.\n"
.size .L.str, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.2, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device input vector!\n"
.size .L.str.5, 41
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device output vector!\n"
.size .L.str.7, 42
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to copy input vector from host to device (error code %s)!\n"
.size .L.str.10, 66
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "CUDA kernel launching with %d blocks of %d threads\n"
.size .L.str.11, 52
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to launch the kernel in %d iteration (error code %s)!\n"
.size .L.str.12, 62
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to copy output vector from device to host (error code %s)!\n"
.size .L.str.13, 67
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "GPU sum is %f and CPU sum is %f.\n"
.size .L.str.14, 34
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Time elapsed for GPU computations: %lf ms.\n"
.size .L.str.15, 44
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Failed to free input vector (error code %s)!\n"
.size .L.str.16, 46
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Failed to free output vector (error code %s)!\n"
.size .L.str.17, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vectorAddPKfS0_Pfi"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5totalPfS_i"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Allocating host vectors..."
.size .Lstr, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Allocating device vectors... "
.size .Lstr.2, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Device input vector allocated."
.size .Lstr.3, 31
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Device output vector allocated."
.size .Lstr.4, 32
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Copying input vector from the host memory to the CUDA device..."
.size .Lstr.5, 64
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Success."
.size .Lstr.6, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPKfS0_Pfi
.addrsig_sym _Z20__device_stub__totalPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPKfS0_Pfi
.addrsig_sym _Z5totalPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void
cuda_xor(char * encrypt, char * key, int numElements, size_t len_key){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements){
encrypt[i] = encrypt[i] ^ key[i % len_key];
}
}
void xor_encrypt(char h_m[], char h_k[], size_t o_m_len) {
cudaError_t err = cudaSuccess;
int numElements_m = (int) o_m_len;
int numElements_k = strlen(h_k);
size_t size_m = numElements_m * sizeof(char);
size_t size_k = numElements_k * sizeof(char);
// Alocacao dos vetores do device
char * d_m = NULL;
err = cudaMalloc((void **)&d_m, size_m);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (mensagem) (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
char * d_k = NULL;
err = cudaMalloc((void **)&d_k, size_k);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (chave) (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Copia do vetor com o texto original do host para o do device
printf("Copiando mensagem do host para o device\n");
err = cudaMemcpy(d_m, h_m, size_m, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao copiar string mensagem do host para o device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copiando chave do host para o device\n");
err = cudaMemcpy(d_k, h_k, size_k, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao copiar string chave do host para o device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Rodando o algoritmo de encriptacao
// O tamanho do bloco eh determinado pela funcao cudaOccupancyMaxPotentialBlockSize
// das ferramentas do CUDA.
// O tamanho maximo do grid eh de 65535
int minGridSize, blockSize, gridSize;
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, cuda_xor, 0, numElements_m);
gridSize = (numElements_m + blockSize - 1) / blockSize;
if (gridSize > 65535) gridSize = 65535;
printf("CUDA kernel executando com %d blocos de %d threads\n", gridSize, blockSize);
cuda_xor<<<gridSize, blockSize>>>(d_m, d_k, numElements_m, numElements_k);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao rodar XOR kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copia o resultado do device para o host
printf("Copiando saida do device para o host\n");
err = cudaMemcpy(h_m, d_m, size_m, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao copiar mensagem do device pro host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Liberando o conteudo do device
err = cudaFree(d_m);
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao liberar mensagem do device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_k);
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao liberar chave do device (error code %s )!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Resetando o device e terminando
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao resetar o device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("\nDone\n");
}
int xor_test(char * file, char * key_file)
{
char * o_message, * key, * message;
int pass = 1, fsize;
FILE *f;
f = fopen(file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
o_message = (char *) malloc (fsize * sizeof (char));
fread(o_message, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da mensagem!\n");
exit(EXIT_FAILURE);
}
f = fopen(key_file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
key = (char *) malloc (fsize * sizeof (char));
fread(key, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da chave!\n");
exit(EXIT_FAILURE);
}
message = (char *) malloc (strlen(o_message) * sizeof (char));
strcpy(message, o_message);
xor_encrypt(message, key, strlen(o_message));
xor_encrypt(message, key, strlen(o_message));
pass = pass && !strcmp(o_message, message);
return(pass);
}
int main(int argc, char ** argv)
{
printf("CUDA XOR tests: %s\n", xor_test(argv[1], argv[2]) ? "SUCCEEDED" : "FAILED");
return(0);
} | code for sm_80
Function : _Z8cuda_xorPcS_im
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1100 */
/*00b0*/ LOP3.LUT R6, R5, c[0x0][0x17c], RZ, 0xfc, !PT ; /* 0x00005f0005067a12 */
/* 0x000fe200078efcff */
/*00c0*/ BSSY B0, 0x250 ; /* 0x0000018000007945 */
/* 0x000fe60003800000 */
/*00d0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*00e0*/ @!P0 BRA 0x120 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R6, 0x110 ; /* 0x0000011000067802 */
/* 0x001fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x2b0 ; /* 0x000001a000007944 */
/* 0x020fea0003c00000 */
/*0110*/ BRA 0x240 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0120*/ I2F.U32.RP R5, c[0x0][0x178] ; /* 0x00005e0000057b06 */
/* 0x001e220000209000 */
/*0130*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fce0003f25070 */
/*0140*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fe20007ffe0ff */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fca00078e00ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a07 */
/*01a0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*01c0*/ IMAD.HI.U32 R7, R7, R4, RZ ; /* 0x0000000407077227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a07 */
/*01e0*/ IMAD R4, R7, c[0x0][0x178], R4 ; /* 0x00005e0007047a24 */
/* 0x000fca00078e0204 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R4, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004040a10 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*0220*/ @P0 IADD3 R4, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004040a10 */
/* 0x000fe40007ffe0ff */
/*0230*/ @!P1 LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff049a12 */
/* 0x000fe400078e33ff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f1e0ff */
/*0260*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005057a10 */
/* 0x000fcc00007fe4ff */
/*0270*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1100 */
/*0280*/ LOP3.LUT R7, R5, R0, RZ, 0x3c, !PT ; /* 0x0000000005077212 */
/* 0x024fca00078e3cff */
/*0290*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ I2F.U64.RP R7, c[0x0][0x178] ; /* 0x00005e0000077b12 */
/* 0x000e300000309000 */
/*02c0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*02d0*/ IADD3 R8, R7, 0x1ffffffe, RZ ; /* 0x1ffffffe07087810 */
/* 0x001fcc0007ffe0ff */
/*02e0*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*02f0*/ IMAD.WIDE.U32 R10, R8, c[0x0][0x178], RZ ; /* 0x00005e00080a7a25 */
/* 0x001fc800078e00ff */
/*0300*/ IMAD R11, R8, c[0x0][0x17c], R11 ; /* 0x00005f00080b7a24 */
/* 0x000fe200078e020b */
/*0310*/ IADD3 R13, P0, RZ, -R10, RZ ; /* 0x8000000aff0d7210 */
/* 0x000fc60007f1e0ff */
/*0320*/ IMAD R11, R9, c[0x0][0x178], R11 ; /* 0x00005e00090b7a24 */
/* 0x000fe400078e020b */
/*0330*/ IMAD.HI.U32 R10, R8, R13, RZ ; /* 0x0000000d080a7227 */
/* 0x000fc800078e00ff */
/*0340*/ IMAD.X R15, RZ, RZ, ~R11, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0e0b */
/*0350*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0008 */
/*0360*/ IMAD R17, R9, R15.reuse, RZ ; /* 0x0000000f09117224 */
/* 0x080fe400078e02ff */
/*0370*/ IMAD.WIDE.U32 R10, P0, R8, R15, R10 ; /* 0x0000000f080a7225 */
/* 0x000fc8000780000a */
/*0380*/ IMAD.HI.U32 R7, R9, R15, RZ ; /* 0x0000000f09077227 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.HI.U32 R10, P1, R9, R13, R10 ; /* 0x0000000d090a7227 */
/* 0x000fe2000782000a */
/*03a0*/ IADD3.X R7, R7, R9, RZ, P0, !PT ; /* 0x0000000907077210 */
/* 0x000fc800007fe4ff */
/*03b0*/ IADD3 R11, P2, R17, R10, RZ ; /* 0x0000000a110b7210 */
/* 0x000fc80007f5e0ff */
/*03c0*/ IADD3.X R7, RZ, RZ, R7, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fe200017e2407 */
/*03d0*/ IMAD.WIDE.U32 R8, R11, c[0x0][0x178], RZ ; /* 0x00005e000b087a25 */
/* 0x000fc800078e00ff */
/*03e0*/ IMAD R10, R11, c[0x0][0x17c], R9 ; /* 0x00005f000b0a7a24 */
/* 0x000fe200078e0209 */
/*03f0*/ IADD3 R9, P0, RZ, -R8, RZ ; /* 0x80000008ff097210 */
/* 0x000fc60007f1e0ff */
/*0400*/ IMAD R8, R7, c[0x0][0x178], R10 ; /* 0x00005e0007087a24 */
/* 0x000fe400078e020a */
/*0410*/ IMAD.HI.U32 R10, R11, R9, RZ ; /* 0x000000090b0a7227 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD.X R8, RZ, RZ, ~R8, P0 ; /* 0x000000ffff087224 */
/* 0x000fc800000e0e08 */
/*0430*/ IMAD.WIDE.U32 R10, P0, R11, R8, R10 ; /* 0x000000080b0a7225 */
/* 0x000fc8000780000a */
/*0440*/ IMAD R12, R7.reuse, R8, RZ ; /* 0x00000008070c7224 */
/* 0x040fe400078e02ff */
/*0450*/ IMAD.HI.U32 R11, P1, R7, R9, R10 ; /* 0x00000009070b7227 */
/* 0x000fc8000782000a */
/*0460*/ IMAD.HI.U32 R8, R7, R8, RZ ; /* 0x0000000807087227 */
/* 0x000fe200078e00ff */
/*0470*/ IADD3 R11, P2, R12, R11, RZ ; /* 0x0000000b0c0b7210 */
/* 0x000fc60007f5e0ff */
/*0480*/ IMAD.X R7, R8, 0x1, R7, P0 ; /* 0x0000000108077824 */
/* 0x000fe400000e0607 */
/*0490*/ IMAD.HI.U32 R8, R11, R4, RZ ; /* 0x000000040b087227 */
/* 0x000fc600078e00ff */
/*04a0*/ IADD3.X R7, RZ, RZ, R7, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fe200017e2407 */
/*04b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc800078e00ff */
/*04c0*/ IMAD.WIDE.U32 R8, R11, R5, R8 ; /* 0x000000050b087225 */
/* 0x000fc800078e0008 */
/*04d0*/ IMAD R11, R7.reuse, R5, RZ ; /* 0x00000005070b7224 */
/* 0x040fe400078e02ff */
/*04e0*/ IMAD.HI.U32 R8, P0, R7, R4, R8 ; /* 0x0000000407087227 */
/* 0x000fc80007800008 */
/*04f0*/ IMAD.HI.U32 R7, R7, R5, RZ ; /* 0x0000000507077227 */
/* 0x000fe200078e00ff */
/*0500*/ IADD3 R11, P1, R11, R8, RZ ; /* 0x000000080b0b7210 */
/* 0x000fc60007f3e0ff */
/*0510*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe400000e0607 */
/*0520*/ IMAD.WIDE.U32 R8, R11, c[0x0][0x178], RZ ; /* 0x00005e000b087a25 */
/* 0x000fc600078e00ff */
/*0530*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0540*/ IMAD R10, R11, c[0x0][0x17c], R9 ; /* 0x00005f000b0a7a24 */
/* 0x000fe200078e0209 */
/*0550*/ IADD3 R4, P1, -R8, R4, RZ ; /* 0x0000000408047210 */
/* 0x000fc60007f3e1ff */
/*0560*/ IMAD R10, R7, c[0x0][0x178], R10 ; /* 0x00005e00070a7a24 */
/* 0x000fe200078e020a */
/*0570*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc60003f06070 */
/*0580*/ IMAD.X R5, R5, 0x1, ~R10, P1 ; /* 0x0000000105057824 */
/* 0x000fe200008e0e0a */
/*0590*/ IADD3 R7, P1, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004077a10 */
/* 0x000fc80007f3e0ff */
/*05a0*/ ISETP.GE.U32.AND.EX P0, PT, R5.reuse, c[0x0][0x17c], PT, P0 ; /* 0x00005f0005007a0c */
/* 0x040fe40003f06100 */
/*05b0*/ IADD3.X R8, R5, ~c[0x0][0x17c], RZ, P1, !PT ; /* 0x80005f0005087a10 */
/* 0x000fe40000ffe4ff */
/*05c0*/ SEL R7, R7, R4, P0 ; /* 0x0000000407077207 */
/* 0x000fe40000000000 */
/*05d0*/ SEL R8, R8, R5, P0 ; /* 0x0000000508087207 */
/* 0x000fe40000000000 */
/*05e0*/ ISETP.GE.U32.AND P0, PT, R7.reuse, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x040fe40003f06070 */
/*05f0*/ IADD3 R4, P2, R7, -c[0x0][0x178], RZ ; /* 0x80005e0007047a10 */
/* 0x000fc40007f5e0ff */
/*0600*/ ISETP.GE.U32.AND.EX P0, PT, R8.reuse, c[0x0][0x17c], PT, P0 ; /* 0x00005f0008007a0c */
/* 0x040fe40003f06100 */
/*0610*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25070 */
/*0620*/ IADD3.X R5, R8, ~c[0x0][0x17c], RZ, P2, !PT ; /* 0x80005f0008057a10 */
/* 0x000fe400017fe4ff */
/*0630*/ SEL R4, R4, R7, P0 ; /* 0x0000000704047207 */
/* 0x000fe20000000000 */
/*0640*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fe200078e00ff */
/*0650*/ ISETP.NE.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P1 ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f25310 */
/*0660*/ SEL R5, R5, R8, P0 ; /* 0x0000000805057207 */
/* 0x000fc40000000000 */
/*0670*/ SEL R4, R4, 0xffffffff, P1 ; /* 0xffffffff04047807 */
/* 0x000fe40000800000 */
/*0680*/ SEL R5, R5, 0xffffffff, P1 ; /* 0xffffffff05057807 */
/* 0x000fe20000800000 */
/*0690*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff96006007950 */
/* 0x000fec0003c3ffff */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void
cuda_xor(char * encrypt, char * key, int numElements, size_t len_key){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements){
encrypt[i] = encrypt[i] ^ key[i % len_key];
}
}
void xor_encrypt(char h_m[], char h_k[], size_t o_m_len) {
cudaError_t err = cudaSuccess;
int numElements_m = (int) o_m_len;
int numElements_k = strlen(h_k);
size_t size_m = numElements_m * sizeof(char);
size_t size_k = numElements_k * sizeof(char);
// Alocacao dos vetores do device
char * d_m = NULL;
err = cudaMalloc((void **)&d_m, size_m);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (mensagem) (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
char * d_k = NULL;
err = cudaMalloc((void **)&d_k, size_k);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (chave) (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Copia do vetor com o texto original do host para o do device
printf("Copiando mensagem do host para o device\n");
err = cudaMemcpy(d_m, h_m, size_m, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao copiar string mensagem do host para o device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copiando chave do host para o device\n");
err = cudaMemcpy(d_k, h_k, size_k, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao copiar string chave do host para o device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Rodando o algoritmo de encriptacao
// O tamanho do bloco eh determinado pela funcao cudaOccupancyMaxPotentialBlockSize
// das ferramentas do CUDA.
// O tamanho maximo do grid eh de 65535
int minGridSize, blockSize, gridSize;
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, cuda_xor, 0, numElements_m);
gridSize = (numElements_m + blockSize - 1) / blockSize;
if (gridSize > 65535) gridSize = 65535;
printf("CUDA kernel executando com %d blocos de %d threads\n", gridSize, blockSize);
cuda_xor<<<gridSize, blockSize>>>(d_m, d_k, numElements_m, numElements_k);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao rodar XOR kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copia o resultado do device para o host
printf("Copiando saida do device para o host\n");
err = cudaMemcpy(h_m, d_m, size_m, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao copiar mensagem do device pro host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Liberando o conteudo do device
err = cudaFree(d_m);
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao liberar mensagem do device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_k);
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao liberar chave do device (error code %s )!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Resetando o device e terminando
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao resetar o device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("\nDone\n");
}
int xor_test(char * file, char * key_file)
{
char * o_message, * key, * message;
int pass = 1, fsize;
FILE *f;
f = fopen(file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
o_message = (char *) malloc (fsize * sizeof (char));
fread(o_message, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da mensagem!\n");
exit(EXIT_FAILURE);
}
f = fopen(key_file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
key = (char *) malloc (fsize * sizeof (char));
fread(key, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da chave!\n");
exit(EXIT_FAILURE);
}
message = (char *) malloc (strlen(o_message) * sizeof (char));
strcpy(message, o_message);
xor_encrypt(message, key, strlen(o_message));
xor_encrypt(message, key, strlen(o_message));
pass = pass && !strcmp(o_message, message);
return(pass);
}
int main(int argc, char ** argv)
{
printf("CUDA XOR tests: %s\n", xor_test(argv[1], argv[2]) ? "SUCCEEDED" : "FAILED");
return(0);
} | .file "tmpxft_000ace56_00000000-6_cuda_xor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8cuda_xorPcS_imPcS_im
.type _Z31__device_stub__Z8cuda_xorPcS_imPcS_im, @function
_Z31__device_stub__Z8cuda_xorPcS_imPcS_im:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cuda_xorPcS_im(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z8cuda_xorPcS_imPcS_im, .-_Z31__device_stub__Z8cuda_xorPcS_imPcS_im
.globl _Z8cuda_xorPcS_im
.type _Z8cuda_xorPcS_im, @function
_Z8cuda_xorPcS_im:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8cuda_xorPcS_imPcS_im
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8cuda_xorPcS_im, .-_Z8cuda_xorPcS_im
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Falha ao alocar string do device (mensagem) (error code %s)!\n"
.align 8
.LC1:
.string "Falha ao alocar string do device (chave) (error code %s)!\n"
.align 8
.LC2:
.string "Copiando mensagem do host para o device\n"
.align 8
.LC3:
.string "Falha ao copiar string mensagem do host para o device (error code %s)!\n"
.align 8
.LC4:
.string "Copiando chave do host para o device\n"
.align 8
.LC5:
.string "Falha ao copiar string chave do host para o device (error code %s)!\n"
.align 8
.LC6:
.string "CUDA kernel executando com %d blocos de %d threads\n"
.align 8
.LC7:
.string "Erro ao rodar XOR kernel (error code %s)!\n"
.align 8
.LC8:
.string "Copiando saida do device para o host\n"
.align 8
.LC9:
.string "Erro ao copiar mensagem do device pro host (error code %s)!\n"
.align 8
.LC10:
.string "Erro ao liberar mensagem do device (error code %s)!\n"
.align 8
.LC11:
.string "Erro ao liberar chave do device (error code %s )!\n"
.align 8
.LC12:
.string "Erro ao resetar o device! error=%s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC13:
.string "\nDone\n"
.text
.globl _Z11xor_encryptPcS_m
.type _Z11xor_encryptPcS_m, @function
_Z11xor_encryptPcS_m:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movq %rdi, %r12
movq %rsi, %r15
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movl %edx, 4(%rsp)
movq %rsi, %rdi
call strlen@PLT
movslq %ebx, %r14
movslq %eax, %rbp
movq $0, 72(%rsp)
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
movq $0, 80(%rsp)
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
leaq 56(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L38
.L16:
leal -1(%r13,%rbx), %eax
cltd
idivl %r13d
movl $65535, %edx
cmpl %edx, %eax
movl %edx, %ebx
cmovle %eax, %ebx
movl %r13d, %ecx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl %ebx, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L20:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L40
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r14, %rdx
movq 72(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L41
movq 72(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L42
movq 80(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L43
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L44
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
leaq 60(%rsp), %rdi
movl 56(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L16
leaq 64(%rsp), %rdi
movl 56(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L16
leaq 68(%rsp), %rdi
movl 56(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L16
leaq 88(%rsp), %rdi
movl 56(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L16
leaq 112(%rsp), %rdi
leaq _Z8cuda_xorPcS_im(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L16
movl 136(%rsp), %eax
movl 60(%rsp), %esi
movl 64(%rsp), %ecx
movl %ebx, %edx
testl %ebx, %ebx
jne .L17
movl 68(%rsp), %edx
.L17:
movl 68(%rsp), %edi
cmpl %edi, %eax
cmovg %edi, %eax
cmpl %edx, %eax
cmovle %eax, %edx
movl %edx, %edi
leal -1(%rcx,%rdx), %eax
cltd
idivl %ecx
imull %ecx, %eax
movl %eax, %r15d
testl %eax, %eax
jle .L28
movl $0, 40(%rsp)
movl $0, %eax
movq %r14, 8(%rsp)
movq %rbp, 16(%rsp)
movl %eax, %ebp
movl %ecx, %r14d
movl %r13d, 44(%rsp)
movl %esi, %r13d
movq %r12, 24(%rsp)
movl %edi, %r12d
movq %rbx, 32(%rsp)
jmp .L19
.L18:
cmpl %ebp, %r13d
je .L30
subl %r14d, %r15d
testl %r15d, %r15d
jle .L46
.L19:
cmpl %r15d, %r12d
movl %r15d, %ebx
cmovle %r12d, %ebx
leaq 100(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z8cuda_xorPcS_im(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L32
movl %ebx, %eax
imull 100(%rsp), %eax
cmpl %eax, %ebp
jge .L18
movl %eax, %ebp
movl %ebx, 40(%rsp)
jmp .L18
.L46:
movq 8(%rsp), %r14
movq 16(%rsp), %rbp
movq 24(%rsp), %r12
movq 32(%rsp), %rbx
movl 40(%rsp), %r13d
jmp .L16
.L28:
movl $0, %r13d
jmp .L16
.L30:
movq 8(%rsp), %r14
movq 16(%rsp), %rbp
movq 24(%rsp), %r12
movq 32(%rsp), %rbx
movl 40(%rsp), %r13d
jmp .L16
.L32:
movq 8(%rsp), %r14
movq 16(%rsp), %rbp
movl 44(%rsp), %r13d
movq 24(%rsp), %r12
movq 32(%rsp), %rbx
jmp .L16
.L39:
movq %rbp, %rcx
movl 4(%rsp), %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z31__device_stub__Z8cuda_xorPcS_imPcS_im
jmp .L20
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11xor_encryptPcS_m, .-_Z11xor_encryptPcS_m
.section .rodata.str1.1
.LC14:
.string "r"
.section .rodata.str1.8
.align 8
.LC15:
.string "Erro ao abrir arquivo da mensagem!\n"
.align 8
.LC16:
.string "Erro ao abrir arquivo da chave!\n"
.text
.globl _Z8xor_testPcS_
.type _Z8xor_testPcS_, @function
_Z8xor_testPcS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r13
leaq .LC14(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L48
movq %rax, %rbx
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %rbx, %rdi
call ftell@PLT
movq %rax, %r12
movq %rbx, %rdi
call rewind@PLT
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %r8
movq %r12, %rcx
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
leaq .LC14(%rip), %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, %r13
testq %rax, %rax
je .L54
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %r13, %rdi
call ftell@PLT
movq %rax, %rbx
movq %r13, %rdi
call rewind@PLT
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %r8
movq %rbx, %rcx
movl $1, %edx
movq %rbx, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %r13, %rdi
call fclose@PLT
movq %rbp, %rdi
call strlen@PLT
movq %rax, %r13
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdx
movq %rbp, %rsi
movq %rax, %rdi
call __strcpy_chk@PLT
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z11xor_encryptPcS_m
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z11xor_encryptPcS_m
movq %rbx, %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
sete %al
movzbl %al, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8xor_testPcS_, .-_Z8xor_testPcS_
.section .rodata.str1.1
.LC17:
.string "SUCCEEDED"
.LC18:
.string "FAILED"
.LC19:
.string "CUDA XOR tests: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rsi), %rax
movq 8(%rsi), %rdi
movq %rax, %rsi
call _Z8xor_testPcS_
testl %eax, %eax
leaq .LC18(%rip), %rdx
leaq .LC17(%rip), %rax
cmovne %rax, %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC20:
.string "_Z8cuda_xorPcS_im"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cuda_xorPcS_im(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void
cuda_xor(char * encrypt, char * key, int numElements, size_t len_key){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements){
encrypt[i] = encrypt[i] ^ key[i % len_key];
}
}
void xor_encrypt(char h_m[], char h_k[], size_t o_m_len) {
cudaError_t err = cudaSuccess;
int numElements_m = (int) o_m_len;
int numElements_k = strlen(h_k);
size_t size_m = numElements_m * sizeof(char);
size_t size_k = numElements_k * sizeof(char);
// Alocacao dos vetores do device
char * d_m = NULL;
err = cudaMalloc((void **)&d_m, size_m);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (mensagem) (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
char * d_k = NULL;
err = cudaMalloc((void **)&d_k, size_k);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (chave) (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Copia do vetor com o texto original do host para o do device
printf("Copiando mensagem do host para o device\n");
err = cudaMemcpy(d_m, h_m, size_m, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao copiar string mensagem do host para o device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copiando chave do host para o device\n");
err = cudaMemcpy(d_k, h_k, size_k, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Falha ao copiar string chave do host para o device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Rodando o algoritmo de encriptacao
// O tamanho do bloco eh determinado pela funcao cudaOccupancyMaxPotentialBlockSize
// das ferramentas do CUDA.
// O tamanho maximo do grid eh de 65535
int minGridSize, blockSize, gridSize;
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, cuda_xor, 0, numElements_m);
gridSize = (numElements_m + blockSize - 1) / blockSize;
if (gridSize > 65535) gridSize = 65535;
printf("CUDA kernel executando com %d blocos de %d threads\n", gridSize, blockSize);
cuda_xor<<<gridSize, blockSize>>>(d_m, d_k, numElements_m, numElements_k);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao rodar XOR kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copia o resultado do device para o host
printf("Copiando saida do device para o host\n");
err = cudaMemcpy(h_m, d_m, size_m, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao copiar mensagem do device pro host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Liberando o conteudo do device
err = cudaFree(d_m);
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao liberar mensagem do device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_k);
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao liberar chave do device (error code %s )!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Resetando o device e terminando
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Erro ao resetar o device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("\nDone\n");
}
int xor_test(char * file, char * key_file)
{
char * o_message, * key, * message;
int pass = 1, fsize;
FILE *f;
f = fopen(file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
o_message = (char *) malloc (fsize * sizeof (char));
fread(o_message, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da mensagem!\n");
exit(EXIT_FAILURE);
}
f = fopen(key_file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
key = (char *) malloc (fsize * sizeof (char));
fread(key, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da chave!\n");
exit(EXIT_FAILURE);
}
message = (char *) malloc (strlen(o_message) * sizeof (char));
strcpy(message, o_message);
xor_encrypt(message, key, strlen(o_message));
xor_encrypt(message, key, strlen(o_message));
pass = pass && !strcmp(o_message, message);
return(pass);
}
int main(int argc, char ** argv)
{
printf("CUDA XOR tests: %s\n", xor_test(argv[1], argv[2]) ? "SUCCEEDED" : "FAILED");
return(0);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void
cuda_xor(char * encrypt, char * key, int numElements, size_t len_key){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements){
encrypt[i] = encrypt[i] ^ key[i % len_key];
}
}
void xor_encrypt(char h_m[], char h_k[], size_t o_m_len) {
hipError_t err = hipSuccess;
int numElements_m = (int) o_m_len;
int numElements_k = strlen(h_k);
size_t size_m = numElements_m * sizeof(char);
size_t size_k = numElements_k * sizeof(char);
// Alocacao dos vetores do device
char * d_m = NULL;
err = hipMalloc((void **)&d_m, size_m);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (mensagem) (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
char * d_k = NULL;
err = hipMalloc((void **)&d_k, size_k);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (chave) (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Copia do vetor com o texto original do host para o do device
printf("Copiando mensagem do host para o device\n");
err = hipMemcpy(d_m, h_m, size_m, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao copiar string mensagem do host para o device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copiando chave do host para o device\n");
err = hipMemcpy(d_k, h_k, size_k, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao copiar string chave do host para o device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Rodando o algoritmo de encriptacao
// O tamanho do bloco eh determinado pela funcao cudaOccupancyMaxPotentialBlockSize
// das ferramentas do CUDA.
// O tamanho maximo do grid eh de 65535
int minGridSize, blockSize, gridSize;
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, cuda_xor, 0, numElements_m);
gridSize = (numElements_m + blockSize - 1) / blockSize;
if (gridSize > 65535) gridSize = 65535;
printf("CUDA kernel executando com %d blocos de %d threads\n", gridSize, blockSize);
cuda_xor<<<gridSize, blockSize>>>(d_m, d_k, numElements_m, numElements_k);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao rodar XOR kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copia o resultado do device para o host
printf("Copiando saida do device para o host\n");
err = hipMemcpy(h_m, d_m, size_m, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao copiar mensagem do device pro host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Liberando o conteudo do device
err = hipFree(d_m);
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao liberar mensagem do device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_k);
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao liberar chave do device (error code %s )!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Resetando o device e terminando
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao resetar o device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("\nDone\n");
}
int xor_test(char * file, char * key_file)
{
char * o_message, * key, * message;
int pass = 1, fsize;
FILE *f;
f = fopen(file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
o_message = (char *) malloc (fsize * sizeof (char));
fread(o_message, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da mensagem!\n");
exit(EXIT_FAILURE);
}
f = fopen(key_file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
key = (char *) malloc (fsize * sizeof (char));
fread(key, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da chave!\n");
exit(EXIT_FAILURE);
}
message = (char *) malloc (strlen(o_message) * sizeof (char));
strcpy(message, o_message);
xor_encrypt(message, key, strlen(o_message));
xor_encrypt(message, key, strlen(o_message));
pass = pass && !strcmp(o_message, message);
return(pass);
}
int main(int argc, char ** argv)
{
printf("CUDA XOR tests: %s\n", xor_test(argv[1], argv[2]) ? "SUCCEEDED" : "FAILED");
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void
cuda_xor(char * encrypt, char * key, int numElements, size_t len_key){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements){
encrypt[i] = encrypt[i] ^ key[i % len_key];
}
}
void xor_encrypt(char h_m[], char h_k[], size_t o_m_len) {
hipError_t err = hipSuccess;
int numElements_m = (int) o_m_len;
int numElements_k = strlen(h_k);
size_t size_m = numElements_m * sizeof(char);
size_t size_k = numElements_k * sizeof(char);
// Alocacao dos vetores do device
char * d_m = NULL;
err = hipMalloc((void **)&d_m, size_m);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (mensagem) (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
char * d_k = NULL;
err = hipMalloc((void **)&d_k, size_k);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (chave) (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Copia do vetor com o texto original do host para o do device
printf("Copiando mensagem do host para o device\n");
err = hipMemcpy(d_m, h_m, size_m, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao copiar string mensagem do host para o device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copiando chave do host para o device\n");
err = hipMemcpy(d_k, h_k, size_k, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao copiar string chave do host para o device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Rodando o algoritmo de encriptacao
// O tamanho do bloco eh determinado pela funcao cudaOccupancyMaxPotentialBlockSize
// das ferramentas do CUDA.
// O tamanho maximo do grid eh de 65535
int minGridSize, blockSize, gridSize;
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, cuda_xor, 0, numElements_m);
gridSize = (numElements_m + blockSize - 1) / blockSize;
if (gridSize > 65535) gridSize = 65535;
printf("CUDA kernel executando com %d blocos de %d threads\n", gridSize, blockSize);
cuda_xor<<<gridSize, blockSize>>>(d_m, d_k, numElements_m, numElements_k);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao rodar XOR kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copia o resultado do device para o host
printf("Copiando saida do device para o host\n");
err = hipMemcpy(h_m, d_m, size_m, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao copiar mensagem do device pro host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Liberando o conteudo do device
err = hipFree(d_m);
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao liberar mensagem do device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_k);
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao liberar chave do device (error code %s )!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Resetando o device e terminando
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao resetar o device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("\nDone\n");
}
int xor_test(char * file, char * key_file)
{
char * o_message, * key, * message;
int pass = 1, fsize;
FILE *f;
f = fopen(file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
o_message = (char *) malloc (fsize * sizeof (char));
fread(o_message, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da mensagem!\n");
exit(EXIT_FAILURE);
}
f = fopen(key_file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
key = (char *) malloc (fsize * sizeof (char));
fread(key, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da chave!\n");
exit(EXIT_FAILURE);
}
message = (char *) malloc (strlen(o_message) * sizeof (char));
strcpy(message, o_message);
xor_encrypt(message, key, strlen(o_message));
xor_encrypt(message, key, strlen(o_message));
pass = pass && !strcmp(o_message, message);
return(pass);
}
int main(int argc, char ** argv)
{
printf("CUDA XOR tests: %s\n", xor_test(argv[1], argv[2]) ? "SUCCEEDED" : "FAILED");
return(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cuda_xorPcS_im
.globl _Z8cuda_xorPcS_im
.p2align 8
.type _Z8cuda_xorPcS_im,@function
_Z8cuda_xorPcS_im:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_or_b32_e32 v5, s5, v3
global_load_u8 v6, v[0:1], off
v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s3, exec_lo, s2
s_cbranch_execz .LBB0_3
v_cvt_f32_u32_e32 v4, s4
v_cvt_f32_u32_e32 v5, s5
s_sub_u32 s2, 0, s4
s_subb_u32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0x4f800000, v4
v_rcp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x5f7ffffc, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x2f800000, v4
v_trunc_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v5, 0xcf800000, v4
v_cvt_u32_f32_e32 v5, v5
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, s2, v5
v_mul_hi_u32 v8, s2, v4
v_mul_lo_u32 v9, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v8, v7
v_mul_lo_u32 v8, s2, v4
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v4, v8
v_mul_lo_u32 v10, v4, v7
v_mul_hi_u32 v11, v4, v7
v_mul_hi_u32 v12, v5, v8
v_mul_lo_u32 v8, v5, v8
v_mul_hi_u32 v13, v5, v7
v_mul_lo_u32 v7, v5, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v7, s2, v4
v_mul_lo_u32 v9, s6, v4
v_mul_lo_u32 v8, s2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v8, s2, v4
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v4, v8
v_mul_lo_u32 v10, v4, v7
v_mul_hi_u32 v11, v4, v7
v_mul_hi_u32 v12, v5, v8
v_mul_lo_u32 v8, v5, v8
v_mul_hi_u32 v13, v5, v7
v_mul_lo_u32 v7, v5, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v4, v7
v_add_co_ci_u32_e32 v11, vcc_lo, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v12, v2, v9
v_mad_u64_u32 v[7:8], null, v3, v9, 0
v_mad_u64_u32 v[4:5], null, v2, v11, 0
v_mad_u64_u32 v[9:10], null, v3, v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v12, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v7
v_add_co_ci_u32_e32 v4, vcc_lo, v5, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v4, v9
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v9, s5, v7
v_mad_u64_u32 v[4:5], null, s4, v7, 0
v_mul_lo_u32 v7, s4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, vcc_lo, v2, v4
v_add3_u32 v5, v5, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v3, v5
v_subrev_co_ci_u32_e64 v4, s2, s5, v7, vcc_lo
v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
v_sub_co_u32 v5, vcc_lo, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v7, s2, 0, v4, vcc_lo
v_cmp_le_u32_e64 s2, s4, v2
v_subrev_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_cndmask_b32_e64 v8, 0, -1, s2
v_cmp_le_u32_e64 s2, s4, v5
v_cndmask_b32_e64 v11, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v9, 0, -1, s2
v_cmp_le_u32_e64 s2, s5, v7
v_cndmask_b32_e64 v10, 0, -1, s2
v_cmp_eq_u32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v10, v9, vcc_lo
v_sub_co_u32 v10, vcc_lo, v5, s4
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v9
v_cndmask_b32_e64 v8, v11, v8, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v4, v7, v4 :: v_dual_cndmask_b32 v7, v5, v10
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v5, v3, v4 :: v_dual_cndmask_b32 v4, v2, v7
.LBB0_3:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_5
v_cvt_f32_u32_e32 v3, s4
s_sub_i32 s3, 0, s4
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s3, v3
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s4
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v4, v2, v3, vcc_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v2, v2, v6
global_store_b8 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cuda_xorPcS_im
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cuda_xorPcS_im, .Lfunc_end0-_Z8cuda_xorPcS_im
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cuda_xorPcS_im
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8cuda_xorPcS_im.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__global__ void
cuda_xor(char * encrypt, char * key, int numElements, size_t len_key){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements){
encrypt[i] = encrypt[i] ^ key[i % len_key];
}
}
void xor_encrypt(char h_m[], char h_k[], size_t o_m_len) {
hipError_t err = hipSuccess;
int numElements_m = (int) o_m_len;
int numElements_k = strlen(h_k);
size_t size_m = numElements_m * sizeof(char);
size_t size_k = numElements_k * sizeof(char);
// Alocacao dos vetores do device
char * d_m = NULL;
err = hipMalloc((void **)&d_m, size_m);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (mensagem) (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
char * d_k = NULL;
err = hipMalloc((void **)&d_k, size_k);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao alocar string do device (chave) (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Copia do vetor com o texto original do host para o do device
printf("Copiando mensagem do host para o device\n");
err = hipMemcpy(d_m, h_m, size_m, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao copiar string mensagem do host para o device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copiando chave do host para o device\n");
err = hipMemcpy(d_k, h_k, size_k, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Falha ao copiar string chave do host para o device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Rodando o algoritmo de encriptacao
// O tamanho do bloco eh determinado pela funcao cudaOccupancyMaxPotentialBlockSize
// das ferramentas do CUDA.
// O tamanho maximo do grid eh de 65535
int minGridSize, blockSize, gridSize;
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, cuda_xor, 0, numElements_m);
gridSize = (numElements_m + blockSize - 1) / blockSize;
if (gridSize > 65535) gridSize = 65535;
printf("CUDA kernel executando com %d blocos de %d threads\n", gridSize, blockSize);
cuda_xor<<<gridSize, blockSize>>>(d_m, d_k, numElements_m, numElements_k);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao rodar XOR kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Copia o resultado do device para o host
printf("Copiando saida do device para o host\n");
err = hipMemcpy(h_m, d_m, size_m, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao copiar mensagem do device pro host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Liberando o conteudo do device
err = hipFree(d_m);
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao liberar mensagem do device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_k);
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao liberar chave do device (error code %s )!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Resetando o device e terminando
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Erro ao resetar o device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("\nDone\n");
}
int xor_test(char * file, char * key_file)
{
char * o_message, * key, * message;
int pass = 1, fsize;
FILE *f;
f = fopen(file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
o_message = (char *) malloc (fsize * sizeof (char));
fread(o_message, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da mensagem!\n");
exit(EXIT_FAILURE);
}
f = fopen(key_file, "r");
if (f){
fseek(f, 0, SEEK_END);
fsize = ftell(f);
rewind(f);
key = (char *) malloc (fsize * sizeof (char));
fread(key, 1, fsize, f);
fclose(f);
}
else{
fprintf(stderr, "Erro ao abrir arquivo da chave!\n");
exit(EXIT_FAILURE);
}
message = (char *) malloc (strlen(o_message) * sizeof (char));
strcpy(message, o_message);
xor_encrypt(message, key, strlen(o_message));
xor_encrypt(message, key, strlen(o_message));
pass = pass && !strcmp(o_message, message);
return(pass);
}
int main(int argc, char ** argv)
{
printf("CUDA XOR tests: %s\n", xor_test(argv[1], argv[2]) ? "SUCCEEDED" : "FAILED");
return(0);
} | .text
.file "cuda_xor.hip"
.globl _Z23__device_stub__cuda_xorPcS_im # -- Begin function _Z23__device_stub__cuda_xorPcS_im
.p2align 4, 0x90
.type _Z23__device_stub__cuda_xorPcS_im,@function
_Z23__device_stub__cuda_xorPcS_im: # @_Z23__device_stub__cuda_xorPcS_im
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cuda_xorPcS_im, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__cuda_xorPcS_im, .Lfunc_end0-_Z23__device_stub__cuda_xorPcS_im
.cfi_endproc
# -- End function
.globl _Z11xor_encryptPcS_m # -- Begin function _Z11xor_encryptPcS_m
.p2align 4, 0x90
.type _Z11xor_encryptPcS_m,@function
_Z11xor_encryptPcS_m: # @_Z11xor_encryptPcS_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq strlen
movq %rax, %r12
movslq %r15d, %r14
movq $0, (%rsp)
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
movslq %r12d, %r12
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
leaq 108(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $_Z8cuda_xorPcS_im, %edx
xorl %ecx, %ecx
movl %r15d, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 12(%rsp), %ecx
leal (%r15,%rcx), %eax
decl %eax
cltd
idivl %ecx
cmpl $65535, %eax # imm = 0xFFFF
movl $65535, %r13d # imm = 0xFFFF
cmovll %eax, %r13d
movl $.L.str.6, %edi
movl %r13d, %esi
movl %ecx, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r13
orq %rax, %rdx
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl %r15d, 28(%rsp)
movq %r12, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8cuda_xorPcS_im, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_12
# %bb.13:
movl $.Lstr.2, %edi
callq puts@PLT
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_18
# %bb.19:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_20
# %bb.21:
movl $.Lstr.3, %edi
callq puts@PLT
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
.LBB1_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z11xor_encryptPcS_m, .Lfunc_end1-_Z11xor_encryptPcS_m
.cfi_endproc
# -- End function
.globl _Z8xor_testPcS_ # -- Begin function _Z8xor_testPcS_
.p2align 4, 0x90
.type _Z8xor_testPcS_,@function
_Z8xor_testPcS_: # @_Z8xor_testPcS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movl $.L.str.14, %esi
callq fopen
testq %rax, %rax
je .LBB2_3
# %bb.1:
movq %rax, %r15
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r15, %rdi
callq ftell
movq %rax, %rbx
movq %r15, %rdi
callq rewind
movslq %ebx, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movl $1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r15, %rcx
callq fread
movq %r15, %rdi
callq fclose
movl $.L.str.14, %esi
movq %r14, %rdi
callq fopen
testq %rax, %rax
je .LBB2_5
# %bb.2:
movq %rax, %r15
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r15, %rdi
callq ftell
movq %rax, %r14
movq %r15, %rdi
callq rewind
movslq %r14d, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r15, %rcx
callq fread
movq %r15, %rdi
callq fclose
movq %rbx, %rdi
callq strlen
movq %rax, %rdi
callq malloc
movq %rax, %r15
movq %rax, %rdi
movq %rbx, %rsi
callq strcpy
movq %rbx, %rdi
callq strlen
movq %rax, %r12
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _Z11xor_encryptPcS_m
movq %r15, %rdi
movq %r14, %rsi
movq %r12, %rdx
callq _Z11xor_encryptPcS_m
movq %rbx, %rdi
movq %r15, %rsi
callq strcmp
xorl %ecx, %ecx
testl %eax, %eax
sete %cl
movl %ecx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_3:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rcx
movl $.L.str.15, %edi
movl $35, %esi
jmp .LBB2_4
.LBB2_5:
movq stderr(%rip), %rcx
movl $.L.str.16, %edi
movl $32, %esi
.LBB2_4:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z8xor_testPcS_, .Lfunc_end2-_Z8xor_testPcS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq 8(%rsi), %rdi
movq 16(%rsi), %rsi
callq _Z8xor_testPcS_
testl %eax, %eax
movl $.L.str.19, %eax
movl $.L.str.18, %esi
cmoveq %rax, %rsi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cuda_xorPcS_im, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cuda_xorPcS_im,@object # @_Z8cuda_xorPcS_im
.section .rodata,"a",@progbits
.globl _Z8cuda_xorPcS_im
.p2align 3, 0x0
_Z8cuda_xorPcS_im:
.quad _Z23__device_stub__cuda_xorPcS_im
.size _Z8cuda_xorPcS_im, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Falha ao alocar string do device (mensagem) (error code %s)!\n"
.size .L.str, 62
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Falha ao alocar string do device (chave) (error code %s)!\n"
.size .L.str.1, 59
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Falha ao copiar string mensagem do host para o device (error code %s)!\n"
.size .L.str.3, 72
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Falha ao copiar string chave do host para o device (error code %s)!\n"
.size .L.str.5, 69
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA kernel executando com %d blocos de %d threads\n"
.size .L.str.6, 52
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Erro ao rodar XOR kernel (error code %s)!\n"
.size .L.str.7, 43
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Erro ao copiar mensagem do device pro host (error code %s)!\n"
.size .L.str.9, 61
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Erro ao liberar mensagem do device (error code %s)!\n"
.size .L.str.10, 53
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Erro ao liberar chave do device (error code %s )!\n"
.size .L.str.11, 51
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Erro ao resetar o device! error=%s\n"
.size .L.str.12, 36
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "r"
.size .L.str.14, 2
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Erro ao abrir arquivo da mensagem!\n"
.size .L.str.15, 36
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Erro ao abrir arquivo da chave!\n"
.size .L.str.16, 33
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "CUDA XOR tests: %s\n"
.size .L.str.17, 20
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "SUCCEEDED"
.size .L.str.18, 10
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "FAILED"
.size .L.str.19, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8cuda_xorPcS_im"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Copiando mensagem do host para o device"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Copiando chave do host para o device"
.size .Lstr.1, 37
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Copiando saida do device para o host"
.size .Lstr.2, 37
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone"
.size .Lstr.3, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cuda_xorPcS_im
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cuda_xorPcS_im
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8cuda_xorPcS_im
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1100 */
/*00b0*/ LOP3.LUT R6, R5, c[0x0][0x17c], RZ, 0xfc, !PT ; /* 0x00005f0005067a12 */
/* 0x000fe200078efcff */
/*00c0*/ BSSY B0, 0x250 ; /* 0x0000018000007945 */
/* 0x000fe60003800000 */
/*00d0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*00e0*/ @!P0 BRA 0x120 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R6, 0x110 ; /* 0x0000011000067802 */
/* 0x001fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x2b0 ; /* 0x000001a000007944 */
/* 0x020fea0003c00000 */
/*0110*/ BRA 0x240 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0120*/ I2F.U32.RP R5, c[0x0][0x178] ; /* 0x00005e0000057b06 */
/* 0x001e220000209000 */
/*0130*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fce0003f25070 */
/*0140*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fe20007ffe0ff */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fca00078e00ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a07 */
/*01a0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*01c0*/ IMAD.HI.U32 R7, R7, R4, RZ ; /* 0x0000000407077227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a07 */
/*01e0*/ IMAD R4, R7, c[0x0][0x178], R4 ; /* 0x00005e0007047a24 */
/* 0x000fca00078e0204 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R4, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004040a10 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*0220*/ @P0 IADD3 R4, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004040a10 */
/* 0x000fe40007ffe0ff */
/*0230*/ @!P1 LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff049a12 */
/* 0x000fe400078e33ff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f1e0ff */
/*0260*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005057a10 */
/* 0x000fcc00007fe4ff */
/*0270*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1100 */
/*0280*/ LOP3.LUT R7, R5, R0, RZ, 0x3c, !PT ; /* 0x0000000005077212 */
/* 0x024fca00078e3cff */
/*0290*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ I2F.U64.RP R7, c[0x0][0x178] ; /* 0x00005e0000077b12 */
/* 0x000e300000309000 */
/*02c0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*02d0*/ IADD3 R8, R7, 0x1ffffffe, RZ ; /* 0x1ffffffe07087810 */
/* 0x001fcc0007ffe0ff */
/*02e0*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*02f0*/ IMAD.WIDE.U32 R10, R8, c[0x0][0x178], RZ ; /* 0x00005e00080a7a25 */
/* 0x001fc800078e00ff */
/*0300*/ IMAD R11, R8, c[0x0][0x17c], R11 ; /* 0x00005f00080b7a24 */
/* 0x000fe200078e020b */
/*0310*/ IADD3 R13, P0, RZ, -R10, RZ ; /* 0x8000000aff0d7210 */
/* 0x000fc60007f1e0ff */
/*0320*/ IMAD R11, R9, c[0x0][0x178], R11 ; /* 0x00005e00090b7a24 */
/* 0x000fe400078e020b */
/*0330*/ IMAD.HI.U32 R10, R8, R13, RZ ; /* 0x0000000d080a7227 */
/* 0x000fc800078e00ff */
/*0340*/ IMAD.X R15, RZ, RZ, ~R11, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0e0b */
/*0350*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0008 */
/*0360*/ IMAD R17, R9, R15.reuse, RZ ; /* 0x0000000f09117224 */
/* 0x080fe400078e02ff */
/*0370*/ IMAD.WIDE.U32 R10, P0, R8, R15, R10 ; /* 0x0000000f080a7225 */
/* 0x000fc8000780000a */
/*0380*/ IMAD.HI.U32 R7, R9, R15, RZ ; /* 0x0000000f09077227 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.HI.U32 R10, P1, R9, R13, R10 ; /* 0x0000000d090a7227 */
/* 0x000fe2000782000a */
/*03a0*/ IADD3.X R7, R7, R9, RZ, P0, !PT ; /* 0x0000000907077210 */
/* 0x000fc800007fe4ff */
/*03b0*/ IADD3 R11, P2, R17, R10, RZ ; /* 0x0000000a110b7210 */
/* 0x000fc80007f5e0ff */
/*03c0*/ IADD3.X R7, RZ, RZ, R7, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fe200017e2407 */
/*03d0*/ IMAD.WIDE.U32 R8, R11, c[0x0][0x178], RZ ; /* 0x00005e000b087a25 */
/* 0x000fc800078e00ff */
/*03e0*/ IMAD R10, R11, c[0x0][0x17c], R9 ; /* 0x00005f000b0a7a24 */
/* 0x000fe200078e0209 */
/*03f0*/ IADD3 R9, P0, RZ, -R8, RZ ; /* 0x80000008ff097210 */
/* 0x000fc60007f1e0ff */
/*0400*/ IMAD R8, R7, c[0x0][0x178], R10 ; /* 0x00005e0007087a24 */
/* 0x000fe400078e020a */
/*0410*/ IMAD.HI.U32 R10, R11, R9, RZ ; /* 0x000000090b0a7227 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD.X R8, RZ, RZ, ~R8, P0 ; /* 0x000000ffff087224 */
/* 0x000fc800000e0e08 */
/*0430*/ IMAD.WIDE.U32 R10, P0, R11, R8, R10 ; /* 0x000000080b0a7225 */
/* 0x000fc8000780000a */
/*0440*/ IMAD R12, R7.reuse, R8, RZ ; /* 0x00000008070c7224 */
/* 0x040fe400078e02ff */
/*0450*/ IMAD.HI.U32 R11, P1, R7, R9, R10 ; /* 0x00000009070b7227 */
/* 0x000fc8000782000a */
/*0460*/ IMAD.HI.U32 R8, R7, R8, RZ ; /* 0x0000000807087227 */
/* 0x000fe200078e00ff */
/*0470*/ IADD3 R11, P2, R12, R11, RZ ; /* 0x0000000b0c0b7210 */
/* 0x000fc60007f5e0ff */
/*0480*/ IMAD.X R7, R8, 0x1, R7, P0 ; /* 0x0000000108077824 */
/* 0x000fe400000e0607 */
/*0490*/ IMAD.HI.U32 R8, R11, R4, RZ ; /* 0x000000040b087227 */
/* 0x000fc600078e00ff */
/*04a0*/ IADD3.X R7, RZ, RZ, R7, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fe200017e2407 */
/*04b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc800078e00ff */
/*04c0*/ IMAD.WIDE.U32 R8, R11, R5, R8 ; /* 0x000000050b087225 */
/* 0x000fc800078e0008 */
/*04d0*/ IMAD R11, R7.reuse, R5, RZ ; /* 0x00000005070b7224 */
/* 0x040fe400078e02ff */
/*04e0*/ IMAD.HI.U32 R8, P0, R7, R4, R8 ; /* 0x0000000407087227 */
/* 0x000fc80007800008 */
/*04f0*/ IMAD.HI.U32 R7, R7, R5, RZ ; /* 0x0000000507077227 */
/* 0x000fe200078e00ff */
/*0500*/ IADD3 R11, P1, R11, R8, RZ ; /* 0x000000080b0b7210 */
/* 0x000fc60007f3e0ff */
/*0510*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe400000e0607 */
/*0520*/ IMAD.WIDE.U32 R8, R11, c[0x0][0x178], RZ ; /* 0x00005e000b087a25 */
/* 0x000fc600078e00ff */
/*0530*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0540*/ IMAD R10, R11, c[0x0][0x17c], R9 ; /* 0x00005f000b0a7a24 */
/* 0x000fe200078e0209 */
/*0550*/ IADD3 R4, P1, -R8, R4, RZ ; /* 0x0000000408047210 */
/* 0x000fc60007f3e1ff */
/*0560*/ IMAD R10, R7, c[0x0][0x178], R10 ; /* 0x00005e00070a7a24 */
/* 0x000fe200078e020a */
/*0570*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc60003f06070 */
/*0580*/ IMAD.X R5, R5, 0x1, ~R10, P1 ; /* 0x0000000105057824 */
/* 0x000fe200008e0e0a */
/*0590*/ IADD3 R7, P1, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004077a10 */
/* 0x000fc80007f3e0ff */
/*05a0*/ ISETP.GE.U32.AND.EX P0, PT, R5.reuse, c[0x0][0x17c], PT, P0 ; /* 0x00005f0005007a0c */
/* 0x040fe40003f06100 */
/*05b0*/ IADD3.X R8, R5, ~c[0x0][0x17c], RZ, P1, !PT ; /* 0x80005f0005087a10 */
/* 0x000fe40000ffe4ff */
/*05c0*/ SEL R7, R7, R4, P0 ; /* 0x0000000407077207 */
/* 0x000fe40000000000 */
/*05d0*/ SEL R8, R8, R5, P0 ; /* 0x0000000508087207 */
/* 0x000fe40000000000 */
/*05e0*/ ISETP.GE.U32.AND P0, PT, R7.reuse, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x040fe40003f06070 */
/*05f0*/ IADD3 R4, P2, R7, -c[0x0][0x178], RZ ; /* 0x80005e0007047a10 */
/* 0x000fc40007f5e0ff */
/*0600*/ ISETP.GE.U32.AND.EX P0, PT, R8.reuse, c[0x0][0x17c], PT, P0 ; /* 0x00005f0008007a0c */
/* 0x040fe40003f06100 */
/*0610*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25070 */
/*0620*/ IADD3.X R5, R8, ~c[0x0][0x17c], RZ, P2, !PT ; /* 0x80005f0008057a10 */
/* 0x000fe400017fe4ff */
/*0630*/ SEL R4, R4, R7, P0 ; /* 0x0000000704047207 */
/* 0x000fe20000000000 */
/*0640*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fe200078e00ff */
/*0650*/ ISETP.NE.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P1 ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f25310 */
/*0660*/ SEL R5, R5, R8, P0 ; /* 0x0000000805057207 */
/* 0x000fc40000000000 */
/*0670*/ SEL R4, R4, 0xffffffff, P1 ; /* 0xffffffff04047807 */
/* 0x000fe40000800000 */
/*0680*/ SEL R5, R5, 0xffffffff, P1 ; /* 0xffffffff05057807 */
/* 0x000fe20000800000 */
/*0690*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff96006007950 */
/* 0x000fec0003c3ffff */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cuda_xorPcS_im
.globl _Z8cuda_xorPcS_im
.p2align 8
.type _Z8cuda_xorPcS_im,@function
_Z8cuda_xorPcS_im:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_or_b32_e32 v5, s5, v3
global_load_u8 v6, v[0:1], off
v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s3, exec_lo, s2
s_cbranch_execz .LBB0_3
v_cvt_f32_u32_e32 v4, s4
v_cvt_f32_u32_e32 v5, s5
s_sub_u32 s2, 0, s4
s_subb_u32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0x4f800000, v4
v_rcp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x5f7ffffc, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x2f800000, v4
v_trunc_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v5, 0xcf800000, v4
v_cvt_u32_f32_e32 v5, v5
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, s2, v5
v_mul_hi_u32 v8, s2, v4
v_mul_lo_u32 v9, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v8, v7
v_mul_lo_u32 v8, s2, v4
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v4, v8
v_mul_lo_u32 v10, v4, v7
v_mul_hi_u32 v11, v4, v7
v_mul_hi_u32 v12, v5, v8
v_mul_lo_u32 v8, v5, v8
v_mul_hi_u32 v13, v5, v7
v_mul_lo_u32 v7, v5, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v7, s2, v4
v_mul_lo_u32 v9, s6, v4
v_mul_lo_u32 v8, s2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v7, v8
v_mul_lo_u32 v8, s2, v4
v_add_nc_u32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v4, v8
v_mul_lo_u32 v10, v4, v7
v_mul_hi_u32 v11, v4, v7
v_mul_hi_u32 v12, v5, v8
v_mul_lo_u32 v8, v5, v8
v_mul_hi_u32 v13, v5, v7
v_mul_lo_u32 v7, v5, v7
v_add_co_u32 v9, vcc_lo, v9, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v12, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v4, v7
v_add_co_ci_u32_e32 v11, vcc_lo, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v12, v2, v9
v_mad_u64_u32 v[7:8], null, v3, v9, 0
v_mad_u64_u32 v[4:5], null, v2, v11, 0
v_mad_u64_u32 v[9:10], null, v3, v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v12, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v7
v_add_co_ci_u32_e32 v4, vcc_lo, v5, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v4, v9
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v9, s5, v7
v_mad_u64_u32 v[4:5], null, s4, v7, 0
v_mul_lo_u32 v7, s4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, vcc_lo, v2, v4
v_add3_u32 v5, v5, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v3, v5
v_subrev_co_ci_u32_e64 v4, s2, s5, v7, vcc_lo
v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
v_sub_co_u32 v5, vcc_lo, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v7, s2, 0, v4, vcc_lo
v_cmp_le_u32_e64 s2, s4, v2
v_subrev_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_cndmask_b32_e64 v8, 0, -1, s2
v_cmp_le_u32_e64 s2, s4, v5
v_cndmask_b32_e64 v11, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v9, 0, -1, s2
v_cmp_le_u32_e64 s2, s5, v7
v_cndmask_b32_e64 v10, 0, -1, s2
v_cmp_eq_u32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v10, v9, vcc_lo
v_sub_co_u32 v10, vcc_lo, v5, s4
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v9
v_cndmask_b32_e64 v8, v11, v8, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v4, v7, v4 :: v_dual_cndmask_b32 v7, v5, v10
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v5, v3, v4 :: v_dual_cndmask_b32 v4, v2, v7
.LBB0_3:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_5
v_cvt_f32_u32_e32 v3, s4
s_sub_i32 s3, 0, s4
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s3, v3
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s4
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v4, v2, v3, vcc_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v2, v2, v6
global_store_b8 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cuda_xorPcS_im
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cuda_xorPcS_im, .Lfunc_end0-_Z8cuda_xorPcS_im
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cuda_xorPcS_im
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8cuda_xorPcS_im.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ace56_00000000-6_cuda_xor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8cuda_xorPcS_imPcS_im
.type _Z31__device_stub__Z8cuda_xorPcS_imPcS_im, @function
_Z31__device_stub__Z8cuda_xorPcS_imPcS_im:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cuda_xorPcS_im(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z8cuda_xorPcS_imPcS_im, .-_Z31__device_stub__Z8cuda_xorPcS_imPcS_im
.globl _Z8cuda_xorPcS_im
.type _Z8cuda_xorPcS_im, @function
_Z8cuda_xorPcS_im:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8cuda_xorPcS_imPcS_im
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8cuda_xorPcS_im, .-_Z8cuda_xorPcS_im
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Falha ao alocar string do device (mensagem) (error code %s)!\n"
.align 8
.LC1:
.string "Falha ao alocar string do device (chave) (error code %s)!\n"
.align 8
.LC2:
.string "Copiando mensagem do host para o device\n"
.align 8
.LC3:
.string "Falha ao copiar string mensagem do host para o device (error code %s)!\n"
.align 8
.LC4:
.string "Copiando chave do host para o device\n"
.align 8
.LC5:
.string "Falha ao copiar string chave do host para o device (error code %s)!\n"
.align 8
.LC6:
.string "CUDA kernel executando com %d blocos de %d threads\n"
.align 8
.LC7:
.string "Erro ao rodar XOR kernel (error code %s)!\n"
.align 8
.LC8:
.string "Copiando saida do device para o host\n"
.align 8
.LC9:
.string "Erro ao copiar mensagem do device pro host (error code %s)!\n"
.align 8
.LC10:
.string "Erro ao liberar mensagem do device (error code %s)!\n"
.align 8
.LC11:
.string "Erro ao liberar chave do device (error code %s )!\n"
.align 8
.LC12:
.string "Erro ao resetar o device! error=%s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC13:
.string "\nDone\n"
.text
.globl _Z11xor_encryptPcS_m
.type _Z11xor_encryptPcS_m, @function
_Z11xor_encryptPcS_m:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movq %rdi, %r12
movq %rsi, %r15
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movl %edx, 4(%rsp)
movq %rsi, %rdi
call strlen@PLT
movslq %ebx, %r14
movslq %eax, %rbp
movq $0, 72(%rsp)
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
movq $0, 80(%rsp)
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
leaq 56(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L38
.L16:
leal -1(%r13,%rbx), %eax
cltd
idivl %r13d
movl $65535, %edx
cmpl %edx, %eax
movl %edx, %ebx
cmovle %eax, %ebx
movl %r13d, %ecx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl %ebx, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L20:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L40
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r14, %rdx
movq 72(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L41
movq 72(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L42
movq 80(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L43
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L44
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
leaq 60(%rsp), %rdi
movl 56(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L16
leaq 64(%rsp), %rdi
movl 56(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L16
leaq 68(%rsp), %rdi
movl 56(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L16
leaq 88(%rsp), %rdi
movl 56(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L16
leaq 112(%rsp), %rdi
leaq _Z8cuda_xorPcS_im(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L16
movl 136(%rsp), %eax
movl 60(%rsp), %esi
movl 64(%rsp), %ecx
movl %ebx, %edx
testl %ebx, %ebx
jne .L17
movl 68(%rsp), %edx
.L17:
movl 68(%rsp), %edi
cmpl %edi, %eax
cmovg %edi, %eax
cmpl %edx, %eax
cmovle %eax, %edx
movl %edx, %edi
leal -1(%rcx,%rdx), %eax
cltd
idivl %ecx
imull %ecx, %eax
movl %eax, %r15d
testl %eax, %eax
jle .L28
movl $0, 40(%rsp)
movl $0, %eax
movq %r14, 8(%rsp)
movq %rbp, 16(%rsp)
movl %eax, %ebp
movl %ecx, %r14d
movl %r13d, 44(%rsp)
movl %esi, %r13d
movq %r12, 24(%rsp)
movl %edi, %r12d
movq %rbx, 32(%rsp)
jmp .L19
.L18:
cmpl %ebp, %r13d
je .L30
subl %r14d, %r15d
testl %r15d, %r15d
jle .L46
.L19:
cmpl %r15d, %r12d
movl %r15d, %ebx
cmovle %r12d, %ebx
leaq 100(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z8cuda_xorPcS_im(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L32
movl %ebx, %eax
imull 100(%rsp), %eax
cmpl %eax, %ebp
jge .L18
movl %eax, %ebp
movl %ebx, 40(%rsp)
jmp .L18
.L46:
movq 8(%rsp), %r14
movq 16(%rsp), %rbp
movq 24(%rsp), %r12
movq 32(%rsp), %rbx
movl 40(%rsp), %r13d
jmp .L16
.L28:
movl $0, %r13d
jmp .L16
.L30:
movq 8(%rsp), %r14
movq 16(%rsp), %rbp
movq 24(%rsp), %r12
movq 32(%rsp), %rbx
movl 40(%rsp), %r13d
jmp .L16
.L32:
movq 8(%rsp), %r14
movq 16(%rsp), %rbp
movl 44(%rsp), %r13d
movq 24(%rsp), %r12
movq 32(%rsp), %rbx
jmp .L16
.L39:
movq %rbp, %rcx
movl 4(%rsp), %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z31__device_stub__Z8cuda_xorPcS_imPcS_im
jmp .L20
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11xor_encryptPcS_m, .-_Z11xor_encryptPcS_m
.section .rodata.str1.1
.LC14:
.string "r"
.section .rodata.str1.8
.align 8
.LC15:
.string "Erro ao abrir arquivo da mensagem!\n"
.align 8
.LC16:
.string "Erro ao abrir arquivo da chave!\n"
.text
.globl _Z8xor_testPcS_
.type _Z8xor_testPcS_, @function
_Z8xor_testPcS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r13
leaq .LC14(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L48
movq %rax, %rbx
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %rbx, %rdi
call ftell@PLT
movq %rax, %r12
movq %rbx, %rdi
call rewind@PLT
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %r8
movq %r12, %rcx
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
leaq .LC14(%rip), %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, %r13
testq %rax, %rax
je .L54
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %r13, %rdi
call ftell@PLT
movq %rax, %rbx
movq %r13, %rdi
call rewind@PLT
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %r8
movq %rbx, %rcx
movl $1, %edx
movq %rbx, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %r13, %rdi
call fclose@PLT
movq %rbp, %rdi
call strlen@PLT
movq %rax, %r13
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdx
movq %rbp, %rsi
movq %rax, %rdi
call __strcpy_chk@PLT
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z11xor_encryptPcS_m
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z11xor_encryptPcS_m
movq %rbx, %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
sete %al
movzbl %al, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8xor_testPcS_, .-_Z8xor_testPcS_
.section .rodata.str1.1
.LC17:
.string "SUCCEEDED"
.LC18:
.string "FAILED"
.LC19:
.string "CUDA XOR tests: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rsi), %rax
movq 8(%rsi), %rdi
movq %rax, %rsi
call _Z8xor_testPcS_
testl %eax, %eax
leaq .LC18(%rip), %rdx
leaq .LC17(%rip), %rax
cmovne %rax, %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC20:
.string "_Z8cuda_xorPcS_im"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cuda_xorPcS_im(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_xor.hip"
.globl _Z23__device_stub__cuda_xorPcS_im # -- Begin function _Z23__device_stub__cuda_xorPcS_im
.p2align 4, 0x90
.type _Z23__device_stub__cuda_xorPcS_im,@function
_Z23__device_stub__cuda_xorPcS_im: # @_Z23__device_stub__cuda_xorPcS_im
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cuda_xorPcS_im, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__cuda_xorPcS_im, .Lfunc_end0-_Z23__device_stub__cuda_xorPcS_im
.cfi_endproc
# -- End function
.globl _Z11xor_encryptPcS_m # -- Begin function _Z11xor_encryptPcS_m
.p2align 4, 0x90
.type _Z11xor_encryptPcS_m,@function
_Z11xor_encryptPcS_m: # @_Z11xor_encryptPcS_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq strlen
movq %rax, %r12
movslq %r15d, %r14
movq $0, (%rsp)
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
movslq %r12d, %r12
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9:
leaq 108(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $_Z8cuda_xorPcS_im, %edx
xorl %ecx, %ecx
movl %r15d, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 12(%rsp), %ecx
leal (%r15,%rcx), %eax
decl %eax
cltd
idivl %ecx
cmpl $65535, %eax # imm = 0xFFFF
movl $65535, %r13d # imm = 0xFFFF
cmovll %eax, %r13d
movl $.L.str.6, %edi
movl %r13d, %esi
movl %ecx, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r13
orq %rax, %rdx
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl %r15d, 28(%rsp)
movq %r12, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8cuda_xorPcS_im, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_12
# %bb.13:
movl $.Lstr.2, %edi
callq puts@PLT
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_18
# %bb.19:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_20
# %bb.21:
movl $.Lstr.3, %edi
callq puts@PLT
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
.LBB1_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z11xor_encryptPcS_m, .Lfunc_end1-_Z11xor_encryptPcS_m
.cfi_endproc
# -- End function
.globl _Z8xor_testPcS_ # -- Begin function _Z8xor_testPcS_
.p2align 4, 0x90
.type _Z8xor_testPcS_,@function
_Z8xor_testPcS_: # @_Z8xor_testPcS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movl $.L.str.14, %esi
callq fopen
testq %rax, %rax
je .LBB2_3
# %bb.1:
movq %rax, %r15
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r15, %rdi
callq ftell
movq %rax, %rbx
movq %r15, %rdi
callq rewind
movslq %ebx, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movl $1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r15, %rcx
callq fread
movq %r15, %rdi
callq fclose
movl $.L.str.14, %esi
movq %r14, %rdi
callq fopen
testq %rax, %rax
je .LBB2_5
# %bb.2:
movq %rax, %r15
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r15, %rdi
callq ftell
movq %rax, %r14
movq %r15, %rdi
callq rewind
movslq %r14d, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $1, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r15, %rcx
callq fread
movq %r15, %rdi
callq fclose
movq %rbx, %rdi
callq strlen
movq %rax, %rdi
callq malloc
movq %rax, %r15
movq %rax, %rdi
movq %rbx, %rsi
callq strcpy
movq %rbx, %rdi
callq strlen
movq %rax, %r12
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _Z11xor_encryptPcS_m
movq %r15, %rdi
movq %r14, %rsi
movq %r12, %rdx
callq _Z11xor_encryptPcS_m
movq %rbx, %rdi
movq %r15, %rsi
callq strcmp
xorl %ecx, %ecx
testl %eax, %eax
sete %cl
movl %ecx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_3:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rcx
movl $.L.str.15, %edi
movl $35, %esi
jmp .LBB2_4
.LBB2_5:
movq stderr(%rip), %rcx
movl $.L.str.16, %edi
movl $32, %esi
.LBB2_4:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z8xor_testPcS_, .Lfunc_end2-_Z8xor_testPcS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq 8(%rsi), %rdi
movq 16(%rsi), %rsi
callq _Z8xor_testPcS_
testl %eax, %eax
movl $.L.str.19, %eax
movl $.L.str.18, %esi
cmoveq %rax, %rsi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cuda_xorPcS_im, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cuda_xorPcS_im,@object # @_Z8cuda_xorPcS_im
.section .rodata,"a",@progbits
.globl _Z8cuda_xorPcS_im
.p2align 3, 0x0
_Z8cuda_xorPcS_im:
.quad _Z23__device_stub__cuda_xorPcS_im
.size _Z8cuda_xorPcS_im, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Falha ao alocar string do device (mensagem) (error code %s)!\n"
.size .L.str, 62
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Falha ao alocar string do device (chave) (error code %s)!\n"
.size .L.str.1, 59
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Falha ao copiar string mensagem do host para o device (error code %s)!\n"
.size .L.str.3, 72
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Falha ao copiar string chave do host para o device (error code %s)!\n"
.size .L.str.5, 69
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA kernel executando com %d blocos de %d threads\n"
.size .L.str.6, 52
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Erro ao rodar XOR kernel (error code %s)!\n"
.size .L.str.7, 43
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Erro ao copiar mensagem do device pro host (error code %s)!\n"
.size .L.str.9, 61
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Erro ao liberar mensagem do device (error code %s)!\n"
.size .L.str.10, 53
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Erro ao liberar chave do device (error code %s )!\n"
.size .L.str.11, 51
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Erro ao resetar o device! error=%s\n"
.size .L.str.12, 36
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "r"
.size .L.str.14, 2
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Erro ao abrir arquivo da mensagem!\n"
.size .L.str.15, 36
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Erro ao abrir arquivo da chave!\n"
.size .L.str.16, 33
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "CUDA XOR tests: %s\n"
.size .L.str.17, 20
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "SUCCEEDED"
.size .L.str.18, 10
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "FAILED"
.size .L.str.19, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8cuda_xorPcS_im"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Copiando mensagem do host para o device"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Copiando chave do host para o device"
.size .Lstr.1, 37
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Copiando saida do device para o host"
.size .Lstr.2, 37
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone"
.size .Lstr.3, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cuda_xorPcS_im
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cuda_xorPcS_im
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <algorithm>
#include <cassert>
#include <iostream>
#include <random>
#include <vector>
#include <cuda.h>
using std::cout;
using std::endl;
int constexpr kN = 1000;
std::mt19937_64 rand_engine;
void cudaCheckSuccess(cudaError_t const cuda_status, std::string const& message)
{
if(cudaSuccess != cuda_status) {
std::cout << "CUDA ERROR " << cuda_status << ": " << message << std::endl;
std::cout << "- " << cudaGetErrorName(cuda_status) << ": " << cudaGetErrorString(cuda_status) << std::endl;
}
}
__constant__ float filter_gpu[9];
__global__ void modulate(float *data, int N)
{
int const tid = blockDim.x * blockIdx.x + threadIdx.x;
if(tid < N) {
data[tid] *= filter_gpu[tid % 9];
}
}
int main(void)
{
std::vector<float> v(kN);
std::uniform_real_distribution<float> rand_gen(0.0, 1.0);
std::generate(v.begin(), v.end(), [&](){ return rand_gen(rand_engine); });
float *gpu_v;
cudaError_t cuda_status = cudaMalloc((void**) &gpu_v, kN * sizeof(float));
cudaCheckSuccess(cuda_status, "Unable to cudaMalloc");
cuda_status = cudaMemcpy((void*) gpu_v, (const void*) v.data(), kN * sizeof(float), cudaMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to memcpy into GPU");
std::vector<float> filter(9);
std::iota(filter.begin(), filter.end(), 1.0);
cuda_status = cudaMemcpyToSymbol(filter_gpu, (const void*) filter.data(), 9 * sizeof(float), 0, cudaMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to cudaMemcpyToSymbol");
modulate<<<(v.size() + 99 ) / 100, 100>>>(gpu_v, kN);
cuda_status = cudaGetLastError();
cudaCheckSuccess(cuda_status, "Unable to launch kernel");
std::vector<float> v2(v.size(), 0.0f);
cuda_status = cudaMemcpy((void*) v2.data(), (const void*) gpu_v, kN * sizeof(float), cudaMemcpyDeviceToHost);
cudaCheckSuccess(cuda_status, "Unable to copy data out of GPU");
std::vector<float> v3(v.size(), 0.0f);
for(int i = 0; i < v.size(); ++i) {
v3[i] = filter[i % filter.size()] * v[i];
}
assert(v2 == v3 && "FAIL");
return 0;
} | code for sm_80
Function : _Z8modulatePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.HI R4, R0, 0x38e38e39, RZ ; /* 0x38e38e3900047827 */
/* 0x000fca00078e02ff */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fc80000011404 */
/*00c0*/ LEA.HI R5, R4, R5, RZ, 0x1 ; /* 0x0000000504057211 */
/* 0x000fca00078f08ff */
/*00d0*/ IMAD R5, R5, -0x9, R0 ; /* 0xfffffff705057824 */
/* 0x000fca00078e0200 */
/*00e0*/ SHF.L.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057819 */
/* 0x000fcc00000006ff */
/*00f0*/ LDC R5, c[0x3][R5] ; /* 0x00c0000005057b82 */
/* 0x000ea40000000800 */
/*0100*/ FMUL R7, R6, R5 ; /* 0x0000000506077220 */
/* 0x004fca0000400000 */
/*0110*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <algorithm>
#include <cassert>
#include <iostream>
#include <random>
#include <vector>
#include <cuda.h>
using std::cout;
using std::endl;
int constexpr kN = 1000;
std::mt19937_64 rand_engine;
void cudaCheckSuccess(cudaError_t const cuda_status, std::string const& message)
{
if(cudaSuccess != cuda_status) {
std::cout << "CUDA ERROR " << cuda_status << ": " << message << std::endl;
std::cout << "- " << cudaGetErrorName(cuda_status) << ": " << cudaGetErrorString(cuda_status) << std::endl;
}
}
__constant__ float filter_gpu[9];
__global__ void modulate(float *data, int N)
{
int const tid = blockDim.x * blockIdx.x + threadIdx.x;
if(tid < N) {
data[tid] *= filter_gpu[tid % 9];
}
}
int main(void)
{
std::vector<float> v(kN);
std::uniform_real_distribution<float> rand_gen(0.0, 1.0);
std::generate(v.begin(), v.end(), [&](){ return rand_gen(rand_engine); });
float *gpu_v;
cudaError_t cuda_status = cudaMalloc((void**) &gpu_v, kN * sizeof(float));
cudaCheckSuccess(cuda_status, "Unable to cudaMalloc");
cuda_status = cudaMemcpy((void*) gpu_v, (const void*) v.data(), kN * sizeof(float), cudaMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to memcpy into GPU");
std::vector<float> filter(9);
std::iota(filter.begin(), filter.end(), 1.0);
cuda_status = cudaMemcpyToSymbol(filter_gpu, (const void*) filter.data(), 9 * sizeof(float), 0, cudaMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to cudaMemcpyToSymbol");
modulate<<<(v.size() + 99 ) / 100, 100>>>(gpu_v, kN);
cuda_status = cudaGetLastError();
cudaCheckSuccess(cuda_status, "Unable to launch kernel");
std::vector<float> v2(v.size(), 0.0f);
cuda_status = cudaMemcpy((void*) v2.data(), (const void*) gpu_v, kN * sizeof(float), cudaMemcpyDeviceToHost);
cudaCheckSuccess(cuda_status, "Unable to copy data out of GPU");
std::vector<float> v3(v.size(), 0.0f);
for(int i = 0; i < v.size(); ++i) {
v3[i] = filter[i % filter.size()] * v[i];
}
assert(v2 == v3 && "FAIL");
return 0;
} | .file "tmpxft_00105dd6_00000000-6_constant_mem_array_modulation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4975:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4975:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA ERROR "
.LC1:
.string ": "
.LC2:
.string "- "
.text
.globl _Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB4970:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L19
ret
.L19:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
movq %rsi, %rbp
movl $11, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L20
cmpb $0, 56(%r12)
je .L6
movzbl 67(%r12), %esi
.L7:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $2, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorName@PLT
movq %rax, %rbp
testq %rax, %rax
je .L21
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L9:
movl $2, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L22
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L23
cmpb $0, 56(%rbx)
je .L13
movzbl 67(%rbx), %esi
.L14:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L6:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L7
.L21:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L9
.L22:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L11
.L23:
call _ZSt16__throw_bad_castv@PLT
.L13:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L14
.cfi_endproc
.LFE4970:
.size _Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.globl _Z28__device_stub__Z8modulatePfiPfi
.type _Z28__device_stub__Z8modulatePfiPfi, @function
_Z28__device_stub__Z8modulatePfiPfi:
.LFB4997:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8modulatePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4997:
.size _Z28__device_stub__Z8modulatePfiPfi, .-_Z28__device_stub__Z8modulatePfiPfi
.globl _Z8modulatePfi
.type _Z8modulatePfi, @function
_Z8modulatePfi:
.LFB4998:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8modulatePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4998:
.size _Z8modulatePfi, .-_Z8modulatePfi
.section .rodata.str1.1
.LC3:
.string "_Z8modulatePfi"
.LC4:
.string "filter_gpu"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5000:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8modulatePfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10filter_gpu(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5000:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB5301:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L43
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L44
cmpq $1, %rax
jne .L39
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L40:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L46
leaq .LC5(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L46:
call __stack_chk_fail@PLT
.L44:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L38:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L40
.L39:
testq %rax, %rax
je .L40
jmp .L38
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5301:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB5333:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L50
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L50:
ret
.cfi_endproc
.LFE5333:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKfRKS0_,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.type _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, @function
_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_:
.LFB5347:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $61, %rax
jne .L61
movq %rdi, %rbx
movq %rdx, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L55
leaq 0(,%rsi,4), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movss 0(%rbp), %xmm0
.L56:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L56
.L57:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
leaq .LC6(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L55:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
jmp .L57
.cfi_endproc
.LFE5347:
.size _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.weak _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.set _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv:
.LFB5779:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1248(%rdi), %r9
movq %rdi, %rcx
movabsq $-5403634167711393303, %r8
.L64:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 1248(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L64
leaq 1240(%rdi), %r8
movabsq $-5403634167711393303, %rsi
.L66:
movq 1248(%rdx), %rax
andq $-2147483648, %rax
movq 1256(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1248(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L66
movq 2488(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 1240(%rdi), %rdx
andl $1, %eax
movabsq $-5403634167711393303, %rcx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 2488(%rdi)
movq $0, 2496(%rdi)
ret
.cfi_endproc
.LFE5779:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.section .rodata.str1.1
.LC12:
.string "Unable to cudaMalloc"
.LC13:
.string "Unable to memcpy into GPU"
.LC14:
.string "Unable to cudaMemcpyToSymbol"
.LC15:
.string "Unable to launch kernel"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "Unable to copy data out of GPU"
.text
.globl main
.type main, @function
main:
.LFB4971:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4971
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $200, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl $4000, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
movq %rax, 16(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 32(%rsp)
movl $0x00000000, (%rax)
leaq 4(%rax), %rax
.L71:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L71
movq %rdx, 24(%rsp)
movq %r12, %rbp
leaq 4000(%r12), %r13
leaq rand_engine(%rip), %rbx
jmp .L72
.L109:
movq %rbx, %rdi
call _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
jmp .L78
.L73:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
.L74:
pxor %xmm3, %xmm3
addss %xmm3, %xmm0
mulss .LC10(%rip), %xmm0
comiss .LC11(%rip), %xmm0
jnb .L108
.L75:
pxor %xmm4, %xmm4
addss %xmm4, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %rbp, %r13
je .L76
.L72:
cmpq $311, 2496(%rbx)
ja .L109
.L78:
movq 2496(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 2496(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $29, %rdx
movabsq $6148914691236517205, %rcx
andq %rcx, %rdx
xorq %rdx, %rax
movq %rax, %rdx
salq $17, %rdx
movabsq $8202884508482404352, %rcx
andq %rcx, %rdx
xorq %rdx, %rax
movq %rax, %rdx
salq $37, %rdx
movabsq $-2270628950310912, %rcx
andq %rcx, %rdx
xorq %rdx, %rax
movq %rax, %rdx
shrq $43, %rdx
xorq %rdx, %rax
js .L73
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
jmp .L74
.L108:
movss .LC7(%rip), %xmm0
jmp .L75
.L76:
leaq 8(%rsp), %rdi
movl $4000, %esi
.LEHB1:
call cudaMalloc@PLT
movl %eax, %ebx
leaq 112(%rsp), %rdx
leaq 144(%rsp), %rdi
leaq .LC12(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE1:
leaq 144(%rsp), %rsi
movl %ebx, %edi
.LEHB2:
call _Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE2:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, %ecx
movl $4000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
.LEHB3:
call cudaMemcpy@PLT
movl %eax, %ebx
leaq 112(%rsp), %rdx
leaq 144(%rsp), %rdi
leaq .LC13(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE3:
leaq 144(%rsp), %rsi
movl %ebx, %edi
.LEHB4:
call _Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE4:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movl $36, %edi
.LEHB5:
call _Znwm@PLT
.LEHE5:
movq %rax, %rbx
movq %rax, 48(%rsp)
leaq 36(%rax), %rdx
movq %rdx, 64(%rsp)
movl $0x00000000, (%rax)
leaq 4(%rax), %rax
.L79:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L79
movq %rdx, 56(%rsp)
movq %rbx, %rax
leaq 36(%rbx), %rdx
movsd .LC8(%rip), %xmm0
movapd %xmm0, %xmm2
.L80:
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movss %xmm1, (%rax)
addsd %xmm2, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L80
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
movq %rbx, %rsi
leaq _ZL10filter_gpu(%rip), %rdi
.LEHB6:
call cudaMemcpyToSymbol@PLT
movl %eax, %ebp
leaq 112(%rsp), %rdx
leaq 144(%rsp), %rdi
leaq .LC14(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
leaq 144(%rsp), %rsi
movl %ebp, %edi
.LEHB7:
call _Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE7:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $100, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $10, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
.LEHB8:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L81
movl $1000, %esi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z8modulatePfiPfi
.L81:
call cudaGetLastError@PLT
movl %eax, %ebp
leaq 112(%rsp), %rdx
leaq 144(%rsp), %rdi
leaq .LC15(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE8:
leaq 144(%rsp), %rsi
movl %ebp, %edi
.LEHB9:
call _Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE9:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0x00000000, 112(%rsp)
leaq 4(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 80(%rsp), %rdi
movl $1000, %esi
.LEHB10:
call _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE10:
movl $2, %ecx
movl $4000, %edx
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi
.LEHB11:
call cudaMemcpy@PLT
movl %eax, %ebp
leaq 112(%rsp), %rdx
leaq 144(%rsp), %rdi
leaq .LC16(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE11:
leaq 144(%rsp), %rsi
movl %ebp, %edi
.LEHB12:
call _Z16cudaCheckSuccess9cudaErrorRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE12:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0x00000000, 4(%rsp)
leaq 3(%rsp), %rcx
leaq 4(%rsp), %rdx
leaq 112(%rsp), %rdi
movl $1000, %esi
.LEHB13:
call _ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE13:
movq 112(%rsp), %rdi
movl $0, %ecx
movabsq $-2049638230412172401, %rsi
.L82:
movq %rcx, %rax
mulq %rsi
movq %rdx, %rax
shrq $3, %rax
andq $-8, %rdx
addq %rax, %rdx
movq %rcx, %rax
subq %rdx, %rax
movss (%rbx,%rax,4), %xmm0
mulss (%r12,%rcx,4), %xmm0
movss %xmm0, (%rdi,%rcx,4)
addq $1, %rcx
cmpq $1000, %rcx
jne .L82
leaq 112(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 16(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L110
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L84:
leaq 16(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 184(%rsp), %rax
subq %fs:40, %rax
je .L91
call __stack_chk_fail@PLT
.L96:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L84
.L98:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L87:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L84
.L99:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L87
.L101:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L90:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L87
.L100:
endbr64
movq %rax, %rbx
jmp .L90
.L97:
endbr64
movq %rax, %rbx
jmp .L87
.L94:
endbr64
movq %rax, %rbx
jmp .L84
.L91:
movq %rbx, %rdi
.LEHB14:
call _Unwind_Resume@PLT
.LEHE14:
.L110:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4971:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4971:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4971-.LLSDACSB4971
.LLSDACSB4971:
.uleb128 .LEHB0-.LFB4971
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4971
.uleb128 .LEHE1-.LEHB1
.uleb128 .L94-.LFB4971
.uleb128 0
.uleb128 .LEHB2-.LFB4971
.uleb128 .LEHE2-.LEHB2
.uleb128 .L95-.LFB4971
.uleb128 0
.uleb128 .LEHB3-.LFB4971
.uleb128 .LEHE3-.LEHB3
.uleb128 .L94-.LFB4971
.uleb128 0
.uleb128 .LEHB4-.LFB4971
.uleb128 .LEHE4-.LEHB4
.uleb128 .L96-.LFB4971
.uleb128 0
.uleb128 .LEHB5-.LFB4971
.uleb128 .LEHE5-.LEHB5
.uleb128 .L94-.LFB4971
.uleb128 0
.uleb128 .LEHB6-.LFB4971
.uleb128 .LEHE6-.LEHB6
.uleb128 .L97-.LFB4971
.uleb128 0
.uleb128 .LEHB7-.LFB4971
.uleb128 .LEHE7-.LEHB7
.uleb128 .L98-.LFB4971
.uleb128 0
.uleb128 .LEHB8-.LFB4971
.uleb128 .LEHE8-.LEHB8
.uleb128 .L97-.LFB4971
.uleb128 0
.uleb128 .LEHB9-.LFB4971
.uleb128 .LEHE9-.LEHB9
.uleb128 .L99-.LFB4971
.uleb128 0
.uleb128 .LEHB10-.LFB4971
.uleb128 .LEHE10-.LEHB10
.uleb128 .L97-.LFB4971
.uleb128 0
.uleb128 .LEHB11-.LFB4971
.uleb128 .LEHE11-.LEHB11
.uleb128 .L100-.LFB4971
.uleb128 0
.uleb128 .LEHB12-.LFB4971
.uleb128 .LEHE12-.LEHB12
.uleb128 .L101-.LFB4971
.uleb128 0
.uleb128 .LEHB13-.LFB4971
.uleb128 .LEHE13-.LEHB13
.uleb128 .L100-.LFB4971
.uleb128 0
.uleb128 .LEHB14-.LFB4971
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.LLSDACSE4971:
.text
.size main, .-main
.type _GLOBAL__sub_I_rand_engine, @function
_GLOBAL__sub_I_rand_engine:
.LFB5789:
.cfi_startproc
endbr64
movq $5489, rand_engine(%rip)
movl $1, %ecx
leaq -8+rand_engine(%rip), %r10
movabsq $6364136223846793005, %r9
leaq 8(%r10), %r8
movabsq $945986875574848801, %rdi
.L112:
movq (%r10,%rcx,8), %rax
movq %rax, %rdx
shrq $62, %rdx
xorq %rdx, %rax
imulq %r9, %rax
movq %rax, %rsi
movq %rcx, %rdx
shrq $3, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $312, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addq %rsi, %rax
movq %rax, (%r8,%rcx,8)
addq $1, %rcx
cmpq $312, %rcx
jne .L112
movq $312, 2496+rand_engine(%rip)
ret
.cfi_endproc
.LFE5789:
.size _GLOBAL__sub_I_rand_engine, .-_GLOBAL__sub_I_rand_engine
.section .init_array
.align 8
.quad _GLOBAL__sub_I_rand_engine
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10filter_gpu
.comm _ZL10filter_gpu,36,32
.globl rand_engine
.bss
.align 32
.type rand_engine, @object
.size rand_engine, 2504
rand_engine:
.zero 2504
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1065353215
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1072693248
.section .rodata.cst4
.align 4
.LC10:
.long 528482304
.align 4
.LC11:
.long 1065353216
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <algorithm>
#include <cassert>
#include <iostream>
#include <random>
#include <vector>
#include <cuda.h>
using std::cout;
using std::endl;
int constexpr kN = 1000;
std::mt19937_64 rand_engine;
void cudaCheckSuccess(cudaError_t const cuda_status, std::string const& message)
{
if(cudaSuccess != cuda_status) {
std::cout << "CUDA ERROR " << cuda_status << ": " << message << std::endl;
std::cout << "- " << cudaGetErrorName(cuda_status) << ": " << cudaGetErrorString(cuda_status) << std::endl;
}
}
__constant__ float filter_gpu[9];
__global__ void modulate(float *data, int N)
{
int const tid = blockDim.x * blockIdx.x + threadIdx.x;
if(tid < N) {
data[tid] *= filter_gpu[tid % 9];
}
}
int main(void)
{
std::vector<float> v(kN);
std::uniform_real_distribution<float> rand_gen(0.0, 1.0);
std::generate(v.begin(), v.end(), [&](){ return rand_gen(rand_engine); });
float *gpu_v;
cudaError_t cuda_status = cudaMalloc((void**) &gpu_v, kN * sizeof(float));
cudaCheckSuccess(cuda_status, "Unable to cudaMalloc");
cuda_status = cudaMemcpy((void*) gpu_v, (const void*) v.data(), kN * sizeof(float), cudaMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to memcpy into GPU");
std::vector<float> filter(9);
std::iota(filter.begin(), filter.end(), 1.0);
cuda_status = cudaMemcpyToSymbol(filter_gpu, (const void*) filter.data(), 9 * sizeof(float), 0, cudaMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to cudaMemcpyToSymbol");
modulate<<<(v.size() + 99 ) / 100, 100>>>(gpu_v, kN);
cuda_status = cudaGetLastError();
cudaCheckSuccess(cuda_status, "Unable to launch kernel");
std::vector<float> v2(v.size(), 0.0f);
cuda_status = cudaMemcpy((void*) v2.data(), (const void*) gpu_v, kN * sizeof(float), cudaMemcpyDeviceToHost);
cudaCheckSuccess(cuda_status, "Unable to copy data out of GPU");
std::vector<float> v3(v.size(), 0.0f);
for(int i = 0; i < v.size(); ++i) {
v3[i] = filter[i % filter.size()] * v[i];
}
assert(v2 == v3 && "FAIL");
return 0;
} | #include <algorithm>
#include <cassert>
#include <iostream>
#include <random>
#include <vector>
#include <hip/hip_runtime.h>
using std::cout;
using std::endl;
int constexpr kN = 1000;
std::mt19937_64 rand_engine;
void cudaCheckSuccess(hipError_t const cuda_status, std::string const& message)
{
if(hipSuccess != cuda_status) {
std::cout << "CUDA ERROR " << cuda_status << ": " << message << std::endl;
std::cout << "- " << hipGetErrorName(cuda_status) << ": " << hipGetErrorString(cuda_status) << std::endl;
}
}
__constant__ float filter_gpu[9];
__global__ void modulate(float *data, int N)
{
int const tid = blockDim.x * blockIdx.x + threadIdx.x;
if(tid < N) {
data[tid] *= filter_gpu[tid % 9];
}
}
int main(void)
{
std::vector<float> v(kN);
std::uniform_real_distribution<float> rand_gen(0.0, 1.0);
std::generate(v.begin(), v.end(), [&](){ return rand_gen(rand_engine); });
float *gpu_v;
hipError_t cuda_status = hipMalloc((void**) &gpu_v, kN * sizeof(float));
cudaCheckSuccess(cuda_status, "Unable to hipMalloc");
cuda_status = hipMemcpy((void*) gpu_v, (const void*) v.data(), kN * sizeof(float), hipMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to memcpy into GPU");
std::vector<float> filter(9);
std::iota(filter.begin(), filter.end(), 1.0);
cuda_status = hipMemcpyToSymbol(HIP_SYMBOL(filter_gpu), (const void*) filter.data(), 9 * sizeof(float), 0, hipMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to hipMemcpyToSymbol");
modulate<<<(v.size() + 99 ) / 100, 100>>>(gpu_v, kN);
cuda_status = hipGetLastError();
cudaCheckSuccess(cuda_status, "Unable to launch kernel");
std::vector<float> v2(v.size(), 0.0f);
cuda_status = hipMemcpy((void*) v2.data(), (const void*) gpu_v, kN * sizeof(float), hipMemcpyDeviceToHost);
cudaCheckSuccess(cuda_status, "Unable to copy data out of GPU");
std::vector<float> v3(v.size(), 0.0f);
for(int i = 0; i < v.size(); ++i) {
v3[i] = filter[i % filter.size()] * v[i];
}
assert(v2 == v3 && "FAIL");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <algorithm>
#include <cassert>
#include <iostream>
#include <random>
#include <vector>
#include <hip/hip_runtime.h>
using std::cout;
using std::endl;
int constexpr kN = 1000;
std::mt19937_64 rand_engine;
void cudaCheckSuccess(hipError_t const cuda_status, std::string const& message)
{
if(hipSuccess != cuda_status) {
std::cout << "CUDA ERROR " << cuda_status << ": " << message << std::endl;
std::cout << "- " << hipGetErrorName(cuda_status) << ": " << hipGetErrorString(cuda_status) << std::endl;
}
}
__constant__ float filter_gpu[9];
__global__ void modulate(float *data, int N)
{
int const tid = blockDim.x * blockIdx.x + threadIdx.x;
if(tid < N) {
data[tid] *= filter_gpu[tid % 9];
}
}
int main(void)
{
std::vector<float> v(kN);
std::uniform_real_distribution<float> rand_gen(0.0, 1.0);
std::generate(v.begin(), v.end(), [&](){ return rand_gen(rand_engine); });
float *gpu_v;
hipError_t cuda_status = hipMalloc((void**) &gpu_v, kN * sizeof(float));
cudaCheckSuccess(cuda_status, "Unable to hipMalloc");
cuda_status = hipMemcpy((void*) gpu_v, (const void*) v.data(), kN * sizeof(float), hipMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to memcpy into GPU");
std::vector<float> filter(9);
std::iota(filter.begin(), filter.end(), 1.0);
cuda_status = hipMemcpyToSymbol(HIP_SYMBOL(filter_gpu), (const void*) filter.data(), 9 * sizeof(float), 0, hipMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to hipMemcpyToSymbol");
modulate<<<(v.size() + 99 ) / 100, 100>>>(gpu_v, kN);
cuda_status = hipGetLastError();
cudaCheckSuccess(cuda_status, "Unable to launch kernel");
std::vector<float> v2(v.size(), 0.0f);
cuda_status = hipMemcpy((void*) v2.data(), (const void*) gpu_v, kN * sizeof(float), hipMemcpyDeviceToHost);
cudaCheckSuccess(cuda_status, "Unable to copy data out of GPU");
std::vector<float> v3(v.size(), 0.0f);
for(int i = 0; i < v.size(); ++i) {
v3[i] = filter[i % filter.size()] * v[i];
}
assert(v2 == v3 && "FAIL");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8modulatePfi
.globl _Z8modulatePfi
.p2align 8
.type _Z8modulatePfi,@function
_Z8modulatePfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_mul_hi_i32 v0, v1, 0x38e38e39
s_load_b64 s[0:1], s[0:1], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, filter_gpu@rel32@lo+4
s_addc_u32 s3, s3, filter_gpu@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 1, v0
v_add_nc_u32_e32 v0, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 3, v0
v_sub_nc_u32_e32 v3, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, v3, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8modulatePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8modulatePfi, .Lfunc_end0-_Z8modulatePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected filter_gpu
.type filter_gpu,@object
.section .bss,"aw",@nobits
.globl filter_gpu
.p2align 4, 0x0
filter_gpu:
.zero 36
.size filter_gpu, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym filter_gpu
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8modulatePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8modulatePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <algorithm>
#include <cassert>
#include <iostream>
#include <random>
#include <vector>
#include <hip/hip_runtime.h>
using std::cout;
using std::endl;
int constexpr kN = 1000;
std::mt19937_64 rand_engine;
void cudaCheckSuccess(hipError_t const cuda_status, std::string const& message)
{
if(hipSuccess != cuda_status) {
std::cout << "CUDA ERROR " << cuda_status << ": " << message << std::endl;
std::cout << "- " << hipGetErrorName(cuda_status) << ": " << hipGetErrorString(cuda_status) << std::endl;
}
}
__constant__ float filter_gpu[9];
__global__ void modulate(float *data, int N)
{
int const tid = blockDim.x * blockIdx.x + threadIdx.x;
if(tid < N) {
data[tid] *= filter_gpu[tid % 9];
}
}
int main(void)
{
std::vector<float> v(kN);
std::uniform_real_distribution<float> rand_gen(0.0, 1.0);
std::generate(v.begin(), v.end(), [&](){ return rand_gen(rand_engine); });
float *gpu_v;
hipError_t cuda_status = hipMalloc((void**) &gpu_v, kN * sizeof(float));
cudaCheckSuccess(cuda_status, "Unable to hipMalloc");
cuda_status = hipMemcpy((void*) gpu_v, (const void*) v.data(), kN * sizeof(float), hipMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to memcpy into GPU");
std::vector<float> filter(9);
std::iota(filter.begin(), filter.end(), 1.0);
cuda_status = hipMemcpyToSymbol(HIP_SYMBOL(filter_gpu), (const void*) filter.data(), 9 * sizeof(float), 0, hipMemcpyHostToDevice);
cudaCheckSuccess(cuda_status, "Unable to hipMemcpyToSymbol");
modulate<<<(v.size() + 99 ) / 100, 100>>>(gpu_v, kN);
cuda_status = hipGetLastError();
cudaCheckSuccess(cuda_status, "Unable to launch kernel");
std::vector<float> v2(v.size(), 0.0f);
cuda_status = hipMemcpy((void*) v2.data(), (const void*) gpu_v, kN * sizeof(float), hipMemcpyDeviceToHost);
cudaCheckSuccess(cuda_status, "Unable to copy data out of GPU");
std::vector<float> v3(v.size(), 0.0f);
for(int i = 0; i < v.size(); ++i) {
v3[i] = filter[i % filter.size()] * v[i];
}
assert(v2 == v3 && "FAIL");
return 0;
} | .text
.file "constant_mem_array_modulation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %edi, %edi
je .LBB0_16
# %bb.1:
movq %rsi, %r14
movl %edi, %ebx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rsi
movq 8(%r14), %rdx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_17
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_4
# %bb.3:
movzbl 67(%r14), %ecx
jmp .LBB0_5
.LBB0_16:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_4:
.cfi_def_cfa_offset 32
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorName
testq %rax, %rax
je .LBB0_6
# %bb.7:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_8
.LBB0_6:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB0_9
# %bb.10:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_11
.LBB0_9:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_11: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit5
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB0_14
# %bb.13:
movzbl 67(%rbx), %eax
jmp .LBB0_15
.LBB0_14:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB0_17:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end0-_Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
# -- End function
.globl _Z23__device_stub__modulatePfi # -- Begin function _Z23__device_stub__modulatePfi
.p2align 4, 0x90
.type _Z23__device_stub__modulatePfi,@function
_Z23__device_stub__modulatePfi: # @_Z23__device_stub__modulatePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8modulatePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__modulatePfi, .Lfunc_end1-_Z23__device_stub__modulatePfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x5f800000 # float 1.84467441E+19
.LCPI2_1:
.long 0x40000000 # float 2
.LCPI2_2:
.long 0x5f000000 # float 9.22337203E+18
.LCPI2_3:
.long 0x3f800000 # float 1
.LCPI2_5:
.long 0x00000000 # float 0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_4:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000, %edi # imm = 0xFA0
callq _Znwm
movq %rax, %rbx
xorl %r15d, %r15d
movl $4000, %edx # imm = 0xFA0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
flds .LCPI2_0(%rip)
fstpt (%rsp)
callq logl
fstpt 76(%rsp) # 10-byte Folded Spill
flds .LCPI2_1(%rip)
fstpt (%rsp)
callq logl
fldt 76(%rsp) # 10-byte Folded Reload
fdivp %st, %st(1)
flds .LCPI2_2(%rip)
xorl %ecx, %ecx
fxch %st(1)
fucomi %st(1), %st
fldz
fcmovnb %st(2), %st
fstp %st(2)
fsubp %st, %st(1)
setae %cl
fnstcw 30(%rsp)
movzwl 30(%rsp), %eax
orl $3072, %eax # imm = 0xC00
movw %ax, 74(%rsp)
fldcw 74(%rsp)
fistpll 104(%rsp)
fldcw 30(%rsp)
shlq $63, %rcx
xorq 104(%rsp), %rcx
leaq 23(%rcx), %rax
xorl %edx, %edx
divq %rcx
movq %rax, %r14
cmpq $1, %rax
adcq $0, %r14
movss .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 68(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
movss %xmm0, 76(%rsp) # 4-byte Spill
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_2: # %.noexc
# in Loop: Header=BB2_4 Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
.LBB2_3: # %.noexc
# in Loop: Header=BB2_4 Depth=2
movss 68(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
movss 76(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, 76(%rsp) # 4-byte Spill
mulss .LCPI2_0(%rip), %xmm2
movss %xmm2, 68(%rsp) # 4-byte Spill
decq %r14
je .LBB2_7
.LBB2_4: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp0:
movl $rand_engine, %edi
callq _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.Ltmp1:
# %bb.5: # %.noexc
# in Loop: Header=BB2_4 Depth=2
testq %rax, %rax
jns .LBB2_2
# %bb.6: # in Loop: Header=BB2_4 Depth=2
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
movss 76(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 68(%rsp), %xmm0 # 4-byte Folded Reload
ucomiss .LCPI2_3(%rip), %xmm0
jae .LBB2_9
.LBB2_8: # %_ZZ4mainENKUlvE_clEv.exit.i
# in Loop: Header=BB2_1 Depth=1
addss .LCPI2_5(%rip), %xmm0
movss %xmm0, (%rbx,%r15)
addq $4, %r15
cmpq $4000, %r15 # imm = 0xFA0
jne .LBB2_1
jmp .LBB2_10
.LBB2_9: # in Loop: Header=BB2_1 Depth=1
xorps %xmm1, %xmm1
movss .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq nextafterf
jmp .LBB2_8
.LBB2_10: # %_ZSt8generateIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEEZ4mainEUlvE_EvT_S8_T0_.exit
.Ltmp3:
leaq 88(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.Ltmp4:
# %bb.11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
movl %eax, %ebp
leaq 48(%rsp), %r13
movq %r13, 32(%rsp)
.Ltmp5:
movl $20, %edi
callq _Znwm
.Ltmp6:
# %bb.12: # %.noexc52
movq %rax, 32(%rsp)
movq $19, 48(%rsp)
movups .L.str.3(%rip), %xmm0
movups %xmm0, (%rax)
movl $1668246636, 15(%rax) # imm = 0x636F6C6C
movq $19, 40(%rsp)
movb $0, 19(%rax)
.Ltmp8:
leaq 32(%rsp), %rsi
movl %ebp, %edi
callq _Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp9:
# %bb.13:
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_15
# %bb.14: # %.critedge.i.i
callq _ZdlPv
.LBB2_15: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 88(%rsp), %rdi
.Ltmp11:
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp12:
# %bb.16: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i53
movl %eax, %ebp
movq %r13, 32(%rsp)
.Ltmp14:
movl $26, %edi
callq _Znwm
.Ltmp15:
# %bb.17: # %.noexc58
movq %rax, 32(%rsp)
movq $25, 48(%rsp)
movups .L.str.4+9(%rip), %xmm0
movups %xmm0, 9(%rax)
movups .L.str.4(%rip), %xmm0
movups %xmm0, (%rax)
movq $25, 40(%rsp)
movb $0, 25(%rax)
.Ltmp17:
leaq 32(%rsp), %rsi
movl %ebp, %edi
callq _Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp18:
# %bb.18:
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_20
# %bb.19: # %.critedge.i.i60
callq _ZdlPv
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit62
.Ltmp20:
movl $36, %edi
callq _Znwm
.Ltmp21:
# %bb.21: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit64
movq %rax, %r14
xorps %xmm0, %xmm0
movups %xmm0, 16(%rax)
movups %xmm0, (%rax)
movl $0, 32(%rax)
movsd .LCPI2_4(%rip), %xmm0 # xmm0 = mem[0],zero
xorl %eax, %eax
movaps %xmm0, %xmm1
.p2align 4, 0x90
.LBB2_22: # %.lr.ph.i65
# =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
movss %xmm2, (%r14,%rax)
addsd %xmm0, %xmm1
addq $4, %rax
cmpq $36, %rax
jne .LBB2_22
# %bb.23: # %_ZSt4iotaIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEEdEvT_S7_T0_.exit
.Ltmp23:
movl $filter_gpu, %edi
movl $36, %edx
movq %r14, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
.Ltmp24:
# %bb.24: # %_Z17hipMemcpyToSymbolIA9_fE10hipError_tRKT_PKvmm13hipMemcpyKind.exit
movl %eax, %ebp
movq %r13, 32(%rsp)
.Ltmp25:
movl $28, %edi
callq _Znwm
.Ltmp26:
# %bb.25: # %.noexc72
movq %rax, 32(%rsp)
movq $27, 48(%rsp)
movups .L.str.5+11(%rip), %xmm0
movups %xmm0, 11(%rax)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movq $27, 40(%rsp)
movb $0, 27(%rax)
.Ltmp28:
leaq 32(%rsp), %rsi
movl %ebp, %edi
callq _Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp29:
# %bb.26:
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_28
# %bb.27: # %.critedge.i.i74
callq _ZdlPv
.LBB2_28: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit76
.Ltmp31:
movabsq $4294967306, %rdi # imm = 0x10000000A
movabsq $4294967396, %rdx # imm = 0x100000064
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp32:
# %bb.29:
testl %eax, %eax
jne .LBB2_32
# %bb.30:
movq 88(%rsp), %rax
movq %rax, 160(%rsp)
movl $1000, 100(%rsp) # imm = 0x3E8
leaq 160(%rsp), %rax
movq %rax, 32(%rsp)
leaq 100(%rsp), %rax
movq %rax, 40(%rsp)
.Ltmp33:
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp34:
# %bb.31: # %.noexc77
movq 120(%rsp), %rax
movq 112(%rsp), %rdi
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
.Ltmp35:
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 32(%rsp), %r9
movl $_Z8modulatePfi, %edi
callq hipLaunchKernel
.Ltmp36:
.LBB2_32:
.Ltmp37:
callq hipGetLastError
.Ltmp38:
# %bb.33: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i88
movl %eax, %ebp
movq %r13, 32(%rsp)
.Ltmp40:
movl $24, %edi
callq _Znwm
.Ltmp41:
# %bb.34: # %.noexc93
movq %rax, 32(%rsp)
movq $23, 48(%rsp)
movups .L.str.6(%rip), %xmm0
movups %xmm0, (%rax)
movabsq $7810770566350839912, %rcx # imm = 0x6C656E72656B2068
movq %rcx, 15(%rax)
movq $23, 40(%rsp)
movb $0, 23(%rax)
.Ltmp43:
leaq 32(%rsp), %rsi
movl %ebp, %edi
callq _Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp44:
# %bb.35:
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_37
# %bb.36: # %.critedge.i.i95
callq _ZdlPv
.LBB2_37: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit97
.Ltmp46:
movl $4000, %edi # imm = 0xFA0
callq _Znwm
.Ltmp47:
# %bb.38: # %.lr.ph.i.i.i.i.i.i.i.i.i.preheader
movq %rax, %r12
movl $4000, %edx # imm = 0xFA0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq 88(%rsp), %rsi
.Ltmp49:
movl $4000, %edx # imm = 0xFA0
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp50:
# %bb.39: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i100
movl %eax, %ebp
movq %r13, 32(%rsp)
.Ltmp52:
movl $31, %edi
callq _Znwm
.Ltmp53:
# %bb.40: # %.noexc105
movq %rax, 32(%rsp)
movq $30, 48(%rsp)
movups .L.str.7+14(%rip), %xmm0
movups %xmm0, 14(%rax)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movq $30, 40(%rsp)
movb $0, 30(%rax)
.Ltmp55:
leaq 32(%rsp), %rsi
movl %ebp, %edi
callq _Z16cudaCheckSuccess10hipError_tRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp56:
# %bb.41:
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_43
# %bb.42: # %.critedge.i.i107
callq _ZdlPv
.LBB2_43: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit109
movq %r12, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_44:
.cfi_def_cfa_offset 224
.Ltmp57:
movq %rax, %r15
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_49
# %bb.45: # %.critedge.i.i130
callq _ZdlPv
jmp .LBB2_49
.LBB2_46:
.Ltmp54:
jmp .LBB2_48
.LBB2_47:
.Ltmp51:
.LBB2_48:
movq %rax, %r15
.LBB2_49:
movq %r12, %rdi
jmp .LBB2_55
.LBB2_50:
.Ltmp48:
jmp .LBB2_65
.LBB2_51:
.Ltmp45:
jmp .LBB2_54
.LBB2_52:
.Ltmp42:
jmp .LBB2_65
.LBB2_53:
.Ltmp30:
.LBB2_54:
movq %rax, %r15
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_66
.LBB2_55: # %_ZNSt6vectorIfSaIfEED2Ev.exit134
callq _ZdlPv
jmp .LBB2_66
.LBB2_56:
.Ltmp27:
jmp .LBB2_65
.LBB2_57:
.Ltmp22:
jmp .LBB2_69
.LBB2_58:
.Ltmp19:
jmp .LBB2_61
.LBB2_59:
.Ltmp16:
jmp .LBB2_69
.LBB2_60:
.Ltmp10:
.LBB2_61:
movq %rax, %r15
movq 32(%rsp), %rdi
cmpq %r13, %rdi
jne .LBB2_67
jmp .LBB2_70
.LBB2_62:
.Ltmp7:
jmp .LBB2_69
.LBB2_63:
.Ltmp13:
jmp .LBB2_69
.LBB2_64:
.Ltmp39:
.LBB2_65: # %_ZNSt6vectorIfSaIfEED2Ev.exit134
movq %rax, %r15
.LBB2_66: # %_ZNSt6vectorIfSaIfEED2Ev.exit134
movq %r14, %rdi
.LBB2_67: # %_ZNSt6vectorIfSaIfEED2Ev.exit138
callq _ZdlPv
jmp .LBB2_70
.LBB2_68:
.Ltmp2:
.LBB2_69: # %_ZNSt6vectorIfSaIfEED2Ev.exit138
movq %rax, %r15
.LBB2_70: # %_ZNSt6vectorIfSaIfEED2Ev.exit138
movq %rbx, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26
.uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp38-.Ltmp31 # Call between .Ltmp31 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44
.uleb128 .Ltmp45-.Lfunc_begin0 # jumps to .Ltmp45
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp47-.Ltmp46 # Call between .Ltmp46 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp49-.Ltmp47 # Call between .Ltmp47 and .Ltmp49
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp50-.Ltmp49 # Call between .Ltmp49 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53
.uleb128 .Ltmp54-.Lfunc_begin0 # jumps to .Ltmp54
.byte 0 # On action: cleanup
.uleb128 .Ltmp55-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp56-.Ltmp55 # Call between .Ltmp55 and .Ltmp56
.uleb128 .Ltmp57-.Lfunc_begin0 # jumps to .Ltmp57
.byte 0 # On action: cleanup
.uleb128 .Ltmp56-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Lfunc_end2-.Ltmp56 # Call between .Ltmp56 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,@function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv: # @_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_startproc
# %bb.0:
cmpq $312, 2496(%rdi) # imm = 0x138
jb .LBB3_6
# %bb.1: # %.preheader.preheader
movabsq $-5403634167711393303, %rax # imm = 0xB5026F5AA96619E9
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 1248(%rdi,%rdx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $156, %rsi
jne .LBB3_2
# %bb.3: # %.preheader.i.preheader
movl $157, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB3_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1256(%rdi,%rcx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $312, %rcx # imm = 0x138
jne .LBB3_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 2488(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 1240(%rdi), %rsi
andl $1, %edx
negq %rdx
andq %rax, %rdx
xorq %rsi, %rdx
movq %rdx, 2488(%rdi)
movq $0, 2496(%rdi)
.LBB3_6:
movq 2496(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 2496(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $29, %rcx
movabsq $22906492245, %rdx # imm = 0x555555555
andq %rcx, %rdx
xorq %rax, %rdx
movq %rdx, %rax
shlq $17, %rax
movabsq $8202884508482404352, %rcx # imm = 0x71D67FFFEDA60000
andq %rax, %rcx
xorq %rdx, %rcx
movl %ecx, %edx
andl $134201207, %edx # imm = 0x7FFBF77
shlq $37, %rdx
xorq %rcx, %rdx
movq %rdx, %rax
shrq $43, %rax
xorq %rdx, %rax
retq
.Lfunc_end3:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv, .Lfunc_end3-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_constant_mem_array_modulation.hip
.type _GLOBAL__sub_I_constant_mem_array_modulation.hip,@function
_GLOBAL__sub_I_constant_mem_array_modulation.hip: # @_GLOBAL__sub_I_constant_mem_array_modulation.hip
.cfi_startproc
# %bb.0:
movq $5489, rand_engine(%rip) # imm = 0x1571
movl $1, %eax
movl $5489, %esi # imm = 0x1571
movabsq $6364136223846793005, %rcx # imm = 0x5851F42D4C957F2D
movq %rsi, %rdx
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
shrq $62, %rdx
xorq %rsi, %rdx
imulq %rcx, %rdx
addq %rax, %rdx
movq %rdx, rand_engine(,%rax,8)
incq %rax
movq %rdx, %rsi
cmpq $312, %rax # imm = 0x138
jne .LBB4_1
# %bb.2: # %__cxx_global_var_init.exit
movq $312, rand_engine+2496(%rip) # imm = 0x138
retq
.Lfunc_end4:
.size _GLOBAL__sub_I_constant_mem_array_modulation.hip, .Lfunc_end4-_GLOBAL__sub_I_constant_mem_array_modulation.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8modulatePfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $filter_gpu, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type rand_engine,@object # @rand_engine
.bss
.globl rand_engine
.p2align 3, 0x0
rand_engine:
.zero 2504
.size rand_engine, 2504
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA ERROR "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "- "
.size .L.str.2, 3
.type filter_gpu,@object # @filter_gpu
.local filter_gpu
.comm filter_gpu,36,16
.type _Z8modulatePfi,@object # @_Z8modulatePfi
.section .rodata,"a",@progbits
.globl _Z8modulatePfi
.p2align 3, 0x0
_Z8modulatePfi:
.quad _Z23__device_stub__modulatePfi
.size _Z8modulatePfi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Unable to hipMalloc"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Unable to memcpy into GPU"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Unable to hipMemcpyToSymbol"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Unable to launch kernel"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Unable to copy data out of GPU"
.size .L.str.7, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8modulatePfi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "filter_gpu"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_constant_mem_array_modulation.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__modulatePfi
.addrsig_sym __gxx_personality_v0
.addrsig_sym _GLOBAL__sub_I_constant_mem_array_modulation.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym rand_engine
.addrsig_sym _ZSt4cout
.addrsig_sym filter_gpu
.addrsig_sym _Z8modulatePfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8modulatePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.HI R4, R0, 0x38e38e39, RZ ; /* 0x38e38e3900047827 */
/* 0x000fca00078e02ff */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fc80000011404 */
/*00c0*/ LEA.HI R5, R4, R5, RZ, 0x1 ; /* 0x0000000504057211 */
/* 0x000fca00078f08ff */
/*00d0*/ IMAD R5, R5, -0x9, R0 ; /* 0xfffffff705057824 */
/* 0x000fca00078e0200 */
/*00e0*/ SHF.L.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057819 */
/* 0x000fcc00000006ff */
/*00f0*/ LDC R5, c[0x3][R5] ; /* 0x00c0000005057b82 */
/* 0x000ea40000000800 */
/*0100*/ FMUL R7, R6, R5 ; /* 0x0000000506077220 */
/* 0x004fca0000400000 */
/*0110*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8modulatePfi
.globl _Z8modulatePfi
.p2align 8
.type _Z8modulatePfi,@function
_Z8modulatePfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_mul_hi_i32 v0, v1, 0x38e38e39
s_load_b64 s[0:1], s[0:1], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, filter_gpu@rel32@lo+4
s_addc_u32 s3, s3, filter_gpu@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 1, v0
v_add_nc_u32_e32 v0, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 3, v0
v_sub_nc_u32_e32 v3, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, v3, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8modulatePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8modulatePfi, .Lfunc_end0-_Z8modulatePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected filter_gpu
.type filter_gpu,@object
.section .bss,"aw",@nobits
.globl filter_gpu
.p2align 4, 0x0
filter_gpu:
.zero 36
.size filter_gpu, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym filter_gpu
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8modulatePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8modulatePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
gridDim.x = n / blockDim.x;
gridDim.y = n / blockDim.y;
if(n % blockDim.x != 0)
gridDim.x++;
if(n % blockDim.y != 0)
gridDim.y++;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
gridDim.x = n / blockDim.x;
gridDim.y = n / blockDim.y;
if(n % blockDim.x != 0)
gridDim.x++;
if(n % blockDim.y != 0)
gridDim.y++;
} | .file "tmpxft_000ad63d_00000000-6_setGrid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7setGridiR4dim3S0_
.type _Z7setGridiR4dim3S0_, @function
_Z7setGridiR4dim3S0_:
.LFB2027:
.cfi_startproc
endbr64
movq %rdx, %rcx
movl %edi, %eax
movl $0, %edx
divl (%rsi)
movl %eax, %r9d
movl %eax, (%rcx)
movl %edi, %eax
movl $0, %edx
divl 4(%rsi)
movl %eax, %r8d
movl %eax, 4(%rcx)
movl %edi, %eax
movl $0, %edx
divl (%rsi)
cmpl $1, %edx
sbbl $-1, %r9d
movl %r9d, (%rcx)
movl %edi, %eax
movl $0, %edx
divl 4(%rsi)
cmpl $1, %edx
sbbl $-1, %r8d
movl %r8d, 4(%rcx)
ret
.cfi_endproc
.LFE2027:
.size _Z7setGridiR4dim3S0_, .-_Z7setGridiR4dim3S0_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
gridDim.x = n / blockDim.x;
gridDim.y = n / blockDim.y;
if(n % blockDim.x != 0)
gridDim.x++;
if(n % blockDim.y != 0)
gridDim.y++;
} | #include <hip/hip_runtime.h>
void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
gridDim.x = n / blockDim.x;
gridDim.y = n / blockDim.y;
if(n % blockDim.x != 0)
gridDim.x++;
if(n % blockDim.y != 0)
gridDim.y++;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
gridDim.x = n / blockDim.x;
gridDim.y = n / blockDim.y;
if(n % blockDim.x != 0)
gridDim.x++;
if(n % blockDim.y != 0)
gridDim.y++;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
void setGrid(int n, dim3 &blockDim, dim3 &gridDim)
{
// set your block dimensions and grid dimensions here
gridDim.x = n / blockDim.x;
gridDim.y = n / blockDim.y;
if(n % blockDim.x != 0)
gridDim.x++;
if(n % blockDim.y != 0)
gridDim.y++;
} | .text
.file "setGrid.hip"
.globl _Z7setGridiR4dim3S0_ # -- Begin function _Z7setGridiR4dim3S0_
.p2align 4, 0x90
.type _Z7setGridiR4dim3S0_,@function
_Z7setGridiR4dim3S0_: # @_Z7setGridiR4dim3S0_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movl %edi, %r8d
movl %edi, %eax
xorl %edx, %edx
divl (%rsi)
movl %eax, %r9d
movl %eax, (%rcx)
movl %edi, %eax
xorl %edx, %edx
divl 4(%rsi)
movl %eax, %edi
movl %eax, 4(%rcx)
movl %r8d, %eax
xorl %edx, %edx
divl (%rsi)
testl %edx, %edx
je .LBB0_2
# %bb.1:
incl %r9d
movl %r9d, (%rcx)
.LBB0_2:
movl %r8d, %eax
xorl %edx, %edx
divl 4(%rsi)
testl %edx, %edx
je .LBB0_4
# %bb.3:
incl %edi
movl %edi, 4(%rcx)
.LBB0_4:
retq
.Lfunc_end0:
.size _Z7setGridiR4dim3S0_, .Lfunc_end0-_Z7setGridiR4dim3S0_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ad63d_00000000-6_setGrid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7setGridiR4dim3S0_
.type _Z7setGridiR4dim3S0_, @function
_Z7setGridiR4dim3S0_:
.LFB2027:
.cfi_startproc
endbr64
movq %rdx, %rcx
movl %edi, %eax
movl $0, %edx
divl (%rsi)
movl %eax, %r9d
movl %eax, (%rcx)
movl %edi, %eax
movl $0, %edx
divl 4(%rsi)
movl %eax, %r8d
movl %eax, 4(%rcx)
movl %edi, %eax
movl $0, %edx
divl (%rsi)
cmpl $1, %edx
sbbl $-1, %r9d
movl %r9d, (%rcx)
movl %edi, %eax
movl $0, %edx
divl 4(%rsi)
cmpl $1, %edx
sbbl $-1, %r8d
movl %r8d, 4(%rcx)
ret
.cfi_endproc
.LFE2027:
.size _Z7setGridiR4dim3S0_, .-_Z7setGridiR4dim3S0_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "setGrid.hip"
.globl _Z7setGridiR4dim3S0_ # -- Begin function _Z7setGridiR4dim3S0_
.p2align 4, 0x90
.type _Z7setGridiR4dim3S0_,@function
_Z7setGridiR4dim3S0_: # @_Z7setGridiR4dim3S0_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movl %edi, %r8d
movl %edi, %eax
xorl %edx, %edx
divl (%rsi)
movl %eax, %r9d
movl %eax, (%rcx)
movl %edi, %eax
xorl %edx, %edx
divl 4(%rsi)
movl %eax, %edi
movl %eax, 4(%rcx)
movl %r8d, %eax
xorl %edx, %edx
divl (%rsi)
testl %edx, %edx
je .LBB0_2
# %bb.1:
incl %r9d
movl %r9d, (%rcx)
.LBB0_2:
movl %r8d, %eax
xorl %edx, %edx
divl 4(%rsi)
testl %edx, %edx
je .LBB0_4
# %bb.3:
incl %edi
movl %edi, 4(%rcx)
.LBB0_4:
retq
.Lfunc_end0:
.size _Z7setGridiR4dim3S0_, .Lfunc_end0-_Z7setGridiR4dim3S0_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | template<typename T>
__device__ void matrixRows(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesLength && col < numColumns) {
int resultIndex = row * numColumns + col;
int matrixIndex = indices[row] * numColumns + col;
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void matrixColumns(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < numRows && col < indicesLength) {
int resultIndex = row * indicesLength + col;
int matrixIndex = row * numColumns + indices[col];
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void vectorValuesMatrix(const T* vector, const int* indices, T* result, const int length, const int indicesNumRows, const int indicesNumColumns) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesNumRows && col < indicesNumColumns) {
int ij = row * indicesNumColumns + col;
result[ij] = vector[indices[ij]];
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | template<typename T>
__device__ void matrixRows(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesLength && col < numColumns) {
int resultIndex = row * numColumns + col;
int matrixIndex = indices[row] * numColumns + col;
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void matrixColumns(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < numRows && col < indicesLength) {
int resultIndex = row * indicesLength + col;
int matrixIndex = row * numColumns + indices[col];
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void vectorValuesMatrix(const T* vector, const int* indices, T* result, const int length, const int indicesNumRows, const int indicesNumColumns) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesNumRows && col < indicesNumColumns) {
int ij = row * indicesNumColumns + col;
result[ij] = vector[indices[ij]];
}
} | .file "tmpxft_0012f106_00000000-6_Values.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | template<typename T>
__device__ void matrixRows(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesLength && col < numColumns) {
int resultIndex = row * numColumns + col;
int matrixIndex = indices[row] * numColumns + col;
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void matrixColumns(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < numRows && col < indicesLength) {
int resultIndex = row * indicesLength + col;
int matrixIndex = row * numColumns + indices[col];
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void vectorValuesMatrix(const T* vector, const int* indices, T* result, const int length, const int indicesNumRows, const int indicesNumColumns) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesNumRows && col < indicesNumColumns) {
int ij = row * indicesNumColumns + col;
result[ij] = vector[indices[ij]];
}
} | #include <hip/hip_runtime.h>
template<typename T>
__device__ void matrixRows(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesLength && col < numColumns) {
int resultIndex = row * numColumns + col;
int matrixIndex = indices[row] * numColumns + col;
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void matrixColumns(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < numRows && col < indicesLength) {
int resultIndex = row * indicesLength + col;
int matrixIndex = row * numColumns + indices[col];
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void vectorValuesMatrix(const T* vector, const int* indices, T* result, const int length, const int indicesNumRows, const int indicesNumColumns) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesNumRows && col < indicesNumColumns) {
int ij = row * indicesNumColumns + col;
result[ij] = vector[indices[ij]];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
template<typename T>
__device__ void matrixRows(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesLength && col < numColumns) {
int resultIndex = row * numColumns + col;
int matrixIndex = indices[row] * numColumns + col;
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void matrixColumns(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < numRows && col < indicesLength) {
int resultIndex = row * indicesLength + col;
int matrixIndex = row * numColumns + indices[col];
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void vectorValuesMatrix(const T* vector, const int* indices, T* result, const int length, const int indicesNumRows, const int indicesNumColumns) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesNumRows && col < indicesNumColumns) {
int ij = row * indicesNumColumns + col;
result[ij] = vector[indices[ij]];
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
template<typename T>
__device__ void matrixRows(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesLength && col < numColumns) {
int resultIndex = row * numColumns + col;
int matrixIndex = indices[row] * numColumns + col;
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void matrixColumns(const T* matrix, const int* indices, T* result, const int numRows, const int numColumns, const int indicesLength) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < numRows && col < indicesLength) {
int resultIndex = row * indicesLength + col;
int matrixIndex = row * numColumns + indices[col];
result[resultIndex] = matrix[matrixIndex];
}
}
template<typename T>
__device__ void vectorValuesMatrix(const T* vector, const int* indices, T* result, const int length, const int indicesNumRows, const int indicesNumColumns) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
if (row < indicesNumRows && col < indicesNumColumns) {
int ij = row * indicesNumColumns + col;
result[ij] = vector[indices[ij]];
}
} | .text
.file "Values.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012f106_00000000-6_Values.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Values.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define N 1024
#include<stdio.h>
__global__ void add(int *a, int *b, int *c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void **) &dev_a, N * sizeof(int));
cudaMalloc((void **) &dev_b, N * sizeof(int));
cudaMalloc((void **) &dev_c, N * sizeof(int));
for(int j = 0; j < N; j++){
a[j] = 2;
b[j] = 3;
}
cudaMemcpy(dev_a, a, (N * sizeof(int)), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, (N * sizeof(int)), cudaMemcpyHostToDevice);
add<<<1, 1024>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, (N * sizeof(int)), cudaMemcpyDeviceToHost);
for(int j = 0; j <= 5; j++)
printf("\n%d",c[j]);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define N 1024
#include<stdio.h>
__global__ void add(int *a, int *b, int *c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void **) &dev_a, N * sizeof(int));
cudaMalloc((void **) &dev_b, N * sizeof(int));
cudaMalloc((void **) &dev_c, N * sizeof(int));
for(int j = 0; j < N; j++){
a[j] = 2;
b[j] = 3;
}
cudaMemcpy(dev_a, a, (N * sizeof(int)), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, (N * sizeof(int)), cudaMemcpyHostToDevice);
add<<<1, 1024>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, (N * sizeof(int)), cudaMemcpyDeviceToHost);
for(int j = 0; j <= 5; j++)
printf("\n%d",c[j]);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_00056c3a_00000000-6_CUDA_Vector_Addition_SingleBlock_MultiThread.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n%d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8224
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 12320
orq $0, (%rsp)
subq $64, %rsp
.cfi_def_cfa_offset 12384
movq %fs:40, %rax
movq %rax, 12344(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl $2, 48(%rsp,%rax)
movl $3, 4144(%rsp,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 4144(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 8240(%rsp), %rbx
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 8264(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 12344(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $12352, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define N 1024
#include<stdio.h>
__global__ void add(int *a, int *b, int *c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void **) &dev_a, N * sizeof(int));
cudaMalloc((void **) &dev_b, N * sizeof(int));
cudaMalloc((void **) &dev_c, N * sizeof(int));
for(int j = 0; j < N; j++){
a[j] = 2;
b[j] = 3;
}
cudaMemcpy(dev_a, a, (N * sizeof(int)), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, (N * sizeof(int)), cudaMemcpyHostToDevice);
add<<<1, 1024>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, (N * sizeof(int)), cudaMemcpyDeviceToHost);
for(int j = 0; j <= 5; j++)
printf("\n%d",c[j]);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | #define N 1024
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void add(int *a, int *b, int *c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void **) &dev_a, N * sizeof(int));
hipMalloc((void **) &dev_b, N * sizeof(int));
hipMalloc((void **) &dev_c, N * sizeof(int));
for(int j = 0; j < N; j++){
a[j] = 2;
b[j] = 3;
}
hipMemcpy(dev_a, a, (N * sizeof(int)), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, (N * sizeof(int)), hipMemcpyHostToDevice);
add<<<1, 1024>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, (N * sizeof(int)), hipMemcpyDeviceToHost);
for(int j = 0; j <= 5; j++)
printf("\n%d",c[j]);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define N 1024
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void add(int *a, int *b, int *c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void **) &dev_a, N * sizeof(int));
hipMalloc((void **) &dev_b, N * sizeof(int));
hipMalloc((void **) &dev_c, N * sizeof(int));
for(int j = 0; j < N; j++){
a[j] = 2;
b[j] = 3;
}
hipMemcpy(dev_a, a, (N * sizeof(int)), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, (N * sizeof(int)), hipMemcpyHostToDevice);
add<<<1, 1024>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, (N * sizeof(int)), hipMemcpyDeviceToHost);
for(int j = 0; j <= 5; j++)
printf("\n%d",c[j]);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define N 1024
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void add(int *a, int *b, int *c){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void **) &dev_a, N * sizeof(int));
hipMalloc((void **) &dev_b, N * sizeof(int));
hipMalloc((void **) &dev_c, N * sizeof(int));
for(int j = 0; j < N; j++){
a[j] = 2;
b[j] = 3;
}
hipMemcpy(dev_a, a, (N * sizeof(int)), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, (N * sizeof(int)), hipMemcpyHostToDevice);
add<<<1, 1024>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, (N * sizeof(int)), hipMemcpyDeviceToHost);
for(int j = 0; j <= 5; j++)
printf("\n%d",c[j]);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.file "CUDA_Vector_Addition_SingleBlock_MultiThread.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $12384, %rsp # imm = 0x3060
.cfi_def_cfa_offset 12400
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $2, 8288(%rsp,%rax,4)
movl $3, 4192(%rsp,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 8288(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 4192(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $6, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $12384, %rsp # imm = 0x3060
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n%d"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00056c3a_00000000-6_CUDA_Vector_Addition_SingleBlock_MultiThread.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n%d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8224
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 12320
orq $0, (%rsp)
subq $64, %rsp
.cfi_def_cfa_offset 12384
movq %fs:40, %rax
movq %rax, 12344(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl $2, 48(%rsp,%rax)
movl $3, 4144(%rsp,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 4144(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 8240(%rsp), %rbx
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 8264(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 12344(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $12352, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA_Vector_Addition_SingleBlock_MultiThread.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $12384, %rsp # imm = 0x3060
.cfi_def_cfa_offset 12400
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $2, 8288(%rsp,%rax,4)
movl $3, 4192(%rsp,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 8288(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 4192(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $6, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $12384, %rsp # imm = 0x3060
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n%d"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define NSTREAM 4
#include<stdio.h>
__global__ void addVec(int* a, int* b, int* c, int const len){
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<len) c[i] = a[i] + b[i];
};
int main(){
int const totalLen = 1<<16;
int const mSize = totalLen*sizeof(int);
int* h_a;
int* h_b;
int* h_c;
cudaHostAlloc((void**)&h_a, mSize, cudaHostAllocDefault);
cudaHostAlloc((void**)&h_b, mSize, cudaHostAllocDefault);
cudaHostAlloc((void**)&h_c, mSize, cudaHostAllocDefault);
for (int i=0; i<totalLen; i++){
h_a[i] = i;
h_b[i] = totalLen - i;
}
int* d_a;
int* d_b;
int* d_c;
cudaMalloc((void**)&d_a, mSize);
cudaMalloc((void**)&d_b, mSize);
cudaMalloc((void**)&d_c, mSize);
int const lenPerStream = totalLen/NSTREAM;
int const mSizePerStream = mSize/NSTREAM;
cudaStream_t lsStream[NSTREAM];
for (int i=0; i<NSTREAM; i++){
cudaStreamCreate(&lsStream[i]);
}
int const block = 256;
int const grid = lenPerStream/block;
for (int i=0; i<NSTREAM; i++){
int offset = i*lenPerStream;
cudaMemcpyAsync(&d_a[offset], &h_a[offset], mSizePerStream, cudaMemcpyHostToDevice, lsStream[i]);
cudaMemcpyAsync(&d_b[offset], &h_b[offset], mSizePerStream, cudaMemcpyHostToDevice, lsStream[i]);
addVec<<<grid, block, 0, lsStream[i]>>>(&d_a[offset], &d_b[offset], &d_c[offset], lenPerStream);
cudaMemcpyAsync(&h_c[offset], &d_c[offset], mSizePerStream, cudaMemcpyDeviceToHost, lsStream[i]);
}
for (int i=0; i<NSTREAM; i++){
cudaStreamSynchronize(lsStream[i]);
}
for (int i=0; i<totalLen; i++){
if (h_c[i]!=totalLen) {
printf("error, %d, %d \n", h_c[i], i);
break;
}
}
for (int i=0; i<NSTREAM; i++){
cudaStreamDestroy(lsStream[i]);
}
return 0;
} | code for sm_80
Function : _Z6addVecPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define NSTREAM 4
#include<stdio.h>
__global__ void addVec(int* a, int* b, int* c, int const len){
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<len) c[i] = a[i] + b[i];
};
int main(){
int const totalLen = 1<<16;
int const mSize = totalLen*sizeof(int);
int* h_a;
int* h_b;
int* h_c;
cudaHostAlloc((void**)&h_a, mSize, cudaHostAllocDefault);
cudaHostAlloc((void**)&h_b, mSize, cudaHostAllocDefault);
cudaHostAlloc((void**)&h_c, mSize, cudaHostAllocDefault);
for (int i=0; i<totalLen; i++){
h_a[i] = i;
h_b[i] = totalLen - i;
}
int* d_a;
int* d_b;
int* d_c;
cudaMalloc((void**)&d_a, mSize);
cudaMalloc((void**)&d_b, mSize);
cudaMalloc((void**)&d_c, mSize);
int const lenPerStream = totalLen/NSTREAM;
int const mSizePerStream = mSize/NSTREAM;
cudaStream_t lsStream[NSTREAM];
for (int i=0; i<NSTREAM; i++){
cudaStreamCreate(&lsStream[i]);
}
int const block = 256;
int const grid = lenPerStream/block;
for (int i=0; i<NSTREAM; i++){
int offset = i*lenPerStream;
cudaMemcpyAsync(&d_a[offset], &h_a[offset], mSizePerStream, cudaMemcpyHostToDevice, lsStream[i]);
cudaMemcpyAsync(&d_b[offset], &h_b[offset], mSizePerStream, cudaMemcpyHostToDevice, lsStream[i]);
addVec<<<grid, block, 0, lsStream[i]>>>(&d_a[offset], &d_b[offset], &d_c[offset], lenPerStream);
cudaMemcpyAsync(&h_c[offset], &d_c[offset], mSizePerStream, cudaMemcpyDeviceToHost, lsStream[i]);
}
for (int i=0; i<NSTREAM; i++){
cudaStreamSynchronize(lsStream[i]);
}
for (int i=0; i<totalLen; i++){
if (h_c[i]!=totalLen) {
printf("error, %d, %d \n", h_c[i], i);
break;
}
}
for (int i=0; i<NSTREAM; i++){
cudaStreamDestroy(lsStream[i]);
}
return 0;
} | .file "tmpxft_0019a63c_00000000-6_concurrent.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6addVecPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addVecPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.globl _Z6addVecPiS_S_i
.type _Z6addVecPiS_S_i, @function
_Z6addVecPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6addVecPiS_S_i, .-_Z6addVecPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "error, %d, %d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
addq $-128, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
movl $0, %eax
movl $65536, %esi
.L12:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movl %esi, %ecx
subl %eax, %ecx
movq 16(%rsp), %rdx
movl %ecx, (%rdx,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L12
leaq 32(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %r13
movq %r13, %rdi
call cudaStreamCreate@PLT
leaq 88(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 96(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 104(%rsp), %rdi
call cudaStreamCreate@PLT
movq %r13, %r12
movq %r13, %rbp
movl $0, %ebx
jmp .L14
.L13:
movq %rbx, %rsi
addq 48(%rsp), %rsi
movq %rbx, %rdi
addq 24(%rsp), %rdi
movq (%r14), %r8
movl $2, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $65536, %rbx
cmpq $262144, %rbx
je .L27
.L14:
movq %rbp, %r14
movq %rbx, %rsi
addq 8(%rsp), %rsi
movq %rbx, %rdi
addq 32(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq %rbx, %rdi
addq 40(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $64, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movq 0(%rbp), %r9
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq %rbx, %rdx
addq 48(%rsp), %rdx
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq %rbx, %rdi
addq 32(%rsp), %rdi
movl $16384, %ecx
call _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
jmp .L13
.L27:
leaq 32(%r13), %rbp
.L15:
movq 0(%r13), %rdi
call cudaStreamSynchronize@PLT
addq $8, %r13
cmpq %rbp, %r13
jne .L15
movq 24(%rsp), %rax
movl $0, %ecx
.L18:
movl (%rax,%rcx,4), %edx
cmpl $65536, %edx
jne .L28
addq $1, %rcx
cmpq $65536, %rcx
jne .L18
jmp .L17
.L28:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L17:
movq (%r12), %rdi
call cudaStreamDestroy@PLT
addq $8, %r12
cmpq %rbp, %r12
jne .L17
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6addVecPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addVecPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define NSTREAM 4
#include<stdio.h>
__global__ void addVec(int* a, int* b, int* c, int const len){
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<len) c[i] = a[i] + b[i];
};
int main(){
int const totalLen = 1<<16;
int const mSize = totalLen*sizeof(int);
int* h_a;
int* h_b;
int* h_c;
cudaHostAlloc((void**)&h_a, mSize, cudaHostAllocDefault);
cudaHostAlloc((void**)&h_b, mSize, cudaHostAllocDefault);
cudaHostAlloc((void**)&h_c, mSize, cudaHostAllocDefault);
for (int i=0; i<totalLen; i++){
h_a[i] = i;
h_b[i] = totalLen - i;
}
int* d_a;
int* d_b;
int* d_c;
cudaMalloc((void**)&d_a, mSize);
cudaMalloc((void**)&d_b, mSize);
cudaMalloc((void**)&d_c, mSize);
int const lenPerStream = totalLen/NSTREAM;
int const mSizePerStream = mSize/NSTREAM;
cudaStream_t lsStream[NSTREAM];
for (int i=0; i<NSTREAM; i++){
cudaStreamCreate(&lsStream[i]);
}
int const block = 256;
int const grid = lenPerStream/block;
for (int i=0; i<NSTREAM; i++){
int offset = i*lenPerStream;
cudaMemcpyAsync(&d_a[offset], &h_a[offset], mSizePerStream, cudaMemcpyHostToDevice, lsStream[i]);
cudaMemcpyAsync(&d_b[offset], &h_b[offset], mSizePerStream, cudaMemcpyHostToDevice, lsStream[i]);
addVec<<<grid, block, 0, lsStream[i]>>>(&d_a[offset], &d_b[offset], &d_c[offset], lenPerStream);
cudaMemcpyAsync(&h_c[offset], &d_c[offset], mSizePerStream, cudaMemcpyDeviceToHost, lsStream[i]);
}
for (int i=0; i<NSTREAM; i++){
cudaStreamSynchronize(lsStream[i]);
}
for (int i=0; i<totalLen; i++){
if (h_c[i]!=totalLen) {
printf("error, %d, %d \n", h_c[i], i);
break;
}
}
for (int i=0; i<NSTREAM; i++){
cudaStreamDestroy(lsStream[i]);
}
return 0;
} | #define NSTREAM 4
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void addVec(int* a, int* b, int* c, int const len){
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<len) c[i] = a[i] + b[i];
};
int main(){
int const totalLen = 1<<16;
int const mSize = totalLen*sizeof(int);
int* h_a;
int* h_b;
int* h_c;
hipHostAlloc((void**)&h_a, mSize, hipHostMallocDefault);
hipHostAlloc((void**)&h_b, mSize, hipHostMallocDefault);
hipHostAlloc((void**)&h_c, mSize, hipHostMallocDefault);
for (int i=0; i<totalLen; i++){
h_a[i] = i;
h_b[i] = totalLen - i;
}
int* d_a;
int* d_b;
int* d_c;
hipMalloc((void**)&d_a, mSize);
hipMalloc((void**)&d_b, mSize);
hipMalloc((void**)&d_c, mSize);
int const lenPerStream = totalLen/NSTREAM;
int const mSizePerStream = mSize/NSTREAM;
hipStream_t lsStream[NSTREAM];
for (int i=0; i<NSTREAM; i++){
hipStreamCreate(&lsStream[i]);
}
int const block = 256;
int const grid = lenPerStream/block;
for (int i=0; i<NSTREAM; i++){
int offset = i*lenPerStream;
hipMemcpyAsync(&d_a[offset], &h_a[offset], mSizePerStream, hipMemcpyHostToDevice, lsStream[i]);
hipMemcpyAsync(&d_b[offset], &h_b[offset], mSizePerStream, hipMemcpyHostToDevice, lsStream[i]);
addVec<<<grid, block, 0, lsStream[i]>>>(&d_a[offset], &d_b[offset], &d_c[offset], lenPerStream);
hipMemcpyAsync(&h_c[offset], &d_c[offset], mSizePerStream, hipMemcpyDeviceToHost, lsStream[i]);
}
for (int i=0; i<NSTREAM; i++){
hipStreamSynchronize(lsStream[i]);
}
for (int i=0; i<totalLen; i++){
if (h_c[i]!=totalLen) {
printf("error, %d, %d \n", h_c[i], i);
break;
}
}
for (int i=0; i<NSTREAM; i++){
hipStreamDestroy(lsStream[i]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define NSTREAM 4
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void addVec(int* a, int* b, int* c, int const len){
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<len) c[i] = a[i] + b[i];
};
int main(){
int const totalLen = 1<<16;
int const mSize = totalLen*sizeof(int);
int* h_a;
int* h_b;
int* h_c;
hipHostAlloc((void**)&h_a, mSize, hipHostMallocDefault);
hipHostAlloc((void**)&h_b, mSize, hipHostMallocDefault);
hipHostAlloc((void**)&h_c, mSize, hipHostMallocDefault);
for (int i=0; i<totalLen; i++){
h_a[i] = i;
h_b[i] = totalLen - i;
}
int* d_a;
int* d_b;
int* d_c;
hipMalloc((void**)&d_a, mSize);
hipMalloc((void**)&d_b, mSize);
hipMalloc((void**)&d_c, mSize);
int const lenPerStream = totalLen/NSTREAM;
int const mSizePerStream = mSize/NSTREAM;
hipStream_t lsStream[NSTREAM];
for (int i=0; i<NSTREAM; i++){
hipStreamCreate(&lsStream[i]);
}
int const block = 256;
int const grid = lenPerStream/block;
for (int i=0; i<NSTREAM; i++){
int offset = i*lenPerStream;
hipMemcpyAsync(&d_a[offset], &h_a[offset], mSizePerStream, hipMemcpyHostToDevice, lsStream[i]);
hipMemcpyAsync(&d_b[offset], &h_b[offset], mSizePerStream, hipMemcpyHostToDevice, lsStream[i]);
addVec<<<grid, block, 0, lsStream[i]>>>(&d_a[offset], &d_b[offset], &d_c[offset], lenPerStream);
hipMemcpyAsync(&h_c[offset], &d_c[offset], mSizePerStream, hipMemcpyDeviceToHost, lsStream[i]);
}
for (int i=0; i<NSTREAM; i++){
hipStreamSynchronize(lsStream[i]);
}
for (int i=0; i<totalLen; i++){
if (h_c[i]!=totalLen) {
printf("error, %d, %d \n", h_c[i], i);
break;
}
}
for (int i=0; i<NSTREAM; i++){
hipStreamDestroy(lsStream[i]);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addVecPiS_S_i
.globl _Z6addVecPiS_S_i
.p2align 8
.type _Z6addVecPiS_S_i,@function
_Z6addVecPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addVecPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addVecPiS_S_i, .Lfunc_end0-_Z6addVecPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addVecPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6addVecPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define NSTREAM 4
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void addVec(int* a, int* b, int* c, int const len){
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<len) c[i] = a[i] + b[i];
};
int main(){
int const totalLen = 1<<16;
int const mSize = totalLen*sizeof(int);
int* h_a;
int* h_b;
int* h_c;
hipHostAlloc((void**)&h_a, mSize, hipHostMallocDefault);
hipHostAlloc((void**)&h_b, mSize, hipHostMallocDefault);
hipHostAlloc((void**)&h_c, mSize, hipHostMallocDefault);
for (int i=0; i<totalLen; i++){
h_a[i] = i;
h_b[i] = totalLen - i;
}
int* d_a;
int* d_b;
int* d_c;
hipMalloc((void**)&d_a, mSize);
hipMalloc((void**)&d_b, mSize);
hipMalloc((void**)&d_c, mSize);
int const lenPerStream = totalLen/NSTREAM;
int const mSizePerStream = mSize/NSTREAM;
hipStream_t lsStream[NSTREAM];
for (int i=0; i<NSTREAM; i++){
hipStreamCreate(&lsStream[i]);
}
int const block = 256;
int const grid = lenPerStream/block;
for (int i=0; i<NSTREAM; i++){
int offset = i*lenPerStream;
hipMemcpyAsync(&d_a[offset], &h_a[offset], mSizePerStream, hipMemcpyHostToDevice, lsStream[i]);
hipMemcpyAsync(&d_b[offset], &h_b[offset], mSizePerStream, hipMemcpyHostToDevice, lsStream[i]);
addVec<<<grid, block, 0, lsStream[i]>>>(&d_a[offset], &d_b[offset], &d_c[offset], lenPerStream);
hipMemcpyAsync(&h_c[offset], &d_c[offset], mSizePerStream, hipMemcpyDeviceToHost, lsStream[i]);
}
for (int i=0; i<NSTREAM; i++){
hipStreamSynchronize(lsStream[i]);
}
for (int i=0; i<totalLen; i++){
if (h_c[i]!=totalLen) {
printf("error, %d, %d \n", h_c[i], i);
break;
}
}
for (int i=0; i<NSTREAM; i++){
hipStreamDestroy(lsStream[i]);
}
return 0;
} | .text
.file "concurrent.hip"
.globl _Z21__device_stub__addVecPiS_S_i # -- Begin function _Z21__device_stub__addVecPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__addVecPiS_S_i,@function
_Z21__device_stub__addVecPiS_S_i: # @_Z21__device_stub__addVecPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addVecPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__addVecPiS_S_i, .Lfunc_end0-_Z21__device_stub__addVecPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 48(%rsp), %rdi
xorl %ebx, %ebx
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 40(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 32(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
movq 48(%rsp), %rax
movl $65536, %ecx # imm = 0x10000
movq 40(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rax,%rbx,4)
movl %ecx, (%rdx,%rbx,4)
incq %rbx
decq %rcx
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $160, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $32, %rbx
jne .LBB1_3
# %bb.4: # %.preheader50
leaq 160(%rsp), %r12
movabsq $4294967360, %rbx # imm = 0x100000040
xorl %r13d, %r13d
leaq 192(%rbx), %r14
leaq 56(%rsp), %rbp
leaq 128(%rsp), %r15
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
movq 32(%rsp), %rdi
addq %r13, %rdi
movq 8(%rsp), %rsi
addq %r13, %rsi
movq (%r12), %r8
movl $65536, %edx # imm = 0x10000
movl $2, %ecx
callq hipMemcpyAsync
addq $65536, %r13 # imm = 0x10000
addq $8, %r12
cmpq $262144, %r13 # imm = 0x40000
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi
addq %r13, %rdi
movq 48(%rsp), %rsi
addq %r13, %rsi
movq (%r12), %r8
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
addq %r13, %rdi
movq 40(%rsp), %rsi
addq %r13, %rsi
movq (%r12), %r8
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpyAsync
movq (%r12), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 24(%rsp), %rax
addq %r13, %rax
movq 16(%rsp), %rcx
addq %r13, %rcx
movq 8(%rsp), %rdx
addq %r13, %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $16384, 4(%rsp) # imm = 0x4000
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z6addVecPiS_S_i, %edi
movq %r15, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %.preheader49.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # %.preheader49
# =>This Inner Loop Header: Depth=1
movq 160(%rsp,%rbx,8), %rdi
callq hipStreamSynchronize
incq %rbx
cmpq $4, %rbx
jne .LBB1_9
# %bb.10: # %.preheader
movq 32(%rsp), %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
movl (%rax,%rdx,4), %esi
cmpl $65536, %esi # imm = 0x10000
jne .LBB1_12
# %bb.16: # in Loop: Header=BB1_11 Depth=1
incq %rdx
cmpq $65536, %rdx # imm = 0x10000
jne .LBB1_11
jmp .LBB1_13
.LBB1_12:
movl $.L.str, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
.LBB1_13: # %.loopexit.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_14: # %.loopexit
# =>This Inner Loop Header: Depth=1
movq 160(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $4, %rbx
jne .LBB1_14
# %bb.15:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addVecPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addVecPiS_S_i,@object # @_Z6addVecPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6addVecPiS_S_i
.p2align 3, 0x0
_Z6addVecPiS_S_i:
.quad _Z21__device_stub__addVecPiS_S_i
.size _Z6addVecPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error, %d, %d \n"
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addVecPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addVecPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addVecPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6addVecPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addVecPiS_S_i
.globl _Z6addVecPiS_S_i
.p2align 8
.type _Z6addVecPiS_S_i,@function
_Z6addVecPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addVecPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addVecPiS_S_i, .Lfunc_end0-_Z6addVecPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addVecPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6addVecPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019a63c_00000000-6_concurrent.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6addVecPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addVecPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.globl _Z6addVecPiS_S_i
.type _Z6addVecPiS_S_i, @function
_Z6addVecPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6addVecPiS_S_i, .-_Z6addVecPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "error, %d, %d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
addq $-128, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
movl $0, %eax
movl $65536, %esi
.L12:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movl %esi, %ecx
subl %eax, %ecx
movq 16(%rsp), %rdx
movl %ecx, (%rdx,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L12
leaq 32(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %r13
movq %r13, %rdi
call cudaStreamCreate@PLT
leaq 88(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 96(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 104(%rsp), %rdi
call cudaStreamCreate@PLT
movq %r13, %r12
movq %r13, %rbp
movl $0, %ebx
jmp .L14
.L13:
movq %rbx, %rsi
addq 48(%rsp), %rsi
movq %rbx, %rdi
addq 24(%rsp), %rdi
movq (%r14), %r8
movl $2, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $65536, %rbx
cmpq $262144, %rbx
je .L27
.L14:
movq %rbp, %r14
movq %rbx, %rsi
addq 8(%rsp), %rsi
movq %rbx, %rdi
addq 32(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq %rbx, %rdi
addq 40(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $64, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movq 0(%rbp), %r9
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq %rbx, %rdx
addq 48(%rsp), %rdx
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq %rbx, %rdi
addq 32(%rsp), %rdi
movl $16384, %ecx
call _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
jmp .L13
.L27:
leaq 32(%r13), %rbp
.L15:
movq 0(%r13), %rdi
call cudaStreamSynchronize@PLT
addq $8, %r13
cmpq %rbp, %r13
jne .L15
movq 24(%rsp), %rax
movl $0, %ecx
.L18:
movl (%rax,%rcx,4), %edx
cmpl $65536, %edx
jne .L28
addq $1, %rcx
cmpq $65536, %rcx
jne .L18
jmp .L17
.L28:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L17:
movq (%r12), %rdi
call cudaStreamDestroy@PLT
addq $8, %r12
cmpq %rbp, %r12
jne .L17
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6addVecPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addVecPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "concurrent.hip"
.globl _Z21__device_stub__addVecPiS_S_i # -- Begin function _Z21__device_stub__addVecPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__addVecPiS_S_i,@function
_Z21__device_stub__addVecPiS_S_i: # @_Z21__device_stub__addVecPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addVecPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__addVecPiS_S_i, .Lfunc_end0-_Z21__device_stub__addVecPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 48(%rsp), %rdi
xorl %ebx, %ebx
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 40(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 32(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
movq 48(%rsp), %rax
movl $65536, %ecx # imm = 0x10000
movq 40(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rax,%rbx,4)
movl %ecx, (%rdx,%rbx,4)
incq %rbx
decq %rcx
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $160, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $32, %rbx
jne .LBB1_3
# %bb.4: # %.preheader50
leaq 160(%rsp), %r12
movabsq $4294967360, %rbx # imm = 0x100000040
xorl %r13d, %r13d
leaq 192(%rbx), %r14
leaq 56(%rsp), %rbp
leaq 128(%rsp), %r15
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
movq 32(%rsp), %rdi
addq %r13, %rdi
movq 8(%rsp), %rsi
addq %r13, %rsi
movq (%r12), %r8
movl $65536, %edx # imm = 0x10000
movl $2, %ecx
callq hipMemcpyAsync
addq $65536, %r13 # imm = 0x10000
addq $8, %r12
cmpq $262144, %r13 # imm = 0x40000
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi
addq %r13, %rdi
movq 48(%rsp), %rsi
addq %r13, %rsi
movq (%r12), %r8
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
addq %r13, %rdi
movq 40(%rsp), %rsi
addq %r13, %rsi
movq (%r12), %r8
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpyAsync
movq (%r12), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 24(%rsp), %rax
addq %r13, %rax
movq 16(%rsp), %rcx
addq %r13, %rcx
movq 8(%rsp), %rdx
addq %r13, %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $16384, 4(%rsp) # imm = 0x4000
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z6addVecPiS_S_i, %edi
movq %r15, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %.preheader49.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # %.preheader49
# =>This Inner Loop Header: Depth=1
movq 160(%rsp,%rbx,8), %rdi
callq hipStreamSynchronize
incq %rbx
cmpq $4, %rbx
jne .LBB1_9
# %bb.10: # %.preheader
movq 32(%rsp), %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
movl (%rax,%rdx,4), %esi
cmpl $65536, %esi # imm = 0x10000
jne .LBB1_12
# %bb.16: # in Loop: Header=BB1_11 Depth=1
incq %rdx
cmpq $65536, %rdx # imm = 0x10000
jne .LBB1_11
jmp .LBB1_13
.LBB1_12:
movl $.L.str, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
.LBB1_13: # %.loopexit.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_14: # %.loopexit
# =>This Inner Loop Header: Depth=1
movq 160(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $4, %rbx
jne .LBB1_14
# %bb.15:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addVecPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addVecPiS_S_i,@object # @_Z6addVecPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6addVecPiS_S_i
.p2align 3, 0x0
_Z6addVecPiS_S_i:
.quad _Z21__device_stub__addVecPiS_S_i
.size _Z6addVecPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error, %d, %d \n"
.size .L.str, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addVecPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addVecPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addVecPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#define MY_CUDA_CHECK( call) { \
cudaError err = call; \
if( cudaSuccess != err) { \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, cudaGetErrorString( err) ); \
exit(EXIT_FAILURE); \
} }
#define MY_CHECK_ERROR(errorMessage) { \
cudaError_t err = cudaGetLastError(); \
if( cudaSuccess != err) { \
fprintf(stderr, "Cuda error: %s in file '%s' in line %i : %s.\n", \
errorMessage, __FILE__, __LINE__, cudaGetErrorString( err) );\
exit(EXIT_FAILURE); \
} \
}
void writelog(int, int, const char *, ...);
#define MAKEMATR_RC 1
#if !defined(TRUE)
enum {FALSE, TRUE};
#endif
#if !defined(MAKEMATR_RC)
#define MAKEMATR_RC 12
#endif
void **mmcuda(void ***rp, int r, int c, int s, int init) {
int i;
char **pc;
short int **psi;
int **pi;
double **pd;
char **d_pc;
short int **d_psi;
int **d_pi;
double **d_pd;
switch(s) {
case sizeof(char):
pc=(char **)malloc(r*sizeof(char *));
if(!pc) writelog(TRUE, MAKEMATR_RC, "error in makematr 1\n");
MY_CUDA_CHECK( cudaMalloc( (void **) &d_pc, r*sizeof(char*) ) );
for(i=0; i<r; i++) {
MY_CUDA_CHECK( cudaMalloc( (void **) &pc[i], c*sizeof(char) ) );
if(init) {
MY_CUDA_CHECK( cudaMemset( pc[i], 0, c*sizeof(char) ) );
}
}
MY_CUDA_CHECK( cudaMemcpy( d_pc, pc, r*sizeof(char *), cudaMemcpyHostToDevice ) );
rp[0]=(void **)d_pc;
return (void **)pc;
case sizeof(short int):
psi=(short int **)malloc(r*sizeof(short int*));
if(!psi) writelog(TRUE, MAKEMATR_RC, "error in makematr 2\n");
MY_CUDA_CHECK( cudaMalloc( (void **) &d_psi, r*sizeof(short int*) ) );
for(i=0; i<r; i++) {
MY_CUDA_CHECK( cudaMalloc( (void **) &psi[i], c*sizeof(short int) ) );
if(init) {
MY_CUDA_CHECK( cudaMemset( psi[i], 0, c*sizeof(short int) ) );
}
}
MY_CUDA_CHECK( cudaMemcpy( d_psi, psi, r*sizeof(short int*), cudaMemcpyHostToDevice ) );
rp[0]=(void **)d_psi;
return (void **)psi;
case sizeof(int):
pi=(int **)malloc(r*sizeof(int*));
if(!pi) writelog(TRUE, MAKEMATR_RC, "error in makematr 3\n");
MY_CUDA_CHECK( cudaMalloc( (void **) &d_pi, r*sizeof(int*) ) );
for(i=0; i<r; i++) {
MY_CUDA_CHECK( cudaMalloc( (void **) &pi[i], c*sizeof(int) ) );
if(init) {
MY_CUDA_CHECK( cudaMemset( pi[i], 0, c*sizeof(int) ) );
}
}
MY_CUDA_CHECK( cudaMemcpy( d_pi, pi, r*sizeof(int *), cudaMemcpyHostToDevice ) );
rp[0]=(void **)d_pi;
return (void **)pi;
case sizeof(double):
pd=(double **)malloc(r*sizeof(double*));
if(!pd) writelog(TRUE, MAKEMATR_RC, "error in makematr 4 for %d rows\n",r);
MY_CUDA_CHECK( cudaMalloc( (void **) &d_pd, r*sizeof(double*) ) );
for(i=0; i<r; i++) {
MY_CUDA_CHECK( cudaMalloc( (void **) &pd[i], c*sizeof(double) ) );
if(init) {
MY_CUDA_CHECK( cudaMemset( pd[i], 0, c*sizeof(double) ) );
}
}
MY_CUDA_CHECK( cudaMemcpy( d_pd, pd, r*sizeof(double *), cudaMemcpyHostToDevice ) );
rp[0]=(void **)d_pd;
return (void **)pd;
default:
writelog(TRUE,MAKEMATR_RC,"Unexpected size: %d\n",s);
break;
}
return NULL;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#define MY_CUDA_CHECK( call) { \
cudaError err = call; \
if( cudaSuccess != err) { \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, cudaGetErrorString( err) ); \
exit(EXIT_FAILURE); \
} }
#define MY_CHECK_ERROR(errorMessage) { \
cudaError_t err = cudaGetLastError(); \
if( cudaSuccess != err) { \
fprintf(stderr, "Cuda error: %s in file '%s' in line %i : %s.\n", \
errorMessage, __FILE__, __LINE__, cudaGetErrorString( err) );\
exit(EXIT_FAILURE); \
} \
}
void writelog(int, int, const char *, ...);
#define MAKEMATR_RC 1
#if !defined(TRUE)
enum {FALSE, TRUE};
#endif
#if !defined(MAKEMATR_RC)
#define MAKEMATR_RC 12
#endif
void **mmcuda(void ***rp, int r, int c, int s, int init) {
int i;
char **pc;
short int **psi;
int **pi;
double **pd;
char **d_pc;
short int **d_psi;
int **d_pi;
double **d_pd;
switch(s) {
case sizeof(char):
pc=(char **)malloc(r*sizeof(char *));
if(!pc) writelog(TRUE, MAKEMATR_RC, "error in makematr 1\n");
MY_CUDA_CHECK( cudaMalloc( (void **) &d_pc, r*sizeof(char*) ) );
for(i=0; i<r; i++) {
MY_CUDA_CHECK( cudaMalloc( (void **) &pc[i], c*sizeof(char) ) );
if(init) {
MY_CUDA_CHECK( cudaMemset( pc[i], 0, c*sizeof(char) ) );
}
}
MY_CUDA_CHECK( cudaMemcpy( d_pc, pc, r*sizeof(char *), cudaMemcpyHostToDevice ) );
rp[0]=(void **)d_pc;
return (void **)pc;
case sizeof(short int):
psi=(short int **)malloc(r*sizeof(short int*));
if(!psi) writelog(TRUE, MAKEMATR_RC, "error in makematr 2\n");
MY_CUDA_CHECK( cudaMalloc( (void **) &d_psi, r*sizeof(short int*) ) );
for(i=0; i<r; i++) {
MY_CUDA_CHECK( cudaMalloc( (void **) &psi[i], c*sizeof(short int) ) );
if(init) {
MY_CUDA_CHECK( cudaMemset( psi[i], 0, c*sizeof(short int) ) );
}
}
MY_CUDA_CHECK( cudaMemcpy( d_psi, psi, r*sizeof(short int*), cudaMemcpyHostToDevice ) );
rp[0]=(void **)d_psi;
return (void **)psi;
case sizeof(int):
pi=(int **)malloc(r*sizeof(int*));
if(!pi) writelog(TRUE, MAKEMATR_RC, "error in makematr 3\n");
MY_CUDA_CHECK( cudaMalloc( (void **) &d_pi, r*sizeof(int*) ) );
for(i=0; i<r; i++) {
MY_CUDA_CHECK( cudaMalloc( (void **) &pi[i], c*sizeof(int) ) );
if(init) {
MY_CUDA_CHECK( cudaMemset( pi[i], 0, c*sizeof(int) ) );
}
}
MY_CUDA_CHECK( cudaMemcpy( d_pi, pi, r*sizeof(int *), cudaMemcpyHostToDevice ) );
rp[0]=(void **)d_pi;
return (void **)pi;
case sizeof(double):
pd=(double **)malloc(r*sizeof(double*));
if(!pd) writelog(TRUE, MAKEMATR_RC, "error in makematr 4 for %d rows\n",r);
MY_CUDA_CHECK( cudaMalloc( (void **) &d_pd, r*sizeof(double*) ) );
for(i=0; i<r; i++) {
MY_CUDA_CHECK( cudaMalloc( (void **) &pd[i], c*sizeof(double) ) );
if(init) {
MY_CUDA_CHECK( cudaMemset( pd[i], 0, c*sizeof(double) ) );
}
}
MY_CUDA_CHECK( cudaMemcpy( d_pd, pd, r*sizeof(double *), cudaMemcpyHostToDevice ) );
rp[0]=(void **)d_pd;
return (void **)pd;
default:
writelog(TRUE,MAKEMATR_RC,"Unexpected size: %d\n",s);
break;
}
return NULL;
} | .file "tmpxft_00138fb7_00000000-6_mmcuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "error in makematr 1\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mbernaschi/StrongErgodicityBreaking/master/SBcode/GPU/mmcuda.cu"
.align 8
.LC2:
.string "Cuda error in file '%s' in line %i : %s.\n"
.section .rodata.str1.1
.LC3:
.string "error in makematr 2\n"
.LC4:
.string "error in makematr 3\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "error in makematr 4 for %d rows\n"
.section .rodata.str1.1
.LC6:
.string "Unexpected size: %d\n"
.text
.globl _Z6mmcudaPPPviiii
.type _Z6mmcudaPPPviiii, @function
_Z6mmcudaPPPviiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, (%rsp)
movl %esi, %r14d
movl %edx, %r13d
movl %r8d, %ebp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
cmpl $4, %ecx
je .L4
jg .L5
cmpl $1, %ecx
je .L6
cmpl $2, %ecx
jne .L8
movslq %esi, %rax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L50
.L19:
leaq 16(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L20
testl %r14d, %r14d
jle .L22
movslq %r13d, %r13
addq %r13, %r13
movq %r12, %rbx
movq 8(%rsp), %rax
leaq (%rax,%r12), %r15
jmp .L25
.L5:
cmpl $8, %ecx
jne .L8
movslq %esi, %rax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L51
.L35:
leaq 16(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
testl %r14d, %r14d
jle .L38
movslq %r13d, %r13
salq $3, %r13
movq %r12, %rbx
movq 8(%rsp), %rax
leaq (%rax,%r12), %r15
jmp .L41
.L6:
movslq %esi, %rax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L52
.L10:
leaq 16(%rsp), %rdi
movq 8(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L11
movq %r12, %rbx
addq %r12, %r15
movslq %r13d, %r13
testl %r14d, %r14d
jg .L16
.L13:
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L53
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq %rax, (%rcx)
jmp .L3
.L52:
leaq .LC0(%rip), %rdx
movl $1, %esi
movl $1, %edi
movl $0, %eax
call _Z8writelogiiPKcz@PLT
jmp .L10
.L11:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $46, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $48, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
addq $8, %rbx
cmpq %r15, %rbx
je .L13
.L16:
movq %r13, %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L54
testl %ebp, %ebp
je .L15
movq (%rbx), %rdi
movq %r13, %rdx
movl $0, %esi
call cudaMemset@PLT
testl %eax, %eax
je .L15
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $50, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $53, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
leaq .LC3(%rip), %rdx
movl $1, %esi
movl $1, %edi
movl $0, %eax
call _Z8writelogiiPKcz@PLT
jmp .L19
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $59, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $61, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
addq $8, %rbx
cmpq %r15, %rbx
je .L22
.L25:
movq %r13, %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L55
testl %ebp, %ebp
je .L24
movq (%rbx), %rdi
movq %r13, %rdx
movl $0, %esi
call cudaMemset@PLT
testl %eax, %eax
je .L24
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $63, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L56
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq %rax, (%rcx)
jmp .L3
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $66, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L4:
movslq %esi, %rax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L57
.L27:
leaq 16(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
testl %r14d, %r14d
jle .L30
movslq %r13d, %r13
salq $2, %r13
movq %r12, %rbx
movq 8(%rsp), %rax
leaq (%rax,%r12), %r15
jmp .L33
.L57:
leaq .LC4(%rip), %rdx
movl $1, %esi
movl $1, %edi
movl $0, %eax
call _Z8writelogiiPKcz@PLT
jmp .L27
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $72, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $74, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
addq $8, %rbx
cmpq %r15, %rbx
je .L30
.L33:
movq %r13, %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
testl %ebp, %ebp
je .L32
movq (%rbx), %rdi
movq %r13, %rdx
movl $0, %esi
call cudaMemset@PLT
testl %eax, %eax
je .L32
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $76, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L59
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq %rax, (%rcx)
jmp .L3
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $79, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movl %r14d, %ecx
leaq .LC5(%rip), %rdx
movl $1, %esi
movl $1, %edi
movl $0, %eax
call _Z8writelogiiPKcz@PLT
jmp .L35
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $85, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $87, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
addq $8, %rbx
cmpq %r15, %rbx
je .L38
.L41:
movq %r13, %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L60
testl %ebp, %ebp
je .L40
movq (%rbx), %rdi
movq %r13, %rdx
movl $0, %esi
call cudaMemset@PLT
testl %eax, %eax
je .L40
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $89, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L61
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq %rax, (%rcx)
jmp .L3
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $92, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L8:
leaq .LC6(%rip), %rdx
movl $1, %esi
movl $1, %edi
movl $0, %eax
call _Z8writelogiiPKcz@PLT
movl $0, %r12d
.L3:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L62
movq %r12, %rax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6mmcudaPPPviiii, .-_Z6mmcudaPPPviiii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.