system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define ITERATIONS 4 //Repeat the experiment for greater accuracy
__global__ void add(int *a, int *b, int *c, int tpb)
{
//Find the correct thread index in the grid
int i = blockIdx.x * tpb + threadIdx.x;
c[i] = a[i] + b[i];
}
#define N 1000000 //Array Size
#define min_threads 16
#define max_threads 1024
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
//Allocate on device
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
srand(time(NULL));
//Populate a and b
for (int i = 0; i < N; ++i)
{
a[i] = rand()%20;
b[i] = rand()%37;
}
int numBlocks;
cudaEvent_t start, copy, exec, result; //Events for measuring time
//To calculate average over a number of iterations
float t1[7], t2[7], t3[7], total[7];
for (int i = 0; i < 7; ++i)
{
t1[i]=0;
t2[i]=0;
t3[i]=0;
total[i]=0;
}
printf("t1: time for copying arrays\n");
printf("t2: time for kernel execution\n");
printf("t3: time for copying result back\n\n");
printf("All times in milliseconds\n");
printf("TPB\t\tNB\t\tt1\t\tt2\t\tt3\t\ttotal\t\n");
int count;
for (int i = 0; i < ITERATIONS; ++i)
{
count=0;
for (int threadsPerBlock = min_threads; threadsPerBlock <= max_threads; threadsPerBlock*=2)
{
numBlocks = (N + threadsPerBlock - 1)/threadsPerBlock;
cudaEventCreate(&start);
cudaEventCreate(©);
cudaEventCreate(&exec);
cudaEventCreate(&result);
cudaEventRecord(start);
//Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
cudaEventRecord(copy);
cudaEventSynchronize(copy);
//Launch add() kernel on GPU
add<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c, threadsPerBlock);
cudaEventRecord(exec);
cudaEventSynchronize(exec);
//Copy result back to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
cudaEventRecord(result);
cudaEventSynchronize(result);
float temp1=0, temp2=0, temp3=0, temptotal;
cudaEventElapsedTime(&temp1, start, copy);
cudaEventElapsedTime(&temp2, copy, exec);
cudaEventElapsedTime(&temp3, exec, result);
cudaEventElapsedTime(&temptotal, start, result);
t1[count] += temp1;
t2[count] += temp2;
t3[count] += temp3;
total[count] += temptotal;
cudaEventDestroy(start);
cudaEventDestroy(copy);
cudaEventDestroy(exec);
cudaEventDestroy(result);
count++;
}
}
int threadsPerBlock = min_threads;
for (int i = 0; i < 7; ++i)
{
numBlocks = (N + threadsPerBlock - 1)/threadsPerBlock;
t1[i]/=(float)ITERATIONS;
t2[i]/=(float)ITERATIONS;
t3[i]/=(float)ITERATIONS;
total[i]/=(float)ITERATIONS;
printf("%d\t\t%d\t\t%.5f\t\t%.5f\t\t%.5f\t\t%.5f\t\t\n",
threadsPerBlock, numBlocks, t1[i], t2[i], t3[i], total[i]);
threadsPerBlock*=2;
}
//Cleanup
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define ITERATIONS 4 //Repeat the experiment for greater accuracy
__global__ void add(int *a, int *b, int *c, int tpb)
{
//Find the correct thread index in the grid
int i = blockIdx.x * tpb + threadIdx.x;
c[i] = a[i] + b[i];
}
#define N 1000000 //Array Size
#define min_threads 16
#define max_threads 1024
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
//Allocate on device
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
srand(time(NULL));
//Populate a and b
for (int i = 0; i < N; ++i)
{
a[i] = rand()%20;
b[i] = rand()%37;
}
int numBlocks;
hipEvent_t start, copy, exec, result; //Events for measuring time
//To calculate average over a number of iterations
float t1[7], t2[7], t3[7], total[7];
for (int i = 0; i < 7; ++i)
{
t1[i]=0;
t2[i]=0;
t3[i]=0;
total[i]=0;
}
printf("t1: time for copying arrays\n");
printf("t2: time for kernel execution\n");
printf("t3: time for copying result back\n\n");
printf("All times in milliseconds\n");
printf("TPB\t\tNB\t\tt1\t\tt2\t\tt3\t\ttotal\t\n");
int count;
for (int i = 0; i < ITERATIONS; ++i)
{
count=0;
for (int threadsPerBlock = min_threads; threadsPerBlock <= max_threads; threadsPerBlock*=2)
{
numBlocks = (N + threadsPerBlock - 1)/threadsPerBlock;
hipEventCreate(&start);
hipEventCreate(©);
hipEventCreate(&exec);
hipEventCreate(&result);
hipEventRecord(start);
//Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipEventRecord(copy);
hipEventSynchronize(copy);
//Launch add() kernel on GPU
add<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c, threadsPerBlock);
hipEventRecord(exec);
hipEventSynchronize(exec);
//Copy result back to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
hipEventRecord(result);
hipEventSynchronize(result);
float temp1=0, temp2=0, temp3=0, temptotal;
hipEventElapsedTime(&temp1, start, copy);
hipEventElapsedTime(&temp2, copy, exec);
hipEventElapsedTime(&temp3, exec, result);
hipEventElapsedTime(&temptotal, start, result);
t1[count] += temp1;
t2[count] += temp2;
t3[count] += temp3;
total[count] += temptotal;
hipEventDestroy(start);
hipEventDestroy(copy);
hipEventDestroy(exec);
hipEventDestroy(result);
count++;
}
}
int threadsPerBlock = min_threads;
for (int i = 0; i < 7; ++i)
{
numBlocks = (N + threadsPerBlock - 1)/threadsPerBlock;
t1[i]/=(float)ITERATIONS;
t2[i]/=(float)ITERATIONS;
t3[i]/=(float)ITERATIONS;
total[i]/=(float)ITERATIONS;
printf("%d\t\t%d\t\t%.5f\t\t%.5f\t\t%.5f\t\t%.5f\t\t\n",
threadsPerBlock, numBlocks, t1[i], t2[i], t3[i], total[i]);
threadsPerBlock*=2;
}
//Cleanup
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define ITERATIONS 4 //Repeat the experiment for greater accuracy
__global__ void add(int *a, int *b, int *c, int tpb)
{
//Find the correct thread index in the grid
int i = blockIdx.x * tpb + threadIdx.x;
c[i] = a[i] + b[i];
}
#define N 1000000 //Array Size
#define min_threads 16
#define max_threads 1024
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
//Allocate on device
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
srand(time(NULL));
//Populate a and b
for (int i = 0; i < N; ++i)
{
a[i] = rand()%20;
b[i] = rand()%37;
}
int numBlocks;
hipEvent_t start, copy, exec, result; //Events for measuring time
//To calculate average over a number of iterations
float t1[7], t2[7], t3[7], total[7];
for (int i = 0; i < 7; ++i)
{
t1[i]=0;
t2[i]=0;
t3[i]=0;
total[i]=0;
}
printf("t1: time for copying arrays\n");
printf("t2: time for kernel execution\n");
printf("t3: time for copying result back\n\n");
printf("All times in milliseconds\n");
printf("TPB\t\tNB\t\tt1\t\tt2\t\tt3\t\ttotal\t\n");
int count;
for (int i = 0; i < ITERATIONS; ++i)
{
count=0;
for (int threadsPerBlock = min_threads; threadsPerBlock <= max_threads; threadsPerBlock*=2)
{
numBlocks = (N + threadsPerBlock - 1)/threadsPerBlock;
hipEventCreate(&start);
hipEventCreate(©);
hipEventCreate(&exec);
hipEventCreate(&result);
hipEventRecord(start);
//Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipEventRecord(copy);
hipEventSynchronize(copy);
//Launch add() kernel on GPU
add<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c, threadsPerBlock);
hipEventRecord(exec);
hipEventSynchronize(exec);
//Copy result back to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
hipEventRecord(result);
hipEventSynchronize(result);
float temp1=0, temp2=0, temp3=0, temptotal;
hipEventElapsedTime(&temp1, start, copy);
hipEventElapsedTime(&temp2, copy, exec);
hipEventElapsedTime(&temp3, exec, result);
hipEventElapsedTime(&temptotal, start, result);
t1[count] += temp1;
t2[count] += temp2;
t3[count] += temp3;
total[count] += temptotal;
hipEventDestroy(start);
hipEventDestroy(copy);
hipEventDestroy(exec);
hipEventDestroy(result);
count++;
}
}
int threadsPerBlock = min_threads;
for (int i = 0; i < 7; ++i)
{
numBlocks = (N + threadsPerBlock - 1)/threadsPerBlock;
t1[i]/=(float)ITERATIONS;
t2[i]/=(float)ITERATIONS;
t3[i]/=(float)ITERATIONS;
total[i]/=(float)ITERATIONS;
printf("%d\t\t%d\t\t%.5f\t\t%.5f\t\t%.5f\t\t%.5f\t\t\n",
threadsPerBlock, numBlocks, t1[i], t2[i], t3[i], total[i]);
threadsPerBlock*=2;
}
//Cleanup
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define ITERATIONS 4 //Repeat the experiment for greater accuracy
__global__ void add(int *a, int *b, int *c, int tpb)
{
//Find the correct thread index in the grid
int i = blockIdx.x * tpb + threadIdx.x;
c[i] = a[i] + b[i];
}
#define N 1000000 //Array Size
#define min_threads 16
#define max_threads 1024
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
//Allocate on device
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
srand(time(NULL));
//Populate a and b
for (int i = 0; i < N; ++i)
{
a[i] = rand()%20;
b[i] = rand()%37;
}
int numBlocks;
hipEvent_t start, copy, exec, result; //Events for measuring time
//To calculate average over a number of iterations
float t1[7], t2[7], t3[7], total[7];
for (int i = 0; i < 7; ++i)
{
t1[i]=0;
t2[i]=0;
t3[i]=0;
total[i]=0;
}
printf("t1: time for copying arrays\n");
printf("t2: time for kernel execution\n");
printf("t3: time for copying result back\n\n");
printf("All times in milliseconds\n");
printf("TPB\t\tNB\t\tt1\t\tt2\t\tt3\t\ttotal\t\n");
int count;
for (int i = 0; i < ITERATIONS; ++i)
{
count=0;
for (int threadsPerBlock = min_threads; threadsPerBlock <= max_threads; threadsPerBlock*=2)
{
numBlocks = (N + threadsPerBlock - 1)/threadsPerBlock;
hipEventCreate(&start);
hipEventCreate(©);
hipEventCreate(&exec);
hipEventCreate(&result);
hipEventRecord(start);
//Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipEventRecord(copy);
hipEventSynchronize(copy);
//Launch add() kernel on GPU
add<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c, threadsPerBlock);
hipEventRecord(exec);
hipEventSynchronize(exec);
//Copy result back to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
hipEventRecord(result);
hipEventSynchronize(result);
float temp1=0, temp2=0, temp3=0, temptotal;
hipEventElapsedTime(&temp1, start, copy);
hipEventElapsedTime(&temp2, copy, exec);
hipEventElapsedTime(&temp3, exec, result);
hipEventElapsedTime(&temptotal, start, result);
t1[count] += temp1;
t2[count] += temp2;
t3[count] += temp3;
total[count] += temptotal;
hipEventDestroy(start);
hipEventDestroy(copy);
hipEventDestroy(exec);
hipEventDestroy(result);
count++;
}
}
int threadsPerBlock = min_threads;
for (int i = 0; i < 7; ++i)
{
numBlocks = (N + threadsPerBlock - 1)/threadsPerBlock;
t1[i]/=(float)ITERATIONS;
t2[i]/=(float)ITERATIONS;
t3[i]/=(float)ITERATIONS;
total[i]/=(float)ITERATIONS;
printf("%d\t\t%d\t\t%.5f\t\t%.5f\t\t%.5f\t\t%.5f\t\t\n",
threadsPerBlock, numBlocks, t1[i], t2[i], t3[i], total[i]);
threadsPerBlock*=2;
}
//Cleanup
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.file "q3.hip"
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3e800000 # float 0.25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r12
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r15
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
leaq 48(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
shrq $32, %rcx
sarl $3, %ecx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r12,%rbx,4)
callq rand
cltq
imulq $-580400985, %rax, %rcx # imm = 0xDD67C8A7
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $5, %ecx
addl %edx, %ecx
leal (%rcx,%rcx,8), %edx
leal (%rcx,%rdx,4), %ecx
subl %ecx, %eax
movl %eax, (%r15,%rbx,4)
incq %rbx
cmpq $1000000, %rbx # imm = 0xF4240
jne .LBB1_1
# %bb.2:
movabsq $4294967296, %r14 # imm = 0x100000000
xorps %xmm0, %xmm0
movaps %xmm0, 288(%rsp)
movups %xmm0, 300(%rsp)
movaps %xmm0, 256(%rsp)
movups %xmm0, 268(%rsp)
movaps %xmm0, 224(%rsp)
movups %xmm0, 236(%rsp)
movaps %xmm0, 192(%rsp)
movups %xmm0, 204(%rsp)
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
xorl %eax, %eax
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
movq 152(%rsp), %rax # 8-byte Reload
incl %eax
cmpl $4, %eax
je .LBB1_8
.LBB1_3: # %.preheader71
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq %rax, 152(%rsp) # 8-byte Spill
movl $16, %r13d
xorl %ebp, %ebp
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 104(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 112(%rsp)
movl $0, 72(%rsp)
movl $0, 56(%rsp)
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 72(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 88(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 288(%rsp,%rbp,4), %xmm0
movss %xmm0, 288(%rsp,%rbp,4)
movss 72(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 256(%rsp,%rbp,4), %xmm0
movss %xmm0, 256(%rsp,%rbp,4)
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 224(%rsp,%rbp,4), %xmm0
movss %xmm0, 224(%rsp,%rbp,4)
movss 88(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 192(%rsp,%rbp,4), %xmm0
movss %xmm0, 192(%rsp,%rbp,4)
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
incq %rbp
addl %r13d, %r13d
cmpq $7, %rbp
je .LBB1_7
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
leal 999999(%r13), %eax
xorl %edx, %edx
divl %r13d
movl %eax, %ebx
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
orq %r14, %rbx
movl %r13d, %edx
orq %r14, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movl %r13d, 100(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 184(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 100(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z3addPiS_S_i, %edi
leaq 112(%rsp), %r9
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_6
.LBB1_8: # %.preheader.preheader
movl $16, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Inner Loop Header: Depth=1
leal 999999(%rbx), %eax
xorl %edx, %edx
divl %ebx
movss 288(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
mulss %xmm4, %xmm0
movss %xmm0, 288(%rsp,%r14,4)
movss 256(%rsp,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm4, %xmm1
movss %xmm1, 256(%rsp,%r14,4)
movss 224(%rsp,%r14,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm4, %xmm2
movss %xmm2, 224(%rsp,%r14,4)
movss 192(%rsp,%r14,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm4, %xmm3
movss %xmm3, 192(%rsp,%r14,4)
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movl $.L.str.5, %edi
movl %ebx, %esi
movl %eax, %edx
movb $4, %al
callq printf
addl %ebx, %ebx
incq %r14
cmpq $7, %r14
jne .LBB1_9
# %bb.10:
movq %r12, %rdi
callq free
movq %r15, %rdi
callq free
movq 104(%rsp), %rdi # 8-byte Reload
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "%d\t\t%d\t\t%.5f\t\t%.5f\t\t%.5f\t\t%.5f\t\t\n"
.size .L.str.5, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "t1: time for copying arrays"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "t2: time for kernel execution"
.size .Lstr.1, 30
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "t3: time for copying result back\n"
.size .Lstr.2, 34
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "All times in milliseconds"
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "TPB\t\tNB\t\tt1\t\tt2\t\tt3\t\ttotal\t"
.size .Lstr.4, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x178], R3 ; /* 0x00005e0006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016390e_00000000-6_q3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "t1: time for copying arrays\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "t2: time for kernel execution\n"
.align 8
.LC3:
.string "t3: time for copying result back\n\n"
.section .rodata.str1.1
.LC4:
.string "All times in milliseconds\n"
.LC5:
.string "TPB\t\tNB\t\tt1\t\tt2\t\tt3\t\ttotal\t\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "%d\t\t%d\t\t%.5f\t\t%.5f\t\t%.5f\t\t%.5f\t\t\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call malloc@PLT
movq %rax, %r14
movl $4000000, %edi
call malloc@PLT
movq %rax, %r13
movl $4000000, %edi
call malloc@PLT
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%r14,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $-580400985, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $5, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,8), %ecx
leal (%rdx,%rcx,4), %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
addq $4, %rbx
cmpq $4000000, %rbx
jne .L12
movl $0, %eax
.L13:
movl $0x00000000, 112(%rsp,%rax)
movl $0x00000000, 144(%rsp,%rax)
movl $0x00000000, 176(%rsp,%rax)
movl $0x00000000, 208(%rsp,%rax)
addq $4, %rax
cmpq $28, %rax
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 12(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
jmp .L14
.L15:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $4000000, %edx
movq 48(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 24(%rsp)
movl $0x00000000, 28(%rsp)
movl $0x00000000, 88(%rsp)
leaq 24(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 28(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 88(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 100(%rsp), %rdi
movq 80(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 112(%rsp,%rbx), %xmm0
addss 24(%rsp), %xmm0
movss %xmm0, 112(%rsp,%rbx)
movss 144(%rsp,%rbx), %xmm0
addss 28(%rsp), %xmm0
movss %xmm0, 144(%rsp,%rbx)
movss 176(%rsp,%rbx), %xmm0
addss 88(%rsp), %xmm0
movss %xmm0, 176(%rsp,%rbx)
movss 208(%rsp,%rbx), %xmm0
addss 100(%rsp), %xmm0
movss %xmm0, 208(%rsp,%rbx)
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
addl %ebp, %ebp
addq $4, %rbx
cmpq $28, %rbx
je .L25
.L16:
leal 999999(%rbp), %eax
cltd
idivl %ebp
movl %eax, %r12d
movq (%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %ebp, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl %r12d, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L15
.L25:
subl $1, 12(%rsp)
je .L19
.L14:
movl $0, %ebx
movl $16, %ebp
jmp .L16
.L19:
movl $0, %ebx
movl $16, %ebp
leaq .LC7(%rip), %r12
.L17:
movss .LC6(%rip), %xmm0
mulss 112(%rsp,%rbx), %xmm0
movss %xmm0, 112(%rsp,%rbx)
movss .LC6(%rip), %xmm1
mulss 144(%rsp,%rbx), %xmm1
movss %xmm1, 144(%rsp,%rbx)
movss .LC6(%rip), %xmm2
mulss 176(%rsp,%rbx), %xmm2
movss %xmm2, 176(%rsp,%rbx)
movss .LC6(%rip), %xmm3
mulss 208(%rsp,%rbx), %xmm3
movss %xmm3, 208(%rsp,%rbx)
cvtss2sd %xmm0, %xmm0
leal 999999(%rbp), %eax
cltd
idivl %ebp
cvtss2sd %xmm3, %xmm3
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
movl %eax, %ecx
movl %ebp, %edx
movq %r12, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
addl %ebp, %ebp
addq $4, %rbx
cmpq $28, %rbx
jne .L17
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1048576000
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q3.hip"
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3e800000 # float 0.25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r12
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r15
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
leaq 48(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
shrq $32, %rcx
sarl $3, %ecx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r12,%rbx,4)
callq rand
cltq
imulq $-580400985, %rax, %rcx # imm = 0xDD67C8A7
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $5, %ecx
addl %edx, %ecx
leal (%rcx,%rcx,8), %edx
leal (%rcx,%rdx,4), %ecx
subl %ecx, %eax
movl %eax, (%r15,%rbx,4)
incq %rbx
cmpq $1000000, %rbx # imm = 0xF4240
jne .LBB1_1
# %bb.2:
movabsq $4294967296, %r14 # imm = 0x100000000
xorps %xmm0, %xmm0
movaps %xmm0, 288(%rsp)
movups %xmm0, 300(%rsp)
movaps %xmm0, 256(%rsp)
movups %xmm0, 268(%rsp)
movaps %xmm0, 224(%rsp)
movups %xmm0, 236(%rsp)
movaps %xmm0, 192(%rsp)
movups %xmm0, 204(%rsp)
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
xorl %eax, %eax
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
movq 152(%rsp), %rax # 8-byte Reload
incl %eax
cmpl $4, %eax
je .LBB1_8
.LBB1_3: # %.preheader71
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq %rax, 152(%rsp) # 8-byte Spill
movl $16, %r13d
xorl %ebp, %ebp
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=2
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 104(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movl $0, 112(%rsp)
movl $0, 72(%rsp)
movl $0, 56(%rsp)
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 72(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 88(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 288(%rsp,%rbp,4), %xmm0
movss %xmm0, 288(%rsp,%rbp,4)
movss 72(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 256(%rsp,%rbp,4), %xmm0
movss %xmm0, 256(%rsp,%rbp,4)
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 224(%rsp,%rbp,4), %xmm0
movss %xmm0, 224(%rsp,%rbp,4)
movss 88(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 192(%rsp,%rbp,4), %xmm0
movss %xmm0, 192(%rsp,%rbp,4)
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
incq %rbp
addl %r13d, %r13d
cmpq $7, %rbp
je .LBB1_7
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
leal 999999(%r13), %eax
xorl %edx, %edx
divl %r13d
movl %eax, %ebx
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
orq %r14, %rbx
movl %r13d, %edx
orq %r14, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movl %r13d, 100(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 184(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 100(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z3addPiS_S_i, %edi
leaq 112(%rsp), %r9
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_6
.LBB1_8: # %.preheader.preheader
movl $16, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Inner Loop Header: Depth=1
leal 999999(%rbx), %eax
xorl %edx, %edx
divl %ebx
movss 288(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
mulss %xmm4, %xmm0
movss %xmm0, 288(%rsp,%r14,4)
movss 256(%rsp,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm4, %xmm1
movss %xmm1, 256(%rsp,%r14,4)
movss 224(%rsp,%r14,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm4, %xmm2
movss %xmm2, 224(%rsp,%r14,4)
movss 192(%rsp,%r14,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm4, %xmm3
movss %xmm3, 192(%rsp,%r14,4)
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movl $.L.str.5, %edi
movl %ebx, %esi
movl %eax, %edx
movb $4, %al
callq printf
addl %ebx, %ebx
incq %r14
cmpq $7, %r14
jne .LBB1_9
# %bb.10:
movq %r12, %rdi
callq free
movq %r15, %rdi
callq free
movq 104(%rsp), %rdi # 8-byte Reload
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "%d\t\t%d\t\t%.5f\t\t%.5f\t\t%.5f\t\t%.5f\t\t\n"
.size .L.str.5, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "t1: time for copying arrays"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "t2: time for kernel execution"
.size .Lstr.1, 30
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "t3: time for copying result back\n"
.size .Lstr.2, 34
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "All times in milliseconds"
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "TPB\t\tNB\t\tt1\t\tt2\t\tt3\t\ttotal\t"
.size .Lstr.4, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime_api.h>
#include <iostream>
#include <list>
#include "tbb/concurrent_queue.h"
#include "math.h"
#define nThreadsPerBlocks 512
__global__ void assign(int *d_a, int *d_b, int size) {
int index = threadIdx.x;
if (index < size) {
d_b[index] = d_a[0] ;
}
}
void cudaPrintError(std::string m) {
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) {
std::cerr<<m<<" : "<<cudaGetErrorString(err)<<std::endl;
}
}
int main(int argc, char* argv[]){
int GPU1 = 0;
int GPU2 = 1;
int size = 200;
int *a;
int *d_a0;
int *b, *c;
int *d_b1;
cudaSetDevice(GPU1);
a = (int *) malloc(1 * sizeof(int));
a[0] = 15 ;
cudaMalloc((void**)&d_a0, 1*sizeof(int)) ;
cudaMemcpy(d_a0, a, 1*sizeof(int), cudaMemcpyHostToDevice);
cudaPrintError("after GPU1");
cudaDeviceEnablePeerAccess(GPU1,0);
cudaSetDevice(GPU2);
cudaMalloc((void**)&d_b1, size*sizeof(int)) ;
cudaDeviceEnablePeerAccess(GPU1,0);
cudaPrintError("after GPU2");
assign<<<1, nThreadsPerBlocks>>>(d_a0,d_b1,size);
cudaPrintError("after KERNEL");
c = (int *) malloc(size * sizeof(int));
cudaMemcpy(c, d_b1, size*sizeof(int), cudaMemcpyDeviceToHost);
cudaPrintError("after getData");
for(int i=0; i<size; i++ )
std::cout << i << " " << c[i] << std::endl;
cudaFree(d_a0);
cudaFree(d_b1);
return 0;
} | code for sm_80
Function : _Z6assignPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime_api.h>
#include <iostream>
#include <list>
#include "tbb/concurrent_queue.h"
#include "math.h"
#define nThreadsPerBlocks 512
__global__ void assign(int *d_a, int *d_b, int size) {
int index = threadIdx.x;
if (index < size) {
d_b[index] = d_a[0] ;
}
}
void cudaPrintError(std::string m) {
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) {
std::cerr<<m<<" : "<<cudaGetErrorString(err)<<std::endl;
}
}
int main(int argc, char* argv[]){
int GPU1 = 0;
int GPU2 = 1;
int size = 200;
int *a;
int *d_a0;
int *b, *c;
int *d_b1;
cudaSetDevice(GPU1);
a = (int *) malloc(1 * sizeof(int));
a[0] = 15 ;
cudaMalloc((void**)&d_a0, 1*sizeof(int)) ;
cudaMemcpy(d_a0, a, 1*sizeof(int), cudaMemcpyHostToDevice);
cudaPrintError("after GPU1");
cudaDeviceEnablePeerAccess(GPU1,0);
cudaSetDevice(GPU2);
cudaMalloc((void**)&d_b1, size*sizeof(int)) ;
cudaDeviceEnablePeerAccess(GPU1,0);
cudaPrintError("after GPU2");
assign<<<1, nThreadsPerBlocks>>>(d_a0,d_b1,size);
cudaPrintError("after KERNEL");
c = (int *) malloc(size * sizeof(int));
cudaMemcpy(c, d_b1, size*sizeof(int), cudaMemcpyDeviceToHost);
cudaPrintError("after getData");
for(int i=0; i<size; i++ )
std::cout << i << " " << c[i] << std::endl;
cudaFree(d_a0);
cudaFree(d_b1);
return 0;
} | .file "tmpxft_000eecf1_00000000-6_test_cuda_peerTopeer.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB12824:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12824:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " : "
.text
.globl _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB12820:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
call cudaGetLastError@PLT
testl %eax, %eax
jne .L11
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl %eax, %ebx
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC0(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L12
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L6:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L13
cmpb $0, 56(%rbx)
je .L8
movzbl 67(%rbx), %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L3
.L12:
movq 0(%rbp), %rax
movq %rbp, %rdi
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L6
.L13:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.cfi_endproc
.LFE12820:
.size _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.globl _Z28__device_stub__Z6assignPiS_iPiS_i
.type _Z28__device_stub__Z6assignPiS_iPiS_i, @function
_Z28__device_stub__Z6assignPiS_iPiS_i:
.LFB12846:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6assignPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE12846:
.size _Z28__device_stub__Z6assignPiS_iPiS_i, .-_Z28__device_stub__Z6assignPiS_iPiS_i
.globl _Z6assignPiS_i
.type _Z6assignPiS_i, @function
_Z6assignPiS_i:
.LFB12847:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6assignPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12847:
.size _Z6assignPiS_i, .-_Z6assignPiS_i
.section .rodata.str1.1
.LC1:
.string "_Z6assignPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB12849:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6assignPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12849:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB13261:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L33
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L34
cmpq $1, %rax
jne .L29
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L30:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L36
leaq .LC2(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L36:
call __stack_chk_fail@PLT
.L34:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L28:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L30
.L29:
testq %rax, %rax
je .L30
jmp .L28
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE13261:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC3:
.string "after GPU1"
.LC4:
.string "after GPU2"
.LC5:
.string "after KERNEL"
.LC6:
.string "after getData"
.LC7:
.string " "
.text
.globl main
.type main, @function
main:
.LFB12821:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA12821
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %edi
.LEHB0:
call cudaSetDevice@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $15, (%rax)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 36(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movq %rbx, %rdi
.LEHB1:
call _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE1:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %esi
movl $0, %edi
.LEHB2:
call cudaDeviceEnablePeerAccess@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $0, %esi
movl $0, %edi
call cudaDeviceEnablePeerAccess@PLT
leaq 36(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movq %rbx, %rdi
.LEHB3:
call _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE3:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L38:
leaq 36(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movq %rbx, %rdi
.LEHB5:
call _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE5:
jmp .L61
.L60:
movl $200, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
.LEHB6:
call _Z28__device_stub__Z6assignPiS_iPiS_i
jmp .L38
.L61:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $800, %edi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movl $800, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq 36(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movq %rbx, %rdi
.LEHB7:
call _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE7:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r14
leaq .LC7(%rip), %r13
jmp .L43
.L64:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L62
.LEHB8:
call _ZSt16__throw_bad_castv@PLT
.L62:
call __stack_chk_fail@PLT
.L65:
movzbl 67(%r15), %esi
.L42:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $200, %rbp
je .L63
.L43:
movl %ebp, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r12,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L64
cmpb $0, 56(%r15)
jne .L65
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L42
.L63:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L66
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L54:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L55:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L56:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE8:
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE12821:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA12821:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE12821-.LLSDACSB12821
.LLSDACSB12821:
.uleb128 .LEHB0-.LFB12821
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB12821
.uleb128 .LEHE1-.LEHB1
.uleb128 .L53-.LFB12821
.uleb128 0
.uleb128 .LEHB2-.LFB12821
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB12821
.uleb128 .LEHE3-.LEHB3
.uleb128 .L54-.LFB12821
.uleb128 0
.uleb128 .LEHB4-.LFB12821
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB12821
.uleb128 .LEHE5-.LEHB5
.uleb128 .L55-.LFB12821
.uleb128 0
.uleb128 .LEHB6-.LFB12821
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB12821
.uleb128 .LEHE7-.LEHB7
.uleb128 .L56-.LFB12821
.uleb128 0
.uleb128 .LEHB8-.LFB12821
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE12821:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime_api.h>
#include <iostream>
#include <list>
#include "tbb/concurrent_queue.h"
#include "math.h"
#define nThreadsPerBlocks 512
__global__ void assign(int *d_a, int *d_b, int size) {
int index = threadIdx.x;
if (index < size) {
d_b[index] = d_a[0] ;
}
}
void cudaPrintError(std::string m) {
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) {
std::cerr<<m<<" : "<<cudaGetErrorString(err)<<std::endl;
}
}
int main(int argc, char* argv[]){
int GPU1 = 0;
int GPU2 = 1;
int size = 200;
int *a;
int *d_a0;
int *b, *c;
int *d_b1;
cudaSetDevice(GPU1);
a = (int *) malloc(1 * sizeof(int));
a[0] = 15 ;
cudaMalloc((void**)&d_a0, 1*sizeof(int)) ;
cudaMemcpy(d_a0, a, 1*sizeof(int), cudaMemcpyHostToDevice);
cudaPrintError("after GPU1");
cudaDeviceEnablePeerAccess(GPU1,0);
cudaSetDevice(GPU2);
cudaMalloc((void**)&d_b1, size*sizeof(int)) ;
cudaDeviceEnablePeerAccess(GPU1,0);
cudaPrintError("after GPU2");
assign<<<1, nThreadsPerBlocks>>>(d_a0,d_b1,size);
cudaPrintError("after KERNEL");
c = (int *) malloc(size * sizeof(int));
cudaMemcpy(c, d_b1, size*sizeof(int), cudaMemcpyDeviceToHost);
cudaPrintError("after getData");
for(int i=0; i<size; i++ )
std::cout << i << " " << c[i] << std::endl;
cudaFree(d_a0);
cudaFree(d_b1);
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
#include <list>
#include "tbb/concurrent_queue.h"
#include "math.h"
#define nThreadsPerBlocks 512
__global__ void assign(int *d_a, int *d_b, int size) {
int index = threadIdx.x;
if (index < size) {
d_b[index] = d_a[0] ;
}
}
void cudaPrintError(std::string m) {
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
std::cerr<<m<<" : "<<hipGetErrorString(err)<<std::endl;
}
}
int main(int argc, char* argv[]){
int GPU1 = 0;
int GPU2 = 1;
int size = 200;
int *a;
int *d_a0;
int *b, *c;
int *d_b1;
hipSetDevice(GPU1);
a = (int *) malloc(1 * sizeof(int));
a[0] = 15 ;
hipMalloc((void**)&d_a0, 1*sizeof(int)) ;
hipMemcpy(d_a0, a, 1*sizeof(int), hipMemcpyHostToDevice);
cudaPrintError("after GPU1");
hipDeviceEnablePeerAccess(GPU1,0);
hipSetDevice(GPU2);
hipMalloc((void**)&d_b1, size*sizeof(int)) ;
hipDeviceEnablePeerAccess(GPU1,0);
cudaPrintError("after GPU2");
assign<<<1, nThreadsPerBlocks>>>(d_a0,d_b1,size);
cudaPrintError("after KERNEL");
c = (int *) malloc(size * sizeof(int));
hipMemcpy(c, d_b1, size*sizeof(int), hipMemcpyDeviceToHost);
cudaPrintError("after getData");
for(int i=0; i<size; i++ )
std::cout << i << " " << c[i] << std::endl;
hipFree(d_a0);
hipFree(d_b1);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
#include <list>
#include "tbb/concurrent_queue.h"
#include "math.h"
#define nThreadsPerBlocks 512
__global__ void assign(int *d_a, int *d_b, int size) {
int index = threadIdx.x;
if (index < size) {
d_b[index] = d_a[0] ;
}
}
void cudaPrintError(std::string m) {
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
std::cerr<<m<<" : "<<hipGetErrorString(err)<<std::endl;
}
}
int main(int argc, char* argv[]){
int GPU1 = 0;
int GPU2 = 1;
int size = 200;
int *a;
int *d_a0;
int *b, *c;
int *d_b1;
hipSetDevice(GPU1);
a = (int *) malloc(1 * sizeof(int));
a[0] = 15 ;
hipMalloc((void**)&d_a0, 1*sizeof(int)) ;
hipMemcpy(d_a0, a, 1*sizeof(int), hipMemcpyHostToDevice);
cudaPrintError("after GPU1");
hipDeviceEnablePeerAccess(GPU1,0);
hipSetDevice(GPU2);
hipMalloc((void**)&d_b1, size*sizeof(int)) ;
hipDeviceEnablePeerAccess(GPU1,0);
cudaPrintError("after GPU2");
assign<<<1, nThreadsPerBlocks>>>(d_a0,d_b1,size);
cudaPrintError("after KERNEL");
c = (int *) malloc(size * sizeof(int));
hipMemcpy(c, d_b1, size*sizeof(int), hipMemcpyDeviceToHost);
cudaPrintError("after getData");
for(int i=0; i<size; i++ )
std::cout << i << " " << c[i] << std::endl;
hipFree(d_a0);
hipFree(d_b1);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6assignPiS_i
.globl _Z6assignPiS_i
.p2align 8
.type _Z6assignPiS_i,@function
_Z6assignPiS_i:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s0 :: v_dual_lshlrev_b32 v0, 2, v0
global_store_b32 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6assignPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6assignPiS_i, .Lfunc_end0-_Z6assignPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6assignPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6assignPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
#include <list>
#include "tbb/concurrent_queue.h"
#include "math.h"
#define nThreadsPerBlocks 512
__global__ void assign(int *d_a, int *d_b, int size) {
int index = threadIdx.x;
if (index < size) {
d_b[index] = d_a[0] ;
}
}
void cudaPrintError(std::string m) {
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
std::cerr<<m<<" : "<<hipGetErrorString(err)<<std::endl;
}
}
int main(int argc, char* argv[]){
int GPU1 = 0;
int GPU2 = 1;
int size = 200;
int *a;
int *d_a0;
int *b, *c;
int *d_b1;
hipSetDevice(GPU1);
a = (int *) malloc(1 * sizeof(int));
a[0] = 15 ;
hipMalloc((void**)&d_a0, 1*sizeof(int)) ;
hipMemcpy(d_a0, a, 1*sizeof(int), hipMemcpyHostToDevice);
cudaPrintError("after GPU1");
hipDeviceEnablePeerAccess(GPU1,0);
hipSetDevice(GPU2);
hipMalloc((void**)&d_b1, size*sizeof(int)) ;
hipDeviceEnablePeerAccess(GPU1,0);
cudaPrintError("after GPU2");
assign<<<1, nThreadsPerBlocks>>>(d_a0,d_b1,size);
cudaPrintError("after KERNEL");
c = (int *) malloc(size * sizeof(int));
hipMemcpy(c, d_b1, size*sizeof(int), hipMemcpyDeviceToHost);
cudaPrintError("after getData");
for(int i=0; i<size; i++ )
std::cout << i << " " << c[i] << std::endl;
hipFree(d_a0);
hipFree(d_b1);
return 0;
} | .text
.file "test_cuda_peerTopeer.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__assignPiS_i # -- Begin function _Z21__device_stub__assignPiS_i
.p2align 4, 0x90
.type _Z21__device_stub__assignPiS_i,@function
_Z21__device_stub__assignPiS_i: # @_Z21__device_stub__assignPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6assignPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__assignPiS_i, .Lfunc_end0-_Z21__device_stub__assignPiS_i
.cfi_endproc
# -- End function
.globl _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
je .LBB1_9
# %bb.1:
movl %eax, %ebp
movq (%rbx), %rsi
movq 8(%rbx), %rdx
movl $_ZSt4cerr, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
movl $.L.str, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_2
# %bb.3:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_4
.LBB1_9:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 32
movq (%rbx), %rax
movq -24(%rax), %rax
movq %rbx, %rdi
addq %rax, %rdi
movl 32(%rbx,%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_10
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB1_8
.LBB1_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_10:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end1-_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $248, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq hipSetDevice
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $15, (%rax)
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 144(%rsp), %r14
movq %r14, 128(%rsp)
movabsq $5784627922081179233, %rbx # imm = 0x5047207265746661
movq %rbx, 144(%rsp)
movw $12629, 152(%rsp) # imm = 0x3155
movq $10, 136(%rsp)
movb $0, 154(%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
callq _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 128(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_3
# %bb.2: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq hipSetDevice
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
leaq 112(%rsp), %r14
movq %r14, 96(%rsp)
movq %rbx, 112(%rsp)
movw $12885, 120(%rsp) # imm = 0x3255
movq $10, 104(%rsp)
movb $0, 122(%rsp)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp4:
# %bb.4:
movq 96(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_6
# %bb.5: # %.critedge.i.i43
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit45
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movl $200, 28(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 28(%rsp), %rax
movq %rax, 240(%rsp)
.cfi_escape 0x2e, 0x00
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 224(%rsp), %r9
movl $_Z6assignPiS_i, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit58
leaq 80(%rsp), %r14
movq %r14, 64(%rsp)
movabsq $4993120287570814561, %rax # imm = 0x454B207265746661
movq %rax, 80(%rsp)
movl $1279610450, 88(%rsp) # imm = 0x4C454E52
movq $12, 72(%rsp)
movb $0, 92(%rsp)
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp7:
# %bb.9:
movq 64(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_11
# %bb.10: # %.critedge.i.i59
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit61
.cfi_escape 0x2e, 0x00
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $800, %edx # imm = 0x320
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %r14
movq %r14, 32(%rsp)
movabsq $7306844596132406881, %rax # imm = 0x6567207265746661
movq %rax, 48(%rsp)
movabsq $7022344665615918880, %rax # imm = 0x6174614474656720
movq %rax, 53(%rsp)
movq $13, 40(%rsp)
movb $0, 61(%rsp)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp10:
# %bb.12:
movq 32(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_14
# %bb.13: # %.critedge.i.i69
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_14: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit71.preheader
xorl %r14d, %r14d
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_29: # in Loop: Header=BB2_15 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_15 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $200, %r14
je .LBB2_31
.LBB2_15: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit71
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx,%r14,4), %esi
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_16
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_15 Depth=1
cmpb $0, 56(%r15)
je .LBB2_29
# %bb.28: # in Loop: Header=BB2_15 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB2_30
.LBB2_31:
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_16:
.cfi_def_cfa_offset 288
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_25:
.Ltmp11:
movq %rax, %rbx
movq 32(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.26: # %.critedge.i.i75
.cfi_escape 0x2e, 0x00
jmp .LBB2_19
.LBB2_23:
.Ltmp8:
movq %rax, %rbx
movq 64(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.24: # %.critedge.i.i72
.cfi_escape 0x2e, 0x00
jmp .LBB2_19
.LBB2_21:
.Ltmp5:
movq %rax, %rbx
movq 96(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.22: # %.critedge.i.i49
.cfi_escape 0x2e, 0x00
jmp .LBB2_19
.LBB2_17:
.Ltmp2:
movq %rax, %rbx
movq 128(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.18: # %.critedge.i.i46
.cfi_escape 0x2e, 0x00
.LBB2_19: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit48
callq _ZdlPv
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit48
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end2-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6assignPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6assignPiS_i,@object # @_Z6assignPiS_i
.section .rodata,"a",@progbits
.globl _Z6assignPiS_i
.p2align 3, 0x0
_Z6assignPiS_i:
.quad _Z21__device_stub__assignPiS_i
.size _Z6assignPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " : "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "after GPU1"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "after GPU2"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "after KERNEL"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "after getData"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " "
.size .L.str.5, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6assignPiS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__assignPiS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6assignPiS_i
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6assignPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6assignPiS_i
.globl _Z6assignPiS_i
.p2align 8
.type _Z6assignPiS_i,@function
_Z6assignPiS_i:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s0 :: v_dual_lshlrev_b32 v0, 2, v0
global_store_b32 v0, v1, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6assignPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6assignPiS_i, .Lfunc_end0-_Z6assignPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6assignPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6assignPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eecf1_00000000-6_test_cuda_peerTopeer.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB12824:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12824:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " : "
.text
.globl _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB12820:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
call cudaGetLastError@PLT
testl %eax, %eax
jne .L11
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl %eax, %ebx
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC0(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L12
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L6:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L13
cmpb $0, 56(%rbx)
je .L8
movzbl 67(%rbx), %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L3
.L12:
movq 0(%rbp), %rax
movq %rbp, %rdi
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L6
.L13:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.cfi_endproc
.LFE12820:
.size _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.globl _Z28__device_stub__Z6assignPiS_iPiS_i
.type _Z28__device_stub__Z6assignPiS_iPiS_i, @function
_Z28__device_stub__Z6assignPiS_iPiS_i:
.LFB12846:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6assignPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE12846:
.size _Z28__device_stub__Z6assignPiS_iPiS_i, .-_Z28__device_stub__Z6assignPiS_iPiS_i
.globl _Z6assignPiS_i
.type _Z6assignPiS_i, @function
_Z6assignPiS_i:
.LFB12847:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6assignPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12847:
.size _Z6assignPiS_i, .-_Z6assignPiS_i
.section .rodata.str1.1
.LC1:
.string "_Z6assignPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB12849:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6assignPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12849:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB13261:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L33
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L34
cmpq $1, %rax
jne .L29
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L30:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L36
leaq .LC2(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L36:
call __stack_chk_fail@PLT
.L34:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L28:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L30
.L29:
testq %rax, %rax
je .L30
jmp .L28
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE13261:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC3:
.string "after GPU1"
.LC4:
.string "after GPU2"
.LC5:
.string "after KERNEL"
.LC6:
.string "after getData"
.LC7:
.string " "
.text
.globl main
.type main, @function
main:
.LFB12821:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA12821
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %edi
.LEHB0:
call cudaSetDevice@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $15, (%rax)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 36(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movq %rbx, %rdi
.LEHB1:
call _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE1:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %esi
movl $0, %edi
.LEHB2:
call cudaDeviceEnablePeerAccess@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $0, %esi
movl $0, %edi
call cudaDeviceEnablePeerAccess@PLT
leaq 36(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movq %rbx, %rdi
.LEHB3:
call _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE3:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L38:
leaq 36(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movq %rbx, %rdi
.LEHB5:
call _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE5:
jmp .L61
.L60:
movl $200, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
.LEHB6:
call _Z28__device_stub__Z6assignPiS_iPiS_i
jmp .L38
.L61:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $800, %edi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movl $800, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq 36(%rsp), %rdx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movq %rbx, %rdi
.LEHB7:
call _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE7:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r14
leaq .LC7(%rip), %r13
jmp .L43
.L64:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L62
.LEHB8:
call _ZSt16__throw_bad_castv@PLT
.L62:
call __stack_chk_fail@PLT
.L65:
movzbl 67(%r15), %esi
.L42:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $200, %rbp
je .L63
.L43:
movl %ebp, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r12,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L64
cmpb $0, 56(%r15)
jne .L65
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L42
.L63:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L66
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L54:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L55:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L56:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE8:
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE12821:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA12821:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE12821-.LLSDACSB12821
.LLSDACSB12821:
.uleb128 .LEHB0-.LFB12821
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB12821
.uleb128 .LEHE1-.LEHB1
.uleb128 .L53-.LFB12821
.uleb128 0
.uleb128 .LEHB2-.LFB12821
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB12821
.uleb128 .LEHE3-.LEHB3
.uleb128 .L54-.LFB12821
.uleb128 0
.uleb128 .LEHB4-.LFB12821
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB12821
.uleb128 .LEHE5-.LEHB5
.uleb128 .L55-.LFB12821
.uleb128 0
.uleb128 .LEHB6-.LFB12821
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB12821
.uleb128 .LEHE7-.LEHB7
.uleb128 .L56-.LFB12821
.uleb128 0
.uleb128 .LEHB8-.LFB12821
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE12821:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_cuda_peerTopeer.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__assignPiS_i # -- Begin function _Z21__device_stub__assignPiS_i
.p2align 4, 0x90
.type _Z21__device_stub__assignPiS_i,@function
_Z21__device_stub__assignPiS_i: # @_Z21__device_stub__assignPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6assignPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__assignPiS_i, .Lfunc_end0-_Z21__device_stub__assignPiS_i
.cfi_endproc
# -- End function
.globl _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
je .LBB1_9
# %bb.1:
movl %eax, %ebp
movq (%rbx), %rsi
movq 8(%rbx), %rdx
movl $_ZSt4cerr, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
movl $.L.str, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_2
# %bb.3:
movq %rax, %rdi
movq %rax, %r14
callq strlen
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_4
.LBB1_9:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 32
movq (%rbx), %rax
movq -24(%rax), %rax
movq %rbx, %rdi
addq %rax, %rdi
movl 32(%rbx,%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_10
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB1_8
.LBB1_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_10:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end1-_Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $248, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq hipSetDevice
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $15, (%rax)
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 144(%rsp), %r14
movq %r14, 128(%rsp)
movabsq $5784627922081179233, %rbx # imm = 0x5047207265746661
movq %rbx, 144(%rsp)
movw $12629, 152(%rsp) # imm = 0x3155
movq $10, 136(%rsp)
movb $0, 154(%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
callq _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 128(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_3
# %bb.2: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq hipSetDevice
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
leaq 112(%rsp), %r14
movq %r14, 96(%rsp)
movq %rbx, 112(%rsp)
movw $12885, 120(%rsp) # imm = 0x3255
movq $10, 104(%rsp)
movb $0, 122(%rsp)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp4:
# %bb.4:
movq 96(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_6
# %bb.5: # %.critedge.i.i43
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit45
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movl $200, 28(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 28(%rsp), %rax
movq %rax, 240(%rsp)
.cfi_escape 0x2e, 0x00
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 224(%rsp), %r9
movl $_Z6assignPiS_i, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit58
leaq 80(%rsp), %r14
movq %r14, 64(%rsp)
movabsq $4993120287570814561, %rax # imm = 0x454B207265746661
movq %rax, 80(%rsp)
movl $1279610450, 88(%rsp) # imm = 0x4C454E52
movq $12, 72(%rsp)
movb $0, 92(%rsp)
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp7:
# %bb.9:
movq 64(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_11
# %bb.10: # %.critedge.i.i59
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit61
.cfi_escape 0x2e, 0x00
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $800, %edx # imm = 0x320
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %r14
movq %r14, 32(%rsp)
movabsq $7306844596132406881, %rax # imm = 0x6567207265746661
movq %rax, 48(%rsp)
movabsq $7022344665615918880, %rax # imm = 0x6174614474656720
movq %rax, 53(%rsp)
movq $13, 40(%rsp)
movb $0, 61(%rsp)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq _Z14cudaPrintErrorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp10:
# %bb.12:
movq 32(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_14
# %bb.13: # %.critedge.i.i69
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_14: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit71.preheader
xorl %r14d, %r14d
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_29: # in Loop: Header=BB2_15 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_15 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $200, %r14
je .LBB2_31
.LBB2_15: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit71
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx,%r14,4), %esi
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_16
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_15 Depth=1
cmpb $0, 56(%r15)
je .LBB2_29
# %bb.28: # in Loop: Header=BB2_15 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB2_30
.LBB2_31:
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_16:
.cfi_def_cfa_offset 288
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_25:
.Ltmp11:
movq %rax, %rbx
movq 32(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.26: # %.critedge.i.i75
.cfi_escape 0x2e, 0x00
jmp .LBB2_19
.LBB2_23:
.Ltmp8:
movq %rax, %rbx
movq 64(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.24: # %.critedge.i.i72
.cfi_escape 0x2e, 0x00
jmp .LBB2_19
.LBB2_21:
.Ltmp5:
movq %rax, %rbx
movq 96(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.22: # %.critedge.i.i49
.cfi_escape 0x2e, 0x00
jmp .LBB2_19
.LBB2_17:
.Ltmp2:
movq %rax, %rbx
movq 128(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.18: # %.critedge.i.i46
.cfi_escape 0x2e, 0x00
.LBB2_19: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit48
callq _ZdlPv
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit48
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end2-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6assignPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6assignPiS_i,@object # @_Z6assignPiS_i
.section .rodata,"a",@progbits
.globl _Z6assignPiS_i
.p2align 3, 0x0
_Z6assignPiS_i:
.quad _Z21__device_stub__assignPiS_i
.size _Z6assignPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " : "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "after GPU1"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "after GPU2"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "after KERNEL"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "after getData"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " "
.size .L.str.5, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6assignPiS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__assignPiS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6assignPiS_i
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sgemm_kernel_B(const float *A, const float *B, float *C, int N, int M, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
} | code for sm_80
Function : _Z14sgemm_kernel_BPKfS0_Pfiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xbd0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xad0 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R5, c[0x0][0x180], RZ ; /* 0x0000600005067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R7, R3, c[0x0][0x180], RZ ; /* 0x0000600003077a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fcc00078e0209 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020e */
/*0230*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc600078e0208 */
/*0250*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004040e127981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R22, R0.reuse, 0x4, R8 ; /* 0x0000000400167825 */
/* 0x040fe200078e0208 */
/*0270*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0000e8000c1e1900 */
/*0280*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000322000c1e1900 */
/*0290*/ IMAD.WIDE R26, R0, 0x4, R22 ; /* 0x00000004001a7825 */
/* 0x000fc600078e0216 */
/*02a0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008040e1d7981 */
/* 0x000f26000c1e1900 */
/*02b0*/ IMAD.WIDE R12, R0.reuse, 0x4, R26 ; /* 0x00000004000c7825 */
/* 0x040fe200078e021a */
/*02c0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b28000c1e1900 */
/*02d0*/ LDG.E R17, [R14.64+0xc] ; /* 0x00000c040e117981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R20, [R14.64+0x10] ; /* 0x000010040e147981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R8, [R14.64+0x14] ; /* 0x000014040e087981 */
/* 0x001f28000c1e1900 */
/*0310*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c040e1a7981 */
/* 0x020f62000c1e1900 */
/*0320*/ IMAD.WIDE R12, R0, 0x4, R12 ; /* 0x00000004000c7825 */
/* 0x002fca00078e020c */
/*0330*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000562000c1e1900 */
/*0340*/ IMAD.WIDE R22, R0, 0x4, R12 ; /* 0x0000000400167825 */
/* 0x000fc800078e020c */
/*0350*/ FFMA R12, R11, R10, R24 ; /* 0x0000000a0b0c7223 */
/* 0x004fe40000000018 */
/*0360*/ LDG.E R10, [R14.64+0x18] ; /* 0x000018040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000a8000c1e1900 */
/*0390*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x0002a2000c1e1900 */
/*03a0*/ FFMA R12, R19, R18, R12 ; /* 0x00000012130c7223 */
/* 0x008fe4000000000c */
/*03b0*/ IMAD.WIDE R18, R0, 0x4, R24 ; /* 0x0000000400127825 */
/* 0x000fe200078e0218 */
/*03c0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x001ee6000c1e1900 */
/*03d0*/ FFMA R28, R28, R29, R12 ; /* 0x0000001d1c1c7223 */
/* 0x010fc4000000000c */
/*03e0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*03f0*/ LDG.E R25, [R14.64+0x24] ; /* 0x000024040e197981 */
/* 0x002f26000c1e1900 */
/*0400*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x000fe2000000001c */
/*0410*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0420*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0430*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000322000c1e1900 */
/*0440*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0450*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e2000c1e1900 */
/*0460*/ IMAD.WIDE R20, R0, 0x4, R16 ; /* 0x0000000400147825 */
/* 0x000fc600078e0210 */
/*0470*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028040e1d7981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R19, [R14.64+0x2c] ; /* 0x00002c040e137981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000f22000c1e1900 */
/*04a0*/ FFMA R28, R9, R8, R28 ; /* 0x00000008091c7223 */
/* 0x020fe4000000001c */
/*04b0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x000fc400078e0214 */
/*04c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R21, [R14.64+0x38] ; /* 0x000038040e157981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R28, R11, R10, R28 ; /* 0x0000000a0b1c7223 */
/* 0x004fe4000000001c */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe400078e0208 */
/*0500*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R13, R27, R26, R28 ; /* 0x0000001a1b0d7223 */
/* 0x002fc4000000001c */
/*0520*/ IMAD.WIDE R26, R0.reuse, 0x4, R10 ; /* 0x00000004001a7825 */
/* 0x040fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002a8000c1e1900 */
/*0540*/ LDG.E R9, [R14.64+0x34] ; /* 0x000034040e097981 */
/* 0x001ea2000c1e1900 */
/*0550*/ IMAD.WIDE R16, R0, 0x4, R26 ; /* 0x0000000400107825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x0000a8000c1e1900 */
/*0570*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x002ea8000c1e1900 */
/*0580*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c040e1a7981 */
/* 0x001ea2000c1e1900 */
/*0590*/ FFMA R13, R18, R23, R13 ; /* 0x00000017120d7223 */
/* 0x008fc8000000000d */
/*05a0*/ FFMA R12, R12, R25, R13 ; /* 0x000000190c0c7223 */
/* 0x010fe2000000000d */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ FFMA R12, R22, R29, R12 ; /* 0x0000001d160c7223 */
/* 0x000fe2000000000c */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*05e0*/ FFMA R19, R20, R19, R12 ; /* 0x0000001314137223 */
/* 0x020fe2000000000c */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R8, R8, R24, R19 ; /* 0x0000001808087223 */
/* 0x004fc80000000013 */
/*0630*/ FFMA R8, R10, R9, R8 ; /* 0x000000090a087223 */
/* 0x000fc80000000008 */
/*0640*/ FFMA R8, R28, R21, R8 ; /* 0x000000151c087223 */
/* 0x000fc80000000008 */
/*0650*/ FFMA R24, R11, R26, R8 ; /* 0x0000001a0b187223 */
/* 0x000fe40000000008 */
/*0660*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fe200078e0210 */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fe200078e0208 */
/*06b0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0.reuse, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x040fe400078e0210 */
/*06f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e4000c1e1900 */
/*0700*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*0710*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000964000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe400078e020c */
/*0730*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R20, R0.reuse, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x040fe200078e0212 */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x001fc600078e0214 */
/*07b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07c0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0208 */
/*07e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f28000c1e1900 */
/*0800*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000328000c1e1900 */
/*0810*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001f28000c1e1900 */
/*0820*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f28000c1e1900 */
/*0830*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08a0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08b0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08c0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08d0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*08e0*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x010fc80000000012 */
/*08f0*/ FFMA R8, R17, R8, R15 ; /* 0x0000000811087223 */
/* 0x000fc8000000000f */
/*0900*/ FFMA R24, R9, R19, R8 ; /* 0x0000001309187223 */
/* 0x000fe40000000008 */
/*0910*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0208 */
/*0960*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0990*/ IMAD.WIDE R14, R0.reuse, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020a */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*09d0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0a80*/ FFMA R18, R11, R19, R18 ; /* 0x000000130b127223 */
/* 0x008fe40000000012 */
/*0a90*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fc800078e0210 */
/*0aa0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ab0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbd0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b00*/ IMAD R6, R3, c[0x0][0x180], R4 ; /* 0x0000600003067a24 */
/* 0x000fe400078e0204 */
/*0b10*/ IMAD R4, R4, c[0x0][0x180], R2 ; /* 0x0000600004047a24 */
/* 0x000fce00078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b30*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b40*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b50*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b60*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b70*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b80*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0b90*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R24, R11, R4, R24 ; /* 0x000000040b187223 */
/* 0x004fcc0000000018 */
/*0bc0*/ @P0 BRA 0xb40 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bd0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*0be0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fc800078e0202 */
/*0bf0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0c00*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0c10*/ FMUL R5, R0, c[0x0][0x188] ; /* 0x0000620000057a20 */
/* 0x004fc80000400000 */
/*0c20*/ FFMA R5, R24, c[0x0][0x184], R5 ; /* 0x0000610018057a23 */
/* 0x000fca0000000005 */
/*0c30*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sgemm_kernel_B(const float *A, const float *B, float *C, int N, int M, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
} | .file "tmpxft_0012fe85_00000000-6_sgemm_kernel_B.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff
.type _Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff, @function
_Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14sgemm_kernel_BPKfS0_Pfiiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff, .-_Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff
.globl _Z14sgemm_kernel_BPKfS0_Pfiiiff
.type _Z14sgemm_kernel_BPKfS0_Pfiiiff, @function
_Z14sgemm_kernel_BPKfS0_Pfiiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sgemm_kernel_BPKfS0_Pfiiiff, .-_Z14sgemm_kernel_BPKfS0_Pfiiiff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14sgemm_kernel_BPKfS0_Pfiiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sgemm_kernel_BPKfS0_Pfiiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sgemm_kernel_B(const float *A, const float *B, float *C, int N, int M, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sgemm_kernel_B(const float *A, const float *B, float *C, int N, int M, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sgemm_kernel_B(const float *A, const float *B, float *C, int N, int M, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sgemm_kernel_BPKfS0_Pfiiiff
.globl _Z14sgemm_kernel_BPKfS0_Pfiiiff
.p2align 8
.type _Z14sgemm_kernel_BPKfS0_Pfiiiff,@function
_Z14sgemm_kernel_BPKfS0_Pfiiiff:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sgemm_kernel_BPKfS0_Pfiiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sgemm_kernel_BPKfS0_Pfiiiff, .Lfunc_end0-_Z14sgemm_kernel_BPKfS0_Pfiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sgemm_kernel_BPKfS0_Pfiiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sgemm_kernel_BPKfS0_Pfiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sgemm_kernel_B(const float *A, const float *B, float *C, int N, int M, int K, float alpha, float beta)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
float sum = 0.f;
for (int i = 0; i < K; ++i)
sum += A[row * K + i] * B[i * K + col];
C[row * M + col] = alpha * sum + beta * C[row * M + col];
} | .text
.file "sgemm_kernel_B.hip"
.globl _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff # -- Begin function _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.p2align 4, 0x90
.type _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff,@function
_Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff: # @_Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14sgemm_kernel_BPKfS0_Pfiiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff, .Lfunc_end0-_Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sgemm_kernel_BPKfS0_Pfiiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sgemm_kernel_BPKfS0_Pfiiiff,@object # @_Z14sgemm_kernel_BPKfS0_Pfiiiff
.section .rodata,"a",@progbits
.globl _Z14sgemm_kernel_BPKfS0_Pfiiiff
.p2align 3, 0x0
_Z14sgemm_kernel_BPKfS0_Pfiiiff:
.quad _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.size _Z14sgemm_kernel_BPKfS0_Pfiiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sgemm_kernel_BPKfS0_Pfiiiff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sgemm_kernel_BPKfS0_Pfiiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14sgemm_kernel_BPKfS0_Pfiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xbd0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xad0 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R5, c[0x0][0x180], RZ ; /* 0x0000600005067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R7, R3, c[0x0][0x180], RZ ; /* 0x0000600003077a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fcc00078e0209 */
/*01a0*/ @!P0 BRA 0x940 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x680 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020e */
/*0230*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc600078e0208 */
/*0250*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004040e127981 */
/* 0x000ee6000c1e1900 */
/*0260*/ IMAD.WIDE R22, R0.reuse, 0x4, R8 ; /* 0x0000000400167825 */
/* 0x040fe200078e0208 */
/*0270*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0000e8000c1e1900 */
/*0280*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000322000c1e1900 */
/*0290*/ IMAD.WIDE R26, R0, 0x4, R22 ; /* 0x00000004001a7825 */
/* 0x000fc600078e0216 */
/*02a0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008040e1d7981 */
/* 0x000f26000c1e1900 */
/*02b0*/ IMAD.WIDE R12, R0.reuse, 0x4, R26 ; /* 0x00000004000c7825 */
/* 0x040fe200078e021a */
/*02c0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b28000c1e1900 */
/*02d0*/ LDG.E R17, [R14.64+0xc] ; /* 0x00000c040e117981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R20, [R14.64+0x10] ; /* 0x000010040e147981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R8, [R14.64+0x14] ; /* 0x000014040e087981 */
/* 0x001f28000c1e1900 */
/*0310*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c040e1a7981 */
/* 0x020f62000c1e1900 */
/*0320*/ IMAD.WIDE R12, R0, 0x4, R12 ; /* 0x00000004000c7825 */
/* 0x002fca00078e020c */
/*0330*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000562000c1e1900 */
/*0340*/ IMAD.WIDE R22, R0, 0x4, R12 ; /* 0x0000000400167825 */
/* 0x000fc800078e020c */
/*0350*/ FFMA R12, R11, R10, R24 ; /* 0x0000000a0b0c7223 */
/* 0x004fe40000000018 */
/*0360*/ LDG.E R10, [R14.64+0x18] ; /* 0x000018040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000a8000c1e1900 */
/*0390*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x0002a2000c1e1900 */
/*03a0*/ FFMA R12, R19, R18, R12 ; /* 0x00000012130c7223 */
/* 0x008fe4000000000c */
/*03b0*/ IMAD.WIDE R18, R0, 0x4, R24 ; /* 0x0000000400127825 */
/* 0x000fe200078e0218 */
/*03c0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x001ee6000c1e1900 */
/*03d0*/ FFMA R28, R28, R29, R12 ; /* 0x0000001d1c1c7223 */
/* 0x010fc4000000000c */
/*03e0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*03f0*/ LDG.E R25, [R14.64+0x24] ; /* 0x000024040e197981 */
/* 0x002f26000c1e1900 */
/*0400*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x000fe2000000001c */
/*0410*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0420*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0430*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000322000c1e1900 */
/*0440*/ FFMA R28, R21, R20, R28 ; /* 0x00000014151c7223 */
/* 0x000fc6000000001c */
/*0450*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e2000c1e1900 */
/*0460*/ IMAD.WIDE R20, R0, 0x4, R16 ; /* 0x0000000400147825 */
/* 0x000fc600078e0210 */
/*0470*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028040e1d7981 */
/* 0x000f28000c1e1900 */
/*0480*/ LDG.E R19, [R14.64+0x2c] ; /* 0x00002c040e137981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000f22000c1e1900 */
/*04a0*/ FFMA R28, R9, R8, R28 ; /* 0x00000008091c7223 */
/* 0x020fe4000000001c */
/*04b0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x000fc400078e0214 */
/*04c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R21, [R14.64+0x38] ; /* 0x000038040e157981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R28, R11, R10, R28 ; /* 0x0000000a0b1c7223 */
/* 0x004fe4000000001c */
/*04f0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe400078e0208 */
/*0500*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R13, R27, R26, R28 ; /* 0x0000001a1b0d7223 */
/* 0x002fc4000000001c */
/*0520*/ IMAD.WIDE R26, R0.reuse, 0x4, R10 ; /* 0x00000004001a7825 */
/* 0x040fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002a8000c1e1900 */
/*0540*/ LDG.E R9, [R14.64+0x34] ; /* 0x000034040e097981 */
/* 0x001ea2000c1e1900 */
/*0550*/ IMAD.WIDE R16, R0, 0x4, R26 ; /* 0x0000000400107825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x0000a8000c1e1900 */
/*0570*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x002ea8000c1e1900 */
/*0580*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c040e1a7981 */
/* 0x001ea2000c1e1900 */
/*0590*/ FFMA R13, R18, R23, R13 ; /* 0x00000017120d7223 */
/* 0x008fc8000000000d */
/*05a0*/ FFMA R12, R12, R25, R13 ; /* 0x000000190c0c7223 */
/* 0x010fe2000000000d */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ FFMA R12, R22, R29, R12 ; /* 0x0000001d160c7223 */
/* 0x000fe2000000000c */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*05e0*/ FFMA R19, R20, R19, R12 ; /* 0x0000001314137223 */
/* 0x020fe2000000000c */
/*05f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0600*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0620*/ FFMA R8, R8, R24, R19 ; /* 0x0000001808087223 */
/* 0x004fc80000000013 */
/*0630*/ FFMA R8, R10, R9, R8 ; /* 0x000000090a087223 */
/* 0x000fc80000000008 */
/*0640*/ FFMA R8, R28, R21, R8 ; /* 0x000000151c087223 */
/* 0x000fc80000000008 */
/*0650*/ FFMA R24, R11, R26, R8 ; /* 0x0000001a0b187223 */
/* 0x000fe40000000008 */
/*0660*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fe200078e0210 */
/*0670*/ @P1 BRA 0x1f0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0690*/ @!P1 BRA 0x920 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fe200078e0208 */
/*06b0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fc60008000f00 */
/*06e0*/ IMAD.WIDE R12, R0.reuse, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x040fe400078e0210 */
/*06f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e4000c1e1900 */
/*0700*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*0710*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000964000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe400078e020c */
/*0730*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0760*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R20, R0.reuse, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x040fe200078e0212 */
/*0780*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0790*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R8, R0, 0x4, R20 ; /* 0x0000000400087825 */
/* 0x001fc600078e0214 */
/*07b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07c0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0208 */
/*07e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f28000c1e1900 */
/*0800*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000328000c1e1900 */
/*0810*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001f28000c1e1900 */
/*0820*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f28000c1e1900 */
/*0830*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000f22000c1e1900 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0860*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0880*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0890*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08a0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08b0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08c0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08d0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*08e0*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x010fc80000000012 */
/*08f0*/ FFMA R8, R17, R8, R15 ; /* 0x0000000811087223 */
/* 0x000fc8000000000f */
/*0900*/ FFMA R24, R9, R19, R8 ; /* 0x0000001309187223 */
/* 0x000fe40000000008 */
/*0910*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*0920*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0930*/ @!P0 BRA 0xad0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0940*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0950*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0208 */
/*0960*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*0970*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0980*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0990*/ IMAD.WIDE R14, R0.reuse, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020a */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*09d0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x000ee8000c1e1900 */
/*09e0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000f28000c1e1900 */
/*0a00*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000f68000c1e1900 */
/*0a10*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000f62000c1e1900 */
/*0a20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a70*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0a80*/ FFMA R18, R11, R19, R18 ; /* 0x000000130b127223 */
/* 0x008fe40000000012 */
/*0a90*/ IMAD.WIDE R8, R0, 0x4, R16 ; /* 0x0000000400087825 */
/* 0x000fc800078e0210 */
/*0aa0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ab0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0ac0*/ @P0 BRA 0x940 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xbd0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b00*/ IMAD R6, R3, c[0x0][0x180], R4 ; /* 0x0000600003067a24 */
/* 0x000fe400078e0204 */
/*0b10*/ IMAD R4, R4, c[0x0][0x180], R2 ; /* 0x0000600004047a24 */
/* 0x000fce00078e0202 */
/*0b20*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b30*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b40*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b50*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b60*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b70*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b80*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0b90*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R24, R11, R4, R24 ; /* 0x000000040b187223 */
/* 0x004fcc0000000018 */
/*0bc0*/ @P0 BRA 0xb40 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bd0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*0be0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fc800078e0202 */
/*0bf0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0205 */
/*0c00*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0c10*/ FMUL R5, R0, c[0x0][0x188] ; /* 0x0000620000057a20 */
/* 0x004fc80000400000 */
/*0c20*/ FFMA R5, R24, c[0x0][0x184], R5 ; /* 0x0000610018057a23 */
/* 0x000fca0000000005 */
/*0c30*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sgemm_kernel_BPKfS0_Pfiiiff
.globl _Z14sgemm_kernel_BPKfS0_Pfiiiff
.p2align 8
.type _Z14sgemm_kernel_BPKfS0_Pfiiiff,@function
_Z14sgemm_kernel_BPKfS0_Pfiiiff:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sgemm_kernel_BPKfS0_Pfiiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sgemm_kernel_BPKfS0_Pfiiiff, .Lfunc_end0-_Z14sgemm_kernel_BPKfS0_Pfiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sgemm_kernel_BPKfS0_Pfiiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sgemm_kernel_BPKfS0_Pfiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012fe85_00000000-6_sgemm_kernel_B.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff
.type _Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff, @function
_Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14sgemm_kernel_BPKfS0_Pfiiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff, .-_Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff
.globl _Z14sgemm_kernel_BPKfS0_Pfiiiff
.type _Z14sgemm_kernel_BPKfS0_Pfiiiff, @function
_Z14sgemm_kernel_BPKfS0_Pfiiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14sgemm_kernel_BPKfS0_PfiiiffPKfS0_Pfiiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sgemm_kernel_BPKfS0_Pfiiiff, .-_Z14sgemm_kernel_BPKfS0_Pfiiiff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14sgemm_kernel_BPKfS0_Pfiiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sgemm_kernel_BPKfS0_Pfiiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sgemm_kernel_B.hip"
.globl _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff # -- Begin function _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.p2align 4, 0x90
.type _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff,@function
_Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff: # @_Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14sgemm_kernel_BPKfS0_Pfiiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff, .Lfunc_end0-_Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sgemm_kernel_BPKfS0_Pfiiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sgemm_kernel_BPKfS0_Pfiiiff,@object # @_Z14sgemm_kernel_BPKfS0_Pfiiiff
.section .rodata,"a",@progbits
.globl _Z14sgemm_kernel_BPKfS0_Pfiiiff
.p2align 3, 0x0
_Z14sgemm_kernel_BPKfS0_Pfiiiff:
.quad _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.size _Z14sgemm_kernel_BPKfS0_Pfiiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sgemm_kernel_BPKfS0_Pfiiiff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sgemm_kernel_BPKfS0_Pfiiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sgemm_kernel_BPKfS0_Pfiiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// helper for CUDA error handling
__global__ void getMeanImage( const double* images, double* meanImage, std::size_t imageNum, std::size_t pixelNum )
{
std::size_t col = blockIdx.x * blockDim.x + threadIdx.x;
if(col >= pixelNum)
{
return;
}
meanImage[col] = 0.0;
for(std::size_t row = 0; row < imageNum; ++row)
{
meanImage[col] += images[row*pixelNum + col];
}
meanImage[col] /= imageNum;
} | code for sm_80
Function : _Z12getMeanImagePKdPdmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R8, R4, 0x8, RZ ; /* 0x0000000804087824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R11, RZ, 0x1d, R4 ; /* 0x0000001dff0b7819 */
/* 0x000fe20000011604 */
/*0090*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe4000001ff00 */
/*00b0*/ IADD3 R2, P0, R8, c[0x0][0x168], RZ ; /* 0x00005a0008027a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R3, R11, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000b037a10 */
/* 0x000fe400007fe4ff */
/*00d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc60003f05070 */
/*00e0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101b0a */
/*00f0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f05300 */
/*0100*/ @!P0 BRA 0x5e0 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x001fe200078e00ff */
/*0120*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0130*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff097624 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3 ; /* 0x00000003ff007424 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R7, P0, -R7, c[0x0][0x170], RZ ; /* 0x00005c0007077a10 */
/* 0x000fc80007f1e1ff */
/*0160*/ ISETP.GE.U32.AND P1, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f26070 */
/*0170*/ IADD3.X R7, R9, -0x1, RZ, P0, !PT ; /* 0xffffffff09077810 */
/* 0x000fe200007fe4ff */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0190*/ LOP3.LUT R6, R0, c[0x0][0x170], RZ, 0xc0, !PT ; /* 0x00005c0000067a12 */
/* 0x000fe400078ec0ff */
/*01a0*/ ISETP.GE.U32.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fe20003f26110 */
/*01b0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*01c0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05070 */
/*01d0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fce0003f05300 */
/*01e0*/ @!P1 BRA 0x460 ; /* 0x0000027000009947 */
/* 0x000fec0003800000 */
/*01f0*/ IADD3 R10, P2, R6, -c[0x0][0x170], RZ ; /* 0x80005c00060a7a10 */
/* 0x000fe20007f5e0ff */
/*0200*/ UMOV UR6, 0x8 ; /* 0x0000000800067882 */
/* 0x000fe20000000000 */
/*0210*/ IADD3 R22, P1, R8, c[0x0][0x160], RZ ; /* 0x0000580008167a10 */
/* 0x000fe20007f3e0ff */
/*0220*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe20000000a00 */
/*0230*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0240*/ UIMAD.WIDE.U32 UR4, UR6, UR8, URZ ; /* 0x00000008060472a5 */
/* 0x000fe2000f8e003f */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0260*/ UIMAD UR6, UR6, UR9, URZ ; /* 0x00000009060672a4 */
/* 0x000fe2000f8e023f */
/*0270*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0280*/ IADD3.X R23, R11, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000b177a10 */
/* 0x000fe20000ffe4ff */
/*0290*/ IMAD.X R8, RZ, RZ, ~c[0x0][0x174], P2 ; /* 0x80005d00ff087624 */
/* 0x000fe200010e06ff */
/*02a0*/ UIADD3 UR6, UR5, UR6, URZ ; /* 0x0000000605067290 */
/* 0x000fc6000fffe03f */
/*02b0*/ LDG.E.64 R14, [R22.64] ; /* 0x0000000a160e7981 */
/* 0x000ea2000c1e1b00 */
/*02c0*/ IADD3 R16, P1, R22, UR4, RZ ; /* 0x0000000416107c10 */
/* 0x000fc8000ff3e0ff */
/*02d0*/ IADD3.X R17, R23, UR6, RZ, P1, !PT ; /* 0x0000000617117c10 */
/* 0x000fe20008ffe4ff */
/*02e0*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x006e0e000000000c */
/*02f0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b0a */
/*0300*/ LDG.E.64 R14, [R16.64] ; /* 0x0000000a100e7981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ IADD3 R24, P1, R16, UR4, RZ ; /* 0x0000000410187c10 */
/* 0x000fc8000ff3e0ff */
/*0320*/ IADD3.X R25, R17, UR6, RZ, P1, !PT ; /* 0x0000000611197c10 */
/* 0x000fe20008ffe4ff */
/*0330*/ DADD R18, R12, R14 ; /* 0x000000000c127229 */
/* 0x004e4e000000000e */
/*0340*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0023e8000c101b0a */
/*0350*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000a18147981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ IADD3 R14, P1, R24, UR4, RZ ; /* 0x00000004180e7c10 */
/* 0x000fc8000ff3e0ff */
/*0370*/ IADD3.X R15, R25, UR6, RZ, P1, !PT ; /* 0x00000006190f7c10 */
/* 0x000fe20008ffe4ff */
/*0380*/ DADD R20, R18, R20 ; /* 0x0000000012147229 */
/* 0x004e8e0000000014 */
/*0390*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0043e8000c101b0a */
/*03a0*/ LDG.E.64 R12, [R14.64] ; /* 0x0000000a0e0c7981 */
/* 0x001ea2000c1e1b00 */
/*03b0*/ IADD3 R7, P1, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc80007f3e0ff */
/*03c0*/ IADD3 R11, P2, R7, R10, RZ ; /* 0x0000000a070b7210 */
/* 0x000fe20007f5e0ff */
/*03d0*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fc600008e0609 */
/*03e0*/ ISETP.NE.U32.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25070 */
/*03f0*/ IMAD.X R11, R9, 0x1, R8, P2 ; /* 0x00000001090b7824 */
/* 0x000fe200010e0608 */
/*0400*/ IADD3 R22, P2, R14, UR4, RZ ; /* 0x000000040e167c10 */
/* 0x000fc8000ff5e0ff */
/*0410*/ ISETP.NE.AND.EX P1, PT, R11, RZ, PT, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe40003f25310 */
/*0420*/ IADD3.X R23, R15, UR6, RZ, P2, !PT ; /* 0x000000060f177c10 */
/* 0x000fe200097fe4ff */
/*0430*/ DADD R12, R20, R12 ; /* 0x00000000140c7229 */
/* 0x004e0e000000000c */
/*0440*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0013e6000c101b0a */
/*0450*/ @P1 BRA 0x2b0 ; /* 0xfffffe5000001947 */
/* 0x000fea000383ffff */
/*0460*/ @!P0 BRA 0x5e0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD R8, R9, c[0x0][0x178], RZ ; /* 0x00005e0009087a24 */
/* 0x000fe200078e02ff */
/*0480*/ IADD3 R6, P1, RZ, -R6, RZ ; /* 0x80000006ff067210 */
/* 0x000fe20007f3e0ff */
/*0490*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*04a0*/ IMAD R9, R7.reuse, c[0x0][0x17c], R8 ; /* 0x00005f0007097a24 */
/* 0x040fe400078e0208 */
/*04b0*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x178], R4 ; /* 0x00005e0007047a25 */
/* 0x000fc800078e0004 */
/*04c0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0a7624 */
/* 0x000fe200078e00ff */
/*04d0*/ LEA R7, P0, R4, c[0x0][0x160], 0x3 ; /* 0x0000580004077a11 */
/* 0x000fe200078018ff */
/*04e0*/ IMAD.IADD R5, R5, 0x1, R9 ; /* 0x0000000105057824 */
/* 0x000fc600078e0209 */
/*04f0*/ SHF.L.U64.HI R9, R10, R0, c[0x0][0x17c] ; /* 0x00005f000a097619 */
/* 0x000fe20000010200 */
/*0500*/ IMAD.X R0, RZ, RZ, -0x1, P1 ; /* 0xffffffffff007424 */
/* 0x000fe200008e06ff */
/*0510*/ LEA.HI.X R8, R4, c[0x0][0x164], R5, 0x3, P0 ; /* 0x0000590004087a11 */
/* 0x000fc600000f1c05 */
/*0520*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0007 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0008 */
/*0540*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000a04047981 */
/* 0x000ea2000c1e1b00 */
/*0550*/ IADD3 R6, P0, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007f1e0ff */
/*0560*/ LEA R7, P1, R10, R7, 0x3 ; /* 0x000000070a077211 */
/* 0x000fc600078218ff */
/*0570*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*0580*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05070 */
/*0590*/ IMAD.X R8, R8, 0x1, R9, P1 ; /* 0x0000000108087824 */
/* 0x000fc600008e0609 */
/*05a0*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*05b0*/ DADD R12, R4, R12 ; /* 0x00000000040c7229 */
/* 0x007e0e000000000c */
/*05c0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011ea000c101b0a */
/*05d0*/ @P0 BRA 0x520 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*05e0*/ I2F.F64.U64 R8, c[0x0][0x170] ; /* 0x00005c0000087b12 */
/* 0x001e220000301800 */
/*05f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0600*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe20003f2e200 */
/*0610*/ BSSY B0, 0x750 ; /* 0x0000013000007945 */
/* 0x000fea0003800000 */
/*0620*/ MUFU.RCP64H R5, R9 ; /* 0x0000000900057308 */
/* 0x001e240000001800 */
/*0630*/ DFMA R6, -R8, R4, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c0000000104 */
/*0640*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0650*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*0660*/ DFMA R4, -R8, R6, 1 ; /* 0x3ff000000804742b */
/* 0x001e0c0000000106 */
/*0670*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e0c0000000006 */
/*0680*/ DMUL R6, R4, R12 ; /* 0x0000000c04067228 */
/* 0x001e0c0000000000 */
/*0690*/ DFMA R10, -R8, R6, R12 ; /* 0x00000006080a722b */
/* 0x001e0c000000010c */
/*06a0*/ DFMA R4, R4, R10, R6 ; /* 0x0000000a0404722b */
/* 0x001e140000000006 */
/*06b0*/ FFMA R0, RZ, R9, R5 ; /* 0x00000009ff007223 */
/* 0x001fca0000000005 */
/*06c0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*06d0*/ @P0 BRA P1, 0x740 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*06e0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*06f0*/ MOV R0, 0x720 ; /* 0x0000072000007802 */
/* 0x000fe20000000f00 */
/*0700*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000d */
/*0710*/ CALL.REL.NOINC 0x770 ; /* 0x0000005000007944 */
/* 0x002fea0003c00000 */
/*0720*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0730*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0740*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0750*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b0a */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0780*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0790*/ LOP3.LUT R4, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x000fe200078ec0ff */
/*07a0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*07b0*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*07c0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*07d0*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*07e0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*07f0*/ LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070c7812 */
/* 0x000fe200078ec0ff */
/*0800*/ BSSY B1, 0xd10 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*0810*/ LOP3.LUT R15, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090f7812 */
/* 0x000fc600078ec0ff */
/*0820*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e220000000000 */
/*0830*/ ISETP.GE.U32.AND P1, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fc60003f26070 */
/*0840*/ @!P2 LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ba812 */
/* 0x000fe200078ec0ff */
/*0850*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0860*/ MUFU.RCP64H R17, R5 ; /* 0x0000000500117308 */
/* 0x001e240000001800 */
/*0870*/ @!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ; /* 0x0000000b0c00a20c */
/* 0x000fe40003f66070 */
/*0880*/ SEL R11, R13.reuse, 0x63400000, !P1 ; /* 0x634000000d0b7807 */
/* 0x040fe40004800000 */
/*0890*/ @!P2 SEL R21, R13, 0x63400000, !P3 ; /* 0x634000000d15a807 */
/* 0x000fe40005800000 */
/*08a0*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef807 */
/*08b0*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef807 */
/*08c0*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*08d0*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x001e0a0000000804 */
/*08e0*/ @!P2 DFMA R10, R10, 2, -R20 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000814 */
/*08f0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0900*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x0010640000000010 */
/*0910*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x001fe200078e000c */
/*0920*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*0930*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*0940*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*0950*/ DFMA R20, R18, -R4, 1 ; /* 0x3ff000001214742b */
/* 0x002e060000000804 */
/*0960*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fc60007ffe0ff */
/*0970*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*0980*/ IADD3 R20, R16, -0x1, RZ ; /* 0xffffffff10147810 */
/* 0x001fc80007ffe0ff */
/*0990*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*09a0*/ DMUL R14, R18, R10 ; /* 0x0000000a120e7228 */
/* 0x002e060000000000 */
/*09b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*09c0*/ DFMA R20, R14, -R4, R10 ; /* 0x800000040e14722b */
/* 0x001e0c000000000a */
/*09d0*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x001048000000000e */
/*09e0*/ @P0 BRA 0xbb0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*09f0*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x003fc800078ec0ff */
/*0a00*/ ISETP.GE.U32.AND P0, PT, R12.reuse, R7, PT ; /* 0x000000070c00720c */
/* 0x040fe20003f06070 */
/*0a10*/ IMAD.IADD R6, R12, 0x1, -R7 ; /* 0x000000010c067824 */
/* 0x000fc600078e0a07 */
/*0a20*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe40004000000 */
/*0a30*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0a40*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0a50*/ IMAD.IADD R16, R6, 0x1, -R13 ; /* 0x0000000106107824 */
/* 0x000fe400078e0a0d */
/*0a60*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0a70*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*0a80*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*0a90*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0aa0*/ @P0 BRA 0xd00 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0ab0*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e22000000000a */
/*0ac0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0ad0*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0ae0*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*0af0*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0b00*/ @!P0 BRA 0xd00 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0b10*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*0b20*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0b30*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0b40*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*0b50*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*0b60*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*0b70*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0b80*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*0b90*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0ba0*/ BRA 0xd00 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0bc0*/ @P0 BRA 0xce0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0bd0*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0be0*/ @P0 BRA 0xcb0 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0bf0*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0c10*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0c20*/ @!P0 BRA 0xd00 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0c30*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*0c40*/ LOP3.LUT R13, R7, 0x80000000, R9, 0x48, !PT ; /* 0x80000000070d7812 */
/* 0x000fe400078e4809 */
/*0c50*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*0c60*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*0c70*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0c80*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0c90*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*0ca0*/ BRA 0xd00 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0cc0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0cd0*/ BRA 0xd00 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0ce0*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0cf0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0d00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d10*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0d20*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0d30*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2c004007950 */
/* 0x000fea0003c3ffff */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// helper for CUDA error handling
__global__ void getMeanImage( const double* images, double* meanImage, std::size_t imageNum, std::size_t pixelNum )
{
std::size_t col = blockIdx.x * blockDim.x + threadIdx.x;
if(col >= pixelNum)
{
return;
}
meanImage[col] = 0.0;
for(std::size_t row = 0; row < imageNum; ++row)
{
meanImage[col] += images[row*pixelNum + col];
}
meanImage[col] /= imageNum;
} | .file "tmpxft_0010e20e_00000000-6_getMeanImage.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm
.type _Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm, @function
_Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12getMeanImagePKdPdmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm, .-_Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm
.globl _Z12getMeanImagePKdPdmm
.type _Z12getMeanImagePKdPdmm, @function
_Z12getMeanImagePKdPdmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12getMeanImagePKdPdmm, .-_Z12getMeanImagePKdPdmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12getMeanImagePKdPdmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12getMeanImagePKdPdmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// helper for CUDA error handling
__global__ void getMeanImage( const double* images, double* meanImage, std::size_t imageNum, std::size_t pixelNum )
{
std::size_t col = blockIdx.x * blockDim.x + threadIdx.x;
if(col >= pixelNum)
{
return;
}
meanImage[col] = 0.0;
for(std::size_t row = 0; row < imageNum; ++row)
{
meanImage[col] += images[row*pixelNum + col];
}
meanImage[col] /= imageNum;
} | #include <hip/hip_runtime.h>
#include "includes.h"
// helper for CUDA error handling
__global__ void getMeanImage( const double* images, double* meanImage, std::size_t imageNum, std::size_t pixelNum )
{
std::size_t col = blockIdx.x * blockDim.x + threadIdx.x;
if(col >= pixelNum)
{
return;
}
meanImage[col] = 0.0;
for(std::size_t row = 0; row < imageNum; ++row)
{
meanImage[col] += images[row*pixelNum + col];
}
meanImage[col] /= imageNum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// helper for CUDA error handling
__global__ void getMeanImage( const double* images, double* meanImage, std::size_t imageNum, std::size_t pixelNum )
{
std::size_t col = blockIdx.x * blockDim.x + threadIdx.x;
if(col >= pixelNum)
{
return;
}
meanImage[col] = 0.0;
for(std::size_t row = 0; row < imageNum; ++row)
{
meanImage[col] += images[row*pixelNum + col];
}
meanImage[col] /= imageNum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12getMeanImagePKdPdmm
.globl _Z12getMeanImagePKdPdmm
.p2align 8
.type _Z12getMeanImagePKdPdmm,@function
_Z12getMeanImagePKdPdmm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
s_cmp_eq_u64 s[6:7], 0
global_store_b64 v[0:1], v[2:3], off
s_cbranch_scc1 .LBB0_4
global_load_b64 v[2:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_lshl_b64 s[0:1], s[2:3], 3
s_mov_b64 s[2:3], s[6:7]
.LBB0_3:
global_load_b64 v[6:7], v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, s0
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[6:7], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_cbranch_scc0 .LBB0_3
.LBB0_4:
global_load_b64 v[2:3], v[0:1], off
v_cvt_f64_u32_e32 v[4:5], s7
v_cvt_f64_u32_e32 v[6:7], s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], 32
v_add_f64 v[4:5], v[4:5], v[6:7]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
v_mul_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12getMeanImagePKdPdmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12getMeanImagePKdPdmm, .Lfunc_end0-_Z12getMeanImagePKdPdmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12getMeanImagePKdPdmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12getMeanImagePKdPdmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// helper for CUDA error handling
__global__ void getMeanImage( const double* images, double* meanImage, std::size_t imageNum, std::size_t pixelNum )
{
std::size_t col = blockIdx.x * blockDim.x + threadIdx.x;
if(col >= pixelNum)
{
return;
}
meanImage[col] = 0.0;
for(std::size_t row = 0; row < imageNum; ++row)
{
meanImage[col] += images[row*pixelNum + col];
}
meanImage[col] /= imageNum;
} | .text
.file "getMeanImage.hip"
.globl _Z27__device_stub__getMeanImagePKdPdmm # -- Begin function _Z27__device_stub__getMeanImagePKdPdmm
.p2align 4, 0x90
.type _Z27__device_stub__getMeanImagePKdPdmm,@function
_Z27__device_stub__getMeanImagePKdPdmm: # @_Z27__device_stub__getMeanImagePKdPdmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12getMeanImagePKdPdmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__getMeanImagePKdPdmm, .Lfunc_end0-_Z27__device_stub__getMeanImagePKdPdmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12getMeanImagePKdPdmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12getMeanImagePKdPdmm,@object # @_Z12getMeanImagePKdPdmm
.section .rodata,"a",@progbits
.globl _Z12getMeanImagePKdPdmm
.p2align 3, 0x0
_Z12getMeanImagePKdPdmm:
.quad _Z27__device_stub__getMeanImagePKdPdmm
.size _Z12getMeanImagePKdPdmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12getMeanImagePKdPdmm"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__getMeanImagePKdPdmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12getMeanImagePKdPdmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12getMeanImagePKdPdmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R8, R4, 0x8, RZ ; /* 0x0000000804087824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R11, RZ, 0x1d, R4 ; /* 0x0000001dff0b7819 */
/* 0x000fe20000011604 */
/*0090*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe4000001ff00 */
/*00b0*/ IADD3 R2, P0, R8, c[0x0][0x168], RZ ; /* 0x00005a0008027a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R3, R11, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000b037a10 */
/* 0x000fe400007fe4ff */
/*00d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc60003f05070 */
/*00e0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101b0a */
/*00f0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f05300 */
/*0100*/ @!P0 BRA 0x5e0 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x001fe200078e00ff */
/*0120*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0130*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff097624 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3 ; /* 0x00000003ff007424 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R7, P0, -R7, c[0x0][0x170], RZ ; /* 0x00005c0007077a10 */
/* 0x000fc80007f1e1ff */
/*0160*/ ISETP.GE.U32.AND P1, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f26070 */
/*0170*/ IADD3.X R7, R9, -0x1, RZ, P0, !PT ; /* 0xffffffff09077810 */
/* 0x000fe200007fe4ff */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0190*/ LOP3.LUT R6, R0, c[0x0][0x170], RZ, 0xc0, !PT ; /* 0x00005c0000067a12 */
/* 0x000fe400078ec0ff */
/*01a0*/ ISETP.GE.U32.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fe20003f26110 */
/*01b0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*01c0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05070 */
/*01d0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fce0003f05300 */
/*01e0*/ @!P1 BRA 0x460 ; /* 0x0000027000009947 */
/* 0x000fec0003800000 */
/*01f0*/ IADD3 R10, P2, R6, -c[0x0][0x170], RZ ; /* 0x80005c00060a7a10 */
/* 0x000fe20007f5e0ff */
/*0200*/ UMOV UR6, 0x8 ; /* 0x0000000800067882 */
/* 0x000fe20000000000 */
/*0210*/ IADD3 R22, P1, R8, c[0x0][0x160], RZ ; /* 0x0000580008167a10 */
/* 0x000fe20007f3e0ff */
/*0220*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe20000000a00 */
/*0230*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0240*/ UIMAD.WIDE.U32 UR4, UR6, UR8, URZ ; /* 0x00000008060472a5 */
/* 0x000fe2000f8e003f */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0260*/ UIMAD UR6, UR6, UR9, URZ ; /* 0x00000009060672a4 */
/* 0x000fe2000f8e023f */
/*0270*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0280*/ IADD3.X R23, R11, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000b177a10 */
/* 0x000fe20000ffe4ff */
/*0290*/ IMAD.X R8, RZ, RZ, ~c[0x0][0x174], P2 ; /* 0x80005d00ff087624 */
/* 0x000fe200010e06ff */
/*02a0*/ UIADD3 UR6, UR5, UR6, URZ ; /* 0x0000000605067290 */
/* 0x000fc6000fffe03f */
/*02b0*/ LDG.E.64 R14, [R22.64] ; /* 0x0000000a160e7981 */
/* 0x000ea2000c1e1b00 */
/*02c0*/ IADD3 R16, P1, R22, UR4, RZ ; /* 0x0000000416107c10 */
/* 0x000fc8000ff3e0ff */
/*02d0*/ IADD3.X R17, R23, UR6, RZ, P1, !PT ; /* 0x0000000617117c10 */
/* 0x000fe20008ffe4ff */
/*02e0*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x006e0e000000000c */
/*02f0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b0a */
/*0300*/ LDG.E.64 R14, [R16.64] ; /* 0x0000000a100e7981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ IADD3 R24, P1, R16, UR4, RZ ; /* 0x0000000410187c10 */
/* 0x000fc8000ff3e0ff */
/*0320*/ IADD3.X R25, R17, UR6, RZ, P1, !PT ; /* 0x0000000611197c10 */
/* 0x000fe20008ffe4ff */
/*0330*/ DADD R18, R12, R14 ; /* 0x000000000c127229 */
/* 0x004e4e000000000e */
/*0340*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0023e8000c101b0a */
/*0350*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000a18147981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ IADD3 R14, P1, R24, UR4, RZ ; /* 0x00000004180e7c10 */
/* 0x000fc8000ff3e0ff */
/*0370*/ IADD3.X R15, R25, UR6, RZ, P1, !PT ; /* 0x00000006190f7c10 */
/* 0x000fe20008ffe4ff */
/*0380*/ DADD R20, R18, R20 ; /* 0x0000000012147229 */
/* 0x004e8e0000000014 */
/*0390*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0043e8000c101b0a */
/*03a0*/ LDG.E.64 R12, [R14.64] ; /* 0x0000000a0e0c7981 */
/* 0x001ea2000c1e1b00 */
/*03b0*/ IADD3 R7, P1, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc80007f3e0ff */
/*03c0*/ IADD3 R11, P2, R7, R10, RZ ; /* 0x0000000a070b7210 */
/* 0x000fe20007f5e0ff */
/*03d0*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fc600008e0609 */
/*03e0*/ ISETP.NE.U32.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25070 */
/*03f0*/ IMAD.X R11, R9, 0x1, R8, P2 ; /* 0x00000001090b7824 */
/* 0x000fe200010e0608 */
/*0400*/ IADD3 R22, P2, R14, UR4, RZ ; /* 0x000000040e167c10 */
/* 0x000fc8000ff5e0ff */
/*0410*/ ISETP.NE.AND.EX P1, PT, R11, RZ, PT, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe40003f25310 */
/*0420*/ IADD3.X R23, R15, UR6, RZ, P2, !PT ; /* 0x000000060f177c10 */
/* 0x000fe200097fe4ff */
/*0430*/ DADD R12, R20, R12 ; /* 0x00000000140c7229 */
/* 0x004e0e000000000c */
/*0440*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0013e6000c101b0a */
/*0450*/ @P1 BRA 0x2b0 ; /* 0xfffffe5000001947 */
/* 0x000fea000383ffff */
/*0460*/ @!P0 BRA 0x5e0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD R8, R9, c[0x0][0x178], RZ ; /* 0x00005e0009087a24 */
/* 0x000fe200078e02ff */
/*0480*/ IADD3 R6, P1, RZ, -R6, RZ ; /* 0x80000006ff067210 */
/* 0x000fe20007f3e0ff */
/*0490*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*04a0*/ IMAD R9, R7.reuse, c[0x0][0x17c], R8 ; /* 0x00005f0007097a24 */
/* 0x040fe400078e0208 */
/*04b0*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x178], R4 ; /* 0x00005e0007047a25 */
/* 0x000fc800078e0004 */
/*04c0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0a7624 */
/* 0x000fe200078e00ff */
/*04d0*/ LEA R7, P0, R4, c[0x0][0x160], 0x3 ; /* 0x0000580004077a11 */
/* 0x000fe200078018ff */
/*04e0*/ IMAD.IADD R5, R5, 0x1, R9 ; /* 0x0000000105057824 */
/* 0x000fc600078e0209 */
/*04f0*/ SHF.L.U64.HI R9, R10, R0, c[0x0][0x17c] ; /* 0x00005f000a097619 */
/* 0x000fe20000010200 */
/*0500*/ IMAD.X R0, RZ, RZ, -0x1, P1 ; /* 0xffffffffff007424 */
/* 0x000fe200008e06ff */
/*0510*/ LEA.HI.X R8, R4, c[0x0][0x164], R5, 0x3, P0 ; /* 0x0000590004087a11 */
/* 0x000fc600000f1c05 */
/*0520*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0007 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0008 */
/*0540*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000a04047981 */
/* 0x000ea2000c1e1b00 */
/*0550*/ IADD3 R6, P0, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007f1e0ff */
/*0560*/ LEA R7, P1, R10, R7, 0x3 ; /* 0x000000070a077211 */
/* 0x000fc600078218ff */
/*0570*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*0580*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05070 */
/*0590*/ IMAD.X R8, R8, 0x1, R9, P1 ; /* 0x0000000108087824 */
/* 0x000fc600008e0609 */
/*05a0*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*05b0*/ DADD R12, R4, R12 ; /* 0x00000000040c7229 */
/* 0x007e0e000000000c */
/*05c0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011ea000c101b0a */
/*05d0*/ @P0 BRA 0x520 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*05e0*/ I2F.F64.U64 R8, c[0x0][0x170] ; /* 0x00005c0000087b12 */
/* 0x001e220000301800 */
/*05f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0600*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe20003f2e200 */
/*0610*/ BSSY B0, 0x750 ; /* 0x0000013000007945 */
/* 0x000fea0003800000 */
/*0620*/ MUFU.RCP64H R5, R9 ; /* 0x0000000900057308 */
/* 0x001e240000001800 */
/*0630*/ DFMA R6, -R8, R4, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c0000000104 */
/*0640*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0650*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*0660*/ DFMA R4, -R8, R6, 1 ; /* 0x3ff000000804742b */
/* 0x001e0c0000000106 */
/*0670*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e0c0000000006 */
/*0680*/ DMUL R6, R4, R12 ; /* 0x0000000c04067228 */
/* 0x001e0c0000000000 */
/*0690*/ DFMA R10, -R8, R6, R12 ; /* 0x00000006080a722b */
/* 0x001e0c000000010c */
/*06a0*/ DFMA R4, R4, R10, R6 ; /* 0x0000000a0404722b */
/* 0x001e140000000006 */
/*06b0*/ FFMA R0, RZ, R9, R5 ; /* 0x00000009ff007223 */
/* 0x001fca0000000005 */
/*06c0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*06d0*/ @P0 BRA P1, 0x740 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*06e0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*06f0*/ MOV R0, 0x720 ; /* 0x0000072000007802 */
/* 0x000fe20000000f00 */
/*0700*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000d */
/*0710*/ CALL.REL.NOINC 0x770 ; /* 0x0000005000007944 */
/* 0x002fea0003c00000 */
/*0720*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0730*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0740*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0750*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b0a */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0780*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0790*/ LOP3.LUT R4, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x000fe200078ec0ff */
/*07a0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*07b0*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*07c0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*07d0*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*07e0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*07f0*/ LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070c7812 */
/* 0x000fe200078ec0ff */
/*0800*/ BSSY B1, 0xd10 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*0810*/ LOP3.LUT R15, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090f7812 */
/* 0x000fc600078ec0ff */
/*0820*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e220000000000 */
/*0830*/ ISETP.GE.U32.AND P1, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fc60003f26070 */
/*0840*/ @!P2 LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ba812 */
/* 0x000fe200078ec0ff */
/*0850*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0860*/ MUFU.RCP64H R17, R5 ; /* 0x0000000500117308 */
/* 0x001e240000001800 */
/*0870*/ @!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ; /* 0x0000000b0c00a20c */
/* 0x000fe40003f66070 */
/*0880*/ SEL R11, R13.reuse, 0x63400000, !P1 ; /* 0x634000000d0b7807 */
/* 0x040fe40004800000 */
/*0890*/ @!P2 SEL R21, R13, 0x63400000, !P3 ; /* 0x634000000d15a807 */
/* 0x000fe40005800000 */
/*08a0*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef807 */
/*08b0*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef807 */
/*08c0*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*08d0*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x001e0a0000000804 */
/*08e0*/ @!P2 DFMA R10, R10, 2, -R20 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000814 */
/*08f0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0900*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x0010640000000010 */
/*0910*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x001fe200078e000c */
/*0920*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*0930*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*0940*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*0950*/ DFMA R20, R18, -R4, 1 ; /* 0x3ff000001214742b */
/* 0x002e060000000804 */
/*0960*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fc60007ffe0ff */
/*0970*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*0980*/ IADD3 R20, R16, -0x1, RZ ; /* 0xffffffff10147810 */
/* 0x001fc80007ffe0ff */
/*0990*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*09a0*/ DMUL R14, R18, R10 ; /* 0x0000000a120e7228 */
/* 0x002e060000000000 */
/*09b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*09c0*/ DFMA R20, R14, -R4, R10 ; /* 0x800000040e14722b */
/* 0x001e0c000000000a */
/*09d0*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x001048000000000e */
/*09e0*/ @P0 BRA 0xbb0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*09f0*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x003fc800078ec0ff */
/*0a00*/ ISETP.GE.U32.AND P0, PT, R12.reuse, R7, PT ; /* 0x000000070c00720c */
/* 0x040fe20003f06070 */
/*0a10*/ IMAD.IADD R6, R12, 0x1, -R7 ; /* 0x000000010c067824 */
/* 0x000fc600078e0a07 */
/*0a20*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe40004000000 */
/*0a30*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0a40*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0a50*/ IMAD.IADD R16, R6, 0x1, -R13 ; /* 0x0000000106107824 */
/* 0x000fe400078e0a0d */
/*0a60*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0a70*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*0a80*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*0a90*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0aa0*/ @P0 BRA 0xd00 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0ab0*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e22000000000a */
/*0ac0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0ad0*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0ae0*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*0af0*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0b00*/ @!P0 BRA 0xd00 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0b10*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*0b20*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0b30*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0b40*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*0b50*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*0b60*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*0b70*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0b80*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*0b90*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0ba0*/ BRA 0xd00 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0bc0*/ @P0 BRA 0xce0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0bd0*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0be0*/ @P0 BRA 0xcb0 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0bf0*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0c10*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0c20*/ @!P0 BRA 0xd00 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0c30*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*0c40*/ LOP3.LUT R13, R7, 0x80000000, R9, 0x48, !PT ; /* 0x80000000070d7812 */
/* 0x000fe400078e4809 */
/*0c50*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*0c60*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*0c70*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0c80*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0c90*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*0ca0*/ BRA 0xd00 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0cc0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0cd0*/ BRA 0xd00 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0ce0*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0cf0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0d00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d10*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0d20*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0d30*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2c004007950 */
/* 0x000fea0003c3ffff */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12getMeanImagePKdPdmm
.globl _Z12getMeanImagePKdPdmm
.p2align 8
.type _Z12getMeanImagePKdPdmm,@function
_Z12getMeanImagePKdPdmm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
s_cmp_eq_u64 s[6:7], 0
global_store_b64 v[0:1], v[2:3], off
s_cbranch_scc1 .LBB0_4
global_load_b64 v[2:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_lshl_b64 s[0:1], s[2:3], 3
s_mov_b64 s[2:3], s[6:7]
.LBB0_3:
global_load_b64 v[6:7], v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, s0
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[6:7], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_cbranch_scc0 .LBB0_3
.LBB0_4:
global_load_b64 v[2:3], v[0:1], off
v_cvt_f64_u32_e32 v[4:5], s7
v_cvt_f64_u32_e32 v[6:7], s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], 32
v_add_f64 v[4:5], v[4:5], v[6:7]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
v_mul_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12getMeanImagePKdPdmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12getMeanImagePKdPdmm, .Lfunc_end0-_Z12getMeanImagePKdPdmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12getMeanImagePKdPdmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12getMeanImagePKdPdmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010e20e_00000000-6_getMeanImage.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm
.type _Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm, @function
_Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12getMeanImagePKdPdmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm, .-_Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm
.globl _Z12getMeanImagePKdPdmm
.type _Z12getMeanImagePKdPdmm, @function
_Z12getMeanImagePKdPdmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12getMeanImagePKdPdmmPKdPdmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12getMeanImagePKdPdmm, .-_Z12getMeanImagePKdPdmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12getMeanImagePKdPdmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12getMeanImagePKdPdmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "getMeanImage.hip"
.globl _Z27__device_stub__getMeanImagePKdPdmm # -- Begin function _Z27__device_stub__getMeanImagePKdPdmm
.p2align 4, 0x90
.type _Z27__device_stub__getMeanImagePKdPdmm,@function
_Z27__device_stub__getMeanImagePKdPdmm: # @_Z27__device_stub__getMeanImagePKdPdmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12getMeanImagePKdPdmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__getMeanImagePKdPdmm, .Lfunc_end0-_Z27__device_stub__getMeanImagePKdPdmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12getMeanImagePKdPdmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12getMeanImagePKdPdmm,@object # @_Z12getMeanImagePKdPdmm
.section .rodata,"a",@progbits
.globl _Z12getMeanImagePKdPdmm
.p2align 3, 0x0
_Z12getMeanImagePKdPdmm:
.quad _Z27__device_stub__getMeanImagePKdPdmm
.size _Z12getMeanImagePKdPdmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12getMeanImagePKdPdmm"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__getMeanImagePKdPdmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12getMeanImagePKdPdmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* a simple test
*/
__shared__ float data1[32][32];
__shared__ float data2[32][32];
__shared__ float data3[32][32];
__device__ void mult(__shared__ float d1[32][32],
__shared__ float d2[32][32],
__shared__ float d3[32][32],
int idx)
{
int i;
for (i = 0; i < 31; i++) {
d1[idx][i] = d2[idx+1][i-1] + d2[idx][i-1] + d2[idx-1][i-1] +
d2[idx+1][i] + d2[idx][i] + d2[idx-1][i] +
d2[idx+1][i+1] + d2[idx][i+1] + d2[idx-1][i+1];
}
}
__global__ void doit(int start, int end) {
int i;
for (i = start; i < end; i++) {
mult(data1, data2, data3, i);
}
} | code for sm_80
Function : _Z4doitii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* a simple test
*/
__shared__ float data1[32][32];
__shared__ float data2[32][32];
__shared__ float data3[32][32];
__device__ void mult(__shared__ float d1[32][32],
__shared__ float d2[32][32],
__shared__ float d3[32][32],
int idx)
{
int i;
for (i = 0; i < 31; i++) {
d1[idx][i] = d2[idx+1][i-1] + d2[idx][i-1] + d2[idx-1][i-1] +
d2[idx+1][i] + d2[idx][i] + d2[idx-1][i] +
d2[idx+1][i+1] + d2[idx][i+1] + d2[idx-1][i+1];
}
}
__global__ void doit(int start, int end) {
int i;
for (i = start; i < end; i++) {
mult(data1, data2, data3, i);
}
} | .file "tmpxft_000688de_00000000-6_iv12.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4multPA32_fS0_S0_i
.type _Z4multPA32_fS0_S0_i, @function
_Z4multPA32_fS0_S0_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4multPA32_fS0_S0_i, .-_Z4multPA32_fS0_S0_i
.globl _Z23__device_stub__Z4doitiiii
.type _Z23__device_stub__Z4doitiiii, @function
_Z23__device_stub__Z4doitiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4doitii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z23__device_stub__Z4doitiiii, .-_Z23__device_stub__Z4doitiiii
.globl _Z4doitii
.type _Z4doitii, @function
_Z4doitii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4doitiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z4doitii, .-_Z4doitii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4doitii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4doitii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* a simple test
*/
__shared__ float data1[32][32];
__shared__ float data2[32][32];
__shared__ float data3[32][32];
__device__ void mult(__shared__ float d1[32][32],
__shared__ float d2[32][32],
__shared__ float d3[32][32],
int idx)
{
int i;
for (i = 0; i < 31; i++) {
d1[idx][i] = d2[idx+1][i-1] + d2[idx][i-1] + d2[idx-1][i-1] +
d2[idx+1][i] + d2[idx][i] + d2[idx-1][i] +
d2[idx+1][i+1] + d2[idx][i+1] + d2[idx-1][i+1];
}
}
__global__ void doit(int start, int end) {
int i;
for (i = start; i < end; i++) {
mult(data1, data2, data3, i);
}
} | #include <hip/hip_runtime.h>
/*
* a simple test
*/
__shared__ float data1[32][32];
__shared__ float data2[32][32];
__shared__ float data3[32][32];
__device__ void mult(__shared__ float d1[32][32],
__shared__ float d2[32][32],
__shared__ float d3[32][32],
int idx)
{
int i;
for (i = 0; i < 31; i++) {
d1[idx][i] = d2[idx+1][i-1] + d2[idx][i-1] + d2[idx-1][i-1] +
d2[idx+1][i] + d2[idx][i] + d2[idx-1][i] +
d2[idx+1][i+1] + d2[idx][i+1] + d2[idx-1][i+1];
}
}
__global__ void doit(int start, int end) {
int i;
for (i = start; i < end; i++) {
mult(data1, data2, data3, i);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* a simple test
*/
__shared__ float data1[32][32];
__shared__ float data2[32][32];
__shared__ float data3[32][32];
__device__ void mult(__shared__ float d1[32][32],
__shared__ float d2[32][32],
__shared__ float d3[32][32],
int idx)
{
int i;
for (i = 0; i < 31; i++) {
d1[idx][i] = d2[idx+1][i-1] + d2[idx][i-1] + d2[idx-1][i-1] +
d2[idx+1][i] + d2[idx][i] + d2[idx-1][i] +
d2[idx+1][i+1] + d2[idx][i+1] + d2[idx-1][i+1];
}
}
__global__ void doit(int start, int end) {
int i;
for (i = start; i < end; i++) {
mult(data1, data2, data3, i);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4doitii
.globl _Z4doitii
.p2align 8
.type _Z4doitii,@function
_Z4doitii:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s0, s1
s_cbranch_scc1 .LBB0_5
s_lshl_b32 s2, s0, 7
s_movk_i32 s5, 0xc00
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mov_b32 s3, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_i32 s4, s2, s3
s_add_i32 s3, s3, 4
v_mov_b32_e32 v8, s4
s_movk_i32 s4, 0x1000
s_cmpk_lg_i32 s3, 0x7c
v_add_nc_u32_e32 v0, s4, v8
s_movk_i32 s4, 0xc00
v_add_nc_u32_e32 v2, s5, v8
v_add_nc_u32_e32 v4, s4, v8
s_movk_i32 s4, 0x1000
ds_load_2addr_b32 v[0:1], v0 offset0:31 offset1:32
ds_load_2addr_b32 v[2:3], v2 offset0:225 offset1:255
ds_load_2addr_b32 v[4:5], v4 offset0:223 offset1:224
v_add_nc_u32_e32 v6, s4, v8
ds_load_2addr_b32 v[6:7], v6 offset1:1
s_waitcnt lgkmcnt(2)
v_add_f32_e32 v0, v0, v3
ds_load_b32 v3, v8 offset:4228
s_waitcnt lgkmcnt(2)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v1
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v7
v_add_f32_e32 v0, v0, v2
ds_store_b32 v8, v0
s_cbranch_scc1 .LBB0_3
s_add_i32 s0, s0, 1
s_addk_i32 s2, 0x80
s_cmp_lt_i32 s0, s1
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4doitii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4doitii, .Lfunc_end0-_Z4doitii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 4
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4doitii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z4doitii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* a simple test
*/
__shared__ float data1[32][32];
__shared__ float data2[32][32];
__shared__ float data3[32][32];
__device__ void mult(__shared__ float d1[32][32],
__shared__ float d2[32][32],
__shared__ float d3[32][32],
int idx)
{
int i;
for (i = 0; i < 31; i++) {
d1[idx][i] = d2[idx+1][i-1] + d2[idx][i-1] + d2[idx-1][i-1] +
d2[idx+1][i] + d2[idx][i] + d2[idx-1][i] +
d2[idx+1][i+1] + d2[idx][i+1] + d2[idx-1][i+1];
}
}
__global__ void doit(int start, int end) {
int i;
for (i = start; i < end; i++) {
mult(data1, data2, data3, i);
}
} | .text
.file "iv12.hip"
.globl _Z19__device_stub__doitii # -- Begin function _Z19__device_stub__doitii
.p2align 4, 0x90
.type _Z19__device_stub__doitii,@function
_Z19__device_stub__doitii: # @_Z19__device_stub__doitii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4doitii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__doitii, .Lfunc_end0-_Z19__device_stub__doitii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4doitii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4doitii,@object # @_Z4doitii
.section .rodata,"a",@progbits
.globl _Z4doitii
.p2align 3, 0x0
_Z4doitii:
.quad _Z19__device_stub__doitii
.size _Z4doitii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4doitii"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__doitii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4doitii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4doitii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4doitii
.globl _Z4doitii
.p2align 8
.type _Z4doitii,@function
_Z4doitii:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s0, s1
s_cbranch_scc1 .LBB0_5
s_lshl_b32 s2, s0, 7
s_movk_i32 s5, 0xc00
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mov_b32 s3, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_i32 s4, s2, s3
s_add_i32 s3, s3, 4
v_mov_b32_e32 v8, s4
s_movk_i32 s4, 0x1000
s_cmpk_lg_i32 s3, 0x7c
v_add_nc_u32_e32 v0, s4, v8
s_movk_i32 s4, 0xc00
v_add_nc_u32_e32 v2, s5, v8
v_add_nc_u32_e32 v4, s4, v8
s_movk_i32 s4, 0x1000
ds_load_2addr_b32 v[0:1], v0 offset0:31 offset1:32
ds_load_2addr_b32 v[2:3], v2 offset0:225 offset1:255
ds_load_2addr_b32 v[4:5], v4 offset0:223 offset1:224
v_add_nc_u32_e32 v6, s4, v8
ds_load_2addr_b32 v[6:7], v6 offset1:1
s_waitcnt lgkmcnt(2)
v_add_f32_e32 v0, v0, v3
ds_load_b32 v3, v8 offset:4228
s_waitcnt lgkmcnt(2)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v1
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v7
v_add_f32_e32 v0, v0, v2
ds_store_b32 v8, v0
s_cbranch_scc1 .LBB0_3
s_add_i32 s0, s0, 1
s_addk_i32 s2, 0x80
s_cmp_lt_i32 s0, s1
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4doitii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4doitii, .Lfunc_end0-_Z4doitii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 4
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4doitii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z4doitii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000688de_00000000-6_iv12.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4multPA32_fS0_S0_i
.type _Z4multPA32_fS0_S0_i, @function
_Z4multPA32_fS0_S0_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4multPA32_fS0_S0_i, .-_Z4multPA32_fS0_S0_i
.globl _Z23__device_stub__Z4doitiiii
.type _Z23__device_stub__Z4doitiiii, @function
_Z23__device_stub__Z4doitiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4doitii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z23__device_stub__Z4doitiiii, .-_Z23__device_stub__Z4doitiiii
.globl _Z4doitii
.type _Z4doitii, @function
_Z4doitii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4doitiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z4doitii, .-_Z4doitii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4doitii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4doitii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "iv12.hip"
.globl _Z19__device_stub__doitii # -- Begin function _Z19__device_stub__doitii
.p2align 4, 0x90
.type _Z19__device_stub__doitii,@function
_Z19__device_stub__doitii: # @_Z19__device_stub__doitii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4doitii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__doitii, .Lfunc_end0-_Z19__device_stub__doitii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4doitii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4doitii,@object # @_Z4doitii
.section .rodata,"a",@progbits
.globl _Z4doitii
.p2align 3, 0x0
_Z4doitii:
.quad _Z19__device_stub__doitii
.size _Z4doitii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4doitii"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__doitii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4doitii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void InvertValuesKernel(float *input, float* outputs, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(id < size)
{
outputs[id] = 1.00f - input[id];
}
} | code for sm_80
Function : _Z18InvertValuesKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0205 */
/*00d0*/ FADD R7, -R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000100 */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void InvertValuesKernel(float *input, float* outputs, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(id < size)
{
outputs[id] = 1.00f - input[id];
}
} | .file "tmpxft_001b6801_00000000-6_InvertValuesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i
.type _Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i, @function
_Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18InvertValuesKernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i, .-_Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i
.globl _Z18InvertValuesKernelPfS_i
.type _Z18InvertValuesKernelPfS_i, @function
_Z18InvertValuesKernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18InvertValuesKernelPfS_i, .-_Z18InvertValuesKernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18InvertValuesKernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18InvertValuesKernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void InvertValuesKernel(float *input, float* outputs, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(id < size)
{
outputs[id] = 1.00f - input[id];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InvertValuesKernel(float *input, float* outputs, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(id < size)
{
outputs[id] = 1.00f - input[id];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InvertValuesKernel(float *input, float* outputs, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(id < size)
{
outputs[id] = 1.00f - input[id];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18InvertValuesKernelPfS_i
.globl _Z18InvertValuesKernelPfS_i
.p2align 8
.type _Z18InvertValuesKernelPfS_i,@function
_Z18InvertValuesKernelPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18InvertValuesKernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18InvertValuesKernelPfS_i, .Lfunc_end0-_Z18InvertValuesKernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18InvertValuesKernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18InvertValuesKernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InvertValuesKernel(float *input, float* outputs, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(id < size)
{
outputs[id] = 1.00f - input[id];
}
} | .text
.file "InvertValuesKernel.hip"
.globl _Z33__device_stub__InvertValuesKernelPfS_i # -- Begin function _Z33__device_stub__InvertValuesKernelPfS_i
.p2align 4, 0x90
.type _Z33__device_stub__InvertValuesKernelPfS_i,@function
_Z33__device_stub__InvertValuesKernelPfS_i: # @_Z33__device_stub__InvertValuesKernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18InvertValuesKernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__InvertValuesKernelPfS_i, .Lfunc_end0-_Z33__device_stub__InvertValuesKernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18InvertValuesKernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18InvertValuesKernelPfS_i,@object # @_Z18InvertValuesKernelPfS_i
.section .rodata,"a",@progbits
.globl _Z18InvertValuesKernelPfS_i
.p2align 3, 0x0
_Z18InvertValuesKernelPfS_i:
.quad _Z33__device_stub__InvertValuesKernelPfS_i
.size _Z18InvertValuesKernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18InvertValuesKernelPfS_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__InvertValuesKernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18InvertValuesKernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18InvertValuesKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0205 */
/*00d0*/ FADD R7, -R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000100 */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18InvertValuesKernelPfS_i
.globl _Z18InvertValuesKernelPfS_i
.p2align 8
.type _Z18InvertValuesKernelPfS_i,@function
_Z18InvertValuesKernelPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18InvertValuesKernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18InvertValuesKernelPfS_i, .Lfunc_end0-_Z18InvertValuesKernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18InvertValuesKernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18InvertValuesKernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b6801_00000000-6_InvertValuesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i
.type _Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i, @function
_Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18InvertValuesKernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i, .-_Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i
.globl _Z18InvertValuesKernelPfS_i
.type _Z18InvertValuesKernelPfS_i, @function
_Z18InvertValuesKernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18InvertValuesKernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18InvertValuesKernelPfS_i, .-_Z18InvertValuesKernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18InvertValuesKernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18InvertValuesKernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "InvertValuesKernel.hip"
.globl _Z33__device_stub__InvertValuesKernelPfS_i # -- Begin function _Z33__device_stub__InvertValuesKernelPfS_i
.p2align 4, 0x90
.type _Z33__device_stub__InvertValuesKernelPfS_i,@function
_Z33__device_stub__InvertValuesKernelPfS_i: # @_Z33__device_stub__InvertValuesKernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18InvertValuesKernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__InvertValuesKernelPfS_i, .Lfunc_end0-_Z33__device_stub__InvertValuesKernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18InvertValuesKernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18InvertValuesKernelPfS_i,@object # @_Z18InvertValuesKernelPfS_i
.section .rodata,"a",@progbits
.globl _Z18InvertValuesKernelPfS_i
.p2align 3, 0x0
_Z18InvertValuesKernelPfS_i:
.quad _Z33__device_stub__InvertValuesKernelPfS_i
.size _Z18InvertValuesKernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18InvertValuesKernelPfS_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__InvertValuesKernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18InvertValuesKernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void find_unique_id(int* arr) {
int bid = (blockIdx.z * gridDim.y * gridDim.x) + (blockIdx.y * gridDim.x) + blockIdx.x;
int tid = (bid * blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * blockDim.y * blockDim.x) + (threadIdx.y * blockDim.x) + threadIdx.x;
arr[tid] = tid;
}
int main() {
dim3 grid(1,2,3);
dim3 block(4,5,6);
int threads = 1*2*3*4*5*6;
int *arr, *darr;
arr = (int*)malloc(threads*sizeof(int));
cudaMalloc(&darr, threads*sizeof(int));
find_unique_id<<<grid, block>>>(darr);
cudaDeviceSynchronize();
cudaMemcpy(arr, darr, threads*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0; i<threads; i++)
printf("%d\n", arr[i]);
printf("\n");
return 0;
} | code for sm_80
Function : _Z14find_unique_idPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea80000002300 */
/*0070*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0080*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000f220000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*00b0*/ IMAD R0, R0, c[0x0][0x8], R7 ; /* 0x0000020000007a24 */
/* 0x004fc800078e0207 */
/*00c0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00d0*/ IMAD R5, R0, c[0x0][0x0], R11 ; /* 0x0000000000057a24 */
/* 0x010fc800078e020b */
/*00e0*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void find_unique_id(int* arr) {
int bid = (blockIdx.z * gridDim.y * gridDim.x) + (blockIdx.y * gridDim.x) + blockIdx.x;
int tid = (bid * blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * blockDim.y * blockDim.x) + (threadIdx.y * blockDim.x) + threadIdx.x;
arr[tid] = tid;
}
int main() {
dim3 grid(1,2,3);
dim3 block(4,5,6);
int threads = 1*2*3*4*5*6;
int *arr, *darr;
arr = (int*)malloc(threads*sizeof(int));
cudaMalloc(&darr, threads*sizeof(int));
find_unique_id<<<grid, block>>>(darr);
cudaDeviceSynchronize();
cudaMemcpy(arr, darr, threads*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0; i<threads; i++)
printf("%d\n", arr[i]);
printf("\n");
return 0;
} | .file "tmpxft_001062d8_00000000-6_unique_id.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14find_unique_idPiPi
.type _Z34__device_stub__Z14find_unique_idPiPi, @function
_Z34__device_stub__Z14find_unique_idPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14find_unique_idPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z14find_unique_idPiPi, .-_Z34__device_stub__Z14find_unique_idPiPi
.globl _Z14find_unique_idPi
.type _Z14find_unique_idPi, @function
_Z14find_unique_idPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14find_unique_idPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14find_unique_idPi, .-_Z14find_unique_idPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $4, 28(%rsp)
movl $5, 32(%rsp)
movl $6, 36(%rsp)
movl $2880, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $2880, %esi
call cudaMalloc@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $2880, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $2880, %rbp
leaq .LC0(%rip), %r12
.L13:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z34__device_stub__Z14find_unique_idPiPi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14find_unique_idPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14find_unique_idPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
__global__ void find_unique_id(int* arr) {
int bid = (blockIdx.z * gridDim.y * gridDim.x) + (blockIdx.y * gridDim.x) + blockIdx.x;
int tid = (bid * blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * blockDim.y * blockDim.x) + (threadIdx.y * blockDim.x) + threadIdx.x;
arr[tid] = tid;
}
int main() {
dim3 grid(1,2,3);
dim3 block(4,5,6);
int threads = 1*2*3*4*5*6;
int *arr, *darr;
arr = (int*)malloc(threads*sizeof(int));
cudaMalloc(&darr, threads*sizeof(int));
find_unique_id<<<grid, block>>>(darr);
cudaDeviceSynchronize();
cudaMemcpy(arr, darr, threads*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0; i<threads; i++)
printf("%d\n", arr[i]);
printf("\n");
return 0;
} | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void find_unique_id(int* arr) {
int bid = (blockIdx.z * gridDim.y * gridDim.x) + (blockIdx.y * gridDim.x) + blockIdx.x;
int tid = (bid * blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * blockDim.y * blockDim.x) + (threadIdx.y * blockDim.x) + threadIdx.x;
arr[tid] = tid;
}
int main() {
dim3 grid(1,2,3);
dim3 block(4,5,6);
int threads = 1*2*3*4*5*6;
int *arr, *darr;
arr = (int*)malloc(threads*sizeof(int));
hipMalloc(&darr, threads*sizeof(int));
find_unique_id<<<grid, block>>>(darr);
hipDeviceSynchronize();
hipMemcpy(arr, darr, threads*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0; i<threads; i++)
printf("%d\n", arr[i]);
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void find_unique_id(int* arr) {
int bid = (blockIdx.z * gridDim.y * gridDim.x) + (blockIdx.y * gridDim.x) + blockIdx.x;
int tid = (bid * blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * blockDim.y * blockDim.x) + (threadIdx.y * blockDim.x) + threadIdx.x;
arr[tid] = tid;
}
int main() {
dim3 grid(1,2,3);
dim3 block(4,5,6);
int threads = 1*2*3*4*5*6;
int *arr, *darr;
arr = (int*)malloc(threads*sizeof(int));
hipMalloc(&darr, threads*sizeof(int));
find_unique_id<<<grid, block>>>(darr);
hipDeviceSynchronize();
hipMemcpy(arr, darr, threads*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0; i<threads; i++)
printf("%d\n", arr[i]);
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14find_unique_idPi
.globl _Z14find_unique_idPi
.p2align 8
.type _Z14find_unique_idPi,@function
_Z14find_unique_idPi:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x14
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s7, s15
s_and_b32 s1, s1, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s6
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s2, s1, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s1, s0, 16
v_and_b32_e32 v0, 0x3ff, v0
s_and_b32 s0, s0, 0xffff
v_mad_u64_u32 v[3:4], null, v2, s1, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s0, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14find_unique_idPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14find_unique_idPi, .Lfunc_end0-_Z14find_unique_idPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14find_unique_idPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14find_unique_idPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void find_unique_id(int* arr) {
int bid = (blockIdx.z * gridDim.y * gridDim.x) + (blockIdx.y * gridDim.x) + blockIdx.x;
int tid = (bid * blockDim.x * blockDim.y * blockDim.z) + (threadIdx.z * blockDim.y * blockDim.x) + (threadIdx.y * blockDim.x) + threadIdx.x;
arr[tid] = tid;
}
int main() {
dim3 grid(1,2,3);
dim3 block(4,5,6);
int threads = 1*2*3*4*5*6;
int *arr, *darr;
arr = (int*)malloc(threads*sizeof(int));
hipMalloc(&darr, threads*sizeof(int));
find_unique_id<<<grid, block>>>(darr);
hipDeviceSynchronize();
hipMemcpy(arr, darr, threads*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0; i<threads; i++)
printf("%d\n", arr[i]);
printf("\n");
return 0;
} | .text
.file "unique_id.hip"
.globl _Z29__device_stub__find_unique_idPi # -- Begin function _Z29__device_stub__find_unique_idPi
.p2align 4, 0x90
.type _Z29__device_stub__find_unique_idPi,@function
_Z29__device_stub__find_unique_idPi: # @_Z29__device_stub__find_unique_idPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14find_unique_idPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__find_unique_idPi, .Lfunc_end0-_Z29__device_stub__find_unique_idPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $2880, %edi # imm = 0xB40
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $2880, %esi # imm = 0xB40
callq hipMalloc
movabsq $8589934593, %rdi # imm = 0x200000001
movabsq $21474836484, %rdx # imm = 0x500000004
movl $3, %esi
movl $6, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14find_unique_idPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $2880, %edx # imm = 0xB40
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $720, %r14 # imm = 0x2D0
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14find_unique_idPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14find_unique_idPi,@object # @_Z14find_unique_idPi
.section .rodata,"a",@progbits
.globl _Z14find_unique_idPi
.p2align 3, 0x0
_Z14find_unique_idPi:
.quad _Z29__device_stub__find_unique_idPi
.size _Z14find_unique_idPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14find_unique_idPi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__find_unique_idPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14find_unique_idPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14find_unique_idPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0060*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea80000002300 */
/*0070*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0080*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000f220000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*00b0*/ IMAD R0, R0, c[0x0][0x8], R7 ; /* 0x0000020000007a24 */
/* 0x004fc800078e0207 */
/*00c0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00d0*/ IMAD R5, R0, c[0x0][0x0], R11 ; /* 0x0000000000057a24 */
/* 0x010fc800078e020b */
/*00e0*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14find_unique_idPi
.globl _Z14find_unique_idPi
.p2align 8
.type _Z14find_unique_idPi,@function
_Z14find_unique_idPi:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x14
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s7, s15
s_and_b32 s1, s1, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s6
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s2, s1, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s1, s0, 16
v_and_b32_e32 v0, 0x3ff, v0
s_and_b32 s0, s0, 0xffff
v_mad_u64_u32 v[3:4], null, v2, s1, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s0, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14find_unique_idPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14find_unique_idPi, .Lfunc_end0-_Z14find_unique_idPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14find_unique_idPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14find_unique_idPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001062d8_00000000-6_unique_id.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14find_unique_idPiPi
.type _Z34__device_stub__Z14find_unique_idPiPi, @function
_Z34__device_stub__Z14find_unique_idPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14find_unique_idPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z14find_unique_idPiPi, .-_Z34__device_stub__Z14find_unique_idPiPi
.globl _Z14find_unique_idPi
.type _Z14find_unique_idPi, @function
_Z14find_unique_idPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14find_unique_idPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14find_unique_idPi, .-_Z14find_unique_idPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $3, 24(%rsp)
movl $4, 28(%rsp)
movl $5, 32(%rsp)
movl $6, 36(%rsp)
movl $2880, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $2880, %esi
call cudaMalloc@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $2880, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $2880, %rbp
leaq .LC0(%rip), %r12
.L13:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z34__device_stub__Z14find_unique_idPiPi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14find_unique_idPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14find_unique_idPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unique_id.hip"
.globl _Z29__device_stub__find_unique_idPi # -- Begin function _Z29__device_stub__find_unique_idPi
.p2align 4, 0x90
.type _Z29__device_stub__find_unique_idPi,@function
_Z29__device_stub__find_unique_idPi: # @_Z29__device_stub__find_unique_idPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14find_unique_idPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__find_unique_idPi, .Lfunc_end0-_Z29__device_stub__find_unique_idPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $2880, %edi # imm = 0xB40
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $2880, %esi # imm = 0xB40
callq hipMalloc
movabsq $8589934593, %rdi # imm = 0x200000001
movabsq $21474836484, %rdx # imm = 0x500000004
movl $3, %esi
movl $6, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14find_unique_idPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $2880, %edx # imm = 0xB40
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $720, %r14 # imm = 0x2D0
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14find_unique_idPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14find_unique_idPi,@object # @_Z14find_unique_idPi
.section .rodata,"a",@progbits
.globl _Z14find_unique_idPi
.p2align 3, 0x0
_Z14find_unique_idPi:
.quad _Z29__device_stub__find_unique_idPi
.size _Z14find_unique_idPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14find_unique_idPi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__find_unique_idPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14find_unique_idPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#define Tile_size 2
int numARows, numAColumns;
int numBRows, numBColumns;
int numCRows, numCColumns;
__global__ void matrixMultiplyShared(float *A, float *B, float *C,
int numARows, int numAColumns,
int numBRows, int numBColumns,
int numCRows, int numCColumns) {
__shared__ float sA[Tile_size][Tile_size]; // Tile size to store elements in shared memory
__shared__ float sB[Tile_size][Tile_size];
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
float cvalue = 0.0;
sA[threadIdx.y][threadIdx.x] = 0.0;
sB[threadIdx.y][threadIdx.x] = 0.0;
for (int k = 0; k < (((numAColumns - 1) / Tile_size) + 1); k++) {
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if ((row < numARows) && (threadIdx.x + (k * Tile_size)) < numAColumns) {
sA[threadIdx.y][threadIdx.x] = A[(row * numAColumns) + threadIdx.x + (k * Tile_size)];
} else {
sA[threadIdx.y][threadIdx.x] = 0.0;
}
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if (col < numBColumns && (threadIdx.y + k * Tile_size) < numBRows) {
sB[threadIdx.y][threadIdx.x] = B[(threadIdx.y + k * Tile_size) * numBColumns + col];
} else {
sB[threadIdx.y][threadIdx.x] = 0.0;
}
__syncthreads();
for (int j = 0; j < Tile_size; ++j)//Multiplying Elements present in tile
{
cvalue += sA[threadIdx.y][j] * sB[j][threadIdx.x];
}
}
if (row < numCRows && col < numCColumns)//Saving Final result into Matrix C
{
C[row * numCColumns + col] = cvalue;
}
}
void printMat(int row, int col, float *Mat) {
for (int i = 0; i < row * col; i++) {
printf("%f ", *(Mat + i));
if ((i % col) == 0 && i != 0) {
printf("\n");
}
}
}
void matMultiplyOnHost(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
for (int i = 0; i < numARows; i++) {
for (int j = 0; j < numAColumns; j++) {
C[i * numCColumns + j] = 0.0;
for (int k = 0; k < numCColumns; k++) {
C[i * numCColumns + j] += A[i * numAColumns + k] * B[k * numBColumns + j];
}
}
}
}
int main(int argc, char **argv) {
float *hostA, *hostB, *hostC;
float *hostComputedC;
float *deviceA, *deviceB, *deviceC;
printf("\nEnter Rows and Columns of A:");
scanf("%d %d", &numARows, &numAColumns);
printf("\nEnter Rows and Columns of B:");
scanf("%d %d", &numBRows, &numBColumns);
hostA = (float *) malloc(sizeof(float) * numARows * numAColumns);
hostB = (float *) malloc(sizeof(float) * numBRows * numBColumns);
int lower = 10.0, upper = 20.0;
for (int i = 0; i < numARows * numAColumns; i++)
hostA[i] = (rand() % (upper - lower + 1)) + lower;
for (int i = 0; i < numBRows * numBColumns; i++)
hostB[i] = (rand() % (upper - lower + 1)) + lower;
printf("\nMatrix A Values:\n");
printMat(numARows, numAColumns, hostA);
printf("\n\nMatrix B Values:\n");
printMat(numBRows, numBColumns, hostB);
numCRows = numARows;
numCColumns = numBColumns;
hostC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
hostComputedC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
// Allocating GPU memory
cudaMalloc((void **) &deviceA, sizeof(float) * numARows * numAColumns);
cudaMalloc((void **) &deviceB, sizeof(float) * numBRows * numBColumns);
cudaMalloc((void **) &deviceC, sizeof(float) * numCRows * numCColumns);
// Copy memory to the GPU
cudaMemcpy(deviceA, hostA, sizeof(float) * numARows * numAColumns, cudaMemcpyHostToDevice);
cudaMemcpy(deviceB, hostB, sizeof(float) * numBRows * numBColumns, cudaMemcpyHostToDevice);
// Initialize the grid and block dimensions
dim3 dimGrid((numCColumns / Tile_size) + 1, (numCRows / Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
matrixMultiplyShared<<<dimGrid, dimBlock>>>(deviceA, deviceB, deviceC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
cudaError_t err1 = cudaPeekAtLastError();//To capture last error in function call
cudaDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
cudaMemcpy(hostC, deviceC, sizeof(float) * numCRows * numCColumns, cudaMemcpyDeviceToHost);
printf("\nMatrix C From Device\n");
printMat(numCRows, numCColumns, hostC);//Function Call
matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
printf("\nMatrix C From Host\n");
printMat(numCRows, numCColumns, hostComputedC);
printf("\n\n");
for (int i = 0; i < numCColumns *
numCRows; i++)//Compare both the result matrices 1. MatrixMultiplyonHost 2. MatrixMultiplyonDevice
{
if (hostComputedC[i] != hostC[i]) {
printf("Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n", i / numCColumns,
i % numCColumns, hostComputedC[i], hostC[i]);
break;
}
}
printf("\nNumber of Blocks Created:%d \n", ((numCColumns / Tile_size) + 1) * ((numCColumns / Tile_size) + 1));
printf("\nNumber of Threads Per Block: %d \n", (Tile_size * Tile_size));
// Free the GPU memory
cudaFree(deviceA);
cudaFree(deviceB);
cudaFree(deviceC);
//Free the Pointer Memory
free(hostA);
free(hostB);
free(hostC);
free(hostComputedC);
return 0;
} | code for sm_80
Function : _Z20matrixMultiplySharedPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ISETP.LE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f03270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e680000002100 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000ee20000002500 */
/*0080*/ IMAD.SHL.U32 R3, R0, 0x8, RZ ; /* 0x0000000800037824 */
/* 0x001fca00078e00ff */
/*0090*/ LEA R3, R2, R3, 0x2 ; /* 0x0000000302037211 */
/* 0x002fe200078e10ff */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x004fc800078e0200 */
/*00b0*/ STS [R3], RZ ; /* 0x000000ff03007388 */
/* 0x0001e20000000800 */
/*00c0*/ IMAD R6, R7, c[0x0][0x0], R2 ; /* 0x0000000007067a24 */
/* 0x008fc600078e0202 */
/*00d0*/ STS [R3+0x10], RZ ; /* 0x000010ff03007388 */
/* 0x0001e20000000800 */
/*00e0*/ @!P0 BRA 0xab0 ; /* 0x000009c000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff087624 */
/* 0x000fe200078e00ff */
/*0100*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0110*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fc600078e00ff */
/*0120*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0130*/ LEA.HI R4, R4, R4, RZ, 0x1 ; /* 0x0000000404047211 */
/* 0x000fc800078f08ff */
/*0140*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011404 */
/*0150*/ IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff047217 */
/* 0x000fc80007800200 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R4.reuse, 0x3, PT ; /* 0x000000030400780c */
/* 0x040fe40003f06070 */
/*0170*/ IADD3 R7, R4, 0x1, RZ ; /* 0x0000000104077810 */
/* 0x000fc80007ffe0ff */
/*0180*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fc800078ec0ff */
/*0190*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f25270 */
/*01a0*/ @!P0 BRA 0x880 ; /* 0x000006d000008947 */
/* 0x000ff40003800000 */
/*01b0*/ IMAD R21, R5.reuse, c[0x0][0x17c], R2 ; /* 0x00005f0005157a24 */
/* 0x040fe200078e0202 */
/*01c0*/ IADD3 R11, R0.reuse, 0x6, RZ ; /* 0x00000006000b7810 */
/* 0x040fe20007ffe0ff */
/*01d0*/ IMAD R8, R5.reuse, R8, 0x2 ; /* 0x0000000205087424 */
/* 0x040fe200078e0208 */
/*01e0*/ IADD3 R23, R0.reuse, 0x4, RZ ; /* 0x0000000400177810 */
/* 0x040fe20007ffe0ff */
/*01f0*/ IMAD R22, R0.reuse, c[0x0][0x184], R6 ; /* 0x0000610000167a24 */
/* 0x040fe200078e0206 */
/*0200*/ IADD3 R13, R0, 0x2, RZ ; /* 0x00000002000d7810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R10, -R4, -0x1, R7 ; /* 0xffffffff040a7810 */
/* 0x000fe20007ffe107 */
/*0230*/ IMAD.MOV.U32 R20, RZ, RZ, R2 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0002 */
/*0240*/ ISETP.GE.AND P2, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f46270 */
/*0250*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe200078e00ff */
/*0260*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD R11, R11, c[0x0][0x184], R6.reuse ; /* 0x000061000b0b7a24 */
/* 0x100fe200078e0206 */
/*0280*/ IADD3 R21, R21, 0x6, RZ ; /* 0x0000000615157810 */
/* 0x000fe20007ffe0ff */
/*0290*/ IMAD R23, R23, c[0x0][0x184], R6 ; /* 0x0000610017177a24 */
/* 0x000fc400078e0206 */
/*02a0*/ IMAD R24, R13, c[0x0][0x184], R6 ; /* 0x000061000d187a24 */
/* 0x000fe400078e0206 */
/*02b0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x184], PT ; /* 0x0000610006007a0c */
/* 0x000fe20003f06270 */
/*02c0*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*02d0*/ ISETP.GE.U32.OR P3, PT, R20, c[0x0][0x17c], P2 ; /* 0x00005f0014007a0c */
/* 0x000fe20001766470 */
/*02e0*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*02f0*/ ISETP.GE.U32.OR P4, PT, R4, c[0x0][0x180], P0 ; /* 0x0000600004007a0c */
/* 0x000fd60000786470 */
/*0300*/ @!P3 MOV R15, 0x4 ; /* 0x00000004000fb802 */
/* 0x000fe20000000f00 */
/*0310*/ @!P3 IMAD R14, R5, c[0x0][0x17c], R20 ; /* 0x00005f00050eba24 */
/* 0x000fe400078e0214 */
/*0320*/ @!P4 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0dc424 */
/* 0x000fe400078e00ff */
/*0330*/ @!P3 IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0eb625 */
/* 0x000fc800078e000f */
/*0340*/ @!P4 IMAD.WIDE.U32 R12, R22, R13, c[0x0][0x168] ; /* 0x00005a00160cc625 */
/* 0x000fe200078e000d */
/*0350*/ @!P3 LDG.E R28, [R14.64] ; /* 0x000000040e1cb981 */
/* 0x000ea8000c1e1900 */
/*0360*/ @!P4 LDG.E R16, [R12.64] ; /* 0x000000040c10c981 */
/* 0x0002e2000c1e1900 */
/*0370*/ IADD3 R17, R20, 0x2, RZ ; /* 0x0000000214117810 */
/* 0x000fe20007ffe0ff */
/*0380*/ CS2R R26, SRZ ; /* 0x00000000001a7805 */
/* 0x000fc6000001ff00 */
/*0390*/ ISETP.GE.U32.OR P3, PT, R17, c[0x0][0x17c], P2 ; /* 0x00005f0011007a0c */
/* 0x000fe40001766470 */
/*03a0*/ IADD3 R17, R4, 0x2, RZ ; /* 0x0000000204117810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ ISETP.GE.U32.OR P4, PT, R17, c[0x0][0x180], P0 ; /* 0x0000600011007a0c */
/* 0x000fce0000786470 */
/*03c0*/ @!P3 IMAD.IADD R18, R8, 0x1, R20 ; /* 0x000000010812b824 */
/* 0x000fe400078e0214 */
/*03d0*/ @!P3 IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff13b424 */
/* 0x000fc800078e00ff */
/*03e0*/ @!P4 MOV R17, 0x4 ; /* 0x000000040011c802 */
/* 0x000fe20000000f00 */
/*03f0*/ @!P3 IMAD.WIDE.U32 R18, R18, R19, c[0x0][0x160] ; /* 0x000058001212b625 */
/* 0x000fc800078e0013 */
/*0400*/ @!P4 IMAD.WIDE.U32 R12, R24, R17, c[0x0][0x168] ; /* 0x00005a00180cc625 */
/* 0x002fe200078e0011 */
/*0410*/ STS [R3], R28 ; /* 0x0000001c03007388 */
/* 0x004fe80000000800 */
/*0420*/ STS [R3+0x10], R16 ; /* 0x0000101003007388 */
/* 0x0083e80000000800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ @!P3 LDG.E R26, [R18.64] ; /* 0x00000004121ab981 */
/* 0x000ea8000c1e1900 */
/*0450*/ @!P4 LDG.E R27, [R12.64] ; /* 0x000000040c1bc981 */
/* 0x000722000c1e1900 */
/*0460*/ IADD3 R14, R20, 0x4, RZ ; /* 0x00000004140e7810 */
/* 0x000fc60007ffe0ff */
/*0470*/ LDS R28, [R2.X4+0x18] ; /* 0x00001800021c7984 */
/* 0x000fe20000004800 */
/*0480*/ ISETP.GE.U32.OR P3, PT, R14, c[0x0][0x17c], P2 ; /* 0x00005f000e007a0c */
/* 0x000fc60001766470 */
/*0490*/ LDS.64 R14, [R0.X8] ; /* 0x00000000000e7984 */
/* 0x000fe80000008a00 */
/*04a0*/ LDS R12, [R2.X4+0x10] ; /* 0x00001000020c7984 */
/* 0x008eec0000004800 */
/*04b0*/ @!P3 IADD3 R17, R21, -0x2, RZ ; /* 0xfffffffe1511b810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ @!P3 IMAD.MOV.U32 R29, RZ, RZ, 0x4 ; /* 0x00000004ff1db424 */
/* 0x000fc800078e00ff */
/*04d0*/ @!P3 IMAD.WIDE.U32 R16, R17, R29, c[0x0][0x160] ; /* 0x000058001110b625 */
/* 0x002fe200078e001d */
/*04e0*/ HFMA2.MMA R29, -RZ, RZ, 0, 0 ; /* 0x00000000ff1d7435 */
/* 0x000fe200000001ff */
/*04f0*/ IADD3 R13, R4, 0x4, RZ ; /* 0x00000004040d7810 */
/* 0x000fe20007ffe0ff */
/*0500*/ STS [R3], R26 ; /* 0x0000001a03007388 */
/* 0x004fe80000000800 */
/*0510*/ STS [R3+0x10], R27 ; /* 0x0000101b03007388 */
/* 0x0107e80000000800 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ @!P3 LDG.E R29, [R16.64] ; /* 0x00000004101db981 */
/* 0x0002a2000c1e1900 */
/*0540*/ ISETP.GE.U32.OR P3, PT, R13, c[0x0][0x180], P0 ; /* 0x000060000d007a0c */
/* 0x000fe20000766470 */
/*0550*/ FFMA R27, R12, R14, R25 ; /* 0x0000000e0c1b7223 */
/* 0x008fc40000000019 */
/*0560*/ LDS R14, [R2.X4+0x10] ; /* 0x00001000020e7984 */
/* 0x000fe80000004800 */
/*0570*/ LDS R26, [R2.X4+0x18] ; /* 0x00001800021a7984 */
/* 0x000fe20000004800 */
/*0580*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x002fc60000000f00 */
/*0590*/ LDS.64 R12, [R0.X8] ; /* 0x00000000000c7984 */
/* 0x000e640000008a00 */
/*05a0*/ @!P3 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff12b424 */
/* 0x000fc800078e00ff */
/*05b0*/ @!P3 IMAD.WIDE.U32 R18, R23, R18, c[0x0][0x168] ; /* 0x00005a001712b625 */
/* 0x000fca00078e0012 */
/*05c0*/ @!P3 LDG.E R16, [R18.64] ; /* 0x000000041210b981 */
/* 0x000722000c1e1900 */
/*05d0*/ IADD3 R17, R20, 0x6, RZ ; /* 0x0000000614117810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ ISETP.GE.U32.OR P3, PT, R17, c[0x0][0x17c], P2 ; /* 0x00005f0011007a0c */
/* 0x000fe20001766470 */
/*05f0*/ HFMA2.MMA R25, -RZ, RZ, 0, 0 ; /* 0x00000000ff197435 */
/* 0x000fd800000001ff */
/*0600*/ @!P3 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff11b424 */
/* 0x000fe200078e00ff */
/*0610*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x008fe20000000f00 */
/*0620*/ STS [R3], R29 ; /* 0x0000001d03007388 */
/* 0x0045e40000000800 */
/*0630*/ IADD3 R29, R4, 0x6, RZ ; /* 0x00000006041d7810 */
/* 0x004fc80007ffe0ff */
/*0640*/ ISETP.GE.U32.OR P0, PT, R29, c[0x0][0x180], P0 ; /* 0x000060001d007a0c */
/* 0x000fe20000706470 */
/*0650*/ STS [R3+0x10], R16 ; /* 0x0000101003007388 */
/* 0x0105d80000000800 */
/*0660*/ @!P0 IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff138424 */
/* 0x000fe400078e00ff */
/*0670*/ @!P3 IMAD.WIDE.U32 R16, R21, R17, c[0x0][0x160] ; /* 0x000058001510b625 */
/* 0x004fe200078e0011 */
/*0680*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0690*/ @!P3 LDG.E R25, [R16.64] ; /* 0x000000041019b981 */
/* 0x0004e4000c1e1900 */
/*06a0*/ @!P0 IMAD.WIDE.U32 R16, R11, R19, c[0x0][0x168] ; /* 0x00005a000b108625 */
/* 0x004fca00078e0013 */
/*06b0*/ @!P0 LDG.E R18, [R16.64] ; /* 0x0000000410128981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ FFMA R15, R28, R15, R27 ; /* 0x0000000f1c0f7223 */
/* 0x000fc6000000001b */
/*06d0*/ LDS R27, [R2.X4+0x10] ; /* 0x00001000021b7984 */
/* 0x000fe20000004800 */
/*06e0*/ FFMA R28, R14, R12, R15 ; /* 0x0000000c0e1c7223 */
/* 0x002fc6000000000f */
/*06f0*/ LDS R12, [R2.X4+0x18] ; /* 0x00001800020c7984 */
/* 0x000fe80000004800 */
/*0700*/ LDS.64 R14, [R0.X8] ; /* 0x00000000000e7984 */
/* 0x000e620000008a00 */
/*0710*/ FFMA R13, R26, R13, R28 ; /* 0x0000000d1a0d7223 */
/* 0x000fe2000000001c */
/*0720*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0730*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fc40007ffe0ff */
/*0750*/ IADD3 R21, R21, 0x8, RZ ; /* 0x0000000815157810 */
/* 0x000fe20007ffe0ff */
/*0760*/ FFMA R14, R27, R14, R13 ; /* 0x0000000e1b0e7223 */
/* 0x002fc8000000000d */
/*0770*/ FFMA R14, R12, R15, R14 ; /* 0x0000000f0c0e7223 */
/* 0x000fe4000000000e */
/*0780*/ IMAD.IADD R12, R10, 0x1, R9 ; /* 0x000000010a0c7824 */
/* 0x000fca00078e0209 */
/*0790*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*07a0*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fd400000001ff */
/*07b0*/ IMAD R11, R13.reuse, c[0x0][0x184], R11 ; /* 0x000061000d0b7a24 */
/* 0x040fe400078e020b */
/*07c0*/ IMAD R23, R13.reuse, c[0x0][0x184], R23 ; /* 0x000061000d177a24 */
/* 0x040fe400078e0217 */
/*07d0*/ IMAD R24, R13.reuse, c[0x0][0x184], R24 ; /* 0x000061000d187a24 */
/* 0x040fe400078e0218 */
/*07e0*/ IMAD R22, R13, c[0x0][0x184], R22 ; /* 0x000061000d167a24 */
/* 0x000fe200078e0216 */
/*07f0*/ STS [R3], R25 ; /* 0x0000001903007388 */
/* 0x008fe80000000800 */
/*0800*/ STS [R3+0x10], R18 ; /* 0x0000101203007388 */
/* 0x004fe80000000800 */
/*0810*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0820*/ LDS R29, [R2.X4+0x10] ; /* 0x00001000021d7984 */
/* 0x000fe80000004800 */
/*0830*/ LDS.64 R18, [R0.X8] ; /* 0x0000000000127984 */
/* 0x000e680000008a00 */
/*0840*/ LDS R26, [R2.X4+0x18] ; /* 0x00001800021a7984 */
/* 0x000ea20000004800 */
/*0850*/ FFMA R18, R29, R18, R14 ; /* 0x000000121d127223 */
/* 0x002fc8000000000e */
/*0860*/ FFMA R25, R26, R19, R18 ; /* 0x000000131a197223 */
/* 0x004fe20000000012 */
/*0870*/ @P0 BRA 0x2b0 ; /* 0xfffffa3000000947 */
/* 0x000fea000383ffff */
/*0880*/ @!P1 BRA 0xab0 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD R4, R5, c[0x0][0x17c], R2 ; /* 0x00005f0005047a24 */
/* 0x000fe200078e0202 */
/*08a0*/ IADD3 R16, -R7, RZ, RZ ; /* 0x000000ff07107210 */
/* 0x000fe20007ffe1ff */
/*08b0*/ IMAD R15, R9.reuse, 0x2, R0 ; /* 0x00000002090f7824 */
/* 0x040fe200078e0200 */
/*08c0*/ LEA R14, R9.reuse, R2, 0x1 ; /* 0x00000002090e7211 */
/* 0x040fe200078e08ff */
/*08d0*/ IMAD R7, R9, 0x2, R4 ; /* 0x0000000209077824 */
/* 0x000fe400078e0204 */
/*08e0*/ IMAD R4, R15, c[0x0][0x184], R6 ; /* 0x000061000f047a24 */
/* 0x000fe400078e0206 */
/*08f0*/ ISETP.GE.U32.AND P1, PT, R15, c[0x0][0x180], PT ; /* 0x000060000f007a0c */
/* 0x000fe20003f26070 */
/*0900*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*0910*/ ISETP.GE.U32.AND P0, PT, R14, c[0x0][0x17c], PT ; /* 0x00005f000e007a0c */
/* 0x000fe20003f06070 */
/*0920*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0930*/ ISETP.GE.OR P1, PT, R6, c[0x0][0x184], P1 ; /* 0x0000610006007a0c */
/* 0x000fc40000f26670 */
/*0940*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fd60000706670 */
/*0950*/ @!P1 MOV R11, 0x4 ; /* 0x00000004000b9802 */
/* 0x000fe40000000f00 */
/*0960*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff088424 */
/* 0x000fc600078e00ff */
/*0970*/ @!P1 IMAD.WIDE.U32 R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a9625 */
/* 0x000fc800078e000b */
/*0980*/ @!P0 IMAD.WIDE.U32 R8, R7, R8, c[0x0][0x160] ; /* 0x0000580007088625 */
/* 0x000fe200078e0008 */
/*0990*/ @!P1 LDG.E R18, [R10.64] ; /* 0x000000040a129981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ @!P0 LDG.E R20, [R8.64] ; /* 0x0000000408148981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fc80007ffe0ff */
/*09c0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*09d0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x2 ; /* 0x00000002ff157424 */
/* 0x000fe200078e00ff */
/*09e0*/ IADD3 R15, R15, 0x2, RZ ; /* 0x000000020f0f7810 */
/* 0x000fe40007ffe0ff */
/*09f0*/ IADD3 R14, R14, 0x2, RZ ; /* 0x000000020e0e7810 */
/* 0x000fe20007ffe0ff */
/*0a00*/ IMAD R4, R21, c[0x0][0x184], R4 ; /* 0x0000610015047a24 */
/* 0x000fe200078e0204 */
/*0a10*/ IADD3 R7, R7, 0x2, RZ ; /* 0x0000000207077810 */
/* 0x000fe20007ffe0ff */
/*0a20*/ STS [R3+0x10], R18 ; /* 0x0000101203007388 */
/* 0x004fe80000000800 */
/*0a30*/ STS [R3], R20 ; /* 0x0000001403007388 */
/* 0x008fe80000000800 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a50*/ LDS R17, [R2.X4+0x10] ; /* 0x0000100002117984 */
/* 0x000fe80000004800 */
/*0a60*/ LDS.64 R12, [R0.X8] ; /* 0x00000000000c7984 */
/* 0x000e680000008a00 */
/*0a70*/ LDS R19, [R2.X4+0x18] ; /* 0x0000180002137984 */
/* 0x000ea20000004800 */
/*0a80*/ FFMA R12, R17, R12, R25 ; /* 0x0000000c110c7223 */
/* 0x002fc80000000019 */
/*0a90*/ FFMA R25, R19, R13, R12 ; /* 0x0000000d13197223 */
/* 0x004fe2000000000c */
/*0aa0*/ @P0 BRA 0x8f0 ; /* 0xfffffe4000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x18c], PT ; /* 0x0000630006007a0c */
/* 0x000fc80003f06270 */
/*0ac0*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x188], P0 ; /* 0x0000620005007a0c */
/* 0x000fda0000706670 */
/*0ad0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fe20000000f00 */
/*0af0*/ IMAD R2, R5, c[0x0][0x18c], R6 ; /* 0x0000630005027a24 */
/* 0x000fc800078e0206 */
/*0b00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0b10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*0b20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#define Tile_size 2
int numARows, numAColumns;
int numBRows, numBColumns;
int numCRows, numCColumns;
__global__ void matrixMultiplyShared(float *A, float *B, float *C,
int numARows, int numAColumns,
int numBRows, int numBColumns,
int numCRows, int numCColumns) {
__shared__ float sA[Tile_size][Tile_size]; // Tile size to store elements in shared memory
__shared__ float sB[Tile_size][Tile_size];
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
float cvalue = 0.0;
sA[threadIdx.y][threadIdx.x] = 0.0;
sB[threadIdx.y][threadIdx.x] = 0.0;
for (int k = 0; k < (((numAColumns - 1) / Tile_size) + 1); k++) {
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if ((row < numARows) && (threadIdx.x + (k * Tile_size)) < numAColumns) {
sA[threadIdx.y][threadIdx.x] = A[(row * numAColumns) + threadIdx.x + (k * Tile_size)];
} else {
sA[threadIdx.y][threadIdx.x] = 0.0;
}
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if (col < numBColumns && (threadIdx.y + k * Tile_size) < numBRows) {
sB[threadIdx.y][threadIdx.x] = B[(threadIdx.y + k * Tile_size) * numBColumns + col];
} else {
sB[threadIdx.y][threadIdx.x] = 0.0;
}
__syncthreads();
for (int j = 0; j < Tile_size; ++j)//Multiplying Elements present in tile
{
cvalue += sA[threadIdx.y][j] * sB[j][threadIdx.x];
}
}
if (row < numCRows && col < numCColumns)//Saving Final result into Matrix C
{
C[row * numCColumns + col] = cvalue;
}
}
void printMat(int row, int col, float *Mat) {
for (int i = 0; i < row * col; i++) {
printf("%f ", *(Mat + i));
if ((i % col) == 0 && i != 0) {
printf("\n");
}
}
}
void matMultiplyOnHost(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
for (int i = 0; i < numARows; i++) {
for (int j = 0; j < numAColumns; j++) {
C[i * numCColumns + j] = 0.0;
for (int k = 0; k < numCColumns; k++) {
C[i * numCColumns + j] += A[i * numAColumns + k] * B[k * numBColumns + j];
}
}
}
}
int main(int argc, char **argv) {
float *hostA, *hostB, *hostC;
float *hostComputedC;
float *deviceA, *deviceB, *deviceC;
printf("\nEnter Rows and Columns of A:");
scanf("%d %d", &numARows, &numAColumns);
printf("\nEnter Rows and Columns of B:");
scanf("%d %d", &numBRows, &numBColumns);
hostA = (float *) malloc(sizeof(float) * numARows * numAColumns);
hostB = (float *) malloc(sizeof(float) * numBRows * numBColumns);
int lower = 10.0, upper = 20.0;
for (int i = 0; i < numARows * numAColumns; i++)
hostA[i] = (rand() % (upper - lower + 1)) + lower;
for (int i = 0; i < numBRows * numBColumns; i++)
hostB[i] = (rand() % (upper - lower + 1)) + lower;
printf("\nMatrix A Values:\n");
printMat(numARows, numAColumns, hostA);
printf("\n\nMatrix B Values:\n");
printMat(numBRows, numBColumns, hostB);
numCRows = numARows;
numCColumns = numBColumns;
hostC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
hostComputedC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
// Allocating GPU memory
cudaMalloc((void **) &deviceA, sizeof(float) * numARows * numAColumns);
cudaMalloc((void **) &deviceB, sizeof(float) * numBRows * numBColumns);
cudaMalloc((void **) &deviceC, sizeof(float) * numCRows * numCColumns);
// Copy memory to the GPU
cudaMemcpy(deviceA, hostA, sizeof(float) * numARows * numAColumns, cudaMemcpyHostToDevice);
cudaMemcpy(deviceB, hostB, sizeof(float) * numBRows * numBColumns, cudaMemcpyHostToDevice);
// Initialize the grid and block dimensions
dim3 dimGrid((numCColumns / Tile_size) + 1, (numCRows / Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
matrixMultiplyShared<<<dimGrid, dimBlock>>>(deviceA, deviceB, deviceC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
cudaError_t err1 = cudaPeekAtLastError();//To capture last error in function call
cudaDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
cudaMemcpy(hostC, deviceC, sizeof(float) * numCRows * numCColumns, cudaMemcpyDeviceToHost);
printf("\nMatrix C From Device\n");
printMat(numCRows, numCColumns, hostC);//Function Call
matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
printf("\nMatrix C From Host\n");
printMat(numCRows, numCColumns, hostComputedC);
printf("\n\n");
for (int i = 0; i < numCColumns *
numCRows; i++)//Compare both the result matrices 1. MatrixMultiplyonHost 2. MatrixMultiplyonDevice
{
if (hostComputedC[i] != hostC[i]) {
printf("Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n", i / numCColumns,
i % numCColumns, hostComputedC[i], hostC[i]);
break;
}
}
printf("\nNumber of Blocks Created:%d \n", ((numCColumns / Tile_size) + 1) * ((numCColumns / Tile_size) + 1));
printf("\nNumber of Threads Per Block: %d \n", (Tile_size * Tile_size));
// Free the GPU memory
cudaFree(deviceA);
cudaFree(deviceB);
cudaFree(deviceC);
//Free the Pointer Memory
free(hostA);
free(hostB);
free(hostC);
free(hostComputedC);
return 0;
} | .file "tmpxft_000ceb69_00000000-6_mat_mul_shared_memory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.text
.globl _Z8printMatiiPf
.type _Z8printMatiiPf, @function
_Z8printMatiiPf:
.LFB2057:
.cfi_startproc
endbr64
imull %esi, %edi
testl %edi, %edi
jle .L9
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %ebp
movq %rdx, %r13
movslq %edi, %r12
movl $0, %ebx
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L6
.L5:
addq $1, %rbx
cmpq %r12, %rbx
je .L12
.L6:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .L5
testl %ebx, %ebx
je .L5
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L12:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z8printMatiiPf, .-_Z8printMatiiPf
.globl _Z17matMultiplyOnHostPfS_S_iiiiii
.type _Z17matMultiplyOnHostPfS_S_iiiiii, @function
_Z17matMultiplyOnHostPfS_S_iiiiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -8(%rsp)
movl %ecx, -12(%rsp)
movl 72(%rsp), %ebx
testl %ecx, %ecx
jle .L13
movq %rdi, %rbp
movq %rdx, %r15
movl %r8d, %r11d
movslq 56(%rsp), %rdi
salq $2, %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebx, %r14
movq %r15, %r8
movq %r14, %rsi
jmp .L15
.L19:
movslq %ecx, %rax
leaq (%r8,%rax,4), %r10
movq -8(%rsp), %r14
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r15
addq %rsi, %rax
leaq 0(%rbp,%rax,4), %r9
movl $0, %r12d
movl %edx, -20(%rsp)
movl %ecx, -16(%rsp)
.L18:
movq %r10, %rcx
movl $0x00000000, (%r10)
testl %ebx, %ebx
jle .L16
movq %r14, %rdx
movq %r15, %rax
.L17:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L17
.L16:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L18
movl -20(%rsp), %edx
movl -16(%rsp), %ecx
.L20:
addl $1, %edx
addl %ebx, %ecx
addl %r11d, %r13d
cmpl %edx, -12(%rsp)
je .L13
.L15:
testl %r11d, %r11d
jg .L19
jmp .L20
.L13:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z17matMultiplyOnHostPfS_S_iiiiii, .-_Z17matMultiplyOnHostPfS_S_iiiiii
.globl _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.type _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, .-_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.type _Z20matrixMultiplySharedPfS_S_iiiiii, @function
_Z20matrixMultiplySharedPfS_S_iiiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .-_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata.str1.1
.LC3:
.string "\nEnter Rows and Columns of A:"
.LC4:
.string "%d %d"
.LC5:
.string "\nEnter Rows and Columns of B:"
.LC6:
.string "\nMatrix A Values:\n"
.LC7:
.string "\n\nMatrix B Values:\n"
.LC8:
.string "\nMatrix C From Device\n"
.LC9:
.string "\nMatrix C From Host\n"
.LC10:
.string "\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n"
.align 8
.LC12:
.string "\nNumber of Blocks Created:%d \n"
.align 8
.LC13:
.string "\nNumber of Threads Per Block: %d \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq numAColumns(%rip), %rdx
leaq numARows(%rip), %rsi
leaq .LC4(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq numBColumns(%rip), %rdx
leaq numBRows(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl numARows(%rip), %ebx
movl numAColumns(%rip), %r13d
movslq %ebx, %rdi
movslq %r13d, %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movslq numBRows(%rip), %rdi
movslq numBColumns(%rip), %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
imull %r13d, %ebx
testl %ebx, %ebx
jle .L33
movl $0, %ebx
.L34:
call rand@PLT
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
leal (%rdx,%rcx,2), %edx
subl %edx, %eax
addl $10, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
movl numARows(%rip), %eax
imull numAColumns(%rip), %eax
cmpl %ebx, %eax
jg .L34
.L33:
movl numBRows(%rip), %eax
imull numBColumns(%rip), %eax
testl %eax, %eax
jle .L35
movl $0, %ebx
.L36:
call rand@PLT
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
leal (%rdx,%rcx,2), %edx
subl %edx, %eax
addl $10, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
movl numBRows(%rip), %eax
imull numBColumns(%rip), %eax
cmpl %ebx, %eax
jg .L36
.L35:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
movl numAColumns(%rip), %esi
movl numARows(%rip), %edi
call _Z8printMatiiPf
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movl numBColumns(%rip), %esi
movl numBRows(%rip), %edi
call _Z8printMatiiPf
movl numARows(%rip), %r14d
movl %r14d, numCRows(%rip)
movl numBColumns(%rip), %ebx
movl %ebx, numCColumns(%rip)
movslq %r14d, %r14
movslq %ebx, %rbx
imulq %r14, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movslq numAColumns(%rip), %rsi
imulq %r14, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq numBRows(%rip), %rsi
movslq numBColumns(%rip), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq numCRows(%rip), %rsi
movslq numCColumns(%rip), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq numARows(%rip), %rdx
movslq numAColumns(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq numBRows(%rip), %rdx
movslq numBColumns(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl numCRows(%rip), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl $1, %eax
movl numCColumns(%rip), %ecx
movl %ecx, %edx
shrl $31, %edx
addl %ecx, %edx
sarl %edx
addl $1, %edx
movl %edx, 32(%rsp)
movl %eax, 36(%rsp)
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L37:
call cudaPeekAtLastError@PLT
call cudaDeviceSynchronize@PLT
movslq numCRows(%rip), %rdx
movslq numCColumns(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
movl numCColumns(%rip), %esi
movl numCRows(%rip), %edi
call _Z8printMatiiPf
subq $8, %rsp
.cfi_def_cfa_offset 120
movl numCColumns(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 128
movl numCRows(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 136
movl numBColumns(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl numBRows(%rip), %r9d
movl numAColumns(%rip), %r8d
movl numARows(%rip), %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z17matMultiplyOnHostPfS_S_iiiiii
addq $32, %rsp
.cfi_def_cfa_offset 112
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
movl numCColumns(%rip), %esi
movl numCRows(%rip), %edi
call _Z8printMatiiPf
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl numCColumns(%rip), %esi
movl %esi, %edx
imull numCRows(%rip), %edx
testl %edx, %edx
jle .L38
movslq %edx, %rdx
movl $0, %eax
.L41:
movss (%rbx,%rax,4), %xmm0
movss 0(%r13,%rax,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L43
jne .L43
addq $1, %rax
cmpq %rax, %rdx
jne .L41
jmp .L38
.L48:
subq $8, %rsp
.cfi_def_cfa_offset 120
movl numCColumns(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 128
movl numCRows(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 136
movl numBColumns(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl numBRows(%rip), %r9d
movl numAColumns(%rip), %r8d
movl numARows(%rip), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
addq $32, %rsp
.cfi_def_cfa_offset 112
jmp .L37
.L43:
cvtss2sd %xmm0, %xmm0
cltd
idivl %esi
movl %edx, %ecx
cvtss2sd %xmm1, %xmm1
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L38:
movl numCColumns(%rip), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
addl $1, %edx
imull %edx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z20matrixMultiplySharedPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl numCColumns
.bss
.align 4
.type numCColumns, @object
.size numCColumns, 4
numCColumns:
.zero 4
.globl numCRows
.align 4
.type numCRows, @object
.size numCRows, 4
numCRows:
.zero 4
.globl numBColumns
.align 4
.type numBColumns, @object
.size numBColumns, 4
numBColumns:
.zero 4
.globl numBRows
.align 4
.type numBRows, @object
.size numBRows, 4
numBRows:
.zero 4
.globl numAColumns
.align 4
.type numAColumns, @object
.size numAColumns, 4
numAColumns:
.zero 4
.globl numARows
.align 4
.type numARows, @object
.size numARows, 4
numARows:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#define Tile_size 2
int numARows, numAColumns;
int numBRows, numBColumns;
int numCRows, numCColumns;
__global__ void matrixMultiplyShared(float *A, float *B, float *C,
int numARows, int numAColumns,
int numBRows, int numBColumns,
int numCRows, int numCColumns) {
__shared__ float sA[Tile_size][Tile_size]; // Tile size to store elements in shared memory
__shared__ float sB[Tile_size][Tile_size];
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
float cvalue = 0.0;
sA[threadIdx.y][threadIdx.x] = 0.0;
sB[threadIdx.y][threadIdx.x] = 0.0;
for (int k = 0; k < (((numAColumns - 1) / Tile_size) + 1); k++) {
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if ((row < numARows) && (threadIdx.x + (k * Tile_size)) < numAColumns) {
sA[threadIdx.y][threadIdx.x] = A[(row * numAColumns) + threadIdx.x + (k * Tile_size)];
} else {
sA[threadIdx.y][threadIdx.x] = 0.0;
}
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if (col < numBColumns && (threadIdx.y + k * Tile_size) < numBRows) {
sB[threadIdx.y][threadIdx.x] = B[(threadIdx.y + k * Tile_size) * numBColumns + col];
} else {
sB[threadIdx.y][threadIdx.x] = 0.0;
}
__syncthreads();
for (int j = 0; j < Tile_size; ++j)//Multiplying Elements present in tile
{
cvalue += sA[threadIdx.y][j] * sB[j][threadIdx.x];
}
}
if (row < numCRows && col < numCColumns)//Saving Final result into Matrix C
{
C[row * numCColumns + col] = cvalue;
}
}
void printMat(int row, int col, float *Mat) {
for (int i = 0; i < row * col; i++) {
printf("%f ", *(Mat + i));
if ((i % col) == 0 && i != 0) {
printf("\n");
}
}
}
void matMultiplyOnHost(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
for (int i = 0; i < numARows; i++) {
for (int j = 0; j < numAColumns; j++) {
C[i * numCColumns + j] = 0.0;
for (int k = 0; k < numCColumns; k++) {
C[i * numCColumns + j] += A[i * numAColumns + k] * B[k * numBColumns + j];
}
}
}
}
int main(int argc, char **argv) {
float *hostA, *hostB, *hostC;
float *hostComputedC;
float *deviceA, *deviceB, *deviceC;
printf("\nEnter Rows and Columns of A:");
scanf("%d %d", &numARows, &numAColumns);
printf("\nEnter Rows and Columns of B:");
scanf("%d %d", &numBRows, &numBColumns);
hostA = (float *) malloc(sizeof(float) * numARows * numAColumns);
hostB = (float *) malloc(sizeof(float) * numBRows * numBColumns);
int lower = 10.0, upper = 20.0;
for (int i = 0; i < numARows * numAColumns; i++)
hostA[i] = (rand() % (upper - lower + 1)) + lower;
for (int i = 0; i < numBRows * numBColumns; i++)
hostB[i] = (rand() % (upper - lower + 1)) + lower;
printf("\nMatrix A Values:\n");
printMat(numARows, numAColumns, hostA);
printf("\n\nMatrix B Values:\n");
printMat(numBRows, numBColumns, hostB);
numCRows = numARows;
numCColumns = numBColumns;
hostC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
hostComputedC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
// Allocating GPU memory
cudaMalloc((void **) &deviceA, sizeof(float) * numARows * numAColumns);
cudaMalloc((void **) &deviceB, sizeof(float) * numBRows * numBColumns);
cudaMalloc((void **) &deviceC, sizeof(float) * numCRows * numCColumns);
// Copy memory to the GPU
cudaMemcpy(deviceA, hostA, sizeof(float) * numARows * numAColumns, cudaMemcpyHostToDevice);
cudaMemcpy(deviceB, hostB, sizeof(float) * numBRows * numBColumns, cudaMemcpyHostToDevice);
// Initialize the grid and block dimensions
dim3 dimGrid((numCColumns / Tile_size) + 1, (numCRows / Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
matrixMultiplyShared<<<dimGrid, dimBlock>>>(deviceA, deviceB, deviceC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
cudaError_t err1 = cudaPeekAtLastError();//To capture last error in function call
cudaDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
cudaMemcpy(hostC, deviceC, sizeof(float) * numCRows * numCColumns, cudaMemcpyDeviceToHost);
printf("\nMatrix C From Device\n");
printMat(numCRows, numCColumns, hostC);//Function Call
matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
printf("\nMatrix C From Host\n");
printMat(numCRows, numCColumns, hostComputedC);
printf("\n\n");
for (int i = 0; i < numCColumns *
numCRows; i++)//Compare both the result matrices 1. MatrixMultiplyonHost 2. MatrixMultiplyonDevice
{
if (hostComputedC[i] != hostC[i]) {
printf("Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n", i / numCColumns,
i % numCColumns, hostComputedC[i], hostC[i]);
break;
}
}
printf("\nNumber of Blocks Created:%d \n", ((numCColumns / Tile_size) + 1) * ((numCColumns / Tile_size) + 1));
printf("\nNumber of Threads Per Block: %d \n", (Tile_size * Tile_size));
// Free the GPU memory
cudaFree(deviceA);
cudaFree(deviceB);
cudaFree(deviceC);
//Free the Pointer Memory
free(hostA);
free(hostB);
free(hostC);
free(hostComputedC);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define Tile_size 2
int numARows, numAColumns;
int numBRows, numBColumns;
int numCRows, numCColumns;
__global__ void matrixMultiplyShared(float *A, float *B, float *C,
int numARows, int numAColumns,
int numBRows, int numBColumns,
int numCRows, int numCColumns) {
__shared__ float sA[Tile_size][Tile_size]; // Tile size to store elements in shared memory
__shared__ float sB[Tile_size][Tile_size];
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
float cvalue = 0.0;
sA[threadIdx.y][threadIdx.x] = 0.0;
sB[threadIdx.y][threadIdx.x] = 0.0;
for (int k = 0; k < (((numAColumns - 1) / Tile_size) + 1); k++) {
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if ((row < numARows) && (threadIdx.x + (k * Tile_size)) < numAColumns) {
sA[threadIdx.y][threadIdx.x] = A[(row * numAColumns) + threadIdx.x + (k * Tile_size)];
} else {
sA[threadIdx.y][threadIdx.x] = 0.0;
}
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if (col < numBColumns && (threadIdx.y + k * Tile_size) < numBRows) {
sB[threadIdx.y][threadIdx.x] = B[(threadIdx.y + k * Tile_size) * numBColumns + col];
} else {
sB[threadIdx.y][threadIdx.x] = 0.0;
}
__syncthreads();
for (int j = 0; j < Tile_size; ++j)//Multiplying Elements present in tile
{
cvalue += sA[threadIdx.y][j] * sB[j][threadIdx.x];
}
}
if (row < numCRows && col < numCColumns)//Saving Final result into Matrix C
{
C[row * numCColumns + col] = cvalue;
}
}
void printMat(int row, int col, float *Mat) {
for (int i = 0; i < row * col; i++) {
printf("%f ", *(Mat + i));
if ((i % col) == 0 && i != 0) {
printf("\n");
}
}
}
void matMultiplyOnHost(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
for (int i = 0; i < numARows; i++) {
for (int j = 0; j < numAColumns; j++) {
C[i * numCColumns + j] = 0.0;
for (int k = 0; k < numCColumns; k++) {
C[i * numCColumns + j] += A[i * numAColumns + k] * B[k * numBColumns + j];
}
}
}
}
int main(int argc, char **argv) {
float *hostA, *hostB, *hostC;
float *hostComputedC;
float *deviceA, *deviceB, *deviceC;
printf("\nEnter Rows and Columns of A:");
scanf("%d %d", &numARows, &numAColumns);
printf("\nEnter Rows and Columns of B:");
scanf("%d %d", &numBRows, &numBColumns);
hostA = (float *) malloc(sizeof(float) * numARows * numAColumns);
hostB = (float *) malloc(sizeof(float) * numBRows * numBColumns);
int lower = 10.0, upper = 20.0;
for (int i = 0; i < numARows * numAColumns; i++)
hostA[i] = (rand() % (upper - lower + 1)) + lower;
for (int i = 0; i < numBRows * numBColumns; i++)
hostB[i] = (rand() % (upper - lower + 1)) + lower;
printf("\nMatrix A Values:\n");
printMat(numARows, numAColumns, hostA);
printf("\n\nMatrix B Values:\n");
printMat(numBRows, numBColumns, hostB);
numCRows = numARows;
numCColumns = numBColumns;
hostC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
hostComputedC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
// Allocating GPU memory
hipMalloc((void **) &deviceA, sizeof(float) * numARows * numAColumns);
hipMalloc((void **) &deviceB, sizeof(float) * numBRows * numBColumns);
hipMalloc((void **) &deviceC, sizeof(float) * numCRows * numCColumns);
// Copy memory to the GPU
hipMemcpy(deviceA, hostA, sizeof(float) * numARows * numAColumns, hipMemcpyHostToDevice);
hipMemcpy(deviceB, hostB, sizeof(float) * numBRows * numBColumns, hipMemcpyHostToDevice);
// Initialize the grid and block dimensions
dim3 dimGrid((numCColumns / Tile_size) + 1, (numCRows / Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
matrixMultiplyShared<<<dimGrid, dimBlock>>>(deviceA, deviceB, deviceC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
hipError_t err1 = hipPeekAtLastError();//To capture last error in function call
hipDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
hipMemcpy(hostC, deviceC, sizeof(float) * numCRows * numCColumns, hipMemcpyDeviceToHost);
printf("\nMatrix C From Device\n");
printMat(numCRows, numCColumns, hostC);//Function Call
matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
printf("\nMatrix C From Host\n");
printMat(numCRows, numCColumns, hostComputedC);
printf("\n\n");
for (int i = 0; i < numCColumns *
numCRows; i++)//Compare both the result matrices 1. MatrixMultiplyonHost 2. MatrixMultiplyonDevice
{
if (hostComputedC[i] != hostC[i]) {
printf("Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n", i / numCColumns,
i % numCColumns, hostComputedC[i], hostC[i]);
break;
}
}
printf("\nNumber of Blocks Created:%d \n", ((numCColumns / Tile_size) + 1) * ((numCColumns / Tile_size) + 1));
printf("\nNumber of Threads Per Block: %d \n", (Tile_size * Tile_size));
// Free the GPU memory
hipFree(deviceA);
hipFree(deviceB);
hipFree(deviceC);
//Free the Pointer Memory
free(hostA);
free(hostB);
free(hostC);
free(hostComputedC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define Tile_size 2
int numARows, numAColumns;
int numBRows, numBColumns;
int numCRows, numCColumns;
__global__ void matrixMultiplyShared(float *A, float *B, float *C,
int numARows, int numAColumns,
int numBRows, int numBColumns,
int numCRows, int numCColumns) {
__shared__ float sA[Tile_size][Tile_size]; // Tile size to store elements in shared memory
__shared__ float sB[Tile_size][Tile_size];
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
float cvalue = 0.0;
sA[threadIdx.y][threadIdx.x] = 0.0;
sB[threadIdx.y][threadIdx.x] = 0.0;
for (int k = 0; k < (((numAColumns - 1) / Tile_size) + 1); k++) {
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if ((row < numARows) && (threadIdx.x + (k * Tile_size)) < numAColumns) {
sA[threadIdx.y][threadIdx.x] = A[(row * numAColumns) + threadIdx.x + (k * Tile_size)];
} else {
sA[threadIdx.y][threadIdx.x] = 0.0;
}
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if (col < numBColumns && (threadIdx.y + k * Tile_size) < numBRows) {
sB[threadIdx.y][threadIdx.x] = B[(threadIdx.y + k * Tile_size) * numBColumns + col];
} else {
sB[threadIdx.y][threadIdx.x] = 0.0;
}
__syncthreads();
for (int j = 0; j < Tile_size; ++j)//Multiplying Elements present in tile
{
cvalue += sA[threadIdx.y][j] * sB[j][threadIdx.x];
}
}
if (row < numCRows && col < numCColumns)//Saving Final result into Matrix C
{
C[row * numCColumns + col] = cvalue;
}
}
void printMat(int row, int col, float *Mat) {
for (int i = 0; i < row * col; i++) {
printf("%f ", *(Mat + i));
if ((i % col) == 0 && i != 0) {
printf("\n");
}
}
}
void matMultiplyOnHost(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
for (int i = 0; i < numARows; i++) {
for (int j = 0; j < numAColumns; j++) {
C[i * numCColumns + j] = 0.0;
for (int k = 0; k < numCColumns; k++) {
C[i * numCColumns + j] += A[i * numAColumns + k] * B[k * numBColumns + j];
}
}
}
}
int main(int argc, char **argv) {
float *hostA, *hostB, *hostC;
float *hostComputedC;
float *deviceA, *deviceB, *deviceC;
printf("\nEnter Rows and Columns of A:");
scanf("%d %d", &numARows, &numAColumns);
printf("\nEnter Rows and Columns of B:");
scanf("%d %d", &numBRows, &numBColumns);
hostA = (float *) malloc(sizeof(float) * numARows * numAColumns);
hostB = (float *) malloc(sizeof(float) * numBRows * numBColumns);
int lower = 10.0, upper = 20.0;
for (int i = 0; i < numARows * numAColumns; i++)
hostA[i] = (rand() % (upper - lower + 1)) + lower;
for (int i = 0; i < numBRows * numBColumns; i++)
hostB[i] = (rand() % (upper - lower + 1)) + lower;
printf("\nMatrix A Values:\n");
printMat(numARows, numAColumns, hostA);
printf("\n\nMatrix B Values:\n");
printMat(numBRows, numBColumns, hostB);
numCRows = numARows;
numCColumns = numBColumns;
hostC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
hostComputedC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
// Allocating GPU memory
hipMalloc((void **) &deviceA, sizeof(float) * numARows * numAColumns);
hipMalloc((void **) &deviceB, sizeof(float) * numBRows * numBColumns);
hipMalloc((void **) &deviceC, sizeof(float) * numCRows * numCColumns);
// Copy memory to the GPU
hipMemcpy(deviceA, hostA, sizeof(float) * numARows * numAColumns, hipMemcpyHostToDevice);
hipMemcpy(deviceB, hostB, sizeof(float) * numBRows * numBColumns, hipMemcpyHostToDevice);
// Initialize the grid and block dimensions
dim3 dimGrid((numCColumns / Tile_size) + 1, (numCRows / Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
matrixMultiplyShared<<<dimGrid, dimBlock>>>(deviceA, deviceB, deviceC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
hipError_t err1 = hipPeekAtLastError();//To capture last error in function call
hipDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
hipMemcpy(hostC, deviceC, sizeof(float) * numCRows * numCColumns, hipMemcpyDeviceToHost);
printf("\nMatrix C From Device\n");
printMat(numCRows, numCColumns, hostC);//Function Call
matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
printf("\nMatrix C From Host\n");
printMat(numCRows, numCColumns, hostComputedC);
printf("\n\n");
for (int i = 0; i < numCColumns *
numCRows; i++)//Compare both the result matrices 1. MatrixMultiplyonHost 2. MatrixMultiplyonDevice
{
if (hostComputedC[i] != hostC[i]) {
printf("Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n", i / numCColumns,
i % numCColumns, hostComputedC[i], hostC[i]);
break;
}
}
printf("\nNumber of Blocks Created:%d \n", ((numCColumns / Tile_size) + 1) * ((numCColumns / Tile_size) + 1));
printf("\nNumber of Threads Per Block: %d \n", (Tile_size * Tile_size));
// Free the GPU memory
hipFree(deviceA);
hipFree(deviceB);
hipFree(deviceC);
//Free the Pointer Memory
free(hostA);
free(hostB);
free(hostC);
free(hostComputedC);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20matrixMultiplySharedPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 8
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@function
_Z20matrixMultiplySharedPfS_S_iiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s10, s[0:1], 0x1c
v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 2, v3
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_lshl_add_u32 v2, v4, 3, v5
v_mov_b32_e32 v5, 0
s_cmp_lt_i32 s10, 0
ds_store_2addr_b32 v2, v5, v5 offset1:4
s_cbranch_scc1 .LBB0_14
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_add_i32 s3, s10, -1
v_mad_u64_u32 v[5:6], null, v0, s10, v[3:4]
s_lshr_b32 s12, s3, 31
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v9, 16, v2
s_add_i32 s3, s3, s12
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v10, 3, v4
v_lshl_add_u32 v11, v3, 2, 16
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_max_i32 s12, s3, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s9, v1
.LBB0_2:
v_mov_b32_e32 v6, 0
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_6
s_lshl_b32 s15, s11, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s15, v3
v_cmp_gt_u32_e64 s3, s10, v6
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s14, s3
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v6, s15, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[6:7]
v_add_co_u32 v12, s3, s4, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s3, s5, v13, s3
global_load_b32 v6, v[12:13], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v12, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v6
s_and_saveexec_b32 s13, s2
s_cbranch_execz .LBB0_10
v_lshl_add_u32 v6, s11, 1, v4
v_mov_b32_e32 v12, 0
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 s8, v6
s_cbranch_execz .LBB0_9
v_mad_u64_u32 v[12:13], null, v6, s9, v[1:2]
v_mov_b32_e32 v13, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, s3, s6, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s3, s7, v13, s3
global_load_b32 v12, v[12:13], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v6, v11
s_mov_b32 s3, 0
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v12, s3, v10
s_add_i32 s3, s3, 4
ds_load_b32 v13, v6
ds_load_b32 v12, v12
v_add_nc_u32_e32 v6, 8, v6
s_cmp_lg_u32 s3, 4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v8, v12, v13
s_cbranch_scc0 .LBB0_11
s_add_i32 s3, s11, 1
s_cmp_eq_u32 s11, s12
s_cbranch_scc1 .LBB0_14
s_mov_b32 s11, s3
s_branch .LBB0_2
.LBB0_14:
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v8, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20matrixMultiplySharedPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z20matrixMultiplySharedPfS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20matrixMultiplySharedPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20matrixMultiplySharedPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define Tile_size 2
int numARows, numAColumns;
int numBRows, numBColumns;
int numCRows, numCColumns;
__global__ void matrixMultiplyShared(float *A, float *B, float *C,
int numARows, int numAColumns,
int numBRows, int numBColumns,
int numCRows, int numCColumns) {
__shared__ float sA[Tile_size][Tile_size]; // Tile size to store elements in shared memory
__shared__ float sB[Tile_size][Tile_size];
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
float cvalue = 0.0;
sA[threadIdx.y][threadIdx.x] = 0.0;
sB[threadIdx.y][threadIdx.x] = 0.0;
for (int k = 0; k < (((numAColumns - 1) / Tile_size) + 1); k++) {
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if ((row < numARows) && (threadIdx.x + (k * Tile_size)) < numAColumns) {
sA[threadIdx.y][threadIdx.x] = A[(row * numAColumns) + threadIdx.x + (k * Tile_size)];
} else {
sA[threadIdx.y][threadIdx.x] = 0.0;
}
//Copy Data to Tile from Matrix (Global Memory to Shared Memory)
if (col < numBColumns && (threadIdx.y + k * Tile_size) < numBRows) {
sB[threadIdx.y][threadIdx.x] = B[(threadIdx.y + k * Tile_size) * numBColumns + col];
} else {
sB[threadIdx.y][threadIdx.x] = 0.0;
}
__syncthreads();
for (int j = 0; j < Tile_size; ++j)//Multiplying Elements present in tile
{
cvalue += sA[threadIdx.y][j] * sB[j][threadIdx.x];
}
}
if (row < numCRows && col < numCColumns)//Saving Final result into Matrix C
{
C[row * numCColumns + col] = cvalue;
}
}
void printMat(int row, int col, float *Mat) {
for (int i = 0; i < row * col; i++) {
printf("%f ", *(Mat + i));
if ((i % col) == 0 && i != 0) {
printf("\n");
}
}
}
void matMultiplyOnHost(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
for (int i = 0; i < numARows; i++) {
for (int j = 0; j < numAColumns; j++) {
C[i * numCColumns + j] = 0.0;
for (int k = 0; k < numCColumns; k++) {
C[i * numCColumns + j] += A[i * numAColumns + k] * B[k * numBColumns + j];
}
}
}
}
int main(int argc, char **argv) {
float *hostA, *hostB, *hostC;
float *hostComputedC;
float *deviceA, *deviceB, *deviceC;
printf("\nEnter Rows and Columns of A:");
scanf("%d %d", &numARows, &numAColumns);
printf("\nEnter Rows and Columns of B:");
scanf("%d %d", &numBRows, &numBColumns);
hostA = (float *) malloc(sizeof(float) * numARows * numAColumns);
hostB = (float *) malloc(sizeof(float) * numBRows * numBColumns);
int lower = 10.0, upper = 20.0;
for (int i = 0; i < numARows * numAColumns; i++)
hostA[i] = (rand() % (upper - lower + 1)) + lower;
for (int i = 0; i < numBRows * numBColumns; i++)
hostB[i] = (rand() % (upper - lower + 1)) + lower;
printf("\nMatrix A Values:\n");
printMat(numARows, numAColumns, hostA);
printf("\n\nMatrix B Values:\n");
printMat(numBRows, numBColumns, hostB);
numCRows = numARows;
numCColumns = numBColumns;
hostC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
hostComputedC = (float *) malloc(sizeof(float) * numCRows * numCColumns);
// Allocating GPU memory
hipMalloc((void **) &deviceA, sizeof(float) * numARows * numAColumns);
hipMalloc((void **) &deviceB, sizeof(float) * numBRows * numBColumns);
hipMalloc((void **) &deviceC, sizeof(float) * numCRows * numCColumns);
// Copy memory to the GPU
hipMemcpy(deviceA, hostA, sizeof(float) * numARows * numAColumns, hipMemcpyHostToDevice);
hipMemcpy(deviceB, hostB, sizeof(float) * numBRows * numBColumns, hipMemcpyHostToDevice);
// Initialize the grid and block dimensions
dim3 dimGrid((numCColumns / Tile_size) + 1, (numCRows / Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
matrixMultiplyShared<<<dimGrid, dimBlock>>>(deviceA, deviceB, deviceC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
hipError_t err1 = hipPeekAtLastError();//To capture last error in function call
hipDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
hipMemcpy(hostC, deviceC, sizeof(float) * numCRows * numCColumns, hipMemcpyDeviceToHost);
printf("\nMatrix C From Device\n");
printMat(numCRows, numCColumns, hostC);//Function Call
matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
printf("\nMatrix C From Host\n");
printMat(numCRows, numCColumns, hostComputedC);
printf("\n\n");
for (int i = 0; i < numCColumns *
numCRows; i++)//Compare both the result matrices 1. MatrixMultiplyonHost 2. MatrixMultiplyonDevice
{
if (hostComputedC[i] != hostC[i]) {
printf("Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n", i / numCColumns,
i % numCColumns, hostComputedC[i], hostC[i]);
break;
}
}
printf("\nNumber of Blocks Created:%d \n", ((numCColumns / Tile_size) + 1) * ((numCColumns / Tile_size) + 1));
printf("\nNumber of Threads Per Block: %d \n", (Tile_size * Tile_size));
// Free the GPU memory
hipFree(deviceA);
hipFree(deviceB);
hipFree(deviceC);
//Free the Pointer Memory
free(hostA);
free(hostB);
free(hostC);
free(hostComputedC);
return 0;
} | .text
.file "mat_mul_shared_memory.hip"
.globl _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii # -- Begin function _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.p2align 4, 0x90
.type _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii,@function
_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii: # @_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_endproc
# -- End function
.globl _Z8printMatiiPf # -- Begin function _Z8printMatiiPf
.p2align 4, 0x90
.type _Z8printMatiiPf,@function
_Z8printMatiiPf: # @_Z8printMatiiPf
.cfi_startproc
# %bb.0:
imull %esi, %edi
testl %edi, %edi
jle .LBB1_7
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, %ebp
movl %edi, %r15d
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_2 Depth=1
incq %r14
cmpq %r14, %r15
je .LBB1_6
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r14d, %eax
cltd
idivl %ebp
testq %r14, %r14
je .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
testl %edx, %edx
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_5
.LBB1_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_7: # %._crit_edge
retq
.Lfunc_end1:
.size _Z8printMatiiPf, .Lfunc_end1-_Z8printMatiiPf
.cfi_endproc
# -- End function
.globl _Z17matMultiplyOnHostPfS_S_iiiiii # -- Begin function _Z17matMultiplyOnHostPfS_S_iiiiii
.p2align 4, 0x90
.type _Z17matMultiplyOnHostPfS_S_iiiiii,@function
_Z17matMultiplyOnHostPfS_S_iiiiii: # @_Z17matMultiplyOnHostPfS_S_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB2_9
# %bb.1: # %.preheader.lr.ph
movl 72(%rsp), %eax
movslq 56(%rsp), %r9
movslq %eax, %r10
movslq %r8d, %r11
movl %ecx, %ecx
movl %r11d, %ebx
movl %r10d, %r14d
shlq $2, %r11
shlq $2, %r9
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r15
addq %r11, %rdi
cmpq %rcx, %r15
je .LBB2_9
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
testl %r8d, %r8d
jle .LBB2_8
# %bb.3: # %.lr.ph29
# in Loop: Header=BB2_2 Depth=1
movq %r15, %rdx
imulq %r10, %rdx
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r12
movq -16(%rsp), %rsi # 8-byte Reload
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
incq %rbp
addq $4, %rsi
cmpq %rbx, %rbp
je .LBB2_8
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
movl $0, (%r12,%rbp,4)
testl %eax, %eax
jle .LBB2_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB2_4 Depth=2
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rsi, %r13
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r13), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rdx
addq %r9, %r13
cmpq %rdx, %r14
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z17matMultiplyOnHostPfS_S_iiiiii, .Lfunc_end2-_Z17matMultiplyOnHostPfS_S_iiiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $numARows, %esi
movl $numAColumns, %edx
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $numBRows, %esi
movl $numBColumns, %edx
xorl %eax, %eax
callq __isoc23_scanf
movslq numARows(%rip), %rax
movslq numAColumns(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r13
movslq numBRows(%rip), %rax
movslq numBColumns(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
movl numAColumns(%rip), %eax
imull numARows(%rip), %eax
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
negl %ecx
addl %ecx, %eax
addl $10, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%rbx,4)
incq %rbx
movslq numARows(%rip), %rax
movslq numAColumns(%rip), %rcx
imulq %rax, %rcx
cmpq %rcx, %rbx
jl .LBB3_2
.LBB3_3: # %.preheader
movl numBColumns(%rip), %eax
imull numBRows(%rip), %eax
testl %eax, %eax
jle .LBB3_6
# %bb.4: # %.lr.ph95.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_5: # %.lr.ph95
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
negl %ecx
addl %ecx, %eax
addl $10, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rbx,4)
incq %rbx
movslq numBRows(%rip), %rax
movslq numBColumns(%rip), %rcx
imulq %rax, %rcx
cmpq %rcx, %rbx
jl .LBB3_5
.LBB3_6: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
movl numAColumns(%rip), %ebp
movl numARows(%rip), %eax
imull %ebp, %eax
testl %eax, %eax
jle .LBB3_12
# %bb.7: # %.lr.ph.preheader.i
movl %eax, %r12d
xorl %r15d, %r15d
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_8 Depth=1
incq %r15
cmpq %r15, %r12
je .LBB3_12
.LBB3_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r13,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r15d, %eax
cltd
idivl %ebp
testq %r15, %r15
je .LBB3_11
# %bb.9: # %.lr.ph.i
# in Loop: Header=BB3_8 Depth=1
testl %edx, %edx
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_8 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_11
.LBB3_12: # %_Z8printMatiiPf.exit
movl $.Lstr.1, %edi
callq puts@PLT
movl numBColumns(%rip), %ebp
movl numBRows(%rip), %eax
imull %ebp, %eax
testl %eax, %eax
jle .LBB3_18
# %bb.13: # %.lr.ph.preheader.i54
movl %eax, %r12d
xorl %r15d, %r15d
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_14 Depth=1
incq %r15
cmpq %r15, %r12
je .LBB3_18
.LBB3_14: # %.lr.ph.i56
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r15d, %eax
cltd
idivl %ebp
testq %r15, %r15
je .LBB3_17
# %bb.15: # %.lr.ph.i56
# in Loop: Header=BB3_14 Depth=1
testl %edx, %edx
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_14 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_17
.LBB3_18: # %_Z8printMatiiPf.exit62
movslq numARows(%rip), %rbx
movl %ebx, numCRows(%rip)
movslq numBColumns(%rip), %r12
movl %r12d, numCColumns(%rip)
shlq $2, %rbx
imulq %rbx, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r12
movslq numAColumns(%rip), %rsi
imulq %rbx, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq numBRows(%rip), %rax
movslq numBColumns(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movslq numCRows(%rip), %rax
movslq numCColumns(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movslq numARows(%rip), %rax
movslq numAColumns(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, 56(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq numBRows(%rip), %rax
movslq numBColumns(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, 64(%rsp) # 8-byte Spill
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl numCColumns(%rip), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
incl %ecx
movl numCRows(%rip), %eax
movl %eax, %edi
shrl $31, %edi
addl %eax, %edi
sarl %edi
incl %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl numARows(%rip), %esi
movl numAColumns(%rip), %edi
movl numBRows(%rip), %r8d
movl numBColumns(%rip), %r9d
movl numCRows(%rip), %r10d
movl numCColumns(%rip), %r11d
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %esi, 52(%rsp)
movl %edi, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movl %r10d, 36(%rsp)
movl %r11d, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 36(%rsp), %rax
movq %rax, 200(%rsp)
leaq 32(%rsp), %rax
movq %rax, 208(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20:
callq hipPeekAtLastError
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movslq numCRows(%rip), %rax
movslq numCColumns(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %r14
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl numCColumns(%rip), %ebp
movl numCRows(%rip), %eax
imull %ebp, %eax
testl %eax, %eax
jle .LBB3_26
# %bb.21: # %.lr.ph.preheader.i63
movl %eax, %ebx
xorl %r13d, %r13d
jmp .LBB3_22
.p2align 4, 0x90
.LBB3_25: # in Loop: Header=BB3_22 Depth=1
incq %r13
cmpq %r13, %rbx
je .LBB3_26
.LBB3_22: # %.lr.ph.i65
# =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r13d, %eax
cltd
idivl %ebp
testq %r13, %r13
je .LBB3_25
# %bb.23: # %.lr.ph.i65
# in Loop: Header=BB3_22 Depth=1
testl %edx, %edx
jne .LBB3_25
# %bb.24: # in Loop: Header=BB3_22 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_25
.LBB3_26: # %_Z8printMatiiPf.exit71
movl numARows(%rip), %eax
testl %eax, %eax
jle .LBB3_36
# %bb.27: # %.preheader.lr.ph.i
movl numCColumns(%rip), %ecx
movl numAColumns(%rip), %edx
movslq numBColumns(%rip), %rsi
movslq %ecx, %rdi
movslq %edx, %r8
shlq $2, %r8
shlq $2, %rsi
xorl %r9d, %r9d
movq 56(%rsp), %r10 # 8-byte Reload
jmp .LBB3_28
.p2align 4, 0x90
.LBB3_35: # %._crit_edge30.i
# in Loop: Header=BB3_28 Depth=1
incq %r9
addq %r8, %r10
cmpq %rax, %r9
je .LBB3_36
.LBB3_28: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_30 Depth 2
# Child Loop BB3_32 Depth 3
testl %edx, %edx
jle .LBB3_35
# %bb.29: # %.lr.ph29.i
# in Loop: Header=BB3_28 Depth=1
movq %r9, %r11
imulq %rdi, %r11
leaq (%r12,%r11,4), %r11
movq 64(%rsp), %r13 # 8-byte Reload
xorl %ebp, %ebp
jmp .LBB3_30
.p2align 4, 0x90
.LBB3_34: # %._crit_edge.i
# in Loop: Header=BB3_30 Depth=2
incq %rbp
addq $4, %r13
cmpq %rdx, %rbp
je .LBB3_35
.LBB3_30: # Parent Loop BB3_28 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_32 Depth 3
movl $0, (%r11,%rbp,4)
testl %ecx, %ecx
jle .LBB3_34
# %bb.31: # %.lr.ph.i72
# in Loop: Header=BB3_30 Depth=2
xorps %xmm0, %xmm0
movq %r13, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_32: # Parent Loop BB3_28 Depth=1
# Parent Loop BB3_30 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r10,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbx), %xmm1
addss %xmm1, %xmm0
incq %r15
addq %rsi, %rbx
cmpq %r15, %rcx
jne .LBB3_32
# %bb.33: # %._crit_edge.i.loopexit
# in Loop: Header=BB3_30 Depth=2
movss %xmm0, (%r11,%rbp,4)
jmp .LBB3_34
.LBB3_36: # %_Z17matMultiplyOnHostPfS_S_iiiiii.exit
movl $.Lstr.3, %edi
callq puts@PLT
movl numCColumns(%rip), %ebp
movl numCRows(%rip), %eax
imull %ebp, %eax
testl %eax, %eax
jle .LBB3_42
# %bb.37: # %.lr.ph.preheader.i78
movl %eax, %ebx
xorl %r13d, %r13d
jmp .LBB3_38
.p2align 4, 0x90
.LBB3_41: # in Loop: Header=BB3_38 Depth=1
incq %r13
cmpq %r13, %rbx
je .LBB3_42
.LBB3_38: # %.lr.ph.i80
# =>This Inner Loop Header: Depth=1
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r13d, %eax
cltd
idivl %ebp
testq %r13, %r13
je .LBB3_41
# %bb.39: # %.lr.ph.i80
# in Loop: Header=BB3_38 Depth=1
testl %edx, %edx
jne .LBB3_41
# %bb.40: # in Loop: Header=BB3_38 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_41
.LBB3_42: # %_Z8printMatiiPf.exit86
movl $.Lstr.4, %edi
callq puts@PLT
movl numCColumns(%rip), %ecx
movl numCRows(%rip), %eax
imull %ecx, %eax
testl %eax, %eax
movq 56(%rsp), %rbx # 8-byte Reload
movq %r14, %r15
movq 64(%rsp), %r14 # 8-byte Reload
jle .LBB3_47
# %bb.43: # %.lr.ph101.preheader
movl %eax, %edx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_44: # %.lr.ph101
# =>This Inner Loop Header: Depth=1
movss (%r12,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r15,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB3_45
jp .LBB3_45
# %bb.46: # in Loop: Header=BB3_44 Depth=1
incq %rax
cmpq %rax, %rdx
jne .LBB3_44
jmp .LBB3_47
.LBB3_45:
# kill: def $eax killed $eax killed $rax
cltd
idivl %ecx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.10, %edi
movl %eax, %esi
movb $2, %al
callq printf
.LBB3_47: # %.loopexit
movl numCColumns(%rip), %eax
movl %eax, %esi
shrl $31, %esi
addl %eax, %esi
sarl %esi
incl %esi
imull %esi, %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $.L.str.12, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type numARows,@object # @numARows
.bss
.globl numARows
.p2align 2, 0x0
numARows:
.long 0 # 0x0
.size numARows, 4
.type numAColumns,@object # @numAColumns
.globl numAColumns
.p2align 2, 0x0
numAColumns:
.long 0 # 0x0
.size numAColumns, 4
.type numBRows,@object # @numBRows
.globl numBRows
.p2align 2, 0x0
numBRows:
.long 0 # 0x0
.size numBRows, 4
.type numBColumns,@object # @numBColumns
.globl numBColumns
.p2align 2, 0x0
numBColumns:
.long 0 # 0x0
.size numBColumns, 4
.type numCRows,@object # @numCRows
.globl numCRows
.p2align 2, 0x0
numCRows:
.long 0 # 0x0
.size numCRows, 4
.type numCColumns,@object # @numCColumns
.globl numCColumns
.p2align 2, 0x0
numCColumns:
.long 0 # 0x0
.size numCColumns, 4
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@object # @_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 3, 0x0
_Z20matrixMultiplySharedPfS_S_iiiiii:
.quad _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.size _Z20matrixMultiplySharedPfS_S_iiiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nEnter Rows and Columns of A:"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nEnter Rows and Columns of B:"
.size .L.str.4, 30
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n"
.size .L.str.10, 65
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\nNumber of Blocks Created:%d \n"
.size .L.str.11, 31
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\nNumber of Threads Per Block: %d \n"
.size .L.str.12, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20matrixMultiplySharedPfS_S_iiiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nMatrix A Values:"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nMatrix B Values:"
.size .Lstr.1, 19
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nMatrix C From Device"
.size .Lstr.2, 22
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nMatrix C From Host"
.size .Lstr.3, 20
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n"
.size .Lstr.4, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym numARows
.addrsig_sym numAColumns
.addrsig_sym numBRows
.addrsig_sym numBColumns
.addrsig_sym _Z20matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20matrixMultiplySharedPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ISETP.LE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f03270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e680000002100 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000ee20000002500 */
/*0080*/ IMAD.SHL.U32 R3, R0, 0x8, RZ ; /* 0x0000000800037824 */
/* 0x001fca00078e00ff */
/*0090*/ LEA R3, R2, R3, 0x2 ; /* 0x0000000302037211 */
/* 0x002fe200078e10ff */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x004fc800078e0200 */
/*00b0*/ STS [R3], RZ ; /* 0x000000ff03007388 */
/* 0x0001e20000000800 */
/*00c0*/ IMAD R6, R7, c[0x0][0x0], R2 ; /* 0x0000000007067a24 */
/* 0x008fc600078e0202 */
/*00d0*/ STS [R3+0x10], RZ ; /* 0x000010ff03007388 */
/* 0x0001e20000000800 */
/*00e0*/ @!P0 BRA 0xab0 ; /* 0x000009c000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff087624 */
/* 0x000fe200078e00ff */
/*0100*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0110*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fc600078e00ff */
/*0120*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0130*/ LEA.HI R4, R4, R4, RZ, 0x1 ; /* 0x0000000404047211 */
/* 0x000fc800078f08ff */
/*0140*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011404 */
/*0150*/ IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff047217 */
/* 0x000fc80007800200 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R4.reuse, 0x3, PT ; /* 0x000000030400780c */
/* 0x040fe40003f06070 */
/*0170*/ IADD3 R7, R4, 0x1, RZ ; /* 0x0000000104077810 */
/* 0x000fc80007ffe0ff */
/*0180*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fc800078ec0ff */
/*0190*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f25270 */
/*01a0*/ @!P0 BRA 0x880 ; /* 0x000006d000008947 */
/* 0x000ff40003800000 */
/*01b0*/ IMAD R21, R5.reuse, c[0x0][0x17c], R2 ; /* 0x00005f0005157a24 */
/* 0x040fe200078e0202 */
/*01c0*/ IADD3 R11, R0.reuse, 0x6, RZ ; /* 0x00000006000b7810 */
/* 0x040fe20007ffe0ff */
/*01d0*/ IMAD R8, R5.reuse, R8, 0x2 ; /* 0x0000000205087424 */
/* 0x040fe200078e0208 */
/*01e0*/ IADD3 R23, R0.reuse, 0x4, RZ ; /* 0x0000000400177810 */
/* 0x040fe20007ffe0ff */
/*01f0*/ IMAD R22, R0.reuse, c[0x0][0x184], R6 ; /* 0x0000610000167a24 */
/* 0x040fe200078e0206 */
/*0200*/ IADD3 R13, R0, 0x2, RZ ; /* 0x00000002000d7810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R10, -R4, -0x1, R7 ; /* 0xffffffff040a7810 */
/* 0x000fe20007ffe107 */
/*0230*/ IMAD.MOV.U32 R20, RZ, RZ, R2 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0002 */
/*0240*/ ISETP.GE.AND P2, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f46270 */
/*0250*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe200078e00ff */
/*0260*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD R11, R11, c[0x0][0x184], R6.reuse ; /* 0x000061000b0b7a24 */
/* 0x100fe200078e0206 */
/*0280*/ IADD3 R21, R21, 0x6, RZ ; /* 0x0000000615157810 */
/* 0x000fe20007ffe0ff */
/*0290*/ IMAD R23, R23, c[0x0][0x184], R6 ; /* 0x0000610017177a24 */
/* 0x000fc400078e0206 */
/*02a0*/ IMAD R24, R13, c[0x0][0x184], R6 ; /* 0x000061000d187a24 */
/* 0x000fe400078e0206 */
/*02b0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x184], PT ; /* 0x0000610006007a0c */
/* 0x000fe20003f06270 */
/*02c0*/ HFMA2.MMA R16, -RZ, RZ, 0, 0 ; /* 0x00000000ff107435 */
/* 0x000fe200000001ff */
/*02d0*/ ISETP.GE.U32.OR P3, PT, R20, c[0x0][0x17c], P2 ; /* 0x00005f0014007a0c */
/* 0x000fe20001766470 */
/*02e0*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*02f0*/ ISETP.GE.U32.OR P4, PT, R4, c[0x0][0x180], P0 ; /* 0x0000600004007a0c */
/* 0x000fd60000786470 */
/*0300*/ @!P3 MOV R15, 0x4 ; /* 0x00000004000fb802 */
/* 0x000fe20000000f00 */
/*0310*/ @!P3 IMAD R14, R5, c[0x0][0x17c], R20 ; /* 0x00005f00050eba24 */
/* 0x000fe400078e0214 */
/*0320*/ @!P4 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0dc424 */
/* 0x000fe400078e00ff */
/*0330*/ @!P3 IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0eb625 */
/* 0x000fc800078e000f */
/*0340*/ @!P4 IMAD.WIDE.U32 R12, R22, R13, c[0x0][0x168] ; /* 0x00005a00160cc625 */
/* 0x000fe200078e000d */
/*0350*/ @!P3 LDG.E R28, [R14.64] ; /* 0x000000040e1cb981 */
/* 0x000ea8000c1e1900 */
/*0360*/ @!P4 LDG.E R16, [R12.64] ; /* 0x000000040c10c981 */
/* 0x0002e2000c1e1900 */
/*0370*/ IADD3 R17, R20, 0x2, RZ ; /* 0x0000000214117810 */
/* 0x000fe20007ffe0ff */
/*0380*/ CS2R R26, SRZ ; /* 0x00000000001a7805 */
/* 0x000fc6000001ff00 */
/*0390*/ ISETP.GE.U32.OR P3, PT, R17, c[0x0][0x17c], P2 ; /* 0x00005f0011007a0c */
/* 0x000fe40001766470 */
/*03a0*/ IADD3 R17, R4, 0x2, RZ ; /* 0x0000000204117810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ ISETP.GE.U32.OR P4, PT, R17, c[0x0][0x180], P0 ; /* 0x0000600011007a0c */
/* 0x000fce0000786470 */
/*03c0*/ @!P3 IMAD.IADD R18, R8, 0x1, R20 ; /* 0x000000010812b824 */
/* 0x000fe400078e0214 */
/*03d0*/ @!P3 IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff13b424 */
/* 0x000fc800078e00ff */
/*03e0*/ @!P4 MOV R17, 0x4 ; /* 0x000000040011c802 */
/* 0x000fe20000000f00 */
/*03f0*/ @!P3 IMAD.WIDE.U32 R18, R18, R19, c[0x0][0x160] ; /* 0x000058001212b625 */
/* 0x000fc800078e0013 */
/*0400*/ @!P4 IMAD.WIDE.U32 R12, R24, R17, c[0x0][0x168] ; /* 0x00005a00180cc625 */
/* 0x002fe200078e0011 */
/*0410*/ STS [R3], R28 ; /* 0x0000001c03007388 */
/* 0x004fe80000000800 */
/*0420*/ STS [R3+0x10], R16 ; /* 0x0000101003007388 */
/* 0x0083e80000000800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ @!P3 LDG.E R26, [R18.64] ; /* 0x00000004121ab981 */
/* 0x000ea8000c1e1900 */
/*0450*/ @!P4 LDG.E R27, [R12.64] ; /* 0x000000040c1bc981 */
/* 0x000722000c1e1900 */
/*0460*/ IADD3 R14, R20, 0x4, RZ ; /* 0x00000004140e7810 */
/* 0x000fc60007ffe0ff */
/*0470*/ LDS R28, [R2.X4+0x18] ; /* 0x00001800021c7984 */
/* 0x000fe20000004800 */
/*0480*/ ISETP.GE.U32.OR P3, PT, R14, c[0x0][0x17c], P2 ; /* 0x00005f000e007a0c */
/* 0x000fc60001766470 */
/*0490*/ LDS.64 R14, [R0.X8] ; /* 0x00000000000e7984 */
/* 0x000fe80000008a00 */
/*04a0*/ LDS R12, [R2.X4+0x10] ; /* 0x00001000020c7984 */
/* 0x008eec0000004800 */
/*04b0*/ @!P3 IADD3 R17, R21, -0x2, RZ ; /* 0xfffffffe1511b810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ @!P3 IMAD.MOV.U32 R29, RZ, RZ, 0x4 ; /* 0x00000004ff1db424 */
/* 0x000fc800078e00ff */
/*04d0*/ @!P3 IMAD.WIDE.U32 R16, R17, R29, c[0x0][0x160] ; /* 0x000058001110b625 */
/* 0x002fe200078e001d */
/*04e0*/ HFMA2.MMA R29, -RZ, RZ, 0, 0 ; /* 0x00000000ff1d7435 */
/* 0x000fe200000001ff */
/*04f0*/ IADD3 R13, R4, 0x4, RZ ; /* 0x00000004040d7810 */
/* 0x000fe20007ffe0ff */
/*0500*/ STS [R3], R26 ; /* 0x0000001a03007388 */
/* 0x004fe80000000800 */
/*0510*/ STS [R3+0x10], R27 ; /* 0x0000101b03007388 */
/* 0x0107e80000000800 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ @!P3 LDG.E R29, [R16.64] ; /* 0x00000004101db981 */
/* 0x0002a2000c1e1900 */
/*0540*/ ISETP.GE.U32.OR P3, PT, R13, c[0x0][0x180], P0 ; /* 0x000060000d007a0c */
/* 0x000fe20000766470 */
/*0550*/ FFMA R27, R12, R14, R25 ; /* 0x0000000e0c1b7223 */
/* 0x008fc40000000019 */
/*0560*/ LDS R14, [R2.X4+0x10] ; /* 0x00001000020e7984 */
/* 0x000fe80000004800 */
/*0570*/ LDS R26, [R2.X4+0x18] ; /* 0x00001800021a7984 */
/* 0x000fe20000004800 */
/*0580*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x002fc60000000f00 */
/*0590*/ LDS.64 R12, [R0.X8] ; /* 0x00000000000c7984 */
/* 0x000e640000008a00 */
/*05a0*/ @!P3 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff12b424 */
/* 0x000fc800078e00ff */
/*05b0*/ @!P3 IMAD.WIDE.U32 R18, R23, R18, c[0x0][0x168] ; /* 0x00005a001712b625 */
/* 0x000fca00078e0012 */
/*05c0*/ @!P3 LDG.E R16, [R18.64] ; /* 0x000000041210b981 */
/* 0x000722000c1e1900 */
/*05d0*/ IADD3 R17, R20, 0x6, RZ ; /* 0x0000000614117810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ ISETP.GE.U32.OR P3, PT, R17, c[0x0][0x17c], P2 ; /* 0x00005f0011007a0c */
/* 0x000fe20001766470 */
/*05f0*/ HFMA2.MMA R25, -RZ, RZ, 0, 0 ; /* 0x00000000ff197435 */
/* 0x000fd800000001ff */
/*0600*/ @!P3 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff11b424 */
/* 0x000fe200078e00ff */
/*0610*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x008fe20000000f00 */
/*0620*/ STS [R3], R29 ; /* 0x0000001d03007388 */
/* 0x0045e40000000800 */
/*0630*/ IADD3 R29, R4, 0x6, RZ ; /* 0x00000006041d7810 */
/* 0x004fc80007ffe0ff */
/*0640*/ ISETP.GE.U32.OR P0, PT, R29, c[0x0][0x180], P0 ; /* 0x000060001d007a0c */
/* 0x000fe20000706470 */
/*0650*/ STS [R3+0x10], R16 ; /* 0x0000101003007388 */
/* 0x0105d80000000800 */
/*0660*/ @!P0 IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff138424 */
/* 0x000fe400078e00ff */
/*0670*/ @!P3 IMAD.WIDE.U32 R16, R21, R17, c[0x0][0x160] ; /* 0x000058001510b625 */
/* 0x004fe200078e0011 */
/*0680*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0690*/ @!P3 LDG.E R25, [R16.64] ; /* 0x000000041019b981 */
/* 0x0004e4000c1e1900 */
/*06a0*/ @!P0 IMAD.WIDE.U32 R16, R11, R19, c[0x0][0x168] ; /* 0x00005a000b108625 */
/* 0x004fca00078e0013 */
/*06b0*/ @!P0 LDG.E R18, [R16.64] ; /* 0x0000000410128981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ FFMA R15, R28, R15, R27 ; /* 0x0000000f1c0f7223 */
/* 0x000fc6000000001b */
/*06d0*/ LDS R27, [R2.X4+0x10] ; /* 0x00001000021b7984 */
/* 0x000fe20000004800 */
/*06e0*/ FFMA R28, R14, R12, R15 ; /* 0x0000000c0e1c7223 */
/* 0x002fc6000000000f */
/*06f0*/ LDS R12, [R2.X4+0x18] ; /* 0x00001800020c7984 */
/* 0x000fe80000004800 */
/*0700*/ LDS.64 R14, [R0.X8] ; /* 0x00000000000e7984 */
/* 0x000e620000008a00 */
/*0710*/ FFMA R13, R26, R13, R28 ; /* 0x0000000d1a0d7223 */
/* 0x000fe2000000001c */
/*0720*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0730*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fc40007ffe0ff */
/*0750*/ IADD3 R21, R21, 0x8, RZ ; /* 0x0000000815157810 */
/* 0x000fe20007ffe0ff */
/*0760*/ FFMA R14, R27, R14, R13 ; /* 0x0000000e1b0e7223 */
/* 0x002fc8000000000d */
/*0770*/ FFMA R14, R12, R15, R14 ; /* 0x0000000f0c0e7223 */
/* 0x000fe4000000000e */
/*0780*/ IMAD.IADD R12, R10, 0x1, R9 ; /* 0x000000010a0c7824 */
/* 0x000fca00078e0209 */
/*0790*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*07a0*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fd400000001ff */
/*07b0*/ IMAD R11, R13.reuse, c[0x0][0x184], R11 ; /* 0x000061000d0b7a24 */
/* 0x040fe400078e020b */
/*07c0*/ IMAD R23, R13.reuse, c[0x0][0x184], R23 ; /* 0x000061000d177a24 */
/* 0x040fe400078e0217 */
/*07d0*/ IMAD R24, R13.reuse, c[0x0][0x184], R24 ; /* 0x000061000d187a24 */
/* 0x040fe400078e0218 */
/*07e0*/ IMAD R22, R13, c[0x0][0x184], R22 ; /* 0x000061000d167a24 */
/* 0x000fe200078e0216 */
/*07f0*/ STS [R3], R25 ; /* 0x0000001903007388 */
/* 0x008fe80000000800 */
/*0800*/ STS [R3+0x10], R18 ; /* 0x0000101203007388 */
/* 0x004fe80000000800 */
/*0810*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0820*/ LDS R29, [R2.X4+0x10] ; /* 0x00001000021d7984 */
/* 0x000fe80000004800 */
/*0830*/ LDS.64 R18, [R0.X8] ; /* 0x0000000000127984 */
/* 0x000e680000008a00 */
/*0840*/ LDS R26, [R2.X4+0x18] ; /* 0x00001800021a7984 */
/* 0x000ea20000004800 */
/*0850*/ FFMA R18, R29, R18, R14 ; /* 0x000000121d127223 */
/* 0x002fc8000000000e */
/*0860*/ FFMA R25, R26, R19, R18 ; /* 0x000000131a197223 */
/* 0x004fe20000000012 */
/*0870*/ @P0 BRA 0x2b0 ; /* 0xfffffa3000000947 */
/* 0x000fea000383ffff */
/*0880*/ @!P1 BRA 0xab0 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD R4, R5, c[0x0][0x17c], R2 ; /* 0x00005f0005047a24 */
/* 0x000fe200078e0202 */
/*08a0*/ IADD3 R16, -R7, RZ, RZ ; /* 0x000000ff07107210 */
/* 0x000fe20007ffe1ff */
/*08b0*/ IMAD R15, R9.reuse, 0x2, R0 ; /* 0x00000002090f7824 */
/* 0x040fe200078e0200 */
/*08c0*/ LEA R14, R9.reuse, R2, 0x1 ; /* 0x00000002090e7211 */
/* 0x040fe200078e08ff */
/*08d0*/ IMAD R7, R9, 0x2, R4 ; /* 0x0000000209077824 */
/* 0x000fe400078e0204 */
/*08e0*/ IMAD R4, R15, c[0x0][0x184], R6 ; /* 0x000061000f047a24 */
/* 0x000fe400078e0206 */
/*08f0*/ ISETP.GE.U32.AND P1, PT, R15, c[0x0][0x180], PT ; /* 0x000060000f007a0c */
/* 0x000fe20003f26070 */
/*0900*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*0910*/ ISETP.GE.U32.AND P0, PT, R14, c[0x0][0x17c], PT ; /* 0x00005f000e007a0c */
/* 0x000fe20003f06070 */
/*0920*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0930*/ ISETP.GE.OR P1, PT, R6, c[0x0][0x184], P1 ; /* 0x0000610006007a0c */
/* 0x000fc40000f26670 */
/*0940*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fd60000706670 */
/*0950*/ @!P1 MOV R11, 0x4 ; /* 0x00000004000b9802 */
/* 0x000fe40000000f00 */
/*0960*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff088424 */
/* 0x000fc600078e00ff */
/*0970*/ @!P1 IMAD.WIDE.U32 R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a9625 */
/* 0x000fc800078e000b */
/*0980*/ @!P0 IMAD.WIDE.U32 R8, R7, R8, c[0x0][0x160] ; /* 0x0000580007088625 */
/* 0x000fe200078e0008 */
/*0990*/ @!P1 LDG.E R18, [R10.64] ; /* 0x000000040a129981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ @!P0 LDG.E R20, [R8.64] ; /* 0x0000000408148981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fc80007ffe0ff */
/*09c0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*09d0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x2 ; /* 0x00000002ff157424 */
/* 0x000fe200078e00ff */
/*09e0*/ IADD3 R15, R15, 0x2, RZ ; /* 0x000000020f0f7810 */
/* 0x000fe40007ffe0ff */
/*09f0*/ IADD3 R14, R14, 0x2, RZ ; /* 0x000000020e0e7810 */
/* 0x000fe20007ffe0ff */
/*0a00*/ IMAD R4, R21, c[0x0][0x184], R4 ; /* 0x0000610015047a24 */
/* 0x000fe200078e0204 */
/*0a10*/ IADD3 R7, R7, 0x2, RZ ; /* 0x0000000207077810 */
/* 0x000fe20007ffe0ff */
/*0a20*/ STS [R3+0x10], R18 ; /* 0x0000101203007388 */
/* 0x004fe80000000800 */
/*0a30*/ STS [R3], R20 ; /* 0x0000001403007388 */
/* 0x008fe80000000800 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a50*/ LDS R17, [R2.X4+0x10] ; /* 0x0000100002117984 */
/* 0x000fe80000004800 */
/*0a60*/ LDS.64 R12, [R0.X8] ; /* 0x00000000000c7984 */
/* 0x000e680000008a00 */
/*0a70*/ LDS R19, [R2.X4+0x18] ; /* 0x0000180002137984 */
/* 0x000ea20000004800 */
/*0a80*/ FFMA R12, R17, R12, R25 ; /* 0x0000000c110c7223 */
/* 0x002fc80000000019 */
/*0a90*/ FFMA R25, R19, R13, R12 ; /* 0x0000000d13197223 */
/* 0x004fe2000000000c */
/*0aa0*/ @P0 BRA 0x8f0 ; /* 0xfffffe4000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x18c], PT ; /* 0x0000630006007a0c */
/* 0x000fc80003f06270 */
/*0ac0*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x188], P0 ; /* 0x0000620005007a0c */
/* 0x000fda0000706670 */
/*0ad0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fe20000000f00 */
/*0af0*/ IMAD R2, R5, c[0x0][0x18c], R6 ; /* 0x0000630005027a24 */
/* 0x000fc800078e0206 */
/*0b00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0b10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*0b20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20matrixMultiplySharedPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 8
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@function
_Z20matrixMultiplySharedPfS_S_iiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s10, s[0:1], 0x1c
v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 2, v3
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_lshl_add_u32 v2, v4, 3, v5
v_mov_b32_e32 v5, 0
s_cmp_lt_i32 s10, 0
ds_store_2addr_b32 v2, v5, v5 offset1:4
s_cbranch_scc1 .LBB0_14
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_add_i32 s3, s10, -1
v_mad_u64_u32 v[5:6], null, v0, s10, v[3:4]
s_lshr_b32 s12, s3, 31
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v9, 16, v2
s_add_i32 s3, s3, s12
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v10, 3, v4
v_lshl_add_u32 v11, v3, 2, 16
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_max_i32 s12, s3, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s9, v1
.LBB0_2:
v_mov_b32_e32 v6, 0
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_6
s_lshl_b32 s15, s11, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s15, v3
v_cmp_gt_u32_e64 s3, s10, v6
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s14, s3
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v6, s15, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[6:7]
v_add_co_u32 v12, s3, s4, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s3, s5, v13, s3
global_load_b32 v6, v[12:13], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v12, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v6
s_and_saveexec_b32 s13, s2
s_cbranch_execz .LBB0_10
v_lshl_add_u32 v6, s11, 1, v4
v_mov_b32_e32 v12, 0
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 s8, v6
s_cbranch_execz .LBB0_9
v_mad_u64_u32 v[12:13], null, v6, s9, v[1:2]
v_mov_b32_e32 v13, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, s3, s6, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s3, s7, v13, s3
global_load_b32 v12, v[12:13], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v6, v11
s_mov_b32 s3, 0
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v12, s3, v10
s_add_i32 s3, s3, 4
ds_load_b32 v13, v6
ds_load_b32 v12, v12
v_add_nc_u32_e32 v6, 8, v6
s_cmp_lg_u32 s3, 4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v8, v12, v13
s_cbranch_scc0 .LBB0_11
s_add_i32 s3, s11, 1
s_cmp_eq_u32 s11, s12
s_cbranch_scc1 .LBB0_14
s_mov_b32 s11, s3
s_branch .LBB0_2
.LBB0_14:
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v8, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20matrixMultiplySharedPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z20matrixMultiplySharedPfS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20matrixMultiplySharedPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20matrixMultiplySharedPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ceb69_00000000-6_mat_mul_shared_memory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.text
.globl _Z8printMatiiPf
.type _Z8printMatiiPf, @function
_Z8printMatiiPf:
.LFB2057:
.cfi_startproc
endbr64
imull %esi, %edi
testl %edi, %edi
jle .L9
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %ebp
movq %rdx, %r13
movslq %edi, %r12
movl $0, %ebx
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L6
.L5:
addq $1, %rbx
cmpq %r12, %rbx
je .L12
.L6:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .L5
testl %ebx, %ebx
je .L5
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L12:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z8printMatiiPf, .-_Z8printMatiiPf
.globl _Z17matMultiplyOnHostPfS_S_iiiiii
.type _Z17matMultiplyOnHostPfS_S_iiiiii, @function
_Z17matMultiplyOnHostPfS_S_iiiiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -8(%rsp)
movl %ecx, -12(%rsp)
movl 72(%rsp), %ebx
testl %ecx, %ecx
jle .L13
movq %rdi, %rbp
movq %rdx, %r15
movl %r8d, %r11d
movslq 56(%rsp), %rdi
salq $2, %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebx, %r14
movq %r15, %r8
movq %r14, %rsi
jmp .L15
.L19:
movslq %ecx, %rax
leaq (%r8,%rax,4), %r10
movq -8(%rsp), %r14
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r15
addq %rsi, %rax
leaq 0(%rbp,%rax,4), %r9
movl $0, %r12d
movl %edx, -20(%rsp)
movl %ecx, -16(%rsp)
.L18:
movq %r10, %rcx
movl $0x00000000, (%r10)
testl %ebx, %ebx
jle .L16
movq %r14, %rdx
movq %r15, %rax
.L17:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L17
.L16:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L18
movl -20(%rsp), %edx
movl -16(%rsp), %ecx
.L20:
addl $1, %edx
addl %ebx, %ecx
addl %r11d, %r13d
cmpl %edx, -12(%rsp)
je .L13
.L15:
testl %r11d, %r11d
jg .L19
jmp .L20
.L13:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z17matMultiplyOnHostPfS_S_iiiiii, .-_Z17matMultiplyOnHostPfS_S_iiiiii
.globl _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.type _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, .-_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.type _Z20matrixMultiplySharedPfS_S_iiiiii, @function
_Z20matrixMultiplySharedPfS_S_iiiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .-_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata.str1.1
.LC3:
.string "\nEnter Rows and Columns of A:"
.LC4:
.string "%d %d"
.LC5:
.string "\nEnter Rows and Columns of B:"
.LC6:
.string "\nMatrix A Values:\n"
.LC7:
.string "\n\nMatrix B Values:\n"
.LC8:
.string "\nMatrix C From Device\n"
.LC9:
.string "\nMatrix C From Host\n"
.LC10:
.string "\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n"
.align 8
.LC12:
.string "\nNumber of Blocks Created:%d \n"
.align 8
.LC13:
.string "\nNumber of Threads Per Block: %d \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq numAColumns(%rip), %rdx
leaq numARows(%rip), %rsi
leaq .LC4(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq numBColumns(%rip), %rdx
leaq numBRows(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl numARows(%rip), %ebx
movl numAColumns(%rip), %r13d
movslq %ebx, %rdi
movslq %r13d, %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movslq numBRows(%rip), %rdi
movslq numBColumns(%rip), %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
imull %r13d, %ebx
testl %ebx, %ebx
jle .L33
movl $0, %ebx
.L34:
call rand@PLT
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
leal (%rdx,%rcx,2), %edx
subl %edx, %eax
addl $10, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
movl numARows(%rip), %eax
imull numAColumns(%rip), %eax
cmpl %ebx, %eax
jg .L34
.L33:
movl numBRows(%rip), %eax
imull numBColumns(%rip), %eax
testl %eax, %eax
jle .L35
movl $0, %ebx
.L36:
call rand@PLT
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
leal (%rdx,%rcx,2), %edx
subl %edx, %eax
addl $10, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
movl numBRows(%rip), %eax
imull numBColumns(%rip), %eax
cmpl %ebx, %eax
jg .L36
.L35:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
movl numAColumns(%rip), %esi
movl numARows(%rip), %edi
call _Z8printMatiiPf
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movl numBColumns(%rip), %esi
movl numBRows(%rip), %edi
call _Z8printMatiiPf
movl numARows(%rip), %r14d
movl %r14d, numCRows(%rip)
movl numBColumns(%rip), %ebx
movl %ebx, numCColumns(%rip)
movslq %r14d, %r14
movslq %ebx, %rbx
imulq %r14, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movslq numAColumns(%rip), %rsi
imulq %r14, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq numBRows(%rip), %rsi
movslq numBColumns(%rip), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq numCRows(%rip), %rsi
movslq numCColumns(%rip), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq numARows(%rip), %rdx
movslq numAColumns(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq numBRows(%rip), %rdx
movslq numBColumns(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl numCRows(%rip), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl $1, %eax
movl numCColumns(%rip), %ecx
movl %ecx, %edx
shrl $31, %edx
addl %ecx, %edx
sarl %edx
addl $1, %edx
movl %edx, 32(%rsp)
movl %eax, 36(%rsp)
movl $2, 44(%rsp)
movl $2, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L37:
call cudaPeekAtLastError@PLT
call cudaDeviceSynchronize@PLT
movslq numCRows(%rip), %rdx
movslq numCColumns(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
movl numCColumns(%rip), %esi
movl numCRows(%rip), %edi
call _Z8printMatiiPf
subq $8, %rsp
.cfi_def_cfa_offset 120
movl numCColumns(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 128
movl numCRows(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 136
movl numBColumns(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl numBRows(%rip), %r9d
movl numAColumns(%rip), %r8d
movl numARows(%rip), %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z17matMultiplyOnHostPfS_S_iiiiii
addq $32, %rsp
.cfi_def_cfa_offset 112
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
movl numCColumns(%rip), %esi
movl numCRows(%rip), %edi
call _Z8printMatiiPf
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl numCColumns(%rip), %esi
movl %esi, %edx
imull numCRows(%rip), %edx
testl %edx, %edx
jle .L38
movslq %edx, %rdx
movl $0, %eax
.L41:
movss (%rbx,%rax,4), %xmm0
movss 0(%r13,%rax,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L43
jne .L43
addq $1, %rax
cmpq %rax, %rdx
jne .L41
jmp .L38
.L48:
subq $8, %rsp
.cfi_def_cfa_offset 120
movl numCColumns(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 128
movl numCRows(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 136
movl numBColumns(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl numBRows(%rip), %r9d
movl numAColumns(%rip), %r8d
movl numARows(%rip), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
addq $32, %rsp
.cfi_def_cfa_offset 112
jmp .L37
.L43:
cvtss2sd %xmm0, %xmm0
cltd
idivl %esi
movl %edx, %ecx
cvtss2sd %xmm1, %xmm1
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L38:
movl numCColumns(%rip), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
addl $1, %edx
imull %edx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z20matrixMultiplySharedPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl numCColumns
.bss
.align 4
.type numCColumns, @object
.size numCColumns, 4
numCColumns:
.zero 4
.globl numCRows
.align 4
.type numCRows, @object
.size numCRows, 4
numCRows:
.zero 4
.globl numBColumns
.align 4
.type numBColumns, @object
.size numBColumns, 4
numBColumns:
.zero 4
.globl numBRows
.align 4
.type numBRows, @object
.size numBRows, 4
numBRows:
.zero 4
.globl numAColumns
.align 4
.type numAColumns, @object
.size numAColumns, 4
numAColumns:
.zero 4
.globl numARows
.align 4
.type numARows, @object
.size numARows, 4
numARows:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mul_shared_memory.hip"
.globl _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii # -- Begin function _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.p2align 4, 0x90
.type _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii,@function
_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii: # @_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_endproc
# -- End function
.globl _Z8printMatiiPf # -- Begin function _Z8printMatiiPf
.p2align 4, 0x90
.type _Z8printMatiiPf,@function
_Z8printMatiiPf: # @_Z8printMatiiPf
.cfi_startproc
# %bb.0:
imull %esi, %edi
testl %edi, %edi
jle .LBB1_7
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, %ebp
movl %edi, %r15d
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_2 Depth=1
incq %r14
cmpq %r14, %r15
je .LBB1_6
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r14d, %eax
cltd
idivl %ebp
testq %r14, %r14
je .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
testl %edx, %edx
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_5
.LBB1_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_7: # %._crit_edge
retq
.Lfunc_end1:
.size _Z8printMatiiPf, .Lfunc_end1-_Z8printMatiiPf
.cfi_endproc
# -- End function
.globl _Z17matMultiplyOnHostPfS_S_iiiiii # -- Begin function _Z17matMultiplyOnHostPfS_S_iiiiii
.p2align 4, 0x90
.type _Z17matMultiplyOnHostPfS_S_iiiiii,@function
_Z17matMultiplyOnHostPfS_S_iiiiii: # @_Z17matMultiplyOnHostPfS_S_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB2_9
# %bb.1: # %.preheader.lr.ph
movl 72(%rsp), %eax
movslq 56(%rsp), %r9
movslq %eax, %r10
movslq %r8d, %r11
movl %ecx, %ecx
movl %r11d, %ebx
movl %r10d, %r14d
shlq $2, %r11
shlq $2, %r9
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r15
addq %r11, %rdi
cmpq %rcx, %r15
je .LBB2_9
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
testl %r8d, %r8d
jle .LBB2_8
# %bb.3: # %.lr.ph29
# in Loop: Header=BB2_2 Depth=1
movq %r15, %rdx
imulq %r10, %rdx
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r12
movq -16(%rsp), %rsi # 8-byte Reload
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
incq %rbp
addq $4, %rsi
cmpq %rbx, %rbp
je .LBB2_8
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
movl $0, (%r12,%rbp,4)
testl %eax, %eax
jle .LBB2_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB2_4 Depth=2
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rsi, %r13
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r13), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rdx
addq %r9, %r13
cmpq %rdx, %r14
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z17matMultiplyOnHostPfS_S_iiiiii, .Lfunc_end2-_Z17matMultiplyOnHostPfS_S_iiiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $numARows, %esi
movl $numAColumns, %edx
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $numBRows, %esi
movl $numBColumns, %edx
xorl %eax, %eax
callq __isoc23_scanf
movslq numARows(%rip), %rax
movslq numAColumns(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r13
movslq numBRows(%rip), %rax
movslq numBColumns(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
movl numAColumns(%rip), %eax
imull numARows(%rip), %eax
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
negl %ecx
addl %ecx, %eax
addl $10, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%rbx,4)
incq %rbx
movslq numARows(%rip), %rax
movslq numAColumns(%rip), %rcx
imulq %rax, %rcx
cmpq %rcx, %rbx
jl .LBB3_2
.LBB3_3: # %.preheader
movl numBColumns(%rip), %eax
imull numBRows(%rip), %eax
testl %eax, %eax
jle .LBB3_6
# %bb.4: # %.lr.ph95.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_5: # %.lr.ph95
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
negl %ecx
addl %ecx, %eax
addl $10, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rbx,4)
incq %rbx
movslq numBRows(%rip), %rax
movslq numBColumns(%rip), %rcx
imulq %rax, %rcx
cmpq %rcx, %rbx
jl .LBB3_5
.LBB3_6: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
movl numAColumns(%rip), %ebp
movl numARows(%rip), %eax
imull %ebp, %eax
testl %eax, %eax
jle .LBB3_12
# %bb.7: # %.lr.ph.preheader.i
movl %eax, %r12d
xorl %r15d, %r15d
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_8 Depth=1
incq %r15
cmpq %r15, %r12
je .LBB3_12
.LBB3_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r13,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r15d, %eax
cltd
idivl %ebp
testq %r15, %r15
je .LBB3_11
# %bb.9: # %.lr.ph.i
# in Loop: Header=BB3_8 Depth=1
testl %edx, %edx
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_8 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_11
.LBB3_12: # %_Z8printMatiiPf.exit
movl $.Lstr.1, %edi
callq puts@PLT
movl numBColumns(%rip), %ebp
movl numBRows(%rip), %eax
imull %ebp, %eax
testl %eax, %eax
jle .LBB3_18
# %bb.13: # %.lr.ph.preheader.i54
movl %eax, %r12d
xorl %r15d, %r15d
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_14 Depth=1
incq %r15
cmpq %r15, %r12
je .LBB3_18
.LBB3_14: # %.lr.ph.i56
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r15d, %eax
cltd
idivl %ebp
testq %r15, %r15
je .LBB3_17
# %bb.15: # %.lr.ph.i56
# in Loop: Header=BB3_14 Depth=1
testl %edx, %edx
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_14 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_17
.LBB3_18: # %_Z8printMatiiPf.exit62
movslq numARows(%rip), %rbx
movl %ebx, numCRows(%rip)
movslq numBColumns(%rip), %r12
movl %r12d, numCColumns(%rip)
shlq $2, %rbx
imulq %rbx, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r12
movslq numAColumns(%rip), %rsi
imulq %rbx, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq numBRows(%rip), %rax
movslq numBColumns(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movslq numCRows(%rip), %rax
movslq numCColumns(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movslq numARows(%rip), %rax
movslq numAColumns(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r13, 56(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq numBRows(%rip), %rax
movslq numBColumns(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, 64(%rsp) # 8-byte Spill
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl numCColumns(%rip), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
incl %ecx
movl numCRows(%rip), %eax
movl %eax, %edi
shrl $31, %edi
addl %eax, %edi
sarl %edi
incl %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl numARows(%rip), %esi
movl numAColumns(%rip), %edi
movl numBRows(%rip), %r8d
movl numBColumns(%rip), %r9d
movl numCRows(%rip), %r10d
movl numCColumns(%rip), %r11d
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %esi, 52(%rsp)
movl %edi, 48(%rsp)
movl %r8d, 44(%rsp)
movl %r9d, 40(%rsp)
movl %r10d, 36(%rsp)
movl %r11d, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 36(%rsp), %rax
movq %rax, 200(%rsp)
leaq 32(%rsp), %rax
movq %rax, 208(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20:
callq hipPeekAtLastError
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movslq numCRows(%rip), %rax
movslq numCColumns(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %r14
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl numCColumns(%rip), %ebp
movl numCRows(%rip), %eax
imull %ebp, %eax
testl %eax, %eax
jle .LBB3_26
# %bb.21: # %.lr.ph.preheader.i63
movl %eax, %ebx
xorl %r13d, %r13d
jmp .LBB3_22
.p2align 4, 0x90
.LBB3_25: # in Loop: Header=BB3_22 Depth=1
incq %r13
cmpq %r13, %rbx
je .LBB3_26
.LBB3_22: # %.lr.ph.i65
# =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r13d, %eax
cltd
idivl %ebp
testq %r13, %r13
je .LBB3_25
# %bb.23: # %.lr.ph.i65
# in Loop: Header=BB3_22 Depth=1
testl %edx, %edx
jne .LBB3_25
# %bb.24: # in Loop: Header=BB3_22 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_25
.LBB3_26: # %_Z8printMatiiPf.exit71
movl numARows(%rip), %eax
testl %eax, %eax
jle .LBB3_36
# %bb.27: # %.preheader.lr.ph.i
movl numCColumns(%rip), %ecx
movl numAColumns(%rip), %edx
movslq numBColumns(%rip), %rsi
movslq %ecx, %rdi
movslq %edx, %r8
shlq $2, %r8
shlq $2, %rsi
xorl %r9d, %r9d
movq 56(%rsp), %r10 # 8-byte Reload
jmp .LBB3_28
.p2align 4, 0x90
.LBB3_35: # %._crit_edge30.i
# in Loop: Header=BB3_28 Depth=1
incq %r9
addq %r8, %r10
cmpq %rax, %r9
je .LBB3_36
.LBB3_28: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_30 Depth 2
# Child Loop BB3_32 Depth 3
testl %edx, %edx
jle .LBB3_35
# %bb.29: # %.lr.ph29.i
# in Loop: Header=BB3_28 Depth=1
movq %r9, %r11
imulq %rdi, %r11
leaq (%r12,%r11,4), %r11
movq 64(%rsp), %r13 # 8-byte Reload
xorl %ebp, %ebp
jmp .LBB3_30
.p2align 4, 0x90
.LBB3_34: # %._crit_edge.i
# in Loop: Header=BB3_30 Depth=2
incq %rbp
addq $4, %r13
cmpq %rdx, %rbp
je .LBB3_35
.LBB3_30: # Parent Loop BB3_28 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_32 Depth 3
movl $0, (%r11,%rbp,4)
testl %ecx, %ecx
jle .LBB3_34
# %bb.31: # %.lr.ph.i72
# in Loop: Header=BB3_30 Depth=2
xorps %xmm0, %xmm0
movq %r13, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_32: # Parent Loop BB3_28 Depth=1
# Parent Loop BB3_30 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r10,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbx), %xmm1
addss %xmm1, %xmm0
incq %r15
addq %rsi, %rbx
cmpq %r15, %rcx
jne .LBB3_32
# %bb.33: # %._crit_edge.i.loopexit
# in Loop: Header=BB3_30 Depth=2
movss %xmm0, (%r11,%rbp,4)
jmp .LBB3_34
.LBB3_36: # %_Z17matMultiplyOnHostPfS_S_iiiiii.exit
movl $.Lstr.3, %edi
callq puts@PLT
movl numCColumns(%rip), %ebp
movl numCRows(%rip), %eax
imull %ebp, %eax
testl %eax, %eax
jle .LBB3_42
# %bb.37: # %.lr.ph.preheader.i78
movl %eax, %ebx
xorl %r13d, %r13d
jmp .LBB3_38
.p2align 4, 0x90
.LBB3_41: # in Loop: Header=BB3_38 Depth=1
incq %r13
cmpq %r13, %rbx
je .LBB3_42
.LBB3_38: # %.lr.ph.i80
# =>This Inner Loop Header: Depth=1
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl %r13d, %eax
cltd
idivl %ebp
testq %r13, %r13
je .LBB3_41
# %bb.39: # %.lr.ph.i80
# in Loop: Header=BB3_38 Depth=1
testl %edx, %edx
jne .LBB3_41
# %bb.40: # in Loop: Header=BB3_38 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_41
.LBB3_42: # %_Z8printMatiiPf.exit86
movl $.Lstr.4, %edi
callq puts@PLT
movl numCColumns(%rip), %ecx
movl numCRows(%rip), %eax
imull %ecx, %eax
testl %eax, %eax
movq 56(%rsp), %rbx # 8-byte Reload
movq %r14, %r15
movq 64(%rsp), %r14 # 8-byte Reload
jle .LBB3_47
# %bb.43: # %.lr.ph101.preheader
movl %eax, %edx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_44: # %.lr.ph101
# =>This Inner Loop Header: Depth=1
movss (%r12,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r15,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB3_45
jp .LBB3_45
# %bb.46: # in Loop: Header=BB3_44 Depth=1
incq %rax
cmpq %rax, %rdx
jne .LBB3_44
jmp .LBB3_47
.LBB3_45:
# kill: def $eax killed $eax killed $rax
cltd
idivl %ecx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.10, %edi
movl %eax, %esi
movb $2, %al
callq printf
.LBB3_47: # %.loopexit
movl numCColumns(%rip), %eax
movl %eax, %esi
shrl $31, %esi
addl %eax, %esi
sarl %esi
incl %esi
imull %esi, %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $.L.str.12, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type numARows,@object # @numARows
.bss
.globl numARows
.p2align 2, 0x0
numARows:
.long 0 # 0x0
.size numARows, 4
.type numAColumns,@object # @numAColumns
.globl numAColumns
.p2align 2, 0x0
numAColumns:
.long 0 # 0x0
.size numAColumns, 4
.type numBRows,@object # @numBRows
.globl numBRows
.p2align 2, 0x0
numBRows:
.long 0 # 0x0
.size numBRows, 4
.type numBColumns,@object # @numBColumns
.globl numBColumns
.p2align 2, 0x0
numBColumns:
.long 0 # 0x0
.size numBColumns, 4
.type numCRows,@object # @numCRows
.globl numCRows
.p2align 2, 0x0
numCRows:
.long 0 # 0x0
.size numCRows, 4
.type numCColumns,@object # @numCColumns
.globl numCColumns
.p2align 2, 0x0
numCColumns:
.long 0 # 0x0
.size numCColumns, 4
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@object # @_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 3, 0x0
_Z20matrixMultiplySharedPfS_S_iiiiii:
.quad _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.size _Z20matrixMultiplySharedPfS_S_iiiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nEnter Rows and Columns of A:"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nEnter Rows and Columns of B:"
.size .L.str.4, 30
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Mismatch at Row = %d Col = %d hostComputed[] = %f --device[] %f\n"
.size .L.str.10, 65
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\nNumber of Blocks Created:%d \n"
.size .L.str.11, 31
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\nNumber of Threads Per Block: %d \n"
.size .L.str.12, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20matrixMultiplySharedPfS_S_iiiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nMatrix A Values:"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nMatrix B Values:"
.size .Lstr.1, 19
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nMatrix C From Device"
.size .Lstr.2, 22
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nMatrix C From Host"
.size .Lstr.3, 20
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n"
.size .Lstr.4, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym numARows
.addrsig_sym numAColumns
.addrsig_sym numBRows
.addrsig_sym numBColumns
.addrsig_sym _Z20matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /***
This script is an example of usign CUDA Thrust library.
***/
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <iostream>
using namespace std;
int main(void)
{
thrust::host_vector<int> v;
v.push_back(1);
v.push_back(2);
v.push_back(3);
v.push_back(4);
for (int i = 0; i < v.size(); i++)
cout << "v[" << i << "] == " << v[i] << endl;
thrust::device_vector<int> v_gpu = v;
v_gpu.push_back(5);
for (int i = 0; i < v_gpu.size(); i++)
std::cout << "v_gpu[" << i << "] == " << v_gpu[i] << std::endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***
This script is an example of usign CUDA Thrust library.
***/
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <iostream>
using namespace std;
int main(void)
{
thrust::host_vector<int> v;
v.push_back(1);
v.push_back(2);
v.push_back(3);
v.push_back(4);
for (int i = 0; i < v.size(); i++)
cout << "v[" << i << "] == " << v[i] << endl;
thrust::device_vector<int> v_gpu = v;
v_gpu.push_back(5);
for (int i = 0; i < v_gpu.size(); i++)
std::cout << "v_gpu[" << i << "] == " << v_gpu[i] << std::endl;
return 0;
} | /***
This script is an example of usign CUDA Thrust library.
***/
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <iostream>
using namespace std;
int main(void)
{
thrust::host_vector<int> v;
v.push_back(1);
v.push_back(2);
v.push_back(3);
v.push_back(4);
for (int i = 0; i < v.size(); i++)
cout << "v[" << i << "] == " << v[i] << endl;
thrust::device_vector<int> v_gpu = v;
v_gpu.push_back(5);
for (int i = 0; i < v_gpu.size(); i++)
std::cout << "v_gpu[" << i << "] == " << v_gpu[i] << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /***
This script is an example of usign CUDA Thrust library.
***/
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <iostream>
using namespace std;
int main(void)
{
thrust::host_vector<int> v;
v.push_back(1);
v.push_back(2);
v.push_back(3);
v.push_back(4);
for (int i = 0; i < v.size(); i++)
cout << "v[" << i << "] == " << v[i] << endl;
thrust::device_vector<int> v_gpu = v;
v_gpu.push_back(5);
for (int i = 0; i < v_gpu.size(); i++)
std::cout << "v_gpu[" << i << "] == " << v_gpu[i] << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB2_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.Lfunc_end2:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end2-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB2_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.Lfunc_end2:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end2-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorImNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_miEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUlmE_NS3_21always_true_predicateEEExLj1EEEvSG_SL_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <cuda_runtime.h>
#include <cstdlib>
#include <sstream>
#include <iomanip>
using namespace std;
//input, filter and output considering maximum dimension possible
double a[1000][1000], h[10][10], c[1000][1000];
/**
* CUDA Kernel Device code
*
* Computes the 2D convolution of input b with filter h and output c
*/
__global__ void
convolution2D(double *a_1, double *h_1, double *c_1, int rows_a, int columns_a, int rows_h, int columns_h)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
double sum;
if((idx < (columns_h+columns_a - 1)) && (idy < (rows_h + rows_a - 1)))
{
sum = 0;
for(int k=0; k< rows_h; k++)
{
for(int j=0; j< columns_h; j++)
{
if ((idy - k) >= 0 && (idx - j) >= 0 && (idy - k) < rows_a && (idx - j) < columns_a)
{
sum += a_1[((idy - k)*columns_a) + (idx - j)] * h_1[k*columns_h + j];
}
}
}
c_1[idy*(columns_a + columns_h - 1) + idx] = sum;
__syncthreads();
}
}
/**
* Host main routine
*/
int main(int argc, char** argv)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
int columns_a, columns_h, rows_a, rows_h, size_a, size_h;
columns_a = columns_h = 0;
size_a = size_h = rows_a = rows_h = 0;
char *ip_file;
string line;
double input;
ip_file = argv[1];
int i, j, k;
ifstream file(ip_file);
if(file.is_open())
{
i=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
a[i][j] = input;
size_a++;
j++;
}
i++;
rows_a++;
}
k=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
h[k][j] = input;
j++;
size_h++;
}
k++;
rows_h++;
}
}
file.close();
columns_a = size_a/rows_a;
columns_h = size_h/rows_h;
int op_size = ((rows_a+rows_h-1)*(columns_a+columns_h-1));
size_t size_ax = size_a*sizeof(double);
size_t size_hx = size_h*sizeof(double);
size_t size_cx = op_size*sizeof(double);
// Allocate the host input vector a
double *h_a;
cudaMallocManaged(&h_a, size_ax);
// Allocate the host input vector h
double *h_h;
cudaMallocManaged(&h_h, size_hx);
// Allocate the host output vector c
double *h_c;
cudaMallocManaged(&h_c, size_cx);
for (int i = 0; i < rows_a; i++)
{
for(int j=0;j< columns_a; j++)
{
h_a[i*columns_a + j] = a[i][j];
}
}
for (int i = 0; i < rows_h; i++)
{
for(int j=0;j< columns_h; j++)
{
h_h[i*columns_h + j] = h[i][j];
}
}
// Launch the CUDA Kernel
dim3 blocksPerGrid(((rows_a + rows_h - 2) / 32) + 1, ((columns_h + columns_a - 2) / 32) + 1, 1);
dim3 threadsPerBlock(32,32,1);
convolution2D<<<blocksPerGrid, threadsPerBlock>>>(h_a, h_h, h_c, rows_a, columns_a, rows_h, columns_h);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch convolution2D kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaDeviceSynchronize();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to synchronize (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/////////////////////////////////////////////////////////////////////////////////////////////////////////
for (int i = 0; i < rows_a + rows_h - 1; i++) {
for (int j = 0; j < columns_a + columns_h - 1; j++)
{
cout << fixed << setprecision(3) << h_c[(i*(columns_h+columns_a-1))+j] << " ";
}
cout << endl;
}
// Free device global memory
err = cudaFree(h_a);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector a (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(h_h);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector h (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(h_c);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector c (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Reset the device and exit
// cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Done\n");
return 0;
} | code for sm_80
Function : _Z13convolution2DPdS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULDC.64 UR8, c[0x0][0x180] ; /* 0x0000600000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, UR7, UR9, URZ ; /* 0x0000000907047290 */
/* 0x000fe4000fffe03f */
/*0060*/ UIADD3 UR5, UR6, UR8, URZ ; /* 0x0000000806057290 */
/* 0x000fe2000fffe03f */
/*0070*/ S2R R21, SR_CTAID.Y ; /* 0x0000000000157919 */
/* 0x000e620000002600 */
/*0080*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0090*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe2000fffe03f */
/*00a0*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00c0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06270 */
/*00d0*/ IMAD R21, R21, c[0x0][0x4], R2 ; /* 0x0000010015157a24 */
/* 0x002fca00078e0202 */
/*00e0*/ ISETP.GE.OR P0, PT, R21, UR5, P0 ; /* 0x0000000515007c0c */
/* 0x000fda0008706670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0120*/ ISETP.LE.AND P0, PT, R2, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x000fc80003f03270 */
/*0130*/ ISETP.GT.OR P0, PT, R2, c[0x0][0x180], !P0 ; /* 0x0000600002007a0c */
/* 0x000fe40004704670 */
/*0140*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fd6000001ff00 */
/*0150*/ @P0 BRA 0x7a0 ; /* 0x0000064000000947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff147624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R2, -R2, c[0x0][0x184], RZ ; /* 0x0000610002027a10 */
/* 0x000fe40007ffe1ff */
/*01a0*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */
/* 0x000fe400078ec0ff */
/*01b0*/ ISETP.GE.U32.AND P3, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f66070 */
/*01c0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*01d0*/ IADD3 R23, -R20, c[0x0][0x184], RZ ; /* 0x0000610014177a10 */
/* 0x000fc40007ffe1ff */
/*01e0*/ IMAD.MOV.U32 R26, RZ, RZ, R22.reuse ; /* 0x000000ffff1a7224 */
/* 0x100fe200078e0016 */
/*01f0*/ ISETP.NE.AND P4, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f85270 */
/*0200*/ IMAD.IADD R24, R21, 0x1, -R22 ; /* 0x0000000115187824 */
/* 0x000fe200078e0a16 */
/*0210*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fc600078e00ff */
/*0230*/ ISETP.GE.AND P5, PT, R22, c[0x0][0x180], PT ; /* 0x0000600016007a0c */
/* 0x000fe20003fa6270 */
/*0240*/ @!P3 BRA 0x4f0 ; /* 0x000002a00000b947 */
/* 0x00ffee0003800000 */
/*0250*/ ISETP.GE.AND P6, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003fc6270 */
/*0260*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R27, RZ, RZ, R23 ; /* 0x000000ffff1b7224 */
/* 0x000fc600078e0017 */
/*0280*/ ISETP.LT.OR P0, PT, R0.reuse, R25, !P6 ; /* 0x000000190000720c */
/* 0x040fe20007701670 */
/*0290*/ IMAD.IADD R5, R0, 0x1, -R25 ; /* 0x0000000100057824 */
/* 0x000fe400078e0a19 */
/*02a0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x000fe200078e00ff */
/*02b0*/ ISETP.GE.OR P0, PT, R24.reuse, c[0x0][0x178], P0 ; /* 0x00005e0018007a0c */
/* 0x040fe20000706670 */
/*02c0*/ IMAD R12, R24, c[0x0][0x17c], R5 ; /* 0x00005f00180c7a24 */
/* 0x000fe400078e0205 */
/*02d0*/ IMAD R16, R26, c[0x0][0x184], R25 ; /* 0x000061001a107a24 */
/* 0x000fe200078e0219 */
/*02e0*/ ISETP.GE.OR P2, PT, R5, c[0x0][0x17c], P0 ; /* 0x00005f0005007a0c */
/* 0x000fe20000746670 */
/*02f0*/ IMAD.WIDE R12, R12, R17, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0211 */
/*0300*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fd000078e0211 */
/*0310*/ @!P2 LDG.E.64 R6, [R12.64] ; /* 0x000000060c06a981 */
/* 0x000ea8000c1e1b00 */
/*0320*/ @!P2 LDG.E.64 R4, [R16.64] ; /* 0x000000061004a981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ ISETP.LE.OR P0, PT, R0.reuse, R25, !P6 ; /* 0x000000190000720c */
/* 0x040fe40007703670 */
/*0340*/ IADD3 R8, R0, -0x1, -R25 ; /* 0xffffffff00087810 */
/* 0x000fe40007ffe819 */
/*0350*/ IADD3 R9, R25, 0x2, RZ ; /* 0x0000000219097810 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.GE.OR P0, PT, R24, c[0x0][0x178], P0 ; /* 0x00005e0018007a0c */
/* 0x000fc40000706670 */
/*0370*/ ISETP.LT.OR P1, PT, R0.reuse, R9, !P6 ; /* 0x000000090000720c */
/* 0x040fe20007721670 */
/*0380*/ IMAD.IADD R9, R0, 0x1, -R9 ; /* 0x0000000100097824 */
/* 0x000fe200078e0a09 */
/*0390*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x17c], P0 ; /* 0x00005f0008007a0c */
/* 0x000fe40000706670 */
/*03a0*/ IADD3 R11, R25, 0x3, RZ ; /* 0x00000003190b7810 */
/* 0x000fe40007ffe0ff */
/*03b0*/ ISETP.GE.OR P1, PT, R24, c[0x0][0x178], P1 ; /* 0x00005e0018007a0c */
/* 0x000fc80000f26670 */
/*03c0*/ ISETP.GE.OR P1, PT, R9, c[0x0][0x17c], P1 ; /* 0x00005f0009007a0c */
/* 0x000fda0000f26670 */
/*03d0*/ @!P1 LDG.E.64 R8, [R16.64+0x10] ; /* 0x0000100610089981 */
/* 0x000ee2000c1e1b00 */
/*03e0*/ @!P2 DFMA R2, R6, R4, R2 ; /* 0x000000040602a22b */
/* 0x0070620000000002 */
/*03f0*/ ISETP.LT.OR P2, PT, R0.reuse, R11, !P6 ; /* 0x0000000b0000720c */
/* 0x040fe20007741670 */
/*0400*/ IMAD.IADD R11, R0, 0x1, -R11 ; /* 0x00000001000b7824 */
/* 0x000fe200078e0a0b */
/*0410*/ @!P0 LDG.E.64 R4, [R16.64+0x8] ; /* 0x0000080610048981 */
/* 0x001e64000c1e1b00 */
/*0420*/ ISETP.GE.OR P2, PT, R24, c[0x0][0x178], P2 ; /* 0x00005e0018007a0c */
/* 0x000fe40001746670 */
/*0430*/ @!P0 LDG.E.64 R6, [R12.64+-0x8] ; /* 0xfffff8060c068981 */
/* 0x000e64000c1e1b00 */
/*0440*/ ISETP.GE.OR P2, PT, R11, c[0x0][0x17c], P2 ; /* 0x00005f000b007a0c */
/* 0x000fc40001746670 */
/*0450*/ @!P1 LDG.E.64 R10, [R12.64+-0x10] ; /* 0xfffff0060c0a9981 */
/* 0x000ef6000c1e1b00 */
/*0460*/ @!P2 LDG.E.64 R14, [R16.64+0x18] ; /* 0x00001806100ea981 */
/* 0x000ea8000c1e1b00 */
/*0470*/ @!P2 LDG.E.64 R18, [R12.64+-0x18] ; /* 0xffffe8060c12a981 */
/* 0x000ea2000c1e1b00 */
/*0480*/ IADD3 R27, R27, -0x4, RZ ; /* 0xfffffffc1b1b7810 */
/* 0x000fc40007ffe0ff */
/*0490*/ IADD3 R25, R25, 0x4, RZ ; /* 0x0000000419197810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ @!P0 DFMA R2, R4, R6, R2 ; /* 0x000000060402822b */
/* 0x002ee20000000002 */
/*04b0*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fca0003f05270 */
/*04c0*/ @!P1 DFMA R2, R8, R10, R2 ; /* 0x0000000a0802922b */
/* 0x008e8c0000000002 */
/*04d0*/ @!P2 DFMA R2, R14, R18, R2 ; /* 0x000000120e02a22b */
/* 0x0040640000000002 */
/*04e0*/ @P0 BRA 0x280 ; /* 0xfffffd9000000947 */
/* 0x000fea000383ffff */
/*04f0*/ @!P4 BRA 0x790 ; /* 0x000002900000c947 */
/* 0x000fea0003800000 */
/*0500*/ ISETP.GE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f06270 */
/*0510*/ IMAD.IADD R5, R0.reuse, 0x1, -R25.reuse ; /* 0x0000000100057824 */
/* 0x140fe200078e0a19 */
/*0520*/ BSSY B0, 0x610 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fe200078e00ff */
/*0540*/ ISETP.LT.OR P1, PT, R0, R25, !P0 ; /* 0x000000190000720c */
/* 0x000fe20004721670 */
/*0550*/ IMAD R6, R26, c[0x0][0x184], R25 ; /* 0x000061001a067a24 */
/* 0x000fe200078e0219 */
/*0560*/ ISETP.NE.AND P2, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe40003f45270 */
/*0570*/ ISETP.GE.OR P1, PT, R24, c[0x0][0x178], P1 ; /* 0x00005e0018007a0c */
/* 0x000fe20000f26670 */
/*0580*/ IMAD.WIDE R6, R6, R4, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e0204 */
/*0590*/ ISETP.GE.OR P1, PT, R5, c[0x0][0x17c], P1 ; /* 0x00005f0005007a0c */
/* 0x000fe20000f26670 */
/*05a0*/ IMAD R5, R24, c[0x0][0x17c], R5 ; /* 0x00005f0018057a24 */
/* 0x000fc800078e0205 */
/*05b0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fd000078e0204 */
/*05c0*/ @P1 BRA 0x600 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea8000c1e1b00 */
/*05e0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x000ea4000c1e1b00 */
/*05f0*/ DFMA R2, R8, R10, R2 ; /* 0x0000000a0802722b */
/* 0x00628c0000000002 */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0610*/ @!P2 BRA 0x790 ; /* 0x000001700000a947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.LE.OR P1, PT, R0.reuse, R25, !P0 ; /* 0x000000190000720c */
/* 0x040fe20004723670 */
/*0630*/ BSSY B0, 0x6d0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0640*/ IADD3 R8, R0, -0x1, -R25 ; /* 0xffffffff00087810 */
/* 0x002fe40007ffe819 */
/*0650*/ ISETP.GE.OR P1, PT, R24, c[0x0][0x178], P1 ; /* 0x00005e0018007a0c */
/* 0x000fc40000f26670 */
/*0660*/ ISETP.NE.AND P2, PT, R20, 0x2, PT ; /* 0x000000021400780c */
/* 0x000fe40003f45270 */
/*0670*/ ISETP.GE.OR P1, PT, R8, c[0x0][0x17c], P1 ; /* 0x00005f0008007a0c */
/* 0x000fda0000f26670 */
/*0680*/ @P1 BRA 0x6c0 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080606087981 */
/* 0x000ee8000c1e1b00 */
/*06a0*/ LDG.E.64 R10, [R4.64+-0x8] ; /* 0xfffff806040a7981 */
/* 0x000ee4000c1e1b00 */
/*06b0*/ DFMA R2, R8, R10, R2 ; /* 0x0000000a0802722b */
/* 0x00c28c0000000002 */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ @!P2 BRA 0x790 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*06e0*/ IADD3 R25, R25, 0x2, RZ ; /* 0x0000000219197810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ BSSY B0, 0x790 ; /* 0x0000009000007945 */
/* 0x000fe60003800000 */
/*0700*/ ISETP.LT.OR P0, PT, R0.reuse, R25, !P0 ; /* 0x000000190000720c */
/* 0x040fe20004701670 */
/*0710*/ IMAD.IADD R25, R0, 0x1, -R25 ; /* 0x0000000100197824 */
/* 0x000fc600078e0a19 */
/*0720*/ ISETP.GE.OR P0, PT, R24, c[0x0][0x178], P0 ; /* 0x00005e0018007a0c */
/* 0x000fc80000706670 */
/*0730*/ ISETP.GE.OR P0, PT, R25, c[0x0][0x17c], P0 ; /* 0x00005f0019007a0c */
/* 0x000fda0000706670 */
/*0740*/ @P0 BRA 0x780 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0750*/ LDG.E.64 R6, [R6.64+0x10] ; /* 0x0000100606067981 */
/* 0x000ee8000c1e1b00 */
/*0760*/ LDG.E.64 R4, [R4.64+-0x10] ; /* 0xfffff00604047981 */
/* 0x000ee4000c1e1b00 */
/*0770*/ DFMA R2, R6, R4, R2 ; /* 0x000000040602722b */
/* 0x00c4cc0000000002 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ @!P5 BRA 0x1e0 ; /* 0xfffffa400000d947 */
/* 0x000fea000383ffff */
/*07a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x004fe400078e00ff */
/*07b0*/ IMAD R4, R21, UR4, R0 ; /* 0x0000000415047c24 */
/* 0x000fc8000f8e0200 */
/*07c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*07d0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x00afe8000c101b06 */
/*07e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <cuda_runtime.h>
#include <cstdlib>
#include <sstream>
#include <iomanip>
using namespace std;
//input, filter and output considering maximum dimension possible
double a[1000][1000], h[10][10], c[1000][1000];
/**
* CUDA Kernel Device code
*
* Computes the 2D convolution of input b with filter h and output c
*/
__global__ void
convolution2D(double *a_1, double *h_1, double *c_1, int rows_a, int columns_a, int rows_h, int columns_h)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
double sum;
if((idx < (columns_h+columns_a - 1)) && (idy < (rows_h + rows_a - 1)))
{
sum = 0;
for(int k=0; k< rows_h; k++)
{
for(int j=0; j< columns_h; j++)
{
if ((idy - k) >= 0 && (idx - j) >= 0 && (idy - k) < rows_a && (idx - j) < columns_a)
{
sum += a_1[((idy - k)*columns_a) + (idx - j)] * h_1[k*columns_h + j];
}
}
}
c_1[idy*(columns_a + columns_h - 1) + idx] = sum;
__syncthreads();
}
}
/**
* Host main routine
*/
int main(int argc, char** argv)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
int columns_a, columns_h, rows_a, rows_h, size_a, size_h;
columns_a = columns_h = 0;
size_a = size_h = rows_a = rows_h = 0;
char *ip_file;
string line;
double input;
ip_file = argv[1];
int i, j, k;
ifstream file(ip_file);
if(file.is_open())
{
i=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
a[i][j] = input;
size_a++;
j++;
}
i++;
rows_a++;
}
k=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
h[k][j] = input;
j++;
size_h++;
}
k++;
rows_h++;
}
}
file.close();
columns_a = size_a/rows_a;
columns_h = size_h/rows_h;
int op_size = ((rows_a+rows_h-1)*(columns_a+columns_h-1));
size_t size_ax = size_a*sizeof(double);
size_t size_hx = size_h*sizeof(double);
size_t size_cx = op_size*sizeof(double);
// Allocate the host input vector a
double *h_a;
cudaMallocManaged(&h_a, size_ax);
// Allocate the host input vector h
double *h_h;
cudaMallocManaged(&h_h, size_hx);
// Allocate the host output vector c
double *h_c;
cudaMallocManaged(&h_c, size_cx);
for (int i = 0; i < rows_a; i++)
{
for(int j=0;j< columns_a; j++)
{
h_a[i*columns_a + j] = a[i][j];
}
}
for (int i = 0; i < rows_h; i++)
{
for(int j=0;j< columns_h; j++)
{
h_h[i*columns_h + j] = h[i][j];
}
}
// Launch the CUDA Kernel
dim3 blocksPerGrid(((rows_a + rows_h - 2) / 32) + 1, ((columns_h + columns_a - 2) / 32) + 1, 1);
dim3 threadsPerBlock(32,32,1);
convolution2D<<<blocksPerGrid, threadsPerBlock>>>(h_a, h_h, h_c, rows_a, columns_a, rows_h, columns_h);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch convolution2D kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaDeviceSynchronize();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to synchronize (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/////////////////////////////////////////////////////////////////////////////////////////////////////////
for (int i = 0; i < rows_a + rows_h - 1; i++) {
for (int j = 0; j < columns_a + columns_h - 1; j++)
{
cout << fixed << setprecision(3) << h_c[(i*(columns_h+columns_a-1))+j] << " ";
}
cout << endl;
}
// Free device global memory
err = cudaFree(h_a);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector a (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(h_h);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector h (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(h_c);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector c (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Reset the device and exit
// cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Done\n");
return 0;
} | .file "tmpxft_001387e5_00000000-6_exec2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4043:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4043:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z13convolution2DPdS_S_iiiiPdS_S_iiii
.type _Z41__device_stub__Z13convolution2DPdS_S_iiiiPdS_S_iiii, @function
_Z41__device_stub__Z13convolution2DPdS_S_iiiiPdS_S_iiii:
.LFB4065:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13convolution2DPdS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4065:
.size _Z41__device_stub__Z13convolution2DPdS_S_iiiiPdS_S_iiii, .-_Z41__device_stub__Z13convolution2DPdS_S_iiiiPdS_S_iiii
.globl _Z13convolution2DPdS_S_iiii
.type _Z13convolution2DPdS_S_iiii, @function
_Z13convolution2DPdS_S_iiii:
.LFB4066:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z13convolution2DPdS_S_iiiiPdS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4066:
.size _Z13convolution2DPdS_S_iiii, .-_Z13convolution2DPdS_S_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13convolution2DPdS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13convolution2DPdS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev,"axG",@progbits,_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED5Ev,comdat
.align 2
.weak _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev
.type _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev, @function
_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev:
.LFB4400:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, (%rdi)
movq 72(%rdi), %rdi
leaq 88(%rbx), %rax
cmpq %rax, %rdi
je .L14
movq 88(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L14:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rbx)
leaq 56(%rbx), %rdi
call _ZNSt6localeD1Ev@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4400:
.size _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev, .-_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev
.weak _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED1Ev
.set _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED1Ev,_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED2Ev
.section .text._ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED0Ev,"axG",@progbits,_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED5Ev,comdat
.align 2
.weak _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED0Ev
.type _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED0Ev, @function
_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED0Ev:
.LFB4402:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, (%rdi)
movq 72(%rdi), %rdi
leaq 88(%rbx), %rax
cmpq %rax, %rdi
je .L17
movq 88(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L17:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rbx)
leaq 56(%rbx), %rdi
call _ZNSt6localeD1Ev@PLT
movl $104, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4402:
.size _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED0Ev, .-_ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED0Ev
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB4495:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L26
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L22
movzbl (%rsi), %eax
movb %al, (%rdi)
.L23:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L21:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L23
.L22:
testq %rdx, %rdx
je .L23
jmp .L21
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4495:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string: construction from null is not valid"
.align 8
.LC2:
.string "Failed to launch convolution2D kernel (error code %s)!\n"
.align 8
.LC3:
.string "Failed to synchronize (error code %s)!\n"
.section .rodata.str1.1
.LC4:
.string " "
.section .rodata.str1.8
.align 8
.LC5:
.string "Failed to free device vector a (error code %s)!\n"
.align 8
.LC6:
.string "Failed to free device vector h (error code %s)!\n"
.align 8
.LC7:
.string "Failed to free device vector c (error code %s)!\n"
.align 8
.LC8:
.string "Failed to deinitialize the device! error=%s\n"
.section .rodata.str1.1
.LC9:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB4039:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4039
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1080, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -992(%rbp), %rax
movq %rax, -1008(%rbp)
movq $0, -1000(%rbp)
movb $0, -992(%rbp)
movq 8(%rsi), %rsi
leaq -576(%rbp), %rdi
movl $8, %edx
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq -456(%rbp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L103
movq -576(%rbp), %rax
movq -24(%rax), %rax
movq -336(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L30
leaq a(%rip), %rax
movq %rax, -1088(%rbp)
movl $0, -1080(%rbp)
movl $0, -1092(%rbp)
jmp .L34
.L141:
movq -1088(%rbp), %rbx
leaq -1064(%rbp), %r12
jmp .L49
.L134:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L133
movsd -1064(%rbp), %xmm0
movsd %xmm0, (%rbx)
addl $1, -1080(%rbp)
addq $8, %rbx
.L49:
leaq -976(%rbp), %rdi
movq %r12, %rsi
.LEHB1:
call _ZNSi10_M_extractIdEERSiRT_@PLT
.LEHE1:
jmp .L134
.L133:
addl $1, -1092(%rbp)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -976(%rbp)
leaq 80(%rax), %rax
movq %rax, -848(%rbp)
leaq -40(%rax), %rax
movq %rax, -960(%rbp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -952(%rbp)
movq -880(%rbp), %rdi
leaq -864(%rbp), %rax
cmpq %rax, %rdi
je .L33
movq -864(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L33:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -952(%rbp)
leaq -896(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r14, -976(%rbp)
movq -24(%r14), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rsi, -976(%rbp,%rax)
movq %r15, -960(%rbp)
movq -24(%r15), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rsi, -960(%rbp,%rax)
movq %r13, -976(%rbp)
movq -24(%r13), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx
movq %rbx, -976(%rbp,%rax)
movq $0, -968(%rbp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -848(%rbp)
leaq -848(%rbp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq -576(%rbp), %rax
movq -24(%rax), %rax
movq -336(%rbp,%rax), %rbx
addq $8000, -1088(%rbp)
testq %rbx, %rbx
je .L30
.L34:
cmpb $0, 56(%rbx)
je .L36
movzbl 67(%rbx), %edx
.L37:
movsbl %dl, %edx
leaq -1008(%rbp), %rsi
leaq -576(%rbp), %rdi
.LEHB2:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L135
.L30:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L136
call _ZSt16__throw_bad_castv@PLT
.L136:
call __stack_chk_fail@PLT
.L36:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE2:
movl %eax, %edx
jmp .L37
.L135:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L38
cmpq $0, -1000(%rbp)
je .L38
leaq -976(%rbp), %rbx
leaq -848(%rbp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -848(%rbp)
movq $0, -632(%rbp)
movb $0, -624(%rbp)
movb $0, -623(%rbp)
movq $0, -616(%rbp)
movq $0, -608(%rbp)
movq $0, -600(%rbp)
movq $0, -592(%rbp)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r13
movq %r13, -976(%rbp)
movq -24(%r13), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rsi, -976(%rbp,%rax)
movq $0, -968(%rbp)
movq -976(%rbp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB3:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE3:
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r15
movq %r15, -960(%rbp)
movq -24(%r15), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx
movq %rbx, -960(%rbp,%rax)
movq -960(%rbp), %rax
movq -24(%rax), %rax
leaq -960(%rbp,%rax), %rdi
movl $0, %esi
.LEHB4:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE4:
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r14
movq %r14, -976(%rbp)
movq -24(%r14), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rsi, -976(%rbp,%rax)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -976(%rbp)
leaq 80(%rax), %rax
movq %rax, -848(%rbp)
leaq -40(%rax), %rax
movq %rax, -960(%rbp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -952(%rbp)
movq $0, -944(%rbp)
movq $0, -936(%rbp)
movq $0, -928(%rbp)
movq $0, -920(%rbp)
movq $0, -912(%rbp)
movq $0, -904(%rbp)
leaq -896(%rbp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -952(%rbp)
movl $0, -888(%rbp)
movq -1000(%rbp), %rdx
movq -1008(%rbp), %rsi
leaq -864(%rbp), %rax
movq %rax, -880(%rbp)
testq %rsi, %rsi
jne .L41
testq %rdx, %rdx
jne .L137
.L41:
addq %rsi, %rdx
leaq -880(%rbp), %rdi
.LEHB5:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
jmp .L138
.L112:
endbr64
movq %rax, %rbx
movq %r13, -976(%rbp)
movq -24(%r13), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rsi, -976(%rbp,%rax)
movq $0, -968(%rbp)
.L43:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -848(%rbp)
leaq -848(%rbp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L51:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L100:
leaq -1008(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L101
call __stack_chk_fail@PLT
.L137:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L139
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.LEHE5:
.L113:
endbr64
movq %rax, %rbx
jmp .L47
.L139:
call __stack_chk_fail@PLT
.L138:
movl $24, -888(%rbp)
leaq -952(%rbp), %rdi
movl $0, %ecx
movl $0, %edx
movq -880(%rbp), %rsi
.LEHB6:
call _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@PLT
.LEHE6:
jmp .L140
.L114:
endbr64
movq %rax, %rbx
leaq -880(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L47:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -952(%rbp)
leaq -896(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
.L48:
leaq -976(%rbp), %rdi
leaq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
call _ZNSdD2Ev@PLT
jmp .L43
.L140:
leaq -952(%rbp), %rsi
leaq -848(%rbp), %rdi
.LEHB7:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE7:
jmp .L141
.L111:
endbr64
movq %rax, %rbx
leaq -952(%rbp), %rdi
call _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED1Ev
jmp .L48
.L110:
endbr64
movq %rax, %rbx
jmp .L43
.L150:
movq -1088(%rbp), %rbx
leaq -1064(%rbp), %r13
jmp .L70
.L143:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L142
movsd -1064(%rbp), %xmm0
movsd %xmm0, (%rbx)
addl $1, %r12d
addq $8, %rbx
.L70:
leaq -976(%rbp), %rdi
movq %r13, %rsi
.LEHB8:
call _ZNSi10_M_extractIdEERSiRT_@PLT
.LEHE8:
jmp .L143
.L142:
addl $1, -1096(%rbp)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -976(%rbp)
leaq 80(%rax), %rax
movq %rax, -848(%rbp)
leaq -40(%rax), %rax
movq %rax, -960(%rbp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -952(%rbp)
movq -880(%rbp), %rdi
leaq -864(%rbp), %rax
cmpq %rax, %rdi
je .L53
movq -864(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L53:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -952(%rbp)
leaq -896(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -976(%rbp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx
movq %rbx, -976(%rbp,%rax)
movq %r15, -960(%rbp)
movq -24(%r15), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rsi, -960(%rbp,%rax)
movq %r14, -976(%rbp)
movq -24(%r14), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx
movq %rbx, -976(%rbp,%rax)
movq $0, -968(%rbp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -848(%rbp)
leaq -848(%rbp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq -576(%rbp), %rax
movq -24(%rax), %rax
movq -336(%rbp,%rax), %rbx
addq $80, -1088(%rbp)
testq %rbx, %rbx
je .L54
.L55:
cmpb $0, 56(%rbx)
je .L58
movzbl 67(%rbx), %edx
.L59:
movsbl %dl, %edx
leaq -1008(%rbp), %rsi
leaq -576(%rbp), %rdi
.LEHB9:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L144
.L38:
movq -576(%rbp), %rax
movq -24(%rax), %rax
movq -336(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L54
leaq h(%rip), %rax
movq %rax, -1088(%rbp)
movl $0, -1096(%rbp)
movl $0, %r12d
jmp .L55
.L54:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L145
call _ZSt16__throw_bad_castv@PLT
.L145:
call __stack_chk_fail@PLT
.L58:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE9:
movl %eax, %edx
jmp .L59
.L144:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L29
cmpq $0, -1000(%rbp)
je .L29
leaq -976(%rbp), %rbx
leaq -848(%rbp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -848(%rbp)
movq $0, -632(%rbp)
movb $0, -624(%rbp)
movb $0, -623(%rbp)
movq $0, -616(%rbp)
movq $0, -608(%rbp)
movq $0, -600(%rbp)
movq $0, -592(%rbp)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r14
movq %r14, -976(%rbp)
movq -24(%r14), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rsi, -976(%rbp,%rax)
movq $0, -968(%rbp)
movq -976(%rbp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB10:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE10:
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r15
movq %r15, -960(%rbp)
movq -24(%r15), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rbx
movq %rbx, -960(%rbp,%rax)
movq -960(%rbp), %rax
movq -24(%rax), %rax
leaq -960(%rbp,%rax), %rdi
movl $0, %esi
.LEHB11:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE11:
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -976(%rbp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rsi, -976(%rbp,%rax)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -976(%rbp)
leaq 80(%rax), %rax
movq %rax, -848(%rbp)
leaq -40(%rax), %rax
movq %rax, -960(%rbp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -952(%rbp)
movq $0, -944(%rbp)
movq $0, -936(%rbp)
movq $0, -928(%rbp)
movq $0, -920(%rbp)
movq $0, -912(%rbp)
movq $0, -904(%rbp)
leaq -896(%rbp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -952(%rbp)
movl $0, -888(%rbp)
movq -1000(%rbp), %rdx
movq -1008(%rbp), %rsi
leaq -864(%rbp), %rax
movq %rax, -880(%rbp)
testq %rsi, %rsi
jne .L62
testq %rdx, %rdx
jne .L146
.L62:
addq %rsi, %rdx
leaq -880(%rbp), %rdi
.LEHB12:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
jmp .L147
.L117:
endbr64
movq %rax, %rbx
movq %r14, -976(%rbp)
movq -24(%r14), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rsi, -976(%rbp,%rax)
movq $0, -968(%rbp)
.L64:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -848(%rbp)
leaq -848(%rbp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
jmp .L51
.L146:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L148
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.LEHE12:
.L118:
endbr64
movq %rax, %rbx
jmp .L68
.L148:
call __stack_chk_fail@PLT
.L147:
movl $24, -888(%rbp)
leaq -952(%rbp), %rdi
movl $0, %ecx
movl $0, %edx
movq -880(%rbp), %rsi
.LEHB13:
call _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@PLT
.LEHE13:
jmp .L149
.L119:
endbr64
movq %rax, %rbx
leaq -880(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L68:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -952(%rbp)
leaq -896(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
.L69:
leaq -976(%rbp), %rdi
leaq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
call _ZNSdD2Ev@PLT
jmp .L64
.L149:
leaq -952(%rbp), %rsi
leaq -848(%rbp), %rdi
.LEHB14:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE14:
jmp .L150
.L116:
endbr64
movq %rax, %rbx
leaq -952(%rbp), %rdi
call _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEED1Ev
jmp .L69
.L115:
endbr64
movq %rax, %rbx
jmp .L64
.L103:
movl $0, %r12d
movl $0, -1080(%rbp)
movl $0, -1096(%rbp)
movl $0, -1092(%rbp)
.L29:
leaq -576(%rbp), %rdi
.LEHB15:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
movl -1080(%rbp), %eax
movl -1092(%rbp), %ebx
cltd
idivl %ebx
movl %eax, %r13d
movl %r12d, %eax
movl -1096(%rbp), %esi
cltd
idivl %esi
movl %eax, %r14d
leal (%rbx,%rsi), %r15d
leal -1(%r15), %edi
movl %edi, -1100(%rbp)
leal 0(%r13,%rax), %ebx
leal -1(%rbx), %edx
movl %edx, -1088(%rbp)
movslq %r12d, %rax
leaq 0(,%rax,8), %rsi
movq %rsi, -1112(%rbp)
imull %edx, %edi
movslq %edi, %r12
salq $3, %r12
movslq -1080(%rbp), %rsi
salq $3, %rsi
leaq -1056(%rbp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq -1048(%rbp), %rdi
movl $1, %edx
movq -1112(%rbp), %rsi
call cudaMallocManaged@PLT
leaq -1040(%rbp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
movl -1092(%rbp), %eax
testl %eax, %eax
jle .L72
movslq %eax, %r9
imulq $8000, %r9, %r9
movl $0, %edi
movl $0, %r8d
movslq %r13d, %r11
leaq a(%rip), %r10
jmp .L73
.L76:
addl %r13d, %r8d
addq $8000, %rdi
cmpq %rdi, %r9
je .L72
.L73:
testl %r13d, %r13d
jle .L76
movslq %r8d, %rdx
leaq 0(,%rdx,8), %rax
leaq (%r11,%rdx), %rsi
salq $3, %rsi
negq %rdx
leaq (%rdi,%rdx,8), %rcx
addq %r10, %rcx
.L74:
movsd (%rcx,%rax), %xmm0
movq -1056(%rbp), %rdx
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq %rsi, %rax
jne .L74
jmp .L76
.L72:
movl -1096(%rbp), %eax
testl %eax, %eax
jle .L77
cltq
leaq (%rax,%rax,4), %r9
salq $4, %r9
movl $0, %edi
movl $0, %r8d
movslq %r14d, %r11
leaq h(%rip), %r10
jmp .L78
.L81:
addl %r14d, %r8d
addq $80, %rdi
cmpq %rdi, %r9
je .L77
.L78:
testl %r14d, %r14d
jle .L81
movslq %r8d, %rdx
leaq 0(,%rdx,8), %rax
leaq (%r11,%rdx), %rsi
salq $3, %rsi
negq %rdx
leaq (%rdi,%rdx,8), %rcx
addq %r10, %rcx
.L79:
movsd (%rcx,%rax), %xmm0
movq -1048(%rbp), %rdx
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq %rsi, %rax
jne .L79
jmp .L81
.L77:
leal 29(%r15), %eax
movl %r15d, %edx
subl $2, %edx
cmovns %edx, %eax
sarl $5, %eax
addl $1, %eax
movl %eax, -1032(%rbp)
leal 29(%rbx), %eax
movl %ebx, %edx
subl $2, %edx
cmovns %edx, %eax
sarl $5, %eax
addl $1, %eax
movl %eax, -1028(%rbp)
movl $1, -1024(%rbp)
movl $32, -1020(%rbp)
movl $32, -1016(%rbp)
movl $1, -1012(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1020(%rbp), %rdx
movl $1, %ecx
movq -1032(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L82
subq $8, %rsp
pushq %r14
movl -1096(%rbp), %r9d
movl %r13d, %r8d
movl -1092(%rbp), %ecx
movq -1040(%rbp), %rdx
movq -1048(%rbp), %rsi
movq -1056(%rbp), %rdi
.cfi_escape 0x2e,0x10
call _Z41__device_stub__Z13convolution2DPdS_S_iiiiPdS_S_iiii
addq $16, %rsp
.L82:
.cfi_escape 0x2e,0
call cudaGetLastError@PLT
testl %eax, %eax
jne .L151
call cudaDeviceSynchronize@PLT
jmp .L152
.L151:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L152:
movl %eax, %r14d
testl %eax, %eax
jne .L84
cmpl $0, -1100(%rbp)
jle .L85
leal -1(%r15), %eax
movl %eax, -1092(%rbp)
movl $0, %r15d
leal -1(%rbx), %eax
movl %eax, -1096(%rbp)
leaq _ZSt4cout(%rip), %rbx
leaq .LC4(%rip), %r13
jmp .L86
.L84:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L153:
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, -1080(%rbp)
movq -1080(%rbp), %rcx
cmpq %rcx, %r12
je .L93
.L87:
movq (%rbx), %rdx
movq %rbx, %rcx
addq -24(%rdx), %rcx
movl 24(%rcx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rcx)
movq -24(%rdx), %rax
movq $3, 8(%rbx,%rax)
movq -1040(%rbp), %rax
movq -1080(%rbp), %rcx
movsd (%rax,%rcx), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L153
.L93:
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rax
movq %rax, %rdi
testq %rax, %rax
je .L154
cmpb $0, 56(%rax)
je .L90
movzbl 67(%rax), %esi
.L91:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L155
.L154:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L156
call _ZSt16__throw_bad_castv@PLT
.L108:
endbr64
movq %rax, %rbx
jmp .L51
.L156:
call __stack_chk_fail@PLT
.L90:
movq %rax, %r12
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq %r12, %rdi
movq (%r12), %rax
movl $10, %esi
call *48(%rax)
movl %eax, %esi
jmp .L91
.L155:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r15d
movl -1088(%rbp), %eax
addl %eax, %r14d
movl -1092(%rbp), %eax
cmpl %eax, %r15d
je .L85
.L86:
cmpl $0, -1088(%rbp)
jle .L93
movslq %r14d, %rax
leaq 0(,%rax,8), %rsi
movq %rsi, -1080(%rbp)
movl -1096(%rbp), %r12d
addq %rax, %r12
salq $3, %r12
jmp .L87
.L85:
movq -1056(%rbp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L157
movq -1048(%rbp), %rdi
call cudaFree@PLT
jmp .L158
.L157:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L158:
testl %eax, %eax
jne .L159
movq -1040(%rbp), %rdi
call cudaFree@PLT
jmp .L160
.L159:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L160:
testl %eax, %eax
jne .L161
call cudaDeviceReset@PLT
jmp .L162
.L161:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L162:
testl %eax, %eax
jne .L163
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L164
.L163:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE15:
movl $1, %edi
call exit@PLT
.L164:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq -1008(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L165
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L107:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -976(%rbp), %rdi
call _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
jmp .L51
.L109:
endbr64
movq %rax, %rbx
leaq -976(%rbp), %rdi
call _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
jmp .L51
.L106:
endbr64
movq %rax, %rbx
jmp .L100
.L101:
movq %rbx, %rdi
.LEHB16:
call _Unwind_Resume@PLT
.LEHE16:
.L165:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4039:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4039-.LLSDACSB4039
.LLSDACSB4039:
.uleb128 .LEHB0-.LFB4039
.uleb128 .LEHE0-.LEHB0
.uleb128 .L106-.LFB4039
.uleb128 0
.uleb128 .LEHB1-.LFB4039
.uleb128 .LEHE1-.LEHB1
.uleb128 .L107-.LFB4039
.uleb128 0
.uleb128 .LEHB2-.LFB4039
.uleb128 .LEHE2-.LEHB2
.uleb128 .L108-.LFB4039
.uleb128 0
.uleb128 .LEHB3-.LFB4039
.uleb128 .LEHE3-.LEHB3
.uleb128 .L110-.LFB4039
.uleb128 0
.uleb128 .LEHB4-.LFB4039
.uleb128 .LEHE4-.LEHB4
.uleb128 .L112-.LFB4039
.uleb128 0
.uleb128 .LEHB5-.LFB4039
.uleb128 .LEHE5-.LEHB5
.uleb128 .L113-.LFB4039
.uleb128 0
.uleb128 .LEHB6-.LFB4039
.uleb128 .LEHE6-.LEHB6
.uleb128 .L114-.LFB4039
.uleb128 0
.uleb128 .LEHB7-.LFB4039
.uleb128 .LEHE7-.LEHB7
.uleb128 .L111-.LFB4039
.uleb128 0
.uleb128 .LEHB8-.LFB4039
.uleb128 .LEHE8-.LEHB8
.uleb128 .L109-.LFB4039
.uleb128 0
.uleb128 .LEHB9-.LFB4039
.uleb128 .LEHE9-.LEHB9
.uleb128 .L108-.LFB4039
.uleb128 0
.uleb128 .LEHB10-.LFB4039
.uleb128 .LEHE10-.LEHB10
.uleb128 .L115-.LFB4039
.uleb128 0
.uleb128 .LEHB11-.LFB4039
.uleb128 .LEHE11-.LEHB11
.uleb128 .L117-.LFB4039
.uleb128 0
.uleb128 .LEHB12-.LFB4039
.uleb128 .LEHE12-.LEHB12
.uleb128 .L118-.LFB4039
.uleb128 0
.uleb128 .LEHB13-.LFB4039
.uleb128 .LEHE13-.LEHB13
.uleb128 .L119-.LFB4039
.uleb128 0
.uleb128 .LEHB14-.LFB4039
.uleb128 .LEHE14-.LEHB14
.uleb128 .L116-.LFB4039
.uleb128 0
.uleb128 .LEHB15-.LFB4039
.uleb128 .LEHE15-.LEHB15
.uleb128 .L108-.LFB4039
.uleb128 0
.uleb128 .LEHB16-.LFB4039
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.LLSDACSE4039:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl c
.bss
.align 32
.type c, @object
.size c, 8000000
c:
.zero 8000000
.globl h
.align 32
.type h, @object
.size h, 800
h:
.zero 800
.globl a
.align 32
.type a, @object
.size a, 8000000
a:
.zero 8000000
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <cuda_runtime.h>
#include <cstdlib>
#include <sstream>
#include <iomanip>
using namespace std;
//input, filter and output considering maximum dimension possible
double a[1000][1000], h[10][10], c[1000][1000];
/**
* CUDA Kernel Device code
*
* Computes the 2D convolution of input b with filter h and output c
*/
__global__ void
convolution2D(double *a_1, double *h_1, double *c_1, int rows_a, int columns_a, int rows_h, int columns_h)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
double sum;
if((idx < (columns_h+columns_a - 1)) && (idy < (rows_h + rows_a - 1)))
{
sum = 0;
for(int k=0; k< rows_h; k++)
{
for(int j=0; j< columns_h; j++)
{
if ((idy - k) >= 0 && (idx - j) >= 0 && (idy - k) < rows_a && (idx - j) < columns_a)
{
sum += a_1[((idy - k)*columns_a) + (idx - j)] * h_1[k*columns_h + j];
}
}
}
c_1[idy*(columns_a + columns_h - 1) + idx] = sum;
__syncthreads();
}
}
/**
* Host main routine
*/
int main(int argc, char** argv)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
int columns_a, columns_h, rows_a, rows_h, size_a, size_h;
columns_a = columns_h = 0;
size_a = size_h = rows_a = rows_h = 0;
char *ip_file;
string line;
double input;
ip_file = argv[1];
int i, j, k;
ifstream file(ip_file);
if(file.is_open())
{
i=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
a[i][j] = input;
size_a++;
j++;
}
i++;
rows_a++;
}
k=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
h[k][j] = input;
j++;
size_h++;
}
k++;
rows_h++;
}
}
file.close();
columns_a = size_a/rows_a;
columns_h = size_h/rows_h;
int op_size = ((rows_a+rows_h-1)*(columns_a+columns_h-1));
size_t size_ax = size_a*sizeof(double);
size_t size_hx = size_h*sizeof(double);
size_t size_cx = op_size*sizeof(double);
// Allocate the host input vector a
double *h_a;
cudaMallocManaged(&h_a, size_ax);
// Allocate the host input vector h
double *h_h;
cudaMallocManaged(&h_h, size_hx);
// Allocate the host output vector c
double *h_c;
cudaMallocManaged(&h_c, size_cx);
for (int i = 0; i < rows_a; i++)
{
for(int j=0;j< columns_a; j++)
{
h_a[i*columns_a + j] = a[i][j];
}
}
for (int i = 0; i < rows_h; i++)
{
for(int j=0;j< columns_h; j++)
{
h_h[i*columns_h + j] = h[i][j];
}
}
// Launch the CUDA Kernel
dim3 blocksPerGrid(((rows_a + rows_h - 2) / 32) + 1, ((columns_h + columns_a - 2) / 32) + 1, 1);
dim3 threadsPerBlock(32,32,1);
convolution2D<<<blocksPerGrid, threadsPerBlock>>>(h_a, h_h, h_c, rows_a, columns_a, rows_h, columns_h);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch convolution2D kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaDeviceSynchronize();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to synchronize (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/////////////////////////////////////////////////////////////////////////////////////////////////////////
for (int i = 0; i < rows_a + rows_h - 1; i++) {
for (int j = 0; j < columns_a + columns_h - 1; j++)
{
cout << fixed << setprecision(3) << h_c[(i*(columns_h+columns_a-1))+j] << " ";
}
cout << endl;
}
// Free device global memory
err = cudaFree(h_a);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector a (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(h_h);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector h (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(h_c);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector c (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Reset the device and exit
// cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Done\n");
return 0;
} | #include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <sstream>
#include <iomanip>
using namespace std;
//input, filter and output considering maximum dimension possible
double a[1000][1000], h[10][10], c[1000][1000];
/**
* CUDA Kernel Device code
*
* Computes the 2D convolution of input b with filter h and output c
*/
__global__ void
convolution2D(double *a_1, double *h_1, double *c_1, int rows_a, int columns_a, int rows_h, int columns_h)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
double sum;
if((idx < (columns_h+columns_a - 1)) && (idy < (rows_h + rows_a - 1)))
{
sum = 0;
for(int k=0; k< rows_h; k++)
{
for(int j=0; j< columns_h; j++)
{
if ((idy - k) >= 0 && (idx - j) >= 0 && (idy - k) < rows_a && (idx - j) < columns_a)
{
sum += a_1[((idy - k)*columns_a) + (idx - j)] * h_1[k*columns_h + j];
}
}
}
c_1[idy*(columns_a + columns_h - 1) + idx] = sum;
__syncthreads();
}
}
/**
* Host main routine
*/
int main(int argc, char** argv)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
int columns_a, columns_h, rows_a, rows_h, size_a, size_h;
columns_a = columns_h = 0;
size_a = size_h = rows_a = rows_h = 0;
char *ip_file;
string line;
double input;
ip_file = argv[1];
int i, j, k;
ifstream file(ip_file);
if(file.is_open())
{
i=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
a[i][j] = input;
size_a++;
j++;
}
i++;
rows_a++;
}
k=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
h[k][j] = input;
j++;
size_h++;
}
k++;
rows_h++;
}
}
file.close();
columns_a = size_a/rows_a;
columns_h = size_h/rows_h;
int op_size = ((rows_a+rows_h-1)*(columns_a+columns_h-1));
size_t size_ax = size_a*sizeof(double);
size_t size_hx = size_h*sizeof(double);
size_t size_cx = op_size*sizeof(double);
// Allocate the host input vector a
double *h_a;
hipMallocManaged(&h_a, size_ax);
// Allocate the host input vector h
double *h_h;
hipMallocManaged(&h_h, size_hx);
// Allocate the host output vector c
double *h_c;
hipMallocManaged(&h_c, size_cx);
for (int i = 0; i < rows_a; i++)
{
for(int j=0;j< columns_a; j++)
{
h_a[i*columns_a + j] = a[i][j];
}
}
for (int i = 0; i < rows_h; i++)
{
for(int j=0;j< columns_h; j++)
{
h_h[i*columns_h + j] = h[i][j];
}
}
// Launch the CUDA Kernel
dim3 blocksPerGrid(((rows_a + rows_h - 2) / 32) + 1, ((columns_h + columns_a - 2) / 32) + 1, 1);
dim3 threadsPerBlock(32,32,1);
convolution2D<<<blocksPerGrid, threadsPerBlock>>>(h_a, h_h, h_c, rows_a, columns_a, rows_h, columns_h);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch convolution2D kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipDeviceSynchronize();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to synchronize (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/////////////////////////////////////////////////////////////////////////////////////////////////////////
for (int i = 0; i < rows_a + rows_h - 1; i++) {
for (int j = 0; j < columns_a + columns_h - 1; j++)
{
cout << fixed << setprecision(3) << h_c[(i*(columns_h+columns_a-1))+j] << " ";
}
cout << endl;
}
// Free device global memory
err = hipFree(h_a);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector a (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(h_h);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector h (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(h_c);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector c (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Reset the device and exit
// cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Done\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <sstream>
#include <iomanip>
using namespace std;
//input, filter and output considering maximum dimension possible
double a[1000][1000], h[10][10], c[1000][1000];
/**
* CUDA Kernel Device code
*
* Computes the 2D convolution of input b with filter h and output c
*/
__global__ void
convolution2D(double *a_1, double *h_1, double *c_1, int rows_a, int columns_a, int rows_h, int columns_h)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
double sum;
if((idx < (columns_h+columns_a - 1)) && (idy < (rows_h + rows_a - 1)))
{
sum = 0;
for(int k=0; k< rows_h; k++)
{
for(int j=0; j< columns_h; j++)
{
if ((idy - k) >= 0 && (idx - j) >= 0 && (idy - k) < rows_a && (idx - j) < columns_a)
{
sum += a_1[((idy - k)*columns_a) + (idx - j)] * h_1[k*columns_h + j];
}
}
}
c_1[idy*(columns_a + columns_h - 1) + idx] = sum;
__syncthreads();
}
}
/**
* Host main routine
*/
int main(int argc, char** argv)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
int columns_a, columns_h, rows_a, rows_h, size_a, size_h;
columns_a = columns_h = 0;
size_a = size_h = rows_a = rows_h = 0;
char *ip_file;
string line;
double input;
ip_file = argv[1];
int i, j, k;
ifstream file(ip_file);
if(file.is_open())
{
i=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
a[i][j] = input;
size_a++;
j++;
}
i++;
rows_a++;
}
k=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
h[k][j] = input;
j++;
size_h++;
}
k++;
rows_h++;
}
}
file.close();
columns_a = size_a/rows_a;
columns_h = size_h/rows_h;
int op_size = ((rows_a+rows_h-1)*(columns_a+columns_h-1));
size_t size_ax = size_a*sizeof(double);
size_t size_hx = size_h*sizeof(double);
size_t size_cx = op_size*sizeof(double);
// Allocate the host input vector a
double *h_a;
hipMallocManaged(&h_a, size_ax);
// Allocate the host input vector h
double *h_h;
hipMallocManaged(&h_h, size_hx);
// Allocate the host output vector c
double *h_c;
hipMallocManaged(&h_c, size_cx);
for (int i = 0; i < rows_a; i++)
{
for(int j=0;j< columns_a; j++)
{
h_a[i*columns_a + j] = a[i][j];
}
}
for (int i = 0; i < rows_h; i++)
{
for(int j=0;j< columns_h; j++)
{
h_h[i*columns_h + j] = h[i][j];
}
}
// Launch the CUDA Kernel
dim3 blocksPerGrid(((rows_a + rows_h - 2) / 32) + 1, ((columns_h + columns_a - 2) / 32) + 1, 1);
dim3 threadsPerBlock(32,32,1);
convolution2D<<<blocksPerGrid, threadsPerBlock>>>(h_a, h_h, h_c, rows_a, columns_a, rows_h, columns_h);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch convolution2D kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipDeviceSynchronize();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to synchronize (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/////////////////////////////////////////////////////////////////////////////////////////////////////////
for (int i = 0; i < rows_a + rows_h - 1; i++) {
for (int j = 0; j < columns_a + columns_h - 1; j++)
{
cout << fixed << setprecision(3) << h_c[(i*(columns_h+columns_a-1))+j] << " ";
}
cout << endl;
}
// Free device global memory
err = hipFree(h_a);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector a (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(h_h);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector h (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(h_c);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector c (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Reset the device and exit
// cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Done\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13convolution2DPdS_S_iiii
.globl _Z13convolution2DPdS_S_iiii
.p2align 8
.type _Z13convolution2DPdS_S_iiii,@function
_Z13convolution2DPdS_S_iiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x1c
s_load_b32 s13, s[0:1], 0x24
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_add_i32 s5, s12, s13
s_mov_b32 s4, exec_lo
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_14
s_load_b32 s2, s[2:3], 0xc
s_clause 0x1
s_load_b32 s14, s[0:1], 0x18
s_load_b32 s16, s[0:1], 0x20
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_add_i32 s2, s14, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_cmp_lt_i32 s16, 1
s_cbranch_scc1 .LBB0_12
s_load_b128 s[8:11], s[0:1], 0x0
v_mul_lo_u32 v0, s12, v2
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_cmp_gt_i32 s13, 0
s_mov_b32 s7, 0
s_cselect_b32 s15, -1, 0
s_mov_b32 s17, 0
s_mov_b32 s18, 0
s_branch .LBB0_5
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_subrev_nc_u32_e32 v0, s12, v0
s_add_i32 s18, s18, 1
s_add_i32 s17, s17, s13
s_cmp_eq_u32 s18, s16
s_cbranch_scc1 .LBB0_13
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_4
v_subrev_nc_u32_e32 v5, s18, v2
s_mov_b32 s6, s17
s_mov_b32 s19, s13
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s14, v5
v_mov_b32_e32 v5, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s20
v_add_nc_u32_e32 v5, -1, v5
s_add_i32 s19, s19, -1
s_add_i32 s6, s6, 1
s_cmp_eq_u32 s19, 0
s_cbranch_scc1 .LBB0_4
.LBB0_9:
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz .LBB0_8
v_cmp_lt_i32_e64 s3, -1, v5
v_cmp_gt_i32_e64 s4, s12, v5
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v6, v0, v5
s_lshl_b64 s[22:23], s[6:7], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s22, s10, s22
s_addc_u32 s23, s11, s23
v_ashrrev_i32_e32 v7, 31, v6
s_load_b64 s[22:23], s[22:23], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_u32 v6, s3, s8, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s3, s9, v7, s3
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], v[6:7], s[22:23], v[3:4]
s_branch .LBB0_7
.LBB0_12:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_13:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v2, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13convolution2DPdS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13convolution2DPdS_S_iiii, .Lfunc_end0-_Z13convolution2DPdS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13convolution2DPdS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z13convolution2DPdS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <sstream>
#include <iomanip>
using namespace std;
//input, filter and output considering maximum dimension possible
double a[1000][1000], h[10][10], c[1000][1000];
/**
* CUDA Kernel Device code
*
* Computes the 2D convolution of input b with filter h and output c
*/
__global__ void
convolution2D(double *a_1, double *h_1, double *c_1, int rows_a, int columns_a, int rows_h, int columns_h)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
double sum;
if((idx < (columns_h+columns_a - 1)) && (idy < (rows_h + rows_a - 1)))
{
sum = 0;
for(int k=0; k< rows_h; k++)
{
for(int j=0; j< columns_h; j++)
{
if ((idy - k) >= 0 && (idx - j) >= 0 && (idy - k) < rows_a && (idx - j) < columns_a)
{
sum += a_1[((idy - k)*columns_a) + (idx - j)] * h_1[k*columns_h + j];
}
}
}
c_1[idy*(columns_a + columns_h - 1) + idx] = sum;
__syncthreads();
}
}
/**
* Host main routine
*/
int main(int argc, char** argv)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
int columns_a, columns_h, rows_a, rows_h, size_a, size_h;
columns_a = columns_h = 0;
size_a = size_h = rows_a = rows_h = 0;
char *ip_file;
string line;
double input;
ip_file = argv[1];
int i, j, k;
ifstream file(ip_file);
if(file.is_open())
{
i=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
a[i][j] = input;
size_a++;
j++;
}
i++;
rows_a++;
}
k=0;
while(getline(file, line) && line != "")
{
j=0;
stringstream ss(line);
while(ss >> input)
{
h[k][j] = input;
j++;
size_h++;
}
k++;
rows_h++;
}
}
file.close();
columns_a = size_a/rows_a;
columns_h = size_h/rows_h;
int op_size = ((rows_a+rows_h-1)*(columns_a+columns_h-1));
size_t size_ax = size_a*sizeof(double);
size_t size_hx = size_h*sizeof(double);
size_t size_cx = op_size*sizeof(double);
// Allocate the host input vector a
double *h_a;
hipMallocManaged(&h_a, size_ax);
// Allocate the host input vector h
double *h_h;
hipMallocManaged(&h_h, size_hx);
// Allocate the host output vector c
double *h_c;
hipMallocManaged(&h_c, size_cx);
for (int i = 0; i < rows_a; i++)
{
for(int j=0;j< columns_a; j++)
{
h_a[i*columns_a + j] = a[i][j];
}
}
for (int i = 0; i < rows_h; i++)
{
for(int j=0;j< columns_h; j++)
{
h_h[i*columns_h + j] = h[i][j];
}
}
// Launch the CUDA Kernel
dim3 blocksPerGrid(((rows_a + rows_h - 2) / 32) + 1, ((columns_h + columns_a - 2) / 32) + 1, 1);
dim3 threadsPerBlock(32,32,1);
convolution2D<<<blocksPerGrid, threadsPerBlock>>>(h_a, h_h, h_c, rows_a, columns_a, rows_h, columns_h);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch convolution2D kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipDeviceSynchronize();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to synchronize (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/////////////////////////////////////////////////////////////////////////////////////////////////////////
for (int i = 0; i < rows_a + rows_h - 1; i++) {
for (int j = 0; j < columns_a + columns_h - 1; j++)
{
cout << fixed << setprecision(3) << h_c[(i*(columns_h+columns_a-1))+j] << " ";
}
cout << endl;
}
// Free device global memory
err = hipFree(h_a);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector a (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(h_h);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector h (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(h_c);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector c (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Reset the device and exit
// cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Done\n");
return 0;
} | .text
.file "exec2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__convolution2DPdS_S_iiii # -- Begin function _Z28__device_stub__convolution2DPdS_S_iiii
.p2align 4, 0x90
.type _Z28__device_stub__convolution2DPdS_S_iiii,@function
_Z28__device_stub__convolution2DPdS_S_iiii: # @_Z28__device_stub__convolution2DPdS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13convolution2DPdS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__convolution2DPdS_S_iiii, .Lfunc_end0-_Z28__device_stub__convolution2DPdS_S_iiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1096, %rsp # imm = 0x448
.cfi_def_cfa_offset 1152
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movq $0, 72(%rsp)
movb $0, 80(%rsp)
movq 8(%rsi), %rsi
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 576(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
leaq 696(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNKSt12__basic_fileIcE7is_openEv
xorl %ebp, %ebp
movl $0, %ebx
movl $0, %ecx
movq %rcx, (%rsp) # 8-byte Spill
movl $0, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
testb %al, %al
je .LBB1_47
# %bb.2: # %.preheader218
movq 576(%rsp), %rax
movq -24(%rax), %rax
movq 816(%rsp,%rax), %r15
testq %r15, %r15
je .LBB1_30
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i.lr.ph
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movl $a, %r13d
leaq 64(%rsp), %r12
leaq 176(%rsp), %rbp
leaq 40(%rsp), %r14
xorl %ebx, %ebx
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_29: # %_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev.exit
# in Loop: Header=BB1_4 Depth=1
incq 8(%rsp) # 8-byte Folded Spill
movq $_ZTVSt15basic_streambufIcSt11char_traitsIcEE+16, 200(%rsp)
.cfi_escape 0x2e, 0x00
leaq 256(%rsp), %rdi
callq _ZNSt6localeD1Ev
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+16(%rip), %rax
movq %rax, 176(%rsp)
movq -24(%rax), %rax
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+24(%rip), %rcx
movq %rcx, 176(%rsp,%rax)
movq $0, 184(%rsp)
.cfi_escape 0x2e, 0x00
leaq 304(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq 576(%rsp), %rax
movq -24(%rax), %rax
movq 816(%rsp,%rax), %r15
addq $8000, %r13 # imm = 0x1F40
testq %r15, %r15
je .LBB1_30
.LBB1_4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# =>This Loop Header: Depth=1
# Child Loop BB1_17 Depth 2
cmpb $0, 56(%r15)
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_4 Depth=1
.Ltmp3:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp4:
# %bb.7: # %.noexc149
# in Loop: Header=BB1_4 Depth=1
movq (%r15), %rax
.Ltmp5:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp6:
.LBB1_8: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_4 Depth=1
.Ltmp7:
.cfi_escape 0x2e, 0x00
movsbl %al, %edx
leaq 576(%rsp), %rdi
movq %r12, %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp8:
# %bb.9: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
# in Loop: Header=BB1_4 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB1_11
# %bb.10: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
# in Loop: Header=BB1_4 Depth=1
cmpq $0, 72(%rsp)
je .LBB1_11
# %bb.15: # %.critedge202
# in Loop: Header=BB1_4 Depth=1
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movq %r12, %rsi
movl $24, %edx
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC1ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode
.Ltmp11:
# %bb.16: # %.preheader217.preheader
# in Loop: Header=BB1_4 Depth=1
movq %r13, %r15
.p2align 4, 0x90
.LBB1_17: # %.preheader217
# Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp13:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movq %r14, %rsi
callq _ZNSi10_M_extractIdEERSiRT_
.Ltmp14:
# %bb.18: # %_ZNSirsERd.exit
# in Loop: Header=BB1_17 Depth=2
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB1_27
# %bb.19: # in Loop: Header=BB1_17 Depth=2
movsd 40(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r15)
incl %ebx
addq $8, %r15
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_27: # in Loop: Header=BB1_4 Depth=1
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 176(%rsp)
movq -24(%rax), %rax
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+64(%rip), %rcx
movq %rcx, 176(%rsp,%rax)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+72(%rip), %rax
movq %rax, 192(%rsp)
movq $_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE+16, 200(%rsp)
movq 272(%rsp), %rdi
leaq 288(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_29
# %bb.28: # %.critedge.i.i.i.i.i
# in Loop: Header=BB1_4 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB1_29
.LBB1_11: # %.critedge.preheader
movq 576(%rsp), %rax
movq -24(%rax), %rax
movq 816(%rsp,%rax), %r12
testq %r12, %r12
je .LBB1_30
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i155.lr.ph
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
movl $h, %r13d
leaq 176(%rsp), %r14
leaq 40(%rsp), %r15
xorl %ebp, %ebp
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_46: # %_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev.exit172
# in Loop: Header=BB1_13 Depth=1
incq (%rsp) # 8-byte Folded Spill
movq $_ZTVSt15basic_streambufIcSt11char_traitsIcEE+16, 200(%rsp)
.cfi_escape 0x2e, 0x00
leaq 256(%rsp), %rdi
callq _ZNSt6localeD1Ev
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+16(%rip), %rax
movq %rax, 176(%rsp)
movq -24(%rax), %rax
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+24(%rip), %rcx
movq %rcx, 176(%rsp,%rax)
movq $0, 184(%rsp)
.cfi_escape 0x2e, 0x00
leaq 304(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq 576(%rsp), %rax
movq -24(%rax), %rax
movq 816(%rsp,%rax), %r12
addq $80, %r13
testq %r12, %r12
je .LBB1_30
.LBB1_13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i155
# =>This Loop Header: Depth=1
# Child Loop BB1_39 Depth 2
cmpb $0, 56(%r12)
je .LBB1_32
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_32: # in Loop: Header=BB1_13 Depth=1
.Ltmp16:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp17:
# %bb.33: # %.noexc160
# in Loop: Header=BB1_13 Depth=1
movq (%r12), %rax
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp19:
.LBB1_34: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i157
# in Loop: Header=BB1_13 Depth=1
.Ltmp20:
.cfi_escape 0x2e, 0x00
movsbl %al, %edx
leaq 576(%rsp), %rdi
leaq 64(%rsp), %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp21:
# %bb.35: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit163
# in Loop: Header=BB1_13 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB1_47
# %bb.36: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit163
# in Loop: Header=BB1_13 Depth=1
cmpq $0, 72(%rsp)
je .LBB1_47
# %bb.37: # %.critedge203
# in Loop: Header=BB1_13 Depth=1
.Ltmp23:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
leaq 64(%rsp), %rsi
movl $24, %edx
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC1ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode
.Ltmp24:
# %bb.38: # %.preheader211.preheader
# in Loop: Header=BB1_13 Depth=1
movq %r13, %r12
.p2align 4, 0x90
.LBB1_39: # %.preheader211
# Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %r15, %rsi
callq _ZNSi10_M_extractIdEERSiRT_
.Ltmp27:
# %bb.40: # %_ZNSirsERd.exit168
# in Loop: Header=BB1_39 Depth=2
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB1_44
# %bb.41: # in Loop: Header=BB1_39 Depth=2
movsd 40(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r12)
incl %ebp
addq $8, %r12
jmp .LBB1_39
.p2align 4, 0x90
.LBB1_44: # in Loop: Header=BB1_13 Depth=1
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 176(%rsp)
movq -24(%rax), %rax
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+64(%rip), %rcx
movq %rcx, 176(%rsp,%rax)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+72(%rip), %rax
movq %rax, 192(%rsp)
movq $_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE+16, 200(%rsp)
movq 272(%rsp), %rdi
leaq 288(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_46
# %bb.45: # %.critedge.i.i.i.i.i170
# in Loop: Header=BB1_13 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB1_46
.LBB1_47: # %.critedge2
leaq 592(%rsp), %rdi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp30:
# %bb.48: # %.noexc174
testq %rax, %rax
jne .LBB1_50
# %bb.49:
movq 576(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $576, %rdi # imm = 0x240
movl 608(%rsp,%rax), %esi
orl $4, %esi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp32:
.LBB1_50: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
movl %ebx, %eax
cltd
idivl 8(%rsp) # 4-byte Folded Reload
movl %eax, %r14d
movl %ebp, %eax
cltd
idivl (%rsp) # 4-byte Folded Reload
movl %eax, %r15d
movslq %ebx, %rsi
shlq $3, %rsi
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
.Ltmp34:
# %bb.51: # %_ZL16hipMallocManagedIdE10hipError_tPPT_mj.exit
movslq %ebp, %rsi
shlq $3, %rsi
.Ltmp36:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
.Ltmp37:
# %bb.52: # %_ZL16hipMallocManagedIdE10hipError_tPPT_mj.exit178
.Ltmp39:
movq 8(%rsp), %rbx # 8-byte Reload
movq (%rsp), %r12 # 8-byte Reload
leal (%rbx,%r12), %r13d
decl %r13d
leal (%r15,%r14), %ebp
decl %ebp
movl %ebp, %eax
imull %r13d, %eax
movslq %eax, %rsi
shlq $3, %rsi
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
.Ltmp40:
# %bb.53: # %_ZL16hipMallocManagedIdE10hipError_tPPT_mj.exit180.preheader
movq %rbx, %rcx
addl %r12d, %ebx
leal (%r15,%r14), %eax
movq %rax, 96(%rsp) # 8-byte Spill
movq 32(%rsp), %rax
cmpl $1, %ecx
# kill: def $ecx killed $ecx killed $rcx def $rcx
adcl $0, %ecx
movl %r14d, %edx
xorl %esi, %esi
movl $a, %edi
xorl %r8d, %r8d
jmp .LBB1_54
.p2align 4, 0x90
.LBB1_57: # %_ZL16hipMallocManagedIdE10hipError_tPPT_mj.exit180
# in Loop: Header=BB1_54 Depth=1
incq %r8
addl %r14d, %esi
addq $8000, %rdi # imm = 0x1F40
cmpq %rcx, %r8
je .LBB1_58
.LBB1_54: # %.preheader210
# =>This Loop Header: Depth=1
# Child Loop BB1_56 Depth 2
testl %r14d, %r14d
jle .LBB1_57
# %bb.55: # %.lr.ph
# in Loop: Header=BB1_54 Depth=1
movl %esi, %r9d
leaq (%rax,%r9,8), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_56: # Parent Loop BB1_54 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdi,%r10,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r9,%r10,8)
incq %r10
cmpq %r10, %rdx
jne .LBB1_56
jmp .LBB1_57
.LBB1_58: # %.preheader209
movq 24(%rsp), %rax
movq (%rsp), %rcx # 8-byte Reload
cmpl $1, %ecx
# kill: def $ecx killed $ecx killed $rcx def $rcx
adcl $0, %ecx
movl %r15d, %edx
xorl %esi, %esi
movl $h, %edi
xorl %r8d, %r8d
jmp .LBB1_59
.p2align 4, 0x90
.LBB1_62: # %._crit_edge257
# in Loop: Header=BB1_59 Depth=1
incq %r8
addl %r15d, %esi
addq $80, %rdi
cmpq %rcx, %r8
je .LBB1_63
.LBB1_59: # %.preheader208
# =>This Loop Header: Depth=1
# Child Loop BB1_61 Depth 2
testl %r15d, %r15d
jle .LBB1_62
# %bb.60: # %.lr.ph256
# in Loop: Header=BB1_59 Depth=1
movl %esi, %r9d
leaq (%rax,%r9,8), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_61: # Parent Loop BB1_59 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdi,%r10,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r9,%r10,8)
incq %r10
cmpq %r10, %rdx
jne .LBB1_61
jmp .LBB1_62
.LBB1_63:
leal -2(%rbx), %eax
leal 29(%rbx), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
incl %ecx
movq 96(%rsp), %rdx # 8-byte Reload
leal -2(%rdx), %eax
leal 29(%rdx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $5, %edi
incl %edi
shlq $32, %rdi
orq %rcx, %rdi
.Ltmp42:
.cfi_escape 0x2e, 0x00
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp43:
# %bb.64:
testl %eax, %eax
jne .LBB1_67
# %bb.65:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 60(%rsp)
movl %r14d, 56(%rsp)
movq (%rsp), %rax # 8-byte Reload
movl %eax, 52(%rsp)
movl %r15d, 48(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 52(%rsp), %rax
movq %rax, 216(%rsp)
leaq 48(%rsp), %rax
movq %rax, 224(%rsp)
.Ltmp44:
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp45:
# %bb.66: # %.noexc181
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
.Ltmp46:
.cfi_escape 0x2e, 0x10
leaq 176(%rsp), %r9
movl $_Z13convolution2DPdS_S_iiii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp47:
.LBB1_67:
.Ltmp48:
.cfi_escape 0x2e, 0x00
callq hipGetLastError
.Ltmp49:
# %bb.68:
testl %eax, %eax
jne .LBB1_69
# %bb.74:
.Ltmp52:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp53:
# %bb.75:
testl %eax, %eax
jne .LBB1_81
# %bb.76: # %.preheader207
cmpl $2, %ebx
jb .LBB1_91
# %bb.77: # %.preheader.lr.ph
cmpl $2, %ebp
movl $1, %ecx
movl $1, %eax
cmovgel %ebp, %eax
movq %rax, (%rsp) # 8-byte Spill
movl %r13d, %eax
movslq %ebp, %r13
cmpl $2, %eax
cmovgel %eax, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
shlq $3, %r13
xorl %r15d, %r15d
movl $-261, %r12d # imm = 0xFEFB
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_78: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_95 Depth 2
movq (%rsp), %rbx # 8-byte Reload
movq %r15, %rbp
cmpl $2, 96(%rsp) # 4-byte Folded Reload
jl .LBB1_79
.p2align 4, 0x90
.LBB1_95: # %_ZNSolsEPFRSt8ios_baseS0_E.exit
# Parent Loop BB1_78 Depth=1
# => This Inner Loop Header: Depth=2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl _ZSt4cout+24(%rcx), %edx
andl %r12d, %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $3, _ZSt4cout+8(%rax)
movq 16(%rsp), %rax
movsd (%rax,%rbp), %xmm0 # xmm0 = mem[0],zero
.Ltmp56:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp57:
# %bb.96: # %_ZNSolsEd.exit
# in Loop: Header=BB1_95 Depth=2
.Ltmp58:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp59:
# %bb.97: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_95 Depth=2
addq $8, %rbp
decq %rbx
jne .LBB1_95
.LBB1_79: # %._crit_edge262
# in Loop: Header=BB1_78 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_80
# %bb.84: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i191
# in Loop: Header=BB1_78 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_86
# %bb.85: # in Loop: Header=BB1_78 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB1_88
.p2align 4, 0x90
.LBB1_86: # in Loop: Header=BB1_78 Depth=1
.Ltmp61:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp62:
# %bb.87: # %.noexc196
# in Loop: Header=BB1_78 Depth=1
movq (%rbx), %rax
.Ltmp63:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp64:
.LBB1_88: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i193
# in Loop: Header=BB1_78 Depth=1
.Ltmp65:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp66:
# %bb.89: # %.noexc198
# in Loop: Header=BB1_78 Depth=1
.Ltmp67:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp68:
# %bb.90: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_78 Depth=1
incq %r14
addq %r13, %r15
cmpq 8(%rsp), %r14 # 8-byte Folded Reload
jne .LBB1_78
.LBB1_91: # %._crit_edge265
movq 32(%rsp), %rdi
.Ltmp70:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp71:
# %bb.92:
testl %eax, %eax
jne .LBB1_93
# %bb.101:
movq 24(%rsp), %rdi
.Ltmp74:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp75:
# %bb.102:
testl %eax, %eax
jne .LBB1_103
# %bb.105:
movq 16(%rsp), %rdi
.Ltmp78:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp79:
# %bb.106:
testl %eax, %eax
jne .LBB1_107
# %bb.109:
.Ltmp82:
.cfi_escape 0x2e, 0x00
callq hipDeviceReset
.Ltmp83:
# %bb.110:
testl %eax, %eax
jne .LBB1_111
# %bb.113:
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
.cfi_escape 0x2e, 0x00
leaq 576(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 832(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
movq 64(%rsp), %rdi
leaq 80(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_115
# %bb.114: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_115: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
xorl %eax, %eax
addq $1096, %rsp # imm = 0x448
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_30: # %.critedge._crit_edge.invoke
.cfi_def_cfa_offset 1152
.Ltmp90:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp91:
# %bb.31: # %.critedge._crit_edge.cont
.LBB1_80:
.Ltmp87:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp88:
# %bb.83: # %.noexc195
.LBB1_69:
movq stderr(%rip), %rbx
.Ltmp50:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp51:
# %bb.70:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
jmp .LBB1_71
.LBB1_81:
movq stderr(%rip), %rbx
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp55:
# %bb.82:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
jmp .LBB1_71
.LBB1_93:
movq stderr(%rip), %rbx
.Ltmp72:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp73:
# %bb.94:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
jmp .LBB1_71
.LBB1_103:
movq stderr(%rip), %rbx
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp77:
# %bb.104:
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
jmp .LBB1_71
.LBB1_107:
movq stderr(%rip), %rbx
.Ltmp80:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp81:
# %bb.108:
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
jmp .LBB1_71
.LBB1_111:
movq stderr(%rip), %rbx
.Ltmp84:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp85:
# %bb.112:
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %esi
.LBB1_71:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq exit
.LBB1_116:
.Ltmp41:
jmp .LBB1_117
.LBB1_73:
.Ltmp38:
jmp .LBB1_117
.LBB1_72:
.Ltmp35:
jmp .LBB1_117
.LBB1_20:
.Ltmp2:
movq %rax, %rbx
jmp .LBB1_119
.LBB1_122:
.Ltmp86:
jmp .LBB1_117
.LBB1_42:
.Ltmp25:
jmp .LBB1_117
.LBB1_24:
.Ltmp12:
jmp .LBB1_117
.LBB1_100: # %.loopexit.split-lp
.Ltmp89:
jmp .LBB1_117
.LBB1_21: # %.loopexit212
.Ltmp22:
jmp .LBB1_117
.LBB1_22: # %.loopexit.split-lp213.loopexit
.Ltmp9:
jmp .LBB1_117
.LBB1_23: # %.loopexit.split-lp213.loopexit.split-lp
.Ltmp92:
jmp .LBB1_117
.LBB1_99: # %.loopexit
.Ltmp69:
jmp .LBB1_117
.LBB1_43:
.Ltmp28:
jmp .LBB1_26
.LBB1_25:
.Ltmp15:
.LBB1_26: # %.loopexit.split-lp213
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev
jmp .LBB1_118
.LBB1_98:
.Ltmp60:
.LBB1_117: # %.loopexit.split-lp213
movq %rax, %rbx
.LBB1_118: # %.loopexit.split-lp213
.cfi_escape 0x2e, 0x00
leaq 576(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 832(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB1_119:
movq 64(%rsp), %rdi
leaq 80(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_121
# %bb.120: # %.critedge.i.i187
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_121: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit189
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp8-.Ltmp3 # Call between .Ltmp3 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp21-.Ltmp16 # Call between .Ltmp16 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin0 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp32-.Ltmp29 # Call between .Ltmp29 and .Ltmp32
.uleb128 .Ltmp92-.Lfunc_begin0 # jumps to .Ltmp92
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp53-.Ltmp42 # Call between .Ltmp42 and .Ltmp53
.uleb128 .Ltmp86-.Lfunc_begin0 # jumps to .Ltmp86
.byte 0 # On action: cleanup
.uleb128 .Ltmp56-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp59-.Ltmp56 # Call between .Ltmp56 and .Ltmp59
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp61-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp68-.Ltmp61 # Call between .Ltmp61 and .Ltmp68
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp70-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp83-.Ltmp70 # Call between .Ltmp70 and .Ltmp83
.uleb128 .Ltmp86-.Lfunc_begin0 # jumps to .Ltmp86
.byte 0 # On action: cleanup
.uleb128 .Ltmp90-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp91-.Ltmp90 # Call between .Ltmp90 and .Ltmp91
.uleb128 .Ltmp92-.Lfunc_begin0 # jumps to .Ltmp92
.byte 0 # On action: cleanup
.uleb128 .Ltmp87-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp88-.Ltmp87 # Call between .Ltmp87 and .Ltmp88
.uleb128 .Ltmp89-.Lfunc_begin0 # jumps to .Ltmp89
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp85-.Ltmp50 # Call between .Ltmp50 and .Ltmp85
.uleb128 .Ltmp86-.Lfunc_begin0 # jumps to .Ltmp86
.byte 0 # On action: cleanup
.uleb128 .Ltmp85-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Lfunc_end1-.Ltmp85 # Call between .Ltmp85 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13convolution2DPdS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type a,@object # @a
.bss
.globl a
.p2align 4, 0x0
a:
.zero 8000000
.size a, 8000000
.type h,@object # @h
.globl h
.p2align 4, 0x0
h:
.zero 800
.size h, 800
.type c,@object # @c
.globl c
.p2align 4, 0x0
c:
.zero 8000000
.size c, 8000000
.type _Z13convolution2DPdS_S_iiii,@object # @_Z13convolution2DPdS_S_iiii
.section .rodata,"a",@progbits
.globl _Z13convolution2DPdS_S_iiii
.p2align 3, 0x0
_Z13convolution2DPdS_S_iiii:
.quad _Z28__device_stub__convolution2DPdS_S_iiii
.size _Z13convolution2DPdS_S_iiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to launch convolution2D kernel (error code %s)!\n"
.size .L.str.1, 56
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to synchronize (error code %s)!\n"
.size .L.str.2, 40
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to free device vector a (error code %s)!\n"
.size .L.str.4, 49
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to free device vector h (error code %s)!\n"
.size .L.str.5, 49
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to free device vector c (error code %s)!\n"
.size .L.str.6, 49
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.7, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13convolution2DPdS_S_iiii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__convolution2DPdS_S_iiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z13convolution2DPdS_S_iiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13convolution2DPdS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULDC.64 UR8, c[0x0][0x180] ; /* 0x0000600000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, UR7, UR9, URZ ; /* 0x0000000907047290 */
/* 0x000fe4000fffe03f */
/*0060*/ UIADD3 UR5, UR6, UR8, URZ ; /* 0x0000000806057290 */
/* 0x000fe2000fffe03f */
/*0070*/ S2R R21, SR_CTAID.Y ; /* 0x0000000000157919 */
/* 0x000e620000002600 */
/*0080*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0090*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe2000fffe03f */
/*00a0*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00c0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06270 */
/*00d0*/ IMAD R21, R21, c[0x0][0x4], R2 ; /* 0x0000010015157a24 */
/* 0x002fca00078e0202 */
/*00e0*/ ISETP.GE.OR P0, PT, R21, UR5, P0 ; /* 0x0000000515007c0c */
/* 0x000fda0008706670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0120*/ ISETP.LE.AND P0, PT, R2, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x000fc80003f03270 */
/*0130*/ ISETP.GT.OR P0, PT, R2, c[0x0][0x180], !P0 ; /* 0x0000600002007a0c */
/* 0x000fe40004704670 */
/*0140*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fd6000001ff00 */
/*0150*/ @P0 BRA 0x7a0 ; /* 0x0000064000000947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff147624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R2, -R2, c[0x0][0x184], RZ ; /* 0x0000610002027a10 */
/* 0x000fe40007ffe1ff */
/*01a0*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */
/* 0x000fe400078ec0ff */
/*01b0*/ ISETP.GE.U32.AND P3, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f66070 */
/*01c0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*01d0*/ IADD3 R23, -R20, c[0x0][0x184], RZ ; /* 0x0000610014177a10 */
/* 0x000fc40007ffe1ff */
/*01e0*/ IMAD.MOV.U32 R26, RZ, RZ, R22.reuse ; /* 0x000000ffff1a7224 */
/* 0x100fe200078e0016 */
/*01f0*/ ISETP.NE.AND P4, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f85270 */
/*0200*/ IMAD.IADD R24, R21, 0x1, -R22 ; /* 0x0000000115187824 */
/* 0x000fe200078e0a16 */
/*0210*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fc600078e00ff */
/*0230*/ ISETP.GE.AND P5, PT, R22, c[0x0][0x180], PT ; /* 0x0000600016007a0c */
/* 0x000fe20003fa6270 */
/*0240*/ @!P3 BRA 0x4f0 ; /* 0x000002a00000b947 */
/* 0x00ffee0003800000 */
/*0250*/ ISETP.GE.AND P6, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003fc6270 */
/*0260*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R27, RZ, RZ, R23 ; /* 0x000000ffff1b7224 */
/* 0x000fc600078e0017 */
/*0280*/ ISETP.LT.OR P0, PT, R0.reuse, R25, !P6 ; /* 0x000000190000720c */
/* 0x040fe20007701670 */
/*0290*/ IMAD.IADD R5, R0, 0x1, -R25 ; /* 0x0000000100057824 */
/* 0x000fe400078e0a19 */
/*02a0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x000fe200078e00ff */
/*02b0*/ ISETP.GE.OR P0, PT, R24.reuse, c[0x0][0x178], P0 ; /* 0x00005e0018007a0c */
/* 0x040fe20000706670 */
/*02c0*/ IMAD R12, R24, c[0x0][0x17c], R5 ; /* 0x00005f00180c7a24 */
/* 0x000fe400078e0205 */
/*02d0*/ IMAD R16, R26, c[0x0][0x184], R25 ; /* 0x000061001a107a24 */
/* 0x000fe200078e0219 */
/*02e0*/ ISETP.GE.OR P2, PT, R5, c[0x0][0x17c], P0 ; /* 0x00005f0005007a0c */
/* 0x000fe20000746670 */
/*02f0*/ IMAD.WIDE R12, R12, R17, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0211 */
/*0300*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fd000078e0211 */
/*0310*/ @!P2 LDG.E.64 R6, [R12.64] ; /* 0x000000060c06a981 */
/* 0x000ea8000c1e1b00 */
/*0320*/ @!P2 LDG.E.64 R4, [R16.64] ; /* 0x000000061004a981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ ISETP.LE.OR P0, PT, R0.reuse, R25, !P6 ; /* 0x000000190000720c */
/* 0x040fe40007703670 */
/*0340*/ IADD3 R8, R0, -0x1, -R25 ; /* 0xffffffff00087810 */
/* 0x000fe40007ffe819 */
/*0350*/ IADD3 R9, R25, 0x2, RZ ; /* 0x0000000219097810 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.GE.OR P0, PT, R24, c[0x0][0x178], P0 ; /* 0x00005e0018007a0c */
/* 0x000fc40000706670 */
/*0370*/ ISETP.LT.OR P1, PT, R0.reuse, R9, !P6 ; /* 0x000000090000720c */
/* 0x040fe20007721670 */
/*0380*/ IMAD.IADD R9, R0, 0x1, -R9 ; /* 0x0000000100097824 */
/* 0x000fe200078e0a09 */
/*0390*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x17c], P0 ; /* 0x00005f0008007a0c */
/* 0x000fe40000706670 */
/*03a0*/ IADD3 R11, R25, 0x3, RZ ; /* 0x00000003190b7810 */
/* 0x000fe40007ffe0ff */
/*03b0*/ ISETP.GE.OR P1, PT, R24, c[0x0][0x178], P1 ; /* 0x00005e0018007a0c */
/* 0x000fc80000f26670 */
/*03c0*/ ISETP.GE.OR P1, PT, R9, c[0x0][0x17c], P1 ; /* 0x00005f0009007a0c */
/* 0x000fda0000f26670 */
/*03d0*/ @!P1 LDG.E.64 R8, [R16.64+0x10] ; /* 0x0000100610089981 */
/* 0x000ee2000c1e1b00 */
/*03e0*/ @!P2 DFMA R2, R6, R4, R2 ; /* 0x000000040602a22b */
/* 0x0070620000000002 */
/*03f0*/ ISETP.LT.OR P2, PT, R0.reuse, R11, !P6 ; /* 0x0000000b0000720c */
/* 0x040fe20007741670 */
/*0400*/ IMAD.IADD R11, R0, 0x1, -R11 ; /* 0x00000001000b7824 */
/* 0x000fe200078e0a0b */
/*0410*/ @!P0 LDG.E.64 R4, [R16.64+0x8] ; /* 0x0000080610048981 */
/* 0x001e64000c1e1b00 */
/*0420*/ ISETP.GE.OR P2, PT, R24, c[0x0][0x178], P2 ; /* 0x00005e0018007a0c */
/* 0x000fe40001746670 */
/*0430*/ @!P0 LDG.E.64 R6, [R12.64+-0x8] ; /* 0xfffff8060c068981 */
/* 0x000e64000c1e1b00 */
/*0440*/ ISETP.GE.OR P2, PT, R11, c[0x0][0x17c], P2 ; /* 0x00005f000b007a0c */
/* 0x000fc40001746670 */
/*0450*/ @!P1 LDG.E.64 R10, [R12.64+-0x10] ; /* 0xfffff0060c0a9981 */
/* 0x000ef6000c1e1b00 */
/*0460*/ @!P2 LDG.E.64 R14, [R16.64+0x18] ; /* 0x00001806100ea981 */
/* 0x000ea8000c1e1b00 */
/*0470*/ @!P2 LDG.E.64 R18, [R12.64+-0x18] ; /* 0xffffe8060c12a981 */
/* 0x000ea2000c1e1b00 */
/*0480*/ IADD3 R27, R27, -0x4, RZ ; /* 0xfffffffc1b1b7810 */
/* 0x000fc40007ffe0ff */
/*0490*/ IADD3 R25, R25, 0x4, RZ ; /* 0x0000000419197810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ @!P0 DFMA R2, R4, R6, R2 ; /* 0x000000060402822b */
/* 0x002ee20000000002 */
/*04b0*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fca0003f05270 */
/*04c0*/ @!P1 DFMA R2, R8, R10, R2 ; /* 0x0000000a0802922b */
/* 0x008e8c0000000002 */
/*04d0*/ @!P2 DFMA R2, R14, R18, R2 ; /* 0x000000120e02a22b */
/* 0x0040640000000002 */
/*04e0*/ @P0 BRA 0x280 ; /* 0xfffffd9000000947 */
/* 0x000fea000383ffff */
/*04f0*/ @!P4 BRA 0x790 ; /* 0x000002900000c947 */
/* 0x000fea0003800000 */
/*0500*/ ISETP.GE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f06270 */
/*0510*/ IMAD.IADD R5, R0.reuse, 0x1, -R25.reuse ; /* 0x0000000100057824 */
/* 0x140fe200078e0a19 */
/*0520*/ BSSY B0, 0x610 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fe200078e00ff */
/*0540*/ ISETP.LT.OR P1, PT, R0, R25, !P0 ; /* 0x000000190000720c */
/* 0x000fe20004721670 */
/*0550*/ IMAD R6, R26, c[0x0][0x184], R25 ; /* 0x000061001a067a24 */
/* 0x000fe200078e0219 */
/*0560*/ ISETP.NE.AND P2, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe40003f45270 */
/*0570*/ ISETP.GE.OR P1, PT, R24, c[0x0][0x178], P1 ; /* 0x00005e0018007a0c */
/* 0x000fe20000f26670 */
/*0580*/ IMAD.WIDE R6, R6, R4, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc600078e0204 */
/*0590*/ ISETP.GE.OR P1, PT, R5, c[0x0][0x17c], P1 ; /* 0x00005f0005007a0c */
/* 0x000fe20000f26670 */
/*05a0*/ IMAD R5, R24, c[0x0][0x17c], R5 ; /* 0x00005f0018057a24 */
/* 0x000fc800078e0205 */
/*05b0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fd000078e0204 */
/*05c0*/ @P1 BRA 0x600 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea8000c1e1b00 */
/*05e0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x000ea4000c1e1b00 */
/*05f0*/ DFMA R2, R8, R10, R2 ; /* 0x0000000a0802722b */
/* 0x00628c0000000002 */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0610*/ @!P2 BRA 0x790 ; /* 0x000001700000a947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.LE.OR P1, PT, R0.reuse, R25, !P0 ; /* 0x000000190000720c */
/* 0x040fe20004723670 */
/*0630*/ BSSY B0, 0x6d0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0640*/ IADD3 R8, R0, -0x1, -R25 ; /* 0xffffffff00087810 */
/* 0x002fe40007ffe819 */
/*0650*/ ISETP.GE.OR P1, PT, R24, c[0x0][0x178], P1 ; /* 0x00005e0018007a0c */
/* 0x000fc40000f26670 */
/*0660*/ ISETP.NE.AND P2, PT, R20, 0x2, PT ; /* 0x000000021400780c */
/* 0x000fe40003f45270 */
/*0670*/ ISETP.GE.OR P1, PT, R8, c[0x0][0x17c], P1 ; /* 0x00005f0008007a0c */
/* 0x000fda0000f26670 */
/*0680*/ @P1 BRA 0x6c0 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080606087981 */
/* 0x000ee8000c1e1b00 */
/*06a0*/ LDG.E.64 R10, [R4.64+-0x8] ; /* 0xfffff806040a7981 */
/* 0x000ee4000c1e1b00 */
/*06b0*/ DFMA R2, R8, R10, R2 ; /* 0x0000000a0802722b */
/* 0x00c28c0000000002 */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ @!P2 BRA 0x790 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*06e0*/ IADD3 R25, R25, 0x2, RZ ; /* 0x0000000219197810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ BSSY B0, 0x790 ; /* 0x0000009000007945 */
/* 0x000fe60003800000 */
/*0700*/ ISETP.LT.OR P0, PT, R0.reuse, R25, !P0 ; /* 0x000000190000720c */
/* 0x040fe20004701670 */
/*0710*/ IMAD.IADD R25, R0, 0x1, -R25 ; /* 0x0000000100197824 */
/* 0x000fc600078e0a19 */
/*0720*/ ISETP.GE.OR P0, PT, R24, c[0x0][0x178], P0 ; /* 0x00005e0018007a0c */
/* 0x000fc80000706670 */
/*0730*/ ISETP.GE.OR P0, PT, R25, c[0x0][0x17c], P0 ; /* 0x00005f0019007a0c */
/* 0x000fda0000706670 */
/*0740*/ @P0 BRA 0x780 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0750*/ LDG.E.64 R6, [R6.64+0x10] ; /* 0x0000100606067981 */
/* 0x000ee8000c1e1b00 */
/*0760*/ LDG.E.64 R4, [R4.64+-0x10] ; /* 0xfffff00604047981 */
/* 0x000ee4000c1e1b00 */
/*0770*/ DFMA R2, R6, R4, R2 ; /* 0x000000040602722b */
/* 0x00c4cc0000000002 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ @!P5 BRA 0x1e0 ; /* 0xfffffa400000d947 */
/* 0x000fea000383ffff */
/*07a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x004fe400078e00ff */
/*07b0*/ IMAD R4, R21, UR4, R0 ; /* 0x0000000415047c24 */
/* 0x000fc8000f8e0200 */
/*07c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*07d0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x00afe8000c101b06 */
/*07e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13convolution2DPdS_S_iiii
.globl _Z13convolution2DPdS_S_iiii
.p2align 8
.type _Z13convolution2DPdS_S_iiii,@function
_Z13convolution2DPdS_S_iiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x1c
s_load_b32 s13, s[0:1], 0x24
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_add_i32 s5, s12, s13
s_mov_b32 s4, exec_lo
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_14
s_load_b32 s2, s[2:3], 0xc
s_clause 0x1
s_load_b32 s14, s[0:1], 0x18
s_load_b32 s16, s[0:1], 0x20
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_add_i32 s2, s14, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_cmp_lt_i32 s16, 1
s_cbranch_scc1 .LBB0_12
s_load_b128 s[8:11], s[0:1], 0x0
v_mul_lo_u32 v0, s12, v2
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_cmp_gt_i32 s13, 0
s_mov_b32 s7, 0
s_cselect_b32 s15, -1, 0
s_mov_b32 s17, 0
s_mov_b32 s18, 0
s_branch .LBB0_5
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_subrev_nc_u32_e32 v0, s12, v0
s_add_i32 s18, s18, 1
s_add_i32 s17, s17, s13
s_cmp_eq_u32 s18, s16
s_cbranch_scc1 .LBB0_13
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_4
v_subrev_nc_u32_e32 v5, s18, v2
s_mov_b32 s6, s17
s_mov_b32 s19, s13
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s14, v5
v_mov_b32_e32 v5, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s20
v_add_nc_u32_e32 v5, -1, v5
s_add_i32 s19, s19, -1
s_add_i32 s6, s6, 1
s_cmp_eq_u32 s19, 0
s_cbranch_scc1 .LBB0_4
.LBB0_9:
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz .LBB0_8
v_cmp_lt_i32_e64 s3, -1, v5
v_cmp_gt_i32_e64 s4, s12, v5
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v6, v0, v5
s_lshl_b64 s[22:23], s[6:7], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s22, s10, s22
s_addc_u32 s23, s11, s23
v_ashrrev_i32_e32 v7, 31, v6
s_load_b64 s[22:23], s[22:23], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_u32 v6, s3, s8, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s3, s9, v7, s3
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], v[6:7], s[22:23], v[3:4]
s_branch .LBB0_7
.LBB0_12:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_13:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v2, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13convolution2DPdS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13convolution2DPdS_S_iiii, .Lfunc_end0-_Z13convolution2DPdS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13convolution2DPdS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z13convolution2DPdS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ void gpu_bottomUpMerge(long* source, long* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__global__ void gpu_mergesort(long* source, long* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
} | .file "tmpxft_000dd33b_00000000-6_gpu_mergesort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17gpu_bottomUpMergePlS_lll
.type _Z17gpu_bottomUpMergePlS_lll, @function
_Z17gpu_bottomUpMergePlS_lll:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17gpu_bottomUpMergePlS_lll, .-_Z17gpu_bottomUpMergePlS_lll
.globl _Z6getIdxP4dim3S0_
.type _Z6getIdxP4dim3S0_, @function
_Z6getIdxP4dim3S0_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z6getIdxP4dim3S0_, .-_Z6getIdxP4dim3S0_
.globl _Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_
.type _Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_, @function
_Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13gpu_mergesortPlS_lllP4dim3S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_, .-_Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_
.globl _Z13gpu_mergesortPlS_lllP4dim3S1_
.type _Z13gpu_mergesortPlS_lllP4dim3S1_, @function
_Z13gpu_mergesortPlS_lllP4dim3S1_:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13gpu_mergesortPlS_lllP4dim3S1_, .-_Z13gpu_mergesortPlS_lllP4dim3S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13gpu_mergesortPlS_lllP4dim3S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_mergesortPlS_lllP4dim3S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ void gpu_bottomUpMerge(long* source, long* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__global__ void gpu_mergesort(long* source, long* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void gpu_bottomUpMerge(long* source, long* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__global__ void gpu_mergesort(long* source, long* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void gpu_bottomUpMerge(long* source, long* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__global__ void gpu_mergesort(long* source, long* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpu_mergesortPlS_lllP4dim3S1_
.globl _Z13gpu_mergesortPlS_lllP4dim3S1_
.p2align 8
.type _Z13gpu_mergesortPlS_lllP4dim3S1_,@function
_Z13gpu_mergesortPlS_lllP4dim3S1_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b256 s[4:11], s[0:1], 0x10
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x4
s_clause 0x1
s_load_b32 s12, s[10:11], 0x8
s_load_b64 s[10:11], s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_mul_i32 s2, s2, s3
s_mul_hi_u32 s3, s8, s6
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s2, s12, v[1:2]
v_bfe_u32 v3, v0, 10, 10
s_mul_i32 s2, s8, s6
v_mul_lo_u32 v1, v2, s11
v_and_b32_e32 v2, 0x3ff, v0
v_cmp_gt_i64_e64 s11, s[8:9], 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v1, v3
v_mad_u64_u32 v[4:5], null, v3, s10, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s2, v4, 0
s_mul_i32 s2, s8, s7
s_add_i32 s2, s3, s2
s_mul_i32 s3, s9, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s2, v4, v[1:2]
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v5
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1]
s_and_b32 s11, s11, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s12, s11
s_cbranch_execz .LBB0_15
v_mad_u64_u32 v[4:5], null, s10, v3, v[2:3]
s_mul_i32 s10, s8, s6
s_mul_hi_u32 s11, s8, s6
s_mul_i32 s16, s9, s6
s_load_b128 s[12:15], s[0:1], 0x0
v_cmp_gt_i64_e64 s1, s[6:7], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s10, v4, 0
s_mul_i32 s10, s8, s7
s_add_i32 s10, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_i32 s10, s10, s16
s_mov_b32 s16, 0
v_mad_u64_u32 v[5:6], null, s10, v4, v[3:4]
s_ashr_i64 s[10:11], s[6:7], 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v3, v5
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s14, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
s_lshl_b64 s[14:15], s[6:7], 3
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s17
.LBB0_3:
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
v_cmp_le_i64_e32 vcc_lo, s[4:5], v[4:5]
v_cmp_ge_i64_e64 s0, s[2:3], s[8:9]
v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s14
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
s_and_b32 s0, exec_lo, s0
s_or_b32 s16, s0, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_15
.LBB0_4:
v_add_co_u32 v4, vcc_lo, v0, s6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_3
v_add_co_u32 v6, vcc_lo, v0, s10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
v_cmp_gt_i64_e64 s0, s[4:5], v[4:5]
v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[6:7]
s_mov_b32 s17, 0
v_mov_b32_e32 v11, v3
v_cndmask_b32_e64 v9, s5, v5, s0
v_cndmask_b32_e64 v8, s4, v4, s0
v_dual_mov_b32 v10, v2 :: v_dual_cndmask_b32 v7, s5, v7
v_cndmask_b32_e32 v6, s4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v6
s_branch .LBB0_7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s18
v_add_co_u32 v0, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v10, s0, v10, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v11, s0, 0, v11, s0
v_cmp_ge_i64_e32 vcc_lo, v[0:1], v[8:9]
v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
s_or_b32 s17, vcc_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_2
.LBB0_7:
s_mov_b32 s19, -1
s_mov_b32 s0, 0
s_mov_b32 s18, exec_lo
v_cmpx_lt_i64_e64 v[12:13], v[6:7]
s_cbranch_execz .LBB0_11
v_cmp_ge_i64_e64 s0, v[14:15], v[8:9]
s_mov_b32 s20, 0
s_mov_b32 s19, exec_lo
v_cmpx_lt_i64_e64 v[14:15], v[8:9]
s_cbranch_execz .LBB0_10
v_lshlrev_b64 v[16:17], 3, v[12:13]
v_lshlrev_b64 v[18:19], 3, v[14:15]
s_or_b32 s0, s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v16, vcc_lo, s12, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v18, vcc_lo, s12, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo
s_clause 0x1
global_load_b64 v[16:17], v[16:17], off
global_load_b64 v[18:19], v[18:19], off
s_waitcnt vmcnt(0)
v_cmp_ge_i64_e32 vcc_lo, v[16:17], v[18:19]
s_and_b32 s20, vcc_lo, exec_lo
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_not1_b32 s19, s20, exec_lo
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s18, s19
s_cbranch_execz .LBB0_13
v_lshlrev_b64 v[16:17], 3, v[14:15]
s_and_not1_b32 s0, s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s12, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s13, v17, vcc_lo
global_load_b64 v[18:19], v[16:17], off
v_add_co_u32 v16, vcc_lo, v14, 1
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v15, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[10:11], v[18:19], off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s18, s0
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[16:17], 3, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s12, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s13, v17, vcc_lo
v_add_co_u32 v12, vcc_lo, v12, 1
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
global_load_b64 v[18:19], v[16:17], off
v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
s_waitcnt vmcnt(0)
global_store_b64 v[10:11], v[18:19], off
s_branch .LBB0_6
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpu_mergesortPlS_lllP4dim3S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpu_mergesortPlS_lllP4dim3S1_, .Lfunc_end0-_Z13gpu_mergesortPlS_lllP4dim3S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpu_mergesortPlS_lllP4dim3S1_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z13gpu_mergesortPlS_lllP4dim3S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void gpu_bottomUpMerge(long* source, long* dest, long start, long middle, long end) {
long i = start;
long j = middle;
for (long k = start; k < end; k++) {
if (i < middle && (j >= end || source[i] < source[j])) {
dest[k] = source[i];
i++;
} else {
dest[k] = source[j];
j++;
}
}
}
__device__ unsigned int getIdx(dim3* threads, dim3* blocks) {
int x;
return threadIdx.x +
threadIdx.y * (x = threads->x) +
threadIdx.z * (x *= threads->y) +
blockIdx.x * (x *= threads->z) +
blockIdx.y * (x *= blocks->z) +
blockIdx.z * (x *= blocks->y);
}
__global__ void gpu_mergesort(long* source, long* dest, long size, long width, long slices, dim3* threads, dim3* blocks) {
unsigned int idx = getIdx(threads, blocks);
long start = width*idx*slices,
middle,
end;
for (long slice = 0; slice < slices; slice++) {
if (start >= size)
break;
middle = min(start + (width >> 1), size);
end = min(start + width, size);
gpu_bottomUpMerge(source, dest, start, middle, end);
start += width;
}
} | .text
.file "gpu_mergesort.hip"
.globl _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_ # -- Begin function _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.p2align 4, 0x90
.type _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_,@function
_Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_: # @_Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13gpu_mergesortPlS_lllP4dim3S1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_, .Lfunc_end0-_Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_mergesortPlS_lllP4dim3S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpu_mergesortPlS_lllP4dim3S1_,@object # @_Z13gpu_mergesortPlS_lllP4dim3S1_
.section .rodata,"a",@progbits
.globl _Z13gpu_mergesortPlS_lllP4dim3S1_
.p2align 3, 0x0
_Z13gpu_mergesortPlS_lllP4dim3S1_:
.quad _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.size _Z13gpu_mergesortPlS_lllP4dim3S1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13gpu_mergesortPlS_lllP4dim3S1_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpu_mergesortPlS_lllP4dim3S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dd33b_00000000-6_gpu_mergesort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17gpu_bottomUpMergePlS_lll
.type _Z17gpu_bottomUpMergePlS_lll, @function
_Z17gpu_bottomUpMergePlS_lll:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17gpu_bottomUpMergePlS_lll, .-_Z17gpu_bottomUpMergePlS_lll
.globl _Z6getIdxP4dim3S0_
.type _Z6getIdxP4dim3S0_, @function
_Z6getIdxP4dim3S0_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z6getIdxP4dim3S0_, .-_Z6getIdxP4dim3S0_
.globl _Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_
.type _Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_, @function
_Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13gpu_mergesortPlS_lllP4dim3S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_, .-_Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_
.globl _Z13gpu_mergesortPlS_lllP4dim3S1_
.type _Z13gpu_mergesortPlS_lllP4dim3S1_, @function
_Z13gpu_mergesortPlS_lllP4dim3S1_:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z13gpu_mergesortPlS_lllP4dim3S1_PlS_lllP4dim3S1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13gpu_mergesortPlS_lllP4dim3S1_, .-_Z13gpu_mergesortPlS_lllP4dim3S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13gpu_mergesortPlS_lllP4dim3S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_mergesortPlS_lllP4dim3S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_mergesort.hip"
.globl _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_ # -- Begin function _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.p2align 4, 0x90
.type _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_,@function
_Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_: # @_Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13gpu_mergesortPlS_lllP4dim3S1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_, .Lfunc_end0-_Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_mergesortPlS_lllP4dim3S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpu_mergesortPlS_lllP4dim3S1_,@object # @_Z13gpu_mergesortPlS_lllP4dim3S1_
.section .rodata,"a",@progbits
.globl _Z13gpu_mergesortPlS_lllP4dim3S1_
.p2align 3, 0x0
_Z13gpu_mergesortPlS_lllP4dim3S1_:
.quad _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.size _Z13gpu_mergesortPlS_lllP4dim3S1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13gpu_mergesortPlS_lllP4dim3S1_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_mergesortPlS_lllP4dim3S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpu_mergesortPlS_lllP4dim3S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void MatrixMulKernel(float* M, float* N, float* P, int Width) {
//We need to iterate with tiles - starting point and end needed for tiles
int Mstart=Width*BLOCK_SIZE*blockIdx.y;//rows of matrix M
int Mend=Mstart+Width-1;
int mstep=BLOCK_SIZE;
int Nstart=BLOCK_SIZE*blockIdx.x;//cols of matrix N
int nstep=BLOCK_SIZE*Width;
float temp=0;
//loop through tiles
for(int m=Mstart,n=Nstart;m<Mend;m+=mstep,n+=nstep){
__shared__ float Ms[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Ns[BLOCK_SIZE][BLOCK_SIZE];
Ms[threadIdx.y][threadIdx.x]=M[m+Width*threadIdx.y+threadIdx.x];
Ns[threadIdx.y][threadIdx.x]=N[n+Width*threadIdx.y+threadIdx.x];
__syncthreads();
for (int i = 0; i < BLOCK_SIZE; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();
}
P[Width * BLOCK_SIZE * blockIdx.y + BLOCK_SIZE * blockIdx.x + Width * threadIdx.y + threadIdx.x] = temp;
} | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fe200000001ff */
/*0040*/ USHF.L.U32 UR4, UR4, 0x5, URZ ; /* 0x0000000504047899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0080*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ea20000002200 */
/*0090*/ IMAD R3, R5, UR4, RZ ; /* 0x0000000405037c24 */
/* 0x001fca000f8e02ff */
/*00a0*/ IADD3 R18, R3, c[0x0][0x178], RZ ; /* 0x00005e0003127a10 */
/* 0x000fe40007ffe0ff */
/*00b0*/ LEA R0, R7, R0, 0x5 ; /* 0x0000000007007211 */
/* 0x002fe400078e28ff */
/*00c0*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fc60007ffe0ff */
/*00d0*/ IMAD R0, R9, c[0x0][0x178], R0 ; /* 0x00005e0009007a24 */
/* 0x004fe200078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, R18, PT ; /* 0x000000120300720c */
/* 0x000fc80003f06270 */
/*00f0*/ IADD3 R0, R3, R0, RZ ; /* 0x0000000003007210 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE.U32 R20, R0, R21, c[0x0][0x170] ; /* 0x00005c0000147625 */
/* 0x000fc800078e0015 */
/*0110*/ @P0 MOV R13, RZ ; /* 0x000000ff000d0202 */
/* 0x000fe20000000f00 */
/*0120*/ @P0 BRA 0x720 ; /* 0x000005f000000947 */
/* 0x000fea0003800000 */
/*0130*/ S2R R19, SR_TID.Y ; /* 0x0000000000137919 */
/* 0x000e220000002200 */
/*0140*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fc60000000f00 */
/*0150*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0160*/ LEA R5, R5, R19, 0x5 ; /* 0x0000001305057211 */
/* 0x001fe200078e28ff */
/*0170*/ IMAD R16, R19.reuse, c[0x0][0x178], R2 ; /* 0x00005e0013107a24 */
/* 0x042fe200078e0202 */
/*0180*/ SHF.L.U32 R19, R19, 0x7, RZ ; /* 0x0000000713137819 */
/* 0x000fc600000006ff */
/*0190*/ IMAD R0, R5, c[0x0][0x178], R2 ; /* 0x00005e0005007a24 */
/* 0x000fe200078e0202 */
/*01a0*/ LEA R16, R7, R16, 0x5 ; /* 0x0000001007107211 */
/* 0x000fe400078e28ff */
/*01b0*/ LEA R17, R2, R19, 0x2 ; /* 0x0000001302117211 */
/* 0x000fe400078e10ff */
/*01c0*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fd400000001ff */
/*01d0*/ IMAD.WIDE.U32 R8, R0, R15, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e000f */
/*01e0*/ IMAD.WIDE.U32 R14, R16.reuse, R15, c[0x0][0x168] ; /* 0x00005a00100e7625 */
/* 0x040fe200078e000f */
/*01f0*/ LDG.E R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000eaa000c1e1900 */
/*0200*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee2000c1e1900 */
/*0210*/ IADD3 R3, R3, 0x20, RZ ; /* 0x0000002003037810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R16, R16, UR4, RZ ; /* 0x0000000410107c10 */
/* 0x000fe4000fffe0ff */
/*0230*/ ISETP.GE.AND P0, PT, R3, R18, PT ; /* 0x000000120300720c */
/* 0x000fc40003f06270 */
/*0240*/ IADD3 R0, R0, 0x20, RZ ; /* 0x0000002000007810 */
/* 0x000fe20007ffe0ff */
/*0250*/ STS [R17], R12 ; /* 0x0000000c11007388 */
/* 0x004fe80000000800 */
/*0260*/ STS [R17+0x1000], R14 ; /* 0x0010000e11007388 */
/* 0x008fe80000000800 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ LDS R23, [R2.X4+0x1000] ; /* 0x0010000002177984 */
/* 0x000fe80000004800 */
/*0290*/ LDS.128 R4, [R19] ; /* 0x0000000013047984 */
/* 0x000e280000000c00 */
/*02a0*/ LDS R28, [R2.X4+0x1080] ; /* 0x00108000021c7984 */
/* 0x000e680000004800 */
/*02b0*/ LDS R29, [R2.X4+0x1100] ; /* 0x00110000021d7984 */
/* 0x000ea80000004800 */
/*02c0*/ LDS R26, [R2.X4+0x1180] ; /* 0x00118000021a7984 */
/* 0x000ee80000004800 */
/*02d0*/ LDS R27, [R2.X4+0x1200] ; /* 0x00120000021b7984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS.128 R8, [R19+0x10] ; /* 0x0000100013087984 */
/* 0x000f280000000c00 */
/*02f0*/ LDS R24, [R2.X4+0x1280] ; /* 0x0012800002187984 */
/* 0x000f680000004800 */
/*0300*/ LDS R25, [R2.X4+0x1300] ; /* 0x0013000002197984 */
/* 0x000f680000004800 */
/*0310*/ LDS R22, [R2.X4+0x1380] ; /* 0x0013800002167984 */
/* 0x000f620000004800 */
/*0320*/ FFMA R4, R23, R4, R13 ; /* 0x0000000417047223 */
/* 0x001fc6000000000d */
/*0330*/ LDS R23, [R2.X4+0x1400] ; /* 0x0014000002177984 */
/* 0x000fe20000004800 */
/*0340*/ FFMA R5, R28, R5, R4 ; /* 0x000000051c057223 */
/* 0x002fc60000000004 */
/*0350*/ LDS.128 R12, [R19+0x20] ; /* 0x00002000130c7984 */
/* 0x000e220000000c00 */
/*0360*/ FFMA R5, R29, R6, R5 ; /* 0x000000061d057223 */
/* 0x004fc60000000005 */
/*0370*/ LDS R28, [R2.X4+0x1480] ; /* 0x00148000021c7984 */
/* 0x000e620000004800 */
/*0380*/ FFMA R5, R26, R7, R5 ; /* 0x000000071a057223 */
/* 0x008fc60000000005 */
/*0390*/ LDS R29, [R2.X4+0x1500] ; /* 0x00150000021d7984 */
/* 0x000ea80000004800 */
/*03a0*/ LDS R26, [R2.X4+0x1680] ; /* 0x00168000021a7984 */
/* 0x000fe20000004800 */
/*03b0*/ FFMA R5, R27, R8, R5 ; /* 0x000000081b057223 */
/* 0x010fc60000000005 */
/*03c0*/ LDS R27, [R2.X4+0x1700] ; /* 0x00170000021b7984 */
/* 0x000fe20000004800 */
/*03d0*/ FFMA R5, R24, R9, R5 ; /* 0x0000000918057223 */
/* 0x020fc60000000005 */
/*03e0*/ LDS R24, [R2.X4+0x1580] ; /* 0x0015800002187984 */
/* 0x000ee20000004800 */
/*03f0*/ FFMA R10, R25, R10, R5 ; /* 0x0000000a190a7223 */
/* 0x000fc60000000005 */
/*0400*/ LDS R25, [R2.X4+0x1600] ; /* 0x0016000002197984 */
/* 0x000fe20000004800 */
/*0410*/ FFMA R10, R22, R11, R10 ; /* 0x0000000b160a7223 */
/* 0x000fc6000000000a */
/*0420*/ LDS.128 R4, [R19+0x30] ; /* 0x0000300013047984 */
/* 0x000f280000000c00 */
/*0430*/ LDS R22, [R2.X4+0x1780] ; /* 0x0017800002167984 */
/* 0x000f620000004800 */
/*0440*/ FFMA R10, R23, R12, R10 ; /* 0x0000000c170a7223 */
/* 0x001fc6000000000a */
/*0450*/ LDS R23, [R2.X4+0x1800] ; /* 0x0018000002177984 */
/* 0x000fe20000004800 */
/*0460*/ FFMA R10, R28, R13, R10 ; /* 0x0000000d1c0a7223 */
/* 0x002fc6000000000a */
/*0470*/ LDS R28, [R2.X4+0x1a80] ; /* 0x001a8000021c7984 */
/* 0x000fe20000004800 */
/*0480*/ FFMA R14, R29, R14, R10 ; /* 0x0000000e1d0e7223 */
/* 0x004fc6000000000a */
/*0490*/ LDS.128 R8, [R19+0x40] ; /* 0x0000400013087984 */
/* 0x000e280000000c00 */
/*04a0*/ LDS R29, [R2.X4+0x1900] ; /* 0x00190000021d7984 */
/* 0x000fe20000004800 */
/*04b0*/ FFMA R14, R24, R15, R14 ; /* 0x0000000f180e7223 */
/* 0x008fc6000000000e */
/*04c0*/ LDS R24, [R2.X4+0x1880] ; /* 0x0018800002187984 */
/* 0x000e620000004800 */
/*04d0*/ FFMA R4, R25, R4, R14 ; /* 0x0000000419047223 */
/* 0x010fc6000000000e */
/*04e0*/ LDS R25, [R2.X4+0x1a00] ; /* 0x001a000002197984 */
/* 0x000fe20000004800 */
/*04f0*/ FFMA R4, R26, R5, R4 ; /* 0x000000051a047223 */
/* 0x000fc60000000004 */
/*0500*/ LDS R26, [R2.X4+0x1980] ; /* 0x00198000021a7984 */
/* 0x000ea20000004800 */
/*0510*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc60000000004 */
/*0520*/ LDS.128 R12, [R19+0x50] ; /* 0x00005000130c7984 */
/* 0x000ee20000000c00 */
/*0530*/ FFMA R4, R22, R7, R4 ; /* 0x0000000716047223 */
/* 0x020fc60000000004 */
/*0540*/ LDS R27, [R2.X4+0x1b00] ; /* 0x001b0000021b7984 */
/* 0x000f280000004800 */
/*0550*/ LDS R22, [R2.X4+0x1b80] ; /* 0x001b800002167984 */
/* 0x000f620000004800 */
/*0560*/ FFMA R4, R23, R8, R4 ; /* 0x0000000817047223 */
/* 0x001fc60000000004 */
/*0570*/ LDS R23, [R2.X4+0x1c00] ; /* 0x001c000002177984 */
/* 0x000fe20000004800 */
/*0580*/ FFMA R4, R24, R9, R4 ; /* 0x0000000918047223 */
/* 0x002fc60000000004 */
/*0590*/ LDS R24, [R2.X4+0x1c80] ; /* 0x001c800002187984 */
/* 0x000fe20000004800 */
/*05a0*/ FFMA R10, R29, R10, R4 ; /* 0x0000000a1d0a7223 */
/* 0x000fc60000000004 */
/*05b0*/ LDS.128 R4, [R19+0x60] ; /* 0x0000600013047984 */
/* 0x000e220000000c00 */
/*05c0*/ FFMA R10, R26, R11, R10 ; /* 0x0000000b1a0a7223 */
/* 0x004fc8000000000a */
/*05d0*/ FFMA R10, R25, R12, R10 ; /* 0x0000000c190a7223 */
/* 0x008fe4000000000a */
/*05e0*/ LDS R25, [R2.X4+0x1d00] ; /* 0x001d000002197984 */
/* 0x000e640000004800 */
/*05f0*/ FFMA R10, R28, R13, R10 ; /* 0x0000000d1c0a7223 */
/* 0x000fe4000000000a */
/*0600*/ LDS R12, [R2.X4+0x1d80] ; /* 0x001d8000020c7984 */
/* 0x000ea40000004800 */
/*0610*/ FFMA R14, R27, R14, R10 ; /* 0x0000000e1b0e7223 */
/* 0x010fe4000000000a */
/*0620*/ LDS R13, [R2.X4+0x1e00] ; /* 0x001e0000020d7984 */
/* 0x000fe40000004800 */
/*0630*/ FFMA R26, R22, R15, R14 ; /* 0x0000000f161a7223 */
/* 0x020fc4000000000e */
/*0640*/ LDS.128 R8, [R19+0x70] ; /* 0x0000700013087984 */
/* 0x000ee80000000c00 */
/*0650*/ LDS R22, [R2.X4+0x1e80] ; /* 0x001e800002167984 */
/* 0x000f280000004800 */
/*0660*/ LDS R15, [R2.X4+0x1f00] ; /* 0x001f0000020f7984 */
/* 0x000f680000004800 */
/*0670*/ LDS R14, [R2.X4+0x1f80] ; /* 0x001f8000020e7984 */
/* 0x000f620000004800 */
/*0680*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x001fc8000000001a */
/*0690*/ FFMA R4, R24, R5, R4 ; /* 0x0000000518047223 */
/* 0x000fc80000000004 */
/*06a0*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x002fc80000000004 */
/*06b0*/ FFMA R4, R12, R7, R4 ; /* 0x000000070c047223 */
/* 0x004fc80000000004 */
/*06c0*/ FFMA R4, R13, R8, R4 ; /* 0x000000080d047223 */
/* 0x008fc80000000004 */
/*06d0*/ FFMA R4, R22, R9, R4 ; /* 0x0000000916047223 */
/* 0x010fc80000000004 */
/*06e0*/ FFMA R4, R15, R10, R4 ; /* 0x0000000a0f047223 */
/* 0x020fc80000000004 */
/*06f0*/ FFMA R13, R14, R11, R4 ; /* 0x0000000b0e0d7223 */
/* 0x000fe20000000004 */
/*0700*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0710*/ @!P0 BRA 0x1c0 ; /* 0xfffffaa000008947 */
/* 0x000fea000383ffff */
/*0720*/ STG.E [R20.64], R13 ; /* 0x0000000d14007986 */
/* 0x000fe2000c101906 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void MatrixMulKernel(float* M, float* N, float* P, int Width) {
//We need to iterate with tiles - starting point and end needed for tiles
int Mstart=Width*BLOCK_SIZE*blockIdx.y;//rows of matrix M
int Mend=Mstart+Width-1;
int mstep=BLOCK_SIZE;
int Nstart=BLOCK_SIZE*blockIdx.x;//cols of matrix N
int nstep=BLOCK_SIZE*Width;
float temp=0;
//loop through tiles
for(int m=Mstart,n=Nstart;m<Mend;m+=mstep,n+=nstep){
__shared__ float Ms[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Ns[BLOCK_SIZE][BLOCK_SIZE];
Ms[threadIdx.y][threadIdx.x]=M[m+Width*threadIdx.y+threadIdx.x];
Ns[threadIdx.y][threadIdx.x]=N[n+Width*threadIdx.y+threadIdx.x];
__syncthreads();
for (int i = 0; i < BLOCK_SIZE; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();
}
P[Width * BLOCK_SIZE * blockIdx.y + BLOCK_SIZE * blockIdx.x + Width * threadIdx.y + threadIdx.x] = temp;
} | .file "tmpxft_00177e16_00000000-6_MatrixMulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void MatrixMulKernel(float* M, float* N, float* P, int Width) {
//We need to iterate with tiles - starting point and end needed for tiles
int Mstart=Width*BLOCK_SIZE*blockIdx.y;//rows of matrix M
int Mend=Mstart+Width-1;
int mstep=BLOCK_SIZE;
int Nstart=BLOCK_SIZE*blockIdx.x;//cols of matrix N
int nstep=BLOCK_SIZE*Width;
float temp=0;
//loop through tiles
for(int m=Mstart,n=Nstart;m<Mend;m+=mstep,n+=nstep){
__shared__ float Ms[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Ns[BLOCK_SIZE][BLOCK_SIZE];
Ms[threadIdx.y][threadIdx.x]=M[m+Width*threadIdx.y+threadIdx.x];
Ns[threadIdx.y][threadIdx.x]=N[n+Width*threadIdx.y+threadIdx.x];
__syncthreads();
for (int i = 0; i < BLOCK_SIZE; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();
}
P[Width * BLOCK_SIZE * blockIdx.y + BLOCK_SIZE * blockIdx.x + Width * threadIdx.y + threadIdx.x] = temp;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MatrixMulKernel(float* M, float* N, float* P, int Width) {
//We need to iterate with tiles - starting point and end needed for tiles
int Mstart=Width*BLOCK_SIZE*blockIdx.y;//rows of matrix M
int Mend=Mstart+Width-1;
int mstep=BLOCK_SIZE;
int Nstart=BLOCK_SIZE*blockIdx.x;//cols of matrix N
int nstep=BLOCK_SIZE*Width;
float temp=0;
//loop through tiles
for(int m=Mstart,n=Nstart;m<Mend;m+=mstep,n+=nstep){
__shared__ float Ms[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Ns[BLOCK_SIZE][BLOCK_SIZE];
Ms[threadIdx.y][threadIdx.x]=M[m+Width*threadIdx.y+threadIdx.x];
Ns[threadIdx.y][threadIdx.x]=N[n+Width*threadIdx.y+threadIdx.x];
__syncthreads();
for (int i = 0; i < BLOCK_SIZE; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();
}
P[Width * BLOCK_SIZE * blockIdx.y + BLOCK_SIZE * blockIdx.x + Width * threadIdx.y + threadIdx.x] = temp;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MatrixMulKernel(float* M, float* N, float* P, int Width) {
//We need to iterate with tiles - starting point and end needed for tiles
int Mstart=Width*BLOCK_SIZE*blockIdx.y;//rows of matrix M
int Mend=Mstart+Width-1;
int mstep=BLOCK_SIZE;
int Nstart=BLOCK_SIZE*blockIdx.x;//cols of matrix N
int nstep=BLOCK_SIZE*Width;
float temp=0;
//loop through tiles
for(int m=Mstart,n=Nstart;m<Mend;m+=mstep,n+=nstep){
__shared__ float Ms[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Ns[BLOCK_SIZE][BLOCK_SIZE];
Ms[threadIdx.y][threadIdx.x]=M[m+Width*threadIdx.y+threadIdx.x];
Ns[threadIdx.y][threadIdx.x]=N[n+Width*threadIdx.y+threadIdx.x];
__syncthreads();
for (int i = 0; i < BLOCK_SIZE; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();
}
P[Width * BLOCK_SIZE * blockIdx.y + BLOCK_SIZE * blockIdx.x + Width * threadIdx.y + threadIdx.x] = temp;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:
s_load_b32 s3, s[0:1], 0x18
v_mov_b32_e32 v5, 0
v_bfe_u32 v4, v0, 10, 10
s_lshl_b32 s8, s14, 5
s_waitcnt lgkmcnt(0)
s_lshl_b32 s9, s3, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s9, s15
s_add_i32 s10, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s10, -1
s_cmp_ge_i32 s2, s10
s_cbranch_scc1 .LBB0_5
v_and_b32_e32 v3, 0x3ff, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v6, 7, v4
s_mov_b32 s11, s8
s_mov_b32 s12, s2
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v8, 2, v3
v_mad_u64_u32 v[1:2], null, v4, s3, v[3:4]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v7, 0x1000, v8
v_add_nc_u32_e32 v8, v6, v8
v_add_nc_u32_e32 v9, v7, v6
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v2, s12, v1
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_add_nc_u32_e32 v2, s11, v1
v_lshlrev_b64 v[12:13], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
v_mov_b32_e32 v2, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b32 v10, v[10:11], off
global_load_b32 v11, v[12:13], off
s_waitcnt vmcnt(1)
ds_store_b32 v8, v10
s_waitcnt vmcnt(0)
ds_store_b32 v9, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s13, v6
s_add_i32 s13, s13, 4
ds_load_b32 v11, v2
ds_load_b32 v10, v10
v_add_nc_u32_e32 v2, 0x80, v2
s_cmpk_eq_i32 s13, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s12, s12, 32
s_add_i32 s11, s11, s9
s_cmp_ge_i32 s12, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v2, v4, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s8, v0
v_add3_u32 v0, v0, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MatrixMulKernel(float* M, float* N, float* P, int Width) {
//We need to iterate with tiles - starting point and end needed for tiles
int Mstart=Width*BLOCK_SIZE*blockIdx.y;//rows of matrix M
int Mend=Mstart+Width-1;
int mstep=BLOCK_SIZE;
int Nstart=BLOCK_SIZE*blockIdx.x;//cols of matrix N
int nstep=BLOCK_SIZE*Width;
float temp=0;
//loop through tiles
for(int m=Mstart,n=Nstart;m<Mend;m+=mstep,n+=nstep){
__shared__ float Ms[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Ns[BLOCK_SIZE][BLOCK_SIZE];
Ms[threadIdx.y][threadIdx.x]=M[m+Width*threadIdx.y+threadIdx.x];
Ns[threadIdx.y][threadIdx.x]=N[n+Width*threadIdx.y+threadIdx.x];
__syncthreads();
for (int i = 0; i < BLOCK_SIZE; ++i) {
temp += Ms[threadIdx.y][i] * Ns[i][threadIdx.x];
}
__syncthreads();
}
P[Width * BLOCK_SIZE * blockIdx.y + BLOCK_SIZE * blockIdx.x + Width * threadIdx.y + threadIdx.x] = temp;
} | .text
.file "MatrixMulKernel.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fe200000001ff */
/*0040*/ USHF.L.U32 UR4, UR4, 0x5, URZ ; /* 0x0000000504047899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0080*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ea20000002200 */
/*0090*/ IMAD R3, R5, UR4, RZ ; /* 0x0000000405037c24 */
/* 0x001fca000f8e02ff */
/*00a0*/ IADD3 R18, R3, c[0x0][0x178], RZ ; /* 0x00005e0003127a10 */
/* 0x000fe40007ffe0ff */
/*00b0*/ LEA R0, R7, R0, 0x5 ; /* 0x0000000007007211 */
/* 0x002fe400078e28ff */
/*00c0*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fc60007ffe0ff */
/*00d0*/ IMAD R0, R9, c[0x0][0x178], R0 ; /* 0x00005e0009007a24 */
/* 0x004fe200078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, R18, PT ; /* 0x000000120300720c */
/* 0x000fc80003f06270 */
/*00f0*/ IADD3 R0, R3, R0, RZ ; /* 0x0000000003007210 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE.U32 R20, R0, R21, c[0x0][0x170] ; /* 0x00005c0000147625 */
/* 0x000fc800078e0015 */
/*0110*/ @P0 MOV R13, RZ ; /* 0x000000ff000d0202 */
/* 0x000fe20000000f00 */
/*0120*/ @P0 BRA 0x720 ; /* 0x000005f000000947 */
/* 0x000fea0003800000 */
/*0130*/ S2R R19, SR_TID.Y ; /* 0x0000000000137919 */
/* 0x000e220000002200 */
/*0140*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fc60000000f00 */
/*0150*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0160*/ LEA R5, R5, R19, 0x5 ; /* 0x0000001305057211 */
/* 0x001fe200078e28ff */
/*0170*/ IMAD R16, R19.reuse, c[0x0][0x178], R2 ; /* 0x00005e0013107a24 */
/* 0x042fe200078e0202 */
/*0180*/ SHF.L.U32 R19, R19, 0x7, RZ ; /* 0x0000000713137819 */
/* 0x000fc600000006ff */
/*0190*/ IMAD R0, R5, c[0x0][0x178], R2 ; /* 0x00005e0005007a24 */
/* 0x000fe200078e0202 */
/*01a0*/ LEA R16, R7, R16, 0x5 ; /* 0x0000001007107211 */
/* 0x000fe400078e28ff */
/*01b0*/ LEA R17, R2, R19, 0x2 ; /* 0x0000001302117211 */
/* 0x000fe400078e10ff */
/*01c0*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fd400000001ff */
/*01d0*/ IMAD.WIDE.U32 R8, R0, R15, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e000f */
/*01e0*/ IMAD.WIDE.U32 R14, R16.reuse, R15, c[0x0][0x168] ; /* 0x00005a00100e7625 */
/* 0x040fe200078e000f */
/*01f0*/ LDG.E R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000eaa000c1e1900 */
/*0200*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee2000c1e1900 */
/*0210*/ IADD3 R3, R3, 0x20, RZ ; /* 0x0000002003037810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R16, R16, UR4, RZ ; /* 0x0000000410107c10 */
/* 0x000fe4000fffe0ff */
/*0230*/ ISETP.GE.AND P0, PT, R3, R18, PT ; /* 0x000000120300720c */
/* 0x000fc40003f06270 */
/*0240*/ IADD3 R0, R0, 0x20, RZ ; /* 0x0000002000007810 */
/* 0x000fe20007ffe0ff */
/*0250*/ STS [R17], R12 ; /* 0x0000000c11007388 */
/* 0x004fe80000000800 */
/*0260*/ STS [R17+0x1000], R14 ; /* 0x0010000e11007388 */
/* 0x008fe80000000800 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ LDS R23, [R2.X4+0x1000] ; /* 0x0010000002177984 */
/* 0x000fe80000004800 */
/*0290*/ LDS.128 R4, [R19] ; /* 0x0000000013047984 */
/* 0x000e280000000c00 */
/*02a0*/ LDS R28, [R2.X4+0x1080] ; /* 0x00108000021c7984 */
/* 0x000e680000004800 */
/*02b0*/ LDS R29, [R2.X4+0x1100] ; /* 0x00110000021d7984 */
/* 0x000ea80000004800 */
/*02c0*/ LDS R26, [R2.X4+0x1180] ; /* 0x00118000021a7984 */
/* 0x000ee80000004800 */
/*02d0*/ LDS R27, [R2.X4+0x1200] ; /* 0x00120000021b7984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS.128 R8, [R19+0x10] ; /* 0x0000100013087984 */
/* 0x000f280000000c00 */
/*02f0*/ LDS R24, [R2.X4+0x1280] ; /* 0x0012800002187984 */
/* 0x000f680000004800 */
/*0300*/ LDS R25, [R2.X4+0x1300] ; /* 0x0013000002197984 */
/* 0x000f680000004800 */
/*0310*/ LDS R22, [R2.X4+0x1380] ; /* 0x0013800002167984 */
/* 0x000f620000004800 */
/*0320*/ FFMA R4, R23, R4, R13 ; /* 0x0000000417047223 */
/* 0x001fc6000000000d */
/*0330*/ LDS R23, [R2.X4+0x1400] ; /* 0x0014000002177984 */
/* 0x000fe20000004800 */
/*0340*/ FFMA R5, R28, R5, R4 ; /* 0x000000051c057223 */
/* 0x002fc60000000004 */
/*0350*/ LDS.128 R12, [R19+0x20] ; /* 0x00002000130c7984 */
/* 0x000e220000000c00 */
/*0360*/ FFMA R5, R29, R6, R5 ; /* 0x000000061d057223 */
/* 0x004fc60000000005 */
/*0370*/ LDS R28, [R2.X4+0x1480] ; /* 0x00148000021c7984 */
/* 0x000e620000004800 */
/*0380*/ FFMA R5, R26, R7, R5 ; /* 0x000000071a057223 */
/* 0x008fc60000000005 */
/*0390*/ LDS R29, [R2.X4+0x1500] ; /* 0x00150000021d7984 */
/* 0x000ea80000004800 */
/*03a0*/ LDS R26, [R2.X4+0x1680] ; /* 0x00168000021a7984 */
/* 0x000fe20000004800 */
/*03b0*/ FFMA R5, R27, R8, R5 ; /* 0x000000081b057223 */
/* 0x010fc60000000005 */
/*03c0*/ LDS R27, [R2.X4+0x1700] ; /* 0x00170000021b7984 */
/* 0x000fe20000004800 */
/*03d0*/ FFMA R5, R24, R9, R5 ; /* 0x0000000918057223 */
/* 0x020fc60000000005 */
/*03e0*/ LDS R24, [R2.X4+0x1580] ; /* 0x0015800002187984 */
/* 0x000ee20000004800 */
/*03f0*/ FFMA R10, R25, R10, R5 ; /* 0x0000000a190a7223 */
/* 0x000fc60000000005 */
/*0400*/ LDS R25, [R2.X4+0x1600] ; /* 0x0016000002197984 */
/* 0x000fe20000004800 */
/*0410*/ FFMA R10, R22, R11, R10 ; /* 0x0000000b160a7223 */
/* 0x000fc6000000000a */
/*0420*/ LDS.128 R4, [R19+0x30] ; /* 0x0000300013047984 */
/* 0x000f280000000c00 */
/*0430*/ LDS R22, [R2.X4+0x1780] ; /* 0x0017800002167984 */
/* 0x000f620000004800 */
/*0440*/ FFMA R10, R23, R12, R10 ; /* 0x0000000c170a7223 */
/* 0x001fc6000000000a */
/*0450*/ LDS R23, [R2.X4+0x1800] ; /* 0x0018000002177984 */
/* 0x000fe20000004800 */
/*0460*/ FFMA R10, R28, R13, R10 ; /* 0x0000000d1c0a7223 */
/* 0x002fc6000000000a */
/*0470*/ LDS R28, [R2.X4+0x1a80] ; /* 0x001a8000021c7984 */
/* 0x000fe20000004800 */
/*0480*/ FFMA R14, R29, R14, R10 ; /* 0x0000000e1d0e7223 */
/* 0x004fc6000000000a */
/*0490*/ LDS.128 R8, [R19+0x40] ; /* 0x0000400013087984 */
/* 0x000e280000000c00 */
/*04a0*/ LDS R29, [R2.X4+0x1900] ; /* 0x00190000021d7984 */
/* 0x000fe20000004800 */
/*04b0*/ FFMA R14, R24, R15, R14 ; /* 0x0000000f180e7223 */
/* 0x008fc6000000000e */
/*04c0*/ LDS R24, [R2.X4+0x1880] ; /* 0x0018800002187984 */
/* 0x000e620000004800 */
/*04d0*/ FFMA R4, R25, R4, R14 ; /* 0x0000000419047223 */
/* 0x010fc6000000000e */
/*04e0*/ LDS R25, [R2.X4+0x1a00] ; /* 0x001a000002197984 */
/* 0x000fe20000004800 */
/*04f0*/ FFMA R4, R26, R5, R4 ; /* 0x000000051a047223 */
/* 0x000fc60000000004 */
/*0500*/ LDS R26, [R2.X4+0x1980] ; /* 0x00198000021a7984 */
/* 0x000ea20000004800 */
/*0510*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc60000000004 */
/*0520*/ LDS.128 R12, [R19+0x50] ; /* 0x00005000130c7984 */
/* 0x000ee20000000c00 */
/*0530*/ FFMA R4, R22, R7, R4 ; /* 0x0000000716047223 */
/* 0x020fc60000000004 */
/*0540*/ LDS R27, [R2.X4+0x1b00] ; /* 0x001b0000021b7984 */
/* 0x000f280000004800 */
/*0550*/ LDS R22, [R2.X4+0x1b80] ; /* 0x001b800002167984 */
/* 0x000f620000004800 */
/*0560*/ FFMA R4, R23, R8, R4 ; /* 0x0000000817047223 */
/* 0x001fc60000000004 */
/*0570*/ LDS R23, [R2.X4+0x1c00] ; /* 0x001c000002177984 */
/* 0x000fe20000004800 */
/*0580*/ FFMA R4, R24, R9, R4 ; /* 0x0000000918047223 */
/* 0x002fc60000000004 */
/*0590*/ LDS R24, [R2.X4+0x1c80] ; /* 0x001c800002187984 */
/* 0x000fe20000004800 */
/*05a0*/ FFMA R10, R29, R10, R4 ; /* 0x0000000a1d0a7223 */
/* 0x000fc60000000004 */
/*05b0*/ LDS.128 R4, [R19+0x60] ; /* 0x0000600013047984 */
/* 0x000e220000000c00 */
/*05c0*/ FFMA R10, R26, R11, R10 ; /* 0x0000000b1a0a7223 */
/* 0x004fc8000000000a */
/*05d0*/ FFMA R10, R25, R12, R10 ; /* 0x0000000c190a7223 */
/* 0x008fe4000000000a */
/*05e0*/ LDS R25, [R2.X4+0x1d00] ; /* 0x001d000002197984 */
/* 0x000e640000004800 */
/*05f0*/ FFMA R10, R28, R13, R10 ; /* 0x0000000d1c0a7223 */
/* 0x000fe4000000000a */
/*0600*/ LDS R12, [R2.X4+0x1d80] ; /* 0x001d8000020c7984 */
/* 0x000ea40000004800 */
/*0610*/ FFMA R14, R27, R14, R10 ; /* 0x0000000e1b0e7223 */
/* 0x010fe4000000000a */
/*0620*/ LDS R13, [R2.X4+0x1e00] ; /* 0x001e0000020d7984 */
/* 0x000fe40000004800 */
/*0630*/ FFMA R26, R22, R15, R14 ; /* 0x0000000f161a7223 */
/* 0x020fc4000000000e */
/*0640*/ LDS.128 R8, [R19+0x70] ; /* 0x0000700013087984 */
/* 0x000ee80000000c00 */
/*0650*/ LDS R22, [R2.X4+0x1e80] ; /* 0x001e800002167984 */
/* 0x000f280000004800 */
/*0660*/ LDS R15, [R2.X4+0x1f00] ; /* 0x001f0000020f7984 */
/* 0x000f680000004800 */
/*0670*/ LDS R14, [R2.X4+0x1f80] ; /* 0x001f8000020e7984 */
/* 0x000f620000004800 */
/*0680*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x001fc8000000001a */
/*0690*/ FFMA R4, R24, R5, R4 ; /* 0x0000000518047223 */
/* 0x000fc80000000004 */
/*06a0*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x002fc80000000004 */
/*06b0*/ FFMA R4, R12, R7, R4 ; /* 0x000000070c047223 */
/* 0x004fc80000000004 */
/*06c0*/ FFMA R4, R13, R8, R4 ; /* 0x000000080d047223 */
/* 0x008fc80000000004 */
/*06d0*/ FFMA R4, R22, R9, R4 ; /* 0x0000000916047223 */
/* 0x010fc80000000004 */
/*06e0*/ FFMA R4, R15, R10, R4 ; /* 0x0000000a0f047223 */
/* 0x020fc80000000004 */
/*06f0*/ FFMA R13, R14, R11, R4 ; /* 0x0000000b0e0d7223 */
/* 0x000fe20000000004 */
/*0700*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0710*/ @!P0 BRA 0x1c0 ; /* 0xfffffaa000008947 */
/* 0x000fea000383ffff */
/*0720*/ STG.E [R20.64], R13 ; /* 0x0000000d14007986 */
/* 0x000fe2000c101906 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:
s_load_b32 s3, s[0:1], 0x18
v_mov_b32_e32 v5, 0
v_bfe_u32 v4, v0, 10, 10
s_lshl_b32 s8, s14, 5
s_waitcnt lgkmcnt(0)
s_lshl_b32 s9, s3, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s9, s15
s_add_i32 s10, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s10, -1
s_cmp_ge_i32 s2, s10
s_cbranch_scc1 .LBB0_5
v_and_b32_e32 v3, 0x3ff, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v6, 7, v4
s_mov_b32 s11, s8
s_mov_b32 s12, s2
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v8, 2, v3
v_mad_u64_u32 v[1:2], null, v4, s3, v[3:4]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v7, 0x1000, v8
v_add_nc_u32_e32 v8, v6, v8
v_add_nc_u32_e32 v9, v7, v6
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v2, s12, v1
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_add_nc_u32_e32 v2, s11, v1
v_lshlrev_b64 v[12:13], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
v_mov_b32_e32 v2, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b32 v10, v[10:11], off
global_load_b32 v11, v[12:13], off
s_waitcnt vmcnt(1)
ds_store_b32 v8, v10
s_waitcnt vmcnt(0)
ds_store_b32 v9, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s13, v6
s_add_i32 s13, s13, 4
ds_load_b32 v11, v2
ds_load_b32 v10, v10
v_add_nc_u32_e32 v2, 0x80, v2
s_cmpk_eq_i32 s13, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s12, s12, 32
s_add_i32 s11, s11, s9
s_cmp_ge_i32 s12, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v2, v4, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s8, v0
v_add3_u32 v0, v0, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00177e16_00000000-6_MatrixMulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixMulKernel.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // 1 / (1 + e^(-x))
extern "C"
__global__ void logistic(size_t n, double *result, double *x)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
result[i] = 1.0 / (1.0 + exp(-x[i]));
}
} | code for sm_80
Function : logistic
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x164], PT, P0 ; /* 0x0000590003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R0, R2.reuse, 0x8, RZ ; /* 0x0000000802007824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R2, R2, 0x3, R3 ; /* 0x0000000302027819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R2, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0002057a10 */
/* 0x000fcc00007fe4ff */
/*00d0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x652b82fe ; /* 0x652b82feff067424 */
/* 0x000fe200078e00ff */
/*00f0*/ BSSY B0, 0x340 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff077424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R12, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0c7424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0d7424 */
/* 0x000fe400078e00ff */
/*0130*/ DFMA R6, -R4, R6, 6.75539944105574400000e+15 ; /* 0x433800000406742b */
/* 0x004e0c0000000106 */
/*0140*/ DADD R8, R6, -6.75539944105574400000e+15 ; /* 0xc338000006087429 */
/* 0x001e0c0000000000 */
/*0150*/ DFMA R10, R8, c[0x2][0x0], -R4 ; /* 0x00800000080a7a2b */
/* 0x001e0c0000000804 */
/*0160*/ DFMA R8, R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */
/* 0x001e0c000000000a */
/*0170*/ DFMA R10, R8, R12, c[0x2][0x10] ; /* 0x00800400080a762b */
/* 0x001e08000000000c */
/*0180*/ DADD R12, -RZ, -R4 ; /* 0x00000000ff0c7229 */
/* 0x000fc80000000904 */
/*0190*/ DFMA R10, R8, R10, c[0x2][0x18] ; /* 0x00800600080a762b */
/* 0x001e0c000000000a */
/*01a0*/ DFMA R10, R8, R10, c[0x2][0x20] ; /* 0x00800800080a762b */
/* 0x001e22000000000a */
/*01b0*/ FSETP.GEU.AND P0, PT, |R13|, 4.1917929649353027344, PT ; /* 0x4086232b0d00780b */
/* 0x000fca0003f0e200 */
/*01c0*/ DFMA R10, R8, R10, c[0x2][0x28] ; /* 0x00800a00080a762b */
/* 0x001e0c000000000a */
/*01d0*/ DFMA R10, R8, R10, c[0x2][0x30] ; /* 0x00800c00080a762b */
/* 0x001e0c000000000a */
/*01e0*/ DFMA R10, R8, R10, c[0x2][0x38] ; /* 0x00800e00080a762b */
/* 0x001e0c000000000a */
/*01f0*/ DFMA R10, R8, R10, c[0x2][0x40] ; /* 0x00801000080a762b */
/* 0x001e0c000000000a */
/*0200*/ DFMA R10, R8, R10, c[0x2][0x48] ; /* 0x00801200080a762b */
/* 0x001e0c000000000a */
/*0210*/ DFMA R10, R8, R10, c[0x2][0x50] ; /* 0x00801400080a762b */
/* 0x001e0c000000000a */
/*0220*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c000000000a */
/*0230*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x001e14000000000a */
/*0240*/ IMAD R9, R6, 0x100000, R11 ; /* 0x0010000006097824 */
/* 0x001fe400078e020b */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000a */
/*0260*/ @!P0 BRA 0x330 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0270*/ FSETP.GEU.AND P1, PT, |R13|, 4.2275390625, PT ; /* 0x408748000d00780b */
/* 0x000fe20003f2e200 */
/*0280*/ DADD R8, -R4, +INF ; /* 0x7ff0000004087429 */
/* 0x000fc80000000100 */
/*0290*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e0c0003f04000 */
/*02a0*/ FSEL R8, R8, RZ, !P0 ; /* 0x000000ff08087208 */
/* 0x001fe40004000000 */
/*02b0*/ @!P1 LEA.HI R3, R6, R6, RZ, 0x1 ; /* 0x0000000606039211 */
/* 0x000fe400078f08ff */
/*02c0*/ FSEL R9, R9, RZ, !P0 ; /* 0x000000ff09097208 */
/* 0x000fe40004000000 */
/*02d0*/ @!P1 SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff039819 */
/* 0x000fca0000011403 */
/*02e0*/ @!P1 IMAD.IADD R4, R6, 0x1, -R3 ; /* 0x0000000106049824 */
/* 0x000fe400078e0a03 */
/*02f0*/ @!P1 IMAD R11, R3, 0x100000, R11 ; /* 0x00100000030b9824 */
/* 0x000fc600078e020b */
/*0300*/ @!P1 LEA R5, R4, 0x3ff00000, 0x14 ; /* 0x3ff0000004059811 */
/* 0x000fe200078ea0ff */
/*0310*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff049224 */
/* 0x000fcc00078e00ff */
/*0320*/ @!P1 DMUL R8, R10, R4 ; /* 0x000000040a089228 */
/* 0x00004c0000000000 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ DADD R10, R8, 1 ; /* 0x3ff00000080a7429 */
/* 0x003e220000000000 */
/*0350*/ BSSY B0, 0x440 ; /* 0x000000e000007945 */
/* 0x000fea0003800000 */
/*0360*/ MUFU.RCP64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e280000001800 */
/*0370*/ IADD3 R4, R11, 0x300402, RZ ; /* 0x003004020b047810 */
/* 0x000fc80007ffe0ff */
/*0380*/ FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ; /* 0x004004020400780b */
/* 0x000fe40003f0e200 */
/*0390*/ DFMA R6, -R10, R4, 1 ; /* 0x3ff000000a06742b */
/* 0x001e0c0000000104 */
/*03a0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*03b0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*03c0*/ DFMA R8, -R10, R6, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c0000000106 */
/*03d0*/ DFMA R6, R6, R8, R6 ; /* 0x000000080606722b */
/* 0x0010620000000006 */
/*03e0*/ @P0 BRA 0x430 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT R3, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0b037812 */
/* 0x000fe400078ec0ff */
/*0400*/ MOV R4, 0x430 ; /* 0x0000043000047802 */
/* 0x000fe40000000f00 */
/*0410*/ IADD3 R3, R3, -0x100000, RZ ; /* 0xfff0000003037810 */
/* 0x000fe40007ffe0ff */
/*0420*/ CALL.REL.NOINC 0x480 ; /* 0x0000005000007944 */
/* 0x003fea0003c00000 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0450*/ IADD3.X R5, R2, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0002057a10 */
/* 0x000fca00007fe4ff */
/*0460*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x002fe2000c101b04 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000a */
/*0490*/ BSSY B1, 0x700 ; /* 0x0000026000017945 */
/* 0x000fe20003800000 */
/*04a0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fcc00078e000b */
/*04b0*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f0c200 */
/*04c0*/ @P0 BRA 0x6d0 ; /* 0x0000020000000947 */
/* 0x001fea0003800000 */
/*04d0*/ LOP3.LUT R10, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0b0a7812 */
/* 0x000fc800078ec0ff */
/*04e0*/ IADD3 R5, R10, -0x1, RZ ; /* 0xffffffff0a057810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GE.U32.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */
/* 0x000fda0003f06070 */
/*0500*/ @P0 LOP3.LUT R9, R7, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000007090812 */
/* 0x000fe200078e3cff */
/*0510*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe200078e00ff */
/*0520*/ @P0 BRA 0x6f0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0530*/ ISETP.GE.U32.AND P0, PT, R10, 0x1000001, PT ; /* 0x010000010a00780c */
/* 0x000fda0003f06070 */
/*0540*/ @!P0 BRA 0x630 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R9, R7, -0x3fe00000, RZ ; /* 0xc020000007097810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*0570*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0003 */
/*0580*/ MUFU.RCP64H R11, R9 ; /* 0x00000009000b7308 */
/* 0x000e2a0000001800 */
/*0590*/ DFMA R12, -R8, R10, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000010a */
/*05a0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*05b0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*05c0*/ DFMA R10, -R8, R12, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c000000010c */
/*05d0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*05e0*/ DMUL R10, R10, 2.2250738585072013831e-308 ; /* 0x001000000a0a7828 */
/* 0x001e0c0000000000 */
/*05f0*/ DFMA R6, -R6, R10, 1 ; /* 0x3ff000000606742b */
/* 0x001e0c000000010a */
/*0600*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0610*/ DFMA R8, R10, R6, R10 ; /* 0x000000060a08722b */
/* 0x001062000000000a */
/*0620*/ BRA 0x6f0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0630*/ DMUL R6, R6, 8.11296384146066816958e+31 ; /* 0x4690000006067828 */
/* 0x000e220000000000 */
/*0640*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0003 */
/*0650*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e240000001800 */
/*0660*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*0670*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0680*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0690*/ DFMA R8, -R6, R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010a */
/*06a0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*06b0*/ DMUL R8, R8, 8.11296384146066816958e+31 ; /* 0x4690000008087828 */
/* 0x001e220000000000 */
/*06c0*/ BRA 0x6f0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06d0*/ LOP3.LUT R9, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007097812 */
/* 0x000fe200078efcff */
/*06e0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0700*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe400078e00ff */
/*0710*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x003fe400078e0008 */
/*0720*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0730*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff8c004007950 */
/* 0x000fec0003c3ffff */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // 1 / (1 + e^(-x))
extern "C"
__global__ void logistic(size_t n, double *result, double *x)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
result[i] = 1.0 / (1.0 + exp(-x[i]));
}
} | .file "tmpxft_0000d6ec_00000000-6_LogisticFunctionKernel_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8logisticmPdS_mPdS_
.type _Z30__device_stub__Z8logisticmPdS_mPdS_, @function
_Z30__device_stub__Z8logisticmPdS_mPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq logistic(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z8logisticmPdS_mPdS_, .-_Z30__device_stub__Z8logisticmPdS_mPdS_
.globl logistic
.type logistic, @function
logistic:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8logisticmPdS_mPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size logistic, .-logistic
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "logistic"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq logistic(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // 1 / (1 + e^(-x))
extern "C"
__global__ void logistic(size_t n, double *result, double *x)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
result[i] = 1.0 / (1.0 + exp(-x[i]));
}
} | #include <hip/hip_runtime.h>
// 1 / (1 + e^(-x))
extern "C"
__global__ void logistic(size_t n, double *result, double *x)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
result[i] = 1.0 / (1.0 + exp(-x[i]));
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// 1 / (1 + e^(-x))
extern "C"
__global__ void logistic(size_t n, double *result, double *x)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
result[i] = 1.0 / (1.0 + exp(-x[i]));
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected logistic
.globl logistic
.p2align 8
.type logistic,@function
logistic:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_mov_b32 s1, 0xbff71547
s_mov_b32 s0, 0x652b82fe
s_mov_b32 s3, 0x3e5ade15
s_mov_b32 s2, 0x6a5dcb37
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[4:5], v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], -v[2:3]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
v_cvt_i32_f64_e32 v10, v[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], s[2:3], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
v_cmp_nlt_f64_e64 s0, 0x4090cc00, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v10
v_add_f64 v[4:5], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[4:5], 1.0
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_cmp_ngt_f64_e32 vcc_lo, 0xc0900000, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[6:7], v[4:5], 1.0
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_cndmask_b32_e64 v3, 0x3ff00000, v5, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel logistic
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size logistic, .Lfunc_end0-logistic
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: logistic
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: logistic.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// 1 / (1 + e^(-x))
extern "C"
__global__ void logistic(size_t n, double *result, double *x)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
result[i] = 1.0 / (1.0 + exp(-x[i]));
}
} | .text
.file "LogisticFunctionKernel_double.hip"
.globl __device_stub__logistic # -- Begin function __device_stub__logistic
.p2align 4, 0x90
.type __device_stub__logistic,@function
__device_stub__logistic: # @__device_stub__logistic
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $logistic, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__logistic, .Lfunc_end0-__device_stub__logistic
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $logistic, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type logistic,@object # @logistic
.section .rodata,"a",@progbits
.globl logistic
.p2align 3, 0x0
logistic:
.quad __device_stub__logistic
.size logistic, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "logistic"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__logistic
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym logistic
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : logistic
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x164], PT, P0 ; /* 0x0000590003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R0, R2.reuse, 0x8, RZ ; /* 0x0000000802007824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R2, R2, 0x3, R3 ; /* 0x0000000302027819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R5, R2, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0002057a10 */
/* 0x000fcc00007fe4ff */
/*00d0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x652b82fe ; /* 0x652b82feff067424 */
/* 0x000fe200078e00ff */
/*00f0*/ BSSY B0, 0x340 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff077424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R12, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0c7424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0d7424 */
/* 0x000fe400078e00ff */
/*0130*/ DFMA R6, -R4, R6, 6.75539944105574400000e+15 ; /* 0x433800000406742b */
/* 0x004e0c0000000106 */
/*0140*/ DADD R8, R6, -6.75539944105574400000e+15 ; /* 0xc338000006087429 */
/* 0x001e0c0000000000 */
/*0150*/ DFMA R10, R8, c[0x2][0x0], -R4 ; /* 0x00800000080a7a2b */
/* 0x001e0c0000000804 */
/*0160*/ DFMA R8, R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */
/* 0x001e0c000000000a */
/*0170*/ DFMA R10, R8, R12, c[0x2][0x10] ; /* 0x00800400080a762b */
/* 0x001e08000000000c */
/*0180*/ DADD R12, -RZ, -R4 ; /* 0x00000000ff0c7229 */
/* 0x000fc80000000904 */
/*0190*/ DFMA R10, R8, R10, c[0x2][0x18] ; /* 0x00800600080a762b */
/* 0x001e0c000000000a */
/*01a0*/ DFMA R10, R8, R10, c[0x2][0x20] ; /* 0x00800800080a762b */
/* 0x001e22000000000a */
/*01b0*/ FSETP.GEU.AND P0, PT, |R13|, 4.1917929649353027344, PT ; /* 0x4086232b0d00780b */
/* 0x000fca0003f0e200 */
/*01c0*/ DFMA R10, R8, R10, c[0x2][0x28] ; /* 0x00800a00080a762b */
/* 0x001e0c000000000a */
/*01d0*/ DFMA R10, R8, R10, c[0x2][0x30] ; /* 0x00800c00080a762b */
/* 0x001e0c000000000a */
/*01e0*/ DFMA R10, R8, R10, c[0x2][0x38] ; /* 0x00800e00080a762b */
/* 0x001e0c000000000a */
/*01f0*/ DFMA R10, R8, R10, c[0x2][0x40] ; /* 0x00801000080a762b */
/* 0x001e0c000000000a */
/*0200*/ DFMA R10, R8, R10, c[0x2][0x48] ; /* 0x00801200080a762b */
/* 0x001e0c000000000a */
/*0210*/ DFMA R10, R8, R10, c[0x2][0x50] ; /* 0x00801400080a762b */
/* 0x001e0c000000000a */
/*0220*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c000000000a */
/*0230*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x001e14000000000a */
/*0240*/ IMAD R9, R6, 0x100000, R11 ; /* 0x0010000006097824 */
/* 0x001fe400078e020b */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000a */
/*0260*/ @!P0 BRA 0x330 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0270*/ FSETP.GEU.AND P1, PT, |R13|, 4.2275390625, PT ; /* 0x408748000d00780b */
/* 0x000fe20003f2e200 */
/*0280*/ DADD R8, -R4, +INF ; /* 0x7ff0000004087429 */
/* 0x000fc80000000100 */
/*0290*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e0c0003f04000 */
/*02a0*/ FSEL R8, R8, RZ, !P0 ; /* 0x000000ff08087208 */
/* 0x001fe40004000000 */
/*02b0*/ @!P1 LEA.HI R3, R6, R6, RZ, 0x1 ; /* 0x0000000606039211 */
/* 0x000fe400078f08ff */
/*02c0*/ FSEL R9, R9, RZ, !P0 ; /* 0x000000ff09097208 */
/* 0x000fe40004000000 */
/*02d0*/ @!P1 SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff039819 */
/* 0x000fca0000011403 */
/*02e0*/ @!P1 IMAD.IADD R4, R6, 0x1, -R3 ; /* 0x0000000106049824 */
/* 0x000fe400078e0a03 */
/*02f0*/ @!P1 IMAD R11, R3, 0x100000, R11 ; /* 0x00100000030b9824 */
/* 0x000fc600078e020b */
/*0300*/ @!P1 LEA R5, R4, 0x3ff00000, 0x14 ; /* 0x3ff0000004059811 */
/* 0x000fe200078ea0ff */
/*0310*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff049224 */
/* 0x000fcc00078e00ff */
/*0320*/ @!P1 DMUL R8, R10, R4 ; /* 0x000000040a089228 */
/* 0x00004c0000000000 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ DADD R10, R8, 1 ; /* 0x3ff00000080a7429 */
/* 0x003e220000000000 */
/*0350*/ BSSY B0, 0x440 ; /* 0x000000e000007945 */
/* 0x000fea0003800000 */
/*0360*/ MUFU.RCP64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e280000001800 */
/*0370*/ IADD3 R4, R11, 0x300402, RZ ; /* 0x003004020b047810 */
/* 0x000fc80007ffe0ff */
/*0380*/ FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ; /* 0x004004020400780b */
/* 0x000fe40003f0e200 */
/*0390*/ DFMA R6, -R10, R4, 1 ; /* 0x3ff000000a06742b */
/* 0x001e0c0000000104 */
/*03a0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*03b0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*03c0*/ DFMA R8, -R10, R6, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c0000000106 */
/*03d0*/ DFMA R6, R6, R8, R6 ; /* 0x000000080606722b */
/* 0x0010620000000006 */
/*03e0*/ @P0 BRA 0x430 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT R3, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0b037812 */
/* 0x000fe400078ec0ff */
/*0400*/ MOV R4, 0x430 ; /* 0x0000043000047802 */
/* 0x000fe40000000f00 */
/*0410*/ IADD3 R3, R3, -0x100000, RZ ; /* 0xfff0000003037810 */
/* 0x000fe40007ffe0ff */
/*0420*/ CALL.REL.NOINC 0x480 ; /* 0x0000005000007944 */
/* 0x003fea0003c00000 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0450*/ IADD3.X R5, R2, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0002057a10 */
/* 0x000fca00007fe4ff */
/*0460*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x002fe2000c101b04 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000a */
/*0490*/ BSSY B1, 0x700 ; /* 0x0000026000017945 */
/* 0x000fe20003800000 */
/*04a0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fcc00078e000b */
/*04b0*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f0c200 */
/*04c0*/ @P0 BRA 0x6d0 ; /* 0x0000020000000947 */
/* 0x001fea0003800000 */
/*04d0*/ LOP3.LUT R10, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0b0a7812 */
/* 0x000fc800078ec0ff */
/*04e0*/ IADD3 R5, R10, -0x1, RZ ; /* 0xffffffff0a057810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GE.U32.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */
/* 0x000fda0003f06070 */
/*0500*/ @P0 LOP3.LUT R9, R7, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000007090812 */
/* 0x000fe200078e3cff */
/*0510*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe200078e00ff */
/*0520*/ @P0 BRA 0x6f0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0530*/ ISETP.GE.U32.AND P0, PT, R10, 0x1000001, PT ; /* 0x010000010a00780c */
/* 0x000fda0003f06070 */
/*0540*/ @!P0 BRA 0x630 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R9, R7, -0x3fe00000, RZ ; /* 0xc020000007097810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*0570*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0003 */
/*0580*/ MUFU.RCP64H R11, R9 ; /* 0x00000009000b7308 */
/* 0x000e2a0000001800 */
/*0590*/ DFMA R12, -R8, R10, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000010a */
/*05a0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*05b0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*05c0*/ DFMA R10, -R8, R12, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c000000010c */
/*05d0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*05e0*/ DMUL R10, R10, 2.2250738585072013831e-308 ; /* 0x001000000a0a7828 */
/* 0x001e0c0000000000 */
/*05f0*/ DFMA R6, -R6, R10, 1 ; /* 0x3ff000000606742b */
/* 0x001e0c000000010a */
/*0600*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0610*/ DFMA R8, R10, R6, R10 ; /* 0x000000060a08722b */
/* 0x001062000000000a */
/*0620*/ BRA 0x6f0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0630*/ DMUL R6, R6, 8.11296384146066816958e+31 ; /* 0x4690000006067828 */
/* 0x000e220000000000 */
/*0640*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0003 */
/*0650*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e240000001800 */
/*0660*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*0670*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0680*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0690*/ DFMA R8, -R6, R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010a */
/*06a0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*06b0*/ DMUL R8, R8, 8.11296384146066816958e+31 ; /* 0x4690000008087828 */
/* 0x001e220000000000 */
/*06c0*/ BRA 0x6f0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06d0*/ LOP3.LUT R9, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007097812 */
/* 0x000fe200078efcff */
/*06e0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0700*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe400078e00ff */
/*0710*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x003fe400078e0008 */
/*0720*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0730*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff8c004007950 */
/* 0x000fec0003c3ffff */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected logistic
.globl logistic
.p2align 8
.type logistic,@function
logistic:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_mov_b32 s1, 0xbff71547
s_mov_b32 s0, 0x652b82fe
s_mov_b32 s3, 0x3e5ade15
s_mov_b32 s2, 0x6a5dcb37
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[4:5], v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], -v[2:3]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
v_cvt_i32_f64_e32 v10, v[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], s[2:3], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
v_cmp_nlt_f64_e64 s0, 0x4090cc00, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v10
v_add_f64 v[4:5], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[4:5], 1.0
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_cmp_ngt_f64_e32 vcc_lo, 0xc0900000, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[6:7], v[4:5], 1.0
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_cndmask_b32_e64 v3, 0x3ff00000, v5, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel logistic
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size logistic, .Lfunc_end0-logistic
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: logistic
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: logistic.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000d6ec_00000000-6_LogisticFunctionKernel_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8logisticmPdS_mPdS_
.type _Z30__device_stub__Z8logisticmPdS_mPdS_, @function
_Z30__device_stub__Z8logisticmPdS_mPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq logistic(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z8logisticmPdS_mPdS_, .-_Z30__device_stub__Z8logisticmPdS_mPdS_
.globl logistic
.type logistic, @function
logistic:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8logisticmPdS_mPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size logistic, .-logistic
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "logistic"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq logistic(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LogisticFunctionKernel_double.hip"
.globl __device_stub__logistic # -- Begin function __device_stub__logistic
.p2align 4, 0x90
.type __device_stub__logistic,@function
__device_stub__logistic: # @__device_stub__logistic
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $logistic, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__logistic, .Lfunc_end0-__device_stub__logistic
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $logistic, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type logistic,@object # @logistic
.section .rodata,"a",@progbits
.globl logistic
.p2align 3, 0x0
logistic:
.quad __device_stub__logistic
.size logistic, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "logistic"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__logistic
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym logistic
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Kernel code for Gaussian Mixture Model Expectation Maximization.
//
// Andrew Harp (andrew.harp@gmail.com)
// http://andrewharp.com/gmmcuda
// This effects the maximum dimensionality of your data.
// Has to be hardcoded because it affects memory allocation.
// Due to the way I clear out the lower triangle of the cholesky (and
// possibly other) places MAX_DIM * MAX_DIM needs to be less than
// BLOCK_SIZE.
#define MAX_DIM 16
// You can change this, but only to a power of 2.
#define BLOCK_SIZE 256
// Estep-normalize is broken down into an arbitrary number of chunks.
#define NUM_CHUNKS 32
#include "cuda_runtime.h"
///////////////////////////////////////////////////////////////////////////
__device__ void cholesky(float* el, const unsigned int ndim) {
const unsigned int tid = threadIdx.x;
// Dunno how to parallelize this part...
if (tid == 0) {
float sum = 0;
int i, j, k;
//if (el.ncols() != n) throw("need square matrix");
for (i=0; i<ndim; i++) {
for (j=i; j<ndim; j++) {
sum = el[__umul24(i, ndim)+j];
for (k=i-1; k >= 0; k--) {
sum -= el[__umul24(i, ndim)+k] * el[__umul24(j, ndim)+k];
}
if (i == j) {
//if (sum <= 0.0)
// throw("Cholesky failed");
el[__umul24(i, ndim)+i] = sqrt(sum);
} else {
el[__umul24(j, ndim)+i] = sum/el[__umul24(i, ndim)+i];
}
}
}
}
__syncthreads();
// Clear lower triangular part.
if ((tid/ndim) < (tid%ndim)) {
el[__umul24((tid/ndim), ndim) + (tid%ndim)] = 0.0f;
}
}
///////////////////////////////////////////////////////////////////////////
__device__ float logdet(float* el, const unsigned int ndim) {
float sum = 0.0f;
for (unsigned int i=0; i<ndim; ++i) {
sum += __logf(el[(i*ndim)+i]);
}
return 2.*sum;
}
///////////////////////////////////////////////////////////////////////////
__device__ float parallelSum(float* data, const unsigned int ndata) {
const unsigned int tid = threadIdx.x;
float t;
__syncthreads();
// Butterfly sum. ndata MUST be a power of 2.
for(unsigned int bit = ndata >> 1; bit > 0; bit >>= 1) {
t = data[tid] + data[tid^bit]; __syncthreads();
data[tid] = t; __syncthreads();
}
return data[tid];
}
///////////////////////////////////////////////////////////////////////////
__device__ void copyArray(float* fromArr, float* toArr, unsigned int ndata=BLOCK_SIZE) {
unsigned int n;
unsigned int base_off;
for (base_off=0; base_off < ndata; base_off += blockDim.x) {
n = base_off + threadIdx.x;
if (n < ndata) {
toArr[n] = fromArr[n];
}
}
}
///////////////////////////////////////////////////////////////////////////
// Parallel reduction, for when all you want is the sum of a certain
// quantity computed for every 1 to N. CODE should be something in terms
// of n. The resulting sum will be placed in RESULT.
// tmp_buff, base_off, RESULT, and n must be previously defined, however
// they will be overwritten during the execution of the macro.
#define REDUCE(N, CODE, RESULT) \
base_off = 0; \
RESULT = 0.0f; \
while (base_off + BLOCK_SIZE < N) { \
n = base_off + tid; \
tmp_buff[tid] = CODE; \
RESULT += parallelSum(tmp_buff, BLOCK_SIZE); \
base_off += BLOCK_SIZE; \
} \
n = base_off + tid; \
if (n < N) {tmp_buff[tid] = CODE;} \
else {tmp_buff[tid] = 0.0f;} \
RESULT += parallelSum(tmp_buff, BLOCK_SIZE);
///////////////////////////////////////////////////////////////////////////
// This function computes for a single cluster k.
__global__ void estep_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_, float* _lndets_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.y;
const unsigned int tid = threadIdx.x;
const unsigned int k = blockIdx.x;
const unsigned int sigsize = __umul24(num_dims, num_dims);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int sb = __umul24(try_num, num_clusts) * sigsize;
const unsigned int fb = __umul24(try_num, num_clusts);
const unsigned int lndb = __umul24(try_num, num_clusts);
unsigned int n, base_off;
float tmp, sum;
float v[MAX_DIM];
__shared__ float lndet_k;
__shared__ float frac_k;
__shared__ float chol[MAX_DIM * MAX_DIM];
__syncthreads();
copyArray(_sig_ + sb + __umul24(k, sigsize), chol, sigsize);
cholesky(chol, num_dims);
__syncthreads();
if (tid == 0) {
frac_k = _frac_[fb + k];
lndet_k = logdet(chol, num_dims);
_lndets_[lndb + k] = lndet_k;
}
__syncthreads();
// Loop through data.
for (base_off=0; base_off < num_data; base_off += BLOCK_SIZE) {
n = base_off + tid;
sum=0.0f;
//if (b.size() != n || y.size() != n) throw("bad lengths");
if (n < num_data) {
for (unsigned int i=0; i<num_dims; ++i) {
tmp = _data_[__umul24(i, num_data) + n] - _means_[mb + __umul24(k, num_dims)+i];
for (unsigned int j=0; j<i; j++) {
tmp -= chol[__umul24(i, num_dims)+j] * v[j];
}
v[i] = tmp/chol[__umul24(i, num_dims)+i];
sum += v[i] * v[i];
}
// Assign likelihood of this data being in this cluster.
_resp_[rb + n] = -0.5f*(sum + lndet_k) + __logf(frac_k);
}
} // (n < num_data)
}
///////////////////////////////////////////////////////////////////////////
// Loop through data again, normalizing probabilities.
// We are looping across clusters here as well as data, since every data
// point needs to know its potential parents.
__global__ void estep_normalize_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_, float* _lndets_,
float* _loglike_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.y;
const unsigned int num_chunks = gridDim.x;
const unsigned int chunk_num = blockIdx.x;
const unsigned int tid = threadIdx.x;
// We're only handling so many data points per block in this kernel, since
// data is independant of other data here.
const unsigned int n_per_block = ceil((float)num_data / (float)num_chunks);
const unsigned int start_off = __umul24(n_per_block, chunk_num);
const unsigned int end_off = min(start_off + n_per_block, num_data);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data;
const unsigned int lb = __umul24(try_num, num_chunks);
unsigned int n, base_off, k;
float sum, max, tmp;
__shared__ float loglike[BLOCK_SIZE];
loglike[tid] = 0.0f;
__syncthreads();
// Loop through data.
for (base_off = start_off; base_off < end_off; base_off += BLOCK_SIZE) {
n = base_off + tid;
if (n < end_off) {
max = -99.9e30f;
// Find cluster with maximum likelihood for this data point.
for (k=0; k<num_clusts; ++k) {
tmp = _resp_[rb + (k*num_data) + n];
if (tmp > max) {
max = tmp;
}
}
// Sum marginal probabilities.
sum = 0.0f;
for (k=0; k<num_clusts; ++k) {
sum += __expf(_resp_[rb + (k*num_data) + n] - max);
}
// Assign probabilities of point belonging to each cluster.
tmp = max + __logf(sum);
for (k = 0; k < num_clusts; ++k) {
_resp_[rb + (k*num_data) + n] =
__expf(_resp_[rb + (k*num_data) + n] - tmp);
}
loglike[tid] += tmp;
}
}
tmp = parallelSum(loglike, BLOCK_SIZE);
if (tid == 0) {
_loglike_[lb + chunk_num] = tmp;
}
}
///////////////////////////////////////////////////////////////////////////
__global__ void mstep_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.x / num_clusts;
const unsigned int tid = threadIdx.x;
// Every block is mapped to cluster and dimension.
const unsigned int k = blockIdx.x % num_clusts;
const unsigned int m = blockIdx.y;
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int fb = __umul24(try_num, num_clusts);
unsigned int n, base_off;
float wgt_k, sum_k_m;
__shared__ float tmp_buff[BLOCK_SIZE];
// Sum all weight assigned to cluster k.
REDUCE(num_data, _resp_[rb + n], wgt_k);
__syncthreads();
// Update fractional prior.
if (tid == 0 && m == 0) {
_frac_[fb + k] = wgt_k / (float)num_data;
}
__syncthreads();
// Only concerned about dimension m in this block.
// Sum will become the sum of movement in that direction for this cluster.
REDUCE(num_data, _resp_[rb + n] * _data_[(m*num_data)+n], sum_k_m);
__syncthreads();
if (tid == 0) {
_means_[mb + __umul24(k, num_dims) + m] = sum_k_m / wgt_k;
}
}
///////////////////////////////////////////////////////////////////////////
__global__ void mstep_sigma_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
// Every block is mapped to cluster and dimension pair.
const unsigned int try_num = blockIdx.x / num_clusts;
const unsigned int k = blockIdx.x % num_clusts;
const unsigned int m = blockIdx.y / num_dims;
const unsigned int j = blockIdx.y % num_dims;
const unsigned int tid = threadIdx.x;
const unsigned int sigsize = __umul24(num_dims, num_dims);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int sb = __umul24(try_num, num_clusts) * sigsize;
const unsigned int fb = __umul24(try_num, num_clusts);
const unsigned int db_m = (m*num_data);
const unsigned int db_j = (j*num_data);
unsigned int n, base_off;
__shared__ float tmp_buff[BLOCK_SIZE];
__shared__ float wgt_k;
__shared__ float mean_k_m;
if (tid == 0) {
wgt_k = _frac_[fb + k] * num_data;
mean_k_m = _means_[mb + __umul24(k, num_dims) + m];
}
__syncthreads();
float sum;
REDUCE(num_data,
_resp_[rb + n] *
(_data_[db_m + n] - mean_k_m) *
(_data_[db_j + n]),
sum);
// Set this block's Sigma val.
if (tid == 0) {
_sig_[sb +
(__umul24(k, sigsize)) +
(__umul24(m, num_dims)) + j] = sum / wgt_k;
}
} | .file "tmpxft_00021a4a_00000000-6_gpugaumixmod_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8choleskyPfj
.type _Z8choleskyPfj, @function
_Z8choleskyPfj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8choleskyPfj, .-_Z8choleskyPfj
.globl _Z6logdetPfj
.type _Z6logdetPfj, @function
_Z6logdetPfj:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z6logdetPfj, .-_Z6logdetPfj
.globl _Z11parallelSumPfj
.type _Z11parallelSumPfj, @function
_Z11parallelSumPfj:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11parallelSumPfj, .-_Z11parallelSumPfj
.globl _Z9copyArrayPfS_j
.type _Z9copyArrayPfS_j, @function
_Z9copyArrayPfS_j:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z9copyArrayPfS_j, .-_Z9copyArrayPfS_j
.globl _Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj
.type _Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj, @function
_Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj:
.LFB2055:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12estep_kernelPfS_S_S_S_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj, .-_Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj
.globl _Z12estep_kernelPfS_S_S_S_S_jjj
.type _Z12estep_kernelPfS_S_S_S_S_jjj, @function
_Z12estep_kernelPfS_S_S_S_S_jjj:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z12estep_kernelPfS_S_S_S_S_jjj, .-_Z12estep_kernelPfS_S_S_S_S_jjj
.globl _Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj
.type _Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj, @function
_Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj:
.LFB2057:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj, .-_Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj
.globl _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.type _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, @function
_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, .-_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.globl _Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
.type _Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj, @function
_Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj:
.LFB2059:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mstep_kernelPfS_S_S_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj, .-_Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
.globl _Z12mstep_kernelPfS_S_S_S_jjj
.type _Z12mstep_kernelPfS_S_S_S_jjj, @function
_Z12mstep_kernelPfS_S_S_S_jjj:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12mstep_kernelPfS_S_S_S_jjj, .-_Z12mstep_kernelPfS_S_S_S_jjj
.globl _Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
.type _Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj, @function
_Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj:
.LFB2061:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18mstep_sigma_kernelPfS_S_S_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj, .-_Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
.globl _Z18mstep_sigma_kernelPfS_S_S_S_jjj
.type _Z18mstep_sigma_kernelPfS_S_S_S_jjj, @function
_Z18mstep_sigma_kernelPfS_S_S_S_jjj:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z18mstep_sigma_kernelPfS_S_S_S_jjj, .-_Z18mstep_sigma_kernelPfS_S_S_S_jjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18mstep_sigma_kernelPfS_S_S_S_jjj"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z12mstep_kernelPfS_S_S_S_jjj"
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj"
.align 8
.LC3:
.string "_Z12estep_kernelPfS_S_S_S_S_jjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18mstep_sigma_kernelPfS_S_S_S_jjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mstep_kernelPfS_S_S_S_jjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12estep_kernelPfS_S_S_S_S_jjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Kernel code for Gaussian Mixture Model Expectation Maximization.
//
// Andrew Harp (andrew.harp@gmail.com)
// http://andrewharp.com/gmmcuda
// This effects the maximum dimensionality of your data.
// Has to be hardcoded because it affects memory allocation.
// Due to the way I clear out the lower triangle of the cholesky (and
// possibly other) places MAX_DIM * MAX_DIM needs to be less than
// BLOCK_SIZE.
#define MAX_DIM 16
// You can change this, but only to a power of 2.
#define BLOCK_SIZE 256
// Estep-normalize is broken down into an arbitrary number of chunks.
#define NUM_CHUNKS 32
#include "cuda_runtime.h"
///////////////////////////////////////////////////////////////////////////
__device__ void cholesky(float* el, const unsigned int ndim) {
const unsigned int tid = threadIdx.x;
// Dunno how to parallelize this part...
if (tid == 0) {
float sum = 0;
int i, j, k;
//if (el.ncols() != n) throw("need square matrix");
for (i=0; i<ndim; i++) {
for (j=i; j<ndim; j++) {
sum = el[__umul24(i, ndim)+j];
for (k=i-1; k >= 0; k--) {
sum -= el[__umul24(i, ndim)+k] * el[__umul24(j, ndim)+k];
}
if (i == j) {
//if (sum <= 0.0)
// throw("Cholesky failed");
el[__umul24(i, ndim)+i] = sqrt(sum);
} else {
el[__umul24(j, ndim)+i] = sum/el[__umul24(i, ndim)+i];
}
}
}
}
__syncthreads();
// Clear lower triangular part.
if ((tid/ndim) < (tid%ndim)) {
el[__umul24((tid/ndim), ndim) + (tid%ndim)] = 0.0f;
}
}
///////////////////////////////////////////////////////////////////////////
__device__ float logdet(float* el, const unsigned int ndim) {
float sum = 0.0f;
for (unsigned int i=0; i<ndim; ++i) {
sum += __logf(el[(i*ndim)+i]);
}
return 2.*sum;
}
///////////////////////////////////////////////////////////////////////////
__device__ float parallelSum(float* data, const unsigned int ndata) {
const unsigned int tid = threadIdx.x;
float t;
__syncthreads();
// Butterfly sum. ndata MUST be a power of 2.
for(unsigned int bit = ndata >> 1; bit > 0; bit >>= 1) {
t = data[tid] + data[tid^bit]; __syncthreads();
data[tid] = t; __syncthreads();
}
return data[tid];
}
///////////////////////////////////////////////////////////////////////////
__device__ void copyArray(float* fromArr, float* toArr, unsigned int ndata=BLOCK_SIZE) {
unsigned int n;
unsigned int base_off;
for (base_off=0; base_off < ndata; base_off += blockDim.x) {
n = base_off + threadIdx.x;
if (n < ndata) {
toArr[n] = fromArr[n];
}
}
}
///////////////////////////////////////////////////////////////////////////
// Parallel reduction, for when all you want is the sum of a certain
// quantity computed for every 1 to N. CODE should be something in terms
// of n. The resulting sum will be placed in RESULT.
// tmp_buff, base_off, RESULT, and n must be previously defined, however
// they will be overwritten during the execution of the macro.
#define REDUCE(N, CODE, RESULT) \
base_off = 0; \
RESULT = 0.0f; \
while (base_off + BLOCK_SIZE < N) { \
n = base_off + tid; \
tmp_buff[tid] = CODE; \
RESULT += parallelSum(tmp_buff, BLOCK_SIZE); \
base_off += BLOCK_SIZE; \
} \
n = base_off + tid; \
if (n < N) {tmp_buff[tid] = CODE;} \
else {tmp_buff[tid] = 0.0f;} \
RESULT += parallelSum(tmp_buff, BLOCK_SIZE);
///////////////////////////////////////////////////////////////////////////
// This function computes for a single cluster k.
__global__ void estep_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_, float* _lndets_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.y;
const unsigned int tid = threadIdx.x;
const unsigned int k = blockIdx.x;
const unsigned int sigsize = __umul24(num_dims, num_dims);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int sb = __umul24(try_num, num_clusts) * sigsize;
const unsigned int fb = __umul24(try_num, num_clusts);
const unsigned int lndb = __umul24(try_num, num_clusts);
unsigned int n, base_off;
float tmp, sum;
float v[MAX_DIM];
__shared__ float lndet_k;
__shared__ float frac_k;
__shared__ float chol[MAX_DIM * MAX_DIM];
__syncthreads();
copyArray(_sig_ + sb + __umul24(k, sigsize), chol, sigsize);
cholesky(chol, num_dims);
__syncthreads();
if (tid == 0) {
frac_k = _frac_[fb + k];
lndet_k = logdet(chol, num_dims);
_lndets_[lndb + k] = lndet_k;
}
__syncthreads();
// Loop through data.
for (base_off=0; base_off < num_data; base_off += BLOCK_SIZE) {
n = base_off + tid;
sum=0.0f;
//if (b.size() != n || y.size() != n) throw("bad lengths");
if (n < num_data) {
for (unsigned int i=0; i<num_dims; ++i) {
tmp = _data_[__umul24(i, num_data) + n] - _means_[mb + __umul24(k, num_dims)+i];
for (unsigned int j=0; j<i; j++) {
tmp -= chol[__umul24(i, num_dims)+j] * v[j];
}
v[i] = tmp/chol[__umul24(i, num_dims)+i];
sum += v[i] * v[i];
}
// Assign likelihood of this data being in this cluster.
_resp_[rb + n] = -0.5f*(sum + lndet_k) + __logf(frac_k);
}
} // (n < num_data)
}
///////////////////////////////////////////////////////////////////////////
// Loop through data again, normalizing probabilities.
// We are looping across clusters here as well as data, since every data
// point needs to know its potential parents.
__global__ void estep_normalize_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_, float* _lndets_,
float* _loglike_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.y;
const unsigned int num_chunks = gridDim.x;
const unsigned int chunk_num = blockIdx.x;
const unsigned int tid = threadIdx.x;
// We're only handling so many data points per block in this kernel, since
// data is independant of other data here.
const unsigned int n_per_block = ceil((float)num_data / (float)num_chunks);
const unsigned int start_off = __umul24(n_per_block, chunk_num);
const unsigned int end_off = min(start_off + n_per_block, num_data);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data;
const unsigned int lb = __umul24(try_num, num_chunks);
unsigned int n, base_off, k;
float sum, max, tmp;
__shared__ float loglike[BLOCK_SIZE];
loglike[tid] = 0.0f;
__syncthreads();
// Loop through data.
for (base_off = start_off; base_off < end_off; base_off += BLOCK_SIZE) {
n = base_off + tid;
if (n < end_off) {
max = -99.9e30f;
// Find cluster with maximum likelihood for this data point.
for (k=0; k<num_clusts; ++k) {
tmp = _resp_[rb + (k*num_data) + n];
if (tmp > max) {
max = tmp;
}
}
// Sum marginal probabilities.
sum = 0.0f;
for (k=0; k<num_clusts; ++k) {
sum += __expf(_resp_[rb + (k*num_data) + n] - max);
}
// Assign probabilities of point belonging to each cluster.
tmp = max + __logf(sum);
for (k = 0; k < num_clusts; ++k) {
_resp_[rb + (k*num_data) + n] =
__expf(_resp_[rb + (k*num_data) + n] - tmp);
}
loglike[tid] += tmp;
}
}
tmp = parallelSum(loglike, BLOCK_SIZE);
if (tid == 0) {
_loglike_[lb + chunk_num] = tmp;
}
}
///////////////////////////////////////////////////////////////////////////
__global__ void mstep_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.x / num_clusts;
const unsigned int tid = threadIdx.x;
// Every block is mapped to cluster and dimension.
const unsigned int k = blockIdx.x % num_clusts;
const unsigned int m = blockIdx.y;
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int fb = __umul24(try_num, num_clusts);
unsigned int n, base_off;
float wgt_k, sum_k_m;
__shared__ float tmp_buff[BLOCK_SIZE];
// Sum all weight assigned to cluster k.
REDUCE(num_data, _resp_[rb + n], wgt_k);
__syncthreads();
// Update fractional prior.
if (tid == 0 && m == 0) {
_frac_[fb + k] = wgt_k / (float)num_data;
}
__syncthreads();
// Only concerned about dimension m in this block.
// Sum will become the sum of movement in that direction for this cluster.
REDUCE(num_data, _resp_[rb + n] * _data_[(m*num_data)+n], sum_k_m);
__syncthreads();
if (tid == 0) {
_means_[mb + __umul24(k, num_dims) + m] = sum_k_m / wgt_k;
}
}
///////////////////////////////////////////////////////////////////////////
__global__ void mstep_sigma_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
// Every block is mapped to cluster and dimension pair.
const unsigned int try_num = blockIdx.x / num_clusts;
const unsigned int k = blockIdx.x % num_clusts;
const unsigned int m = blockIdx.y / num_dims;
const unsigned int j = blockIdx.y % num_dims;
const unsigned int tid = threadIdx.x;
const unsigned int sigsize = __umul24(num_dims, num_dims);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int sb = __umul24(try_num, num_clusts) * sigsize;
const unsigned int fb = __umul24(try_num, num_clusts);
const unsigned int db_m = (m*num_data);
const unsigned int db_j = (j*num_data);
unsigned int n, base_off;
__shared__ float tmp_buff[BLOCK_SIZE];
__shared__ float wgt_k;
__shared__ float mean_k_m;
if (tid == 0) {
wgt_k = _frac_[fb + k] * num_data;
mean_k_m = _means_[mb + __umul24(k, num_dims) + m];
}
__syncthreads();
float sum;
REDUCE(num_data,
_resp_[rb + n] *
(_data_[db_m + n] - mean_k_m) *
(_data_[db_j + n]),
sum);
// Set this block's Sigma val.
if (tid == 0) {
_sig_[sb +
(__umul24(k, sigsize)) +
(__umul24(m, num_dims)) + j] = sum / wgt_k;
}
} | // Kernel code for Gaussian Mixture Model Expectation Maximization.
//
// Andrew Harp (andrew.harp@gmail.com)
// http://andrewharp.com/gmmcuda
// This effects the maximum dimensionality of your data.
// Has to be hardcoded because it affects memory allocation.
// Due to the way I clear out the lower triangle of the cholesky (and
// possibly other) places MAX_DIM * MAX_DIM needs to be less than
// BLOCK_SIZE.
#define MAX_DIM 16
// You can change this, but only to a power of 2.
#define BLOCK_SIZE 256
// Estep-normalize is broken down into an arbitrary number of chunks.
#define NUM_CHUNKS 32
#include "hip/hip_runtime.h"
///////////////////////////////////////////////////////////////////////////
__device__ void cholesky(float* el, const unsigned int ndim) {
const unsigned int tid = threadIdx.x;
// Dunno how to parallelize this part...
if (tid == 0) {
float sum = 0;
int i, j, k;
//if (el.ncols() != n) throw("need square matrix");
for (i=0; i<ndim; i++) {
for (j=i; j<ndim; j++) {
sum = el[__umul24(i, ndim)+j];
for (k=i-1; k >= 0; k--) {
sum -= el[__umul24(i, ndim)+k] * el[__umul24(j, ndim)+k];
}
if (i == j) {
//if (sum <= 0.0)
// throw("Cholesky failed");
el[__umul24(i, ndim)+i] = sqrt(sum);
} else {
el[__umul24(j, ndim)+i] = sum/el[__umul24(i, ndim)+i];
}
}
}
}
__syncthreads();
// Clear lower triangular part.
if ((tid/ndim) < (tid%ndim)) {
el[__umul24((tid/ndim), ndim) + (tid%ndim)] = 0.0f;
}
}
///////////////////////////////////////////////////////////////////////////
__device__ float logdet(float* el, const unsigned int ndim) {
float sum = 0.0f;
for (unsigned int i=0; i<ndim; ++i) {
sum += __logf(el[(i*ndim)+i]);
}
return 2.*sum;
}
///////////////////////////////////////////////////////////////////////////
__device__ float parallelSum(float* data, const unsigned int ndata) {
const unsigned int tid = threadIdx.x;
float t;
__syncthreads();
// Butterfly sum. ndata MUST be a power of 2.
for(unsigned int bit = ndata >> 1; bit > 0; bit >>= 1) {
t = data[tid] + data[tid^bit]; __syncthreads();
data[tid] = t; __syncthreads();
}
return data[tid];
}
///////////////////////////////////////////////////////////////////////////
__device__ void copyArray(float* fromArr, float* toArr, unsigned int ndata=BLOCK_SIZE) {
unsigned int n;
unsigned int base_off;
for (base_off=0; base_off < ndata; base_off += blockDim.x) {
n = base_off + threadIdx.x;
if (n < ndata) {
toArr[n] = fromArr[n];
}
}
}
///////////////////////////////////////////////////////////////////////////
// Parallel reduction, for when all you want is the sum of a certain
// quantity computed for every 1 to N. CODE should be something in terms
// of n. The resulting sum will be placed in RESULT.
// tmp_buff, base_off, RESULT, and n must be previously defined, however
// they will be overwritten during the execution of the macro.
#define REDUCE(N, CODE, RESULT) \
base_off = 0; \
RESULT = 0.0f; \
while (base_off + BLOCK_SIZE < N) { \
n = base_off + tid; \
tmp_buff[tid] = CODE; \
RESULT += parallelSum(tmp_buff, BLOCK_SIZE); \
base_off += BLOCK_SIZE; \
} \
n = base_off + tid; \
if (n < N) {tmp_buff[tid] = CODE;} \
else {tmp_buff[tid] = 0.0f;} \
RESULT += parallelSum(tmp_buff, BLOCK_SIZE);
///////////////////////////////////////////////////////////////////////////
// This function computes for a single cluster k.
__global__ void estep_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_, float* _lndets_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.y;
const unsigned int tid = threadIdx.x;
const unsigned int k = blockIdx.x;
const unsigned int sigsize = __umul24(num_dims, num_dims);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int sb = __umul24(try_num, num_clusts) * sigsize;
const unsigned int fb = __umul24(try_num, num_clusts);
const unsigned int lndb = __umul24(try_num, num_clusts);
unsigned int n, base_off;
float tmp, sum;
float v[MAX_DIM];
__shared__ float lndet_k;
__shared__ float frac_k;
__shared__ float chol[MAX_DIM * MAX_DIM];
__syncthreads();
copyArray(_sig_ + sb + __umul24(k, sigsize), chol, sigsize);
cholesky(chol, num_dims);
__syncthreads();
if (tid == 0) {
frac_k = _frac_[fb + k];
lndet_k = logdet(chol, num_dims);
_lndets_[lndb + k] = lndet_k;
}
__syncthreads();
// Loop through data.
for (base_off=0; base_off < num_data; base_off += BLOCK_SIZE) {
n = base_off + tid;
sum=0.0f;
//if (b.size() != n || y.size() != n) throw("bad lengths");
if (n < num_data) {
for (unsigned int i=0; i<num_dims; ++i) {
tmp = _data_[__umul24(i, num_data) + n] - _means_[mb + __umul24(k, num_dims)+i];
for (unsigned int j=0; j<i; j++) {
tmp -= chol[__umul24(i, num_dims)+j] * v[j];
}
v[i] = tmp/chol[__umul24(i, num_dims)+i];
sum += v[i] * v[i];
}
// Assign likelihood of this data being in this cluster.
_resp_[rb + n] = -0.5f*(sum + lndet_k) + __logf(frac_k);
}
} // (n < num_data)
}
///////////////////////////////////////////////////////////////////////////
// Loop through data again, normalizing probabilities.
// We are looping across clusters here as well as data, since every data
// point needs to know its potential parents.
__global__ void estep_normalize_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_, float* _lndets_,
float* _loglike_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.y;
const unsigned int num_chunks = gridDim.x;
const unsigned int chunk_num = blockIdx.x;
const unsigned int tid = threadIdx.x;
// We're only handling so many data points per block in this kernel, since
// data is independant of other data here.
const unsigned int n_per_block = ceil((float)num_data / (float)num_chunks);
const unsigned int start_off = __umul24(n_per_block, chunk_num);
const unsigned int end_off = min(start_off + n_per_block, num_data);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data;
const unsigned int lb = __umul24(try_num, num_chunks);
unsigned int n, base_off, k;
float sum, max, tmp;
__shared__ float loglike[BLOCK_SIZE];
loglike[tid] = 0.0f;
__syncthreads();
// Loop through data.
for (base_off = start_off; base_off < end_off; base_off += BLOCK_SIZE) {
n = base_off + tid;
if (n < end_off) {
max = -99.9e30f;
// Find cluster with maximum likelihood for this data point.
for (k=0; k<num_clusts; ++k) {
tmp = _resp_[rb + (k*num_data) + n];
if (tmp > max) {
max = tmp;
}
}
// Sum marginal probabilities.
sum = 0.0f;
for (k=0; k<num_clusts; ++k) {
sum += __expf(_resp_[rb + (k*num_data) + n] - max);
}
// Assign probabilities of point belonging to each cluster.
tmp = max + __logf(sum);
for (k = 0; k < num_clusts; ++k) {
_resp_[rb + (k*num_data) + n] =
__expf(_resp_[rb + (k*num_data) + n] - tmp);
}
loglike[tid] += tmp;
}
}
tmp = parallelSum(loglike, BLOCK_SIZE);
if (tid == 0) {
_loglike_[lb + chunk_num] = tmp;
}
}
///////////////////////////////////////////////////////////////////////////
__global__ void mstep_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.x / num_clusts;
const unsigned int tid = threadIdx.x;
// Every block is mapped to cluster and dimension.
const unsigned int k = blockIdx.x % num_clusts;
const unsigned int m = blockIdx.y;
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int fb = __umul24(try_num, num_clusts);
unsigned int n, base_off;
float wgt_k, sum_k_m;
__shared__ float tmp_buff[BLOCK_SIZE];
// Sum all weight assigned to cluster k.
REDUCE(num_data, _resp_[rb + n], wgt_k);
__syncthreads();
// Update fractional prior.
if (tid == 0 && m == 0) {
_frac_[fb + k] = wgt_k / (float)num_data;
}
__syncthreads();
// Only concerned about dimension m in this block.
// Sum will become the sum of movement in that direction for this cluster.
REDUCE(num_data, _resp_[rb + n] * _data_[(m*num_data)+n], sum_k_m);
__syncthreads();
if (tid == 0) {
_means_[mb + __umul24(k, num_dims) + m] = sum_k_m / wgt_k;
}
}
///////////////////////////////////////////////////////////////////////////
__global__ void mstep_sigma_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
// Every block is mapped to cluster and dimension pair.
const unsigned int try_num = blockIdx.x / num_clusts;
const unsigned int k = blockIdx.x % num_clusts;
const unsigned int m = blockIdx.y / num_dims;
const unsigned int j = blockIdx.y % num_dims;
const unsigned int tid = threadIdx.x;
const unsigned int sigsize = __umul24(num_dims, num_dims);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int sb = __umul24(try_num, num_clusts) * sigsize;
const unsigned int fb = __umul24(try_num, num_clusts);
const unsigned int db_m = (m*num_data);
const unsigned int db_j = (j*num_data);
unsigned int n, base_off;
__shared__ float tmp_buff[BLOCK_SIZE];
__shared__ float wgt_k;
__shared__ float mean_k_m;
if (tid == 0) {
wgt_k = _frac_[fb + k] * num_data;
mean_k_m = _means_[mb + __umul24(k, num_dims) + m];
}
__syncthreads();
float sum;
REDUCE(num_data,
_resp_[rb + n] *
(_data_[db_m + n] - mean_k_m) *
(_data_[db_j + n]),
sum);
// Set this block's Sigma val.
if (tid == 0) {
_sig_[sb +
(__umul24(k, sigsize)) +
(__umul24(m, num_dims)) + j] = sum / wgt_k;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Kernel code for Gaussian Mixture Model Expectation Maximization.
//
// Andrew Harp (andrew.harp@gmail.com)
// http://andrewharp.com/gmmcuda
// This effects the maximum dimensionality of your data.
// Has to be hardcoded because it affects memory allocation.
// Due to the way I clear out the lower triangle of the cholesky (and
// possibly other) places MAX_DIM * MAX_DIM needs to be less than
// BLOCK_SIZE.
#define MAX_DIM 16
// You can change this, but only to a power of 2.
#define BLOCK_SIZE 256
// Estep-normalize is broken down into an arbitrary number of chunks.
#define NUM_CHUNKS 32
#include "hip/hip_runtime.h"
///////////////////////////////////////////////////////////////////////////
__device__ void cholesky(float* el, const unsigned int ndim) {
const unsigned int tid = threadIdx.x;
// Dunno how to parallelize this part...
if (tid == 0) {
float sum = 0;
int i, j, k;
//if (el.ncols() != n) throw("need square matrix");
for (i=0; i<ndim; i++) {
for (j=i; j<ndim; j++) {
sum = el[__umul24(i, ndim)+j];
for (k=i-1; k >= 0; k--) {
sum -= el[__umul24(i, ndim)+k] * el[__umul24(j, ndim)+k];
}
if (i == j) {
//if (sum <= 0.0)
// throw("Cholesky failed");
el[__umul24(i, ndim)+i] = sqrt(sum);
} else {
el[__umul24(j, ndim)+i] = sum/el[__umul24(i, ndim)+i];
}
}
}
}
__syncthreads();
// Clear lower triangular part.
if ((tid/ndim) < (tid%ndim)) {
el[__umul24((tid/ndim), ndim) + (tid%ndim)] = 0.0f;
}
}
///////////////////////////////////////////////////////////////////////////
__device__ float logdet(float* el, const unsigned int ndim) {
float sum = 0.0f;
for (unsigned int i=0; i<ndim; ++i) {
sum += __logf(el[(i*ndim)+i]);
}
return 2.*sum;
}
///////////////////////////////////////////////////////////////////////////
__device__ float parallelSum(float* data, const unsigned int ndata) {
const unsigned int tid = threadIdx.x;
float t;
__syncthreads();
// Butterfly sum. ndata MUST be a power of 2.
for(unsigned int bit = ndata >> 1; bit > 0; bit >>= 1) {
t = data[tid] + data[tid^bit]; __syncthreads();
data[tid] = t; __syncthreads();
}
return data[tid];
}
///////////////////////////////////////////////////////////////////////////
__device__ void copyArray(float* fromArr, float* toArr, unsigned int ndata=BLOCK_SIZE) {
unsigned int n;
unsigned int base_off;
for (base_off=0; base_off < ndata; base_off += blockDim.x) {
n = base_off + threadIdx.x;
if (n < ndata) {
toArr[n] = fromArr[n];
}
}
}
///////////////////////////////////////////////////////////////////////////
// Parallel reduction, for when all you want is the sum of a certain
// quantity computed for every 1 to N. CODE should be something in terms
// of n. The resulting sum will be placed in RESULT.
// tmp_buff, base_off, RESULT, and n must be previously defined, however
// they will be overwritten during the execution of the macro.
#define REDUCE(N, CODE, RESULT) \
base_off = 0; \
RESULT = 0.0f; \
while (base_off + BLOCK_SIZE < N) { \
n = base_off + tid; \
tmp_buff[tid] = CODE; \
RESULT += parallelSum(tmp_buff, BLOCK_SIZE); \
base_off += BLOCK_SIZE; \
} \
n = base_off + tid; \
if (n < N) {tmp_buff[tid] = CODE;} \
else {tmp_buff[tid] = 0.0f;} \
RESULT += parallelSum(tmp_buff, BLOCK_SIZE);
///////////////////////////////////////////////////////////////////////////
// This function computes for a single cluster k.
__global__ void estep_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_, float* _lndets_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.y;
const unsigned int tid = threadIdx.x;
const unsigned int k = blockIdx.x;
const unsigned int sigsize = __umul24(num_dims, num_dims);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int sb = __umul24(try_num, num_clusts) * sigsize;
const unsigned int fb = __umul24(try_num, num_clusts);
const unsigned int lndb = __umul24(try_num, num_clusts);
unsigned int n, base_off;
float tmp, sum;
float v[MAX_DIM];
__shared__ float lndet_k;
__shared__ float frac_k;
__shared__ float chol[MAX_DIM * MAX_DIM];
__syncthreads();
copyArray(_sig_ + sb + __umul24(k, sigsize), chol, sigsize);
cholesky(chol, num_dims);
__syncthreads();
if (tid == 0) {
frac_k = _frac_[fb + k];
lndet_k = logdet(chol, num_dims);
_lndets_[lndb + k] = lndet_k;
}
__syncthreads();
// Loop through data.
for (base_off=0; base_off < num_data; base_off += BLOCK_SIZE) {
n = base_off + tid;
sum=0.0f;
//if (b.size() != n || y.size() != n) throw("bad lengths");
if (n < num_data) {
for (unsigned int i=0; i<num_dims; ++i) {
tmp = _data_[__umul24(i, num_data) + n] - _means_[mb + __umul24(k, num_dims)+i];
for (unsigned int j=0; j<i; j++) {
tmp -= chol[__umul24(i, num_dims)+j] * v[j];
}
v[i] = tmp/chol[__umul24(i, num_dims)+i];
sum += v[i] * v[i];
}
// Assign likelihood of this data being in this cluster.
_resp_[rb + n] = -0.5f*(sum + lndet_k) + __logf(frac_k);
}
} // (n < num_data)
}
///////////////////////////////////////////////////////////////////////////
// Loop through data again, normalizing probabilities.
// We are looping across clusters here as well as data, since every data
// point needs to know its potential parents.
__global__ void estep_normalize_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_, float* _lndets_,
float* _loglike_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.y;
const unsigned int num_chunks = gridDim.x;
const unsigned int chunk_num = blockIdx.x;
const unsigned int tid = threadIdx.x;
// We're only handling so many data points per block in this kernel, since
// data is independant of other data here.
const unsigned int n_per_block = ceil((float)num_data / (float)num_chunks);
const unsigned int start_off = __umul24(n_per_block, chunk_num);
const unsigned int end_off = min(start_off + n_per_block, num_data);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data;
const unsigned int lb = __umul24(try_num, num_chunks);
unsigned int n, base_off, k;
float sum, max, tmp;
__shared__ float loglike[BLOCK_SIZE];
loglike[tid] = 0.0f;
__syncthreads();
// Loop through data.
for (base_off = start_off; base_off < end_off; base_off += BLOCK_SIZE) {
n = base_off + tid;
if (n < end_off) {
max = -99.9e30f;
// Find cluster with maximum likelihood for this data point.
for (k=0; k<num_clusts; ++k) {
tmp = _resp_[rb + (k*num_data) + n];
if (tmp > max) {
max = tmp;
}
}
// Sum marginal probabilities.
sum = 0.0f;
for (k=0; k<num_clusts; ++k) {
sum += __expf(_resp_[rb + (k*num_data) + n] - max);
}
// Assign probabilities of point belonging to each cluster.
tmp = max + __logf(sum);
for (k = 0; k < num_clusts; ++k) {
_resp_[rb + (k*num_data) + n] =
__expf(_resp_[rb + (k*num_data) + n] - tmp);
}
loglike[tid] += tmp;
}
}
tmp = parallelSum(loglike, BLOCK_SIZE);
if (tid == 0) {
_loglike_[lb + chunk_num] = tmp;
}
}
///////////////////////////////////////////////////////////////////////////
__global__ void mstep_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
const unsigned int try_num = blockIdx.x / num_clusts;
const unsigned int tid = threadIdx.x;
// Every block is mapped to cluster and dimension.
const unsigned int k = blockIdx.x % num_clusts;
const unsigned int m = blockIdx.y;
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int fb = __umul24(try_num, num_clusts);
unsigned int n, base_off;
float wgt_k, sum_k_m;
__shared__ float tmp_buff[BLOCK_SIZE];
// Sum all weight assigned to cluster k.
REDUCE(num_data, _resp_[rb + n], wgt_k);
__syncthreads();
// Update fractional prior.
if (tid == 0 && m == 0) {
_frac_[fb + k] = wgt_k / (float)num_data;
}
__syncthreads();
// Only concerned about dimension m in this block.
// Sum will become the sum of movement in that direction for this cluster.
REDUCE(num_data, _resp_[rb + n] * _data_[(m*num_data)+n], sum_k_m);
__syncthreads();
if (tid == 0) {
_means_[mb + __umul24(k, num_dims) + m] = sum_k_m / wgt_k;
}
}
///////////////////////////////////////////////////////////////////////////
__global__ void mstep_sigma_kernel(float* _resp_, float* _frac_,
float* _data_, float* _means_,
float* _sig_,
const unsigned int num_clusts,
const unsigned int num_dims,
const unsigned int num_data) {
// Every block is mapped to cluster and dimension pair.
const unsigned int try_num = blockIdx.x / num_clusts;
const unsigned int k = blockIdx.x % num_clusts;
const unsigned int m = blockIdx.y / num_dims;
const unsigned int j = blockIdx.y % num_dims;
const unsigned int tid = threadIdx.x;
const unsigned int sigsize = __umul24(num_dims, num_dims);
// Base offsets.
const unsigned int rb = __umul24(try_num, num_clusts) * num_data + (k*num_data);
const unsigned int mb = __umul24(try_num, num_clusts) * num_dims;
const unsigned int sb = __umul24(try_num, num_clusts) * sigsize;
const unsigned int fb = __umul24(try_num, num_clusts);
const unsigned int db_m = (m*num_data);
const unsigned int db_j = (j*num_data);
unsigned int n, base_off;
__shared__ float tmp_buff[BLOCK_SIZE];
__shared__ float wgt_k;
__shared__ float mean_k_m;
if (tid == 0) {
wgt_k = _frac_[fb + k] * num_data;
mean_k_m = _means_[mb + __umul24(k, num_dims) + m];
}
__syncthreads();
float sum;
REDUCE(num_data,
_resp_[rb + n] *
(_data_[db_m + n] - mean_k_m) *
(_data_[db_j + n]),
sum);
// Set this block's Sigma val.
if (tid == 0) {
_sig_[sb +
(__umul24(k, sigsize)) +
(__umul24(m, num_dims)) + j] = sum / wgt_k;
}
} | .text
.file "gpugaumixmod_kernel.hip"
.globl _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj # -- Begin function _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.p2align 4, 0x90
.type _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj,@function
_Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj: # @_Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12estep_kernelPfS_S_S_S_S_jjj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj, .Lfunc_end0-_Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.cfi_endproc
# -- End function
.globl _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj # -- Begin function _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.p2align 4, 0x90
.type _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj,@function
_Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj: # @_Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj, .Lfunc_end1-_Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.cfi_endproc
# -- End function
.globl _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj # -- Begin function _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.p2align 4, 0x90
.type _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj,@function
_Z27__device_stub__mstep_kernelPfS_S_S_S_jjj: # @_Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mstep_kernelPfS_S_S_S_jjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj, .Lfunc_end2-_Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.cfi_endproc
# -- End function
.globl _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj # -- Begin function _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.p2align 4, 0x90
.type _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj,@function
_Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj: # @_Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18mstep_sigma_kernelPfS_S_S_S_jjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end3:
.size _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj, .Lfunc_end3-_Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12estep_kernelPfS_S_S_S_S_jjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mstep_kernelPfS_S_S_S_jjj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18mstep_sigma_kernelPfS_S_S_S_jjj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12estep_kernelPfS_S_S_S_S_jjj,@object # @_Z12estep_kernelPfS_S_S_S_S_jjj
.section .rodata,"a",@progbits
.globl _Z12estep_kernelPfS_S_S_S_S_jjj
.p2align 3, 0x0
_Z12estep_kernelPfS_S_S_S_S_jjj:
.quad _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.size _Z12estep_kernelPfS_S_S_S_S_jjj, 8
.type _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj,@object # @_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.globl _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.p2align 3, 0x0
_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj:
.quad _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.size _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, 8
.type _Z12mstep_kernelPfS_S_S_S_jjj,@object # @_Z12mstep_kernelPfS_S_S_S_jjj
.globl _Z12mstep_kernelPfS_S_S_S_jjj
.p2align 3, 0x0
_Z12mstep_kernelPfS_S_S_S_jjj:
.quad _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.size _Z12mstep_kernelPfS_S_S_S_jjj, 8
.type _Z18mstep_sigma_kernelPfS_S_S_S_jjj,@object # @_Z18mstep_sigma_kernelPfS_S_S_S_jjj
.globl _Z18mstep_sigma_kernelPfS_S_S_S_jjj
.p2align 3, 0x0
_Z18mstep_sigma_kernelPfS_S_S_S_jjj:
.quad _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.size _Z18mstep_sigma_kernelPfS_S_S_S_jjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12estep_kernelPfS_S_S_S_S_jjj"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj"
.size .L__unnamed_2, 44
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12mstep_kernelPfS_S_S_S_jjj"
.size .L__unnamed_3, 30
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z18mstep_sigma_kernelPfS_S_S_S_jjj"
.size .L__unnamed_4, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.addrsig_sym _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.addrsig_sym _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.addrsig_sym _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12estep_kernelPfS_S_S_S_S_jjj
.addrsig_sym _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.addrsig_sym _Z12mstep_kernelPfS_S_S_S_jjj
.addrsig_sym _Z18mstep_sigma_kernelPfS_S_S_S_jjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00021a4a_00000000-6_gpugaumixmod_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8choleskyPfj
.type _Z8choleskyPfj, @function
_Z8choleskyPfj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8choleskyPfj, .-_Z8choleskyPfj
.globl _Z6logdetPfj
.type _Z6logdetPfj, @function
_Z6logdetPfj:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z6logdetPfj, .-_Z6logdetPfj
.globl _Z11parallelSumPfj
.type _Z11parallelSumPfj, @function
_Z11parallelSumPfj:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11parallelSumPfj, .-_Z11parallelSumPfj
.globl _Z9copyArrayPfS_j
.type _Z9copyArrayPfS_j, @function
_Z9copyArrayPfS_j:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z9copyArrayPfS_j, .-_Z9copyArrayPfS_j
.globl _Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj
.type _Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj, @function
_Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj:
.LFB2055:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12estep_kernelPfS_S_S_S_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj, .-_Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj
.globl _Z12estep_kernelPfS_S_S_S_S_jjj
.type _Z12estep_kernelPfS_S_S_S_S_jjj, @function
_Z12estep_kernelPfS_S_S_S_S_jjj:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z45__device_stub__Z12estep_kernelPfS_S_S_S_S_jjjPfS_S_S_S_S_jjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z12estep_kernelPfS_S_S_S_S_jjj, .-_Z12estep_kernelPfS_S_S_S_S_jjj
.globl _Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj
.type _Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj, @function
_Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj:
.LFB2057:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj, .-_Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj
.globl _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.type _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, @function
_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z57__device_stub__Z22estep_normalize_kernelPfS_S_S_S_S_S_jjjPfS_S_S_S_S_S_jjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, .-_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.globl _Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
.type _Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj, @function
_Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj:
.LFB2059:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mstep_kernelPfS_S_S_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj, .-_Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
.globl _Z12mstep_kernelPfS_S_S_S_jjj
.type _Z12mstep_kernelPfS_S_S_S_jjj, @function
_Z12mstep_kernelPfS_S_S_S_jjj:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z12mstep_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12mstep_kernelPfS_S_S_S_jjj, .-_Z12mstep_kernelPfS_S_S_S_jjj
.globl _Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
.type _Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj, @function
_Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj:
.LFB2061:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18mstep_sigma_kernelPfS_S_S_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj, .-_Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
.globl _Z18mstep_sigma_kernelPfS_S_S_S_jjj
.type _Z18mstep_sigma_kernelPfS_S_S_S_jjj, @function
_Z18mstep_sigma_kernelPfS_S_S_S_jjj:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z18mstep_sigma_kernelPfS_S_S_S_jjjPfS_S_S_S_jjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z18mstep_sigma_kernelPfS_S_S_S_jjj, .-_Z18mstep_sigma_kernelPfS_S_S_S_jjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18mstep_sigma_kernelPfS_S_S_S_jjj"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z12mstep_kernelPfS_S_S_S_jjj"
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj"
.align 8
.LC3:
.string "_Z12estep_kernelPfS_S_S_S_S_jjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18mstep_sigma_kernelPfS_S_S_S_jjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mstep_kernelPfS_S_S_S_jjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12estep_kernelPfS_S_S_S_S_jjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpugaumixmod_kernel.hip"
.globl _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj # -- Begin function _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.p2align 4, 0x90
.type _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj,@function
_Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj: # @_Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12estep_kernelPfS_S_S_S_S_jjj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj, .Lfunc_end0-_Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.cfi_endproc
# -- End function
.globl _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj # -- Begin function _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.p2align 4, 0x90
.type _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj,@function
_Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj: # @_Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj, .Lfunc_end1-_Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.cfi_endproc
# -- End function
.globl _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj # -- Begin function _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.p2align 4, 0x90
.type _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj,@function
_Z27__device_stub__mstep_kernelPfS_S_S_S_jjj: # @_Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mstep_kernelPfS_S_S_S_jjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj, .Lfunc_end2-_Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.cfi_endproc
# -- End function
.globl _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj # -- Begin function _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.p2align 4, 0x90
.type _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj,@function
_Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj: # @_Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18mstep_sigma_kernelPfS_S_S_S_jjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end3:
.size _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj, .Lfunc_end3-_Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12estep_kernelPfS_S_S_S_S_jjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mstep_kernelPfS_S_S_S_jjj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18mstep_sigma_kernelPfS_S_S_S_jjj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12estep_kernelPfS_S_S_S_S_jjj,@object # @_Z12estep_kernelPfS_S_S_S_S_jjj
.section .rodata,"a",@progbits
.globl _Z12estep_kernelPfS_S_S_S_S_jjj
.p2align 3, 0x0
_Z12estep_kernelPfS_S_S_S_S_jjj:
.quad _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.size _Z12estep_kernelPfS_S_S_S_S_jjj, 8
.type _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj,@object # @_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.globl _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.p2align 3, 0x0
_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj:
.quad _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.size _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj, 8
.type _Z12mstep_kernelPfS_S_S_S_jjj,@object # @_Z12mstep_kernelPfS_S_S_S_jjj
.globl _Z12mstep_kernelPfS_S_S_S_jjj
.p2align 3, 0x0
_Z12mstep_kernelPfS_S_S_S_jjj:
.quad _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.size _Z12mstep_kernelPfS_S_S_S_jjj, 8
.type _Z18mstep_sigma_kernelPfS_S_S_S_jjj,@object # @_Z18mstep_sigma_kernelPfS_S_S_S_jjj
.globl _Z18mstep_sigma_kernelPfS_S_S_S_jjj
.p2align 3, 0x0
_Z18mstep_sigma_kernelPfS_S_S_S_jjj:
.quad _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.size _Z18mstep_sigma_kernelPfS_S_S_S_jjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12estep_kernelPfS_S_S_S_S_jjj"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj"
.size .L__unnamed_2, 44
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12mstep_kernelPfS_S_S_S_jjj"
.size .L__unnamed_3, 30
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z18mstep_sigma_kernelPfS_S_S_S_jjj"
.size .L__unnamed_4, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__estep_kernelPfS_S_S_S_S_jjj
.addrsig_sym _Z37__device_stub__estep_normalize_kernelPfS_S_S_S_S_S_jjj
.addrsig_sym _Z27__device_stub__mstep_kernelPfS_S_S_S_jjj
.addrsig_sym _Z33__device_stub__mstep_sigma_kernelPfS_S_S_S_jjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12estep_kernelPfS_S_S_S_S_jjj
.addrsig_sym _Z22estep_normalize_kernelPfS_S_S_S_S_S_jjj
.addrsig_sym _Z12mstep_kernelPfS_S_S_S_jjj
.addrsig_sym _Z18mstep_sigma_kernelPfS_S_S_S_jjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // #include <ATen/ATen.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdio>
#include <cmath>
#include <iostream>
namespace {
template <typename scalar_t>
__device__ __forceinline__ void single_mul(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
scalar_t uavc = x_re * (y_re + y_im);
*out_re += uavc - (x_re + x_im) * y_im;
*out_im += (x_im - x_re) * y_re + uavc;
}
template <typename scalar_t>
__device__ __forceinline__ void single_add(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
*out_re += x_re + y_re;
*out_im += x_im + y_im;
}
/**
Complex multiplication of tensors using shared memory and barrier
synchronization.
Compute the element wise complex multiplication for each thread in the block and
write the result to the shared memory. Then synchronize the threads and in the
log based fashion sum up the results for each output pixel through its channels,
if they are present in the cache. The stride is the number of threads per block
times the I (the two float representation of the complex numbers).
*/
template <typename scalar_t>
__global__ void complex_mul_cuda_kernel(
const scalar_t* __restrict__ x,
const scalar_t* __restrict__ y,
scalar_t* __restrict__ out,
const int N, const int F, const int C, const int H, const int W) {
// The size of the shared memory cache should be twice the number of threads
// per block as we store the real and imaginary part of the result.
extern __shared__ float cache[]; // cache for the result of the complex multiplication
const int I = 2; // the last dimension for the complex number
const int plane_size = H * W;
const int channel_size = plane_size * I;
const int image_size = C * channel_size; // size of the image from the batch
// number of complex values in the input that we iterate through
const int nr_values = C * H * W;
const int n = blockIdx.x; // current index of an image/input map in the batch
const int f = blockIdx.y; // current index of a filter from the filter bank
const int block_size = blockDim.x;
const int thread_nr = threadIdx.x;
// stride for the H*W map is equal to the number of threads declared in a block
const int stride = block_size * I; // we need H*W threads per plane, each deals with I numbers
const int n_idx = n * image_size; // start index in the batch for this input map
const int f_idx = f * image_size; // start index in the bank for this filter
// find index for the output
const int no_idx = n * (F * channel_size); // output index for the batch data point
const int fo_idx = f * channel_size; // output index for the filter/channel
// Each H*W plane contains H*W*I elements in depth.
// We linearize it and start from 0, move by #threads*I steps in outer loop.
const int start_idx = threadIdx.x*I;
// index in the input map
int N_idx = n_idx + start_idx; // index across the first channel plane (in the input map n).
const int last_N_idx = n_idx + image_size; // last index for the starting position to compute the sum through each channel for this pixel
// To prevent us from a deadlock, we have to always execute __syncthreads();
// for all the threads in the block. Each thread has to do the same number of
// iterations for any loop. To ensure that, we keep all threads running,
// even though, some of them are really idle. We keep the loop running to
// the multiple of the block size that is greater than the number of values
// in the input map in total: C*H*W - this is a number of complex cells in the
// input map.
const int num_blocks = (nr_values + block_size - 1) / block_size;
const int last_block_idx = n_idx + num_blocks * block_size * I;
// index in the filter
int F_idx = f_idx + start_idx;
// index in the output, we compute cells on a flat plane (no channels)
int base_O_idx = no_idx + fo_idx;
int run_O_idx = (start_idx % channel_size);
int thread_cidx = thread_nr * I;
printf("N_idx:%d, last_block_idx:%d, last_N_idx:%d\n", N_idx, last_block_idx, last_N_idx);
while (N_idx < last_block_idx) {
// Zero out caches.
cache[thread_cidx] = 0;
cache[thread_cidx + 1] = 0;
if (N_idx < last_N_idx - 1) {
scalar_t out_re = 0;
scalar_t out_im = 0;
scalar_t x_re = x[N_idx];
scalar_t x_im = x[N_idx + 1];
scalar_t y_re = y[F_idx];
scalar_t y_im = y[F_idx + 1];
single_mul(x_re, x_im, y_re, y_im, &out_re, &out_im);
cache[thread_cidx] = out_re;
cache[thread_cidx + 1] = out_im;
}
__syncthreads(); // Make the results visible to all threads.
// It is not O(logN) but O(N) as of now. For each element in the output
// map we have a dedicated thread. The thread goes through all the
// channels present in the cache.
if (thread_nr < plane_size) {
for (int cache_index = thread_nr + plane_size;
cache_index < block_size;
cache_index += plane_size) {
cache[thread_cidx] += cache[cache_index*I];
cache[thread_cidx + 1] += cache[cache_index*I + 1];
}
// Move the summed values (across the channels) for each pixel to
// the output.
const int O_idx = base_O_idx + run_O_idx;
out[O_idx] += cache[thread_cidx];
out[O_idx + 1] = cache[thread_cidx + 1];
}
N_idx += stride;
F_idx += stride;
run_O_idx = (run_O_idx + stride) % channel_size;
// Make sure that all cache cells are zeroed out before moving on.
// We need this as in the second part we access cache cells that do not
// belong only to this thread.
__syncthreads();
}
}
} // namespace
//void complex_mul_stride_no_permute_cuda(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// AT_DISPATCH_FLOATING_TYPES(x.type(), "complex_mul_cuda",
// ([&] {
// complex_mul_cuda_kernel<scalar_t><<<blocks, threads>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
// }));
//}
//template <typename scalar_t>
//void complex_mul_stride_no_permute_cuda_pure(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// // Run kernel on the GPU
// complex_mul_cuda_kernel<scalar_t><<<blocks, 1024>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
//}
/**
Uncomment the pytorch related stuff.
Compile:
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvcc complex_mul_kernel_stride_no_permute.cu -o complex_mul_profile.out
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvprof ./complex_mul_profile.out
nvidia
/usr/local/cuda/bin/nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m -c complex_mul_kernel.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m complex_mul_kernel_stride_no_permute.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
Segmentation fault
*/
int main(void)
{
int N = 1;
int F = 1;
int C = 4;
int H = 3;
int W = 2;
int I = 2;
int size_input = N * C * H * W * I;
int size_filter = F * C * H * W * I;
int size_output = N * F * H * W * I;
int cuda_block_threads = 16;
// auto dims = {128, 32, 16, 8, 2};
// at::Tensor x = at::randn({128, 32, 16, 8, 2});
// at::Tensor y = at::randn({128, 32, 16, 8, 2});
// at::Tensor out = at::zeros({128, 32, 16, 8, 2});
float *x, *y, * out;
// Allocate unified memory - accessible from cpu or gpu
cudaMallocManaged(&x, size_input*sizeof(float));
cudaMallocManaged(&y, size_filter*sizeof(float));
cudaMallocManaged(&out, size_output*sizeof(float));
for (int j=0; j<H; ++j) {
for (int i=0; i<W; ++i) {
x[(j*W+i)*2] = 3;
x[(j*W+i)*2 + 1] = 1;
y[(j*W+i)*2] = 4;
y[(j*W+i)*2 + 1] = 2;
}
}
for (int i=0; i<H*W*2; i+=2) {
printf("%p %d: %f, %f, %f, %f\n", x, i, x[i], x[i+1], y[i], y[i+1]);
}
// float *dz; // device z
// cudaMalloc(&dz, 9*sizeof(float));
// cudaMemcpy(dz, hz, 9*sizeof(float), cudaMemcpyHostToDevice);
const dim3 blocks(N, F);
complex_mul_cuda_kernel<float><<<blocks, cuda_block_threads,
cuda_block_threads*2>>>(x, y, out, N, F, C, H, W);
for (int i=0; i<H*W*C; i+=2) {
printf("%d: %f, %f\n", i, out[i], out[i+1]);
}
cudaFree(x);
cudaFree(y);
cudaFree(out);
// cudaFree(dz);
printf("finished computation\n");
return 0;
} | code for sm_80
Function : _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R6, c[0x0][0x0] ; /* 0x0000000000067a13 */
/* 0x000fe20000000000 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*0040*/ S2UR UR36, SR_CTAID.X ; /* 0x00000000002479c3 */
/* 0x000e220000002500 */
/*0050*/ I2F.RP R3, R6 ; /* 0x0000000600037306 */
/* 0x000e620000209400 */
/*0060*/ IMAD R2, R2, c[0x0][0x184], RZ ; /* 0x0000610002027a24 */
/* 0x000fe200078e02ff */
/*0070*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000ea20000002100 */
/*0080*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe40007ffe0ff */
/*0090*/ IMAD R0, R2.reuse, c[0x0][0x180], R7 ; /* 0x0000600002007a24 */
/* 0x040fe400078e0207 */
/*00a0*/ IMAD.SHL.U32 R18, R2, 0x2, RZ ; /* 0x0000000202127824 */
/* 0x000fc600078e00ff */
/*00b0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD R22, R18, c[0x0][0x180], RZ ; /* 0x0000600012167a24 */
/* 0x000fc600078e02ff */
/*00d0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f46270 */
/*00e0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x002e620000001000 */
/*00f0*/ IMAD R16, R22, UR36, RZ ; /* 0x0000002416107c24 */
/* 0x001fe4000f8e02ff */
/*0100*/ IMAD.SHL.U32 R25, R19, 0x2, RZ ; /* 0x0000000213197824 */
/* 0x004fc600078e00ff */
/*0110*/ IADD3 R24, R22, R16, RZ ; /* 0x0000001016187210 */
/* 0x000fe40007ffe0ff */
/*0120*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x002fc60007ffe0ff */
/*0130*/ STL [R1+0x8], R24 ; /* 0x0000081801007387 */
/* 0x0001e20000100800 */
/*0140*/ IABS R3, R0 ; /* 0x0000000000037213 */
/* 0x000fe20000000000 */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0002a4000021f000 */
/*0160*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x002fe200000001ff */
/*0170*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x004fc800078e0a05 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*0190*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fc60000000f00 */
/*01a0*/ IMAD R7, R7, R6, RZ ; /* 0x0000000607077224 */
/* 0x000fc600078e02ff */
/*01b0*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*01c0*/ IMAD.HI.U32 R4, R5, R7, R4 ; /* 0x0000000705047227 */
/* 0x000fe200078e0004 */
/*01d0*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fca0000000f00 */
/*01e0*/ IMAD.HI.U32 R4, R4, R3, RZ ; /* 0x0000000304047227 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a04 */
/*0200*/ IMAD R3, R6, R4, R3 ; /* 0x0000000406037224 */
/* 0x000fe400078e0203 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fc600078e00ff */
/*0220*/ ISETP.GT.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f04070 */
/*0230*/ @!P0 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103038824 */
/* 0x000fe200078e0a06 */
/*0240*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fc80003f05270 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*0260*/ @!P1 IADD3 R3, R3, -R6, RZ ; /* 0x8000000603039210 */
/* 0x000fca0007ffe0ff */
/*0270*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*0280*/ @!P0 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff038a12 */
/* 0x000fe400078e33ff */
/*0290*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*02a0*/ IADD3 R17, R0, -R3, RZ ; /* 0x8000000300117210 */
/* 0x000fc60007ffe0ff */
/*02b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*02c0*/ IMAD R17, R17, 0x2, R16 ; /* 0x0000000211117824 */
/* 0x000fe200078e0210 */
/*02d0*/ IADD3 R16, R16, R25, RZ ; /* 0x0000001910107210 */
/* 0x000fca0007ffe0ff */
/*02e0*/ STL.64 [R1], R16 ; /* 0x0000001001007387 */
/* 0x0001e40000100a00 */
/*02f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe20000000000 */
/*0300*/ MOV R3, 0x370 ; /* 0x0000037000037802 */
/* 0x000fe40000000f00 */
/*0310*/ MOV R20, 0x2f0 ; /* 0x000002f000147802 */
/* 0x000fe40000000f00 */
/*0320*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0330*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0340*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0350*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0360*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*0370*/ ISETP.GE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fda0003f06270 */
/*0380*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0390*/ I2F.U32.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209000 */
/*03a0*/ IADD3 R7, RZ, -R2, RZ ; /* 0x80000002ff077210 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD.IADD R3, R2.reuse, 0x1, R19 ; /* 0x0000000102037824 */
/* 0x040fe200078e0213 */
/*03c0*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e620000002600 */
/*03d0*/ ISETP.NE.U32.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f45070 */
/*03e0*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*03f0*/ IADD3 R23, R24, -0x1, RZ ; /* 0xffffffff18177810 */
/* 0x000fe40007ffe0ff */
/*0400*/ LOP3.LUT R0, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff007212 */
/* 0x000fe200078e33ff */
/*0410*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e220000001000 */
/*0420*/ UIMAD UR4, UR36, UR4, UR5 ; /* 0x00000004240472a4 */
/* 0x002fe2000f8e0205 */
/*0430*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0440*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0450*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0460*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fd200078e02ff */
/*0470*/ IMAD.HI.U32 R8, R5, R7, R4 ; /* 0x0000000705087227 */
/* 0x000fe200078e0004 */
/*0480*/ IADD3 R5, R0, c[0x0][0x0], RZ ; /* 0x0000000000057a10 */
/* 0x000fe40007ffe0ff */
/*0490*/ SHF.L.U32 R7, R25, 0x2, RZ ; /* 0x0000000219077819 */
/* 0x000fe200000006ff */
/*04a0*/ IMAD R4, R22, UR5, R25 ; /* 0x0000000516047c24 */
/* 0x000fe4000f8e0219 */
/*04b0*/ IMAD.HI.U32 R0, R8, R5, RZ ; /* 0x0000000508007227 */
/* 0x000fc800078e00ff */
/*04c0*/ IMAD.MOV R6, RZ, RZ, -R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0a00 */
/*04d0*/ IMAD R22, R18, UR4, RZ ; /* 0x0000000412167c24 */
/* 0x000fe4000f8e02ff */
/*04e0*/ IMAD R5, R2, R6, R5 ; /* 0x0000000602057224 */
/* 0x000fca00078e0205 */
/*04f0*/ ISETP.GE.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f06070 */
/*0500*/ @P0 IADD3 R5, -R2, R5, RZ ; /* 0x0000000502050210 */
/* 0x000fe40007ffe1ff */
/*0510*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe40007ffe0ff */
/*0520*/ ISETP.GE.U32.AND P1, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe20003f26070 */
/*0530*/ IMAD.IADD R5, R2, 0x1, R3 ; /* 0x0000000102057824 */
/* 0x000fc800078e0203 */
/*0540*/ IMAD.IADD R9, R2, 0x1, R5 ; /* 0x0000000102097824 */
/* 0x000fca00078e0205 */
/*0550*/ IADD3 R6, R2, R9, RZ ; /* 0x0000000902067210 */
/* 0x000fc60007ffe0ff */
/*0560*/ @P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100001810 */
/* 0x000fe40007ffe0ff */
/*0570*/ @!P2 LOP3.LUT R0, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff00a212 */
/* 0x000fc800078e33ff */
/*0580*/ IADD3 R8, R0, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x000fc80007ffe0ff */
/*0590*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*05a0*/ ISETP.GE.AND P1, PT, R16, R23, PT ; /* 0x000000171000720c */
/* 0x000fe20003f26270 */
/*05b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*05c0*/ @!P1 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d9424 */
/* 0x000fc800078e00ff */
/*05d0*/ @!P1 IMAD.WIDE R10, R4, R13, c[0x0][0x168] ; /* 0x00005a00040a9625 */
/* 0x000fc800078e020d */
/*05e0*/ @!P1 IMAD.WIDE R12, R16, R13, c[0x0][0x160] ; /* 0x00005800100c9625 */
/* 0x000fe200078e020d */
/*05f0*/ @!P1 LDG.E.CONSTANT R20, [R10.64+0x4] ; /* 0x000004040a149981 */
/* 0x0000a8000c1e9900 */
/*0600*/ @!P1 LDG.E.CONSTANT R21, [R10.64] ; /* 0x000000040a159981 */
/* 0x0000a8000c1e9900 */
/*0610*/ @!P1 LDG.E.CONSTANT R26, [R12.64] ; /* 0x000000040c1a9981 */
/* 0x0002e8000c1e9900 */
/*0620*/ @!P1 LDG.E.CONSTANT R27, [R12.64+0x4] ; /* 0x000004040c1b9981 */
/* 0x000322000c1e9900 */
/*0630*/ IABS R24, R18 ; /* 0x0000001200187213 */
/* 0x000fe20000000000 */
/*0640*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0650*/ IABS R10, R25 ; /* 0x00000019000a7213 */
/* 0x001fe20000000000 */
/*0660*/ BSSY B0, 0xce0 ; /* 0x0000067000007945 */
/* 0x000fe20003800000 */
/*0670*/ I2F.RP R28, R24 ; /* 0x00000018001c7306 */
/* 0x000e220000209400 */
/*0680*/ ISETP.GE.AND P2, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fce0003f46270 */
/*0690*/ MUFU.RCP R28, R28 ; /* 0x0000001c001c7308 */
/* 0x001e240000001000 */
/*06a0*/ IADD3 R14, R28, 0xffffffe, RZ ; /* 0x0ffffffe1c0e7810 */
/* 0x001fcc0007ffe0ff */
/*06b0*/ F2I.FTZ.U32.TRUNC.NTZ R15, R14 ; /* 0x0000000e000f7305 */
/* 0x000164000021f000 */
/*06c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x001fe200078e00ff */
/*06d0*/ IADD3 R29, RZ, -R15, RZ ; /* 0x8000000fff1d7210 */
/* 0x020fca0007ffe0ff */
/*06e0*/ IMAD R11, R29, R24, RZ ; /* 0x000000181d0b7224 */
/* 0x000fc800078e02ff */
/*06f0*/ IMAD.HI.U32 R15, R15, R11, R14 ; /* 0x0000000b0f0f7227 */
/* 0x000fe200078e000e */
/*0700*/ IABS R11, R18 ; /* 0x00000012000b7213 */
/* 0x000fc80000000000 */
/*0710*/ IADD3 R13, RZ, -R11, RZ ; /* 0x8000000bff0d7210 */
/* 0x002fe20007ffe0ff */
/*0720*/ IMAD.HI.U32 R15, R15, R10, RZ ; /* 0x0000000a0f0f7227 */
/* 0x000fc800078e00ff */
/*0730*/ IMAD R13, R15, R13, R10 ; /* 0x0000000d0f0d7224 */
/* 0x000fca00078e020a */
/*0740*/ ISETP.GT.U32.AND P0, PT, R24, R13, PT ; /* 0x0000000d1800720c */
/* 0x000fda0003f04070 */
/*0750*/ @!P0 IMAD.IADD R13, R13, 0x1, -R24 ; /* 0x000000010d0d8824 */
/* 0x000fca00078e0a18 */
/*0760*/ ISETP.GT.U32.AND P0, PT, R24, R13, PT ; /* 0x0000000d1800720c */
/* 0x000fda0003f04070 */
/*0770*/ @!P0 IADD3 R13, R13, -R24, RZ ; /* 0x800000180d0d8210 */
/* 0x000fe40007ffe0ff */
/*0780*/ ISETP.GE.AND P0, PT, R19, R2, PT ; /* 0x000000021300720c */
/* 0x000fc60003f06270 */
/*0790*/ IMAD.MOV.U32 R25, RZ, RZ, R13 ; /* 0x000000ffff197224 */
/* 0x000fca00078e000d */
/*07a0*/ @!P2 IADD3 R25, -R25, RZ, RZ ; /* 0x000000ff1919a210 */
/* 0x000fe20007ffe1ff */
/*07b0*/ @!P1 FADD R11, R20, R21 ; /* 0x00000015140b9221 */
/* 0x004fc80000000000 */
/*07c0*/ @!P1 FMUL R12, R11, R26 ; /* 0x0000001a0b0c9220 */
/* 0x008fe40000400000 */
/*07d0*/ @!P1 FADD R10, -R26.reuse, R27.reuse ; /* 0x0000001b1a0a9221 */
/* 0x150fe40000000100 */
/*07e0*/ @!P1 FADD R27, R26, R27 ; /* 0x0000001b1a1b9221 */
/* 0x000fe40000000000 */
/*07f0*/ @!P1 FFMA R21, R21, R10, R12.reuse ; /* 0x0000000a15159223 */
/* 0x100fe4000000000c */
/*0800*/ @!P1 FFMA R27, R20, -R27, R12 ; /* 0x8000001b141b9223 */
/* 0x000fe2000000000c */
/*0810*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe4000001ff00 */
/*0820*/ @!P1 FADD R11, RZ, R21 ; /* 0x00000015ff0b9221 */
/* 0x000fc40000000000 */
/*0830*/ @!P1 FADD R10, RZ, R27 ; /* 0x0000001bff0a9221 */
/* 0x000fe20000000000 */
/*0840*/ ISETP.NE.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc80003f25270 */
/*0850*/ STS.64 [R7], R10 ; /* 0x0000000a07007388 */
/* 0x0001f20000000a00 */
/*0860*/ @!P1 LOP3.LUT R25, RZ, R18, RZ, 0x33, !PT ; /* 0x00000012ff199212 */
/* 0x000fe200078e33ff */
/*0870*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0880*/ @P0 BRA 0xcd0 ; /* 0x0000044000000947 */
/* 0x000fea0003800000 */
/*0890*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x0], PT ; /* 0x0000000003007a0c */
/* 0x001fe20003f06270 */
/*08a0*/ BSSY B1, 0xc40 ; /* 0x0000039000017945 */
/* 0x000fd80003800000 */
/*08b0*/ @P0 BRA 0xc30 ; /* 0x0000037000000947 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*08d0*/ BSSY B2, 0xa80 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*08e0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*08f0*/ IMAD.MOV.U32 R27, RZ, RZ, R3 ; /* 0x000000ffff1b7224 */
/* 0x000fd400078e0003 */
/*0900*/ @!P1 BRA 0xa70 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0910*/ LEA R15, R2, R7, 0x3 ; /* 0x00000007020f7211 */
/* 0x000fe200078e18ff */
/*0920*/ LDS.64 R10, [R7] ; /* 0x00000000070a7984 */
/* 0x000fe20000000a00 */
/*0930*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f25270 */
/*0940*/ IMAD.MOV.U32 R27, RZ, RZ, R5 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e0005 */
/*0950*/ LDS.64 R12, [R15] ; /* 0x000000000f0c7984 */
/* 0x000e240000000a00 */
/*0960*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x001fe40000000000 */
/*0970*/ FADD R11, R13, R11 ; /* 0x0000000b0d0b7221 */
/* 0x000fca0000000000 */
/*0980*/ STS.64 [R7], R10 ; /* 0x0000000a07007388 */
/* 0x0001e20000000a00 */
/*0990*/ @!P1 BRA 0xa70 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*09a0*/ LEA R15, R2, R15, 0x3 ; /* 0x0000000f020f7211 */
/* 0x000fe400078e18ff */
/*09b0*/ ISETP.NE.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe40003f25270 */
/*09c0*/ MOV R27, R9 ; /* 0x00000009001b7202 */
/* 0x000fe20000000f00 */
/*09d0*/ LDS.64 R12, [R15] ; /* 0x000000000f0c7984 */
/* 0x000e740000000a00 */
/*09e0*/ @P1 IMAD R14, R2, 0x8, R15 ; /* 0x00000008020e1824 */
/* 0x000fc400078e020f */
/*09f0*/ @P1 IMAD.MOV.U32 R27, RZ, RZ, R6 ; /* 0x000000ffff1b1224 */
/* 0x000fe400078e0006 */
/*0a00*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x002fe40000000000 */
/*0a10*/ FADD R13, R11, R13 ; /* 0x0000000d0b0d7221 */
/* 0x000fca0000000000 */
/*0a20*/ STS.64 [R7], R12 ; /* 0x0000000c07007388 */
/* 0x000fe80000000a00 */
/*0a30*/ @P1 LDS.64 R10, [R14] ; /* 0x000000000e0a1984 */
/* 0x001e240000000a00 */
/*0a40*/ @P1 FADD R11, R13, R11 ; /* 0x0000000b0d0b1221 */
/* 0x001fe40000000000 */
/*0a50*/ @P1 FADD R10, R12, R10 ; /* 0x0000000a0c0a1221 */
/* 0x000fca0000000000 */
/*0a60*/ @P1 STS.64 [R7], R10 ; /* 0x0000000a07001388 */
/* 0x0001e40000000a00 */
/*0a70*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a80*/ @!P0 BRA 0xc30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a90*/ LDS.64 R10, [R7] ; /* 0x00000000070a7984 */
/* 0x0010620000000a00 */
/*0aa0*/ SHF.L.U32 R29, R27, 0x3, RZ ; /* 0x000000031b1d7819 */
/* 0x000fca00000006ff */
/*0ab0*/ LDS.64 R12, [R29] ; /* 0x000000001d0c7984 */
/* 0x0004e20000000a00 */
/*0ac0*/ IMAD R24, R2.reuse, 0x8, R29 ; /* 0x0000000802187824 */
/* 0x040fe200078e021d */
/*0ad0*/ IADD3 R27, R2, R27, R2 ; /* 0x0000001b021b7210 */
/* 0x000fc80007ffe002 */
/*0ae0*/ LEA R26, R2.reuse, R24, 0x3 ; /* 0x00000018021a7211 */
/* 0x040fe400078e18ff */
/*0af0*/ IADD3 R27, R2, R27, R2 ; /* 0x0000001b021b7210 */
/* 0x000fc60007ffe002 */
/*0b00*/ IMAD R28, R2, 0x8, R26 ; /* 0x00000008021c7824 */
/* 0x000fe200078e021a */
/*0b10*/ ISETP.GE.AND P0, PT, R27, c[0x0][0x0], PT ; /* 0x000000001b007a0c */
/* 0x000fc80003f06270 */
/*0b20*/ LEA R29, R2, R28, 0x3 ; /* 0x0000001c021d7211 */
/* 0x004fe200078e18ff */
/*0b30*/ FADD R13, R13, R11 ; /* 0x0000000b0d0d7221 */
/* 0x00afe40000000000 */
/*0b40*/ FADD R12, R12, R10 ; /* 0x0000000a0c0c7221 */
/* 0x000fca0000000000 */
/*0b50*/ STS.64 [R7], R12 ; /* 0x0000000c07007388 */
/* 0x000fe80000000a00 */
/*0b60*/ LDS.64 R10, [R24] ; /* 0x00000000180a7984 */
/* 0x000e640000000a00 */
/*0b70*/ FADD R15, R13, R11 ; /* 0x0000000b0d0f7221 */
/* 0x002fe40000000000 */
/*0b80*/ FADD R14, R12, R10 ; /* 0x0000000a0c0e7221 */
/* 0x000fca0000000000 */
/*0b90*/ STS.64 [R7], R14 ; /* 0x0000000e07007388 */
/* 0x000fe80000000a00 */
/*0ba0*/ LDS.64 R10, [R26] ; /* 0x000000001a0a7984 */
/* 0x000e640000000a00 */
/*0bb0*/ FADD R21, R15, R11 ; /* 0x0000000b0f157221 */
/* 0x002fe40000000000 */
/*0bc0*/ FADD R20, R14, R10 ; /* 0x0000000a0e147221 */
/* 0x000fca0000000000 */
/*0bd0*/ STS.64 [R7], R20 ; /* 0x0000001407007388 */
/* 0x000fe80000000a00 */
/*0be0*/ LDS.64 R10, [R28] ; /* 0x000000001c0a7984 */
/* 0x000e640000000a00 */
/*0bf0*/ FADD R10, R20, R10 ; /* 0x0000000a140a7221 */
/* 0x002fe40000000000 */
/*0c00*/ FADD R11, R21, R11 ; /* 0x0000000b150b7221 */
/* 0x000fca0000000000 */
/*0c10*/ STS.64 [R7], R10 ; /* 0x0000000a07007388 */
/* 0x0003e20000000a00 */
/*0c20*/ @!P0 BRA 0xab0 ; /* 0xfffffe8000008947 */
/* 0x000fea000383ffff */
/*0c30*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c40*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0c50*/ IMAD.IADD R12, R22, 0x1, R25 ; /* 0x00000001160c7824 */
/* 0x000fe200078e0219 */
/*0c60*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0c70*/ LDS.64 R10, [R7] ; /* 0x00000000070a7984 */
/* 0x003e2e0000000a00 */
/*0c80*/ IMAD.WIDE R12, R12, R13, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fca00078e020d */
/*0c90*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea8000c1e1900 */
/*0ca0*/ STG.E [R12.64+0x4], R11 ; /* 0x0000040b0c007986 */
/* 0x0011e2000c101904 */
/*0cb0*/ FADD R15, R15, R10 ; /* 0x0000000a0f0f7221 */
/* 0x004fca0000000000 */
/*0cc0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001e4000c101904 */
/*0cd0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0ce0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fe200078e00ff */
/*0cf0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0d00*/ IMAD R4, R11.reuse, 0x2, R4 ; /* 0x000000020b047824 */
/* 0x040fe200078e0204 */
/*0d10*/ LEA R16, R11.reuse, R16, 0x1 ; /* 0x000000100b107211 */
/* 0x040fe400078e08ff */
/*0d20*/ LEA R25, R11, R25, 0x1 ; /* 0x000000190b197211 */
/* 0x000fe400078e08ff */
/*0d30*/ ISETP.GE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fda0003f06270 */
/*0d40*/ @!P0 BRA 0x5a0 ; /* 0xfffff85000008947 */
/* 0x000fea000383ffff */
/*0d50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d60*/ BRA 0xd60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // #include <ATen/ATen.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdio>
#include <cmath>
#include <iostream>
namespace {
template <typename scalar_t>
__device__ __forceinline__ void single_mul(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
scalar_t uavc = x_re * (y_re + y_im);
*out_re += uavc - (x_re + x_im) * y_im;
*out_im += (x_im - x_re) * y_re + uavc;
}
template <typename scalar_t>
__device__ __forceinline__ void single_add(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
*out_re += x_re + y_re;
*out_im += x_im + y_im;
}
/**
Complex multiplication of tensors using shared memory and barrier
synchronization.
Compute the element wise complex multiplication for each thread in the block and
write the result to the shared memory. Then synchronize the threads and in the
log based fashion sum up the results for each output pixel through its channels,
if they are present in the cache. The stride is the number of threads per block
times the I (the two float representation of the complex numbers).
*/
template <typename scalar_t>
__global__ void complex_mul_cuda_kernel(
const scalar_t* __restrict__ x,
const scalar_t* __restrict__ y,
scalar_t* __restrict__ out,
const int N, const int F, const int C, const int H, const int W) {
// The size of the shared memory cache should be twice the number of threads
// per block as we store the real and imaginary part of the result.
extern __shared__ float cache[]; // cache for the result of the complex multiplication
const int I = 2; // the last dimension for the complex number
const int plane_size = H * W;
const int channel_size = plane_size * I;
const int image_size = C * channel_size; // size of the image from the batch
// number of complex values in the input that we iterate through
const int nr_values = C * H * W;
const int n = blockIdx.x; // current index of an image/input map in the batch
const int f = blockIdx.y; // current index of a filter from the filter bank
const int block_size = blockDim.x;
const int thread_nr = threadIdx.x;
// stride for the H*W map is equal to the number of threads declared in a block
const int stride = block_size * I; // we need H*W threads per plane, each deals with I numbers
const int n_idx = n * image_size; // start index in the batch for this input map
const int f_idx = f * image_size; // start index in the bank for this filter
// find index for the output
const int no_idx = n * (F * channel_size); // output index for the batch data point
const int fo_idx = f * channel_size; // output index for the filter/channel
// Each H*W plane contains H*W*I elements in depth.
// We linearize it and start from 0, move by #threads*I steps in outer loop.
const int start_idx = threadIdx.x*I;
// index in the input map
int N_idx = n_idx + start_idx; // index across the first channel plane (in the input map n).
const int last_N_idx = n_idx + image_size; // last index for the starting position to compute the sum through each channel for this pixel
// To prevent us from a deadlock, we have to always execute __syncthreads();
// for all the threads in the block. Each thread has to do the same number of
// iterations for any loop. To ensure that, we keep all threads running,
// even though, some of them are really idle. We keep the loop running to
// the multiple of the block size that is greater than the number of values
// in the input map in total: C*H*W - this is a number of complex cells in the
// input map.
const int num_blocks = (nr_values + block_size - 1) / block_size;
const int last_block_idx = n_idx + num_blocks * block_size * I;
// index in the filter
int F_idx = f_idx + start_idx;
// index in the output, we compute cells on a flat plane (no channels)
int base_O_idx = no_idx + fo_idx;
int run_O_idx = (start_idx % channel_size);
int thread_cidx = thread_nr * I;
printf("N_idx:%d, last_block_idx:%d, last_N_idx:%d\n", N_idx, last_block_idx, last_N_idx);
while (N_idx < last_block_idx) {
// Zero out caches.
cache[thread_cidx] = 0;
cache[thread_cidx + 1] = 0;
if (N_idx < last_N_idx - 1) {
scalar_t out_re = 0;
scalar_t out_im = 0;
scalar_t x_re = x[N_idx];
scalar_t x_im = x[N_idx + 1];
scalar_t y_re = y[F_idx];
scalar_t y_im = y[F_idx + 1];
single_mul(x_re, x_im, y_re, y_im, &out_re, &out_im);
cache[thread_cidx] = out_re;
cache[thread_cidx + 1] = out_im;
}
__syncthreads(); // Make the results visible to all threads.
// It is not O(logN) but O(N) as of now. For each element in the output
// map we have a dedicated thread. The thread goes through all the
// channels present in the cache.
if (thread_nr < plane_size) {
for (int cache_index = thread_nr + plane_size;
cache_index < block_size;
cache_index += plane_size) {
cache[thread_cidx] += cache[cache_index*I];
cache[thread_cidx + 1] += cache[cache_index*I + 1];
}
// Move the summed values (across the channels) for each pixel to
// the output.
const int O_idx = base_O_idx + run_O_idx;
out[O_idx] += cache[thread_cidx];
out[O_idx + 1] = cache[thread_cidx + 1];
}
N_idx += stride;
F_idx += stride;
run_O_idx = (run_O_idx + stride) % channel_size;
// Make sure that all cache cells are zeroed out before moving on.
// We need this as in the second part we access cache cells that do not
// belong only to this thread.
__syncthreads();
}
}
} // namespace
//void complex_mul_stride_no_permute_cuda(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// AT_DISPATCH_FLOATING_TYPES(x.type(), "complex_mul_cuda",
// ([&] {
// complex_mul_cuda_kernel<scalar_t><<<blocks, threads>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
// }));
//}
//template <typename scalar_t>
//void complex_mul_stride_no_permute_cuda_pure(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// // Run kernel on the GPU
// complex_mul_cuda_kernel<scalar_t><<<blocks, 1024>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
//}
/**
Uncomment the pytorch related stuff.
Compile:
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvcc complex_mul_kernel_stride_no_permute.cu -o complex_mul_profile.out
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvprof ./complex_mul_profile.out
nvidia
/usr/local/cuda/bin/nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m -c complex_mul_kernel.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m complex_mul_kernel_stride_no_permute.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
Segmentation fault
*/
int main(void)
{
int N = 1;
int F = 1;
int C = 4;
int H = 3;
int W = 2;
int I = 2;
int size_input = N * C * H * W * I;
int size_filter = F * C * H * W * I;
int size_output = N * F * H * W * I;
int cuda_block_threads = 16;
// auto dims = {128, 32, 16, 8, 2};
// at::Tensor x = at::randn({128, 32, 16, 8, 2});
// at::Tensor y = at::randn({128, 32, 16, 8, 2});
// at::Tensor out = at::zeros({128, 32, 16, 8, 2});
float *x, *y, * out;
// Allocate unified memory - accessible from cpu or gpu
cudaMallocManaged(&x, size_input*sizeof(float));
cudaMallocManaged(&y, size_filter*sizeof(float));
cudaMallocManaged(&out, size_output*sizeof(float));
for (int j=0; j<H; ++j) {
for (int i=0; i<W; ++i) {
x[(j*W+i)*2] = 3;
x[(j*W+i)*2 + 1] = 1;
y[(j*W+i)*2] = 4;
y[(j*W+i)*2 + 1] = 2;
}
}
for (int i=0; i<H*W*2; i+=2) {
printf("%p %d: %f, %f, %f, %f\n", x, i, x[i], x[i+1], y[i], y[i+1]);
}
// float *dz; // device z
// cudaMalloc(&dz, 9*sizeof(float));
// cudaMemcpy(dz, hz, 9*sizeof(float), cudaMemcpyHostToDevice);
const dim3 blocks(N, F);
complex_mul_cuda_kernel<float><<<blocks, cuda_block_threads,
cuda_block_threads*2>>>(x, y, out, N, F, C, H, W);
for (int i=0; i<H*W*C; i+=2) {
printf("%d: %f, %f\n", i, out[i], out[i+1]);
}
cudaFree(x);
cudaFree(y);
cudaFree(out);
// cudaFree(dz);
printf("finished computation\n");
return 0;
} | .file "tmpxft_00187060_00000000-6_complex_mul_shared_mem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii,"axG",@progbits,_ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii,comdat
.weak _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.hidden _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.type _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, @function
_ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii:
.LFB4002:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl %ecx, 4(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 12(%rsp)
movl 208(%rsp), %eax
movl %eax, 16(%rsp)
movl 216(%rsp), %eax
movl %eax, 20(%rsp)
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4002:
.size _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, .-_ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%p %d: %f, %f, %f, %f\n"
.LC5:
.string "%d: %f, %f\n"
.LC6:
.string "finished computation\n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $192, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $192, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $48, %esi
call cudaMallocManaged@PLT
movl $16, %edx
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
jmp .L10
.L21:
addq $16, %rdx
cmpq $64, %rdx
je .L16
.L10:
leaq -16(%rdx), %rax
.L11:
movq 8(%rsp), %rcx
movss %xmm3, (%rcx,%rax)
movq 8(%rsp), %rcx
movss %xmm2, 4(%rcx,%rax)
movq 16(%rsp), %rcx
movss %xmm1, (%rcx,%rax)
movq 16(%rsp), %rcx
movss %xmm0, 4(%rcx,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L11
jmp .L21
.L16:
movl $4, %ebx
movl $0, %ebp
leaq .LC4(%rip), %r12
.L12:
movq 16(%rsp), %rax
movq 8(%rsp), %rdx
pxor %xmm0, %xmm0
cvtss2sd -4(%rdx,%rbx), %xmm0
pxor %xmm3, %xmm3
cvtss2sd (%rax,%rbx), %xmm3
pxor %xmm2, %xmm2
cvtss2sd -4(%rax,%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%rdx,%rbx), %xmm1
movl %ebp, %ecx
movq %r12, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
addl $2, %ebp
addq $8, %rbx
cmpl $12, %ebp
jne .L12
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $32, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $4, %ebp
movl $0, %ebx
leaq .LC5(%rip), %r12
.L14:
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd -4(%rax,%rbp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbp), %xmm1
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addl $2, %ebx
addq $8, %rbp
cmpl $24, %ebx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq $2
.cfi_def_cfa_offset 104
pushq $3
.cfi_def_cfa_offset 112
movl $4, %r9d
movl $1, %r8d
movl $1, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L13
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1077936128
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1082130432
.align 4
.LC3:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // #include <ATen/ATen.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdio>
#include <cmath>
#include <iostream>
namespace {
template <typename scalar_t>
__device__ __forceinline__ void single_mul(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
scalar_t uavc = x_re * (y_re + y_im);
*out_re += uavc - (x_re + x_im) * y_im;
*out_im += (x_im - x_re) * y_re + uavc;
}
template <typename scalar_t>
__device__ __forceinline__ void single_add(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
*out_re += x_re + y_re;
*out_im += x_im + y_im;
}
/**
Complex multiplication of tensors using shared memory and barrier
synchronization.
Compute the element wise complex multiplication for each thread in the block and
write the result to the shared memory. Then synchronize the threads and in the
log based fashion sum up the results for each output pixel through its channels,
if they are present in the cache. The stride is the number of threads per block
times the I (the two float representation of the complex numbers).
*/
template <typename scalar_t>
__global__ void complex_mul_cuda_kernel(
const scalar_t* __restrict__ x,
const scalar_t* __restrict__ y,
scalar_t* __restrict__ out,
const int N, const int F, const int C, const int H, const int W) {
// The size of the shared memory cache should be twice the number of threads
// per block as we store the real and imaginary part of the result.
extern __shared__ float cache[]; // cache for the result of the complex multiplication
const int I = 2; // the last dimension for the complex number
const int plane_size = H * W;
const int channel_size = plane_size * I;
const int image_size = C * channel_size; // size of the image from the batch
// number of complex values in the input that we iterate through
const int nr_values = C * H * W;
const int n = blockIdx.x; // current index of an image/input map in the batch
const int f = blockIdx.y; // current index of a filter from the filter bank
const int block_size = blockDim.x;
const int thread_nr = threadIdx.x;
// stride for the H*W map is equal to the number of threads declared in a block
const int stride = block_size * I; // we need H*W threads per plane, each deals with I numbers
const int n_idx = n * image_size; // start index in the batch for this input map
const int f_idx = f * image_size; // start index in the bank for this filter
// find index for the output
const int no_idx = n * (F * channel_size); // output index for the batch data point
const int fo_idx = f * channel_size; // output index for the filter/channel
// Each H*W plane contains H*W*I elements in depth.
// We linearize it and start from 0, move by #threads*I steps in outer loop.
const int start_idx = threadIdx.x*I;
// index in the input map
int N_idx = n_idx + start_idx; // index across the first channel plane (in the input map n).
const int last_N_idx = n_idx + image_size; // last index for the starting position to compute the sum through each channel for this pixel
// To prevent us from a deadlock, we have to always execute __syncthreads();
// for all the threads in the block. Each thread has to do the same number of
// iterations for any loop. To ensure that, we keep all threads running,
// even though, some of them are really idle. We keep the loop running to
// the multiple of the block size that is greater than the number of values
// in the input map in total: C*H*W - this is a number of complex cells in the
// input map.
const int num_blocks = (nr_values + block_size - 1) / block_size;
const int last_block_idx = n_idx + num_blocks * block_size * I;
// index in the filter
int F_idx = f_idx + start_idx;
// index in the output, we compute cells on a flat plane (no channels)
int base_O_idx = no_idx + fo_idx;
int run_O_idx = (start_idx % channel_size);
int thread_cidx = thread_nr * I;
printf("N_idx:%d, last_block_idx:%d, last_N_idx:%d\n", N_idx, last_block_idx, last_N_idx);
while (N_idx < last_block_idx) {
// Zero out caches.
cache[thread_cidx] = 0;
cache[thread_cidx + 1] = 0;
if (N_idx < last_N_idx - 1) {
scalar_t out_re = 0;
scalar_t out_im = 0;
scalar_t x_re = x[N_idx];
scalar_t x_im = x[N_idx + 1];
scalar_t y_re = y[F_idx];
scalar_t y_im = y[F_idx + 1];
single_mul(x_re, x_im, y_re, y_im, &out_re, &out_im);
cache[thread_cidx] = out_re;
cache[thread_cidx + 1] = out_im;
}
__syncthreads(); // Make the results visible to all threads.
// It is not O(logN) but O(N) as of now. For each element in the output
// map we have a dedicated thread. The thread goes through all the
// channels present in the cache.
if (thread_nr < plane_size) {
for (int cache_index = thread_nr + plane_size;
cache_index < block_size;
cache_index += plane_size) {
cache[thread_cidx] += cache[cache_index*I];
cache[thread_cidx + 1] += cache[cache_index*I + 1];
}
// Move the summed values (across the channels) for each pixel to
// the output.
const int O_idx = base_O_idx + run_O_idx;
out[O_idx] += cache[thread_cidx];
out[O_idx + 1] = cache[thread_cidx + 1];
}
N_idx += stride;
F_idx += stride;
run_O_idx = (run_O_idx + stride) % channel_size;
// Make sure that all cache cells are zeroed out before moving on.
// We need this as in the second part we access cache cells that do not
// belong only to this thread.
__syncthreads();
}
}
} // namespace
//void complex_mul_stride_no_permute_cuda(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// AT_DISPATCH_FLOATING_TYPES(x.type(), "complex_mul_cuda",
// ([&] {
// complex_mul_cuda_kernel<scalar_t><<<blocks, threads>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
// }));
//}
//template <typename scalar_t>
//void complex_mul_stride_no_permute_cuda_pure(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// // Run kernel on the GPU
// complex_mul_cuda_kernel<scalar_t><<<blocks, 1024>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
//}
/**
Uncomment the pytorch related stuff.
Compile:
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvcc complex_mul_kernel_stride_no_permute.cu -o complex_mul_profile.out
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvprof ./complex_mul_profile.out
nvidia
/usr/local/cuda/bin/nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m -c complex_mul_kernel.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m complex_mul_kernel_stride_no_permute.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
Segmentation fault
*/
int main(void)
{
int N = 1;
int F = 1;
int C = 4;
int H = 3;
int W = 2;
int I = 2;
int size_input = N * C * H * W * I;
int size_filter = F * C * H * W * I;
int size_output = N * F * H * W * I;
int cuda_block_threads = 16;
// auto dims = {128, 32, 16, 8, 2};
// at::Tensor x = at::randn({128, 32, 16, 8, 2});
// at::Tensor y = at::randn({128, 32, 16, 8, 2});
// at::Tensor out = at::zeros({128, 32, 16, 8, 2});
float *x, *y, * out;
// Allocate unified memory - accessible from cpu or gpu
cudaMallocManaged(&x, size_input*sizeof(float));
cudaMallocManaged(&y, size_filter*sizeof(float));
cudaMallocManaged(&out, size_output*sizeof(float));
for (int j=0; j<H; ++j) {
for (int i=0; i<W; ++i) {
x[(j*W+i)*2] = 3;
x[(j*W+i)*2 + 1] = 1;
y[(j*W+i)*2] = 4;
y[(j*W+i)*2 + 1] = 2;
}
}
for (int i=0; i<H*W*2; i+=2) {
printf("%p %d: %f, %f, %f, %f\n", x, i, x[i], x[i+1], y[i], y[i+1]);
}
// float *dz; // device z
// cudaMalloc(&dz, 9*sizeof(float));
// cudaMemcpy(dz, hz, 9*sizeof(float), cudaMemcpyHostToDevice);
const dim3 blocks(N, F);
complex_mul_cuda_kernel<float><<<blocks, cuda_block_threads,
cuda_block_threads*2>>>(x, y, out, N, F, C, H, W);
for (int i=0; i<H*W*C; i+=2) {
printf("%d: %f, %f\n", i, out[i], out[i+1]);
}
cudaFree(x);
cudaFree(y);
cudaFree(out);
// cudaFree(dz);
printf("finished computation\n");
return 0;
} | // #include <ATen/ATen.h>
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cmath>
#include <iostream>
namespace {
template <typename scalar_t>
__device__ __forceinline__ void single_mul(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
scalar_t uavc = x_re * (y_re + y_im);
*out_re += uavc - (x_re + x_im) * y_im;
*out_im += (x_im - x_re) * y_re + uavc;
}
template <typename scalar_t>
__device__ __forceinline__ void single_add(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
*out_re += x_re + y_re;
*out_im += x_im + y_im;
}
/**
Complex multiplication of tensors using shared memory and barrier
synchronization.
Compute the element wise complex multiplication for each thread in the block and
write the result to the shared memory. Then synchronize the threads and in the
log based fashion sum up the results for each output pixel through its channels,
if they are present in the cache. The stride is the number of threads per block
times the I (the two float representation of the complex numbers).
*/
template <typename scalar_t>
__global__ void complex_mul_cuda_kernel(
const scalar_t* __restrict__ x,
const scalar_t* __restrict__ y,
scalar_t* __restrict__ out,
const int N, const int F, const int C, const int H, const int W) {
// The size of the shared memory cache should be twice the number of threads
// per block as we store the real and imaginary part of the result.
extern __shared__ float cache[]; // cache for the result of the complex multiplication
const int I = 2; // the last dimension for the complex number
const int plane_size = H * W;
const int channel_size = plane_size * I;
const int image_size = C * channel_size; // size of the image from the batch
// number of complex values in the input that we iterate through
const int nr_values = C * H * W;
const int n = blockIdx.x; // current index of an image/input map in the batch
const int f = blockIdx.y; // current index of a filter from the filter bank
const int block_size = blockDim.x;
const int thread_nr = threadIdx.x;
// stride for the H*W map is equal to the number of threads declared in a block
const int stride = block_size * I; // we need H*W threads per plane, each deals with I numbers
const int n_idx = n * image_size; // start index in the batch for this input map
const int f_idx = f * image_size; // start index in the bank for this filter
// find index for the output
const int no_idx = n * (F * channel_size); // output index for the batch data point
const int fo_idx = f * channel_size; // output index for the filter/channel
// Each H*W plane contains H*W*I elements in depth.
// We linearize it and start from 0, move by #threads*I steps in outer loop.
const int start_idx = threadIdx.x*I;
// index in the input map
int N_idx = n_idx + start_idx; // index across the first channel plane (in the input map n).
const int last_N_idx = n_idx + image_size; // last index for the starting position to compute the sum through each channel for this pixel
// To prevent us from a deadlock, we have to always execute __syncthreads();
// for all the threads in the block. Each thread has to do the same number of
// iterations for any loop. To ensure that, we keep all threads running,
// even though, some of them are really idle. We keep the loop running to
// the multiple of the block size that is greater than the number of values
// in the input map in total: C*H*W - this is a number of complex cells in the
// input map.
const int num_blocks = (nr_values + block_size - 1) / block_size;
const int last_block_idx = n_idx + num_blocks * block_size * I;
// index in the filter
int F_idx = f_idx + start_idx;
// index in the output, we compute cells on a flat plane (no channels)
int base_O_idx = no_idx + fo_idx;
int run_O_idx = (start_idx % channel_size);
int thread_cidx = thread_nr * I;
printf("N_idx:%d, last_block_idx:%d, last_N_idx:%d\n", N_idx, last_block_idx, last_N_idx);
while (N_idx < last_block_idx) {
// Zero out caches.
cache[thread_cidx] = 0;
cache[thread_cidx + 1] = 0;
if (N_idx < last_N_idx - 1) {
scalar_t out_re = 0;
scalar_t out_im = 0;
scalar_t x_re = x[N_idx];
scalar_t x_im = x[N_idx + 1];
scalar_t y_re = y[F_idx];
scalar_t y_im = y[F_idx + 1];
single_mul(x_re, x_im, y_re, y_im, &out_re, &out_im);
cache[thread_cidx] = out_re;
cache[thread_cidx + 1] = out_im;
}
__syncthreads(); // Make the results visible to all threads.
// It is not O(logN) but O(N) as of now. For each element in the output
// map we have a dedicated thread. The thread goes through all the
// channels present in the cache.
if (thread_nr < plane_size) {
for (int cache_index = thread_nr + plane_size;
cache_index < block_size;
cache_index += plane_size) {
cache[thread_cidx] += cache[cache_index*I];
cache[thread_cidx + 1] += cache[cache_index*I + 1];
}
// Move the summed values (across the channels) for each pixel to
// the output.
const int O_idx = base_O_idx + run_O_idx;
out[O_idx] += cache[thread_cidx];
out[O_idx + 1] = cache[thread_cidx + 1];
}
N_idx += stride;
F_idx += stride;
run_O_idx = (run_O_idx + stride) % channel_size;
// Make sure that all cache cells are zeroed out before moving on.
// We need this as in the second part we access cache cells that do not
// belong only to this thread.
__syncthreads();
}
}
} // namespace
//void complex_mul_stride_no_permute_cuda(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// AT_DISPATCH_FLOATING_TYPES(x.type(), "complex_mul_cuda",
// ([&] {
// complex_mul_cuda_kernel<scalar_t><<<blocks, threads>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
// }));
//}
//template <typename scalar_t>
//void complex_mul_stride_no_permute_cuda_pure(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// // Run kernel on the GPU
// complex_mul_cuda_kernel<scalar_t><<<blocks, 1024>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
//}
/**
Uncomment the pytorch related stuff.
Compile:
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvcc complex_mul_kernel_stride_no_permute.cu -o complex_mul_profile.out
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvprof ./complex_mul_profile.out
nvidia
/usr/local/cuda/bin/nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m -c complex_mul_kernel.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m complex_mul_kernel_stride_no_permute.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
Segmentation fault
*/
int main(void)
{
int N = 1;
int F = 1;
int C = 4;
int H = 3;
int W = 2;
int I = 2;
int size_input = N * C * H * W * I;
int size_filter = F * C * H * W * I;
int size_output = N * F * H * W * I;
int cuda_block_threads = 16;
// auto dims = {128, 32, 16, 8, 2};
// at::Tensor x = at::randn({128, 32, 16, 8, 2});
// at::Tensor y = at::randn({128, 32, 16, 8, 2});
// at::Tensor out = at::zeros({128, 32, 16, 8, 2});
float *x, *y, * out;
// Allocate unified memory - accessible from cpu or gpu
hipMallocManaged(&x, size_input*sizeof(float));
hipMallocManaged(&y, size_filter*sizeof(float));
hipMallocManaged(&out, size_output*sizeof(float));
for (int j=0; j<H; ++j) {
for (int i=0; i<W; ++i) {
x[(j*W+i)*2] = 3;
x[(j*W+i)*2 + 1] = 1;
y[(j*W+i)*2] = 4;
y[(j*W+i)*2 + 1] = 2;
}
}
for (int i=0; i<H*W*2; i+=2) {
printf("%p %d: %f, %f, %f, %f\n", x, i, x[i], x[i+1], y[i], y[i+1]);
}
// float *dz; // device z
// cudaMalloc(&dz, 9*sizeof(float));
// cudaMemcpy(dz, hz, 9*sizeof(float), cudaMemcpyHostToDevice);
const dim3 blocks(N, F);
complex_mul_cuda_kernel<float><<<blocks, cuda_block_threads,
cuda_block_threads*2>>>(x, y, out, N, F, C, H, W);
for (int i=0; i<H*W*C; i+=2) {
printf("%d: %f, %f\n", i, out[i], out[i+1]);
}
hipFree(x);
hipFree(y);
hipFree(out);
// cudaFree(dz);
printf("finished computation\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // #include <ATen/ATen.h>
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cmath>
#include <iostream>
namespace {
template <typename scalar_t>
__device__ __forceinline__ void single_mul(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
scalar_t uavc = x_re * (y_re + y_im);
*out_re += uavc - (x_re + x_im) * y_im;
*out_im += (x_im - x_re) * y_re + uavc;
}
template <typename scalar_t>
__device__ __forceinline__ void single_add(
scalar_t x_re,
scalar_t x_im,
scalar_t y_re,
scalar_t y_im,
scalar_t* out_re,
scalar_t* out_im) {
*out_re += x_re + y_re;
*out_im += x_im + y_im;
}
/**
Complex multiplication of tensors using shared memory and barrier
synchronization.
Compute the element wise complex multiplication for each thread in the block and
write the result to the shared memory. Then synchronize the threads and in the
log based fashion sum up the results for each output pixel through its channels,
if they are present in the cache. The stride is the number of threads per block
times the I (the two float representation of the complex numbers).
*/
template <typename scalar_t>
__global__ void complex_mul_cuda_kernel(
const scalar_t* __restrict__ x,
const scalar_t* __restrict__ y,
scalar_t* __restrict__ out,
const int N, const int F, const int C, const int H, const int W) {
// The size of the shared memory cache should be twice the number of threads
// per block as we store the real and imaginary part of the result.
extern __shared__ float cache[]; // cache for the result of the complex multiplication
const int I = 2; // the last dimension for the complex number
const int plane_size = H * W;
const int channel_size = plane_size * I;
const int image_size = C * channel_size; // size of the image from the batch
// number of complex values in the input that we iterate through
const int nr_values = C * H * W;
const int n = blockIdx.x; // current index of an image/input map in the batch
const int f = blockIdx.y; // current index of a filter from the filter bank
const int block_size = blockDim.x;
const int thread_nr = threadIdx.x;
// stride for the H*W map is equal to the number of threads declared in a block
const int stride = block_size * I; // we need H*W threads per plane, each deals with I numbers
const int n_idx = n * image_size; // start index in the batch for this input map
const int f_idx = f * image_size; // start index in the bank for this filter
// find index for the output
const int no_idx = n * (F * channel_size); // output index for the batch data point
const int fo_idx = f * channel_size; // output index for the filter/channel
// Each H*W plane contains H*W*I elements in depth.
// We linearize it and start from 0, move by #threads*I steps in outer loop.
const int start_idx = threadIdx.x*I;
// index in the input map
int N_idx = n_idx + start_idx; // index across the first channel plane (in the input map n).
const int last_N_idx = n_idx + image_size; // last index for the starting position to compute the sum through each channel for this pixel
// To prevent us from a deadlock, we have to always execute __syncthreads();
// for all the threads in the block. Each thread has to do the same number of
// iterations for any loop. To ensure that, we keep all threads running,
// even though, some of them are really idle. We keep the loop running to
// the multiple of the block size that is greater than the number of values
// in the input map in total: C*H*W - this is a number of complex cells in the
// input map.
const int num_blocks = (nr_values + block_size - 1) / block_size;
const int last_block_idx = n_idx + num_blocks * block_size * I;
// index in the filter
int F_idx = f_idx + start_idx;
// index in the output, we compute cells on a flat plane (no channels)
int base_O_idx = no_idx + fo_idx;
int run_O_idx = (start_idx % channel_size);
int thread_cidx = thread_nr * I;
printf("N_idx:%d, last_block_idx:%d, last_N_idx:%d\n", N_idx, last_block_idx, last_N_idx);
while (N_idx < last_block_idx) {
// Zero out caches.
cache[thread_cidx] = 0;
cache[thread_cidx + 1] = 0;
if (N_idx < last_N_idx - 1) {
scalar_t out_re = 0;
scalar_t out_im = 0;
scalar_t x_re = x[N_idx];
scalar_t x_im = x[N_idx + 1];
scalar_t y_re = y[F_idx];
scalar_t y_im = y[F_idx + 1];
single_mul(x_re, x_im, y_re, y_im, &out_re, &out_im);
cache[thread_cidx] = out_re;
cache[thread_cidx + 1] = out_im;
}
__syncthreads(); // Make the results visible to all threads.
// It is not O(logN) but O(N) as of now. For each element in the output
// map we have a dedicated thread. The thread goes through all the
// channels present in the cache.
if (thread_nr < plane_size) {
for (int cache_index = thread_nr + plane_size;
cache_index < block_size;
cache_index += plane_size) {
cache[thread_cidx] += cache[cache_index*I];
cache[thread_cidx + 1] += cache[cache_index*I + 1];
}
// Move the summed values (across the channels) for each pixel to
// the output.
const int O_idx = base_O_idx + run_O_idx;
out[O_idx] += cache[thread_cidx];
out[O_idx + 1] = cache[thread_cidx + 1];
}
N_idx += stride;
F_idx += stride;
run_O_idx = (run_O_idx + stride) % channel_size;
// Make sure that all cache cells are zeroed out before moving on.
// We need this as in the second part we access cache cells that do not
// belong only to this thread.
__syncthreads();
}
}
} // namespace
//void complex_mul_stride_no_permute_cuda(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// AT_DISPATCH_FLOATING_TYPES(x.type(), "complex_mul_cuda",
// ([&] {
// complex_mul_cuda_kernel<scalar_t><<<blocks, threads>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
// }));
//}
//template <typename scalar_t>
//void complex_mul_stride_no_permute_cuda_pure(
// at::Tensor x,
// at::Tensor y,
// at::Tensor out,
// int threads = 1024) {
//
// const auto N = x.size(0); // batch_size
// const auto F = y.size(0); // filter_bank_size
// const auto C = x.size(1); // number of channels
// const auto H = x.size(2); // height of the matrix
// const auto W = x.size(3); // width of the matrix
//
// const auto x_blocks = N;
// const auto y_blocks = F;
// const dim3 blocks(x_blocks, y_blocks);
//
// // Run kernel on the GPU
// complex_mul_cuda_kernel<scalar_t><<<blocks, 1024>>>(
// x.data<scalar_t>(), y.data<scalar_t>(), out.data<scalar_t>(),
// N, F, C, H, W);
//}
/**
Uncomment the pytorch related stuff.
Compile:
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvcc complex_mul_kernel_stride_no_permute.cu -o complex_mul_profile.out
ady@skr-compute1:/tmp/pycharm_project_154/cnns/nnlib/pytorch_cuda/complex_mul_cuda$ nvprof ./complex_mul_profile.out
nvidia
/usr/local/cuda/bin/nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m -c complex_mul_kernel.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
nvcc -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/torch/csrc/api/include -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/TH -I/local/ady/anaconda3/lib/python3.6/site-packages/torch/lib/include/THC -I/usr/local/cuda/include -I/local/ady/anaconda3/include/python3.6m complex_mul_kernel_stride_no_permute.cu -o complex_mul_kernel_stride_no_permute.out -std=c++11
Segmentation fault
*/
int main(void)
{
int N = 1;
int F = 1;
int C = 4;
int H = 3;
int W = 2;
int I = 2;
int size_input = N * C * H * W * I;
int size_filter = F * C * H * W * I;
int size_output = N * F * H * W * I;
int cuda_block_threads = 16;
// auto dims = {128, 32, 16, 8, 2};
// at::Tensor x = at::randn({128, 32, 16, 8, 2});
// at::Tensor y = at::randn({128, 32, 16, 8, 2});
// at::Tensor out = at::zeros({128, 32, 16, 8, 2});
float *x, *y, * out;
// Allocate unified memory - accessible from cpu or gpu
hipMallocManaged(&x, size_input*sizeof(float));
hipMallocManaged(&y, size_filter*sizeof(float));
hipMallocManaged(&out, size_output*sizeof(float));
for (int j=0; j<H; ++j) {
for (int i=0; i<W; ++i) {
x[(j*W+i)*2] = 3;
x[(j*W+i)*2 + 1] = 1;
y[(j*W+i)*2] = 4;
y[(j*W+i)*2 + 1] = 2;
}
}
for (int i=0; i<H*W*2; i+=2) {
printf("%p %d: %f, %f, %f, %f\n", x, i, x[i], x[i+1], y[i], y[i+1]);
}
// float *dz; // device z
// cudaMalloc(&dz, 9*sizeof(float));
// cudaMemcpy(dz, hz, 9*sizeof(float), cudaMemcpyHostToDevice);
const dim3 blocks(N, F);
complex_mul_cuda_kernel<float><<<blocks, cuda_block_threads,
cuda_block_threads*2>>>(x, y, out, N, F, C, H, W);
for (int i=0; i<H*W*C; i+=2) {
printf("%d: %f, %f\n", i, out[i], out[i+1]);
}
hipFree(x);
hipFree(y);
hipFree(out);
// cudaFree(dz);
printf("finished computation\n");
return 0;
} | .text
.file "complex_mul_shared_mem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $192, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $192, %esi
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $48, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
addq $4, %rcx
addq $4, %rax
xorl %edx, %edx
movabsq $4575657222486360064, %rsi # imm = 0x3F80000040400000
movabsq $4611686019509518336, %rdi # imm = 0x4000000040800000
.p2align 4, 0x90
.LBB0_1: # %.preheader71
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %rsi, -4(%rax,%r8,8)
movq %rdi, -4(%rcx,%r8,8)
incq %r8
cmpq $1, %r8
je .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rdx
addq $16, %rcx
addq $16, %rax
cmpq $3, %rdx
jne .LBB0_1
# %bb.4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rsi
movss (%rsi,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rsi,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movq 8(%rsp), %rax
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss 4(%rax,%rbx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movl $.L.str, %edi
movl %ebx, %edx
movb $4, %al
callq printf
leaq 2(%rbx), %rax
cmpq $10, %rbx
movq %rax, %rbx
jb .LBB0_5
# %bb.6:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $32, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_7
# %bb.10:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $1, 52(%rsp)
movl $1, 48(%rsp)
movl $4, 44(%rsp)
movl $3, 40(%rsp)
movl $2, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_7: # %.preheader86
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_8: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rax,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %ebx, %esi
movb $2, %al
callq printf
leaq 2(%rbx), %rax
cmpq $22, %rbx
movq %rax, %rbx
jb .LBB0_8
# %bb.9:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.type _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii,@function
_ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii: # @_ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, .Lfunc_end1-_ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%p %d: %f, %f, %f, %f\n"
.size .L.str, 23
.type _ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii,@object # @_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii:
.quad _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.size _ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d: %f, %f\n"
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii"
.size .L__unnamed_1, 64
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "finished computation"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187060_00000000-6_complex_mul_shared_mem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii,"axG",@progbits,_ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii,comdat
.weak _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.hidden _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.type _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, @function
_ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii:
.LFB4002:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl %ecx, 4(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 12(%rsp)
movl 208(%rsp), %eax
movl %eax, 16(%rsp)
movl 216(%rsp), %eax
movl %eax, 20(%rsp)
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4002:
.size _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, .-_ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "%p %d: %f, %f, %f, %f\n"
.LC5:
.string "%d: %f, %f\n"
.LC6:
.string "finished computation\n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $192, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $192, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $48, %esi
call cudaMallocManaged@PLT
movl $16, %edx
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
jmp .L10
.L21:
addq $16, %rdx
cmpq $64, %rdx
je .L16
.L10:
leaq -16(%rdx), %rax
.L11:
movq 8(%rsp), %rcx
movss %xmm3, (%rcx,%rax)
movq 8(%rsp), %rcx
movss %xmm2, 4(%rcx,%rax)
movq 16(%rsp), %rcx
movss %xmm1, (%rcx,%rax)
movq 16(%rsp), %rcx
movss %xmm0, 4(%rcx,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L11
jmp .L21
.L16:
movl $4, %ebx
movl $0, %ebp
leaq .LC4(%rip), %r12
.L12:
movq 16(%rsp), %rax
movq 8(%rsp), %rdx
pxor %xmm0, %xmm0
cvtss2sd -4(%rdx,%rbx), %xmm0
pxor %xmm3, %xmm3
cvtss2sd (%rax,%rbx), %xmm3
pxor %xmm2, %xmm2
cvtss2sd -4(%rax,%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%rdx,%rbx), %xmm1
movl %ebp, %ecx
movq %r12, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
addl $2, %ebp
addq $8, %rbx
cmpl $12, %ebp
jne .L12
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $32, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $4, %ebp
movl $0, %ebx
leaq .LC5(%rip), %r12
.L14:
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd -4(%rax,%rbp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbp), %xmm1
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addl $2, %ebx
addq $8, %rbp
cmpl $24, %ebx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq $2
.cfi_def_cfa_offset 104
pushq $3
.cfi_def_cfa_offset 112
movl $4, %r9d
movl $1, %r8d
movl $1, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L13
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN54_GLOBAL__N__d33534c5_25_complex_mul_shared_mem_cu_main23complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1077936128
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1082130432
.align 4
.LC3:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "complex_mul_shared_mem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
leaq 16(%rsp), %rdi
movl $192, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $192, %esi
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $48, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
addq $4, %rcx
addq $4, %rax
xorl %edx, %edx
movabsq $4575657222486360064, %rsi # imm = 0x3F80000040400000
movabsq $4611686019509518336, %rdi # imm = 0x4000000040800000
.p2align 4, 0x90
.LBB0_1: # %.preheader71
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %rsi, -4(%rax,%r8,8)
movq %rdi, -4(%rcx,%r8,8)
incq %r8
cmpq $1, %r8
je .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rdx
addq $16, %rcx
addq $16, %rax
cmpq $3, %rdx
jne .LBB0_1
# %bb.4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rsi
movss (%rsi,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rsi,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movq 8(%rsp), %rax
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss 4(%rax,%rbx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movl $.L.str, %edi
movl %ebx, %edx
movb $4, %al
callq printf
leaq 2(%rbx), %rax
cmpq $10, %rbx
movq %rax, %rbx
jb .LBB0_5
# %bb.6:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $32, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_7
# %bb.10:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $1, 52(%rsp)
movl $1, 48(%rsp)
movl $4, 44(%rsp)
movl $3, 40(%rsp)
movl $2, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_7: # %.preheader86
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_8: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rax,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %ebx, %esi
movb $2, %al
callq printf
leaq 2(%rbx), %rax
cmpq $22, %rbx
movq %rax, %rbx
jb .LBB0_8
# %bb.9:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.type _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii,@function
_ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii: # @_ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, .Lfunc_end1-_ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%p %d: %f, %f, %f, %f\n"
.size .L.str, 23
.type _ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii,@object # @_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii:
.quad _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.size _ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d: %f, %f\n"
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii"
.size .L__unnamed_1, 64
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "finished computation"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN12_GLOBAL__N_138__device_stub__complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN12_GLOBAL__N_123complex_mul_cuda_kernelIfEEvPKT_S3_PS1_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct
{
int width;
int height;
float *elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
cudaSetDevice(0);
cudaDeviceSynchronize();
size_t available, total;
cudaMemGetInfo(&available, &total);
// printf("Mem total: %ld Bytes\nMem available: %ld Bytes\n", available, total);
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
// printf("size of A: %ld\n", size);
cudaMalloc(&d_A.elements, size);
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: allocation A %s\n", cudaGetErrorString(error));
exit(-1);
}
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
error = cudaGetLastError();
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: allocation B %s\n", cudaGetErrorString(error));
exit(-1);
}
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
error = cudaGetLastError();
cudaMalloc(&d_C.elements, size);
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: allocation C %s\n", cudaGetErrorString(error));
exit(-1);
}
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaDeviceSynchronize();
error = cudaGetLastError();
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: calculation error %s\n", cudaGetErrorString(error));
exit(-1);
}
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: copying C %s\n", cudaGetErrorString(error));
exit(-1);
}
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int myrand()
{
return rand() / (RAND_MAX / 10);
}
int main()
{ // A x B
srand(0);
Matrix A, B, C;
A.height = 1 * BLOCK_SIZE;
A.width = 1 * BLOCK_SIZE; // hB = wA
B.height = A.width;
B.width = 1 * BLOCK_SIZE;
C.height = A.height; // hC = hA
C.width = B.width; // wC = wB
A.elements = (float *)malloc(A.height * A.width * sizeof(float));
B.elements = (float *)malloc(B.height * B.width * sizeof(float));
C.elements = (float *)malloc(C.height * C.width * sizeof(float));
printf("Content of A: \n");
for (int i = 0; i < A.height; i++)
{
for (int j = 0; j < A.width; j++)
{
A.elements[i * A.height + j] = myrand();
printf("%2d", (int)A.elements[i * A.height + j]);
}
printf("\n");
}
printf("\n\nContent of B: \n");
for (int i = 0; i < B.height; i++)
{
for (int j = 0; j < B.width; j++)
{
B.elements[i * B.height + j] = myrand();
printf("%2d", (int)B.elements[i * B.height + j]);
}
printf("\n");
}
MatMul(A, B, C);
printf("\n\nContent of C: \n");
for (int i = 0; i < C.height; i++)
{
for (int j = 0; j < C.width; j++)
{
printf("%4d", (int)C.elements[i * C.height + j]);
}
printf("\n");
}
return 0;
} | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc10 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xb00 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R6, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fcc00078e0208 */
/*01a0*/ @!P0 BRA 0x960 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x690 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0250*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0270*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*0290*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02a0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02b0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02c0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02d0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*02e0*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*02f0*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0300*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0320*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0340*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0350*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0360*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*0370*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*0390*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03b0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03c0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03d0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*03e0*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*03f0*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0400*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0410*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0420*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0430*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0440*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0450*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0460*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0470*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*0490*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04a0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04c0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04d0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*04e0*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*04f0*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0500*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0520*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0530*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0550*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0570*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*0580*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*0590*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05a0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05b0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05c0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*05e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*05f0*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0600*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0610*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0620*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0630*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0640*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0650*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0660*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*0670*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*0680*/ @P1 BRA 0x1f0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x940 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*06e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*06f0*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0700*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0710*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0740*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0750*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0760*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0770*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*0780*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0810*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0820*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0830*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0840*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0850*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08c0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08d0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08e0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08f0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0900*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0910*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0920*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0930*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0940*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0970*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*0980*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0990*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09a0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09b0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*09e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a10*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ab0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0ac0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0ad0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ae0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IMAD R6, R0, c[0x0][0x160], R2 ; /* 0x0000580000067a24 */
/* 0x000fe400078e0202 */
/*0b40*/ IMAD R2, R2, c[0x0][0x170], R3 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0203 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct
{
int width;
int height;
float *elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
cudaSetDevice(0);
cudaDeviceSynchronize();
size_t available, total;
cudaMemGetInfo(&available, &total);
// printf("Mem total: %ld Bytes\nMem available: %ld Bytes\n", available, total);
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
// printf("size of A: %ld\n", size);
cudaMalloc(&d_A.elements, size);
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: allocation A %s\n", cudaGetErrorString(error));
exit(-1);
}
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
error = cudaGetLastError();
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: allocation B %s\n", cudaGetErrorString(error));
exit(-1);
}
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
error = cudaGetLastError();
cudaMalloc(&d_C.elements, size);
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: allocation C %s\n", cudaGetErrorString(error));
exit(-1);
}
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaDeviceSynchronize();
error = cudaGetLastError();
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: calculation error %s\n", cudaGetErrorString(error));
exit(-1);
}
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: copying C %s\n", cudaGetErrorString(error));
exit(-1);
}
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int myrand()
{
return rand() / (RAND_MAX / 10);
}
int main()
{ // A x B
srand(0);
Matrix A, B, C;
A.height = 1 * BLOCK_SIZE;
A.width = 1 * BLOCK_SIZE; // hB = wA
B.height = A.width;
B.width = 1 * BLOCK_SIZE;
C.height = A.height; // hC = hA
C.width = B.width; // wC = wB
A.elements = (float *)malloc(A.height * A.width * sizeof(float));
B.elements = (float *)malloc(B.height * B.width * sizeof(float));
C.elements = (float *)malloc(C.height * C.width * sizeof(float));
printf("Content of A: \n");
for (int i = 0; i < A.height; i++)
{
for (int j = 0; j < A.width; j++)
{
A.elements[i * A.height + j] = myrand();
printf("%2d", (int)A.elements[i * A.height + j]);
}
printf("\n");
}
printf("\n\nContent of B: \n");
for (int i = 0; i < B.height; i++)
{
for (int j = 0; j < B.width; j++)
{
B.elements[i * B.height + j] = myrand();
printf("%2d", (int)B.elements[i * B.height + j]);
}
printf("\n");
}
MatMul(A, B, C);
printf("\n\nContent of C: \n");
for (int i = 0; i < C.height; i++)
{
for (int j = 0; j < C.width; j++)
{
printf("%4d", (int)C.elements[i * C.height + j]);
}
printf("\n");
}
return 0;
} | .file "tmpxft_001bbc4f_00000000-6_mm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6myrandv
.type _Z6myrandv, @function
_Z6myrandv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
movl %eax, %edx
cltq
imulq $-1610612725, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $27, %eax
sarl $31, %edx
subl %edx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z6myrandv, .-_Z6myrandv
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ERROR: allocation A %s\n"
.LC1:
.string "ERROR: allocation B %s\n"
.LC2:
.string "ERROR: allocation C %s\n"
.LC3:
.string "ERROR: calculation error %s\n"
.text
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %rdx, %r13
movq %rcx, 16(%rsp)
movq %r8, %rbp
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rdi, %r14
sarq $32, %r14
movq %rdx, %r12
sarq $32, %r12
movq %r8, %r15
sarq $32, %r15
movl $0, %edi
call cudaSetDevice@PLT
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdi
call cudaMemGetInfo@PLT
movl %ebx, 80(%rsp)
movl %r14d, 84(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 96(%rsp)
movl %r12d, 100(%rsp)
imull %r13d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 112(%rsp)
movl %r15d, 116(%rsp)
imull %r15d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 120(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %ebx, %ebx
jne .L23
shrl $4, %r13d
movl %r13d, 68(%rsp)
shrl $4, %r14d
movl %r14d, 72(%rsp)
movl $16, 56(%rsp)
movl $16, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L17:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
movl $2, %ecx
movq %rbp, %rdx
movq 120(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
movdqa 80(%rsp), %xmm0
movaps %xmm0, 128(%rsp)
movdqa 96(%rsp), %xmm1
movaps %xmm1, 144(%rsp)
movdqa 112(%rsp), %xmm2
movaps %xmm2, 160(%rsp)
leaq 160(%rsp), %rdx
leaq 144(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L17
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.section .rodata.str1.1
.LC4:
.string "Content of A: \n"
.LC5:
.string "%2d"
.LC6:
.string "\n"
.LC7:
.string "\n\nContent of B: \n"
.LC8:
.string "\n\nContent of C: \n"
.LC9:
.string "%4d"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $0, %edi
call srand@PLT
movl $1024, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %r13
movl $1024, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rbx), %rbp
leaq 1088(%rbx), %r15
leaq .LC5(%rip), %r12
leaq .LC6(%rip), %r14
.L28:
leaq -64(%rbp), %rbx
.L29:
call _Z6myrandv
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
cvttss2sil %xmm0, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r15, %rbp
jne .L28
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%r13), %rbp
leaq 1088(%r13), %r15
leaq .LC5(%rip), %r12
leaq .LC6(%rip), %r14
.L31:
leaq -64(%rbp), %rbx
.L32:
call _Z6myrandv
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
cvttss2sil %xmm0, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L32
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r15, %rbp
jne .L31
movabsq $68719476736, %r8
movq %r8, %rdi
orq $16, %rdi
movq %rdi, %rdx
movq %rdi, %r8
movq 8(%rsp), %rbx
movq %rbx, %r9
movq %r13, %rcx
movq (%rsp), %rsi
call _Z6MatMul6MatrixS_S_
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rbx), %rbp
leaq 1088(%rbx), %r13
leaq .LC9(%rip), %r12
leaq .LC6(%rip), %r14
.L34:
leaq -64(%rbp), %rbx
.L35:
cvttss2sil (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L35
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r13, %rbp
jne .L34
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct
{
int width;
int height;
float *elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
cudaSetDevice(0);
cudaDeviceSynchronize();
size_t available, total;
cudaMemGetInfo(&available, &total);
// printf("Mem total: %ld Bytes\nMem available: %ld Bytes\n", available, total);
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
// printf("size of A: %ld\n", size);
cudaMalloc(&d_A.elements, size);
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: allocation A %s\n", cudaGetErrorString(error));
exit(-1);
}
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
error = cudaGetLastError();
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: allocation B %s\n", cudaGetErrorString(error));
exit(-1);
}
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
error = cudaGetLastError();
cudaMalloc(&d_C.elements, size);
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: allocation C %s\n", cudaGetErrorString(error));
exit(-1);
}
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaDeviceSynchronize();
error = cudaGetLastError();
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: calculation error %s\n", cudaGetErrorString(error));
exit(-1);
}
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
fprintf(stderr, "ERROR: copying C %s\n", cudaGetErrorString(error));
exit(-1);
}
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int myrand()
{
return rand() / (RAND_MAX / 10);
}
int main()
{ // A x B
srand(0);
Matrix A, B, C;
A.height = 1 * BLOCK_SIZE;
A.width = 1 * BLOCK_SIZE; // hB = wA
B.height = A.width;
B.width = 1 * BLOCK_SIZE;
C.height = A.height; // hC = hA
C.width = B.width; // wC = wB
A.elements = (float *)malloc(A.height * A.width * sizeof(float));
B.elements = (float *)malloc(B.height * B.width * sizeof(float));
C.elements = (float *)malloc(C.height * C.width * sizeof(float));
printf("Content of A: \n");
for (int i = 0; i < A.height; i++)
{
for (int j = 0; j < A.width; j++)
{
A.elements[i * A.height + j] = myrand();
printf("%2d", (int)A.elements[i * A.height + j]);
}
printf("\n");
}
printf("\n\nContent of B: \n");
for (int i = 0; i < B.height; i++)
{
for (int j = 0; j < B.width; j++)
{
B.elements[i * B.height + j] = myrand();
printf("%2d", (int)B.elements[i * B.height + j]);
}
printf("\n");
}
MatMul(A, B, C);
printf("\n\nContent of C: \n");
for (int i = 0; i < C.height; i++)
{
for (int j = 0; j < C.width; j++)
{
printf("%4d", (int)C.elements[i * C.height + j]);
}
printf("\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct
{
int width;
int height;
float *elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
hipSetDevice(0);
hipDeviceSynchronize();
size_t available, total;
hipMemGetInfo(&available, &total);
// printf("Mem total: %ld Bytes\nMem available: %ld Bytes\n", available, total);
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
// printf("size of A: %ld\n", size);
hipMalloc(&d_A.elements, size);
hipError_t error = hipGetLastError();
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: allocation A %s\n", hipGetErrorString(error));
exit(-1);
}
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
error = hipGetLastError();
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: allocation B %s\n", hipGetErrorString(error));
exit(-1);
}
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
error = hipGetLastError();
hipMalloc(&d_C.elements, size);
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: allocation C %s\n", hipGetErrorString(error));
exit(-1);
}
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipDeviceSynchronize();
error = hipGetLastError();
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: calculation error %s\n", hipGetErrorString(error));
exit(-1);
}
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: copying C %s\n", hipGetErrorString(error));
exit(-1);
}
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int myrand()
{
return rand() / (RAND_MAX / 10);
}
int main()
{ // A x B
srand(0);
Matrix A, B, C;
A.height = 1 * BLOCK_SIZE;
A.width = 1 * BLOCK_SIZE; // hB = wA
B.height = A.width;
B.width = 1 * BLOCK_SIZE;
C.height = A.height; // hC = hA
C.width = B.width; // wC = wB
A.elements = (float *)malloc(A.height * A.width * sizeof(float));
B.elements = (float *)malloc(B.height * B.width * sizeof(float));
C.elements = (float *)malloc(C.height * C.width * sizeof(float));
printf("Content of A: \n");
for (int i = 0; i < A.height; i++)
{
for (int j = 0; j < A.width; j++)
{
A.elements[i * A.height + j] = myrand();
printf("%2d", (int)A.elements[i * A.height + j]);
}
printf("\n");
}
printf("\n\nContent of B: \n");
for (int i = 0; i < B.height; i++)
{
for (int j = 0; j < B.width; j++)
{
B.elements[i * B.height + j] = myrand();
printf("%2d", (int)B.elements[i * B.height + j]);
}
printf("\n");
}
MatMul(A, B, C);
printf("\n\nContent of C: \n");
for (int i = 0; i < C.height; i++)
{
for (int j = 0; j < C.width; j++)
{
printf("%4d", (int)C.elements[i * C.height + j]);
}
printf("\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct
{
int width;
int height;
float *elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
hipSetDevice(0);
hipDeviceSynchronize();
size_t available, total;
hipMemGetInfo(&available, &total);
// printf("Mem total: %ld Bytes\nMem available: %ld Bytes\n", available, total);
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
// printf("size of A: %ld\n", size);
hipMalloc(&d_A.elements, size);
hipError_t error = hipGetLastError();
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: allocation A %s\n", hipGetErrorString(error));
exit(-1);
}
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
error = hipGetLastError();
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: allocation B %s\n", hipGetErrorString(error));
exit(-1);
}
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
error = hipGetLastError();
hipMalloc(&d_C.elements, size);
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: allocation C %s\n", hipGetErrorString(error));
exit(-1);
}
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipDeviceSynchronize();
error = hipGetLastError();
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: calculation error %s\n", hipGetErrorString(error));
exit(-1);
}
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: copying C %s\n", hipGetErrorString(error));
exit(-1);
}
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int myrand()
{
return rand() / (RAND_MAX / 10);
}
int main()
{ // A x B
srand(0);
Matrix A, B, C;
A.height = 1 * BLOCK_SIZE;
A.width = 1 * BLOCK_SIZE; // hB = wA
B.height = A.width;
B.width = 1 * BLOCK_SIZE;
C.height = A.height; // hC = hA
C.width = B.width; // wC = wB
A.elements = (float *)malloc(A.height * A.width * sizeof(float));
B.elements = (float *)malloc(B.height * B.width * sizeof(float));
C.elements = (float *)malloc(C.height * C.width * sizeof(float));
printf("Content of A: \n");
for (int i = 0; i < A.height; i++)
{
for (int j = 0; j < A.width; j++)
{
A.elements[i * A.height + j] = myrand();
printf("%2d", (int)A.elements[i * A.height + j]);
}
printf("\n");
}
printf("\n\nContent of B: \n");
for (int i = 0; i < B.height; i++)
{
for (int j = 0; j < B.width; j++)
{
B.elements[i * B.height + j] = myrand();
printf("%2d", (int)B.elements[i * B.height + j]);
}
printf("\n");
}
MatMul(A, B, C);
printf("\n\nContent of C: \n");
for (int i = 0; i < C.height; i++)
{
for (int j = 0; j < C.width; j++)
{
printf("%4d", (int)C.elements[i * C.height + j]);
}
printf("\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s6, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[8:9], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x18
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s6, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct
{
int width;
int height;
float *elements;
} Matrix;
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
hipSetDevice(0);
hipDeviceSynchronize();
size_t available, total;
hipMemGetInfo(&available, &total);
// printf("Mem total: %ld Bytes\nMem available: %ld Bytes\n", available, total);
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
// printf("size of A: %ld\n", size);
hipMalloc(&d_A.elements, size);
hipError_t error = hipGetLastError();
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: allocation A %s\n", hipGetErrorString(error));
exit(-1);
}
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
error = hipGetLastError();
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: allocation B %s\n", hipGetErrorString(error));
exit(-1);
}
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
error = hipGetLastError();
hipMalloc(&d_C.elements, size);
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: allocation C %s\n", hipGetErrorString(error));
exit(-1);
}
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipDeviceSynchronize();
error = hipGetLastError();
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: calculation error %s\n", hipGetErrorString(error));
exit(-1);
}
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
fprintf(stderr, "ERROR: copying C %s\n", hipGetErrorString(error));
exit(-1);
}
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int myrand()
{
return rand() / (RAND_MAX / 10);
}
int main()
{ // A x B
srand(0);
Matrix A, B, C;
A.height = 1 * BLOCK_SIZE;
A.width = 1 * BLOCK_SIZE; // hB = wA
B.height = A.width;
B.width = 1 * BLOCK_SIZE;
C.height = A.height; // hC = hA
C.width = B.width; // wC = wB
A.elements = (float *)malloc(A.height * A.width * sizeof(float));
B.elements = (float *)malloc(B.height * B.width * sizeof(float));
C.elements = (float *)malloc(C.height * C.width * sizeof(float));
printf("Content of A: \n");
for (int i = 0; i < A.height; i++)
{
for (int j = 0; j < A.width; j++)
{
A.elements[i * A.height + j] = myrand();
printf("%2d", (int)A.elements[i * A.height + j]);
}
printf("\n");
}
printf("\n\nContent of B: \n");
for (int i = 0; i < B.height; i++)
{
for (int j = 0; j < B.width; j++)
{
B.elements[i * B.height + j] = myrand();
printf("%2d", (int)B.elements[i * B.height + j]);
}
printf("\n");
}
MatMul(A, B, C);
printf("\n\nContent of C: \n");
for (int i = 0; i < C.height; i++)
{
for (int j = 0; j < C.width; j++)
{
printf("%4d", (int)C.elements[i * C.height + j]);
}
printf("\n");
}
return 0;
} | .text
.file "mm.hip"
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 48(%rsp) # 8-byte Spill
movq %r8, %r12
movq %rcx, 56(%rsp) # 8-byte Spill
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %r15
movq %rdi, %rbx
shrq $32, %rbx
xorl %edi, %edi
callq hipSetDevice
callq hipDeviceSynchronize
leaq 144(%rsp), %rdi
leaq 136(%rsp), %rsi
callq hipMemGetInfo
movq %r15, 32(%rsp)
imull %r15d, %ebx
movslq %ebx, %rbx
shlq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB0_1
# %bb.4:
movq %r13, %r14
shrq $32, %r14
movq 40(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, 16(%rsp)
imull %r13d, %r14d
movslq %r14d, %rbx
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB0_5
# %bb.6:
movq %r12, %r14
shrq $32, %r14
movq 24(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, (%rsp)
movl %r14d, 4(%rsp)
imull %r12d, %r14d
movslq %r14d, %r12
shlq $2, %r12
callq hipGetLastError
movl %eax, %ebx
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %ebx, %ebx
jne .LBB0_7
# %bb.8:
shrl $4, %r13d
shrq $4, %r15
movabsq $1152921500311879680, %rdi # imm = 0xFFFFFFF00000000
andq %r15, %rdi
orq %r13, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_10
# %bb.9:
movups 32(%rsp), %xmm0
movups 16(%rsp), %xmm1
movups (%rsp), %xmm2
movups %xmm0, 184(%rsp)
movups %xmm1, 168(%rsp)
movups %xmm2, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 112(%rsp)
leaq 168(%rsp), %rax
movq %rax, 120(%rsp)
leaq 152(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_10:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB0_11
# %bb.12:
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB0_2
.LBB0_5:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB0_2
.LBB0_7:
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
jmp .LBB0_3
.LBB0_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
.LBB0_2:
movq %rbx, %rdi
.LBB0_3:
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end0-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6myrandv # -- Begin function _Z6myrandv
.p2align 4, 0x90
.type _Z6myrandv,@function
_Z6myrandv: # @_Z6myrandv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cltq
imulq $-1610612725, %rax, %rcx # imm = 0xA000000B
shrq $32, %rcx
addl %ecx, %eax
movl %eax, %ecx
shrl $31, %ecx
sarl $27, %eax
addl %ecx, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6myrandv, .Lfunc_end2-_Z6myrandv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq srand
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r15
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_1: # %.preheader82
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1610612725, %rax, %rcx # imm = 0xA000000B
shrq $32, %rcx
addl %ecx, %eax
movl %eax, %ecx
shrl $31, %ecx
sarl $27, %eax
addl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbp,4)
cvttss2si %xmm0, %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $16, %rbp
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $64, %r12
cmpq $16, %r13
jne .LBB3_1
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_5: # %.preheader81
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1610612725, %rax, %rcx # imm = 0xA000000B
shrq $32, %rcx
addl %ecx, %eax
movl %eax, %ecx
shrl $31, %ecx
sarl $27, %eax
addl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbp,4)
cvttss2si %xmm0, %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $16, %rbp
jne .LBB3_6
# %bb.7: # in Loop: Header=BB3_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $64, %r12
cmpq $16, %r13
jne .LBB3_5
# %bb.8:
movabsq $68719476752, %rdi # imm = 0x1000000010
movq %r14, %rsi
movq %rdi, %rdx
movq %r15, %rcx
movq %rdi, %r8
movq %rbx, %r9
callq _Z6MatMul6MatrixS_S_
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
cvttss2si (%rbx,%r15,4), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $16, %r15
jne .LBB3_10
# %bb.11: # in Loop: Header=BB3_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $64, %rbx
cmpq $16, %r14
jne .LBB3_9
# %bb.12:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: allocation A %s\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: allocation B %s\n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: allocation C %s\n"
.size .L.str.2, 24
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "ERROR: calculation error %s\n"
.size .L.str.3, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%2d"
.size .L.str.6, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%4d"
.size .L.str.10, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Content of A: "
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nContent of B: "
.size .Lstr.1, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\nContent of C: "
.size .Lstr.2, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc10 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xb00 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R6, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fcc00078e0208 */
/*01a0*/ @!P0 BRA 0x960 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x690 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0250*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0270*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*0290*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02a0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02b0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02c0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02d0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*02e0*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*02f0*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0300*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0320*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0340*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0350*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0360*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*0370*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*0390*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03b0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03c0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03d0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*03e0*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*03f0*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0400*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0410*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0420*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0430*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0440*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0450*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0460*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0470*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*0490*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04a0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04c0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04d0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*04e0*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*04f0*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0500*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0520*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0530*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0550*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0570*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*0580*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*0590*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05a0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05b0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05c0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*05e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*05f0*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0600*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0610*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0620*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0630*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0640*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0650*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0660*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*0670*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*0680*/ @P1 BRA 0x1f0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x940 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*06e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*06f0*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0700*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0710*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0740*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0750*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0760*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0770*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*0780*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0810*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0820*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0830*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0840*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0850*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08c0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08d0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08e0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08f0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0900*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0910*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0920*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0930*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0940*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0970*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*0980*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0990*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09a0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09b0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*09e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a10*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ab0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0ac0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0ad0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ae0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IMAD R6, R0, c[0x0][0x160], R2 ; /* 0x0000580000067a24 */
/* 0x000fe400078e0202 */
/*0b40*/ IMAD R2, R2, c[0x0][0x170], R3 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0203 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s6, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[8:9], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x18
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s6, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bbc4f_00000000-6_mm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6myrandv
.type _Z6myrandv, @function
_Z6myrandv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
movl %eax, %edx
cltq
imulq $-1610612725, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $27, %eax
sarl $31, %edx
subl %edx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z6myrandv, .-_Z6myrandv
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ERROR: allocation A %s\n"
.LC1:
.string "ERROR: allocation B %s\n"
.LC2:
.string "ERROR: allocation C %s\n"
.LC3:
.string "ERROR: calculation error %s\n"
.text
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %rdx, %r13
movq %rcx, 16(%rsp)
movq %r8, %rbp
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rdi, %r14
sarq $32, %r14
movq %rdx, %r12
sarq $32, %r12
movq %r8, %r15
sarq $32, %r15
movl $0, %edi
call cudaSetDevice@PLT
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdi
call cudaMemGetInfo@PLT
movl %ebx, 80(%rsp)
movl %r14d, 84(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 96(%rsp)
movl %r12d, 100(%rsp)
imull %r13d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 112(%rsp)
movl %r15d, 116(%rsp)
imull %r15d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 120(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %ebx, %ebx
jne .L23
shrl $4, %r13d
movl %r13d, 68(%rsp)
shrl $4, %r14d
movl %r14d, 72(%rsp)
movl $16, 56(%rsp)
movl $16, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L17:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
movl $2, %ecx
movq %rbp, %rdx
movq 120(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
movdqa 80(%rsp), %xmm0
movaps %xmm0, 128(%rsp)
movdqa 96(%rsp), %xmm1
movaps %xmm1, 144(%rsp)
movdqa 112(%rsp), %xmm2
movaps %xmm2, 160(%rsp)
leaq 160(%rsp), %rdx
leaq 144(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L17
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.section .rodata.str1.1
.LC4:
.string "Content of A: \n"
.LC5:
.string "%2d"
.LC6:
.string "\n"
.LC7:
.string "\n\nContent of B: \n"
.LC8:
.string "\n\nContent of C: \n"
.LC9:
.string "%4d"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $0, %edi
call srand@PLT
movl $1024, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %r13
movl $1024, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rbx), %rbp
leaq 1088(%rbx), %r15
leaq .LC5(%rip), %r12
leaq .LC6(%rip), %r14
.L28:
leaq -64(%rbp), %rbx
.L29:
call _Z6myrandv
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
cvttss2sil %xmm0, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r15, %rbp
jne .L28
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%r13), %rbp
leaq 1088(%r13), %r15
leaq .LC5(%rip), %r12
leaq .LC6(%rip), %r14
.L31:
leaq -64(%rbp), %rbx
.L32:
call _Z6myrandv
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
cvttss2sil %xmm0, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L32
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r15, %rbp
jne .L31
movabsq $68719476736, %r8
movq %r8, %rdi
orq $16, %rdi
movq %rdi, %rdx
movq %rdi, %r8
movq 8(%rsp), %rbx
movq %rbx, %r9
movq %r13, %rcx
movq (%rsp), %rsi
call _Z6MatMul6MatrixS_S_
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 64(%rbx), %rbp
leaq 1088(%rbx), %r13
leaq .LC9(%rip), %r12
leaq .LC6(%rip), %r14
.L34:
leaq -64(%rbp), %rbx
.L35:
cvttss2sil (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L35
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $64, %rbp
cmpq %r13, %rbp
jne .L34
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mm.hip"
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 48(%rsp) # 8-byte Spill
movq %r8, %r12
movq %rcx, 56(%rsp) # 8-byte Spill
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %r15
movq %rdi, %rbx
shrq $32, %rbx
xorl %edi, %edi
callq hipSetDevice
callq hipDeviceSynchronize
leaq 144(%rsp), %rdi
leaq 136(%rsp), %rsi
callq hipMemGetInfo
movq %r15, 32(%rsp)
imull %r15d, %ebx
movslq %ebx, %rbx
shlq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB0_1
# %bb.4:
movq %r13, %r14
shrq $32, %r14
movq 40(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, 16(%rsp)
imull %r13d, %r14d
movslq %r14d, %rbx
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB0_5
# %bb.6:
movq %r12, %r14
shrq $32, %r14
movq 24(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, (%rsp)
movl %r14d, 4(%rsp)
imull %r12d, %r14d
movslq %r14d, %r12
shlq $2, %r12
callq hipGetLastError
movl %eax, %ebx
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %ebx, %ebx
jne .LBB0_7
# %bb.8:
shrl $4, %r13d
shrq $4, %r15
movabsq $1152921500311879680, %rdi # imm = 0xFFFFFFF00000000
andq %r15, %rdi
orq %r13, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_10
# %bb.9:
movups 32(%rsp), %xmm0
movups 16(%rsp), %xmm1
movups (%rsp), %xmm2
movups %xmm0, 184(%rsp)
movups %xmm1, 168(%rsp)
movups %xmm2, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 112(%rsp)
leaq 168(%rsp), %rax
movq %rax, 120(%rsp)
leaq 152(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_10:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB0_11
# %bb.12:
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB0_2
.LBB0_5:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB0_2
.LBB0_7:
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r14, %rdi
jmp .LBB0_3
.LBB0_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
.LBB0_2:
movq %rbx, %rdi
.LBB0_3:
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end0-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6myrandv # -- Begin function _Z6myrandv
.p2align 4, 0x90
.type _Z6myrandv,@function
_Z6myrandv: # @_Z6myrandv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cltq
imulq $-1610612725, %rax, %rcx # imm = 0xA000000B
shrq $32, %rcx
addl %ecx, %eax
movl %eax, %ecx
shrl $31, %ecx
sarl $27, %eax
addl %ecx, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6myrandv, .Lfunc_end2-_Z6myrandv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq srand
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r15
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_1: # %.preheader82
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1610612725, %rax, %rcx # imm = 0xA000000B
shrq $32, %rcx
addl %ecx, %eax
movl %eax, %ecx
shrl $31, %ecx
sarl $27, %eax
addl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbp,4)
cvttss2si %xmm0, %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $16, %rbp
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $64, %r12
cmpq $16, %r13
jne .LBB3_1
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_5: # %.preheader81
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1610612725, %rax, %rcx # imm = 0xA000000B
shrq $32, %rcx
addl %ecx, %eax
movl %eax, %ecx
shrl $31, %ecx
sarl $27, %eax
addl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbp,4)
cvttss2si %xmm0, %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $16, %rbp
jne .LBB3_6
# %bb.7: # in Loop: Header=BB3_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $64, %r12
cmpq $16, %r13
jne .LBB3_5
# %bb.8:
movabsq $68719476752, %rdi # imm = 0x1000000010
movq %r14, %rsi
movq %rdi, %rdx
movq %r15, %rcx
movq %rdi, %r8
movq %rbx, %r9
callq _Z6MatMul6MatrixS_S_
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
cvttss2si (%rbx,%r15,4), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $16, %r15
jne .LBB3_10
# %bb.11: # in Loop: Header=BB3_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $64, %rbx
cmpq $16, %r14
jne .LBB3_9
# %bb.12:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: allocation A %s\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: allocation B %s\n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: allocation C %s\n"
.size .L.str.2, 24
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "ERROR: calculation error %s\n"
.size .L.str.3, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%2d"
.size .L.str.6, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%4d"
.size .L.str.10, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Content of A: "
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nContent of B: "
.size .Lstr.1, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\nContent of C: "
.size .Lstr.2, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void fourier_transform(float *in, float *out, int height, int width, int blockConfig) {
// block elements and function variables
int my_x, k, t;
my_x = blockIdx.x * blockDim.x + threadIdx.x;
// iterate through each element, going from frequency to time domain
for (k = 0; k < height; k++) {
// difference, which will be used to subtract off
float realSum = 0.0;
// iterate through the input element
for (t = 0; t < width; t++) {
// calculate the angle and update the sum
float angle = 2 * M_PI * (my_x * height + t) * (my_x * width + k) / height;
realSum += in[my_x * height + t] * cos(angle);
}
// each output element will be the current sum for that index
out[my_x * height + k] = realSum;
}
} | .file "tmpxft_0002886e_00000000-6_fourier_transform.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii
.type _Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii, @function
_Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17fourier_transformPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii, .-_Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii
.globl _Z17fourier_transformPfS_iii
.type _Z17fourier_transformPfS_iii, @function
_Z17fourier_transformPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17fourier_transformPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17fourier_transformPfS_iii, .-_Z17fourier_transformPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17fourier_transformPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17fourier_transformPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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